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1.1 ! root 1: /*++ ! 2: ! 3: Copyright (c) 1992 Microsoft Corporation ! 4: ! 5: Module Name: ! 6: ! 7: cirrus.h ! 8: ! 9: Abstract: ! 10: ! 11: This module contains the definitions for the code that implements the ! 12: Cirrus Logic VGA 6410/6420/542x device driver. ! 13: ! 14: Environment: ! 15: ! 16: Kernel mode ! 17: ! 18: Revision History: ! 19: ! 20: ! 21: --*/ ! 22: ! 23: // ! 24: // Do full save and restore. ! 25: // ! 26: ! 27: #define EXTENDED_REGISTER_SAVE_RESTORE 1 ! 28: ! 29: // ! 30: // Banking ifdefs to enable banking ! 31: // the banking type MUST match the type in clhard.asm ! 32: // ! 33: ! 34: #define ONE_64K_BANK 0 ! 35: #define TWO_32K_BANKS 1 ! 36: #define MULTIPLE_REFRESH_TABLES 0 ! 37: ! 38: // ! 39: // Base address of VGA memory range. Also used as base address of VGA ! 40: // memory when loading a font, which is done with the VGA mapped at A0000. ! 41: // ! 42: ! 43: #define MEM_VGA 0xA0000 ! 44: #define MEM_VGA_SIZE 0x20000 ! 45: ! 46: // ! 47: // Port definitions for filling the ACCSES_RANGES structure in the miniport ! 48: // information, defines the range of I/O ports the VGA spans. ! 49: // There is a break in the IO ports - a few ports are used for the parallel ! 50: // port. Those cannot be defined in the ACCESS_RANGE, but are still mapped ! 51: // so all VGA ports are in one address range. ! 52: // ! 53: ! 54: #define VGA_BASE_IO_PORT 0x000003B0 ! 55: #define VGA_START_BREAK_PORT 0x000003BB ! 56: #define VGA_END_BREAK_PORT 0x000003C0 ! 57: #define VGA_MAX_IO_PORT 0x000003DF ! 58: ! 59: // ! 60: // VGA port-related definitions. ! 61: // ! 62: ! 63: // ! 64: // VGA register definitions ! 65: // ! 66: // ports in monochrome mode ! 67: #define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and ! 68: #define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode ! 69: #define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port ! 70: // in mono mode ! 71: #define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read ! 72: // port in mono mode ! 73: #define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO ! 74: // Register to read to reset ! 75: // Attribute Controller index/data ! 76: #define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and ! 77: #define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port ! 78: // for writes, but only Address is ! 79: // readable at 0x010 ! 80: #define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is ! 81: // readable here ! 82: #define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write ! 83: // port ! 84: #define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read ! 85: // port ! 86: #define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the ! 87: // entire VGA subsystem ! 88: #define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and ! 89: #define SEQ_DATA_PORT 0x0015 // Data registers ! 90: #define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg ! 91: #define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg, ! 92: // write-only ! 93: #define DAC_STATE_PORT 0x0017 // DAC state (read/write), ! 94: // read-only ! 95: #define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg ! 96: #define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg ! 97: #define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port ! 98: #define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read ! 99: // port ! 100: #define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address ! 101: #define GRAPH_DATA_PORT 0x001F // and Data registers ! 102: ! 103: // ports in color mode ! 104: #define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and ! 105: #define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode ! 106: #define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port ! 107: #define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read ! 108: // port in color mode ! 109: #define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR ! 110: // Register to read to reset ! 111: // Attribute Controller index/data ! 112: // toggle in color mode ! 113: // ! 114: // Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed ! 115: // VGA registers. ! 116: // ! 117: ! 118: #define CRTC_ADDRESS_MONO_OFFSET 0x04 ! 119: #define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A ! 120: #define ATT_ADDRESS_OFFSET 0x10 ! 121: #define MISC_OUTPUT_REG_WRITE_OFFSET 0x12 ! 122: #define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13 ! 123: #define SEQ_ADDRESS_OFFSET 0x14 ! 124: #define DAC_PIXEL_MASK_OFFSET 0x16 ! 125: #define DAC_STATE_OFFSET 0x17 ! 126: #define DAC_ADDRESS_WRITE_OFFSET 0x18 ! 127: #define GRAPH_ADDRESS_OFFSET 0x1E ! 128: #define CRTC_ADDRESS_COLOR_OFFSET 0x24 ! 129: #define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A ! 130: // toggle in color mode ! 131: // ! 132: // VGA indexed register indexes. ! 133: // ! 134: ! 135: // CL-GD542x specific registers: ! 136: // ! 137: #define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts ! 138: #define IND_CL_SCRATCH_PAD 0x0A // index in Seq of POST scratch pad ! 139: #define IND_CL_ID_REG 0x27 // index in CRTC of ID Register ! 140: // ! 141: #define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start ! 142: #define IND_CURSOR_END 0x0B // and End registers ! 143: #define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location ! 144: #define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers ! 145: #define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync ! 146: // End register, which has the bit ! 147: // that protects/unprotects CRTC ! 148: // index registers 0-7 ! 149: #define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC ! 150: #define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC ! 151: #define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr ! 152: #define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr ! 153: #define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr ! 154: #define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr ! 155: #define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq ! 156: #define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer ! 157: #define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq ! 158: #define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in ! 159: // CRTC ! 160: #define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg ! 161: // in CRTC ! 162: #define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start ! 163: // synchronous reset ! 164: #define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end ! 165: // synchronous reset ! 166: ! 167: // ! 168: // Value to write to Extensions Control register values extensions. ! 169: // ! 170: ! 171: #define CL64xx_EXTENSION_ENABLE_INDEX 0x0A // GR0A to be exact! ! 172: #define CL64xx_EXTENSION_ENABLE_VALUE 0xEC ! 173: #define CL64xx_EXTENSION_DISABLE_VALUE 0xCE ! 174: #define CL64xx_TRISTATE_CONTROL_REG 0xA1 ! 175: ! 176: #define CL6340_ENABLE_READBACK_REGISTER 0xE0 ! 177: #define CL6340_ENABLE_READBACK_ALLSEL_VALUE 0xF0 ! 178: #define CL6340_ENABLE_READBACK_OFF_VALUE 0x00 ! 179: #define CL6340_IDENTIFICATION_REGISTER 0xE9 ! 180: // ! 181: // Values for Attribute Controller Index register to turn video off ! 182: // and on, by setting bit 5 to 0 (off) or 1 (on). ! 183: // ! 184: ! 185: #define VIDEO_DISABLE 0 ! 186: #define VIDEO_ENABLE 0x20 ! 187: ! 188: // Masks to keep only the significant bits of the Graphics Controller and ! 189: // Sequencer Address registers. Masking is necessary because some VGAs, such ! 190: // as S3-based ones, don't return unused bits set to 0, and some SVGAs use ! 191: // these bits if extensions are enabled. ! 192: // ! 193: ! 194: #define GRAPH_ADDR_MASK 0x0F ! 195: #define SEQ_ADDR_MASK 0x07 ! 196: ! 197: // ! 198: // Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register. ! 199: // ! 200: ! 201: #define CHAIN4_MASK 0x08 ! 202: ! 203: // ! 204: // Value written to the Read Map register when identifying the existence of ! 205: // a VGA in VgaInitialize. This value must be different from the final test ! 206: // value written to the Bit Mask in that routine. ! 207: // ! 208: ! 209: #define READ_MAP_TEST_SETTING 0x03 ! 210: ! 211: // ! 212: // Default text mode setting for various registers, used to restore their ! 213: // states if VGA detection fails after they've been modified. ! 214: // ! 215: ! 216: #define MEMORY_MODE_TEXT_DEFAULT 0x02 ! 217: #define BIT_MASK_DEFAULT 0xFF ! 218: #define READ_MAP_DEFAULT 0x00 ! 219: ! 220: ! 221: // ! 222: // Palette-related info. ! 223: // ! 224: ! 225: // ! 226: // Highest valid DAC color register index. ! 227: // ! 228: ! 229: #define VIDEO_MAX_COLOR_REGISTER 0xFF ! 230: ! 231: // ! 232: // Highest valid palette register index ! 233: // ! 234: ! 235: #define VIDEO_MAX_PALETTE_REGISTER 0x0F ! 236: ! 237: ! 238: // ! 239: // Indices for type of memory mapping; used in ModesVGA[], must match ! 240: // MemoryMap[]. ! 241: // ! 242: ! 243: typedef enum _VIDEO_MEMORY_MAP { ! 244: MemMap_Mono, ! 245: MemMap_CGA, ! 246: MemMap_VGA ! 247: } VIDEO_MEMORY_MAP, *PVIDEO_MEMORY_MAP; ! 248: ! 249: // ! 250: // For a mode, the type of banking supported. Controls the information ! 251: // returned in VIDEO_BANK_SELECT. PlanarHCBanking includes NormalBanking. ! 252: // ! 253: ! 254: typedef enum _BANK_TYPE { ! 255: NoBanking = 0, ! 256: NormalBanking, ! 257: PlanarHCBanking ! 258: } BANK_TYPE, *PBANK_TYPE; ! 259: ! 260: ! 261: #define CL6410 0x0001 ! 262: #define CL6420 0x0002 ! 263: #define CL542x 0x0004 ! 264: ! 265: // bitfields for the DisplayType ! 266: #define crt 0x0001 ! 267: #define panel 0x0002 ! 268: #define simulscan 0x0004 // this means both, but is unused for now. ! 269: ! 270: typedef struct { ! 271: PUSHORT pCL6410_crt; ! 272: PUSHORT pCL6410_panel; ! 273: PUSHORT pCL6420_crt; ! 274: PUSHORT pCL6420_panel; ! 275: PUSHORT pCL542x; ! 276: PUSHORT pStretchScan; ! 277: } CLCMD, *PCLCMD; ! 278: ! 279: typedef struct { ! 280: USHORT BiosModeCL6410; // bios modes are different across the ! 281: USHORT BiosModeCL6420; // products. that's why we need multiple ! 282: USHORT BiosModeCL542x; // values. ! 283: USHORT Montype; // montype for this mode. ! 284: } CLMODE, *PCLMODE; ! 285: ! 286: ! 287: // ! 288: // Structure used to describe each video mode in ModesVGA[]. ! 289: // ! 290: ! 291: typedef struct { ! 292: USHORT fbType; // color or monochrome, text or graphics, via ! 293: // VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS ! 294: USHORT numPlanes; // # of video memory planes ! 295: USHORT bitsPerPlane; // # of bits of color in each plane ! 296: SHORT col; // # of text columns across screen with default font ! 297: SHORT row; // # of text rows down screen with default font ! 298: USHORT hres; // # of pixels across screen ! 299: USHORT vres; // # of scan lines down screen ! 300: USHORT wbytes; // # of bytes from start of one scan line to start of next ! 301: ULONG sbytes; // total size of addressable display memory in bytes ! 302: ULONG Frequency; // Vertical Frequency ! 303: ULONG Interlaced; // Determines if the mode is interlaced or not ! 304: ULONG MonitorType; // Sets the determined frequency in an int10 ! 305: BANK_TYPE banktype; // NoBanking, NormalBanking, PlanarHCBanking ! 306: VIDEO_MEMORY_MAP MemMap; // index from VIDEO_MEMORY_MAP of memory ! 307: // mapping used by this mode ! 308: USHORT ChipType; // flags that say which chipset runs this mode ! 309: USHORT DisplayType; // display type this mode runs on(crt or panel) ! 310: BOOLEAN ValidMode; // TRUE if mode valid, FALSE if not ! 311: ! 312: CLMODE BiosModes; ! 313: ! 314: // ! 315: // the mode will be TRUE if there is enough video memory to support the ! 316: // mode, and the display type(it could be a panel), will support the mode. ! 317: // PANELS only support 640x480 for now. ! 318: // ! 319: CLCMD CmdStrings; // pointer to array of register-setting commands to ! 320: // set up mode ! 321: } VIDEOMODE, *PVIDEOMODE; ! 322: ! 323: // ! 324: // Mode into which to put the VGA before starting a VDM, so it's a plain ! 325: // vanilla VGA. (This is the mode's index in ModesVGA[], currently standard ! 326: // 80x25 text mode.) ! 327: // ! 328: ! 329: #define DEFAULT_MODE 0 ! 330: ! 331: ! 332: // ! 333: // Info used by the Validator functions and save/restore code. ! 334: // Structure used to trap register accesses that must be done atomically. ! 335: // ! 336: ! 337: #define VGA_MAX_VALIDATOR_DATA 100 ! 338: ! 339: #define VGA_VALIDATOR_UCHAR_ACCESS 1 ! 340: #define VGA_VALIDATOR_USHORT_ACCESS 2 ! 341: #define VGA_VALIDATOR_ULONG_ACCESS 3 ! 342: ! 343: typedef struct _VGA_VALIDATOR_DATA { ! 344: ULONG Port; ! 345: UCHAR AccessType; ! 346: ULONG Data; ! 347: } VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA; ! 348: ! 349: // ! 350: // Number of bytes to save in each plane. ! 351: // ! 352: ! 353: #define VGA_PLANE_SIZE 0x10000 ! 354: ! 355: // ! 356: // Number of each type of indexed register in a standard VGA, used by ! 357: // validator and state save/restore functions. ! 358: // ! 359: // Note: VDMs currently only support basic VGAs only. ! 360: // ! 361: ! 362: #define VGA_NUM_SEQUENCER_PORTS 5 ! 363: #define VGA_NUM_CRTC_PORTS 25 ! 364: #define VGA_NUM_GRAPH_CONT_PORTS 9 ! 365: #define VGA_NUM_ATTRIB_CONT_PORTS 21 ! 366: #define VGA_NUM_DAC_ENTRIES 256 ! 367: ! 368: #ifdef EXTENDED_REGISTER_SAVE_RESTORE ! 369: ! 370: // ! 371: // Indices to start save/restore in extension registers: ! 372: // For both chip types ! 373: ! 374: #define CL64xx_GRAPH_EXT_START 0x0b // does not include ext. enable ! 375: #define CL64xx_GRAPH_EXT_END 0xFF ! 376: ! 377: #define CL542x_GRAPH_EXT_START 0x09 ! 378: #define CL542x_GRAPH_EXT_END 0x39 ! 379: #define CL542x_SEQUENCER_EXT_START 0x07 // does not include ext. enable ! 380: #define CL542x_SEQUENCER_EXT_END 0x1F ! 381: #define CL542x_CRTC_EXT_START 0x19 ! 382: #define CL542x_CRTC_EXT_END 0x1B ! 383: ! 384: // ! 385: // Number of extended regs for both chip types ! 386: // ! 387: ! 388: #define CL64xx_NUM_GRAPH_EXT_PORTS (CL64xx_GRAPH_EXT_END - CL64xx_GRAPH_EXT_START + 1) ! 389: ! 390: #define CL542x_NUM_GRAPH_EXT_PORTS (CL542x_GRAPH_EXT_END - CL542x_GRAPH_EXT_START + 1) ! 391: #define CL542x_NUM_SEQUENCER_EXT_PORTS (CL542x_SEQUENCER_EXT_END - CL542x_SEQUENCER_EXT_START + 1) ! 392: #define CL542x_NUM_CRTC_EXT_PORTS (CL542x_CRTC_EXT_END - CL542x_CRTC_EXT_START + 1) ! 393: ! 394: // ! 395: // set values for save/restore area based on largest value for a chipset. ! 396: // ! 397: ! 398: #define EXT_NUM_GRAPH_CONT_PORTS ((CL64xx_NUM_GRAPH_EXT_PORTS > \ ! 399: CL542x_NUM_GRAPH_EXT_PORTS) ? \ ! 400: CL64xx_NUM_GRAPH_EXT_PORTS : \ ! 401: CL542x_NUM_GRAPH_EXT_PORTS) ! 402: #define EXT_NUM_SEQUENCER_PORTS CL542x_NUM_SEQUENCER_EXT_PORTS ! 403: #define EXT_NUM_CRTC_PORTS CL542x_NUM_CRTC_EXT_PORTS ! 404: #define EXT_NUM_ATTRIB_CONT_PORTS 0 ! 405: #define EXT_NUM_DAC_ENTRIES 0 ! 406: ! 407: #else ! 408: ! 409: #define EXT_NUM_GRAPH_CONT_PORTS 0 ! 410: #define EXT_NUM_SEQUENCER_PORTS 0 ! 411: #define EXT_NUM_CRTC_PORTS 0 ! 412: #define EXT_NUM_ATTRIB_CONT_PORTS 0 ! 413: #define EXT_NUM_DAC_ENTRIES 0 ! 414: ! 415: #endif ! 416: ! 417: // ! 418: // These constants determine the offsets within the ! 419: // VIDEO_HARDWARE_STATE_HEADER structure that are used to save and ! 420: // restore the VGA's state. ! 421: // ! 422: ! 423: #define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER) ! 424: ! 425: #define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0) ! 426: #define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \ ! 427: VGA_NUM_SEQUENCER_PORTS) ! 428: #define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \ ! 429: VGA_NUM_CRTC_PORTS) ! 430: #define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \ ! 431: VGA_NUM_GRAPH_CONT_PORTS) ! 432: #define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \ ! 433: VGA_NUM_ATTRIB_CONT_PORTS) ! 434: #define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \ ! 435: (3 * VGA_NUM_DAC_ENTRIES)) ! 436: ! 437: #define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4) ! 438: #define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \ ! 439: EXT_NUM_SEQUENCER_PORTS) ! 440: #define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \ ! 441: EXT_NUM_CRTC_PORTS) ! 442: #define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\ ! 443: EXT_NUM_GRAPH_CONT_PORTS) ! 444: #define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \ ! 445: EXT_NUM_ATTRIB_CONT_PORTS) ! 446: ! 447: #define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES) ! 448: ! 449: #define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \ ! 450: sizeof (VGA_VALIDATOR_DATA)) + \ ! 451: sizeof (ULONG) + \ ! 452: sizeof (ULONG) + \ ! 453: sizeof (PVIDEO_ACCESS_RANGE) ! 454: ! 455: #define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE ! 456: ! 457: #define VGA_MISC_DATA_AREA_SIZE 0 ! 458: ! 459: #define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE ! 460: ! 461: #define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE ! 462: #define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE ! 463: #define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE ! 464: ! 465: // ! 466: // Space needed to store all state data. ! 467: // ! 468: ! 469: #define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE ! 470: ! 471: ! 472: // ! 473: // Device extension for the driver object. This data is only used ! 474: // locally, so this structure can be added to as needed. ! 475: // ! 476: ! 477: typedef struct _HW_DEVICE_EXTENSION { ! 478: ! 479: PUCHAR IOAddress; // base I/O address of VGA ports ! 480: // PVOID VideoMemoryAddress; // base virtual memory address of VGA memory ! 481: PUCHAR VideoMemoryAddress; // base virtual memory address of VGA memory ! 482: ULONG NumAvailableModes; // number of available modes this session ! 483: ULONG ModeIndex; // index of current mode in ModesVGA[] ! 484: PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for ! 485: // current mode ! 486: ! 487: USHORT FontPelColumns; // Width of the font in pels ! 488: USHORT FontPelRows; // height of the font in pels ! 489: ! 490: VIDEO_CURSOR_POSITION CursorPosition; // current cursor position ! 491: ! 492: ! 493: UCHAR CursorEnable; // whether cursor is enabled or not ! 494: UCHAR CursorTopScanLine; // Cursor Start register setting (top scan) ! 495: UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan) ! 496: // add HW cursor data here ! 497: PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and ! 498: ULONG PhysicalVideoMemoryLength; // length of display memory ! 499: PHYSICAL_ADDRESS PhysicalFrameBase; // physical memory address and ! 500: ULONG PhysicalFrameLength; // length of display memory for the ! 501: // current mode. ! 502: ! 503: USHORT ChipType; // CL6410, CL6420, or CL542x ! 504: USHORT ChipRevision; // chip revision value ! 505: USHORT DisplayType; // crt, panel or simulscan ! 506: ULONG AdapterMemorySize; // amount of installed video ram ! 507: ! 508: // ! 509: // These 4 fields must be at the end of the device extension and must be ! 510: // kept in this order since this data will be copied to and from the save ! 511: // state buffer that is passed to and from the VDM. ! 512: // ! 513: ! 514: ULONG TrappedValidatorCount; // number of entries in the Trapped ! 515: // validator data Array. ! 516: VGA_VALIDATOR_DATA TrappedValidatorData[VGA_MAX_VALIDATOR_DATA]; ! 517: // Data trapped by the validator routines ! 518: // but not yet played back into the VGA ! 519: // register. ! 520: ! 521: ULONG SequencerAddressValue; // Determines if the Sequencer Address Port ! 522: // is currently selecting the SyncReset data ! 523: // register. ! 524: ! 525: ULONG CurrentNumVdmAccessRanges; // Number of access ranges in ! 526: // the access range array pointed ! 527: // to by the next field ! 528: PVIDEO_ACCESS_RANGE CurrentVdmAccessRange; // Access range currently ! 529: // associated to the VDM ! 530: ! 531: } HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION; ! 532: ! 533: ! 534: // ! 535: // Function prototypes. ! 536: // ! 537: ! 538: // ! 539: // Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[]. ! 540: // ! 541: ! 542: VP_STATUS ! 543: VgaValidatorUcharEntry ( ! 544: ULONG Context, ! 545: ULONG Port, ! 546: UCHAR AccessMode, ! 547: PUCHAR Data ! 548: ); ! 549: ! 550: VP_STATUS ! 551: VgaValidatorUshortEntry ( ! 552: ULONG Context, ! 553: ULONG Port, ! 554: UCHAR AccessMode, ! 555: PUSHORT Data ! 556: ); ! 557: ! 558: VP_STATUS ! 559: VgaValidatorUlongEntry ( ! 560: ULONG Context, ! 561: ULONG Port, ! 562: UCHAR AccessMode, ! 563: PULONG Data ! 564: ); ! 565: ! 566: BOOLEAN ! 567: VgaPlaybackValidatorData ( ! 568: PVOID Context ! 569: ); ! 570: ! 571: // ! 572: // Bank switch code start and end labels, define in HARDWARE.ASM ! 573: // ! 574: // two version for Cirrus Logic products ! 575: // ! 576: ! 577: extern UCHAR CL64xxBankSwitchStart; ! 578: extern UCHAR CL64xxBankSwitchEnd; ! 579: extern UCHAR CL64xxPlanarHCBankSwitchStart; ! 580: extern UCHAR CL64xxPlanarHCBankSwitchEnd; ! 581: extern UCHAR CL64xxEnablePlanarHCStart; ! 582: extern UCHAR CL64xxEnablePlanarHCEnd; ! 583: extern UCHAR CL64xxDisablePlanarHCStart; ! 584: extern UCHAR CL64xxDisablePlanarHCEnd; ! 585: ! 586: extern UCHAR CL542xBankSwitchStart; ! 587: extern UCHAR CL542xBankSwitchEnd; ! 588: extern UCHAR CL542xPlanarHCBankSwitchStart; ! 589: extern UCHAR CL542xPlanarHCBankSwitchEnd; ! 590: extern UCHAR CL542xEnablePlanarHCStart; ! 591: extern UCHAR CL542xEnablePlanarHCEnd; ! 592: extern UCHAR CL542xDisablePlanarHCStart; ! 593: extern UCHAR CL542xDisablePlanarHCEnd; ! 594: ! 595: // ! 596: // Vga init scripts for font loading ! 597: // ! 598: ! 599: extern USHORT EnableA000Data[]; ! 600: extern USHORT DisableA000Color[]; ! 601: ! 602: // ! 603: // Mode Information ! 604: // ! 605: ! 606: extern ULONG NumVideoModes; ! 607: extern VIDEOMODE ModesVGA[];
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