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1.1 root 1: title "Cirrus Logic ASM routines"
2: ;
3:
4: ;ONE_64K_BANK equ 1
5: TWO_32K_BANKS equ 1
6:
7: ;++
8: ;
9: ; Copyright (c) 1992 Microsoft Corporation
10: ;
11: ; Module Name:
12: ;
13: ; vgahard.asm
14: ;
15: ; Abstract:
16: ;
17: ; This module implements the banding code for the Cirrus Logic 6410,6420
18: ; and 542x VGA's.
19: ;
20: ; Environment:
21: ;
22: ; Kernel mode only.
23: ;
24: ; Revision History:
25: ;
26: ;
27: ;--
28:
29: .386p
30: .xlist
31: include callconv.inc
32: .list
33:
34: ;----------------------------------------------------------------------------
35: ;
36: ; Cirrus Logic banking control ports.
37: ;
38: GRAPHICS_ADDRESS_PORT equ 03ceh ;banking control here
39: CL6420_BANKING_INDEX_PORT_A equ 0eh ;banking index register A is GR0E
40: CL6420_BANKING_INDEX_PORT_B equ 0fh ;banking index register B is GR0F
41: CL542x_BANKING_INDEX_PORT_A equ 09h ;banking index register A is GR09
42: CL542x_BANKING_INDEX_PORT_B equ 0ah ;banking index register B is GR0A
43:
44: SEQ_ADDRESS_PORT equ 03C4h ;Sequencer Address register
45: IND_MEMORY_MODE equ 04h ;Memory Mode reg. index in Sequencer
46: CHAIN4_MASK equ 08h ;Chain4 bit in Memory Mode register
47:
48: ;----------------------------------------------------------------------------
49:
50: _TEXT SEGMENT DWORD USE32 PUBLIC 'CODE'
51: ASSUME CS:FLAT, DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
52: ;
53: ; Bank switching code. This is a 1-64K-read/1-64K-write bank adapter
54: ; (VideoBanked1R1W).
55: ;
56: ; Input:
57: ; EAX = desired read bank mapping
58: ; EDX = desired write bank mapping
59: ;
60: ; Note: values must be correct, with no stray bits set; no error
61: ; checking is performed.
62: ;
63: public _CL64xxBankSwitchStart
64: public _CL64xxBankSwitchEnd
65: public _CL64xxPlanarHCBankSwitchStart
66: public _CL64xxPlanarHCBankSwitchEnd
67: public _CL64xxEnablePlanarHCStart
68: public _CL64xxEnablePlanarHCEnd
69: public _CL64xxDisablePlanarHCStart
70: public _CL64xxDisablePlanarHCEnd
71:
72: public _CL542xBankSwitchStart
73: public _CL542xBankSwitchEnd
74: public _CL542xPlanarHCBankSwitchStart
75: public _CL542xPlanarHCBankSwitchEnd
76: public _CL542xEnablePlanarHCStart
77: public _CL542xEnablePlanarHCEnd
78: public _CL542xDisablePlanarHCStart
79: public _CL542xDisablePlanarHCEnd
80:
81: align 4
82:
83: ;---------------------------------------------------------------------------
84: ; two versions of banking code are given here, one for 1RW 64k bank, and
85: ; one for 2 32K RW banks. We will check out both implementations and see
86: ; which is faster performance-wise.
87:
88: IFDEF ONE_64K_BANK
89: _CL64xxBankSwitchStart proc ;start of bank switch code
90: _CL64xxPlanarHCBankSwitchStart: ;start of planar HC bank switch code,
91: ; which is the same code as normal
92: ; bank switching
93: ; shl eax,4 ;shift them to bits 7-4
94: ; mov ah,al
95: ; mov al,CL6420_BANKING_INDEX_PORT_A
96: ; mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
97: ; out dx,ax ;select the banks
98:
99: shl eax,4 ;shift them to bits 7-4
100: mov ah,al
101: mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
102: in al,dx
103: push eax ; save index
104: mov al,CL6420_BANKING_INDEX_PORT_A
105: out dx,ax ;select the banks
106:
107: pop eax ; restore index
108: out dx,al
109: ret
110:
111: _CL64xxBankSwitchEnd:
112: _CL64xxPlanarHCBankSwitchEnd:
113:
114: align 4
115: _CL64xxEnablePlanarHCStart:
116: mov dx,SEQ_ADDRESS_PORT
117: in al,dx
118: push eax ;preserve the state of the Seq Address
119: mov al,IND_MEMORY_MODE
120: out dx,al ;point to the Memory Mode register
121: inc edx
122: in al,dx ;get the state of the Memory Mode reg
123: and al,NOT CHAIN4_MASK ;turn off Chain4 to make memory planar
124: out dx,al
125: dec edx
126: pop eax
127: out dx,al ;restore the original Seq Address
128:
129: ERA1_INDEX equ 0A1h
130:
131: mov dx,GRAPHICS_ADDRESS_PORT
132: in al,dx
133: push eax ;preserve the Graphics Index
134: mov al,ERA1_INDEX
135: out dx,al ;point to ERA1
136: inc edx
137: in al,dx ; get ERA1
138: and al,not 30h ; turn off the shift bits
139: out dx,al
140: dec edx
141: pop eax
142: out dx,al ;restore the original Graphics Index
143:
144: ret
145:
146: _CL64xxEnablePlanarHCEnd:
147:
148: align 4
149: _CL64xxDisablePlanarHCStart:
150: mov dx,SEQ_ADDRESS_PORT
151: in al,dx
152: push eax ;preserve the state of the Seq Address
153: mov al,IND_MEMORY_MODE
154: out dx,al ;point to the Memory Mode register
155: inc edx
156: in al,dx ;get the state of the Memory Mode reg
157: or al,CHAIN4_MASK ;turn on Chain4 to make memory linear
158: out dx,al
159: dec edx
160: pop eax
161: out dx,al ;restore the original Seq Address
162:
163: mov dx,GRAPHICS_ADDRESS_PORT
164: in al,dx
165: push eax ;preserve the Graphics Index
166: mov al,ERA1_INDEX
167: out dx,al ;point to ERA1
168: inc edx
169: in al,dx ; get ERA1
170: and al,not 30h
171: or al,20h
172: out dx,al
173: dec edx
174: pop eax
175: out dx,al ;restore the original Graphics Index
176: ret
177:
178: _CL64xxDisablePlanarHCEnd:
179:
180: ;
181: ;
182: _CL64xxBankSwitchStart endp
183:
184: nop
185: align 4
186: _CL542xBankSwitchStart proc ;start of bank switch code
187: _CL542xPlanarHCBankSwitchStart: ;start of planar HC bank switch code,
188: ; which is the same code as normal
189: ; bank switching
190: shl eax,4 ;shift them to bits 7-4
191: mov ah,al
192: mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
193: in al,dx
194: push eax
195: mov al,CL542x_BANKING_INDEX_PORT_A
196: out dx,ax ;select the banks
197: pop eax ; restore index
198: out dx,al
199:
200: ret
201:
202: _CL542xBankSwitchEnd:
203: _CL542xPlanarHCBankSwitchEnd:
204:
205: align 4
206: _CL542xEnablePlanarHCStart:
207: mov dx,SEQ_ADDRESS_PORT
208: in al,dx
209: push eax ;preserve the state of the Seq Address
210: mov al,IND_MEMORY_MODE
211: out dx,al ;point to the Memory Mode register
212: inc edx
213: in al,dx ;get the state of the Memory Mode reg
214: and al,NOT CHAIN4_MASK ;turn off Chain4 to make memory planar
215: out dx,al
216: dec edx
217: pop eax
218: out dx,al ;restore the original Seq Address
219: ret
220:
221: _CL542xEnablePlanarHCEnd:
222:
223: align 4
224: _CL542xDisablePlanarHCStart:
225: mov dx,SEQ_ADDRESS_PORT
226: in al,dx
227: push eax ;preserve the state of the Seq Address
228: mov al,IND_MEMORY_MODE
229: out dx,al ;point to the Memory Mode register
230: inc edx
231: in al,dx ;get the state of the Memory Mode reg
232: or al,CHAIN4_MASK ;turn on Chain4 to make memory linear
233: out dx,al
234: dec edx
235: pop eax
236: out dx,al ;restore the original Seq Address
237: ret
238:
239: _CL542xDisablePlanarHCEnd:
240:
241: _CL542xBankSwitchStart endp
242:
243: ENDIF ;ONE_64K_BANK
244: ;----------------------------------------------------------------------------
245: IFDEF TWO_32K_BANKS
246: _CL64xxBankSwitchStart proc ;start of bank switch code
247: _CL64xxPlanarHCBankSwitchStart: ;start of planar HC bank switch code,
248: ; which is the same code as normal
249: ; bank switching
250: shl eax,3 ;shift them to bits 7-4
251: shl edx,3 ;shift them to bits 7-4
252: ;!!!! NOTE: The October 1992 release NT VGA driver assumes that the Graphics
253: ; index is not changed by the bank switch code. We save it on the
254: ; stack (and save the write bank value in the high order of edx)
255: ; and restore it at the end of the routine. If the NT VGA driver
256: ; changes so that it is the index need not be preserved, this code
257: ; could be simplified (and speeded up!)
258: rol edx,16 ; save write value
259: mov ah,al
260: mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
261: in al,dx ; save graphics index
262: push eax
263: mov al,CL6420_BANKING_INDEX_PORT_A
264: out dx,ax ;select the READ bank
265: rol edx,16
266: mov ah,dl
267: mov al,CL6420_BANKING_INDEX_PORT_B
268: mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
269: out dx,ax ;select the WRITE bank
270: pop eax
271: out dx,al
272:
273: ret
274:
275: _CL64xxBankSwitchEnd:
276: _CL64xxPlanarHCBankSwitchEnd:
277:
278: align 4
279: _CL64xxEnablePlanarHCStart:
280: mov dx,SEQ_ADDRESS_PORT
281: in al,dx
282: push eax ;preserve the state of the Seq Address
283: mov al,IND_MEMORY_MODE
284: out dx,al ;point to the Memory Mode register
285: inc edx
286: in al,dx ;get the state of the Memory Mode reg
287: and al,NOT CHAIN4_MASK ;turn off Chain4 to make memory planar
288: out dx,al
289: dec edx
290: pop eax
291: out dx,al ;restore the original Seq Address
292:
293: ERA1_INDEX equ 0A1h
294:
295: mov dx,GRAPHICS_ADDRESS_PORT
296: in al,dx
297: push eax ;preserve the Graphics Index
298: mov al,ERA1_INDEX
299: out dx,al ;point to ERA1
300: inc edx
301: in al,dx ; get ERA1
302: and al,not 30h ; turn off the shift bits
303: out dx,al
304: dec edx
305: pop eax
306: out dx,al ;restore the original Graphics Index
307: ret
308:
309: _CL64xxEnablePlanarHCEnd:
310:
311: align 4
312: _CL64xxDisablePlanarHCStart:
313: mov dx,SEQ_ADDRESS_PORT
314: in al,dx
315: push eax ;preserve the state of the Seq Address
316: mov al,IND_MEMORY_MODE
317: out dx,al ;point to the Memory Mode register
318: inc edx
319: in al,dx ;get the state of the Memory Mode reg
320: or al,CHAIN4_MASK ;turn on Chain4 to make memory linear
321: out dx,al
322: dec edx
323: pop eax
324: out dx,al ;restore the original Seq Address
325:
326: mov dx,GRAPHICS_ADDRESS_PORT
327: in al,dx
328: push eax ;preserve the Graphics Index
329: mov al,ERA1_INDEX
330: out dx,al ;point to ERA1
331: inc edx
332: in al,dx ; get ERA1
333: and al,not 30h
334: or al,20h
335: out dx,al
336: dec edx
337: pop eax
338: out dx,al ;restore the original Graphics Index
339: ret
340:
341: _CL64xxDisablePlanarHCEnd:
342:
343: _CL64xxBankSwitchStart endp
344:
345:
346: _CL542xBankSwitchStart proc ;start of bank switch code
347: _CL542xPlanarHCBankSwitchStart: ;start of planar HC bank switch code,
348: ; which is the same code as normal
349: ; bank switching
350: shl eax,3 ;shift them to bits 7-4
351: shl edx,3 ;shift them to bits 7-4
352: ;!!!! NOTE: The October 1992 release NT VGA driver assumes that the Graphics
353: ; index is not changed by the bank switch code. We save it on the
354: ; stack (and save the write bank value in the high order of edx)
355: ; and restore it at the end of the routine. If the NT VGA driver
356: ; changes so that it is the index need not be preserved, this code
357: ; could be simplified (and speeded up!)
358: rol edx,16 ; save write value
359: mov ah,al
360: mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
361: in al,dx
362: push eax
363: mov al,CL542x_BANKING_INDEX_PORT_A
364: out dx,ax ;select the READ bank
365:
366: rol edx,16 ; restore write value
367: mov ah,dl
368: mov al,CL542x_BANKING_INDEX_PORT_B
369: mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
370: out dx,ax ;select the WRITE bank
371: pop eax
372: out dx,al
373:
374: ret
375:
376: _CL542xBankSwitchEnd:
377: _CL542xPlanarHCBankSwitchEnd:
378:
379: align 4
380: _CL542xEnablePlanarHCStart:
381: mov dx,SEQ_ADDRESS_PORT
382: in al,dx
383: push eax ;preserve the state of the Seq Address
384: mov al,IND_MEMORY_MODE
385: out dx,al ;point to the Memory Mode register
386: inc edx
387: in al,dx ;get the state of the Memory Mode reg
388: and al,NOT CHAIN4_MASK ;turn off Chain4 to make memory planar
389: out dx,al
390: dec edx
391: pop eax
392: out dx,al ;restore the original Seq Address
393: ret
394:
395: _CL542xEnablePlanarHCEnd:
396:
397: align 4
398: _CL542xDisablePlanarHCStart:
399: mov dx,SEQ_ADDRESS_PORT
400: in al,dx
401: push eax ;preserve the state of the Seq Address
402: mov al,IND_MEMORY_MODE
403: out dx,al ;point to the Memory Mode register
404: inc edx
405: in al,dx ;get the state of the Memory Mode reg
406: or al,CHAIN4_MASK ;turn on Chain4 to make memory linear
407: out dx,al
408: dec edx
409: pop eax
410: out dx,al ;restore the original Seq Address
411: ret
412:
413: _CL542xDisablePlanarHCEnd:
414:
415:
416: _CL542xBankSwitchStart endp
417:
418: ENDIF ;TWO_32K_BANKS
419:
420: _TEXT ends
421: end
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