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1.1 root 1: /*++
2:
3: Copyright (c) 1992 Cirrus Logic, Inc.
4:
5: Module Name:
6:
7: Mode6410.h
8:
9: Abstract:
10:
11: This module contains all the global data used by the Cirrus Logic
12: CL-6410 driver.
13:
14: Environment:
15:
16: Kernel mode
17:
18: Revision History:
19:
20: --*/
21:
22: //
23: // The first set of tables are for the CL6410
24: // Note that only 640x480 and 800x600 are supported.
25: //
26: // Color graphics mode 0x12, 640x480 16 colors.
27: //
28: USHORT CL6410_640x480_crt[] = {
29: // Unlock Key for color mode
30: OW, // GR0A = 0xEC opens extension registers
31: GRAPH_ADDRESS_PORT,
32: 0xec0a,
33:
34: #ifndef INT10_MODE_SET
35: OWM,
36: SEQ_ADDRESS_PORT,
37: 5,
38: 0x0100, // start synch reset
39: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
40:
41: OB,
42: MISC_OUTPUT_REG_WRITE_PORT,
43: 0xe3,
44:
45: OW, //{ SetGraphCmd,{ "\x05", 0x06, 1 } },
46: GRAPH_ADDRESS_PORT,
47: 0x0506,
48:
49: // EndSyncResetCmd
50: OW,
51: SEQ_ADDRESS_PORT,
52: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
53:
54: OW,
55: CRTC_ADDRESS_PORT_COLOR,
56: 0x0111,
57:
58: METAOUT+INDXOUT, // program crtc registers
59: CRTC_ADDRESS_PORT_COLOR,
60: VGA_NUM_CRTC_PORTS, // count
61: 0, // start index
62: 0x5F,0x4F,0x50,0x82,
63: 0x54,0x80,0x0B,0x3E,
64: 0x00,0x40,0x00,0x00,
65: 0x00,0x00,0x00,0x00,
66: 0xEA,0xAC,0xDF,0x28,
67: 0x00,0xE7,0x04,0xE3,
68: 0xFF,
69:
70: // extension registers
71: OWM,
72: GRAPH_ADDRESS_PORT,
73: 16,
74: 0x0262, // ER62 horz. display end extension
75: 0x8064, // ER64 horz. retrace end extension
76: 0x0079, // ER79 vertical overflow
77: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
78: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
79: 0x007c, // ER7c screen A start addr. extension
80: 0x0081, // ER81 display mode
81: 0x0082, // ER82 character clock selection
82: 0x1084, // ER84 clock select extension
83: 0x0090, // ER90 display memory control
84: 0x0091, // ER91 CRT-circular buffer policy select
85: 0x0095, // ER95 CRT-circular buffer delta & burst
86: 0x0096, // ER96 display memory control test
87: 0x12a0, // ERa0 bus interface unit control
88: 0x00a1, // ERa1 three-state and test control
89: 0x00c8, // ERc8 RAMDAC control
90:
91: IB, // prepare atc for writing
92: INPUT_STATUS_1_COLOR,
93:
94: METAOUT+ATCOUT, //
95: ATT_ADDRESS_PORT, // port
96: VGA_NUM_ATTRIB_CONT_PORTS, // count
97: 0, // start index
98: 0x00,0x01,0x02,0x03,0x04,
99: 0x05,0x14,0x07,0x38,0x39,
100: 0x3A,0x3B,0x3C,0x3D,0x3E,
101: 0x3F,0x01,0x00,0x0F,0x00,0x00,
102:
103: METAOUT+INDXOUT, //
104: GRAPH_ADDRESS_PORT, // port
105: VGA_NUM_GRAPH_CONT_PORTS, // count
106: 0, // start index
107: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
108:
109: OB, // turn video on.
110: ATT_ADDRESS_PORT,
111: VIDEO_ENABLE,
112:
113: #endif
114: // disable banking
115: OWM,
116: GRAPH_ADDRESS_PORT,
117: 3,
118: 0x030d, // ER0D = Paging control: 1 64K page,
119: 0x000e, // ER0E page A address = 0
120: 0x000f, // ER0F page B address = 0
121:
122: OB,
123: DAC_PIXEL_MASK_PORT,
124: 0xFF,
125:
126: EOD
127: };
128:
129: USHORT CL6410_640x480_panel[] = {
130: // Unlock Key for color mode
131: OW, // GR0A = 0xEC opens extension registers
132: GRAPH_ADDRESS_PORT,
133: 0xec0a,
134:
135: #ifndef INT10_MODE_SET
136: OWM,
137: SEQ_ADDRESS_PORT,
138: 5,
139: 0x0100, // start synch reset
140: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
141:
142: OB,
143: MISC_OUTPUT_REG_WRITE_PORT,
144: 0xe3,
145:
146: OW, //{ SetGraphCmd,{ "\x05", 0x06, 1 } },
147: GRAPH_ADDRESS_PORT,
148: 0x0506,
149:
150: // EndSyncResetCmd
151: OW,
152: SEQ_ADDRESS_PORT,
153: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
154:
155: OW,
156: CRTC_ADDRESS_PORT_COLOR,
157: 0x0111,
158:
159: METAOUT+INDXOUT, // program crtc registers
160: CRTC_ADDRESS_PORT_COLOR,
161: VGA_NUM_CRTC_PORTS, // count
162: 0, // start index
163: 0x5F,0x4F,0x50,0x82,
164: 0x54,0x80,0x0B,0x3E,
165: 0x00,0x40,0x00,0x00,
166: 0x00,0x00,0x00,0x00,
167: 0xEA,0xAC,0xDF,0x28,
168: 0x00,0xE7,0x04,0xE3,
169: 0xFF,
170:
171: // extension registers
172: OWM,
173: GRAPH_ADDRESS_PORT,
174: 16,
175: 0x0262, // ER62 horz. display end extension
176: 0x8064, // ER64 horz. retrace end extension
177: 0x0079, // ER79 vertical overflow
178: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
179: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
180: 0x007c, // ER7c screen A start addr. extension
181: 0x0181, // ER81 display mode
182: 0x8982, // ER82 character clock selection
183: 0xa684, // ER84 clock select extension
184: 0x0090, // ER90 display memory control
185: 0x0091, // ER91 CRT-circular buffer policy select
186: 0x0095, // ER95 CRT-circular buffer delta & burst
187: 0x0096, // ER96 display memory control test
188: 0x12a0, // ERa0 bus interface unit control
189: 0x00a1, // ERa1 three-state and test control
190: 0xa0c8, // ERc8 RAMDAC control
191:
192: IB, // prepare atc for writing
193: INPUT_STATUS_1_COLOR,
194:
195: METAOUT+ATCOUT, //
196: ATT_ADDRESS_PORT, // port
197: VGA_NUM_ATTRIB_CONT_PORTS, // count
198: 0, // start index
199: 0x00,0x01,0x02,0x03,0x04,
200: 0x05,0x14,0x07,0x38,0x39,
201: 0x3A,0x3B,0x3C,0x3D,0x3E,
202: 0x3F,0x01,0x00,0x0F,0x00,0x00,
203:
204: METAOUT+INDXOUT, //
205: GRAPH_ADDRESS_PORT, // port
206: VGA_NUM_GRAPH_CONT_PORTS, // count
207: 0, // start index
208: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
209:
210: OB, // turn video on.
211: ATT_ADDRESS_PORT,
212: VIDEO_ENABLE,
213:
214: #endif
215: // disable banking
216: OWM,
217: GRAPH_ADDRESS_PORT,
218: 3,
219: 0x030d, // ER0D = Paging control: 1 64K page,
220: 0x000e, // ER0E page A address = 0
221: 0x000f, // ER0F page B address = 0
222:
223: OB,
224: DAC_PIXEL_MASK_PORT,
225: 0xFF,
226:
227: EOD
228: };
229:
230:
231:
232: //
233: // Cirrus color graphics mode 0x64, 800x600 16 colors.
234: //
235: USHORT CL6410_800x600_crt[] = {
236: // Unlock Key for color mode
237: OW, // GR0A = 0xEC opens extension registers
238: GRAPH_ADDRESS_PORT,
239: 0xec0a,
240:
241: #ifndef INT10_MODE_SET
242: OWM,
243: SEQ_ADDRESS_PORT,
244: 5,
245: 0x0100, // start synch reset
246: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
247:
248: OB,
249: MISC_OUTPUT_REG_WRITE_PORT,
250: 0x2f,
251:
252: OWM,
253: GRAPH_ADDRESS_PORT,
254: 3,
255: 0x0506,
256: 0x0f07,
257: 0xff08,
258:
259: // EndSyncResetCmd
260: OW,
261: SEQ_ADDRESS_PORT,
262: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
263:
264: OW,
265: CRTC_ADDRESS_PORT_COLOR,
266: 0x0E11,
267:
268: METAOUT+INDXOUT, // program crtc registers
269: CRTC_ADDRESS_PORT_COLOR,
270: VGA_NUM_CRTC_PORTS, // count
271: 0, // start index
272: 0x7b,0x63,0x64,0x9e,
273: 0x69,0x92,0x6f,0xf0,
274: 0x00,0x60,0x00,0x00,
275: 0x00,0x00,0x00,0x00,
276: 0x58,0xaa,0x57,0x32,
277: 0x00,0x58,0x6f,0xe3,
278: 0xFF,
279:
280: // extension registers
281: OWM,
282: GRAPH_ADDRESS_PORT,
283: 16,
284: 0x1e62, // ER62 horz. display end extension
285: 0x9264, // ER64 horz. retrace end extension
286: 0x0079, // ER79 vertical overflow
287: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
288: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
289: 0x007c, // ER7c screen A start addr. extension
290: 0x0081, // ER81 display mode
291: 0x0082, // ER82 character clock selection
292: 0xac84, // ER84 clock select extension
293: 0x0090, // ER90 display memory control
294: 0x0391, // ER91 CRT-circular buffer policy select
295: 0x0a95, // ER95 CRT-circular buffer delta & burst
296: 0x0096, // ER96 display memory control test
297: 0x12a0, // ERa0 bus interface unit control
298: 0x00a1, // ERa1 three-state and test control
299: 0x00c8, // ERc8 RAMDAC control
300:
301: IB, // prepare atc for writing
302: INPUT_STATUS_1_COLOR,
303:
304: METAOUT+ATCOUT, //
305: ATT_ADDRESS_PORT, // port
306: VGA_NUM_ATTRIB_CONT_PORTS, // count
307: 0, // start index
308: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
309: 0x01,0x0,0x0F,0x0,0x0,
310:
311: METAOUT+INDXOUT, //
312: GRAPH_ADDRESS_PORT, // port
313: VGA_NUM_GRAPH_CONT_PORTS, // count
314: 0, // start index
315: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
316:
317: OB, // turn video on.
318: ATT_ADDRESS_PORT,
319: VIDEO_ENABLE,
320:
321: #endif
322: // disable banking
323: OWM,
324: GRAPH_ADDRESS_PORT,
325: 3,
326: 0x030d, // ER0D = Paging control: 1 64K page,
327: 0x000e, // ER0E page A address = 0
328: 0x000f, // ER0F page B address = 0
329:
330: OB,
331: DAC_PIXEL_MASK_PORT,
332: 0xFF,
333:
334: EOD
335: };
336: //-----------------------------
337: // standard VGA text modes here
338: //-----------------------------
339:
340: USHORT CL6410_80x25_14_Text_crt[] = {
341: // Unlock Key for color mode
342: OW, // GR0A = 0xEC opens extension registers
343: GRAPH_ADDRESS_PORT,
344: 0xec0a,
345:
346: #ifndef INT10_MODE_SET
347: OWM,
348: SEQ_ADDRESS_PORT,
349: 5,
350: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
351:
352: OB,
353: MISC_OUTPUT_REG_WRITE_PORT,
354: 0x67,
355:
356: OW,
357: GRAPH_ADDRESS_PORT,
358: 0x0e06,
359:
360: // EndSyncResetCmd
361: OW,
362: SEQ_ADDRESS_PORT,
363: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
364:
365: OW,
366: CRTC_ADDRESS_PORT_COLOR,
367: 0x0511,
368:
369: METAOUT+INDXOUT, // program crtc registers
370: CRTC_ADDRESS_PORT_COLOR,
371: VGA_NUM_CRTC_PORTS, // count
372: 0, // start index
373: 0x5F,0x4f,0x50,0x82,
374: 0x55,0x81,0xbf,0x1f,
375: 0x00,0x4f,0x0d,0x0e,
376: 0x00,0x00,0x01,0xe0,
377: 0x9c,0xae,0x8f,0x28,
378: 0x1f,0x96,0xb9,0xa3,
379: 0xFF,
380:
381: // extension registers
382: OWM,
383: GRAPH_ADDRESS_PORT,
384: 16,
385: 0x0262, // ER62 horz. display end extension
386: 0x8164, // ER64 horz. retrace end extension
387: 0x0079, // ER79 vertical overflow
388: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
389: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
390: 0x007c, // ER7c screen A start addr. extension
391: 0x0081, // ER81 display mode
392: 0x0082, // ER82 character clock selection
393: 0x1084, // ER84 clock select extension
394: 0x0090, // ER90 display memory control
395: 0x0391, // ER91 CRT-circular buffer policy select
396: 0x0095, // ER95 CRT-circular buffer delta & burst
397: 0x0096, // ER96 display memory control test
398: 0x12a0, // ERa0 bus interface unit control
399: 0x00a1, // ERa1 three-state and test control
400: 0x00c8, // ERc8 RAMDAC control
401:
402: IB, // prepare atc for writing
403: INPUT_STATUS_1_COLOR,
404:
405: METAOUT+ATCOUT, //
406: ATT_ADDRESS_PORT, // port
407: VGA_NUM_ATTRIB_CONT_PORTS, // count
408: 0, // start index
409: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
410: 0x00,0x0,0x0F,0x0,0x0,
411:
412: METAOUT+INDXOUT, //
413: GRAPH_ADDRESS_PORT, // port
414: VGA_NUM_GRAPH_CONT_PORTS, // count
415: 0, // start index
416: 0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
417:
418: IB, // prepare atc for writing
419: INPUT_STATUS_1_COLOR,
420:
421: OB, // turn video on.
422: ATT_ADDRESS_PORT,
423: VIDEO_ENABLE,
424:
425: #endif
426: // disable banking
427: OWM,
428: GRAPH_ADDRESS_PORT,
429: 3,
430: 0x030d, // ER0D = Paging control: 1 64K page,
431: 0x000e, // ER0E page A address = 0
432: 0x000f, // ER0F page B address = 0
433:
434: OB,
435: DAC_PIXEL_MASK_PORT,
436: 0xFF,
437:
438: EOD
439: };
440: //
441: // 80x25 and 720 x 400
442: //
443:
444: USHORT CL6410_80x25_14_Text_panel[] = {
445: // Unlock Key for color mode
446: OW, // GR0A = 0xEC opens extension registers
447: GRAPH_ADDRESS_PORT,
448: 0xec0a,
449:
450: #ifndef INT10_MODE_SET
451: OWM,
452: SEQ_ADDRESS_PORT,
453: 5,
454: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
455:
456: OWM,
457: SEQ_ADDRESS_PORT,
458: 2,
459: 0x0006,0x0fc07, // program up sequencer
460:
461: OB,
462: MISC_OUTPUT_REG_WRITE_PORT,
463: 0x67,
464:
465: OW,
466: GRAPH_ADDRESS_PORT,
467: 0x0e06,
468:
469: // EndSyncResetCmd
470: OW,
471: SEQ_ADDRESS_PORT,
472: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
473:
474: OW,
475: CRTC_ADDRESS_PORT_COLOR,
476: 0x0E11,
477:
478: METAOUT+INDXOUT, // program crtc registers
479: CRTC_ADDRESS_PORT_COLOR,
480: VGA_NUM_CRTC_PORTS, // count
481: 0, // start index
482: 0x5F,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0xd,0xe,0x0,0x0,0x0,0x0,
483: 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,0xFF,
484:
485: // extension registers
486: OWM,
487: GRAPH_ADDRESS_PORT,
488: 16,
489: 0x1e62, // ER62 horz. display end extension
490: 0x9264, // ER64 horz. retrace end extension
491: 0x0079, // ER79 vertical overflow
492: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
493: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
494: 0x007c, // ER7c screen A start addr. extension
495: 0x0081, // ER81 display mode
496: 0x0082, // ER82 character clock selection
497: 0xac84, // ER84 clock select extension
498: 0x0090, // ER90 display memory control
499: 0x0391, // ER91 CRT-circular buffer policy select
500: 0x0a95, // ER95 CRT-circular buffer delta & burst
501: 0x0096, // ER96 display memory control test
502: 0x12a0, // ERa0 bus interface unit control
503: 0x00a1, // ERa1 three-state and test control
504: 0x00c8, // ERc8 RAMDAC control
505:
506: IB, // prepare atc for writing
507: INPUT_STATUS_1_COLOR,
508:
509: METAOUT+ATCOUT, //
510: ATT_ADDRESS_PORT, // port
511: VGA_NUM_ATTRIB_CONT_PORTS, // count
512: 0, // start index
513: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
514: 0x04,0x0,0x0F,0x8,0x0,
515:
516: METAOUT+INDXOUT, //
517: GRAPH_ADDRESS_PORT, // port
518: VGA_NUM_GRAPH_CONT_PORTS, // count
519: 0, // start index
520: 0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
521:
522: OB, // turn video on.
523: ATT_ADDRESS_PORT,
524: VIDEO_ENABLE,
525:
526: #endif
527: // disable banking
528: OWM,
529: GRAPH_ADDRESS_PORT,
530: 3,
531: 0x030d, // ER0D = Paging control: 1 64K page,
532: 0x000e, // ER0E page A address = 0
533: 0x000f, // ER0F page B address = 0
534:
535: OB,
536: DAC_PIXEL_MASK_PORT,
537: 0xFF,
538:
539: EOD
540: };
541: USHORT CL6410_80x25Text_crt[] = {
542: // Unlock Key for color mode
543: OW, // GR0A = 0xEC opens extension registers
544: GRAPH_ADDRESS_PORT,
545: 0xec0a,
546:
547: #ifndef INT10_MODE_SET
548: OWM,
549: SEQ_ADDRESS_PORT,
550: 5,
551: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
552:
553: OB,
554: MISC_OUTPUT_REG_WRITE_PORT,
555: 0x67,
556:
557: OW,
558: GRAPH_ADDRESS_PORT,
559: 0x0e06,
560:
561: // EndSyncResetCmd
562: OW,
563: SEQ_ADDRESS_PORT,
564: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
565:
566: OW,
567: CRTC_ADDRESS_PORT_COLOR,
568: 0x0511,
569:
570: METAOUT+INDXOUT, // program crtc registers
571: CRTC_ADDRESS_PORT_COLOR,
572: VGA_NUM_CRTC_PORTS, // count
573: 0, // start index
574: 0x5F,0x4f,0x50,0x82,
575: 0x55,0x81,0xbf,0x1f,
576: 0x00,0x4f,0x0d,0x0e,
577: 0x00,0x00,0x01,0xe0,
578: 0x9c,0xae,0x8f,0x28,
579: 0x1f,0x96,0xb9,0xa3,
580: 0xFF,
581:
582: // extension registers
583: OWM,
584: GRAPH_ADDRESS_PORT,
585: 16,
586: 0x0262, // ER62 horz. display end extension
587: 0x8164, // ER64 horz. retrace end extension
588: 0x0079, // ER79 vertical overflow
589: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
590: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
591: 0x007c, // ER7c screen A start addr. extension
592: 0x0081, // ER81 display mode
593: 0x0082, // ER82 character clock selection
594: 0x1084, // ER84 clock select extension
595: 0x0090, // ER90 display memory control
596: 0x0391, // ER91 CRT-circular buffer policy select
597: 0x0095, // ER95 CRT-circular buffer delta & burst
598: 0x0096, // ER96 display memory control test
599: 0x12a0, // ERa0 bus interface unit control
600: 0x00a1, // ERa1 three-state and test control
601: 0x00c8, // ERc8 RAMDAC control
602:
603: IB, // prepare atc for writing
604: INPUT_STATUS_1_COLOR,
605:
606: METAOUT+ATCOUT, //
607: ATT_ADDRESS_PORT, // port
608: VGA_NUM_ATTRIB_CONT_PORTS, // count
609: 0, // start index
610: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
611: 0x00,0x0,0x0F,0x0,0x0,
612:
613: METAOUT+INDXOUT, //
614: GRAPH_ADDRESS_PORT, // port
615: VGA_NUM_GRAPH_CONT_PORTS, // count
616: 0, // start index
617: 0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
618:
619: IB, // prepare atc for writing
620: INPUT_STATUS_1_COLOR,
621:
622: OB, // turn video on.
623: ATT_ADDRESS_PORT,
624: VIDEO_ENABLE,
625:
626: #endif
627: // disable banking
628: OWM,
629: GRAPH_ADDRESS_PORT,
630: 3,
631: 0x030d, // ER0D = Paging control: 1 64K page,
632: 0x000e, // ER0E page A address = 0
633: 0x000f, // ER0F page B address = 0
634:
635: OB,
636: DAC_PIXEL_MASK_PORT,
637: 0xFF,
638:
639: EOD
640: };
641: //
642: // 80x25 and 720 x 400
643: //
644:
645: USHORT CL6410_80x25Text_panel[] = {
646: // Unlock Key for color mode
647: OW, // GR0A = 0xEC opens extension registers
648: GRAPH_ADDRESS_PORT,
649: 0xec0a,
650:
651: #ifndef INT10_MODE_SET
652: OWM,
653: SEQ_ADDRESS_PORT,
654: 5,
655: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
656:
657: OWM,
658: SEQ_ADDRESS_PORT,
659: 2,
660: 0x0006,0x0fc07, // program up sequencer
661:
662: OB,
663: MISC_OUTPUT_REG_WRITE_PORT,
664: 0x67,
665:
666: OW,
667: GRAPH_ADDRESS_PORT,
668: 0x0e06,
669:
670: // EndSyncResetCmd
671: OW,
672: SEQ_ADDRESS_PORT,
673: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
674:
675: OW,
676: CRTC_ADDRESS_PORT_COLOR,
677: 0x0E11,
678:
679: METAOUT+INDXOUT, // program crtc registers
680: CRTC_ADDRESS_PORT_COLOR,
681: VGA_NUM_CRTC_PORTS, // count
682: 0, // start index
683: 0x5F,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0xd,0xe,0x0,0x0,0x0,0x0,
684: 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,0xFF,
685:
686: // extension registers
687: OWM,
688: GRAPH_ADDRESS_PORT,
689: 16,
690: 0x1e62, // ER62 horz. display end extension
691: 0x9264, // ER64 horz. retrace end extension
692: 0x0079, // ER79 vertical overflow
693: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
694: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
695: 0x007c, // ER7c screen A start addr. extension
696: 0x0081, // ER81 display mode
697: 0x0082, // ER82 character clock selection
698: 0xac84, // ER84 clock select extension
699: 0x0090, // ER90 display memory control
700: 0x0391, // ER91 CRT-circular buffer policy select
701: 0x0a95, // ER95 CRT-circular buffer delta & burst
702: 0x0096, // ER96 display memory control test
703: 0x12a0, // ERa0 bus interface unit control
704: 0x00a1, // ERa1 three-state and test control
705: 0x00c8, // ERc8 RAMDAC control
706:
707: IB, // prepare atc for writing
708: INPUT_STATUS_1_COLOR,
709:
710: METAOUT+ATCOUT, //
711: ATT_ADDRESS_PORT, // port
712: VGA_NUM_ATTRIB_CONT_PORTS, // count
713: 0, // start index
714: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
715: 0x04,0x0,0x0F,0x8,0x0,
716:
717: METAOUT+INDXOUT, //
718: GRAPH_ADDRESS_PORT, // port
719: VGA_NUM_GRAPH_CONT_PORTS, // count
720: 0, // start index
721: 0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
722:
723: OB, // turn video on.
724: ATT_ADDRESS_PORT,
725: VIDEO_ENABLE,
726:
727: #endif
728: // disable banking
729: OWM,
730: GRAPH_ADDRESS_PORT,
731: 3,
732: 0x030d, // ER0D = Paging control: 1 64K page,
733: 0x000e, // ER0E page A address = 0
734: 0x000f, // ER0F page B address = 0
735:
736: OB,
737: DAC_PIXEL_MASK_PORT,
738: 0xFF,
739:
740: EOD
741: };
742:
743:
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