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1.1 root 1: /*++
2:
3: Copyright (c) 1992 Cirrus Logic, Inc.
4:
5: Module Name:
6:
7: Mode6420.h
8:
9: Abstract:
10:
11: This module contains all the global data used by the Cirrus Logic
12: CL-6420 driver.
13:
14: Environment:
15:
16: Kernel mode
17:
18: Revision History:
19:
20: --*/
21:
22: //---------------------------------------------------------------------------
23: // The next set of tables are for the CL6420
24: // Note: all resolutions supported
25: //
26: USHORT CL6420_640x480_panel[] = {
27: // Unlock Key for color mode
28: OW, // GR0A = 0xEC opens extension registers
29: GRAPH_ADDRESS_PORT,
30: 0xec0a,
31:
32: #ifndef INT10_MODE_SET
33: OWM,
34: SEQ_ADDRESS_PORT,
35: 5,
36: 0x0100, // start synch reset
37: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
38:
39:
40: OB,
41: MISC_OUTPUT_REG_WRITE_PORT,
42: 0xe3,
43:
44: OW, //{ SetGraphCmd,{ "\x05", 0x06, 1 } },
45: GRAPH_ADDRESS_PORT,
46: 0x0506,
47:
48: // EndSyncResetCmd
49: OW,
50: SEQ_ADDRESS_PORT,
51: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
52:
53: OW,
54: CRTC_ADDRESS_PORT_COLOR,
55: 0x0111,
56:
57: METAOUT+INDXOUT, // program crtc registers
58: CRTC_ADDRESS_PORT_COLOR,
59: VGA_NUM_CRTC_PORTS, // count
60: 0, // start index
61: 0x5F,0x4F,0x50,0x82,
62: 0x54,0x80,0x0B,0x3E,
63: 0x00,0x40,0x00,0x00,
64: 0x00,0x00,0x00,0x00,
65: 0xEA,0xAC,0xDF,0x28,
66: 0x00,0xE7,0x04,0xE3,
67: 0xFF,
68:
69: // extension registers
70: OWM,
71: GRAPH_ADDRESS_PORT,
72: 16,
73: 0x0262, // ER62 horz. display end extension
74: 0x8064, // ER64 horz. retrace end extension
75: 0x0079, // ER79 vertical overflow
76: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
77: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
78: 0x007c, // ER7c screen A start addr. extension
79: 0x0181, // ER81 display mode
80: 0x8982, // ER82 character clock selection
81: 0x9a84, // ER84 clock select extension
82: 0x0090, // ER90 display memory control
83: 0x0091, // ER91 CRT-circular buffer policy select
84: 0x0095, // ER95 CRT-circular buffer delta & burst
85: 0x0096, // ER96 display memory control test
86: 0x12a0, // ERa0 bus interface unit control
87: 0x00a1, // ERa1 three-state and test control
88: 0xa1c8, // ERc8 RAMDAC control
89:
90: IB, // prepare atc for writing
91: INPUT_STATUS_1_COLOR,
92:
93: METAOUT+ATCOUT, //
94: ATT_ADDRESS_PORT, // port
95: VGA_NUM_ATTRIB_CONT_PORTS, // count
96: 0, // start index
97: 0x00,0x01,0x02,0x03,0x04,
98: 0x05,0x14,0x07,0x38,0x39,
99: 0x3A,0x3B,0x3C,0x3D,0x3E,
100: 0x3F,0x01,0x00,0x0F,0x00,0x00,
101:
102: METAOUT+INDXOUT, //
103: GRAPH_ADDRESS_PORT, // port
104: VGA_NUM_GRAPH_CONT_PORTS, // count
105: 0, // start index
106: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
107:
108: OB, // turn video on.
109: ATT_ADDRESS_PORT,
110: VIDEO_ENABLE,
111:
112: #endif
113: // zero out the banking regs. for this mode
114: OWM,
115: GRAPH_ADDRESS_PORT,
116: 3,
117: 0x000d, // ER0D = Banking control: 1 64K bank,
118: 0x000e, // ER0E bank A address = 0
119: 0x000f, // ER0F bank B address = 0
120:
121: OB,
122: DAC_PIXEL_MASK_PORT,
123: 0xFF,
124:
125:
126: EOD
127: };
128: USHORT CL6420_640x480_crt[] = {
129: // Unlock Key for color mode
130: OW, // GR0A = 0xEC opens extension registers
131: GRAPH_ADDRESS_PORT,
132: 0xec0a,
133:
134: #ifndef INT10_MODE_SET
135: OWM,
136: SEQ_ADDRESS_PORT,
137: 5,
138: 0x0100, // start synch reset
139: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
140:
141:
142: OB,
143: MISC_OUTPUT_REG_WRITE_PORT,
144: 0xe3,
145:
146: OW, //{ SetGraphCmd,{ "\x05", 0x06, 1 } },
147: GRAPH_ADDRESS_PORT,
148: 0x0506,
149:
150: // EndSyncResetCmd
151: OW,
152: SEQ_ADDRESS_PORT,
153: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
154:
155: OW,
156: CRTC_ADDRESS_PORT_COLOR,
157: 0x0111,
158:
159: METAOUT+INDXOUT, // program crtc registers
160: CRTC_ADDRESS_PORT_COLOR,
161: VGA_NUM_CRTC_PORTS, // count
162: 0, // start index
163: 0x5F,0x4F,0x50,0x82,
164: 0x54,0x80,0x0B,0x3E,
165: 0x00,0x40,0x00,0x00,
166: 0x00,0x00,0x00,0x00,
167: 0xEA,0xAC,0xDF,0x28,
168: 0x00,0xE7,0x04,0xE3,
169: 0xFF,
170:
171: // extension registers
172: OWM,
173: GRAPH_ADDRESS_PORT,
174: 16,
175: 0x0262, // ER62 horz. display end extension
176: 0x8064, // ER64 horz. retrace end extension
177: 0x0079, // ER79 vertical overflow
178: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
179: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
180: 0x007c, // ER7c screen A start addr. extension
181: 0x0081, // ER81 display mode
182: 0x0082, // ER82 character clock selection
183: 0x1084, // ER84 clock select extension
184: 0x0090, // ER90 display memory control
185: 0x0091, // ER91 CRT-circular buffer policy select
186: 0x0095, // ER95 CRT-circular buffer delta & burst
187: 0x0096, // ER96 display memory control test
188: 0x12a0, // ERa0 bus interface unit control
189: 0x00a1, // ERa1 three-state and test control
190: 0x00c8, // ERc8 RAMDAC control
191:
192: IB, // prepare atc for writing
193: INPUT_STATUS_1_COLOR,
194:
195: METAOUT+ATCOUT, //
196: ATT_ADDRESS_PORT, // port
197: VGA_NUM_ATTRIB_CONT_PORTS, // count
198: 0, // start index
199: 0x00,0x01,0x02,0x03,0x04,
200: 0x05,0x14,0x07,0x38,0x39,
201: 0x3A,0x3B,0x3C,0x3D,0x3E,
202: 0x3F,0x01,0x00,0x0F,0x00,0x00,
203:
204: METAOUT+INDXOUT, //
205: GRAPH_ADDRESS_PORT, // port
206: VGA_NUM_GRAPH_CONT_PORTS, // count
207: 0, // start index
208: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
209:
210: OB, // turn video on.
211: ATT_ADDRESS_PORT,
212: VIDEO_ENABLE,
213:
214: #endif
215: // zero out the banking regs. for this mode
216: OWM,
217: GRAPH_ADDRESS_PORT,
218: 3,
219: 0x000d, // ER0D = Banking control: 1 64K bank,
220: 0x000e, // ER0E bank A address = 0
221: 0x000f, // ER0F bank B address = 0
222:
223: OB,
224: DAC_PIXEL_MASK_PORT,
225: 0xFF,
226:
227: EOD
228: };
229:
230:
231: //
232: // 800x600 16-color (60Hz refresh) mode set command string for CL 6420.
233: //
234: USHORT CL6420_800x600_crt[] = {
235: // Unlock Key for color mode
236: OW, // GR0A = 0xEC opens extension registers
237: GRAPH_ADDRESS_PORT,
238: 0xec0a,
239: #ifndef INT10_MODE_SET
240:
241: OWM,
242: SEQ_ADDRESS_PORT,
243: 5,
244: 0x0100, // start synch reset
245: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
246:
247:
248: OB,
249: MISC_OUTPUT_REG_WRITE_PORT,
250: 0xe3,
251:
252: OW,
253: GRAPH_ADDRESS_PORT,
254: 0x0506,
255:
256: // EndSyncResetCmd
257: OW,
258: SEQ_ADDRESS_PORT,
259: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
260:
261: OW,
262: CRTC_ADDRESS_PORT_COLOR,
263: 0x0E11,
264:
265: METAOUT+INDXOUT, // program crtc registers
266: CRTC_ADDRESS_PORT_COLOR,
267: VGA_NUM_CRTC_PORTS, // count
268: 0, // start index
269: 0x7F,0x63,0x64,0x82,
270: 0x6b,0x1d,0x72,0xf0,
271: 0x00,0x60,0x00,0x00,
272: 0x00,0x00,0x00,0x00,
273: 0x58,0xac,0x57,0x32,
274: 0x00,0x58,0x72,0xe3,
275: 0xFF,
276:
277: // extension registers
278: OWM,
279: GRAPH_ADDRESS_PORT,
280: 16,
281: 0x0262, // ER62 horz. display end extension
282: 0x1b64, // ER64 horz. retrace end extension
283: 0x0079, // ER79 vertical overflow
284: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
285: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
286: 0x007c, // ER7c screen A start addr. extension
287: 0x0081, // ER81 display mode
288: 0x0082, // ER82 character clock selection
289: 0x9c84, // ER84 clock select extension
290: 0x0090, // ER90 display memory control
291: 0x0391, // ER91 CRT-circular buffer policy select
292: 0x0395, // ER95 CRT-circular buffer delta & burst
293: 0x0096, // ER96 display memory control test
294: 0x12a0, // ERa0 bus interface unit control
295: 0x00a1, // ERa1 three-state and test control
296: 0x00c8, // ERc8 RAMDAC control
297:
298: IB, // prepare atc for writing
299: INPUT_STATUS_1_COLOR,
300:
301: METAOUT+ATCOUT, //
302: ATT_ADDRESS_PORT, // port
303: VGA_NUM_ATTRIB_CONT_PORTS, // count
304: 0, // start index
305: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
306: 0x01,0x0,0x0F,0x0,0x0,
307:
308: METAOUT+INDXOUT, //
309: GRAPH_ADDRESS_PORT, // port
310: VGA_NUM_GRAPH_CONT_PORTS, // count
311: 0, // start index
312: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
313:
314: OB, // turn video on.
315: ATT_ADDRESS_PORT,
316: VIDEO_ENABLE,
317:
318: #endif
319: // zero out the banking regs. for this mode
320: OWM,
321: GRAPH_ADDRESS_PORT,
322: 3,
323: 0x000d, // ER0D = Banking control: 1 64K bank,
324: 0x000e, // ER0E bank A address = 0
325: 0x000f, // ER0F bank B address = 0
326:
327: OB,
328: DAC_PIXEL_MASK_PORT,
329: 0xFF,
330:
331: EOD
332: };
333:
334: //
335: // 1024x768 16-color (60Hz refresh) mode set command string for CL 6420.
336: // Requires 512K minimum.
337: //
338: USHORT CL6420_1024x768_crt[] = {
339:
340: // Unlock Key for color mode
341: OW, // GR0A = 0xEC opens extension registers
342: GRAPH_ADDRESS_PORT,
343: 0xec0a,
344:
345: #ifndef INT10_MODE_SET
346: OWM,
347: SEQ_ADDRESS_PORT,
348: 5,
349: 0x0100, // start synch reset
350: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
351:
352:
353: OWM,
354: SEQ_ADDRESS_PORT,
355: 2,
356: 0x0006,0x0bc07, // program up sequencer
357:
358: OB,
359: MISC_OUTPUT_REG_WRITE_PORT,
360: 0x2b,
361:
362: OW,
363: GRAPH_ADDRESS_PORT,
364: 0x0506,
365:
366: // EndSyncResetCmd
367: OW,
368: SEQ_ADDRESS_PORT,
369: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
370:
371: OW,
372: CRTC_ADDRESS_PORT_COLOR,
373: 0x0E11,
374:
375: METAOUT+INDXOUT, // program crtc registers
376: CRTC_ADDRESS_PORT_COLOR,
377: VGA_NUM_CRTC_PORTS, // count
378: 0, // start index
379: 0x99,0x7f,0x80,0x9c,
380: 0x83,0x19,0x2f,0xfd,
381: 0x00,0x60,0x00,0x00,
382: 0x00,0x00,0x00,0x00,
383: 0x00,0xa4,0xff,0x3f,
384: 0x00,0x00,0x2f,0xe3,
385: 0xFF,
386: // extension registers
387: OWM,
388: GRAPH_ADDRESS_PORT,
389: 16,
390: 0x1c62, // ER62 horz. display end extension
391: 0x1964, // ER64 horz. retrace end extension
392: 0x0079, // ER79 vertical overflow
393: 0x4c7a, // ER7a coarse vert. retrace skew for interlaced odd fields
394: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
395: 0x007c, // ER7c screen A start addr. extension
396: 0x0481, // ER81 display mode
397: 0x0082, // ER82 character clock selection
398: 0xa084, // ER84 clock select extension
399: 0x0090, // ER90 display memory control
400: 0x8391, // ER91 CRT-circular buffer policy select
401: 0x0295, // ER95 CRT-circular buffer delta & burst
402: 0x0096, // ER96 display memory control test
403: 0x12a0, // ERa0 bus interface unit control
404: 0x00a1, // ERa1 three-state and test control
405: 0x00c8, // ERc8 RAMDAC control
406:
407: OB,
408: DAC_PIXEL_MASK_PORT,
409: 0xFF,
410:
411: IB, // prepare atc for writing
412: INPUT_STATUS_1_COLOR,
413:
414: METAOUT+ATCOUT, //
415: ATT_ADDRESS_PORT, // port
416: VGA_NUM_ATTRIB_CONT_PORTS, // count
417: 0, // start index
418: 0x00,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
419: 0x01,0x00,0x0F,0x00,0x00,
420:
421: METAOUT+INDXOUT, //
422: GRAPH_ADDRESS_PORT, // port
423: VGA_NUM_GRAPH_CONT_PORTS, // count
424: 0, // start index
425: 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0x0FF,
426:
427: OB, // turn video on.
428: ATT_ADDRESS_PORT,
429: VIDEO_ENABLE,
430:
431: #endif
432: // now do the banking registers
433: OWM,
434: GRAPH_ADDRESS_PORT,
435: 3,
436: #if ONE_64K_BANK
437: 0x030d, // ER0D = Banking control: 1 64K bank,
438: #endif
439: #if TWO_32K_BANKS
440: 0x050d,
441: #endif
442: 0x000e, // ER0E bank A address = 0
443: 0x000f, // ER0F bank B address = 0
444:
445: OB,
446: DAC_PIXEL_MASK_PORT,
447: 0xFF,
448:
449: EOD
450: };
451:
452: //-----------------------------
453: // standard VGA text modes here
454: // 80x25 at 640x350
455: //
456: //-----------------------------
457:
458: USHORT CL6420_80x25_14_Text_crt[] = {
459: // Unlock Key for color mode
460: OW, // GR0A = 0xEC opens extension registers
461: GRAPH_ADDRESS_PORT,
462: 0xec0a,
463:
464: #ifndef INT10_MODE_SET
465: OWM,
466: SEQ_ADDRESS_PORT,
467: 5,
468: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
469:
470: OB,
471: MISC_OUTPUT_REG_WRITE_PORT,
472: 0x67,
473:
474: OW,
475: GRAPH_ADDRESS_PORT,
476: 0x0e06,
477:
478: // EndSyncResetCmd
479: OW,
480: SEQ_ADDRESS_PORT,
481: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
482:
483: OW,
484: CRTC_ADDRESS_PORT_COLOR,
485: 0x0511,
486:
487: METAOUT+INDXOUT, // program crtc registers
488: CRTC_ADDRESS_PORT_COLOR,
489: VGA_NUM_CRTC_PORTS, // count
490: 0, // start index
491: 0x5F,0x4f,0x50,0x82,
492: 0x55,0x81,0xbf,0x1f,
493: 0x00,0x4f,0x0d,0x0e,
494: 0x00,0x00,0x01,0xe0,
495: 0x9c,0xae,0x8f,0x28,
496: 0x1f,0x96,0xb9,0xa3,
497: 0xFF,
498:
499: // extension registers
500: OWM,
501: GRAPH_ADDRESS_PORT,
502: 16,
503: 0x0262, // ER62 horz. display end extension
504: 0x8164, // ER64 horz. retrace end extension
505: 0x0079, // ER79 vertical overflow
506: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
507: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
508: 0x007c, // ER7c screen A start addr. extension
509: 0x0081, // ER81 display mode
510: 0x0082, // ER82 character clock selection
511: 0x1084, // ER84 clock select extension
512: 0x0090, // ER90 display memory control
513: 0x0091, // ER91 CRT-circular buffer policy select
514: 0x0095, // ER95 CRT-circular buffer delta & burst
515: 0x0096, // ER96 display memory control test
516: 0x12a0, // ERa0 bus interface unit control
517: 0x00a1, // ERa1 three-state and test control
518: 0x00c8, // ERc8 RAMDAC control
519:
520: IB, // prepare atc for writing
521: INPUT_STATUS_1_COLOR,
522:
523: METAOUT+ATCOUT, //
524: ATT_ADDRESS_PORT, // port
525: VGA_NUM_ATTRIB_CONT_PORTS, // count
526: 0, // start index
527: 0x00,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
528: 0x00,0x00,0x0F,0x00,0x00,
529:
530: METAOUT+INDXOUT, //
531: GRAPH_ADDRESS_PORT, // port
532: VGA_NUM_GRAPH_CONT_PORTS, // count
533: 0, // start index
534: 0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,0x0FF,
535:
536: OB, // turn video on.
537: ATT_ADDRESS_PORT,
538: VIDEO_ENABLE,
539:
540: #endif
541: // zero out the banking regs. for this mode
542: OWM,
543: GRAPH_ADDRESS_PORT,
544: 3,
545: 0x000d, // ER0D = Banking control: 1 64K bank,
546: 0x000e, // ER0E bank A address = 0
547: 0x000f, // ER0F bank B address = 0
548:
549: OB,
550: DAC_PIXEL_MASK_PORT,
551: 0xFF,
552:
553: EOD
554: };
555: //
556: USHORT CL6420_80x25_14_Text_panel[] = {
557: // Unlock Key for color mode
558: OW, // GR0A = 0xEC opens extension registers
559: GRAPH_ADDRESS_PORT,
560: 0xec0a,
561:
562: #ifndef INT10_MODE_SET
563: OWM,
564: SEQ_ADDRESS_PORT,
565: 5,
566: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
567:
568: OB,
569: MISC_OUTPUT_REG_WRITE_PORT,
570: 0x67,
571:
572: OW,
573: GRAPH_ADDRESS_PORT,
574: 0x0e06,
575:
576: // EndSyncResetCmd
577: OW,
578: SEQ_ADDRESS_PORT,
579: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
580:
581: OW,
582: CRTC_ADDRESS_PORT_COLOR,
583: 0x0511,
584:
585: METAOUT+INDXOUT, // program crtc registers
586: CRTC_ADDRESS_PORT_COLOR,
587: VGA_NUM_CRTC_PORTS, // count
588: 0, // start index
589: 0x5F,0x4f,0x50,0x82,
590: 0x55,0x81,0xbf,0x1f,
591: 0x00,0x4f,0x0d,0x0e,
592: 0x00,0x00,0x01,0xe0,
593: 0x9c,0xae,0x8f,0x28,
594: 0x1f,0x96,0xb9,0xa3,
595: 0xFF,
596:
597: // extension registers
598: OWM,
599: GRAPH_ADDRESS_PORT,
600: 16,
601: 0x0262, // ER62 horz. display end extension
602: 0x8164, // ER64 horz. retrace end extension
603: 0x0079, // ER79 vertical overflow
604: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
605: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
606: 0x007c, // ER7c screen A start addr. extension
607: 0x0181, // ER81 display mode
608: 0x8982, // ER82 character clock selection
609: 0x9a84, // ER84 clock select extension
610: 0x0090, // ER90 display memory control
611: 0x0091, // ER91 CRT-circular buffer policy select
612: 0x0095, // ER95 CRT-circular buffer delta & burst
613: 0x0096, // ER96 display memory control test
614: 0x12a0, // ERa0 bus interface unit control
615: 0x00a1, // ERa1 three-state and test control
616: 0xa1c8, // ERc8 RAMDAC control
617:
618: IB, // prepare atc for writing
619: INPUT_STATUS_1_COLOR,
620:
621: METAOUT+ATCOUT, //
622: ATT_ADDRESS_PORT, // port
623: VGA_NUM_ATTRIB_CONT_PORTS, // count
624: 0, // start index
625: 0x00,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
626: 0x00,0x00,0x0F,0x00,0x00,
627:
628: METAOUT+INDXOUT, //
629: GRAPH_ADDRESS_PORT, // port
630: VGA_NUM_GRAPH_CONT_PORTS, // count
631: 0, // start index
632: 0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,0x0FF,
633:
634: OB, // turn video on.
635: ATT_ADDRESS_PORT,
636: VIDEO_ENABLE,
637:
638: #endif
639: // zero out the banking regs. for this mode
640: OWM,
641: GRAPH_ADDRESS_PORT,
642: 3,
643: 0x000d, // ER0D = Banking control: 1 64K bank,
644: 0x000e, // ER0E bank A address = 0
645: 0x000f, // ER0F bank B address = 0
646:
647: OB,
648: DAC_PIXEL_MASK_PORT,
649: 0xFF,
650:
651: EOD
652: };
653: //
654:
655:
656: USHORT CL6420_80x25Text_crt[] = {
657: // Unlock Key for color mode
658: OW, // GR0A = 0xEC opens extension registers
659: GRAPH_ADDRESS_PORT,
660: 0xec0a,
661:
662: #ifndef INT10_MODE_SET
663: OWM,
664: SEQ_ADDRESS_PORT,
665: 5,
666: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
667:
668: OWM,
669: SEQ_ADDRESS_PORT,
670: 2,
671: 0x0006,0x0fc07, // program up sequencer
672:
673: OB,
674: MISC_OUTPUT_REG_WRITE_PORT,
675: 0x67,
676:
677: OW,
678: GRAPH_ADDRESS_PORT,
679: 0x0e06,
680:
681: // EndSyncResetCmd
682: OW,
683: SEQ_ADDRESS_PORT,
684: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
685:
686: OW,
687: CRTC_ADDRESS_PORT_COLOR,
688: 0x0E11,
689:
690: METAOUT+INDXOUT, // program crtc registers
691: CRTC_ADDRESS_PORT_COLOR,
692: VGA_NUM_CRTC_PORTS, // count
693: 0, // start index
694: 0x5F,0x4f,0x50,0x82,
695: 0x55,0x81,0xbf,0x1f,
696: 0x00,0x4f,0x0d,0x0e,
697: 0x00,0x00,0x00,0x00,
698: 0x9c,0x8e,0x8f,0x28,
699: 0x1f,0x96,0xb9,0xa3,
700: 0xFF,
701:
702: // extension registers
703: OWM,
704: GRAPH_ADDRESS_PORT,
705: 16,
706: 0x0262, // ER62 horz. display end extension
707: 0x8164, // ER64 horz. retrace end extension
708: 0x0079, // ER79 vertical overflow
709: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
710: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
711: 0x007c, // ER7c screen A start addr. extension
712: 0x0081, // ER81 display mode
713: 0x8082, // ER82 character clock selection
714: 0x1084, // ER84 clock select extension
715: 0x0090, // ER90 display memory control
716: 0x0091, // ER91 CRT-circular buffer policy select
717: 0x0095, // ER95 CRT-circular buffer delta & burst
718: 0x0096, // ER96 display memory control test
719: 0x12a0, // ERa0 bus interface unit control
720: 0x00a1, // ERa1 three-state and test control
721: 0x00c8, // ERc8 RAMDAC control
722:
723: IB, // prepare atc for writing
724: INPUT_STATUS_1_COLOR,
725:
726: METAOUT+ATCOUT, //
727: ATT_ADDRESS_PORT, // port
728: VGA_NUM_ATTRIB_CONT_PORTS, // count
729: 0, // start index
730: 0x00,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
731: 0x04,0x00,0x0F,0x8,0x00,
732:
733: METAOUT+INDXOUT, //
734: GRAPH_ADDRESS_PORT, // port
735: VGA_NUM_GRAPH_CONT_PORTS, // count
736: 0, // start index
737: 0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,0x0FF,
738:
739: OB, // turn video on.
740: ATT_ADDRESS_PORT,
741: VIDEO_ENABLE,
742:
743: #endif
744: // zero out the banking regs. for this mode
745: OWM,
746: GRAPH_ADDRESS_PORT,
747: 3,
748: 0x000d, // ER0D = Banking control: 1 64K bank,
749: 0x000e, // ER0E bank A address = 0
750: 0x000f, // ER0F bank B address = 0
751:
752: OB,
753: DAC_PIXEL_MASK_PORT,
754: 0xFF,
755:
756: EOD
757: };
758:
759: USHORT CL6420_80x25Text_panel[] = {
760: // Unlock Key for color mode
761: OW, // GR0A = 0xEC opens extension registers
762: GRAPH_ADDRESS_PORT,
763: 0xec0a,
764:
765: #ifndef INT10_MODE_SET
766: OWM,
767: SEQ_ADDRESS_PORT,
768: 5,
769: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
770:
771: OWM,
772: SEQ_ADDRESS_PORT,
773: 2,
774: 0x0006,0x0fc07, // program up sequencer
775:
776: OB,
777: MISC_OUTPUT_REG_WRITE_PORT,
778: 0x67,
779:
780: OW,
781: GRAPH_ADDRESS_PORT,
782: 0x0e06,
783:
784: // EndSyncResetCmd
785: OW,
786: SEQ_ADDRESS_PORT,
787: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
788:
789: OW,
790: CRTC_ADDRESS_PORT_COLOR,
791: 0x0E11,
792:
793: METAOUT+INDXOUT, // program crtc registers
794: CRTC_ADDRESS_PORT_COLOR,
795: VGA_NUM_CRTC_PORTS, // count
796: 0, // start index
797: 0x5F,0x4f,0x50,0x82,
798: 0x55,0x81,0xbf,0x1f,
799: 0x00,0x4f,0x0d,0x0e,
800: 0x00,0x00,0x00,0x00,
801: 0x9c,0xae,0x8f,0x28,
802: 0x1f,0x96,0xb9,0xa3,
803: 0xFF,
804:
805: // extension registers
806: OWM,
807: GRAPH_ADDRESS_PORT,
808: 16,
809: 0x0262, // ER62 horz. display end extension
810: 0x8164, // ER64 horz. retrace end extension
811: 0x0079, // ER79 vertical overflow
812: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
813: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
814: 0x007c, // ER7c screen A start addr. extension
815: 0x0181, // ER81 display mode
816: 0x8982, // ER82 character clock selection
817: 0x9a84, // ER84 clock select extension
818: 0x0090, // ER90 display memory control
819: 0x0091, // ER91 CRT-circular buffer policy select
820: 0x0095, // ER95 CRT-circular buffer delta & burst
821: 0x0096, // ER96 display memory control test
822: 0x12a0, // ERa0 bus interface unit control
823: 0x00a1, // ERa1 three-state and test control
824: 0xa1c8, // ERc8 RAMDAC control
825:
826: IB, // prepare atc for writing
827: INPUT_STATUS_1_COLOR,
828:
829: METAOUT+ATCOUT, //
830: ATT_ADDRESS_PORT, // port
831: VGA_NUM_ATTRIB_CONT_PORTS, // count
832: 0, // start index
833: 0x00,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
834: 0x04,0x00,0x0F,0x8,0x00,
835:
836: METAOUT+INDXOUT, //
837: GRAPH_ADDRESS_PORT, // port
838: VGA_NUM_GRAPH_CONT_PORTS, // count
839: 0, // start index
840: 0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,0x0FF,
841:
842: OB, // turn video on.
843: ATT_ADDRESS_PORT,
844: VIDEO_ENABLE,
845:
846: #endif
847: // zero out the banking regs. for this mode
848: OWM,
849: GRAPH_ADDRESS_PORT,
850: 3,
851: 0x000d, // ER0D = Banking control: 1 64K bank,
852: 0x000e, // ER0E bank A address = 0
853: 0x000f, // ER0F bank B address = 0
854:
855: OB,
856: DAC_PIXEL_MASK_PORT,
857: 0xFF,
858:
859: EOD
860: };
861:
862:
863: //
864: //---------------------------------------------------------------------------
865: // 256 color tables
866: //---------------------------------------------------------------------------
867: //
868: // 800x600 256-color (60Hz refresh) mode set command string for CL 6420.
869: // requires 512k minimum
870: //
871: USHORT CL6420_640x480_256color_crt[] = {
872: // Unlock Key for color mode
873: OW, // GR0A = 0xEC opens extension registers
874: GRAPH_ADDRESS_PORT,
875: 0xec0a,
876:
877: #ifndef INT10_MODE_SET
878: OWM,
879: SEQ_ADDRESS_PORT,
880: 5,
881: 0x0100, // start synch reset
882: 0x0101,0x0f02,0x0003,0x0e04, // program up sequencer
883:
884:
885: OB,
886: MISC_OUTPUT_REG_WRITE_PORT,
887: 0xe3,
888:
889: OW, //{ SetGraphCmd,{ "\x05", 0x06, 1 } },
890: GRAPH_ADDRESS_PORT,
891: 0x0506,
892:
893: // EndSyncResetCmd
894: OW,
895: SEQ_ADDRESS_PORT,
896: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
897:
898: OW,
899: CRTC_ADDRESS_PORT_COLOR,
900: 0x0111,
901:
902: METAOUT+INDXOUT, // program crtc registers
903: CRTC_ADDRESS_PORT_COLOR,
904: VGA_NUM_CRTC_PORTS, // count
905: 0, // start index
906: 0xc3,0x9F,0xa0,0x86,
907: 0xa4,0x10,0x0B,0x3E,
908: 0x00,0x40,0x00,0x00,
909: 0x00,0x00,0x00,0x00,
910: 0xEA,0xAC,0xDF,0x50,
911: 0x00,0xE7,0x04,0xE3,
912: 0xFF,
913:
914: // extension registers
915: OWM,
916: GRAPH_ADDRESS_PORT,
917: 16,
918: 0x2662, // ER62 horz. display end extension
919: 0x1064, // ER64 horz. retrace end extension
920: 0x0079, // ER79 vertical overflow
921: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
922: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
923: 0x007c, // ER7c screen A start addr. extension
924: 0x0081, // ER81 display mode
925: 0x0a82, // ER82 character clock selection
926: 0x1084, // ER84 clock select extension
927: 0x0090, // ER90 display memory control
928: 0x0391, // ER91 CRT-circular buffer policy select
929: 0x0895, // ER95 CRT-circular buffer delta & burst
930: 0x0096, // ER96 display memory control test
931: 0x12a0, // ERa0 bus interface unit control
932: 0x20a1, // ERa1 three-state and test control
933: 0x05c8, // ERc8 RAMDAC control
934:
935: IB, // prepare atc for writing
936: INPUT_STATUS_1_COLOR,
937:
938: METAOUT+ATCOUT, //
939: ATT_ADDRESS_PORT, // port
940: VGA_NUM_ATTRIB_CONT_PORTS, // count
941: 0, // start index
942: 0x00,0x01,0x02,0x03,0x04,
943: 0x05,0x06,0x07,0x08,0x09,
944: 0x0A,0x0B,0x0C,0x0D,0x0E,
945: 0x0F,0x01,0x00,0x0F,0x00,0x00,
946:
947: METAOUT+INDXOUT, //
948: GRAPH_ADDRESS_PORT, // port
949: VGA_NUM_GRAPH_CONT_PORTS, // count
950: 0, // start index
951: 0x00,0x0,0x0,0x0,0x0,0x40,0x05,0x0F,0x0FF,
952:
953: OB, // turn video on.
954: ATT_ADDRESS_PORT,
955: VIDEO_ENABLE,
956:
957: #endif
958: // now do the banking registers
959: OWM,
960: GRAPH_ADDRESS_PORT,
961: 3,
962: #if ONE_64K_BANK
963: 0x030d, // ER0D = Banking control: 1 64K bank,
964: #endif
965: #if TWO_32K_BANKS
966: 0x050d,
967: #endif
968: 0x000e, // ER0E bank A address = 0
969: 0x000f, // ER0F bank B address = 0
970:
971: OB,
972: DAC_PIXEL_MASK_PORT,
973: 0xFF,
974:
975: EOD
976: };
977:
978: USHORT CL6420_640x480_256color_panel[] = {
979: // Unlock Key for color mode
980: OW, // GR0A = 0xEC opens extension registers
981: GRAPH_ADDRESS_PORT,
982: 0xec0a,
983:
984: #ifndef INT10_MODE_SET
985: OWM,
986: SEQ_ADDRESS_PORT,
987: 5,
988: 0x0100, // start synch reset
989: 0x0101,0x0f02,0x0003,0x0e04, // program up sequencer
990:
991:
992: OB,
993: MISC_OUTPUT_REG_WRITE_PORT,
994: 0xe3,
995:
996: OW, //{ SetGraphCmd,{ "\x05", 0x06, 1 } },
997: GRAPH_ADDRESS_PORT,
998: 0x0506,
999:
1000: // EndSyncResetCmd
1001: OW,
1002: SEQ_ADDRESS_PORT,
1003: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
1004:
1005: OW,
1006: CRTC_ADDRESS_PORT_COLOR,
1007: 0x0111,
1008:
1009: METAOUT+INDXOUT, // program crtc registers
1010: CRTC_ADDRESS_PORT_COLOR,
1011: VGA_NUM_CRTC_PORTS, // count
1012: 0, // start index
1013: 0xc3,0x9F,0xa0,0x86,
1014: 0xa4,0x10,0x0B,0x3E,
1015: 0x00,0x40,0x00,0x00,
1016: 0x00,0x00,0x00,0x00,
1017: 0xEA,0xAC,0xDF,0x50,
1018: 0x00,0xE7,0x04,0xE3,
1019: 0xFF,
1020:
1021: // extension registers
1022: OWM,
1023: GRAPH_ADDRESS_PORT,
1024: 16,
1025: 0x2662, // ER62 horz. display end extension
1026: 0x1064, // ER64 horz. retrace end extension
1027: 0x0079, // ER79 vertical overflow
1028: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
1029: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
1030: 0x007c, // ER7c screen A start addr. extension
1031: 0x0181, // ER81 display mode
1032: 0x8a82, // ER82 character clock selection
1033: 0x9a84, // ER84 clock select extension
1034: 0x0090, // ER90 display memory control
1035: 0x0391, // ER91 CRT-circular buffer policy select
1036: 0x0895, // ER95 CRT-circular buffer delta & burst
1037: 0x0096, // ER96 display memory control test
1038: 0x12a0, // ERa0 bus interface unit control
1039: 0x20a1, // ERa1 three-state and test control
1040: 0xa5c8, // ERc8 RAMDAC control
1041:
1042: IB, // prepare atc for writing
1043: INPUT_STATUS_1_COLOR,
1044:
1045: METAOUT+ATCOUT, //
1046: ATT_ADDRESS_PORT, // port
1047: VGA_NUM_ATTRIB_CONT_PORTS, // count
1048: 0, // start index
1049: 0x00,0x01,0x02,0x03,0x04,
1050: 0x05,0x06,0x07,0x08,0x09,
1051: 0x0A,0x0B,0x0C,0x0D,0x0E,
1052: 0x0F,0x01,0x00,0x0F,0x00,0x00,
1053:
1054: METAOUT+INDXOUT, //
1055: GRAPH_ADDRESS_PORT, // port
1056: VGA_NUM_GRAPH_CONT_PORTS, // count
1057: 0, // start index
1058: 0x00,0x0,0x0,0x0,0x0,0x40,0x05,0x0F,0x0FF,
1059:
1060: OB, // turn video on.
1061: ATT_ADDRESS_PORT,
1062: VIDEO_ENABLE,
1063:
1064: #endif
1065: // now do the banking registers
1066: OWM,
1067: GRAPH_ADDRESS_PORT,
1068: 3,
1069: #if ONE_64K_BANK
1070: 0x030d, // ER0D = Banking control: 1 64K bank,
1071: #endif
1072: #if TWO_32K_BANKS
1073: 0x050d,
1074: #endif
1075: 0x000e, // ER0E bank A address = 0
1076: 0x000f, // ER0F bank B address = 0
1077:
1078: OB,
1079: DAC_PIXEL_MASK_PORT,
1080: 0xFF,
1081:
1082: EOD
1083: };
1084:
1085: //
1086: // 800x600 256-color (60Hz refresh) mode set command string for CL 6420.
1087: // requires 512k minimum
1088: //
1089: USHORT CL6420_800x600_256color_crt[] = {
1090: // Unlock Key for color mode
1091: OW, // GR0A = 0xEC opens extension registers
1092: GRAPH_ADDRESS_PORT,
1093: 0xec0a,
1094:
1095: #ifndef INT10_MODE_SET
1096: OWM,
1097: SEQ_ADDRESS_PORT,
1098: 5,
1099: 0x0100, // start synch reset
1100: 0x0101,0x0f02,0x0003,0x0e04, // program up sequencer
1101:
1102:
1103: OB,
1104: MISC_OUTPUT_REG_WRITE_PORT,
1105: 0x2f,
1106:
1107: OW,
1108: GRAPH_ADDRESS_PORT,
1109: 0x0506,
1110:
1111: // EndSyncResetCmd
1112: OW,
1113: SEQ_ADDRESS_PORT,
1114: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
1115:
1116: OW,
1117: CRTC_ADDRESS_PORT_COLOR,
1118: 0x0E11,
1119:
1120: METAOUT+INDXOUT, // program crtc registers
1121: CRTC_ADDRESS_PORT_COLOR,
1122: VGA_NUM_CRTC_PORTS, // count
1123: 0, // start index
1124: 0x03,0xc7,0xc8,0x86,
1125: 0xdc,0x0c,0x72,0xf0,
1126: 0x00,0x60,0x00,0x00,
1127: 0x00,0x00,0x00,0x00,
1128: 0x5a,0xac,0x57,0x64,
1129: 0x00,0x58,0x72,0xe3,
1130: 0xFF,
1131:
1132: // extension registers
1133: OWM,
1134: GRAPH_ADDRESS_PORT,
1135: 16,
1136: 0x2662, // ER62 horz. display end extension
1137: 0x2c64, // ER64 horz. retrace end extension
1138: 0x0079, // ER79 vertical overflow
1139: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
1140: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
1141: 0x007c, // ER7c screen A start addr. extension
1142: 0x0081, // ER81 display mode
1143: 0x0a82, // ER82 character clock selection
1144: 0x9c84, // ER84 clock select extension
1145: 0x0090, // ER90 display memory control
1146: 0x0391, // ER91 CRT-circular buffer policy select
1147: 0x0895, // ER95 CRT-circular buffer delta & burst
1148: 0x0096, // ER96 display memory control test
1149: 0x12a0, // ERa0 bus interface unit control
1150: 0x20a1, // ERa1 three-state and test control
1151: 0x05c8, // ERc8 RAMDAC control
1152:
1153: IB, // prepare atc for writing
1154: INPUT_STATUS_1_COLOR,
1155:
1156: METAOUT+ATCOUT, //
1157: ATT_ADDRESS_PORT, // port
1158: VGA_NUM_ATTRIB_CONT_PORTS, // count
1159: 0, // start index
1160: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
1161: 0x01,0x0,0x0F,0x0,0x0,
1162:
1163: METAOUT+INDXOUT, //
1164: GRAPH_ADDRESS_PORT, // port
1165: VGA_NUM_GRAPH_CONT_PORTS, // count
1166: 0, // start index
1167: 0x00,0x0,0x0,0x0,0x0,0x40,0x05,0x0F,0x0FF,
1168:
1169: OB, // turn video on.
1170: ATT_ADDRESS_PORT,
1171: VIDEO_ENABLE,
1172:
1173: #endif
1174:
1175: // now do the banking registers
1176: OWM,
1177: GRAPH_ADDRESS_PORT,
1178: 3,
1179: #if ONE_64K_BANK
1180: 0x030d, // ER0D = Banking control: 1 64K bank,
1181: #endif
1182: #if TWO_32K_BANKS
1183: 0x050d,
1184: #endif
1185: 0x000e, // ER0E bank A address = 0
1186: 0x000f, // ER0F bank B address = 0
1187:
1188: OB,
1189: DAC_PIXEL_MASK_PORT,
1190: 0xFF,
1191:
1192: EOD
1193: };
1194:
1195: //
1196: // 1024x768 256-color (60Hz refresh) mode set command string for CL 6420.
1197: // Requires 1Meg minimum.
1198: //
1199: USHORT CL6420_1024x768_256color_crt[] = {
1200:
1201: // Unlock Key for color mode
1202: OW, // GR0A = 0xEC opens extension registers
1203: GRAPH_ADDRESS_PORT,
1204: 0xec0a,
1205:
1206: #ifndef INT10_MODE_SET
1207: OWM,
1208: SEQ_ADDRESS_PORT,
1209: 5,
1210: 0x0100, // start synch reset
1211: 0x0101,0x0f02,0x0003,0x0e04, // program up sequencer
1212:
1213: OB,
1214: MISC_OUTPUT_REG_WRITE_PORT,
1215: 0x23,
1216:
1217: OW,
1218: GRAPH_ADDRESS_PORT,
1219: 0x0506,
1220:
1221: // EndSyncResetCmd
1222: OW,
1223: SEQ_ADDRESS_PORT,
1224: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
1225:
1226: OW,
1227: CRTC_ADDRESS_PORT_COLOR,
1228: 0x0E11,
1229:
1230: METAOUT+INDXOUT, // program crtc registers
1231: CRTC_ADDRESS_PORT_COLOR,
1232: VGA_NUM_CRTC_PORTS, // count
1233: 0, // start index
1234: 0x39,0xff,0x00,0x9c,
1235: 0x06,0x91,0x26,0xfd,
1236: 0x00,0x60,0x00,0x00,
1237: 0x00,0x00,0x00,0x00,
1238: 0x04,0xa6,0xff,0x7f,
1239: 0x00,0x00,0x26,0xe3,
1240: 0xFF,
1241: // extension registers
1242: OWM,
1243: GRAPH_ADDRESS_PORT,
1244: 16,
1245: 0xbc62, // ER62 horz. display end extension
1246: 0xf164, // ER64 horz. retrace end extension
1247: 0x0079, // ER79 vertical overflow
1248: 0x997a, // ER7a coarse vert. retrace skew for interlaced odd fields
1249: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
1250: 0x007c, // ER7c screen A start addr. extension
1251: 0x0481, // ER81 display mode
1252: 0x0a82, // ER82 character clock selection
1253: 0xa084, // ER84 clock select extension
1254: 0x0090, // ER90 display memory control
1255: 0x0391, // ER91 CRT-circular buffer policy select
1256: 0x0895, // ER95 CRT-circular buffer delta & burst
1257: 0x0096, // ER96 display memory control test
1258: 0x12a0, // ERa0 bus interface unit control
1259: 0x20a1, // ERa1 three-state and test control
1260: 0x05c8, // ERc8 RAMDAC control
1261:
1262: IB, // prepare atc for writing
1263: INPUT_STATUS_1_COLOR,
1264:
1265: OB,
1266: DAC_PIXEL_MASK_PORT,
1267: 0xFF,
1268:
1269: METAOUT+ATCOUT, //
1270: ATT_ADDRESS_PORT, // port
1271: VGA_NUM_ATTRIB_CONT_PORTS, // count
1272: 0, // start index
1273: 0x00,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
1274: 0x01,0x00,0x0F,0x00,0x00,
1275:
1276: METAOUT+INDXOUT, //
1277: GRAPH_ADDRESS_PORT, // port
1278: VGA_NUM_GRAPH_CONT_PORTS, // count
1279: 0, // start index
1280: 0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0x0FF,
1281:
1282: OB, // turn video on.
1283: ATT_ADDRESS_PORT,
1284: VIDEO_ENABLE,
1285:
1286: #endif
1287: // now do the banking registers
1288: OWM,
1289: GRAPH_ADDRESS_PORT,
1290: 3,
1291: #if ONE_64K_BANK
1292: 0x030d, // ER0D = Banking control: 1 64K bank,
1293: #endif
1294: #if TWO_32K_BANKS
1295: 0x050d,
1296: #endif
1297: 0x000e, // ER0E bank A address = 0
1298: 0x000f, // ER0F bank B address = 0
1299:
1300: OB,
1301: DAC_PIXEL_MASK_PORT,
1302: 0xFF,
1303:
1304: EOD
1305: };
1306:
1307: #if MULTIPLE_REFRESH_TABLES
1308: //
1309: // 800x600 16-color (56Hz refresh) mode set command string for CL 6420.
1310: //
1311: USHORT CL6420_800x600_56Hz_crt[] = {
1312: #ifndef INT10_MODE_SET
1313: // Unlock Key for color mode
1314: OW, // GR0A = 0xEC opens extension registers
1315: GRAPH_ADDRESS_PORT,
1316: 0xec0a,
1317:
1318: OWM,
1319: SEQ_ADDRESS_PORT,
1320: 5,
1321: 0x0100, // start synch reset
1322: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
1323:
1324:
1325: OB,
1326: MISC_OUTPUT_REG_WRITE_PORT,
1327: 0xe3,
1328:
1329: OW,
1330: GRAPH_ADDRESS_PORT,
1331: 0x0506,
1332:
1333: // EndSyncResetCmd
1334: OW,
1335: SEQ_ADDRESS_PORT,
1336: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
1337:
1338: OW,
1339: CRTC_ADDRESS_PORT_COLOR,
1340: 0x0E11,
1341:
1342: METAOUT+INDXOUT, // program crtc registers
1343: CRTC_ADDRESS_PORT_COLOR,
1344: VGA_NUM_CRTC_PORTS, // count
1345: 0, // start index
1346: 0x7b,0x63,0x64,0x9e,
1347: 0x69,0x92,0x6f,0xf0,
1348: 0x00,0x60,0x00,0x00,
1349: 0x00,0x00,0x00,0x00,
1350: 0x58,0xaa,0x57,0x32,
1351: 0x00,0x58,0x6f,0xe3,
1352: 0xFF,
1353:
1354: // extension registers
1355: OWM,
1356: GRAPH_ADDRESS_PORT,
1357: 16,
1358: 0x1e62, // ER62 horz. display end extension
1359: 0x9264, // ER64 horz. retrace end extension
1360: 0x0079, // ER79 vertical overflow
1361: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
1362: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
1363: 0x007c, // ER7c screen A start addr. extension
1364: 0x0081, // ER81 display mode
1365: 0x0082, // ER82 character clock selection
1366: 0x8c84, // ER84 clock select extension
1367: 0x0090, // ER90 display memory control
1368: 0x8391, // ER91 CRT-circular buffer policy select
1369: 0x0395, // ER95 CRT-circular buffer delta & burst
1370: 0x0096, // ER96 display memory control test
1371: 0x12a0, // ERa0 bus interface unit control
1372: 0x00a1, // ERa1 three-state and test control
1373: 0x00c8, // ERc8 RAMDAC control
1374:
1375: // zero out the banking regs. for this mode
1376: OWM,
1377: GRAPH_ADDRESS_PORT,
1378: 3,
1379: 0x000d, // ER0D = Banking control: 1 64K bank,
1380: 0x000e, // ER0E bank A address = 0
1381: 0x000f, // ER0F bank B address = 0
1382:
1383: IB, // prepare atc for writing
1384: INPUT_STATUS_1_COLOR,
1385:
1386: METAOUT+ATCOUT, //
1387: ATT_ADDRESS_PORT, // port
1388: VGA_NUM_ATTRIB_CONT_PORTS, // count
1389: 0, // start index
1390: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
1391: 0x01,0x0,0x0F,0x0,0x0,
1392:
1393: METAOUT+INDXOUT, //
1394: GRAPH_ADDRESS_PORT, // port
1395: VGA_NUM_GRAPH_CONT_PORTS, // count
1396: 0, // start index
1397: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
1398:
1399: OB,
1400: DAC_PIXEL_MASK_PORT,
1401: 0xFF,
1402:
1403: OB, // turn video on.
1404: ATT_ADDRESS_PORT,
1405: VIDEO_ENABLE,
1406:
1407: #endif
1408: EOD
1409: };
1410:
1411: //
1412: // 800x600 16-color (72Hz refresh) mode set command string for CL 6420.
1413: //
1414: USHORT CL6420_800x600_72Hz_crt[] = {
1415: #ifndef INT10_MODE_SET
1416: // Unlock Key for color mode
1417: OW, // GR0A = 0xEC opens extension registers
1418: GRAPH_ADDRESS_PORT,
1419: 0xec0a,
1420:
1421: OWM,
1422: SEQ_ADDRESS_PORT,
1423: 5,
1424: 0x0100, // start synch reset
1425: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
1426:
1427:
1428: OB,
1429: MISC_OUTPUT_REG_WRITE_PORT,
1430: 0xe3,
1431:
1432: OW,
1433: GRAPH_ADDRESS_PORT,
1434: 0x0506,
1435:
1436: // EndSyncResetCmd
1437: OW,
1438: SEQ_ADDRESS_PORT,
1439: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
1440:
1441: OW,
1442: CRTC_ADDRESS_PORT_COLOR,
1443: 0x0E11,
1444:
1445: METAOUT+INDXOUT, // program crtc registers
1446: CRTC_ADDRESS_PORT_COLOR,
1447: VGA_NUM_CRTC_PORTS, // count
1448: 0, // start index
1449: 0x7f,0x63,0x64,0x82,
1450: 0x6b,0x1b,0x72,0xf0,
1451: 0x00,0x60,0x00,0x00,
1452: 0x00,0x00,0x00,0x00,
1453: 0x58,0xac,0x57,0x32,
1454: 0x00,0x58,0x72,0xe3,
1455: 0xFF,
1456:
1457: // extension registers
1458: OWM,
1459: GRAPH_ADDRESS_PORT,
1460: 16,
1461: 0x0262, // ER62 horz. display end extension
1462: 0x1b64, // ER64 horz. retrace end extension
1463: 0x0079, // ER79 vertical overflow
1464: 0x007a, // ER7a coarse vert. retrace skew for interlaced odd fields
1465: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
1466: 0x007c, // ER7c screen A start addr. extension
1467: 0x0081, // ER81 display mode
1468: 0x0082, // ER82 character clock selection
1469: 0x9c84, // ER84 clock select extension
1470: 0x0090, // ER90 display memory control
1471: 0x8391, // ER91 CRT-circular buffer policy select
1472: 0x0395, // ER95 CRT-circular buffer delta & burst
1473: 0x0096, // ER96 display memory control test
1474: 0x12a0, // ERa0 bus interface unit control
1475: 0x00a1, // ERa1 three-state and test control
1476: 0x00c8, // ERc8 RAMDAC control
1477:
1478: // zero out the banking regs. for this mode
1479: OWM,
1480: GRAPH_ADDRESS_PORT,
1481: 3,
1482: 0x000d, // ER0D = Banking control: 1 64K bank,
1483: 0x000e, // ER0E bank A address = 0
1484: 0x000f, // ER0F bank B address = 0
1485:
1486: IB, // prepare atc for writing
1487: INPUT_STATUS_1_COLOR,
1488:
1489: METAOUT+ATCOUT, //
1490: ATT_ADDRESS_PORT, // port
1491: VGA_NUM_ATTRIB_CONT_PORTS, // count
1492: 0, // start index
1493: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
1494: 0x01,0x0,0x0F,0x0,0x0,
1495:
1496: METAOUT+INDXOUT, //
1497: GRAPH_ADDRESS_PORT, // port
1498: VGA_NUM_GRAPH_CONT_PORTS, // count
1499: 0, // start index
1500: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
1501:
1502: OB,
1503: DAC_PIXEL_MASK_PORT,
1504: 0xFF,
1505:
1506: OB, // turn video on.
1507: ATT_ADDRESS_PORT,
1508: VIDEO_ENABLE,
1509:
1510: #endif
1511: EOD
1512: };
1513: //
1514: // 1024x768 16-color (43.5Hz refresh interlaced) mode set command string
1515: // for CL 6420.
1516: // Requires 512K minimum.
1517: //
1518: USHORT CL6420_1024x768_I43Hz_crt[] = {
1519:
1520: #ifndef INT10_MODE_SET
1521: // Unlock Key for color mode
1522: OW, // GR0A = 0xEC opens extension registers
1523: GRAPH_ADDRESS_PORT,
1524: 0xec0a,
1525:
1526: OWM,
1527: SEQ_ADDRESS_PORT,
1528: 5,
1529: 0x0100, // start synch reset
1530: 0x0101,0x0f02,0x0003,0x0604, // program up sequencer
1531:
1532:
1533: OWM,
1534: SEQ_ADDRESS_PORT,
1535: 2,
1536: 0x0006,0x0bc07, // program up sequencer
1537:
1538: OB,
1539: MISC_OUTPUT_REG_WRITE_PORT,
1540: 0x2b,
1541:
1542: OW,
1543: GRAPH_ADDRESS_PORT,
1544: 0x0506,
1545:
1546: // EndSyncResetCmd
1547: OW,
1548: SEQ_ADDRESS_PORT,
1549: IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8),
1550:
1551: OW,
1552: CRTC_ADDRESS_PORT_COLOR,
1553: 0x0E11,
1554:
1555: METAOUT+INDXOUT, // program crtc registers
1556: CRTC_ADDRESS_PORT_COLOR,
1557: VGA_NUM_CRTC_PORTS, // count
1558: 0, // start index
1559: 0x99,0x7f,0x80,0x9c,
1560: 0x83,0x19,0x2f,0xfd,
1561: 0x00,0x60,0x00,0x00,
1562: 0x00,0x00,0x00,0x00,
1563: 0x00,0xa4,0xff,0x3f,
1564: 0x00,0x00,0x2f,0xe3,
1565: 0xff,
1566: // extension registers
1567: OWM,
1568: GRAPH_ADDRESS_PORT,
1569: 16,
1570: 0x1c62, // ER62 horz. display end extension
1571: 0x1964, // ER64 horz. retrace end extension
1572: 0x0079, // ER79 vertical overflow
1573: 0x4c7a, // ER7a coarse vert. retrace skew for interlaced odd fields
1574: 0x007b, // ER7b fine vert. retrace skew for interlaced odd fields
1575: 0x007c, // ER7c screen A start addr. extension
1576: 0x0481, // ER81 display mode
1577: 0x0082, // ER82 character clock selection
1578: 0xa084, // ER84 clock select extension
1579: 0x0090, // ER90 display memory control
1580: 0x0391, // ER91 CRT-circular buffer policy select
1581: 0x0295, // ER95 CRT-circular buffer delta & burst
1582: 0x0096, // ER96 display memory control test
1583: 0x12a0, // ERa0 bus interface unit control
1584: 0x00a1, // ERa1 three-state and test control
1585: 0x00c8, // ERc8 RAMDAC control
1586:
1587: // now do the banking registers
1588: OWM,
1589: GRAPH_ADDRESS_PORT,
1590: 3,
1591: #if ONE_64K_BANK
1592: 0x030d, // ER0D = Banking control: 1 64K bank,
1593: #endif
1594: #if TWO_32K_BANKS
1595: 0x050d,
1596: #endif
1597: 0x000e, // ER0E bank A address = 0
1598: 0x000f, // ER0F bank B address = 0
1599:
1600: OB,
1601: DAC_PIXEL_MASK_PORT,
1602: 0xFF,
1603:
1604: IB, // prepare atc for writing
1605: INPUT_STATUS_1_COLOR,
1606:
1607: METAOUT+ATCOUT, //
1608: ATT_ADDRESS_PORT, // port
1609: VGA_NUM_ATTRIB_CONT_PORTS, // count
1610: 0, // start index
1611: 0x00,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
1612: 0x01,0x00,0x0F,0x00,0x00,
1613:
1614: METAOUT+INDXOUT, //
1615: GRAPH_ADDRESS_PORT, // port
1616: VGA_NUM_GRAPH_CONT_PORTS, // count
1617: 0, // start index
1618: 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0x0FF,
1619:
1620: OB,
1621: DAC_PIXEL_MASK_PORT,
1622: 0xFF,
1623:
1624: OB, // turn video on.
1625: ATT_ADDRESS_PORT,
1626: VIDEO_ENABLE,
1627:
1628: #endif
1629: EOD
1630: };
1631:
1632:
1633: #endif
1634:
1635:
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