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1.1 root 1: /*++
2:
3: Copyright (c) 1992 Microsoft Corporation
4:
5: Module Name:
6:
7: Modeset.h
8:
9: Abstract:
10:
11: This module contains all the global data used by the Tseng Labs
12: ET 4000 driver.
13:
14: Environment:
15:
16: Kernel mode
17:
18: Revision History:
19:
20: --*/
21:
22: //
23: // Define HZ70 for 70 Hz modes (currently, only 1024x768 16-color 70 Hz
24: // mode is supported). Undefine for 60 Hz modes.
25: //
26:
27: //
28: // Define "T9000" for 9022 support at 1024x768, 60 Hz.
29: // Define "PRODESIGNER_II" for 9022 support at 1024x768, 60 Hz.
30: // Defaults to T9000 if neither is defined.
31: //
32:
33: #include "cmdcnst.h"
34:
35: #ifndef INT10_MODE_SET
36:
37: //
38: // Mode index 14 Color graphics mode 0x12, 640x480 16 colors.
39: //
40: USHORT ET4000_640x480[] = {
41: // Unlock Key for color mode
42: OB,
43: HERCULES_COMPATIBILITY_PORT,
44: UNLOCK_KEY_1,
45:
46: OB,
47: MODE_CONTROL_PORT_COLOR,
48: UNLOCK_KEY_2,
49:
50: OWM,
51: SEQ_ADDRESS_PORT,
52: 5,
53: 0x0100,0x0101,0x0f02,0x0003,0x0604, // program up sequencer
54:
55: #ifndef PRODESIGNER_II
56: OWM,
57: SEQ_ADDRESS_PORT,
58: 2,
59: 0x0006,0x0fc07, // program up sequencer
60: #else
61: OWM,
62: SEQ_ADDRESS_PORT,
63: 2,
64: 0x0006,0x0bc07, // program up sequencer
65: #endif //PRODESIGNER_II
66:
67: OB,
68: MISC_OUTPUT_REG_WRITE_PORT,
69: 0xe3,
70:
71: METAOUT+INDXOUT,
72: CRTC_ADDRESS_PORT_COLOR, // reg
73: 6, // count
74: IND_RAS_CAS_CONFIG, // start index
75: 0x28, 0x00, 0x08, 0x00, 0x43, 0x1F,
76:
77: IB, // prepare atc for writing
78: INPUT_STATUS_1_COLOR,
79:
80: OB,
81: ATT_ADDRESS_PORT,
82: 0x16,
83:
84: OB,
85: ATT_ADDRESS_PORT,
86: 0x0,
87:
88: OW, //{ SetGraphCmd,{ "\x05", 0x06, 1 } },
89: GRAPH_ADDRESS_PORT,
90: 0x0506,
91:
92: // EndSyncResetCmd
93: OB,
94: SEQ_ADDRESS_PORT,
95: IND_SYNC_RESET,
96:
97: OB,
98: SEQ_DATA_PORT,
99: END_SYNC_RESET_VALUE,
100:
101: OW,
102: CRTC_ADDRESS_PORT_COLOR,
103: 0x0111,
104:
105: METAOUT+INDXOUT, // program crtc registers
106: CRTC_ADDRESS_PORT_COLOR,
107: VGA_NUM_CRTC_PORTS, // count
108: 0, // start index
109: 0x5F,0x4F,0x50,0x82,0x54,0x80,0x0B,0x3E,0x00,0x40,0x0,0x0,0x0,0x0,0x0,0x0,
110: 0xEA,0x8C,0xDF,0x28,0x0,0xE7,0x4,0xE3,0xFF,
111:
112: IB, // prepare atc for writing
113: INPUT_STATUS_1_COLOR,
114:
115: METAOUT+ATCOUT, //
116: ATT_ADDRESS_PORT, // port
117: VGA_NUM_ATTRIB_CONT_PORTS, // count
118: 0, // start index
119: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
120: 0x01,0x0,0x0F,0x0,0x0,
121:
122: METAOUT+INDXOUT, //
123: GRAPH_ADDRESS_PORT, // port
124: VGA_NUM_GRAPH_CONT_PORTS, // count
125: 0, // start index
126: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
127:
128: OB,
129: SEGMENT_SELECT_PORT,
130: 0x00,
131:
132: OB,
133: HERCULES_COMPATIBILITY_PORT,
134: LOCK_KEY_1,
135:
136: OB,
137: MODE_CONTROL_PORT_COLOR,
138: LOCK_KEY_2,
139:
140: OB,
141: DAC_PIXEL_MASK_PORT,
142: 0xFF,
143:
144: IB, // prepare atc for writing
145: INPUT_STATUS_1_COLOR,
146:
147: OB, // turn video on.
148: ATT_ADDRESS_PORT,
149: VIDEO_ENABLE,
150:
151: EOD
152: };
153:
154:
155: //
156: // Mode index 23
157: // Tseng color graphics mode 0x29, 800x600 16 colors.
158: //
159: USHORT ET4000_800x600[] = {
160: // Unlock Key for color mode
161: OB,
162: HERCULES_COMPATIBILITY_PORT,
163: UNLOCK_KEY_1,
164:
165: OB,
166: MODE_CONTROL_PORT_COLOR,
167: UNLOCK_KEY_2,
168:
169: OWM,
170: SEQ_ADDRESS_PORT,
171: 5,
172: 0x0100,0x0101,0x0f02,0x0003,0x0604, // program up sequencer
173:
174: #ifndef PRODESIGNER_II
175: OWM,
176: SEQ_ADDRESS_PORT,
177: 2,
178: 0x0006,0x0fc07, // program up sequencer
179: #else
180: OWM,
181: SEQ_ADDRESS_PORT,
182: 2,
183: 0x0006,0x0bc07, // program up sequencer
184: #endif //PRODESIGNER_II
185:
186: OB,
187: MISC_OUTPUT_REG_WRITE_PORT,
188: 0xe3,
189:
190: METAOUT+INDXOUT,
191: CRTC_ADDRESS_PORT_COLOR, // reg
192: 6, // count
193: IND_RAS_CAS_CONFIG, // start index
194: 0x28, 0x00, 0x0A, 0x00, 0x43, 0x1F,
195:
196: IB, // prepare atc for writing
197: INPUT_STATUS_1_COLOR,
198:
199: OB,
200: ATT_ADDRESS_PORT,
201: 0x16,
202:
203: OB,
204: ATT_ADDRESS_PORT,
205: 0x0,
206:
207: OW,
208: GRAPH_ADDRESS_PORT,
209: 0x0506,
210:
211: // EndSyncResetCmd
212: OB,
213: SEQ_ADDRESS_PORT,
214: IND_SYNC_RESET,
215:
216: OB,
217: SEQ_DATA_PORT,
218: END_SYNC_RESET_VALUE,
219:
220: OW,
221: CRTC_ADDRESS_PORT_COLOR,
222: 0x0E11,
223:
224: METAOUT+INDXOUT, // program crtc registers
225: CRTC_ADDRESS_PORT_COLOR,
226: VGA_NUM_CRTC_PORTS, // count
227: 0, // start index
228: 0x7F,0x63,0x64,0x02,0x6a,0x1d,0x77,0xf0,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
229: 0x5d,0x8f,0x57,0x32,0x0,0x5b,0x74,0xc3,0xFF,
230:
231: IB, // prepare atc for writing
232: INPUT_STATUS_1_COLOR,
233:
234: METAOUT+ATCOUT, //
235: ATT_ADDRESS_PORT, // port
236: VGA_NUM_ATTRIB_CONT_PORTS, // count
237: 0, // start index
238: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
239: 0x01,0x0,0x0F,0x0,0x0,
240:
241: METAOUT+INDXOUT, //
242: GRAPH_ADDRESS_PORT, // port
243: VGA_NUM_GRAPH_CONT_PORTS, // count
244: 0, // start index
245: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
246:
247: OB,
248: SEGMENT_SELECT_PORT,
249: 0x00,
250:
251: OB,
252: HERCULES_COMPATIBILITY_PORT,
253: LOCK_KEY_1,
254:
255: OB,
256: MODE_CONTROL_PORT_COLOR,
257: LOCK_KEY_2,
258:
259: OB,
260: DAC_PIXEL_MASK_PORT,
261: 0xFF,
262:
263: IB, // prepare atc for writing
264: INPUT_STATUS_1_COLOR,
265:
266: OB, // turn video on.
267: ATT_ADDRESS_PORT,
268: VIDEO_ENABLE,
269:
270: EOD
271: };
272:
273: //
274: // Mode index 28
275: // Tseng color graphics mode 0x37, 1024x768 non-interlaced 16 colors.
276: // Requires 512K minimum.
277: //
278:
279: USHORT ET4000_1024x768[] = {
280:
281: // Unlock Key for color mode
282: OB,
283: HERCULES_COMPATIBILITY_PORT,
284: UNLOCK_KEY_1,
285:
286: OB,
287: MODE_CONTROL_PORT_COLOR,
288: UNLOCK_KEY_2,
289:
290: OWM,
291: SEQ_ADDRESS_PORT,
292: 5,
293: 0x0100,0x0101,0x0f02,0x0003,0x0604, // program up sequencer
294:
295: OWM,
296: SEQ_ADDRESS_PORT,
297: 2,
298: 0x0006,0x0bc07, // program up sequencer
299:
300: #ifndef PRODESIGNER_II
301: #ifdef HZ70
302:
303: OB,
304: MISC_OUTPUT_REG_WRITE_PORT,
305: 0xe3,
306:
307: METAOUT+INDXOUT,
308: CRTC_ADDRESS_PORT_COLOR, // reg
309: 6, // count
310: IND_RAS_CAS_CONFIG, // start index
311: 0x28, 0x00, 0x0A, 0x00, 0x43, 0x1F,
312:
313: IB, // prepare atc for writing
314: INPUT_STATUS_1_COLOR,
315:
316: OB,
317: ATT_ADDRESS_PORT,
318: 0x16,
319:
320: OB,
321: ATT_ADDRESS_PORT,
322: 0x0,
323:
324: OW,
325: GRAPH_ADDRESS_PORT,
326: 0x0506,
327:
328: // EndSyncResetCmd
329: OB,
330: SEQ_ADDRESS_PORT,
331: IND_SYNC_RESET,
332:
333: OB,
334: SEQ_DATA_PORT,
335: END_SYNC_RESET_VALUE,
336:
337: OW,
338: CRTC_ADDRESS_PORT_COLOR,
339: 0x0E11,
340:
341: METAOUT+INDXOUT, // program crtc registers
342: CRTC_ADDRESS_PORT_COLOR,
343: VGA_NUM_CRTC_PORTS, // count
344: 0, // start index
345: 0x9b,0x7f,0x7f,0x9f,0x84,0x15,0x24,0xf5,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
346: 0x02,0x88,0xff,0x40,0x0,0xff,0x25,0xc3,0xFF,
347:
348: #else
349:
350: OB,
351: MISC_OUTPUT_REG_WRITE_PORT,
352: 0x2b,
353:
354: METAOUT+INDXOUT,
355: CRTC_ADDRESS_PORT_COLOR, // reg
356: 6, // count
357: IND_RAS_CAS_CONFIG, // start index
358: 0x28, 0x00, 0x08, 0x00, 0x43, 0x1F,
359:
360: IB, // prepare atc for writing
361: INPUT_STATUS_1_COLOR,
362:
363: OB,
364: ATT_ADDRESS_PORT,
365: 0x16,
366:
367: OB,
368: ATT_ADDRESS_PORT,
369: 0x0,
370:
371: OW,
372: GRAPH_ADDRESS_PORT,
373: 0x0506,
374:
375: // EndSyncResetCmd
376: OB,
377: SEQ_ADDRESS_PORT,
378: IND_SYNC_RESET,
379:
380: OB,
381: SEQ_DATA_PORT,
382: END_SYNC_RESET_VALUE,
383:
384: OW,
385: CRTC_ADDRESS_PORT_COLOR,
386: 0x0E11,
387:
388: METAOUT+INDXOUT, // program crtc registers
389: CRTC_ADDRESS_PORT_COLOR,
390: VGA_NUM_CRTC_PORTS, // count
391: 0, // start index
392: 0xa1,0x7f,0x80,0x04,0x88,0x9e,0x26,0xfd,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
393: 0x08,0x8a,0xff,0x40,0x0,0x04,0x22,0xc3,0xFF,
394:
395: #endif //HZ70
396: #else //PRODESIGNER_II
397:
398: OB,
399: MISC_OUTPUT_REG_WRITE_PORT,
400: 0x2f,
401:
402: METAOUT+INDXOUT,
403: CRTC_ADDRESS_PORT_COLOR, // reg
404: 6, // count
405: IND_RAS_CAS_CONFIG, // start index
406: 0x08, 0x00, 0x0a, 0x00, 0x43, 0x1F,
407:
408: IB, // prepare atc for writing
409: INPUT_STATUS_1_COLOR,
410:
411: OB,
412: ATT_ADDRESS_PORT,
413: 0x16,
414:
415: OB,
416: ATT_ADDRESS_PORT,
417: 0x0,
418:
419: OW,
420: GRAPH_ADDRESS_PORT,
421: 0x0506,
422:
423: // EndSyncResetCmd
424: OB,
425: SEQ_ADDRESS_PORT,
426: IND_SYNC_RESET,
427:
428: OB,
429: SEQ_DATA_PORT,
430: END_SYNC_RESET_VALUE,
431:
432: OW,
433: CRTC_ADDRESS_PORT_COLOR,
434: 0x0E11,
435:
436: METAOUT+INDXOUT, // program crtc registers
437: CRTC_ADDRESS_PORT_COLOR,
438: VGA_NUM_CRTC_PORTS, // count
439: 0, // start index
440: 0xa1,0x7f,0x80,0x04,0x88,0x9e,0x26,0xfd,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
441: 0x08,0x8a,0xff,0x40,0x0,0x04,0x22,0xc3,0xFF,
442:
443: #endif //PRODESIGNER_II
444: OB,
445: DAC_PIXEL_MASK_PORT,
446: 0xFF,
447:
448: IB, // prepare atc for writing
449: INPUT_STATUS_1_COLOR,
450:
451: METAOUT+ATCOUT, //
452: ATT_ADDRESS_PORT, // port
453: VGA_NUM_ATTRIB_CONT_PORTS, // count
454: 0, // start index
455: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
456: 0x01,0x0,0x0F,0x0,0x0,
457:
458: METAOUT+INDXOUT, //
459: GRAPH_ADDRESS_PORT, // port
460: VGA_NUM_GRAPH_CONT_PORTS, // count
461: 0, // start index
462: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
463:
464: OB,
465: SEGMENT_SELECT_PORT,
466: 0x00,
467:
468: OB,
469: HERCULES_COMPATIBILITY_PORT,
470: LOCK_KEY_1,
471:
472: OB,
473: MODE_CONTROL_PORT_COLOR,
474: LOCK_KEY_2,
475:
476: OB,
477: DAC_PIXEL_MASK_PORT,
478: 0xFF,
479:
480: IB, // prepare atc for writing
481: INPUT_STATUS_1_COLOR,
482:
483: OB, // turn video on.
484: ATT_ADDRESS_PORT,
485: VIDEO_ENABLE,
486:
487: EOD
488: };
489:
490: USHORT ET4000_TEXT_0[] = {
491: // Unlock Key for color mode
492: OB,
493: HERCULES_COMPATIBILITY_PORT,
494: UNLOCK_KEY_1,
495:
496: OB,
497: MODE_CONTROL_PORT_COLOR,
498: UNLOCK_KEY_2,
499:
500: OWM,
501: SEQ_ADDRESS_PORT,
502: 5,
503: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
504:
505: OWM,
506: SEQ_ADDRESS_PORT,
507: 2,
508: #ifndef PRODESIGNER_II
509: 0x0006,0x0fc07, // program up sequencer
510: #else
511: 0x0006,0x0bc07, // program up sequencer
512: #endif //PRODESIGNER_II
513:
514: OB,
515: MISC_OUTPUT_REG_WRITE_PORT,
516: 0x67,
517:
518: METAOUT+INDXOUT,
519: CRTC_ADDRESS_PORT_COLOR, // reg
520: 6, // count
521: IND_RAS_CAS_CONFIG, // start index
522: 0x28, 0x00, 0x08, 0x00, 0x43, 0x1F,
523:
524: IB, // prepare atc for writing
525: INPUT_STATUS_1_COLOR,
526:
527: OB,
528: ATT_ADDRESS_PORT,
529: IND_ATC_MISC,
530:
531: OB,
532: ATT_ADDRESS_PORT,
533: 0x0,
534:
535: OW,
536: GRAPH_ADDRESS_PORT,
537: 0x0e06,
538:
539: // EndSyncResetCmd
540: OB,
541: SEQ_ADDRESS_PORT,
542: IND_SYNC_RESET,
543:
544: OB,
545: SEQ_DATA_PORT,
546: END_SYNC_RESET_VALUE,
547:
548: OW,
549: CRTC_ADDRESS_PORT_COLOR,
550: 0x0E11,
551:
552: METAOUT+INDXOUT, // program crtc registers
553: CRTC_ADDRESS_PORT_COLOR,
554: VGA_NUM_CRTC_PORTS, // count
555: 0, // start index
556: 0x5F,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0xd,0xe,0x0,0x0,0x0,0x0,
557: 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,0xFF,
558:
559: IB, // prepare atc for writing
560: INPUT_STATUS_1_COLOR,
561:
562: METAOUT+ATCOUT, //
563: ATT_ADDRESS_PORT, // port
564: VGA_NUM_ATTRIB_CONT_PORTS, // count
565: 0, // start index
566: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
567: 0x04,0x0,0x0F,0x8,0x0,
568:
569: METAOUT+INDXOUT, //
570: GRAPH_ADDRESS_PORT, // port
571: VGA_NUM_GRAPH_CONT_PORTS, // count
572: 0, // start index
573: 0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
574:
575: OB,
576: SEGMENT_SELECT_PORT,
577: 0x00,
578:
579: OB,
580: HERCULES_COMPATIBILITY_PORT,
581: LOCK_KEY_1,
582:
583: OB,
584: MODE_CONTROL_PORT_COLOR,
585: LOCK_KEY_2,
586:
587: OB,
588: DAC_PIXEL_MASK_PORT,
589: 0xFF,
590:
591: IB, // prepare atc for writing
592: INPUT_STATUS_1_COLOR,
593:
594: OB, // turn video on.
595: ATT_ADDRESS_PORT,
596: VIDEO_ENABLE,
597:
598: EOD
599: };
600:
601: USHORT ET4000_TEXT_1[] = {
602: // Unlock Key for color mode
603: OB,
604: HERCULES_COMPATIBILITY_PORT,
605: UNLOCK_KEY_1,
606:
607: OB,
608: MODE_CONTROL_PORT_COLOR,
609: UNLOCK_KEY_2,
610:
611: OWM,
612: SEQ_ADDRESS_PORT,
613: 5,
614: 0x0100,0x0101,0x0302,0x0003,0x0204, // program up sequencer
615:
616: OWM,
617: SEQ_ADDRESS_PORT,
618: 2,
619: #ifndef PRODESIGNER_II
620: 0x0006,0x0fc07, // program up sequencer
621: #else
622: 0x0006,0x0bc07, // program up sequencer
623: #endif //PRODESIGNER_II
624:
625: OB,
626: MISC_OUTPUT_REG_WRITE_PORT,
627: 0xa3,
628:
629: METAOUT+INDXOUT,
630: CRTC_ADDRESS_PORT_COLOR, // reg
631: 6, // count
632: IND_RAS_CAS_CONFIG, // start index
633: 0x28, 0x00, 0x08, 0x00, 0x43, 0x1F,
634:
635: IB, // prepare atc for writing
636: INPUT_STATUS_1_COLOR,
637:
638: OB,
639: ATT_ADDRESS_PORT,
640: IND_ATC_MISC,
641:
642: OB,
643: ATT_ADDRESS_PORT,
644: 0x0,
645:
646: OW,
647: GRAPH_ADDRESS_PORT,
648: 0x0e06,
649:
650: // EndSyncResetCmd
651: OB,
652: SEQ_ADDRESS_PORT,
653: IND_SYNC_RESET,
654:
655: OB,
656: SEQ_DATA_PORT,
657: END_SYNC_RESET_VALUE,
658:
659: OW,
660: CRTC_ADDRESS_PORT_COLOR,
661: 0x0511,
662:
663: METAOUT+INDXOUT, // program crtc registers
664: CRTC_ADDRESS_PORT_COLOR,
665: VGA_NUM_CRTC_PORTS, // count
666: 0, // start index
667: 0x5F,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4d,0xb,0xc,0x0,0x0,0x0,0x0,
668: 0x83,0x85,0x5d,0x28,0x1f,0x63,0xba,0xa3,0xFF,
669:
670: IB, // prepare atc for writing
671: INPUT_STATUS_1_COLOR,
672:
673: METAOUT+ATCOUT, //
674: ATT_ADDRESS_PORT, // port
675: VGA_NUM_ATTRIB_CONT_PORTS, // count
676: 0, // start index
677: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
678: 0x00,0x0,0x0F,0x0,0x0,
679:
680: METAOUT+INDXOUT, //
681: GRAPH_ADDRESS_PORT, // port
682: VGA_NUM_GRAPH_CONT_PORTS, // count
683: 0, // start index
684: 0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
685:
686: OB,
687: SEGMENT_SELECT_PORT,
688: 0x00,
689:
690: OB,
691: HERCULES_COMPATIBILITY_PORT,
692: LOCK_KEY_1,
693:
694: OB,
695: MODE_CONTROL_PORT_COLOR,
696: LOCK_KEY_2,
697:
698: OB,
699: DAC_PIXEL_MASK_PORT,
700: 0xFF,
701:
702: IB, // prepare atc for writing
703: INPUT_STATUS_1_COLOR,
704:
705: OB, // turn video on.
706: ATT_ADDRESS_PORT,
707: VIDEO_ENABLE,
708:
709: EOD
710: };
711: #else//!INT10_MODE_SET
712:
713: USHORT ET4K_1K_WIDE[] = {
714: OW, // stretch scans to 1k
715: CRTC_ADDRESS_PORT_COLOR,
716: 0x8013,
717:
718: EOD
719: };
720:
721: #endif
722: //
723: // Memory map table -
724: //
725: // These memory maps are used to save and restore the physical video buffer.
726: //
727:
728: //
729: // Memory map table definition
730: //
731:
732: typedef struct {
733: ULONG MaxSize; // Maximum addressable size of memory
734: ULONG Start; // Start address of display memory
735: } MEMORYMAPS;
736:
737: MEMORYMAPS MemoryMaps[] = {
738:
739: // length start
740: // ------ -----
741: { 0x08000, 0xB0000}, // all mono text modes (7)
742: { 0x08000, 0xB8000}, // all color text modes (0, 1, 2, 3,
743: { 0x20000, 0xA0000}, // all VGA graphics modes
744: };
745:
746: //
747: // Video mode table - contains information and commands for initializing each
748: // mode. These entries must correspond with those in VIDEO_MODE_VGA. The first
749: // entry is commented; the rest follow the same format, but are not so
750: // heavily commented.
751: //
752:
753: VIDEOMODE ModesVGA[] = {
754:
755: //
756: // Standard VGA modes.
757: //
758:
759: //
760: // Mode index 0
761: // Color text mode 3, 720x400, 9x16 char cell (VGA).
762: //
763:
764: {
765: VIDEO_MODE_COLOR, // flags that this mode is a color mode, but not graphics
766: 4, // four planes
767: 1, // one bit of colour per plane
768: 80, 25, // 80x25 text resolution
769: 720, 400, // 720x400 pixels on screen
770: 0, 0, // only support one frequency, non-interlaced
771: 160, 0x10000, // 160 bytes per scan line, 64K of CPU-addressable bitmap
772: NoBanking, // no banking supported or needed in this mode
773: MemMap_CGA, // the memory mapping is the standard CGA memory mapping
774: // of 32K at B8000
775: FALSE, // Mode is not available by default
776: #ifdef INT10_MODE_SET
777: 0x3, // int 10 modesset value
778: NULL, // scan line stretching option
779: #else
780: ET4000_TEXT_0, // pointer to the command strings
781: #endif
782: },
783:
784: //
785: // Mode index 1.
786: // Color text mode 3, 640x350, 8x14 char cell (EGA).
787: //
788:
789: { VIDEO_MODE_COLOR, 4, 1, 80, 25,
790: 640, 350, 160, 0x10000, 0, 0, NoBanking, MemMap_CGA,
791: FALSE,
792: #ifdef INT10_MODE_SET
793: 0x3,
794: NULL,
795: #else
796: ET4000_TEXT_1, // pointer to the command strings
797: #endif
798: },
799:
800: //
801: //
802: // Mode index 2
803: // Standard VGA Color graphics mode 0x12, 640x480 16 colors.
804: //
805:
806: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 80, 30,
807: 640, 480, 80, 0x10000, 60, 0, NoBanking, MemMap_VGA,
808: FALSE,
809: #ifdef INT10_MODE_SET
810: 0x12,
811: NULL,
812: #else
813: ET4000_640x480, // pointer to the command strings
814: #endif
815: },
816:
817: //
818: //
819: // Mode index 2a
820: // Standard VGA Color graphics mode 0x12, 640x480 16 colors. 72Hz
821: //
822:
823: #ifdef INT10_MODE_SET
824: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 80, 30,
825: 640, 480, 80, 0x10000, 72, 0, NoBanking, MemMap_VGA,
826: FALSE,
827: 0x12,
828: NULL,
829: },
830: #endif
831:
832: //
833: // Beginning of SVGA modes
834: //
835:
836: //
837: // Mode index 3
838: // 800x600 16 colors.
839: //
840:
841: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 100, 37,
842: 800, 600, 100, 0x10000, 60, 0, NoBanking, MemMap_VGA,
843: FALSE,
844: #ifdef INT10_MODE_SET
845: 0x29,
846: NULL,
847: #else
848: ET4000_800x600, // pointer to the command strings
849: #endif
850: },
851:
852: //
853: // Mode index 3a
854: // 800x600 16 colors. 72 hz
855: //
856:
857: #ifdef INT10_MODE_SET
858: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 100, 37,
859: 800, 600, 100, 0x10000, 72, 0, NoBanking, MemMap_VGA,
860: FALSE,
861: 0x29,
862: NULL,
863: },
864:
865: //
866: // Mode index 3b
867: // 800x600 16 colors. 56 hz for 8514/a monitors... (fixed freq)
868: //
869:
870: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 100, 37,
871: 800, 600, 100, 0x10000, 56, 0, NoBanking, MemMap_VGA,
872: FALSE,
873: 0x29,
874: NULL,
875: },
876: #endif
877:
878: //
879: // Mode index 4
880: // 1024x768 non-interlaced 16 colors.
881: // Assumes 512K.
882: //
883:
884: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 128, 48,
885: 1024, 768, 128, 0x20000, 60, 0, NormalBanking, MemMap_VGA,
886: FALSE,
887: #ifdef INT10_MODE_SET
888: 0x37,
889: NULL,
890: #else
891: ET4000_1024x768, // pointer to the command strings
892: #endif
893: },
894:
895: #ifdef INT10_MODE_SET
896: //
897: // Mode index 4a
898: // 1024x768 non-interlaced 16 colors. 70hz
899: // Assumes 512K.
900: //
901:
902: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 128, 48,
903: 1024, 768, 128, 0x20000, 70, 0, NormalBanking, MemMap_VGA,
904: FALSE,
905: 0x37,
906: NULL
907: },
908:
909: //
910: // Mode index 4b
911: // 1024x768 non-interlaced 16 colors. Interlaced (45 hz)
912: // Assumes 512K.
913: //
914:
915: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 128, 48,
916: 1024, 768, 128, 0x20000, 45, 1, NormalBanking, MemMap_VGA,
917: FALSE,
918: 0x37,
919: NULL
920: },
921:
922: //
923: // Mode index 6
924: // 640x480x256
925: //
926:
927: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
928: 640, 480, 1024, 0x80000, 60, 0, PlanarHCBanking, MemMap_VGA,
929: FALSE,
930: 0x2E,
931: ET4K_1K_WIDE
932: },
933:
934: //
935: // Mode index 6a
936: // 640x480x256 72 Hz
937: //
938:
939: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
940: 640, 480, 1024, 0x80000, 72, 0, PlanarHCBanking, MemMap_VGA,
941: FALSE,
942: 0x2E,
943: ET4K_1K_WIDE
944: },
945:
946: // BUGBUG 800x600 modes need 1Meg until we support broken rasters
947:
948: //
949: // Mode index 7
950: // 800x600x256 60Hz
951: //
952:
953: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
954: 800, 600, 1024, 0x100000, 60, 0, PlanarHCBanking, MemMap_VGA,
955: FALSE,
956: 0x30,
957: ET4K_1K_WIDE
958: },
959:
960: //
961: // Mode index 7a
962: // 800x600x256 72Hz
963: //
964:
965: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
966: 800, 600, 1024, 0x100000, 72, 0, PlanarHCBanking, MemMap_VGA,
967: FALSE,
968: 0x30,
969: ET4K_1K_WIDE
970: },
971:
972: //
973: // Mode index 7b
974: // 800x600x256 56Hz
975: //
976: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
977: 800, 600, 1024, 0x100000, 56, 0, PlanarHCBanking, MemMap_VGA,
978: FALSE,
979: 0x30,
980: ET4K_1K_WIDE
981: },
982:
983: //
984: // Mode index 8
985: // 1024x768x256 60
986: //
987:
988: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
989: 1024, 768, 1024, 0x100000, 60, 0, PlanarHCBanking, MemMap_VGA,
990: FALSE,
991: 0x38,
992: NULL
993: },
994:
995: //
996: // Mode index 8a 70 hz
997: // 1024x768x256
998: //
999:
1000: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1001: 1024, 768, 1024, 0x100000, 70, 0, PlanarHCBanking, MemMap_VGA,
1002: FALSE,
1003: 0x38,
1004: NULL
1005: },
1006:
1007: //
1008: // Mode index 8b 45Hz (Interlaced)
1009: // 1024x768x256
1010: //
1011:
1012: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1013: 1024, 768, 1024, 0x100000, 45, 1, PlanarHCBanking, MemMap_VGA,
1014: FALSE,
1015: 0x38,
1016: NULL
1017: },
1018:
1019: //
1020: // Mode index 9
1021: // 640x480x64K
1022: //
1023:
1024: //{ VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 16, 80, 30,
1025: // 640, 480, 1024, 0x100000, 60, 0, NormalBanking, MemMap_VGA,
1026: // FALSE,
1027: // 0x2E,
1028: // ET4K_1K_WIDE
1029: //},
1030:
1031: //
1032: // Mode index 9a 72hz
1033: // 640x480x64K
1034: //
1035:
1036: //{ VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 16, 80, 30,
1037: // 640, 480, 1024, 0x100000, 72, 0, NormalBanking, MemMap_VGA,
1038: // FALSE,
1039: // 0x2E,
1040: // ET4K_1K_WIDE
1041: //},
1042:
1043: //
1044: // Mode index 10
1045: // 800x600x64K
1046: //
1047:
1048: //{ VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 16, 80, 30,
1049: // 800, 600, 800, 0x100000, 60, 0, NormalBanking, MemMap_VGA,
1050: // FALSE,
1051: // 0x30,
1052: // NULL
1053: //},
1054:
1055: //
1056: // Mode index 10a 72 Hz
1057: // 800x600x64K
1058: //
1059:
1060: //{ VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 16, 80, 30,
1061: // 800, 600, 800, 0x100000, 72, 0, NormalBanking, MemMap_VGA,
1062: // FALSE,
1063: // 0x30,
1064: // NULL
1065: //},
1066: #endif//INT10_MODE_SET
1067: };
1068:
1069: ULONG NumVideoModes = sizeof(ModesVGA) / sizeof(VIDEOMODE);
1070:
1071:
1072: //
1073: //
1074: // Data used to set the Graphics and Sequence Controllers to put the
1075: // VGA into a planar state at A0000 for 64K, with plane 2 enabled for
1076: // reads and writes, so that a font can be loaded, and to disable that mode.
1077: //
1078:
1079: // Settings to enable planar mode with plane 2 enabled.
1080: //
1081:
1082: USHORT EnableA000Data[] = {
1083: OWM,
1084: SEQ_ADDRESS_PORT,
1085: 1,
1086: 0x0100,
1087:
1088: OWM,
1089: GRAPH_ADDRESS_PORT,
1090: 3,
1091: 0x0204, // Read Map = plane 2
1092: 0x0005, // Graphics Mode = read mode 0, write mode 0
1093: 0x0406, // Graphics Miscellaneous register = A0000 for 64K, not odd/even,
1094: // graphics mode
1095: OWM,
1096: SEQ_ADDRESS_PORT,
1097: 3,
1098: 0x0402, // Map Mask = write to plane 2 only
1099: 0x0404, // Memory Mode = not odd/even, not full memory, graphics mode
1100: 0x0300, // end sync reset
1101: EOD
1102: };
1103:
1104: //
1105: // Settings to disable the font-loading planar mode.
1106: //
1107:
1108: USHORT DisableA000Color[] = {
1109: OWM,
1110: SEQ_ADDRESS_PORT,
1111: 1,
1112: 0x0100,
1113:
1114: OWM,
1115: GRAPH_ADDRESS_PORT,
1116: 3,
1117: 0x0004, 0x1005, 0x0E06,
1118:
1119: OWM,
1120: SEQ_ADDRESS_PORT,
1121: 3,
1122: 0x0302, 0x0204, 0x0300, // end sync reset
1123: EOD
1124:
1125: };
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