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1.1 root 1: /*++
2:
3: Copyright (c) 1990-1992 Microsoft Corporation
4:
5: Module Name:
6:
7: s3.h
8:
9: Abstract:
10:
11: This module contains the definitions for the S3 miniport driver.
12:
13: Environment:
14:
15: Kernel mode
16:
17: Revision History:
18:
19: --*/
20:
21: #include "dderror.h"
22: #include "devioctl.h"
23: #include "miniport.h"
24:
25: #include "ntddvdeo.h"
26: #include "video.h"
27:
28:
29: //
30: // Number of access ranges used by an S3.
31: //
32:
33: #define NUM_S3_ACCESS_RANGES 22
34: #define S3_EXTENDED_RANGE_START 4
35:
36:
37: //
38: // Supported board definitions.
39: //
40:
41: typedef enum _S3_BOARDS {
42: S3_GENERIC = 0,
43: S3_ORCHID,
44: S3_NUMBER_NINE,
45: S3_DELL,
46: MAX_S3_BOARD
47: } S3_BOARDS;
48:
49: //
50: // Chip type definitions
51: //
52:
53: typedef enum _S3_CHIPSETS {
54: S3_911 = 0, // 911 and 924 boards
55: S3_801, // 801 and 805 boards
56: S3_928, // 928 boards
57: MAX_S3_CHIPSET
58: } S3_CHIPSET;
59:
60: //
61: // Characteristics of each mode
62: //
63:
64: typedef struct _S3_VIDEO_MODES {
65:
66: UCHAR ModeValid;
67: ULONG RequiredVideoMemory;
68: USHORT Int10ModeNumber;
69:
70: PUSHORT CRTCTables[MAX_S3_CHIPSET]; // Array of mode table pointers.
71:
72: VIDEO_MODE_INFORMATION ModeInformation;
73:
74: } S3_VIDEO_MODES, *PS3_VIDEO_MODES;
75:
76:
77: //
78: // Register definitions used with VideoPortRead/Write functions
79: //
80:
81: #define DAC_PIXEL_MASK_REG (PVOID) ((ULONG)( ((PHW_DEVICE_EXTENSION)HwDeviceExtension)->MappedAddress[2]) + (0x03C6 - 0x03C0))
82:
83: #define DAC_ADDRESS_WRITE_PORT (PVOID) ((ULONG)(HwDeviceExtension->MappedAddress[2]) + (0x03C8 - 0x03C0))
84: #define DAC_DATA_REG_PORT (PVOID) ((ULONG)(HwDeviceExtension->MappedAddress[2]) + (0x03C9 - 0x03C0))
85:
86: #define MISC_OUTPUT_REG_WRITE (PVOID) ((ULONG)(HwDeviceExtension->MappedAddress[2]) + (0x03C2 - 0x03C0))
87: #define MISC_OUTPUT_REG_READ (PVOID) ((ULONG)(HwDeviceExtension->MappedAddress[2]) + (0x03CC - 0x03C0))
88:
89: #define SEQ_ADDRESS_REG (PVOID) ((ULONG)(HwDeviceExtension->MappedAddress[2]) + (0x03C4 - 0x03C0))
90: #define SEQ_DATA_REG (PVOID) ((ULONG)(HwDeviceExtension->MappedAddress[2]) + (0x03C5 - 0x03C0))
91:
92: #define CRT_ADDRESS_REG (PVOID) ((PHW_DEVICE_EXTENSION)HwDeviceExtension)->MappedAddress[3]
93: #define CRT_DATA_REG (PVOID) ((ULONG)( ((PHW_DEVICE_EXTENSION)HwDeviceExtension)->MappedAddress[3]) + (0x03D5 - 0x03D4))
94: #define SYSTEM_CONTROL_REG (PVOID) ((ULONG)( ((PHW_DEVICE_EXTENSION)HwDeviceExtension)->MappedAddress[3]) + (0x03DA - 0x03D4))
95:
96: #define ADV_FUNC_CTL (PVOID) ((PHW_DEVICE_EXTENSION)HwDeviceExtension)->MappedAddress[5]
97:
98: #define SUB_SYS_STAT HwDeviceExtension->MappedAddress[4] // 0x42E8
99: #define CUR_Y HwDeviceExtension->MappedAddress[6] // 0x82E8
100: #define CUR_X HwDeviceExtension->MappedAddress[7] // 0x86E8
101: #define RECT_WIDTH HwDeviceExtension->MappedAddress[11] // 0x96E8
102: #define GP_STAT ((PHW_DEVICE_EXTENSION)HwDeviceExtension)->MappedAddress[12] // 0x9AE8
103: #define CMD HwDeviceExtension->MappedAddress[12] // 0x9AE8
104: #define BKGD_COLOR HwDeviceExtension->MappedAddress[14] // 0xA2E8
105: #define FRGD_COLOR HwDeviceExtension->MappedAddress[15] // 0xA6E8
106: #define WRT_MASK HwDeviceExtension->MappedAddress[16] // 0xAAE8
107: #define RD_MASK HwDeviceExtension->MappedAddress[17] // 0xAEE8
108: #define BKGD_MIX HwDeviceExtension->MappedAddress[18] // 0xB6E8
109: #define FRGD_MIX HwDeviceExtension->MappedAddress[19] // 0xBAE8
110: #define MULTIFUNC_CNTL HwDeviceExtension->MappedAddress[20] // 0xBEE8
111: #define PIXEL_TRANSFER HwDeviceExtension->MappedAddress[21] // 0xE2E8
112:
113: //
114: // Define device extension structure. This is device dependant/private
115: // information.
116: //
117:
118: typedef struct _HW_DEVICE_EXTENSION {
119: PVOID FrameAddress;
120: PHYSICAL_ADDRESS PhysicalFrameAddress;
121: ULONG FrameLength;
122: PHYSICAL_ADDRESS PhysicalRegisterAddress;
123: ULONG RegisterLength;
124: UCHAR RegisterSpace;
125: BOOLEAN bUsingInt10;
126: ULONG ModeNumber;
127: ULONG BoardID;
128: ULONG ChipID;
129: ULONG NumAvailableModes;
130: ULONG AdapterMemorySize;
131: PVOID MappedAddress[NUM_S3_ACCESS_RANGES];
132: } HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
133:
134:
135: //
136: // Highest valid DAC color register index.
137: //
138:
139: #define VIDEO_MAX_COLOR_REGISTER 0xFF
140:
141:
142: // Equates to handle the S3 graphics engine.
143:
144: #define S3BM_WIDTH 1024
145: #define S3BM_HEIGHT 768
146:
147:
148: // Command Types
149:
150: #define NOP 0x0000
151: #define DRAW_LINE 0x2000
152: #define RECTANGLE_FILL 0x4000
153: #define BITBLT 0xC000
154:
155: #define BYTE_SWAP 0x1000
156: #define BUS_SIZE_16 0x0200
157: #define BUS_SIZE_8 0x0000
158: #define WAIT 0x0100
159:
160: // Drawing directions (radial)
161:
162: #define DRAWING_DIRECTION_0 0x0000
163: #define DRAWING_DIRECTION_45 0x0020
164: #define DRAWING_DIRECTION_90 0x0040
165: #define DRAWING_DIRECTION_135 0x0060
166: #define DRAWING_DIRECTION_180 0x0080
167: #define DRAWING_DIRECTION_225 0x00A0
168: #define DRAWING_DIRECTION_270 0x00C0
169: #define DRAWING_DIRECTION_315 0x00E0
170:
171: // Drawing directions (x/y)
172:
173: #define DRAWING_DIR_BTRLXM 0x0000
174: #define DRAWING_DIR_BTLRXM 0x0020
175: #define DRAWING_DIR_BTRLYM 0x0040
176: #define DRAWING_DIR_BTLRYM 0x0060
177: #define DRAWING_DIR_TBRLXM 0x0080
178: #define DRAWING_DIR_TBLRXM 0x00A0
179: #define DRAWING_DIR_TBRLYM 0x00C0
180: #define DRAWING_DIR_TBLRYM 0x00E0
181:
182: // Drawing Direction Bits
183:
184: #define PLUS_X 0x0020
185: #define PLUS_Y 0x0080
186: #define MAJOR_Y 0x0040
187:
188: // Draw
189:
190: #define DRAW 0x0010
191:
192: // Direction type
193:
194: #define DIR_TYPE_RADIAL 0x0008
195: #define DIR_TYPE_XY 0x0000
196:
197: // Last Pixel
198:
199: #define LAST_PIXEL_OFF 0x0004
200: #define LAST_PIXEL_ON 0x0000
201:
202: // Pixel Mode
203:
204: #define MULTIPLE_PIXELS 0x0002
205: #define SINGLE_PIXEL 0x0000
206:
207: // Read/Write
208:
209: #define READ 0x0000
210: #define WRITE 0x0001
211:
212:
213: // G.P. Status
214:
215: #define HARDWARE_BUSY 0x200
216: #define READ_DATA_AVAILABLE 0x100
217:
218: // Fifo Status
219:
220: #define FIFO_7_STATUS 0x080
221: #define FIFO_6_STATUS 0x040
222: #define FIFO_5_STATUS 0x020
223: #define FIFO_4_STATUS 0x010
224: #define FIFO_3_STATUS 0x008
225: #define FIFO_2_STATUS 0x004
226: #define FIFO_1_STATUS 0x002
227: #define FIFO_0_STATUS 0x001
228:
229: // Fifo status in terms of empty entries
230:
231: #define FIFO_1_EMPTY FIFO_7_STATUS
232: #define FIFO_2_EMPTY FIFO_6_STATUS
233: #define FIFO_3_EMPTY FIFO_5_STATUS
234: #define FIFO_4_EMPTY FIFO_4_STATUS
235: #define FIFO_5_EMPTY FIFO_3_STATUS
236: #define FIFO_6_EMPTY FIFO_2_STATUS
237: #define FIFO_7_EMPTY FIFO_1_STATUS
238: #define FIFO_8_EMPTY FIFO_0_STATUS
239:
240:
241:
242: // These are the defines for the multifunction control register.
243: // The 4 MSBs define the function of the register.
244:
245: #define RECT_HEIGHT 0x0000
246:
247: #define CLIP_TOP 0x1000
248: #define CLIP_LEFT 0x2000
249: #define CLIP_BOTTOM 0x3000
250: #define CLIP_RIGHT 0x4000
251:
252:
253: #define DATA_EXTENSION 0xA000
254: #define ALL_ONES 0x0000
255: #define CPU_DATA 0x0080
256: #define DISPLAY_MEMORY 0x00C0
257:
258: // Color source
259:
260: #define BACKGROUND_COLOR 0x00
261: #define FOREGROUND_COLOR 0x20
262: #define SRC_CPU_DATA 0x40
263: #define SRC_DISPLAY_MEMORY 0x60
264:
265: // Mix modes
266:
267: #define NOT_SCREEN 0x00
268: #define LOGICAL_0 0x01
269: #define LOGICAL_1 0x02
270: #define LEAVE_ALONE 0x03
271: #define NOT_NEW 0x04
272: #define SCREEN_XOR_NEW 0x05
273: #define NOT_SCREEN_XOR_NEW 0x06
274: #define OVERPAINT 0x07
275: #define NOT_SCREEN_OR_NOT_NEW 0x08
276: #define SCREEN_OR_NOT_NEW 0x09
277: #define NOT_SCREEN_OR_NEW 0x0A
278: #define SCREEN_OR_NEW 0x0B
279: #define SCREEN_AND_NEW 0x0C
280: #define NOT_SCREEN_AND_NEW 0x0D
281: #define SCREEN_AND_NOT_NEW 0x0E
282: #define NOT_SCREEN_AND_NOT_NEW 0x0F
283:
284: //
285: // General purpose support routines & macros.
286: //
287:
288: #define FIFOWAIT(level) while (VideoPortReadPortUshort(GP_STAT) & level);
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