![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to s3data.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [WindowsNT SDKs] / ntddk / src / video / miniport / s3|
Return to s3data.h CVS log | Up to [WindowsNT SDKs] / ntddk / src / video / miniport / s3 |
1.1 root 1: /*++
2:
3: Copyright (c) 1992 Microsoft Corporation
4:
5: Module Name:
6:
7: s3data.h
8:
9: Abstract:
10:
11: This module contains all the global data used by the S3 driver.
12:
13: Environment:
14:
15: Kernel mode
16:
17: Revision History:
18:
19:
20: --*/
21:
22:
23: #include "cmdcnst.h"
24:
25:
26: /*****************************************************************************
27: * Command table to get ready for VGA mode
28: * this is only used for the 911/924 chips
29: ****************************************************************************/
30: USHORT s3_set_vga_mode[] = {
31:
32: SELECTACCESSRANGE + SYSTEMCONTROL,
33:
34: OW, // Unlock the S3 regs
35: 0x3d4, 0x4838,
36:
37: OW, // Unlock the SC regs
38: 0x3d4, 0xa539,
39:
40: OB, // Enable the S3 graphics engine
41: 0x3d4, 0x40,
42:
43: METAOUT+MASKOUT,
44: 0x3d5, 0xfe, 0x01,
45:
46: SELECTACCESSRANGE + ADVANCEDFUNCTIONCONTROL,
47:
48: OB, // reset to normal VGA operation
49: 0x4ae8, 0x02,
50:
51: SELECTACCESSRANGE + SYSTEMCONTROL,
52:
53: OB, // Disable the S3 graphics engine
54: 0x3d4, 0x40,
55:
56: METAOUT+MASKOUT,
57: 0x3d5, 0xfe, 0x00,
58:
59: OB, // Memory Control
60: 0x3d4, 0x31,
61:
62: METAOUT+MASKOUT,
63: 0x3d5, 0x75, 0x85,
64:
65: OB, // Backward Compat 1
66: 0x3d4, 0x32,
67:
68: METAOUT+MASKOUT,
69: 0x3d5, 0x40, 0x00,
70:
71: OW, // Backward Compat 2
72: 0x3d4, 0x0033,
73:
74: OW, // Backward Compat 3
75: 0x3d4, 0x0034,
76:
77: OW, // CRTC Lock
78: 0x3d4, 0x0035,
79:
80: OB, // S3 Misc 1
81: 0x3d4, 0x3a,
82:
83: METAOUT+MASKOUT,
84: 0x3d5, 0x88, 0x05,
85:
86: OW, // Data Transfer Exec Pos
87: 0x3d4, 0x5a3b,
88:
89: OW, // Interlace Retrace start
90: 0x3d4, 0x103c,
91:
92: OW, // Extended Mode
93: 0x3d4, 0x0043,
94:
95: OW, // HW graphics Cursor Mode
96: 0x3d4, 0x0045,
97:
98: OW, // HW graphics Cursor Orig x
99: 0x3d4, 0x0046,
100:
101: OW, // HW graphics Cursor Orig x
102: 0x3d4, 0xff47,
103:
104: OW, // HW graphics Cursor Orig y
105: 0x3d4, 0xfc48,
106:
107: OW, // HW graphics Cursor Orig y
108: 0x3d4, 0xff49,
109:
110: OW, // HW graphics Cursor Orig y
111: 0x3d4, 0xff4a,
112:
113: OW, // HW graphics Cursor Orig y
114: 0x3d4, 0xff4b,
115:
116: OW, // HW graphics Cursor Orig y
117: 0x3d4, 0xff4c,
118:
119: OW, // HW graphics Cursor Orig y
120: 0x3d4, 0xff4d,
121:
122: OW, // Dsp Start x pixel pos
123: 0x3d4, 0xff4e,
124:
125: OW, // Dsp Start y pixel pos
126: 0x3d4, 0xdf4d,
127:
128: OB, // MODE-CNTL
129: 0x3d4, 0x42,
130:
131: METAOUT+MASKOUT,
132: 0x3d5, 0xdf, 0x00,
133:
134: EOD
135:
136: };
137:
138: //
139: // Mode tables are only necessary for non-x86.
140: // This allows us to save lots of space in memory
141:
142: #ifndef i386
143:
144: /*****************************************************************************
145: * S3 - 911 Enhanced mode init.
146: ****************************************************************************/
147: USHORT S3_911_Enhanced_Mode[] = {
148: SELECTACCESSRANGE + VARIOUSVGA,
149:
150: OB, // Make the screen dark
151: 0x3c6, 0x00,
152:
153: OW, // Turn off the screen
154: 0x3c4, 0x2101,
155:
156: METAOUT+VBLANK, // Wait for the 911 to settle down.
157: METAOUT+VBLANK,
158:
159: OW, // Async Reset
160: 0x3c4, 0x0100,
161:
162: OWM, // Sequencer Registers
163: 0x3c4,
164: 4,
165: 0x2101, 0x0F02, 0x0003, 0x0e04,
166:
167: METAOUT+SETCRTC, // Program the CRTC regs
168:
169: SELECTACCESSRANGE + SYSTEMCONTROL,
170:
171: IB, // Prepare to prgram the ACT
172: 0x3da,
173:
174: SELECTACCESSRANGE + VARIOUSVGA,
175:
176: METAOUT+ATCOUT, // Program the ATC
177: 0x3c0,
178: 21, 0,
179: 0x00, 0x01, 0x02, 0x03, 0x04,
180: 0x05, 0x06, 0x07, 0x08, 0x09,
181: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
182: 0x0f, 0x41, 0x00, 0x0f, 0x00,
183: 0x00,
184:
185: OW, // Start the sequencer
186: 0x3c4, 0x300,
187:
188: OWM, // Program the GDC
189: 0x3ce,
190: 9,
191: 0x0000, 0x0001, 0x0002, 0x0003, 0x0004,
192: 0x0005, 0x0506, 0x0f07, 0xff08,
193:
194: SELECTACCESSRANGE + SYSTEMCONTROL,
195:
196: IB, // Set ATC FF to index
197: 0x3da,
198:
199: SELECTACCESSRANGE + VARIOUSVGA,
200:
201: OB, // Enable the palette
202: 0x3c0, 0x20,
203:
204: SELECTACCESSRANGE + SYSTEMCONTROL,
205:
206: OW, // Unlock S3 SC regs
207: 0x3d4, 0xa039,
208:
209: OB, // Enable 8514/a reg access
210: 0x3d4, 0x40,
211:
212: METAOUT+MASKOUT,
213: 0x3d5, 0xfe, 0x01,
214:
215: OB, // Turn off H/W Graphics Cursor
216: 0x3d4, 0x45,
217:
218: METAOUT+MASKOUT,
219: 0x3d5, 0xfe, 0x0,
220:
221: OW, // Set the graphic cursor fg color
222: 0x3d4, 0xff0e,
223:
224: OW, // Set the graphic cursor bg color
225: 0x3d4, 0x000f,
226:
227: OW, // Unlock the S3 specific regs
228: 0x3d4, 0x4838,
229:
230: OB, // Set the Misc 1 reg
231: 0x3d4, 0x3a,
232:
233: METAOUT+MASKOUT,
234: 0x3d5, 0xe2, 0x15,
235:
236: OB, // Disable 2K X 1K X 4 plane
237: 0x3d4, 0x31,
238:
239: METAOUT+MASKOUT,
240: 0x3d5, 0xe4, 0x08,
241:
242: OB, // Disable multiple pages
243: 0x3d4, 0x32,
244:
245: METAOUT+MASKOUT,
246: 0x3d5, 0xbf, 0x0,
247:
248: OW, // Lock S3 specific regs
249: 0x3d4, 0x0038,
250:
251: SELECTACCESSRANGE + ADVANCEDFUNCTIONCONTROL,
252:
253: OW, // Set either 800X600 or 1024X768
254: 0x4ae8, 0x07, // hi-res mode.
255:
256: SELECTACCESSRANGE + VARIOUSVGA,
257:
258: OB, // Set Misc out reg for external clock
259: 0x3c2, 0x2f,
260:
261: SELECTACCESSRANGE + SYSTEMCONTROL,
262:
263: OW, // Unlock the SC regs
264: 0x3d4, 0xa039,
265:
266: METAOUT+SETCLK, // Set the clock for 65 Mhz
267:
268: METAOUT+VBLANK, // Wait for the clock to settle down
269: METAOUT+VBLANK, // S3 product alert Synchronization &
270: METAOUT+VBLANK, // Clock Skew.
271: METAOUT+VBLANK,
272: METAOUT+VBLANK,
273: METAOUT+VBLANK,
274:
275: OW, // Lock the SC regs
276: 0x3d4, 0x0039,
277:
278: SELECTACCESSRANGE + VARIOUSVGA,
279:
280: OB, // Turn on the screen - in the sequencer
281: 0x3c4, 0x01,
282:
283: METAOUT+MASKOUT,
284: 0x3c5, 0xdf, 0x0,
285:
286: METAOUT+VBLANK, // Wait the monitor to settle down
287: METAOUT+VBLANK,
288:
289: OW, // Enable all the planes through the DAC
290: 0x3c6, 0xff,
291:
292: EOD
293:
294: };
295:
296: /*****************************************************************************
297: * S3 - 801 Enhanced mode init.
298: ****************************************************************************/
299: USHORT S3_801_Enhanced_Mode[] = {
300:
301: SELECTACCESSRANGE + VARIOUSVGA,
302:
303: OB, // Make the screen dark
304: 0x3c6, 0x00,
305:
306: OW, // Turn off the screen
307: 0x3c4, 0x2101,
308:
309: METAOUT+VBLANK, // Wait for the 911 to settle down.
310: METAOUT+VBLANK,
311:
312: OW, // Async Reset
313: 0x3c4, 0x0100,
314:
315: OWM, // Sequencer Registers
316: 0x3c4,
317: 4,
318: 0x2101, 0x0F02, 0x0003, 0x0e04,
319:
320: METAOUT+SETCRTC, // Program the CRTC regs
321:
322: SELECTACCESSRANGE + SYSTEMCONTROL,
323:
324: OWM,
325: 0x3d4,
326: 17,
327: 0xA039, 0x0e42, 0x403c, 0x8931, 0x153a,
328: 0x0050, 0x4854, 0x2f60, 0x8161, 0x0062,
329: 0x0058, 0x0033, 0x0043, 0x8013, 0x0051,
330: 0x005c, 0x1034,
331:
332: OW,
333: 0x3d4, 0x0a5a, // Set the low byte of the LAW
334:
335: OW,
336: 0x3d4, 0x0059, // Set the high byte of the LAW
337:
338: OW, // Lock S3 specific regs
339: 0x3d4, 0x0038,
340:
341: OW, // Lock more S3 specific regs
342: 0x3d4, 0x0039,
343:
344: IB, // Prepare to prgram the ACT
345: 0x3da,
346:
347: SELECTACCESSRANGE + VARIOUSVGA,
348:
349: METAOUT+ATCOUT, // Program the ATC
350: 0x3c0,
351: 21, 0,
352: 0x00, 0x01, 0x02, 0x03, 0x04,
353: 0x05, 0x06, 0x07, 0x08, 0x09,
354: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
355: 0x0f, 0x41, 0x00, 0x0f, 0x00,
356: 0x00,
357:
358: OW, // Start the sequencer
359: 0x3c4, 0x300,
360:
361: OWM, // Program the GDC
362: 0x3ce,
363: 9,
364: 0x0000, 0x0001, 0x0002, 0x0003, 0x0004,
365: 0x0005, 0x0506, 0x0f07, 0xff08,
366:
367: SELECTACCESSRANGE + SYSTEMCONTROL,
368:
369: IB, // Set ATC FF to index
370: 0x3da,
371:
372: SELECTACCESSRANGE + VARIOUSVGA,
373:
374: OB, // Enable the palette
375: 0x3c0, 0x20,
376:
377: SELECTACCESSRANGE + SYSTEMCONTROL,
378:
379: OW, // Unlock S3 SC regs
380: 0x3d4, 0xa039,
381:
382: OB, // Enable 8514/a reg access
383: 0x3d4, 0x40,
384:
385: METAOUT+MASKOUT,
386: 0x3d5, 0xfe, 0x01,
387:
388: OB, // Turn off H/W Graphics Cursor
389: 0x3d4, 0x45,
390:
391: METAOUT+MASKOUT,
392: 0x3d5, 0xfe, 0x0,
393:
394: OW, // Set the graphic cursor fg color
395: 0x3d4, 0xff0e,
396:
397: OW, // Set the graphic cursor bg color
398: 0x3d4, 0x000f,
399:
400: OW, // Unlock the S3 specific regs
401: 0x3d4, 0x4838,
402:
403: OB, // Set the Misc 1 reg
404: 0x3d4, 0x3a,
405:
406: METAOUT+MASKOUT,
407: 0x3d5, 0xe2, 0x15,
408:
409: OB, // Disable 2K X 1K X 4 plane
410: 0x3d4, 0x31,
411:
412: METAOUT+MASKOUT,
413: 0x3d5, 0xe4, 0x08,
414:
415: OB, // Disable multiple pages
416: 0x3d4, 0x32,
417:
418: METAOUT+MASKOUT,
419: 0x3d5, 0xbf, 0x0,
420:
421: OW, // Lock S3 specific regs
422: 0x3d4, 0x0038,
423:
424: SELECTACCESSRANGE + ADVANCEDFUNCTIONCONTROL,
425:
426: OW, // Set either 800X600 or 1024X768
427: 0x4ae8, 0x07, // hi-res mode.
428:
429: SELECTACCESSRANGE + VARIOUSVGA,
430:
431: OB, // Set Misc out reg for external clock
432: 0x3c2, 0xef,
433:
434: SELECTACCESSRANGE + SYSTEMCONTROL,
435:
436: OW, // Unlock the SC regs
437: 0x3d4, 0xa039,
438:
439: METAOUT+SETCLK, // Set the clock for 65 Mhz
440:
441: METAOUT+VBLANK, // Wait for the clock to settle down
442: METAOUT+VBLANK, // S3 product alert Synchronization &
443: METAOUT+VBLANK, // Clock Skew.
444: METAOUT+VBLANK,
445: METAOUT+VBLANK,
446: METAOUT+VBLANK,
447:
448: OW, // Lock the SC regs
449: 0x3d4, 0x0039,
450:
451: SELECTACCESSRANGE + VARIOUSVGA,
452:
453: OB, // Turn on the screen - in the sequencer
454: 0x3c4, 0x01,
455:
456: METAOUT+MASKOUT,
457: 0x3c5, 0xdf, 0x0,
458:
459: METAOUT+VBLANK, // Wait the monitor to settle down
460: METAOUT+VBLANK,
461:
462: OW, // Enable all the planes through the DAC
463: 0x3c6, 0xff,
464:
465: EOD
466:
467: };
468:
469: /*****************************************************************************
470: * S3 - 928 1024 X 768, 800 X 600, & 640 X 480 Enhanced mode init.
471: ****************************************************************************/
472: USHORT S3_928_Enhanced_Mode[] = {
473:
474: SELECTACCESSRANGE + VARIOUSVGA,
475:
476: OB, // Make the screen dark
477: 0x3c6, 0x00,
478:
479: OW, // Async Reset
480: 0x3c4, 0x0100,
481:
482: OWM, // Sequencer Registers
483: 0x3c4, 5,
484: 0x0300, 0x0101, 0x0F02, 0x0003, 0x0e04,
485:
486: METAOUT+INDXOUT, // Program the GDC
487: 0x3ce,
488: 9, 0,
489: 0x00, 0x00, 0x00, 0x00, 0x00,
490: 0x00, 0x05, 0x0f, 0xff,
491:
492: SELECTACCESSRANGE + SYSTEMCONTROL,
493:
494: OW, // Unlock the S3 specific regs
495: 0x3d4, 0x4838,
496:
497: OW, // Unlock the more S3 specific regs
498: 0x3d4, 0xA039,
499:
500: METAOUT+SETCRTC, // Program the CRTC regs
501:
502: OW, // Set mode control
503: 0X3D4, 0x0242, // dot clock select
504:
505: OW, // memory configuration reg
506: 0X3D4, 0x8D31,
507:
508: OW, // extended system control reg
509: 0X3D4, 0x0050,
510:
511: OW, // backward compatibility 2 reg
512: 0X3D4, 0x2033,
513:
514: OB, // extended mode reg
515: 0x3D4, 0x43,
516:
517: METAOUT+MASKOUT,
518: 0x3D5, 0x10, 0x00,
519:
520: OW, // extended system control reg 2
521: 0X3D4, 0x4051,
522:
523: OW, // general output port
524: 0X3D4, 0x025c,
525:
526: // METAOUT+BUSTEST,
527:
528: OW,
529: 0x3d4, 0x0a5a, // Set the low byte of the LAW
530:
531: OW,
532: 0x3d4, 0x0059, // Set the high byte of the LAW
533:
534: IB, // Prepare to prgram the ACT
535: 0x3da,
536:
537: SELECTACCESSRANGE + VARIOUSVGA,
538:
539: METAOUT+ATCOUT, // Program the ATC
540: 0x3c0,
541: 21, 0,
542: 0x00, 0x01, 0x02, 0x03, 0x04,
543: 0x05, 0x06, 0x07, 0x08, 0x09,
544: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
545: 0x0f, 0x41, 0x00, 0x0f, 0x00,
546: 0x00,
547:
548: SELECTACCESSRANGE + SYSTEMCONTROL,
549:
550: IB, // Set ATC FF to index
551: 0x3da,
552:
553: SELECTACCESSRANGE + VARIOUSVGA,
554:
555: OB, // Enable the palette
556: 0x3c0, 0x20,
557:
558: SELECTACCESSRANGE + SYSTEMCONTROL,
559:
560: OW, // Enable 8514/a reg access
561: 0x3d4, 0x0140,
562:
563: OB, // Turn off H/W Graphics Cursor
564: 0x3d4, 0x45,
565:
566: METAOUT+MASKOUT,
567: 0x3d5, 0xfe, 0x0,
568:
569: OW, // Set the graphic cursor fg color
570: 0x3d4, 0xff0e,
571:
572: OW, // Set the graphic cursor bg color
573: 0x3d4, 0x000f,
574:
575: OB, // Set the Misc 1 reg
576: 0x3d4, 0x3a,
577:
578: METAOUT+MASKOUT,
579: 0x3d5, 0x62, 0x15,
580:
581: OB, // Disable 2K X 1K X 4 plane
582: 0x3d4, 0x31,
583:
584: METAOUT+MASKOUT,
585: 0x3d5, 0xe4, 0x08,
586:
587: OB, // Disable multiple pages
588: 0x3d4, 0x32,
589:
590: METAOUT+MASKOUT,
591: 0x3d5, 0xbf, 0x0,
592:
593: SELECTACCESSRANGE + ADVANCEDFUNCTIONCONTROL,
594:
595: OW, // Set either 800X600 or 1024X768
596: 0x4ae8, 0x07, // hi-res mode.
597:
598: SELECTACCESSRANGE + VARIOUSVGA,
599:
600: OB, // Set Misc out reg for external clock
601: 0x3c2, 0xef,
602:
603: METAOUT+SETCLK, // Set the clock
604:
605: METAOUT+DELAY, // Wait for the clock to settle down
606: 0x400, // S3 product alert Synchronization &
607: // Clock Skew.
608: METAOUT+VBLANK,
609: METAOUT+VBLANK,
610:
611: METAOUT+MASKOUT,
612: 0x3c5, 0xdf, 0x0,
613:
614: METAOUT+DELAY, // Wait for about 1 millisecond
615: 0x400, // for the monitor to settle down
616:
617: OW, // Enable all the planes through the DAC
618: 0x3c6, 0xff,
619:
620: SELECTACCESSRANGE + SYSTEMCONTROL,
621:
622: OW, // Lock S3 specific regs
623: 0x3d4, 0x0038,
624:
625: OW, // Lock more S3 specific regs
626: 0x3d4, 0x0039,
627:
628: EOD
629:
630: };
631:
632:
633: /*****************************************************************************
634: * S3 - 928 1280 X 1024 Enhanced mode init.
635: ****************************************************************************/
636: USHORT S3_928_1280_Enhanced_Mode[] = {
637:
638: SELECTACCESSRANGE + VARIOUSVGA,
639:
640: OB, // Make the screen dark
641: 0x3c6, 0x00,
642:
643: OW, // Async Reset
644: 0x3c4, 0x0100,
645:
646: OWM, // Sequencer Registers
647: 0x3c4,
648: 5,
649: 0x0300, 0x0101, 0x0F02, 0x0003, 0x0e04,
650:
651: METAOUT+INDXOUT, // Program the GDC
652: 0x3ce,
653: 9, 0,
654: 0x00, 0x00, 0x00, 0x00, 0x00,
655: 0x00, 0x05, 0x0f, 0xff,
656:
657: SELECTACCESSRANGE + SYSTEMCONTROL,
658:
659: OW, // Unlock the S3 specific regs
660: 0x3d4, 0x4838,
661:
662: OW, // Unlock the more S3 specific regs
663: 0x3d4, 0xA039,
664:
665: METAOUT+SETCRTC, // Program the CRTC regs
666:
667: // Set the Bt 485 DAC.
668:
669: OW, // hardware graphics cursor mode reg
670: 0X3D4, 0x2045,
671:
672: OW, // Enable access to Bt 485 CmdReg3
673: 0x3D4, 0x2955, // disable the DAC
674:
675: SELECTACCESSRANGE + VARIOUSVGA,
676:
677: OB,
678: 0x3C6, 0x80, // Bt 485 - CR0
679:
680: METAOUT+DELAY,
681: 0x400,
682:
683: SELECTACCESSRANGE + SYSTEMCONTROL,
684:
685: OW, // S3 extended video DAC control reg
686: 0x3D4, 0x2A55,
687:
688: SELECTACCESSRANGE + VARIOUSVGA,
689:
690: OB,
691: 0x3C8, 0x40, // Bt 485 - CR1
692:
693: METAOUT+DELAY,
694: 0x400,
695:
696: OB,
697: 0x3C9, 0x30, // Bt 485 - CR2
698:
699: METAOUT+DELAY,
700: 0x400,
701:
702: SELECTACCESSRANGE + SYSTEMCONTROL,
703:
704: OW, // S3 extened video DAC control reg
705: 0x3D4, 0x2855,
706:
707: SELECTACCESSRANGE + VARIOUSVGA,
708:
709: OB, // Bt 485
710: 0x3c8, 0x01,
711:
712: METAOUT+DELAY,
713: 0x400,
714:
715: SELECTACCESSRANGE + SYSTEMCONTROL,
716:
717: OW, // S3 extened video DAC control reg
718: 0x3D4, 0x2A55,
719:
720: SELECTACCESSRANGE + VARIOUSVGA,
721:
722: OB, // Bt 485 - CR3
723: 0x3c6, 0x08,
724:
725: METAOUT+DELAY,
726: 0x400,
727:
728: SELECTACCESSRANGE + SYSTEMCONTROL,
729:
730: OW, // Reset the palette index
731: 0x3d4, 0x2855,
732:
733: OW, // Set mode control
734: 0X3D4, 0x0242, // dot clock select
735:
736: METAOUT+DELAY,
737: 0x400,
738:
739: OW, // memory configuration
740: 0X3D4, 0x8f31,
741:
742: OW,
743: 0X3D4, 0x153a,
744:
745: OW, // extended system control reg
746: 0X3D4, 0x0050,
747:
748: OW, // backward compatibility reg
749: 0X3D4, 0x2033,
750:
751: OB, // extended mode reg
752: 0x3D4, 0x43,
753:
754: METAOUT+MASKOUT,
755: 0x3D5, 0x10, 0x00,
756:
757: OW, // extended system control reg 2
758: 0X3D4, 0x5051,
759:
760: OW,
761: 0X3D4, 0x025c, // flash bits, 20 packed mode.
762:
763: // METAOUT+BUSTEST,
764:
765: OW,
766: 0x3d4, 0x0a5a, // Set the low byte of the LAW
767:
768: OW,
769: 0x3d4, 0x0059, // Set the high byte of the LAW
770:
771: IB, // Prepare to prgram the ATC
772: 0x3da,
773:
774: SELECTACCESSRANGE + VARIOUSVGA,
775:
776: METAOUT+ATCOUT, // Program the ATC
777: 0x3c0,
778: 21, 0,
779: 0x00, 0x01, 0x02, 0x03, 0x04,
780: 0x05, 0x06, 0x07, 0x08, 0x09,
781: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
782: 0x0f, 0x41, 0x00, 0x0f, 0x00,
783: 0x00,
784:
785: SELECTACCESSRANGE + SYSTEMCONTROL,
786:
787: IB, // Set ATC FF to index
788: 0x3da,
789:
790: SELECTACCESSRANGE + VARIOUSVGA,
791:
792: OB, // Enable the palette
793: 0x3c0, 0x20,
794:
795: SELECTACCESSRANGE + SYSTEMCONTROL,
796:
797: OW, // Enable 8514/a reg access
798: 0x3d4, 0x0140,
799:
800: SELECTACCESSRANGE + ADVANCEDFUNCTIONCONTROL,
801:
802: OW, // Galen said set to 0
803: 0x4ae8, 0x03, //
804:
805: SELECTACCESSRANGE + VARIOUSVGA,
806:
807: OB, // Set Misc out reg for external clock
808: 0x3c2, 0xef,
809:
810: METAOUT+SETCLK, // Set the clock
811:
812: METAOUT+DELAY, // Wait for the clock to settle down
813: 0x400, // S3 product alert Synchronization &
814: // Clock Skew.
815: METAOUT+VBLANK,
816: METAOUT+VBLANK,
817:
818: METAOUT+MASKOUT,
819: 0x3c5, 0xdf, 0x0,
820:
821: METAOUT+DELAY, // Wait for about 1 millisecond
822: 0x400, // for the monitor to settle down
823:
824: OW, // Enable all the planes through the DAC
825: 0x3c6, 0xff,
826:
827: SELECTACCESSRANGE + SYSTEMCONTROL,
828:
829: OW, // Lock S3 specific regs
830: 0x3d4, 0x0038,
831:
832: OW, // Lock more S3 specific regs
833: 0x3d4, 0x0039,
834:
835: EOD
836:
837: };
838:
839: /******************************************************************************
840: * 911/924 CRTC Values
841: *****************************************************************************/
842:
843: USHORT crtc911_640x480x60Hz[] = {
844:
845: SELECTACCESSRANGE + SYSTEMCONTROL,
846:
847: OW, // Unlock the S3 specific regs
848: 0x3d4, 0x4838,
849:
850: OW, // Data Xfer Execution Position reg
851: 0x3d4, 0x5a3b,
852:
853: OW, // S3R4 - Backwards Compatibility 3
854: 0x3d4, 0x1034,
855:
856: OW, // Lock S3 specific regs
857: 0x3d4, 0x0038,
858:
859: OW, // Unprotect CRTC regs
860: 0x3d4, 0x0011,
861:
862: METAOUT+INDXOUT, // Program the CRTC regs
863: 0x3d4,
864: 25, 0,
865: 0x5f, 0x4f, 0x50, 0x82, 0x54,
866: 0x80, 0x0b, 0x3e, 0x00, 0x40,
867: 0x00, 0x00, 0x00, 0x00, 0x00,
868: 0x00, 0xea, 0x8c, 0xdf, 0x80,
869: 0x60, 0xe7, 0x04, 0xab, 0xff,
870:
871: EOD
872: };
873:
874: USHORT crtc911_800x600x60Hz[] = {
875:
876: SELECTACCESSRANGE + SYSTEMCONTROL,
877:
878: OW, // Unlock the S3 specific regs
879: 0x3d4, 0x4838,
880:
881: OW, // Data Xfer Execution Position reg
882: 0x3d4, 0x7a3b,
883:
884: OW, // S3R4 - Backwards Compatibility 3
885: 0x3d4, 0x1034,
886:
887: OW, // Lock S3 specific regs
888: 0x3d4, 0x0038,
889:
890: OW, // Unprotect CRTC regs
891: 0x3d4, 0x0011,
892:
893: METAOUT+INDXOUT, // Program the CRTC regs
894: 0x3d4,
895: 25, 0,
896: 0x7f, 0x63, 0x64, 0x82, 0x6a,
897: 0x1a, 0x74, 0xf0, 0x00, 0x60,
898: 0x00, 0x00, 0x00, 0x00, 0x00,
899: 0x00, 0x58, 0x8c, 0x57, 0x80,
900: 0x00, 0x57, 0x73, 0xe3, 0xff,
901:
902:
903: EOD
904: };
905:
906: USHORT crtc911_1024x768x60Hz[] = {
907:
908: SELECTACCESSRANGE + SYSTEMCONTROL,
909:
910: OW, // Unlock the S3 specific regs
911: 0x3d4, 0x4838,
912:
913: OW, // Data Xfer Execution Position reg
914: 0x3d4, 0x9f3b,
915:
916: OW, // S3R4 - Backwards Compatibility 3
917: 0x3d4, 0x1034,
918:
919: OW, // Lock S3 specific regs
920: 0x3d4, 0x0038,
921:
922: OW, // Unprotect CRTC regs
923: 0x3d4, 0x0011,
924:
925: METAOUT+INDXOUT, // Program the CRTC
926: 0x3d4,
927: 25, 0,
928: 0xa4, 0x7f, 0x80, 0x87, 0x84,
929: 0x95, 0x25, 0xf5, 0x00, 0x60,
930: 0x00, 0x00, 0x00, 0x00, 0x00,
931: 0x00, 0x02, 0x87, 0xff, 0x80,
932: 0x60, 0xff, 0x21, 0xab, 0xff,
933:
934: EOD
935: };
936:
937:
938:
939: USHORT crtc911_640x480x70Hz[] = {
940:
941: SELECTACCESSRANGE + SYSTEMCONTROL,
942:
943: OW, // Unlock the S3 specific regs
944: 0x3d4, 0x4838,
945:
946: OW, // Data Xfer Execution Position reg
947: 0x3d4, 0x5e3b,
948:
949: OW, // S3R4 - Backwards Compatibility 3
950: 0x3d4, 0x1034,
951:
952: OW, // Lock S3 specific regs
953: 0x3d4, 0x0038,
954:
955: OW, // Unprotect CRTC regs
956: 0x3d4, 0x0011,
957:
958: METAOUT+INDXOUT, // Program the CRTC regs
959: 0x3d4,
960: 25, 0,
961: 0x63, 0x4f, 0x50, 0x86, 0x53,
962: 0x97, 0x07, 0x3e, 0x00, 0x40,
963: 0x00, 0x00, 0x00, 0x00, 0x00,
964: 0x00, 0xe8, 0x8b, 0xdf, 0x80,
965: 0x60, 0xdf, 0x07, 0xab, 0xff,
966:
967:
968: EOD
969: };
970:
971: USHORT crtc911_800x600x70Hz[] = {
972:
973: SELECTACCESSRANGE + SYSTEMCONTROL,
974:
975: OW, // Unlock the S3 specific regs
976: 0x3d4, 0x4838,
977:
978: OW, // Data Xfer Execution Position reg
979: 0x3d4, 0x783b,
980:
981: OW, // S3R4 - Backwards Compatibility 3
982: 0x3d4, 0x1034,
983:
984: OW, // Lock S3 specific regs
985: 0x3d4, 0x0038,
986:
987: OW, // Unprotect CRTC regs
988: 0x3d4, 0x0011,
989:
990: METAOUT+INDXOUT, // Program the CRTC regs
991: 0x3d4,
992: 25, 0,
993: 0x7d, 0x63, 0x64, 0x80, 0x69,
994: 0x1a, 0x98, 0xf0, 0x00, 0x60,
995: 0x00, 0x00, 0x00, 0x00, 0x00,
996: 0x00, 0x7c, 0xa2, 0x57, 0x80,
997: 0x00, 0x57, 0x98, 0xe3, 0xff,
998:
999:
1000:
1001: EOD
1002: };
1003:
1004: USHORT crtc911_1024x768x70Hz[] = {
1005:
1006: SELECTACCESSRANGE + SYSTEMCONTROL,
1007:
1008: OW, // Unlock the S3 specific regs
1009: 0x3d4, 0x4838,
1010:
1011: OW, // Data Xfer Execution Position reg
1012: 0x3d4, 0x9d3b,
1013:
1014: OW, // S3R4 - Backwards Compatibility 3
1015: 0x3d4, 0x1034,
1016:
1017: OW, // Lock S3 specific regs
1018: 0x3d4, 0x0038,
1019:
1020: OW, // Unprotect CRTC regs
1021: 0x3d4, 0x0011,
1022:
1023: METAOUT+INDXOUT, // Program the CRTC regs
1024: 0x3d4,
1025: 25, 0,
1026: 0xa2, 0x7f, 0x80, 0x85, 0x84,
1027: 0x95, 0x24, 0xf5, 0x00, 0x60,
1028: 0x00, 0x00, 0x00, 0x00, 0x00,
1029: 0x00, 0x02, 0x88, 0xff, 0x80,
1030: 0x60, 0xff, 0x24, 0xab, 0xff,
1031:
1032: EOD
1033: };
1034:
1035: /*****************************************************************************
1036: * 801 / 805 CRTC values
1037: ****************************************************************************/
1038:
1039: USHORT crtc801_640x480x60Hz[] = {
1040:
1041: SELECTACCESSRANGE + SYSTEMCONTROL,
1042:
1043: OW, // Unlock the S3 specific regs
1044: 0x3d4, 0x4838,
1045:
1046: OW, // Unlock the more S3 specific regs
1047: 0x3d4, 0xA039,
1048:
1049: OW, // Data Xfer Execution Position reg
1050: 0x3d4, 0x5a3b,
1051:
1052: OW, // S3R4 - Backwards Compatibility 3
1053: 0x3d4, 0x1034,
1054:
1055: OW, // Unprotect CRTC regs
1056: 0x3d4, 0x0011,
1057:
1058: METAOUT+INDXOUT, // Program the CRTC regs
1059: 0x3d4,
1060: 25, 0,
1061: 0x5f, 0x4f, 0x50, 0x82, 0x54,
1062: 0x80, 0x0b, 0x3e, 0x00, 0x40,
1063: 0x00, 0x00, 0x00, 0x00, 0x00,
1064: 0x00, 0xea, 0x8c, 0xdf, 0x80,
1065: 0x60, 0xe7, 0x04, 0xab, 0xff,
1066:
1067: OW,
1068: 0X3D4, 0x005d,
1069:
1070: OW,
1071: 0X3D4, 0x005e,
1072:
1073: EOD
1074: };
1075:
1076: USHORT crtc801_640x480x70Hz[] = {
1077:
1078: SELECTACCESSRANGE + SYSTEMCONTROL,
1079:
1080: OW, // Unlock the S3 specific regs
1081: 0x3d4, 0x4838,
1082:
1083: OW, // Unlock the more S3 specific regs
1084: 0x3d4, 0xA039,
1085:
1086: OW, // Data Xfer Execution Position reg
1087: 0x3d4, 0x5e3b,
1088:
1089: OW, // S3R4 - Backwards Compatibility 3
1090: 0x3d4, 0x1034,
1091:
1092: OW, // Unprotect CRTC regs
1093: 0x3d4, 0x0011,
1094:
1095: METAOUT+INDXOUT, // Program the CRTC regs
1096: 0x3d4,
1097: 25, 0,
1098: 0x63, 0x4f, 0x50, 0x86, 0x53,
1099: 0x97, 0x07, 0x3e, 0x00, 0x40,
1100: 0x00, 0x00, 0x00, 0x00, 0x00,
1101: 0x00, 0xe8, 0x8b, 0xdf, 0x80,
1102: 0x60, 0xdf, 0x07, 0xab, 0xff,
1103:
1104: OW,
1105: 0X3D4, 0x005d,
1106:
1107: OW,
1108: 0X3D4, 0x005e,
1109:
1110: EOD
1111: };
1112:
1113:
1114:
1115: USHORT crtc801_800x600x60Hz[] = {
1116:
1117: SELECTACCESSRANGE + SYSTEMCONTROL,
1118:
1119: OW, // Unlock the S3 specific regs
1120: 0x3d4, 0x4838,
1121:
1122: OW, // Unlock the more S3 specific regs
1123: 0x3d4, 0xA039,
1124:
1125: OW, // Data Xfer Execution Position reg
1126: 0x3d4, 0x7a3b,
1127:
1128: OW, // S3R4 - Backwards Compatibility 3
1129: 0x3d4, 0x1034,
1130:
1131: OW, // Unprotect CRTC regs
1132: 0x3d4, 0x0011,
1133:
1134: METAOUT+INDXOUT, // Program the CRTC regs
1135: 0x3d4,
1136: 25, 0,
1137: 0x7f, 0x63, 0x64, 0x82,
1138: 0x6a, 0x1a, 0x74, 0xf0,
1139: 0x00, 0x60, 0x00, 0x00,
1140: 0x00, 0x00, 0xff, 0x00,
1141: 0x58, 0x8c, 0x57, 0x80,
1142: 0x00, 0x57, 0x73, 0xe3,
1143: 0xff,
1144:
1145: OW,
1146: 0X3D4, 0x005d,
1147:
1148: OW,
1149: 0X3D4, 0x005e,
1150:
1151: EOD
1152: };
1153:
1154: USHORT crtc801_800x600x70Hz[] = {
1155:
1156: SELECTACCESSRANGE + SYSTEMCONTROL,
1157:
1158: OW, // Unlock the S3 specific regs
1159: 0x3d4, 0x4838,
1160:
1161: OW, // Unlock the more S3 specific regs
1162: 0x3d4, 0xA039,
1163:
1164: OW, // Data Xfer Execution Position reg
1165: 0x3d4, 0x783b,
1166:
1167: OW, // S3R4 - Backwards Compatibility 3
1168: 0x3d4, 0x1034,
1169:
1170: OW, // Unprotect CRTC regs
1171: 0x3d4, 0x0011,
1172:
1173: METAOUT+INDXOUT, // Program the CRTC regs
1174: 0x3d4,
1175: 25, 0,
1176: 0x7d, 0x63, 0x64, 0x80,
1177: 0x6c, 0x1b, 0x98, 0xf0,
1178: 0x00, 0x60, 0x00, 0x00,
1179: 0x00, 0x00, 0xff, 0x00,
1180: 0x7c, 0xa2, 0x57, 0x80,
1181: 0x00, 0x57, 0x98, 0xe3,
1182: 0xff,
1183:
1184: OW,
1185: 0X3D4, 0x005d,
1186:
1187: OW,
1188: 0X3D4, 0x005e,
1189:
1190: EOD
1191: };
1192:
1193:
1194:
1195:
1196: USHORT crtc801_1024x768x60Hz[] = {
1197:
1198: SELECTACCESSRANGE + SYSTEMCONTROL,
1199:
1200: OW, // Unlock the S3 specific regs
1201: 0x3d4, 0x4838,
1202:
1203: OW, // Unlock the more S3 specific regs
1204: 0x3d4, 0xA039,
1205:
1206: OW, // Data Xfer Execution Position reg
1207: 0x3d4, 0x9d3b,
1208:
1209: OW, // S3R4 - Backwards Compatibility 3
1210: 0x3d4, 0x1034,
1211:
1212: OW, // Unprotect CRTC regs
1213: 0x3d4, 0x0011,
1214:
1215: METAOUT+INDXOUT, // Program the CRTC regs
1216: 0x3d4,
1217: 25, 0,
1218: 0xa3, 0x7f, 0x80, 0x86,
1219: 0x84, 0x95, 0x25, 0xf5,
1220: 0x00, 0x60, 0x00, 0x00,
1221: 0x00, 0x00, 0xff, 0x00,
1222: 0x02, 0x87, 0xff, 0x80,
1223: 0x60, 0xff, 0x21, 0xeb,
1224: 0xff,
1225:
1226: OW,
1227: 0X3D4, 0x005d,
1228:
1229: OW,
1230: 0X3D4, 0x005e,
1231:
1232: EOD
1233: };
1234:
1235: USHORT crtc801_1024x768x70Hz[] = {
1236:
1237: SELECTACCESSRANGE + SYSTEMCONTROL,
1238:
1239: OW, // Unlock the S3 specific regs
1240: 0x3d4, 0x4838,
1241:
1242: OW, // Unlock the more S3 specific regs
1243: 0x3d4, 0xA039,
1244:
1245: OW, // Data Xfer Execution Position reg
1246: 0x3d4, 0x9d3b,
1247:
1248: OW, // S3R4 - Backwards Compatibility 3
1249: 0x3d4, 0x1034,
1250:
1251: OW, // Unprotect CRTC regs
1252: 0x3d4, 0x0011,
1253:
1254: METAOUT+INDXOUT, // Program the CRTC regs
1255: 0x3d4,
1256: 25, 0,
1257: 0xa1, 0x7f, 0x80, 0x84,
1258: 0x84, 0x95, 0x24, 0xf5,
1259: 0x00, 0x60, 0x00, 0x00,
1260: 0x00, 0x00, 0x0b, 0x00,
1261: 0x02, 0x88, 0xff, 0x80,
1262: 0x60, 0xff, 0x24, 0xeb,
1263: 0xff,
1264:
1265: OW,
1266: 0X3D4, 0x005d,
1267:
1268: OW,
1269: 0X3D4, 0x005e,
1270:
1271: EOD
1272: };
1273:
1274: /*****************************************************************************
1275: * 928 CRTC values
1276: ****************************************************************************/
1277:
1278: USHORT crtc928_640x480x60Hz[] = {
1279:
1280: SELECTACCESSRANGE + SYSTEMCONTROL,
1281:
1282: OW, // Unlock the S3 specific regs
1283: 0x3d4, 0x4838,
1284:
1285: OW, // Unlock the more S3 specific regs
1286: 0x3d4, 0xA039,
1287:
1288: OW, // Data Xfer Execution Position reg
1289: 0x3d4, 0x5a3b,
1290:
1291: OW, // S3R4 - Backwards Compatibility 3
1292: 0x3d4, 0x1034,
1293:
1294: OW, // Unprotect CRTC regs
1295: 0x3d4, 0x0011,
1296:
1297: METAOUT+INDXOUT, // Program the CRTC regs
1298: 0x3d4,
1299: 25, 0,
1300: 0x5f, 0x4f, 0x50, 0x82, 0x54,
1301: 0x80, 0x0b, 0x3e, 0x00, 0x40,
1302: 0x00, 0x00, 0x00, 0x00, 0x00,
1303: 0x00, 0xea, 0x8c, 0xdf, 0x80,
1304: 0x60, 0xe7, 0x04, 0xab, 0xff,
1305:
1306: OW,
1307: 0X3D4, 0x005d,
1308:
1309: OW,
1310: 0X3D4, 0x005e,
1311:
1312: EOD
1313: };
1314:
1315: USHORT crtc928_640x480x70Hz[] = {
1316:
1317: SELECTACCESSRANGE + SYSTEMCONTROL,
1318:
1319: OW, // Unlock the S3 specific regs
1320: 0x3d4, 0x4838,
1321:
1322: OW, // Unlock the more S3 specific regs
1323: 0x3d4, 0xA039,
1324:
1325: OW, // Data Xfer Execution Position reg
1326: 0x3d4, 0x5e3b,
1327:
1328: OW, // S3R4 - Backwards Compatibility 3
1329: 0x3d4, 0x1034,
1330:
1331: OW, // Unprotect CRTC regs
1332: 0x3d4, 0x0011,
1333:
1334: METAOUT+INDXOUT, // Program the CRTC regs
1335: 0x3d4,
1336: 25, 0,
1337: 0x63, 0x4f, 0x50, 0x86, 0x53,
1338: 0x97, 0x07, 0x3e, 0x00, 0x40,
1339: 0x00, 0x00, 0x00, 0x00, 0x00,
1340: 0x00, 0xe8, 0x8b, 0xdf, 0x80,
1341: 0x60, 0xdf, 0x07, 0xab, 0xff,
1342:
1343: OW,
1344: 0X3D4, 0x005d,
1345:
1346: OW,
1347: 0X3D4, 0x005e,
1348:
1349: EOD
1350: };
1351:
1352:
1353:
1354: USHORT crtc928_800x600x60Hz[] = {
1355:
1356: SELECTACCESSRANGE + SYSTEMCONTROL,
1357:
1358: OW, // Unlock the S3 specific regs
1359: 0x3d4, 0x4838,
1360:
1361: OW, // Unlock the more S3 specific regs
1362: 0x3d4, 0xA039,
1363:
1364: OW, // Data Xfer Execution Position reg
1365: 0x3d4, 0x7a3b,
1366:
1367: OW, // S3R4 - Backwards Compatibility 3
1368: 0x3d4, 0x1034,
1369:
1370: OW, // Unprotect CRTC regs
1371: 0x3d4, 0x0011,
1372:
1373: METAOUT+INDXOUT, // Program the CRTC regs
1374: 0x3d4,
1375: 25, 0,
1376: 0x7f, 0x63, 0x64, 0x82,
1377: 0x6a, 0x1a, 0x74, 0xf0,
1378: 0x00, 0x60, 0x00, 0x00,
1379: 0x00, 0x00, 0xff, 0x00,
1380: 0x58, 0x8c, 0x57, 0x80,
1381: 0x00, 0x57, 0x73, 0xe3,
1382: 0xff,
1383:
1384: OW,
1385: 0X3D4, 0x005d,
1386:
1387: OW,
1388: 0X3D4, 0x005e,
1389:
1390: EOD
1391: };
1392:
1393: USHORT crtc928_800x600x70Hz[] = {
1394:
1395: SELECTACCESSRANGE + SYSTEMCONTROL,
1396:
1397: OW, // Unlock the S3 specific regs
1398: 0x3d4, 0x4838,
1399:
1400: OW, // Unlock the more S3 specific regs
1401: 0x3d4, 0xA039,
1402:
1403: OW, // Data Xfer Execution Position reg
1404: 0x3d4, 0x783b,
1405:
1406: OW, // S3R4 - Backwards Compatibility 3
1407: 0x3d4, 0x1034,
1408:
1409: OW, // Unprotect CRTC regs
1410: 0x3d4, 0x0011,
1411:
1412: METAOUT+INDXOUT, // Program the CRTC regs
1413: 0x3d4,
1414: 25, 0,
1415: 0x7d, 0x63, 0x64, 0x80,
1416: 0x6c, 0x1b, 0x98, 0xf0,
1417: 0x00, 0x60, 0x00, 0x00,
1418: 0x00, 0x00, 0xff, 0x00,
1419: 0x7c, 0xa2, 0x57, 0x80,
1420: 0x00, 0x57, 0x98, 0xe3,
1421: 0xff,
1422:
1423: OW,
1424: 0X3D4, 0x005d,
1425:
1426: OW,
1427: 0X3D4, 0x005e,
1428:
1429: EOD
1430: };
1431:
1432:
1433:
1434: /******************************************************************************
1435: * CRTC values for S3-928 in 1024x768 @ 60Hz
1436: *****************************************************************************/
1437: USHORT crtc928_1024x768x60Hz[] = {
1438:
1439: SELECTACCESSRANGE + SYSTEMCONTROL,
1440:
1441: OW, // S3R4 - Backwards Compatibility 3
1442: 0x3d4, 0x0034,
1443:
1444: OW, // Unprotect CRTC regs
1445: 0x3d4, 0x0011,
1446:
1447: METAOUT+INDXOUT, // Program the CRTC regs
1448: 0x3d4,
1449: 25, 0,
1450: 0xa3, 0x7f, 0x80, 0x86,
1451: 0x84, 0x95, 0x25, 0xf5,
1452: 0x00, 0x60, 0x00, 0x00,
1453: 0x00, 0x00, 0xff, 0x00,
1454: 0x02, 0x07, 0xff, 0x80,
1455: 0x60, 0xff, 0x21, 0xeb,
1456: 0xff,
1457:
1458: OW, // overlfow regs
1459: 0X3D4, 0x005d,
1460:
1461: OW, // more overflow regs
1462: 0X3D4, 0x005e,
1463:
1464: EOD
1465: };
1466:
1467: /******************************************************************************
1468: * CRTC values for S3-928 in 1024x768 @ 70Hz
1469: *****************************************************************************/
1470: USHORT crtc928_1024x768x70Hz[] = {
1471:
1472: SELECTACCESSRANGE + SYSTEMCONTROL,
1473:
1474: OW, // S3R4 - Backwards Compatibility 3
1475: 0x3d4, 0x0034,
1476:
1477: OW, // Unprotect CRTC regs
1478: 0x3d4, 0x0011,
1479:
1480: METAOUT+INDXOUT, // Program the CRTC regs
1481: 0x3d4,
1482: 25, 0,
1483: 0xa1, 0x7f, 0x80, 0x84,
1484: 0x84, 0x95, 0x24, 0xf5,
1485: 0x00, 0x60, 0x00, 0x00,
1486: 0x00, 0x00, 0x0b, 0x00,
1487: 0x02, 0x88, 0xff, 0x80,
1488: 0x60, 0xff, 0x24, 0xeb,
1489: 0xff,
1490:
1491: OW, // overflow regs
1492: 0X3D4, 0x005d,
1493:
1494: OW, // more overflow regs
1495: 0X3D4, 0x405e,
1496:
1497: EOD
1498: };
1499:
1500:
1501: /******************************************************************************
1502: * CRTC values for S3-928 in 1280X1024 @ 60Hz
1503: *****************************************************************************/
1504: USHORT crtc928_1280x1024x60Hz[] = {
1505:
1506: SELECTACCESSRANGE + SYSTEMCONTROL,
1507:
1508: OW, // S3R4 - Backwards Compatibility 3
1509: 0x3d4, 0x0034,
1510:
1511: OW, // Unprotect CRTC regs
1512: 0x3d4, 0x0011,
1513:
1514: METAOUT+INDXOUT, // Program the CRTC regs
1515: 0x3d4,
1516: 25, 0,
1517: 0x30, 0x27, 0x29, 0x96,
1518: 0x29, 0x8d, 0x28, 0x5a,
1519: 0x00, 0x60, 0x00, 0x00,
1520: 0x00, 0x00, 0xff, 0x00,
1521: 0x05, 0x09, 0xff, 0x00, // reg 19 == 50 for packed
1522: 0x00, 0xff, 0x29, 0xe3,
1523: 0xff,
1524:
1525: OW, // overflow regs
1526: 0X3D4, 0x005d,
1527:
1528: OW, // more overflow regs
1529: 0X3D4, 0x515e,
1530:
1531: EOD
1532: };
1533:
1534:
1535: /******************************************************************************
1536: * CRTC values for S3-928 in 1280X1024 @ 70Hz
1537: *****************************************************************************/
1538: USHORT crtc928_1280x1024x70Hz[] = {
1539:
1540: SELECTACCESSRANGE + SYSTEMCONTROL,
1541:
1542: OW, // S3R4 - Backwards Compatibility 3
1543: 0x3d4, 0x0034,
1544:
1545: OW, // Unprotect CRTC regs
1546: 0x3d4, 0x0011,
1547:
1548: METAOUT+INDXOUT, // Program the CRTC regs
1549: 0x3d4,
1550: 25, 0,
1551: 0x2f, 0x27, 0x29, 0x95,
1552: 0x29, 0x8d, 0x28, 0x5a,
1553: 0x00, 0x60, 0x00, 0x00,
1554: 0x00, 0x00, 0xff, 0x00,
1555: 0x05, 0x09, 0xff, 0x00, // reg 19 == 50 for packed
1556: 0x00, 0xff, 0x29, 0xe3,
1557: 0xff,
1558:
1559: OW, // overflow regs
1560: 0X3D4, 0x005d,
1561:
1562: OW, // more overflow regs
1563: 0X3D4, 0x515e,
1564:
1565: EOD
1566:
1567: };
1568:
1569: /****************************************************************************
1570: * Chip & Board Specific Mode Selection Tables
1571: ***************************************************************************/
1572:
1573:
1574: ULONG aulGenericClk[] = {
1575: 0, // 640 x 480 @ 60Hz
1576: 0, // 640 x 480 @ 60Hz
1577: 0, // 640 x 480 @ 60Hz
1578: 0, // 640 x 480 @ 60Hz
1579: 0xB, // 640 x 480 @ 72Hz
1580: 2, // 800 x 600 @ 60Hz
1581: 2, // 800 x 600 @ 60Hz
1582: 2, // 800 x 600 @ 60Hz
1583: 2, // 800 x 600 @ 60Hz
1584: 4, // 800 x 600 @ 72Hz
1585: 0xD, // 1024 x 768 @ 60Hz
1586: 0xD, // 1024 x 768 @ 60Hz
1587: 0xD, // 1024 x 768 @ 60Hz
1588: 0xD, // 1024 x 768 @ 60Hz
1589: 0xE // 1024 x 768 @ 72Hz
1590: };
1591:
1592: ULONG aulOrchidClk[] = {
1593: 0, // 640 x 480 @ 60Hz
1594: 0, // 640 x 480 @ 60Hz
1595: 0, // 640 x 480 @ 60Hz
1596: 0, // 640 x 480 @ 60Hz
1597: 2, // 640 x 480 @ 72Hz
1598: 4, // 800 x 600 @ 60Hz
1599: 4, // 800 x 600 @ 60Hz
1600: 4, // 800 x 600 @ 60Hz
1601: 4, // 800 x 600 @ 60Hz
1602: 6, // 800 x 600 @ 72Hz
1603: 7, // 1024 x 768 @ 60Hz
1604: 7, // 1024 x 768 @ 60Hz
1605: 7, // 1024 x 768 @ 60Hz
1606: 7, // 1024 x 768 @ 60Hz
1607: 0xB // 1024 x 768 @ 72Hz
1608: };
1609:
1610: ULONG aulNumberNineClk[] = {
1611: 25175000, // 640 x 480 @ 60Hz
1612: 25175000, // 640 x 480 @ 60Hz
1613: 25175000, // 640 x 480 @ 60Hz
1614: 25175000, // 640 x 480 @ 60Hz
1615: 31500000, // 640 x 480 @ 72Hz
1616: 40000000, // 800 x 600 @ 60Hz
1617: 40000000, // 800 x 600 @ 60Hz
1618: 40000000, // 800 x 600 @ 60Hz
1619: 40000000, // 800 x 600 @ 60Hz
1620: 50000000, // 800 x 600 @ 72Hz
1621: 65000000, // 1024 x 768 @ 60Hz
1622: 65000000, // 1024 x 768 @ 60Hz
1623: 65000000, // 1024 x 768 @ 60Hz
1624: 65000000, // 1024 x 768 @ 60Hz
1625: 77000000, // 1024 x 768 @ 72Hz
1626: 55000000, // 1280 X 1024 @ 60Hz
1627: 55000000, // 1280 X 1024 @ 60Hz
1628: 55000000, // 1280 X 1024 @ 60Hz
1629: 55000000, // 1280 X 1024 @ 60Hz
1630: 64000000 // 1280 X 1024 @ 72Hz
1631: };
1632:
1633: #endif
1634:
1635: //
1636: // Video mode table - Lists the information about each individual mode
1637: //
1638:
1639: //
1640: // BUGBUG
1641: // Need to create mode table values for 43Hz and 56Hz for all
1642: // resolutions.
1643: //
1644:
1645: S3_VIDEO_MODES S3Modes[] = {
1646: {
1647: FALSE, // Is this mode currently supported
1648: 0x00100000, // Required Video memory for this mode
1649: 0x0201, // Int 10 mode number
1650: NULL, NULL, NULL, // CRTC tables for NON-int10 modes.
1651: {
1652: sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
1653: 0, // Mode index used in setting the mode
1654: 640, // X Resolution, in pixels
1655: 480, // Y Resolution, in pixels
1656: 1024, // Screen stride, in bytes (distance
1657: // between the start point of two
1658: // consecutive scan lines, in bytes)
1659: 1, // Number of video memory planes
1660: 8, // Number of bits per plane
1661: 1, // Screen Frequency, in Hertz
1662: 330, // Horizontal size of screen in millimeters
1663: 240, // Vertical size of screen in millimeters
1664: 6, // Number Red pixels in DAC
1665: 6, // Number Green pixels in DAC
1666: 6, // Number Blue pixels in DAC
1667: 0x00000000, // Mask for Red Pixels in non-palette modes
1668: 0x00000000, // Mask for Green Pixels in non-palette modes
1669: 0x00000000, // Mask for Blue Pixels in non-palette modes
1670: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1671: VIDEO_MODE_MANAGED_PALETTE, // Mode description flags.
1672: 1024, // Video Memory Bitmap Width
1673: 1024 // Video Memory Bitmap Height
1674: }
1675: },
1676:
1677: {
1678: FALSE,
1679: 0x00100000,
1680: 0x0201,
1681: NULL, NULL, NULL,
1682: {
1683: sizeof(VIDEO_MODE_INFORMATION),
1684: 0,
1685: 640,
1686: 480,
1687: 1024,
1688: 1,
1689: 8,
1690: 43,
1691: 330,
1692: 240,
1693: 6,
1694: 6,
1695: 6,
1696: 0x00000000,
1697: 0x00000000,
1698: 0x00000000,
1699: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1700: VIDEO_MODE_MANAGED_PALETTE,
1701: 1024,
1702: 1024
1703: }
1704: },
1705:
1706: {
1707: FALSE,
1708: 0x00100000,
1709: 0x0201,
1710: NULL, NULL, NULL,
1711: {
1712: sizeof(VIDEO_MODE_INFORMATION),
1713: 0,
1714: 640,
1715: 480,
1716: 1024,
1717: 1,
1718: 8,
1719: 56,
1720: 330,
1721: 240,
1722: 6,
1723: 6,
1724: 6,
1725: 0x00000000,
1726: 0x00000000,
1727: 0x00000000,
1728: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1729: VIDEO_MODE_MANAGED_PALETTE,
1730: 1024,
1731: 1024
1732: }
1733: },
1734:
1735: {
1736: FALSE,
1737: 0x00100000,
1738: 0x0201,
1739: #ifndef i386
1740: crtc911_640x480x60Hz, crtc801_640x480x60Hz, crtc928_640x480x60Hz,
1741: #else
1742: NULL, NULL, NULL,
1743: #endif
1744: {
1745: sizeof(VIDEO_MODE_INFORMATION),
1746: 0,
1747: 640,
1748: 480,
1749: 1024,
1750: 1,
1751: 8,
1752: 60,
1753: 330,
1754: 240,
1755: 6,
1756: 6,
1757: 6,
1758: 0x00000000,
1759: 0x00000000,
1760: 0x00000000,
1761: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1762: VIDEO_MODE_MANAGED_PALETTE,
1763: 1024,
1764: 1024
1765: }
1766: },
1767:
1768: {
1769: FALSE,
1770: 0x00100000,
1771: 0x0201,
1772: #ifndef i386
1773: crtc911_640x480x70Hz, crtc801_640x480x70Hz, crtc928_640x480x70Hz,
1774: #else
1775: NULL, NULL, NULL,
1776: #endif
1777: {
1778: sizeof(VIDEO_MODE_INFORMATION),
1779: 0,
1780: 640,
1781: 480,
1782: 1024,
1783: 1,
1784: 8,
1785: 72,
1786: 330,
1787: 240,
1788: 6,
1789: 6,
1790: 6,
1791: 0x00000000,
1792: 0x00000000,
1793: 0x00000000,
1794: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1795: VIDEO_MODE_MANAGED_PALETTE,
1796: 1024,
1797: 1024
1798: }
1799: },
1800:
1801: {
1802: FALSE,
1803: 0x00100000,
1804: 0x0203,
1805: NULL, NULL, NULL,
1806: {
1807: sizeof(VIDEO_MODE_INFORMATION),
1808: 0,
1809: 800,
1810: 600,
1811: 1024,
1812: 1,
1813: 8,
1814: 1,
1815: 330,
1816: 240,
1817: 6,
1818: 6,
1819: 6,
1820: 0x00000000,
1821: 0x00000000,
1822: 0x00000000,
1823: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1824: VIDEO_MODE_MANAGED_PALETTE,
1825: 1024,
1826: 1024
1827: }
1828: },
1829:
1830: {
1831: FALSE,
1832: 0x00100000,
1833: 0x0203,
1834: NULL, NULL, NULL,
1835: {
1836: sizeof(VIDEO_MODE_INFORMATION),
1837: 0,
1838: 800,
1839: 600,
1840: 1024,
1841: 1,
1842: 8,
1843: 43,
1844: 330,
1845: 240,
1846: 6,
1847: 6,
1848: 6,
1849: 0x00000000,
1850: 0x00000000,
1851: 0x00000000,
1852: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1853: VIDEO_MODE_MANAGED_PALETTE,
1854: 1024,
1855: 1024
1856: }
1857: },
1858:
1859: {
1860: FALSE,
1861: 0x00100000,
1862: 0x0203,
1863: NULL, NULL, NULL,
1864: {
1865: sizeof(VIDEO_MODE_INFORMATION),
1866: 0,
1867: 800,
1868: 600,
1869: 1024,
1870: 1,
1871: 8,
1872: 56,
1873: 330,
1874: 240,
1875: 6,
1876: 6,
1877: 6,
1878: 0x00000000,
1879: 0x00000000,
1880: 0x00000000,
1881: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1882: VIDEO_MODE_MANAGED_PALETTE,
1883: 1024,
1884: 1024
1885: }
1886: },
1887:
1888: {
1889: FALSE,
1890: 0x00100000,
1891: 0x0203,
1892: #ifndef i386
1893: crtc911_800x600x60Hz, crtc801_800x600x60Hz, crtc928_800x600x60Hz,
1894: #else
1895: NULL, NULL, NULL,
1896: #endif
1897: {
1898: sizeof(VIDEO_MODE_INFORMATION),
1899: 0,
1900: 800,
1901: 600,
1902: 1024,
1903: 1,
1904: 8,
1905: 60,
1906: 330,
1907: 240,
1908: 6,
1909: 6,
1910: 6,
1911: 0x00000000,
1912: 0x00000000,
1913: 0x00000000,
1914: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1915: VIDEO_MODE_MANAGED_PALETTE,
1916: 1024,
1917: 1024
1918: }
1919: },
1920:
1921: {
1922: FALSE,
1923: 0x00100000,
1924: 0x0203,
1925: #ifndef i386
1926: crtc911_800x600x70Hz, crtc801_800x600x70Hz, crtc928_800x600x70Hz,
1927: #else
1928: NULL, NULL, NULL,
1929: #endif
1930: {
1931: sizeof(VIDEO_MODE_INFORMATION),
1932: 0,
1933: 800,
1934: 600,
1935: 1024,
1936: 1,
1937: 8,
1938: 72,
1939: 330,
1940: 240,
1941: 6,
1942: 6,
1943: 6,
1944: 0x00000000,
1945: 0x00000000,
1946: 0x00000000,
1947: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1948: VIDEO_MODE_MANAGED_PALETTE,
1949: 1024,
1950: 1024
1951: }
1952: },
1953:
1954: {
1955: FALSE,
1956: 0x00100000,
1957: 0x0205,
1958: NULL, NULL, NULL,
1959: {
1960: sizeof(VIDEO_MODE_INFORMATION),
1961: 0,
1962: 1024,
1963: 768,
1964: 1024,
1965: 1,
1966: 8,
1967: 1,
1968: 330,
1969: 240,
1970: 6,
1971: 6,
1972: 6,
1973: 0x00000000,
1974: 0x00000000,
1975: 0x00000000,
1976: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
1977: VIDEO_MODE_MANAGED_PALETTE,
1978: 1024,
1979: 1024
1980: }
1981: },
1982:
1983: {
1984: FALSE,
1985: 0x00100000,
1986: 0x0205,
1987: NULL, NULL, NULL,
1988: {
1989: sizeof(VIDEO_MODE_INFORMATION),
1990: 0,
1991: 1024,
1992: 768,
1993: 1024,
1994: 1,
1995: 8,
1996: 43,
1997: 330,
1998: 240,
1999: 6,
2000: 6,
2001: 6,
2002: 0x00000000,
2003: 0x00000000,
2004: 0x00000000,
2005: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
2006: VIDEO_MODE_MANAGED_PALETTE,
2007: 1024,
2008: 1024
2009: }
2010: },
2011:
2012: {
2013: FALSE,
2014: 0x00100000,
2015: 0x0205,
2016: NULL, NULL, NULL,
2017: {
2018: sizeof(VIDEO_MODE_INFORMATION),
2019: 0,
2020: 1024,
2021: 768,
2022: 1024,
2023: 1,
2024: 8,
2025: 56,
2026: 330,
2027: 240,
2028: 6,
2029: 6,
2030: 6,
2031: 0x00000000,
2032: 0x00000000,
2033: 0x00000000,
2034: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
2035: VIDEO_MODE_MANAGED_PALETTE,
2036: 1024,
2037: 1024
2038: }
2039: },
2040:
2041: {
2042: FALSE,
2043: 0x00100000,
2044: 0x0205,
2045: #ifndef i386
2046: crtc911_1024x768x60Hz, crtc801_1024x768x60Hz, crtc928_1024x768x60Hz,
2047: #else
2048: NULL, NULL, NULL,
2049: #endif
2050: {
2051: sizeof(VIDEO_MODE_INFORMATION),
2052: 0,
2053: 1024,
2054: 768,
2055: 1024,
2056: 1,
2057: 8,
2058: 60,
2059: 330,
2060: 240,
2061: 6,
2062: 6,
2063: 6,
2064: 0x00000000,
2065: 0x00000000,
2066: 0x00000000,
2067: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
2068: VIDEO_MODE_MANAGED_PALETTE,
2069: 1024,
2070: 1024
2071: }
2072: },
2073:
2074: {
2075: FALSE,
2076: 0x00100000,
2077: 0x0205,
2078: #ifndef i386
2079: crtc911_1024x768x70Hz, crtc801_1024x768x70Hz, crtc928_1024x768x70Hz,
2080: #else
2081: NULL, NULL, NULL,
2082: #endif
2083: {
2084: sizeof(VIDEO_MODE_INFORMATION),
2085: 0,
2086: 1024,
2087: 768,
2088: 1024,
2089: 1,
2090: 8,
2091: 72,
2092: 330,
2093: 240,
2094: 6,
2095: 6,
2096: 6,
2097: 0x00000000,
2098: 0x00000000,
2099: 0x00000000,
2100: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
2101: VIDEO_MODE_MANAGED_PALETTE,
2102: 1024,
2103: 1024
2104: }
2105: },
2106:
2107: {
2108: FALSE,
2109: 0x00300000,
2110: 0x0107,
2111: NULL, NULL, NULL,
2112: {
2113: sizeof(VIDEO_MODE_INFORMATION),
2114: 0,
2115: 1280,
2116: 1024,
2117: 2048,
2118: 1,
2119: 8,
2120: 1,
2121: 330,
2122: 240,
2123: 6,
2124: 6,
2125: 6,
2126: 0x00000000,
2127: 0x00000000,
2128: 0x00000000,
2129: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
2130: VIDEO_MODE_MANAGED_PALETTE,
2131: 2048,
2132: 1536
2133: }
2134: },
2135:
2136: {
2137: FALSE,
2138: 0x00300000,
2139: 0x0107,
2140: NULL, NULL, NULL,
2141: {
2142: sizeof(VIDEO_MODE_INFORMATION),
2143: 0,
2144: 1280,
2145: 1024,
2146: 2048,
2147: 1,
2148: 8,
2149: 43,
2150: 330,
2151: 240,
2152: 6,
2153: 6,
2154: 6,
2155: 0x00000000,
2156: 0x00000000,
2157: 0x00000000,
2158: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
2159: VIDEO_MODE_MANAGED_PALETTE,
2160: 2048,
2161: 1536
2162: }
2163: },
2164:
2165: {
2166: FALSE,
2167: 0x00300000,
2168: 0x0107,
2169: NULL, NULL, NULL,
2170: {
2171: sizeof(VIDEO_MODE_INFORMATION),
2172: 0,
2173: 1280,
2174: 1024,
2175: 2048,
2176: 1,
2177: 8,
2178: 56,
2179: 330,
2180: 240,
2181: 6,
2182: 6,
2183: 6,
2184: 0x00000000,
2185: 0x00000000,
2186: 0x00000000,
2187: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
2188: VIDEO_MODE_MANAGED_PALETTE,
2189: 2048,
2190: 1536
2191: }
2192: },
2193:
2194: {
2195: FALSE,
2196: 0x00300000,
2197: 0x0107,
2198: #ifndef i386
2199: NULL, NULL, crtc928_1280x1024x60Hz,
2200: #else
2201: NULL, NULL, NULL,
2202: #endif
2203: {
2204: sizeof(VIDEO_MODE_INFORMATION),
2205: 0,
2206: 1280,
2207: 1024,
2208: 2048,
2209: 1,
2210: 8,
2211: 60,
2212: 330,
2213: 240,
2214: 6,
2215: 6,
2216: 6,
2217: 0x00000000,
2218: 0x00000000,
2219: 0x00000000,
2220: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
2221: VIDEO_MODE_MANAGED_PALETTE,
2222: 2048,
2223: 1536
2224: }
2225: },
2226:
2227: {
2228: FALSE,
2229: 0x00300000,
2230: 0x0107,
2231: #ifndef i386
2232: NULL, NULL, crtc928_1280x1024x70Hz,
2233: #else
2234: NULL, NULL, NULL,
2235: #endif
2236: {
2237: sizeof(VIDEO_MODE_INFORMATION),
2238: 0,
2239: 1280,
2240: 1024,
2241: 2048,
2242: 1,
2243: 8,
2244: 72,
2245: 330,
2246: 240,
2247: 6,
2248: 6,
2249: 6,
2250: 0x00000000,
2251: 0x00000000,
2252: 0x00000000,
2253: VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
2254: VIDEO_MODE_MANAGED_PALETTE,
2255: 2048,
2256: 1536
2257: }
2258: }
2259: };
2260:
2261:
2262: ULONG NumS3VideoModes = sizeof(S3Modes) / sizeof(S3_VIDEO_MODES);
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.