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Annotation of ntddk/src/video/miniport/wdvga/i386/wdhard.asm, revision 1.1.1.1

1.1       root        1:         title  "Wd Hard.asm"
                      2: ;++
                      3: ;
                      4: ; Copyright (c) 1992  Microsoft Corporation
                      5: ; Copyright (c) 1993  Western Digital Corporation
                      6: ;
                      7: ; Module Name:
                      8: ;
                      9: ;     vgahard.asm
                     10: ;
                     11: ; Abstract:
                     12: ;
                     13: ;     This module implements the baning code for the WD90Cxx.
                     14: ;
                     15: ; Environment:
                     16: ;
                     17: ;    Kernel mode only.
                     18: ;
                     19: ; Author:
                     20: ;
                     21: ;    Chung-I Chiang, Harold Huang      Western Digital Corporation
                     22: ;
                     23: ; Revision History:
                     24: ;
                     25: ;
                     26: ;--
                     27: 
                     28: .386p
                     29:         .xlist
                     30: include callconv.inc                    ; calling convention macros
                     31:         .list
                     32: 
                     33: ;---------------------------------------
                     34: ;
                     35: ; Western Digital banking control port.
                     36: ;
                     37: 
                     38: SEGMENT_SELECT_PORT equ     03ceh      ;banking control here
                     39: SEQ_ADDRESS_PORT equ        03C4h      ;Sequencer Address register
                     40: WD_PR0A          equ        09h
                     41: WD_PR0B          equ        0Ah
                     42: IND_MEMORY_MODE  equ        04h        ;Memory Mode register index in Sequencer
                     43: CHAIN4_MASK      equ        08h        ;Chain4 bit in Memory Mode register
                     44: 
                     45: 
                     46: _TEXT   SEGMENT DWORD USE32 PUBLIC 'CODE'
                     47:         ASSUME  CS:FLAT, DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
                     48: 
                     49:         page ,132
                     50:         subttl  "Bank Switching Stub"
                     51: 
                     52: ;
                     53: ;    Bank switching code. This is a 1-64K-read/1-64K-write bank adapter
                     54: ;    (VideoBanked1R1W).
                     55: ;
                     56: ;    Input:
                     57: ;          EAX = desired read bank mapping
                     58: ;          EDX = desired write bank mapping
                     59: ;
                     60: ;    Note: values must be correct, with no stray bits set; no error
                     61: ;       checking is performed.
                     62: ;
                     63:        public _BankSwitchStart
                     64:        public _BankSwitchEnd
                     65: 
                     66:         align 4
                     67: 
                     68: _BankSwitchStart proc ;start of bank switch code
                     69: 
                     70:        push    ebx                     
                     71:        push    eax
                     72:        push    edx
                     73:        mov     dx,SEGMENT_SELECT_PORT
                     74:        in      al,dx
                     75:        mov     ebx,eax         ;must save 3CE current index
                     76:        pop     edx
                     77:        pop     eax
                     78: 
                     79:        push    edx
                     80:        shl     eax,12                  ;read bank in PRO0A
                     81:        mov     al,WD_PR0A
                     82:        mov     dx,SEGMENT_SELECT_PORT
                     83:        out     dx,ax
                     84:        pop     edx
                     85: 
                     86:        mov     eax,edx
                     87:        shl     eax,12                  ;write bank in PRO0B
                     88:        mov     al,WD_PR0B
                     89:        mov     dx,SEGMENT_SELECT_PORT
                     90:        out     dx,ax
                     91: 
                     92:        mov     eax,ebx                 ;restore 3CE index
                     93:        mov     dx,SEGMENT_SELECT_PORT
                     94:        out     dx,al
                     95:        pop     ebx
                     96: 
                     97:         ret           ; This should be a fatal error ...
                     98: 
                     99: _BankSwitchEnd:
                    100: 
                    101: _BankSwitchStart endp
                    102: 
                    103: _TEXT   ends
                    104:         end
                    105: 
                    106: 
                    107: 

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