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1.1 root 1: /*++
2:
3: Copyright (c) 1992 Microsoft Corporation
4: Copyright (c) 1993 Western Digital Corporation
5:
6: Module Name:
7:
8: Modeset.h
9:
10: Abstract:
11:
12: This module contains all the global data used by the Western Digital
13: 90Cxx driver.
14:
15: Environment:
16:
17: Kernel mode
18:
19: Revision History:
20:
21: --*/
22:
23: #include "cmdcnst.h"
24:
25:
26: /**************************************************************************
27: * *
28: * Western Digital Color text mode, 640x350, 8x14 char *
29: * *
30: **************************************************************************/
31:
32: USHORT WDVGA_TEXT_1[] = {
33: // SEQ index 7h-9h, 10h-14h
34: OWM, // start sync reset program up sequencer
35: SEQ_ADDRESS_PORT,
36: 8,
37: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0412,0x8013,0x1014,
38:
39: OWM,
40: SEQ_ADDRESS_PORT,
41: 5,
42: 0x0100,0x0101,0x0302,0x0003,0x0204, // program up sequencer
43:
44: OB,
45: MISC_OUTPUT_REG_WRITE_PORT,
46: 0xa3,
47:
48: OW,
49: GRAPH_ADDRESS_PORT,
50: 0x0e06,
51:
52: // EndSyncResetCmd
53: OB,
54: SEQ_ADDRESS_PORT,
55: IND_SYNC_RESET,
56:
57: OB,
58: SEQ_DATA_PORT,
59: END_SYNC_RESET_VALUE,
60:
61: // CRTC index 2ah-30h, 3eh
62: METAOUT+INDXOUT, // program crtc registers
63: CRTC_ADDRESS_PORT_COLOR,
64: 7, // count
65: 0x2a, // start index
66: 0xf0,0x05,0x00,0x00,0x00,0x42,0x00,
67:
68: OW, //
69: CRTC_ADDRESS_PORT_COLOR,
70: 0x003e,
71:
72: OW,
73: CRTC_ADDRESS_PORT_COLOR,
74: 0x0511,
75:
76: METAOUT+INDXOUT, // program crtc registers
77: CRTC_ADDRESS_PORT_COLOR,
78: VGA_NUM_CRTC_PORTS, // count
79: 0, // start index
80: 0x5F,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4d,0xb,0xc,0x0,0x0,0x0,0x0,
81: 0x83,0x85,0x5d,0x28,0x1f,0x63,0xba,0xa3,0xFF,
82:
83: IB, // prepare atc for writing
84: INPUT_STATUS_1_COLOR,
85:
86: METAOUT+ATCOUT, //
87: ATT_ADDRESS_PORT, // port
88: VGA_NUM_ATTRIB_CONT_PORTS, // count
89: 0, // start index
90: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
91: 0x00,0x0,0x0F,0x0,0x0,
92:
93: METAOUT+INDXOUT, // program graphics controller registers
94: GRAPH_ADDRESS_PORT, // port
95: 7, // count
96: 9, // start index
97: 0x00,0x00,0xc6,0x02,0x00,0x00,0x05,
98:
99: METAOUT+INDXOUT, //
100: GRAPH_ADDRESS_PORT, // port
101: VGA_NUM_GRAPH_CONT_PORTS, // count
102: 0, // start index
103: 0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
104:
105: OB,
106: DAC_PIXEL_MASK_PORT,
107: 0xFF,
108:
109: IB, // prepare atc for writing
110: INPUT_STATUS_1_COLOR,
111:
112: OB, // turn video on.
113: ATT_ADDRESS_PORT,
114: VIDEO_ENABLE,
115:
116: EOD
117: };
118:
119: #ifndef INT10_MODE_SET
120: /**************************************************************************
121: * *
122: * Western Digital Color text mode, 720x400, 9x16 char *
123: * *
124: **************************************************************************/
125:
126: USHORT WDVGA_TEXT_0[] = {
127: // SEQ index 7h-9h, 10h-14h
128: OWM, // start sync reset program up sequencer
129: SEQ_ADDRESS_PORT,
130: 8,
131: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0412,0x8013,0x1014,
132:
133: OWM,
134: SEQ_ADDRESS_PORT,
135: 5,
136: 0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
137:
138: OB,
139: MISC_OUTPUT_REG_WRITE_PORT,
140: 0x67,
141:
142: OW,
143: GRAPH_ADDRESS_PORT,
144: 0x0e06,
145:
146: // EndSyncResetCmd
147: OB,
148: SEQ_ADDRESS_PORT,
149: IND_SYNC_RESET,
150:
151: OB,
152: SEQ_DATA_PORT,
153: END_SYNC_RESET_VALUE,
154:
155: // CRTC index 2ah-30h, 3eh
156: METAOUT+INDXOUT, // program crtc registers
157: CRTC_ADDRESS_PORT_COLOR,
158: 7, // count
159: 0x2a, // start index
160: 0xf0,0x05,0x00,0x00,0x00,0x42,0x00,
161:
162: OW, //
163: CRTC_ADDRESS_PORT_COLOR,
164: 0x003e,
165:
166: OW,
167: CRTC_ADDRESS_PORT_COLOR,
168: 0x0E11,
169:
170: METAOUT+INDXOUT, // program crtc registers
171: CRTC_ADDRESS_PORT_COLOR,
172: VGA_NUM_CRTC_PORTS, // count
173: 0, // start index
174: 0x5F,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0xd,0xe,0x0,0x0,0x0,0x0,
175: 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,0xFF,
176:
177: IB, // prepare atc for writing
178: INPUT_STATUS_1_COLOR,
179:
180: METAOUT+ATCOUT, //
181: ATT_ADDRESS_PORT, // port
182: VGA_NUM_ATTRIB_CONT_PORTS, // count
183: 0, // start index
184: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
185: 0x04,0x0,0x0F,0x8,0x0,
186:
187: METAOUT+INDXOUT, // program graphics controller registers
188: GRAPH_ADDRESS_PORT, // port
189: 7, // count
190: 9, // start index
191: 0x00,0x00,0xc6,0x02,0x00,0x00,0x05,
192:
193: METAOUT+INDXOUT, //
194: GRAPH_ADDRESS_PORT, // port
195: VGA_NUM_GRAPH_CONT_PORTS, // count
196: 0, // start index
197: 0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
198:
199: OB,
200: DAC_PIXEL_MASK_PORT,
201: 0xFF,
202:
203: IB, // prepare atc for writing
204: INPUT_STATUS_1_COLOR,
205:
206: OB, // turn video on.
207: ATT_ADDRESS_PORT,
208: VIDEO_ENABLE,
209:
210: EOD
211: };
212:
213:
214: /**************************************************************************
215: * *
216: * Western Digital Color graphics mode 0x12, 640x480 16 colors *
217: * *
218: **************************************************************************/
219:
220: USHORT WDVGA_640x480[] = {
221: // SEQ index 7h-9h, 10h-14h
222: OWM, // start sync reset program up sequencer
223: SEQ_ADDRESS_PORT,
224: 8,
225: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0412,0x8013,0x1014,
226:
227: OWM, // start sync reset program up sequencer
228: SEQ_ADDRESS_PORT,
229: 5,
230: 0x0100,0x0101,0x0f02,0x0003,0x0604,
231:
232: OB,
233: MISC_OUTPUT_REG_WRITE_PORT, // Misc output register
234: 0xe3,
235:
236: OW, // Set chain mode in sync reset
237: GRAPH_ADDRESS_PORT,
238: 0x0506,
239:
240: OB, // EndSyncResetCmd
241: SEQ_ADDRESS_PORT,
242: IND_SYNC_RESET,
243:
244: OB,
245: SEQ_DATA_PORT,
246: END_SYNC_RESET_VALUE,
247:
248: // CRTC index 2ah-30h, 3eh
249: METAOUT+INDXOUT, // program crtc registers
250: CRTC_ADDRESS_PORT_COLOR,
251: 7, // count
252: 0x2a, // start index
253: 0xf0,0x05,0x00,0x00,0x00,0x42,0x00,
254:
255: OW, //
256: CRTC_ADDRESS_PORT_COLOR,
257: 0x003e,
258:
259: OW, // Unlock CRTC registers 0-7
260: CRTC_ADDRESS_PORT_COLOR,
261: 0x0511,
262:
263: METAOUT+INDXOUT, // program crtc registers
264: CRTC_ADDRESS_PORT_COLOR,
265: VGA_NUM_CRTC_PORTS, // count
266: 0, // start index
267: 0x5F,0x4F,0x50,0x82,0x54,0x80,0x0B,0x3E,0x00,0x40,0x0,0x0,0x0,0x0,0x0,0x0,
268: 0xEA,0x8C,0xDF,0x28,0x0,0xE7,0x4,0xE3,0xFF,
269:
270: IB, // prepare atc for writing
271: INPUT_STATUS_1_COLOR,
272:
273: METAOUT+ATCOUT, // program attribute controller registers
274: ATT_ADDRESS_PORT, // port
275: VGA_NUM_ATTRIB_CONT_PORTS, // count
276: 0, // start index
277: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
278: 0x01,0x0,0x0F,0x0,0x0,
279:
280: METAOUT+INDXOUT, // program graphics controller registers
281: GRAPH_ADDRESS_PORT, // port
282: 7, // count
283: 9, // start index
284: 0x00,0x00,0xc6,0x02,0x00,0x00,0x05,
285:
286: METAOUT+INDXOUT, // program graphics controller registers
287: GRAPH_ADDRESS_PORT, // port
288: VGA_NUM_GRAPH_CONT_PORTS, // count
289: 0, // start index
290: 0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
291:
292: OB, // DAC mask registers
293: DAC_PIXEL_MASK_PORT,
294: 0xFF,
295:
296: IB, // prepare atc for writing
297: INPUT_STATUS_1_COLOR,
298:
299: OB, // turn video on.
300: ATT_ADDRESS_PORT,
301: VIDEO_ENABLE,
302:
303: EOD
304: };
305:
306: /********************************************************************
307: * Western Digital 800x600 modes - vRefresh 60Hz. *
308: * *
309: *********************************************************************/
310:
311: //
312: // Color graphics mode 0x58, 800x600 16 colors 60Hz.
313: //
314: USHORT WDVGA_800x600_60hz[] = {
315: // SEQ index 7h-9h, 10h-14h
316: OWM, // start sync reset program up sequencer
317: SEQ_ADDRESS_PORT,
318: 8,
319: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0412,0x8013,0x1014,
320:
321: OWM, // start sync reset program up sequencer
322: SEQ_ADDRESS_PORT,
323: 5,
324: 0x0300,0x0101,0x0f02,0x0003,0x0604,
325:
326: OB,
327: MISC_OUTPUT_REG_WRITE_PORT, // Misc output register
328: 0x23,
329:
330: OW, // Set chain mode in sync reset
331: GRAPH_ADDRESS_PORT,
332: 0x0506,
333:
334: OB, // EndSyncResetCmd
335: SEQ_ADDRESS_PORT,
336: IND_SYNC_RESET,
337:
338: OB,
339: SEQ_DATA_PORT,
340: END_SYNC_RESET_VALUE,
341:
342: // CRTC index 2ah-30h, 3eh
343: METAOUT+INDXOUT, // program crtc registers
344: CRTC_ADDRESS_PORT_COLOR,
345: 7, // count
346: 0x2a, // start index
347: 0xf0,0x45,0x00,0x00,0x00,0x00,0x00,
348:
349: OW, // CRTC index 3e
350: CRTC_ADDRESS_PORT_COLOR,
351: 0x003e,
352:
353: OW, // Unlock CRTC registers 0-7
354: CRTC_ADDRESS_PORT_COLOR,
355: 0x0511,
356:
357: METAOUT+INDXOUT, // program crtc registers
358: CRTC_ADDRESS_PORT_COLOR,
359: VGA_NUM_CRTC_PORTS, // count
360: 0, // start index
361: 0x7f,0x63,0x64,0x82,0x6b,0x1b,0x72,0xf0,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
362: 0x58,0x8c,0x57,0x32,0x0,0x58,0x71,0xE3,0xFF,
363:
364: IB, // prepare atc for writing
365: INPUT_STATUS_1_COLOR,
366:
367: METAOUT+ATCOUT, // program attribute controller registers
368: ATT_ADDRESS_PORT, // port
369: VGA_NUM_ATTRIB_CONT_PORTS, // count
370: 0, // start index
371: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
372: 0x01,0x0,0x0F,0x0,0x0,
373:
374: // GRAPH index 9-fh
375: METAOUT+INDXOUT, // program graphics controller registers
376: GRAPH_ADDRESS_PORT, // port
377: 7, // count
378: 9, // start index
379: 0x00,0x00,0xc6,0x00,0x00,0x00,0x05,
380:
381: METAOUT+INDXOUT, // program graphics controller registers
382: GRAPH_ADDRESS_PORT, // port
383: VGA_NUM_GRAPH_CONT_PORTS, // count
384: 0, // start index
385: 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0x0FF,
386:
387: OB, // DAC mask registers
388: DAC_PIXEL_MASK_PORT,
389: 0xFF,
390:
391: IB, // prepare atc for writing
392: INPUT_STATUS_1_COLOR,
393:
394: OB, // turn video on.
395: ATT_ADDRESS_PORT,
396: VIDEO_ENABLE,
397:
398: EOD
399: };
400:
401: /********************************************************************
402: * Western Digital 800x600 modes - vRefresh6 72Hz. *
403: * *
404: *********************************************************************/
405:
406: //
407: // Color graphics mode 0x58, 800x600 16 colors 72Hz.
408: //
409: USHORT WDVGA_800x600_72hz[] = {
410: // SEQ index 7h-9h, 10h-14h
411: OWM, // start sync reset program up sequencer
412: SEQ_ADDRESS_PORT,
413: 8,
414: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0412,0x8013,0x1014,
415:
416: OWM, // start sync reset program up sequencer
417: SEQ_ADDRESS_PORT,
418: 5,
419: 0x0300,0x0101,0x0f02,0x0003,0x0604,
420:
421: OB,
422: MISC_OUTPUT_REG_WRITE_PORT, // Misc output register
423: 0x27,
424:
425: OW, // Set chain mode in sync reset
426: GRAPH_ADDRESS_PORT,
427: 0x0506,
428:
429: OB, // EndSyncResetCmd
430: SEQ_ADDRESS_PORT,
431: IND_SYNC_RESET,
432:
433: OB,
434: SEQ_DATA_PORT,
435: END_SYNC_RESET_VALUE,
436:
437: // CRTC index 2ah-30h, 3eh
438: METAOUT+INDXOUT, // program crtc registers
439: CRTC_ADDRESS_PORT_COLOR,
440: 7, // count
441: 0x2a, // start index
442: 0xf0,0x85,0x00,0x00,0x00,0x00,0x00,
443:
444: OW, // CRTC index 3e
445: CRTC_ADDRESS_PORT_COLOR,
446: 0x003e,
447:
448: OW, // Unlock CRTC registers 0-7
449: CRTC_ADDRESS_PORT_COLOR,
450: 0x0511,
451:
452: METAOUT+INDXOUT, // program crtc registers
453: CRTC_ADDRESS_PORT_COLOR,
454: VGA_NUM_CRTC_PORTS, // count
455: 0, // start index
456: 0x7e,0x63,0x64,0x81,0x6b,0x1a,0x96,0xf0,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
457: 0x6d,0xf3,0x57,0x32,0x0,0x5a,0x94,0xE3,0xFF,
458:
459: IB, // prepare atc for writing
460: INPUT_STATUS_1_COLOR,
461:
462: METAOUT+ATCOUT, // program attribute controller registers
463: ATT_ADDRESS_PORT, // port
464: VGA_NUM_ATTRIB_CONT_PORTS, // count
465: 0, // start index
466: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
467: 0x01,0x0,0x0F,0x0,0x0,
468:
469: // GRAPH index 9-fh
470: METAOUT+INDXOUT, // program graphics controller registers
471: GRAPH_ADDRESS_PORT, // port
472: 7, // count
473: 9, // start index
474: 0x00,0x00,0xc6,0x00,0x00,0x00,0x05,
475:
476: METAOUT+INDXOUT, // program graphics controller registers
477: GRAPH_ADDRESS_PORT, // port
478: VGA_NUM_GRAPH_CONT_PORTS, // count
479: 0, // start index
480: 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0x0FF,
481:
482: OB, // DAC mask registers
483: DAC_PIXEL_MASK_PORT,
484: 0xFF,
485:
486: IB, // prepare atc for writing
487: INPUT_STATUS_1_COLOR,
488:
489: OB, // turn video on.
490: ATT_ADDRESS_PORT,
491: VIDEO_ENABLE,
492:
493: EOD
494: };
495:
496: /********************************************************************
497: * Western Digital 800x600 modes - vRefresh 56Hz. *
498: * *
499: *********************************************************************/
500:
501: //
502: // Color graphics mode 0x58, 800x600 16 colors 56Hz.
503: //
504: USHORT WDVGA_800x600_56hz[] = {
505: // SEQ index 7h-9h, 10h-14h
506: OWM, // start sync reset program up sequencer
507: SEQ_ADDRESS_PORT,
508: 8,
509: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0412,0x8013,0x1014,
510:
511: OWM, // start sync reset program up sequencer
512: SEQ_ADDRESS_PORT,
513: 5,
514: 0x0300,0x0101,0x0f02,0x0003,0x0604,
515:
516: OB,
517: MISC_OUTPUT_REG_WRITE_PORT, // Misc output register
518: 0xef,
519:
520: OW, // Set chain mode in sync reset
521: GRAPH_ADDRESS_PORT,
522: 0x0506,
523:
524: OB, // EndSyncResetCmd
525: SEQ_ADDRESS_PORT,
526: IND_SYNC_RESET,
527:
528: OB,
529: SEQ_DATA_PORT,
530: END_SYNC_RESET_VALUE,
531:
532: // CRTC index 2ah-30h, 3eh
533: METAOUT+INDXOUT, // program crtc registers
534: CRTC_ADDRESS_PORT_COLOR,
535: 7, // count
536: 0x2a, // start index
537: 0xf0,0x05,0x00,0x00,0x00,0x00,0x00,
538:
539: OW, // CRTC index 3e
540: CRTC_ADDRESS_PORT_COLOR,
541: 0x003e,
542:
543: OW, // Unlock CRTC registers 0-7
544: CRTC_ADDRESS_PORT_COLOR,
545: 0x0511,
546:
547: METAOUT+INDXOUT, // program crtc registers
548: CRTC_ADDRESS_PORT_COLOR,
549: VGA_NUM_CRTC_PORTS, // count
550: 0, // start index
551: 0x7b,0x63,0x64,0x9e,0x69,0x92,0x6f,0xf0,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
552: 0x58,0x8a,0x57,0x32,0x0,0x58,0x6f,0xE3,0xFF,
553:
554: IB, // prepare atc for writing
555: INPUT_STATUS_1_COLOR,
556:
557: METAOUT+ATCOUT, // program attribute controller registers
558: ATT_ADDRESS_PORT, // port
559: VGA_NUM_ATTRIB_CONT_PORTS, // count
560: 0, // start index
561: 0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
562: 0x01,0x0,0x0F,0x0,0x0,
563:
564: // GRAPH index 9-fh
565: METAOUT+INDXOUT, // program graphics controller registers
566: GRAPH_ADDRESS_PORT, // port
567: 7, // count
568: 9, // start index
569: 0x00,0x00,0xc6,0x02,0x00,0x00,0x05,
570:
571: METAOUT+INDXOUT, // program graphics controller registers
572: GRAPH_ADDRESS_PORT, // port
573: VGA_NUM_GRAPH_CONT_PORTS, // count
574: 0, // start index
575: 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0x0FF,
576:
577: OB, // DAC mask registers
578: DAC_PIXEL_MASK_PORT,
579: 0xFF,
580:
581: IB, // prepare atc for writing
582: INPUT_STATUS_1_COLOR,
583:
584: OB, // turn video on.
585: ATT_ADDRESS_PORT,
586: VIDEO_ENABLE,
587:
588: EOD
589: };
590:
591:
592: /**************************************************************************
593: * Western Digital 1024x768 modes - vRefresh 60Hz. *
594: * *
595: **************************************************************************/
596:
597: //
598: // Color graphics mode 0x5d, 1024x768 16 colors. 60Hz non-interlace
599: //
600: USHORT WDVGA_1024x768_60hz[] = {
601: // SEQ index 7h-9h, 10h-14h
602: OWM, // start sync reset program up sequencer
603: SEQ_ADDRESS_PORT,
604: 8,
605: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0412,0x8013,0x1014,
606:
607: OWM, // start sync reset program up sequencer
608: SEQ_ADDRESS_PORT,
609: 5,
610: 0x0300,0x0101,0x0f02,0x0003,0x0604,
611:
612: OB,
613: MISC_OUTPUT_REG_WRITE_PORT, // Misc output register
614: 0xeb,
615:
616: OW, // Set chain mode in sync reset
617: GRAPH_ADDRESS_PORT,
618: 0x0506,
619:
620: OB, // EndSyncResetCmd
621: SEQ_ADDRESS_PORT,
622: IND_SYNC_RESET,
623:
624: OB,
625: SEQ_DATA_PORT,
626: END_SYNC_RESET_VALUE,
627:
628: // CRTC index 2ah-30h, 3eh
629: METAOUT+INDXOUT, // program crtc registers
630: CRTC_ADDRESS_PORT_COLOR,
631: 7, // count
632: 0x2a, // start index
633: 0xf0,0x95,0x00,0x00,0x01,0x00,0x00,
634:
635: OW, //
636: CRTC_ADDRESS_PORT_COLOR,
637: 0x003e,
638:
639: OW, // Unlock CRTC registers 0-7
640: CRTC_ADDRESS_PORT_COLOR,
641: 0x0511,
642:
643: METAOUT+INDXOUT, // program crtc registers
644: CRTC_ADDRESS_PORT_COLOR,
645: VGA_NUM_CRTC_PORTS, // count
646: 0, // start index
647: 0xa3,0x7f,0x80,0x06,0x87,0x98,0x24,0xf1,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
648: 0xff,0x85,0xff,0x40,0x0,0xff,0x23,0xE3,0xFF,
649:
650: IB, // prepare atc for writing
651: INPUT_STATUS_1_COLOR,
652:
653: METAOUT+ATCOUT, // program attribute controller registers
654: ATT_ADDRESS_PORT, // port
655: VGA_NUM_ATTRIB_CONT_PORTS, // count
656: 0, // start index
657: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
658: 0x01,0x0,0x0F,0x0,0x0,
659:
660: METAOUT+INDXOUT, // program graphics controller registers
661: GRAPH_ADDRESS_PORT, // port
662: 7, // count
663: 9, // start index
664: 0x00,0x00,0xc6,0x02,0x00,0x00,0x05,
665:
666: METAOUT+INDXOUT, // program graphics controller registers
667: GRAPH_ADDRESS_PORT, // port
668: VGA_NUM_GRAPH_CONT_PORTS, // count
669: 0, // start index
670: 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0x0FF,
671:
672:
673: OB, // DAC mask registers
674: DAC_PIXEL_MASK_PORT,
675: 0xFF,
676:
677: IB, // prepare atc for writing
678: INPUT_STATUS_1_COLOR,
679:
680: OB, // turn video on.
681: ATT_ADDRESS_PORT,
682: VIDEO_ENABLE,
683:
684: //start of enable 64k read/write bank mode.
685: OW, // enable 64k single read/write bank
686: SEQ_ADDRESS_PORT, // set 3c4.11 bit #7
687: 0xe511,
688:
689: OW, // enable PR0B register
690: GRAPH_ADDRESS_PORT, // set 3ce.0b bit #3
691: 0xce0b,
692: //end of enable 64k read/write bank mode.
693:
694: EOD
695: };
696:
697:
698: /**************************************************************************
699: * Western Digital 1024x768 modes - vRefresh 70Hz. *
700: * *
701: **************************************************************************/
702:
703: //
704: // Color graphics mode 0x5d, 1024x768 16 colors. 70Hz non-interlace
705: //
706: USHORT WDVGA_1024x768_70hz[] = {
707: // SEQ index 7h-9h, 10h-14h
708: OWM, // start sync reset program up sequencer
709: SEQ_ADDRESS_PORT,
710: 8,
711: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0012,0x8013,0x1014,
712:
713: OWM, // start sync reset program up sequencer
714: SEQ_ADDRESS_PORT,
715: 5,
716: 0x0300,0x0101,0x0f02,0x0003,0x0604,
717:
718: OB,
719: MISC_OUTPUT_REG_WRITE_PORT, // Misc output register
720: 0xeb,
721:
722: OW, // Set chain mode in sync reset
723: GRAPH_ADDRESS_PORT,
724: 0x0506,
725:
726: OB, // EndSyncResetCmd
727: SEQ_ADDRESS_PORT,
728: IND_SYNC_RESET,
729:
730: OB,
731: SEQ_DATA_PORT,
732: END_SYNC_RESET_VALUE,
733:
734: // CRTC index 2ah-30h, 3eh
735: METAOUT+INDXOUT, // program crtc registers
736: CRTC_ADDRESS_PORT_COLOR,
737: 7, // count
738: 0x2a, // start index
739: 0xf0,0xa5,0x00,0x00,0x01,0x00,0x00,
740:
741: OW, //
742: CRTC_ADDRESS_PORT_COLOR,
743: 0x003e,
744:
745: OW, // Unlock CRTC registers 0-7
746: CRTC_ADDRESS_PORT_COLOR,
747: 0x0511,
748:
749: METAOUT+INDXOUT, // program crtc registers
750: CRTC_ADDRESS_PORT_COLOR,
751: VGA_NUM_CRTC_PORTS, // count
752: 0, // start index
753: 0xa1,0x7f,0x80,0x04,0x86,0x97,0x24,0xf1,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
754: 0xff,0x85,0xff,0x40,0x0,0xff,0x23,0xE3,0xFF,
755:
756: IB, // prepare atc for writing
757: INPUT_STATUS_1_COLOR,
758:
759: METAOUT+ATCOUT, // program attribute controller registers
760: ATT_ADDRESS_PORT, // port
761: VGA_NUM_ATTRIB_CONT_PORTS, // count
762: 0, // start index
763: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
764: 0x01,0x0,0x0F,0x0,0x0,
765:
766: METAOUT+INDXOUT, // program graphics controller registers
767: GRAPH_ADDRESS_PORT, // port
768: 7, // count
769: 9, // start index
770: 0x00,0x00,0xc6,0x02,0x00,0x00,0x05,
771:
772: METAOUT+INDXOUT, // program graphics controller registers
773: GRAPH_ADDRESS_PORT, // port
774: VGA_NUM_GRAPH_CONT_PORTS, // count
775: 0, // start index
776: 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0x0FF,
777:
778:
779: OB, // DAC mask registers
780: DAC_PIXEL_MASK_PORT,
781: 0xFF,
782:
783: IB, // prepare atc for writing
784: INPUT_STATUS_1_COLOR,
785:
786: OB, // turn video on.
787: ATT_ADDRESS_PORT,
788: VIDEO_ENABLE,
789:
790: //start of enable 64k read/write bank mode.
791: OW, // enable 64k single read/write bank
792: SEQ_ADDRESS_PORT, // set 3c4.11 bit #7
793: 0xe511,
794:
795: OW, // enable PR0B register
796: GRAPH_ADDRESS_PORT, // set 3ce.0b bit #3
797: 0xce0b,
798: //end of enable 64k read/write bank mode.
799:
800: EOD
801: };
802:
803:
804: /**************************************************************************
805: * Western Digital 1024x768 modes - vRefresh 72Hz. *
806: * *
807: **************************************************************************/
808:
809: //
810: // Color graphics mode 0x5d, 1024x768 16 colors. 72Hz non-interlace
811: //
812: USHORT WDVGA_1024x768_72hz[] = {
813: // SEQ index 7h-9h, 10h-14h
814: OWM, // start sync reset program up sequencer
815: SEQ_ADDRESS_PORT,
816: 8,
817: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0012,0x8013,0x1014,
818:
819: OWM, // start sync reset program up sequencer
820: SEQ_ADDRESS_PORT,
821: 5,
822: 0x0300,0x0101,0x0f02,0x0003,0x0604,
823:
824: OB,
825: MISC_OUTPUT_REG_WRITE_PORT, // Misc output register
826: 0xef,
827:
828: OW, // Set chain mode in sync reset
829: GRAPH_ADDRESS_PORT,
830: 0x0506,
831:
832: OB, // EndSyncResetCmd
833: SEQ_ADDRESS_PORT,
834: IND_SYNC_RESET,
835:
836: OB,
837: SEQ_DATA_PORT,
838: END_SYNC_RESET_VALUE,
839:
840: // CRTC index 2ah-30h, 3eh
841: METAOUT+INDXOUT, // program crtc registers
842: CRTC_ADDRESS_PORT_COLOR,
843: 7, // count
844: 0x2a, // start index
845: 0xf0,0xb5,0x00,0x00,0x01,0x00,0x00,
846:
847: OW, //
848: CRTC_ADDRESS_PORT_COLOR,
849: 0x003e,
850:
851: OW, // Unlock CRTC registers 0-7
852: CRTC_ADDRESS_PORT_COLOR,
853: 0x0511,
854:
855: METAOUT+INDXOUT, // program crtc registers
856: CRTC_ADDRESS_PORT_COLOR,
857: VGA_NUM_CRTC_PORTS, // count
858: 0, // start index
859: 0xa3,0x7f,0x80,0x06,0x81,0x92,0x37,0xfd,0x00,0x60,0x0,0x0,0x0,0x0,0x0,0x0,
860: 0x01,0x87,0xff,0x40,0x0,0x00,0x37,0xE3,0xFF,
861:
862: IB, // prepare atc for writing
863: INPUT_STATUS_1_COLOR,
864:
865: METAOUT+ATCOUT, // program attribute controller registers
866: ATT_ADDRESS_PORT, // port
867: VGA_NUM_ATTRIB_CONT_PORTS, // count
868: 0, // start index
869: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
870: 0x01,0x0,0x0F,0x0,0x0,
871:
872: METAOUT+INDXOUT, // program graphics controller registers
873: GRAPH_ADDRESS_PORT, // port
874: 7, // count
875: 9, // start index
876: 0x00,0x00,0xc6,0x00,0x00,0x00,0x05,
877:
878: METAOUT+INDXOUT, // program graphics controller registers
879: GRAPH_ADDRESS_PORT, // port
880: VGA_NUM_GRAPH_CONT_PORTS, // count
881: 0, // start index
882: 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0x0FF,
883:
884:
885: OB, // DAC mask registers
886: DAC_PIXEL_MASK_PORT,
887: 0xFF,
888:
889: IB, // prepare atc for writing
890: INPUT_STATUS_1_COLOR,
891:
892: OB, // turn video on.
893: ATT_ADDRESS_PORT,
894: VIDEO_ENABLE,
895:
896: //start of enable 64k read/write bank mode.
897: OW, // enable 64k single read/write bank
898: SEQ_ADDRESS_PORT, // set 3c4.11 bit #7
899: 0xe511,
900:
901: OW, // enable PR0B register
902: GRAPH_ADDRESS_PORT, // set 3ce.0b bit #3
903: 0xce0b,
904: //end of enable 64k read/write bank mode.
905:
906: EOD
907: };
908:
909:
910: /**************************************************************************
911: * Western Digital 1024x768 modes - vRefresh Interlace. *
912: * *
913: **************************************************************************/
914:
915: //
916: // Color graphics mode 0x5d, 1024x768 16 colors. Default - Interlace
917: //
918: USHORT WDVGA_1024x768_int[] = {
919: // SEQ index 7h-9h, 10h-14h
920: OWM, // start sync reset program up sequencer
921: SEQ_ADDRESS_PORT,
922: 8,
923: 0xf807,0x0008,0x0009,0xc510,0x6511,0x0412,0x8013,0x1014,
924:
925: OWM, // start sync reset program up sequencer
926: SEQ_ADDRESS_PORT,
927: 5,
928: 0x0300,0x0101,0x0f02,0x0003,0x0604,
929:
930: OB,
931: MISC_OUTPUT_REG_WRITE_PORT, // Misc output register
932: 0x2f,
933:
934: OW, // Set chain mode in sync reset
935: GRAPH_ADDRESS_PORT,
936: 0x0506,
937:
938: OB, // EndSyncResetCmd
939: SEQ_ADDRESS_PORT,
940: IND_SYNC_RESET,
941:
942: OB,
943: SEQ_DATA_PORT,
944: END_SYNC_RESET_VALUE,
945:
946: // CRTC index 2ah-30h, 3eh
947: METAOUT+INDXOUT, // program crtc registers
948: CRTC_ADDRESS_PORT_COLOR,
949: 7, // count
950: 0x2a, // start index
951: 0xf0,0x05,0x34,0x2a,0x0b,0x00,0x00,
952:
953: OW, //
954: CRTC_ADDRESS_PORT_COLOR,
955: 0x003e,
956:
957: OW, // Unlock CRTC registers 0-7
958: CRTC_ADDRESS_PORT_COLOR,
959: 0x0511,
960:
961: METAOUT+INDXOUT, // program crtc registers
962: CRTC_ADDRESS_PORT_COLOR,
963: VGA_NUM_CRTC_PORTS, // count
964: 0, // start index
965: 0x99,0x7f,0x7f,0x1c,0x83,0x19,0x97,0x1f,0x00,0x40,0x0,0x0,0x0,0x0,0x0,0x0,
966: 0x7f,0x83,0x7F,0x40,0x0,0x7f,0x96,0xE3,0xFF,
967:
968: IB, // prepare atc for writing
969: INPUT_STATUS_1_COLOR,
970:
971: METAOUT+ATCOUT, // program attribute controller registers
972: ATT_ADDRESS_PORT, // port
973: VGA_NUM_ATTRIB_CONT_PORTS, // count
974: 0, // start index
975: 0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF,
976: 0x01,0x0,0x0F,0x0,0x0,
977:
978: METAOUT+INDXOUT, // program graphics controller registers
979: GRAPH_ADDRESS_PORT, // port
980: 7, // count
981: 9, // start index
982: 0x00,0x00,0xc6,0x00,0x00,0x00,0x05,
983:
984: METAOUT+INDXOUT, // program graphics controller registers
985: GRAPH_ADDRESS_PORT, // port
986: VGA_NUM_GRAPH_CONT_PORTS, // count
987: 0, // start index
988: 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0F,0x0FF,
989:
990:
991: OB, // DAC mask registers
992: DAC_PIXEL_MASK_PORT,
993: 0xFF,
994:
995: IB, // prepare atc for writing
996: INPUT_STATUS_1_COLOR,
997:
998: OB, // turn video on.
999: ATT_ADDRESS_PORT,
1000: VIDEO_ENABLE,
1001:
1002: //start of enable 64k read/write bank mode.
1003: OW, // enable 64k single read/write bank
1004: SEQ_ADDRESS_PORT, // set 3c4.11 bit #7
1005: 0xe511,
1006:
1007: OW, // enable PR0B register
1008: GRAPH_ADDRESS_PORT, // set 3ce.0b bit #3
1009: 0xce0b,
1010: //end of enable 64k read/write bank mode.
1011:
1012: EOD
1013: };
1014: #else//!INT10_MODE_SET
1015:
1016: USHORT WDVGA_1K_WIDE[] = {
1017: OW, // stretch scans to 1k
1018: CRTC_ADDRESS_PORT_COLOR,
1019: 0x8013,
1020:
1021: EOD
1022: };
1023:
1024: USHORT WDVGA_RW_BANK[] = {
1025: OW, //unlock SEQ ext. regs for 90c11
1026: SEQ_ADDRESS_PORT,
1027: 0x4806,
1028:
1029: OB,
1030: SEQ_ADDRESS_PORT, // set 3c4.11 bit #7
1031: 0x11,
1032: METAOUT+MASKOUT,
1033: SEQ_DATA_PORT,
1034: 0x7f,
1035: 0x80,
1036:
1037: OB, // enable PR0B register
1038: GRAPH_ADDRESS_PORT, // set 3ce.0b bit #3
1039: 0x0b,
1040: METAOUT+MASKOUT,
1041: GRAPH_DATA_PORT,
1042: 0xf7,
1043: 0x08,
1044:
1045: EOD
1046: };
1047:
1048: USHORT WDVGA_RW_BANK_1K_WIDE[] = {
1049: OW, // stretch scans to 1k
1050: CRTC_ADDRESS_PORT_COLOR,
1051: 0x8013,
1052:
1053: OW, //unlock SEQ ext. regs for 90c11
1054: SEQ_ADDRESS_PORT,
1055: 0x4806,
1056:
1057: OB,
1058: SEQ_ADDRESS_PORT, // set 3c4.11 bit #7
1059: 0x11,
1060: METAOUT+MASKOUT,
1061: SEQ_DATA_PORT,
1062: 0x7f,
1063: 0x80,
1064:
1065: OB, // enable PR0B register
1066: GRAPH_ADDRESS_PORT, // set 3ce.0b bit #3
1067: 0x0b,
1068: METAOUT+MASKOUT,
1069: GRAPH_DATA_PORT,
1070: 0xf7,
1071: 0x08,
1072:
1073: EOD
1074: };
1075:
1076: #endif
1077: //
1078: // Memory map table -
1079: //
1080: // These memory maps are used to save and restore the physical video buffer.
1081: //
1082:
1083: //
1084: // Memory map table definition
1085: //
1086:
1087: typedef struct {
1088: ULONG MaxSize; // Maximum addressable size of memory.
1089: ULONG Start; // Start address of mode.
1090: } MEMORYMAPS;
1091:
1092: MEMORYMAPS MemoryMaps[] = {
1093:
1094: // length start
1095: // ------ -----
1096: { 0x08000, 0xB0000}, // all mono text modes (7)
1097: { 0x08000, 0xB8000}, // all color text modes (0, 1, 2, 3,
1098: { 0x20000, 0xA0000}, // all VGA graphics modes
1099: };
1100:
1101: //
1102: // Video mode table - contains information and commands for initializing each
1103: // mode. These entries must correspond with those in VIDEO_MODE_VGA. The first
1104: // entry is commented; the rest follow the same format, but are not so
1105: // heavily commented.
1106: //
1107:
1108: //
1109: // Total # of video modes this driver supports.
1110: //
1111:
1112: #ifdef INT10_MODE_SET
1113: #define NUM_VIDEO_MODES 18 //should be changed to support 256-color drivers
1114: #else
1115: #define NUM_VIDEO_MODES 10
1116: #endif
1117:
1118: VIDEOMODE ModesVGA[NUM_VIDEO_MODES] = {
1119:
1120: //
1121: // Standard VGA modes.
1122: //
1123:
1124: //
1125: // Mode index 0
1126: // Color text mode 3, 720x400, 9x16 char cell (VGA).
1127: //
1128:
1129: {
1130: VIDEO_MODE_COLOR, // flags that this mode is a color mode, but not graphics
1131: 4, // four planes
1132: 1, // one bit of color per plane
1133: 80, 25, // 80x25 text resolution
1134: 720, 400, // 720x400 pixels on screen
1135: 160, 0x10000, // 160 bytes per scan line, 64K of CPU-addressable bitmap
1136: 0, 0, // set to 0 frequency, non-interlaced mode.
1137: NoBanking, // no banking supported or needed in this mode
1138: MemMap_CGA, // the memory mapping is the standard CGA memory mapping
1139: // of 32K at B8000
1140: FALSE, // Is mode valid or not
1141: #ifdef INT10_MODE_SET
1142: 0xFF, // mask to AND in for frequency
1143: 0x00, // Value used to set the frequency
1144: 0x3, // int10 mode number
1145: NULL,
1146: #else
1147: WDVGA_TEXT_0, // pointer to the command strings
1148: #endif
1149: },
1150:
1151: //
1152: // Mode index 1.
1153: // Color text mode 3, 640x350, 8x14 char cell (EGA).
1154: //
1155:
1156: {
1157: VIDEO_MODE_COLOR, 4, 1, 80, 25,
1158: 640, 350, 160, 0x10000, 0, 0, NoBanking, MemMap_CGA,
1159: FALSE,
1160: #ifdef INT10_MODE_SET
1161: 0xFF, 0x00,
1162: 0x3,
1163: NULL,
1164: #else
1165: WDVGA_TEXT_1, // pointer to the command strings
1166: #endif
1167: },
1168:
1169: //
1170: //
1171: // Mode index 2
1172: // Standard VGA Color graphics mode 0x12, 640x480 16 colors.
1173: //
1174:
1175: {
1176: VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 80, 30,
1177: 640, 480, 80, 0x10000, 0, 0, NoBanking, MemMap_VGA,
1178: FALSE,
1179: #ifdef INT10_MODE_SET
1180: 0xFF, 0x00,
1181: 0x12,
1182: NULL,
1183: #else
1184: WDVGA_640x480, // pointer to the command strings
1185: #endif
1186: },
1187:
1188: //
1189: // Beginning of SVGA modes
1190: //
1191:
1192: //
1193: // Mode index 3
1194: // 800x600 16 colors. 60hz
1195: //
1196:
1197: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 100, 37,
1198: 800, 600, 100, 0x10000, 60, 0, NoBanking, MemMap_VGA,
1199: FALSE,
1200: #ifdef INT10_MODE_SET
1201: 0x3F, 0x40,
1202: 0x58,
1203: NULL,
1204: #else
1205: WDVGA_800x600_60hz, // pointer to the command strings
1206: #endif
1207: },
1208:
1209: //
1210: // Mode index 4
1211: // 800x600 16 colors. 72hz
1212: //
1213:
1214: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 100, 37,
1215: 800, 600, 100, 0x10000, 72, 0, NoBanking, MemMap_VGA,
1216: FALSE,
1217: #ifdef INT10_MODE_SET
1218: 0x3F, 0x80,
1219: 0x58,
1220: NULL,
1221: #else
1222: WDVGA_800x600_72hz, // pointer to the command strings
1223: #endif
1224: },
1225:
1226: //
1227: // Mode index 5
1228: // 800x600 16 colors. 56hz
1229: //
1230:
1231: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 100, 37,
1232: 800, 600, 100, 0x10000, 56, 0, NoBanking, MemMap_VGA,
1233: FALSE,
1234: #ifdef INT10_MODE_SET
1235: 0x3F, 0x00,
1236: 0x58,
1237: NULL,
1238: #else
1239: WDVGA_800x600_56hz, // pointer to the command strings
1240: #endif
1241: },
1242:
1243: //
1244: // Mode index 6
1245: // 1024x768 non-interlaced 16 colors. 60hz
1246: // Assumes 512K.
1247: //
1248:
1249: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 128, 48,
1250: 1024, 768, 128, 0x20000, 60, 0, NormalBanking, MemMap_VGA,
1251: FALSE,
1252: #ifdef INT10_MODE_SET
1253: 0xCF, 0x10,
1254: 0x5d,
1255: WDVGA_RW_BANK,
1256: #else
1257: WDVGA_1024x768_60hz, // pointer to the command strings
1258: #endif
1259: },
1260:
1261: //
1262: // Mode index 7
1263: // 1024x768 non-interlaced 16 colors. 70hz
1264: // Assumes 512K.
1265: //
1266:
1267: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 128, 48,
1268: 1024, 768, 128, 0x20000, 70, 0, NormalBanking, MemMap_VGA,
1269: FALSE,
1270: #ifdef INT10_MODE_SET
1271: 0xCF, 0x20,
1272: 0x5d,
1273: WDVGA_RW_BANK,
1274: #else
1275: WDVGA_1024x768_70hz, // pointer to the command strings
1276: #endif
1277: },
1278:
1279: //
1280: // Mode index 8
1281: // 1024x768 non-interlaced 16 colors. 72hz
1282: // Assumes 512K.
1283: //
1284:
1285: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 128, 48,
1286: 1024, 768, 128, 0x20000, 72, 0, NormalBanking, MemMap_VGA,
1287: FALSE,
1288: #ifdef INT10_MODE_SET
1289: 0xCF, 0x30,
1290: 0x5d,
1291: WDVGA_RW_BANK,
1292: #else
1293: WDVGA_1024x768_72hz, // pointer to the command strings
1294: #endif
1295: },
1296:
1297: //
1298: // Mode index 9
1299: // 1024x768 interlaced 16 colors. 44hz
1300: // Assumes 512K.
1301: //
1302:
1303: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 4, 1, 128, 48,
1304: 1024, 768, 128, 0x20000, 44, 1, NormalBanking, MemMap_VGA,
1305: FALSE,
1306: #ifdef INT10_MODE_SET
1307: 0xCF, 0x00,
1308: 0x5d,
1309: WDVGA_RW_BANK,
1310: #else
1311: WDVGA_1024x768_int, // pointer to the command strings
1312: #endif
1313: },
1314:
1315: #ifdef INT10_MODE_SET
1316: //
1317: // Mode index 10
1318: // 640x480x256
1319: //
1320:
1321: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1322: 640, 480, 1024, 0x80000, 0, 0, NormalBanking, MemMap_VGA,
1323: FALSE,
1324: 0xFF, 0x00,
1325: 0x5f,
1326: WDVGA_RW_BANK_1K_WIDE,
1327: },
1328:
1329: // BUGBUG 800x600 modes need 1Meg until we support broken rasters
1330:
1331: //
1332: // Mode index 11
1333: // 800x600x256 56Hz
1334: //
1335: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1336: 800, 600, 1024, 0x100000, 56, 0, NormalBanking, MemMap_VGA,
1337: FALSE,
1338: 0x3F, 0x00,
1339: 0x5c,
1340: WDVGA_RW_BANK_1K_WIDE,
1341: },
1342:
1343: //
1344: // Mode index 12
1345: // 800x600x256 60Hz
1346: //
1347: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1348: 800, 600, 1024, 0x100000, 60, 0, NormalBanking, MemMap_VGA,
1349: FALSE,
1350: 0x3F, 0x40,
1351: 0x5c,
1352: WDVGA_RW_BANK_1K_WIDE,
1353: },
1354:
1355: //
1356: // Mode index 13
1357: // 800x600x256 72Hz
1358: //
1359: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1360: 800, 600, 1024, 0x100000, 72, 0, NormalBanking, MemMap_VGA,
1361: FALSE,
1362: 0x3F, 0x80,
1363: 0x5c,
1364: WDVGA_RW_BANK_1K_WIDE,
1365: },
1366:
1367: //
1368: // Mode index 14
1369: // 1024x768x256 60Hz
1370: //
1371: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1372: 1024, 768, 1024, 0x100000, 60, 0, NormalBanking, MemMap_VGA,
1373: FALSE,
1374: 0xCF, 0x10,
1375: 0x60,
1376: WDVGA_RW_BANK,
1377: },
1378:
1379: //
1380: // Mode index 15
1381: // 1024x768x256 70hz
1382: //
1383: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1384: 1024, 768, 1024, 0x100000, 70, 0, NormalBanking, MemMap_VGA,
1385: FALSE,
1386: 0xCF, 0x20,
1387: 0x60,
1388: WDVGA_RW_BANK,
1389: },
1390:
1391: //
1392: //
1393: // Mode index 16
1394: // 1024x768x256 72hz
1395: //
1396: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1397: 1024, 768, 1024, 0x100000, 72, 0, NormalBanking, MemMap_VGA,
1398: FALSE,
1399: 0xCF, 0x30,
1400: 0x60,
1401: WDVGA_RW_BANK,
1402: },
1403:
1404: // Mode index 17
1405: // 1024x768x256 44Hz (Interlaced)
1406: //
1407: { VIDEO_MODE_COLOR+VIDEO_MODE_GRAPHICS, 1, 8, 80, 30,
1408: 1024, 768, 1024, 0x100000, 44, 1, NormalBanking, MemMap_VGA,
1409: FALSE,
1410: 0xCF, 0x00,
1411: 0x60,
1412: WDVGA_RW_BANK,
1413: },
1414: #endif//INT10_MODE_SET
1415: };
1416:
1417:
1418: ULONG NumVideoModes = sizeof(ModesVGA) / sizeof(VIDEOMODE);
1419:
1420: //
1421: //
1422: // Data used to set the Graphics and Sequence Controllers to put the
1423: // VGA into a planar state at A0000 for 64K, with plane 2 enabled for
1424: // reads and writes, so that a font can be loaded, and to disable that mode.
1425: //
1426:
1427: // Settings to enable planar mode with plane 2 enabled.
1428: //
1429:
1430: USHORT EnableA000Data[] = {
1431: OWM,
1432: SEQ_ADDRESS_PORT,
1433: 1,
1434: 0x0100,
1435:
1436: OWM,
1437: GRAPH_ADDRESS_PORT,
1438: 3,
1439: 0x0204, // Read Map = plane 2
1440: 0x0005, // Graphics Mode = read mode 0, write mode 0
1441: 0x0406, // Graphics Miscellaneous register = A0000 for 64K, not odd/even,
1442: // graphics mode
1443: OWM,
1444: SEQ_ADDRESS_PORT,
1445: 3,
1446: 0x0402, // Map Mask = write to plane 2 only
1447: 0x0404, // Memory Mode = not odd/even, not full memory, graphics mode
1448: 0x0300, // end sync reset
1449: EOD
1450: };
1451:
1452: //
1453: // Settings to disable the font-loading planar mode.
1454: //
1455:
1456: USHORT DisableA000Color[] = {
1457: OWM,
1458: SEQ_ADDRESS_PORT,
1459: 1,
1460: 0x0100,
1461:
1462: OWM,
1463: GRAPH_ADDRESS_PORT,
1464: 3,
1465: 0x0004, 0x1005, 0x0E06,
1466:
1467: OWM,
1468: SEQ_ADDRESS_PORT,
1469: 3,
1470: 0x0302, 0x0204, 0x0300, // end sync reset
1471: EOD
1472:
1473: };
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