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1.1 root 1: /*++
2:
3: Copyright (c) 1992 Microsoft Corporation
4: Copyright (c) 1993 Western Digital Corporation
5:
6: Module Name:
7:
8: wdvga.h
9:
10: Abstract:
11:
12: This module contains the definitions for the code that implements the
13: WDVGA device driver.
14:
15: Environment:
16:
17: Kernel mode
18:
19: Revision History:
20:
21: --*/
22:
23: #ifndef NO_INT10_MODE_SET
24: #define INT10_MODE_SET 1
25: #endif
26:
27: //
28: // Do full save and restore.
29: //
30:
31: // #define EXTENDED_REGISTER_SAVE_RESTORE 1
32:
33: //
34: // Define type of ET4000 boards
35: //
36:
37: typedef enum _BOARD_TYPE {
38: WD90C00 = 1,
39: WD90C30,
40: SPEEDSTAR30,
41: WD90C31,
42: SPEEDSTAR31,
43: OTHER
44: } BOARD_TYPE;
45:
46:
47: //
48: // Base address of VGA memory range. Also used as base address of VGA
49: // memory when loading a font, which is done with the VGA mapped at A0000.
50: //
51:
52: #define MEM_VGA 0xA0000
53: #define MEM_VGA_SIZE 0x20000
54:
55: //
56: // Port definitions for filling the ACCSES_RANGES structure in the miniport
57: // information, defines the range of I/O ports the VGA spans.
58: // There is a break in the IO ports - a few ports are used for the parallel
59: // port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
60: // so all VGA ports are in one address range.
61: //
62:
63: #define VGA_BASE_IO_PORT 0x000003B0
64: #define VGA_START_BREAK_PORT 0x000003BB
65: #define VGA_END_BREAK_PORT 0x000003C0
66: #define VGA_MAX_IO_PORT 0x000003DF
67:
68: #define WD_EXT_PORT_START 0x000023C0
69: #define WD_EXT_PORT_END 0x000023C7
70:
71: //
72: // VGA port-related definitions.
73: //
74:
75: //
76: // VGA register definitions
77: //
78: // ports in monochrome mode
79: #define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and
80: #define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode
81: #define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port
82: // in mono mode
83: #define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read
84: // port in mono mode
85: #define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
86: // Register to read to reset
87: // Attribute Controller index/data
88:
89: #define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and
90: #define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port
91: // for writes, but only Address is
92: // readable at 0x3C0
93: #define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is
94: // readable here
95: #define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write
96: // port
97: #define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read
98: // port
99: #define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the
100: // entire VGA subsystem
101: #define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and
102: #define SEQ_DATA_PORT 0x0015 // Data registers
103: #define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg
104: #define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg,
105: // write-only
106: #define DAC_STATE_PORT 0x0017 // DAC state (read/write),
107: // read-only
108: #define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg
109: #define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg
110: #define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port
111: #define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read
112: // port
113: #define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address
114: #define GRAPH_DATA_PORT 0x001F // and Data registers
115:
116: #define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and
117: #define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode
118: #define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port
119: #define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read
120: // port in color mode
121: #define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
122: // Register to read to reset
123: // Attribute Controller index/data
124: // toggle in color mode
125:
126: //
127: // Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
128: // VGA registers.
129: //
130:
131: #define CRTC_ADDRESS_MONO_OFFSET 0x04
132: #define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
133: #define ATT_ADDRESS_OFFSET 0x10
134: #define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
135: #define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
136: #define SEQ_ADDRESS_OFFSET 0x14
137: #define DAC_PIXEL_MASK_OFFSET 0x16
138: #define DAC_STATE_OFFSET 0x17
139: #define DAC_ADDRESS_WRITE_OFFSET 0x18
140: #define GRAPH_ADDRESS_OFFSET 0x1E
141: #define CRTC_ADDRESS_COLOR_OFFSET 0x24
142: #define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
143:
144: //
145: // VGA indexed register indexes.
146: //
147:
148: #define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
149: #define IND_CURSOR_END 0x0B // and End registers
150: #define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
151: #define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
152: #define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
153: // End register, which has the bit
154: // that protects/unprotects CRTC
155: // index registers 0-7
156: #define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
157: #define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
158: #define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
159: #define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
160: #define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
161: #define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
162: #define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
163: #define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
164: #define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
165: #define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
166: // CRTC
167:
168: #define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
169: // synchronous reset
170: #define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
171: // synchronous reset
172:
173: //
174: // Values for Attribute Controller Index register to turn video off
175: // and on, by setting bit 5 to 0 (off) or 1 (on).
176: //
177:
178: #define VIDEO_DISABLE 0
179: #define VIDEO_ENABLE 0x20
180:
181: //
182: // Value written to the Read Map register when identifying the existence of
183: // a VGA in VgaInitialize. This value must be different from the final test
184: // value written to the Bit Mask in that routine.
185: //
186:
187: #define READ_MAP_TEST_SETTING 0x03
188:
189: //
190: // Masks to keep only the significant bits of the Graphics Controller and
191: // Sequencer Address registers. Masking is necessary because some VGAs, such
192: // as S3-based ones, don't return unused bits set to 0, and some SVGAs use
193: // these bits if extensions are enabled.
194: //
195:
196: #define GRAPH_ADDR_MASK 0x0F
197: #define SEQ_ADDR_MASK 0x07
198:
199: //
200: // Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
201: //
202:
203: #define CHAIN4_MASK 0x08
204:
205: //
206: // Default text mode setting for various registers, used to restore their
207: // states if VGA detection fails after they've been modified.
208: //
209:
210: #define MEMORY_MODE_TEXT_DEFAULT 0x02
211: #define BIT_MASK_DEFAULT 0xFF
212: #define READ_MAP_DEFAULT 0x00
213:
214: //
215: // Palette-related info.
216: //
217:
218: //
219: // Highest valid DAC color register index.
220: //
221:
222: #define VIDEO_MAX_COLOR_REGISTER 0xFF
223:
224: //
225: // Highest valid palette register index
226: //
227:
228: #define VIDEO_MAX_PALETTE_REGISTER 0x0F
229:
230: //
231: // Indices for type of memory mapping; used in ModesVGA[], must match
232: // MemoryMap[].
233: //
234:
235: typedef enum _VIDEO_MEMORY_MAP {
236: MemMap_Mono,
237: MemMap_CGA,
238: MemMap_VGA
239: } VIDEO_MEMORY_MAP, *PVIDEO_MEMORY_MAP;
240:
241: //
242: // For a mode, the type of banking supported. Controls the information
243: // returned in VIDEO_BANK_SELECT. PlanarHCBanking includes NormalBanking.
244: //
245:
246: typedef enum _BANK_TYPE {
247: NoBanking = 0,
248: NormalBanking,
249: PlanarHCBanking
250: } BANK_TYPE, *PBANK_TYPE;
251:
252: //
253: // Structure used to describe each video mode in ModesVGA[].
254: //
255:
256: typedef struct {
257: USHORT fbType; // color or monochrome, text or graphics, via
258: // VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
259: USHORT numPlanes; // # of video memory planes
260: USHORT bitsPerPlane; // # of bits of color in each plane
261: SHORT col; // # of text columns across screen with default font
262: SHORT row; // # of text rows down screen with default font
263: USHORT hres; // # of pixels across screen
264: USHORT vres; // # of scan lines down screen
265: USHORT wbytes; // # of bytes from start of one scan line to start of next
266: ULONG sbytes; // total size of addressable display memory in bytes
267: ULONG Frequency; // Vertical Frequency
268: ULONG Interlaced; // Determines if the mode is interlaced or not
269: BANK_TYPE banktype; // NoBanking, NormalBanking, PlanarHCBanking
270: VIDEO_MEMORY_MAP MemMap; // index from VIDEO_MEMORY_MAP of memory
271: // mapping used by this mode
272: BOOLEAN ValidMode; //Determines which modes are valid.
273: #ifdef INT10_MODE_SET
274: UCHAR FrequencyMask; // value used to mask the mode frequency
275: UCHAR FrequencySetting; // value used to set the mode frequency
276: ULONG Int10ModeNumber; // Mode number via Int 10
277: #endif
278: PUSHORT CmdStrings; // pointer to array of register-setting commands
279: } VIDEOMODE, *PVIDEOMODE;
280:
281:
282: //
283: // Mode into which to put the VGA before starting a VDM, so it's a plain
284: // vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
285: // 80x25 text mode.)
286: //
287:
288: #define DEFAULT_MODE 0
289:
290:
291: //
292: // Info for the validator functions.
293: //
294:
295: //
296: // Number of each type of indexed register in a standard VGA, used by
297: // validator and state save/restore functions.
298: //
299: // Note: VDMs currently only support basic VGAs only.
300: //
301:
302: #define VGA_NUM_SEQUENCER_PORTS 5
303: #define VGA_NUM_CRTC_PORTS 25
304: #define VGA_NUM_GRAPH_CONT_PORTS 9
305: #define VGA_NUM_ATTRIB_CONT_PORTS 21
306: #define VGA_NUM_DAC_ENTRIES 256
307:
308: #ifdef EXTENDED_REGISTER_SAVE_RESTORE
309:
310: //
311: // Indices to start save/restore in extension registers:
312: // For both chip types
313:
314: #define WD_GRAPH_EXT_START 0x09
315: #define WD_GRAPH_EXT_END 0x0E
316:
317: #define WD_SEQUENCER_EXT_START 0x07
318: #define WD_SEQUENCER_EXT_END 0x09
319: #define WD_SEQUENCER_1_EXT_START 0x10
320: #define WD_SEQUENCER_1_EXT_END 0x14
321:
322: #define WD_CRTC_EXT_START 0x2A
323: #define WD_CRTC_EXT_END 0x30
324: #define WD_CRTC_1_EXT_START 0x3E
325: #define WD_CRTC_1_EXT_END 0x3E
326:
327: //
328: // Number of extended regs for both chip types.
329: //
330:
331: #define WD_NUM_GRAPH_EXT_PORTS (WD_GRAPH_EXT_END - WD_GRAPH_EXT_START + 1)
332: #define WD_NUM_SEQUENCER_EXT_PORTS (WD_SEQUENCER_EXT_END - WD_SEQUENCER_EXT_START + 1) + \
333: (WD_SEQUENCER_1_EXT_END - WD_SEQUENCER_1_EXT_START + 1)
334: #define WD_NUM_CRTC_EXT_PORTS (WD_CRTC_EXT_END - WD_CRTC_EXT_START + 1) + \
335: (WD_CRTC_1_EXT_END - WD_CRTC_1_EXT_START + 1)
336:
337: //
338: // set values for save/restore area based on largest value for a chipset.
339: //
340:
341: #define EXT_NUM_GRAPH_CONT_PORTS WD_NUM_GRAPH_EXT_PORTS
342: #define EXT_NUM_SEQUENCER_PORTS WD_NUM_SEQUENCER_EXT_PORTS
343: #define EXT_NUM_CRTC_PORTS WD_NUM_CRTC_EXT_PORTS
344: #define EXT_NUM_ATTRIB_CONT_PORTS 0
345: #define EXT_NUM_DAC_ENTRIES 0
346:
347: #else
348:
349: #define EXT_NUM_GRAPH_CONT_PORTS 0
350: #define EXT_NUM_SEQUENCER_PORTS 0
351: #define EXT_NUM_CRTC_PORTS 0
352: #define EXT_NUM_ATTRIB_CONT_PORTS 0
353: #define EXT_NUM_DAC_ENTRIES 0
354:
355: #endif
356:
357: //
358: // Info used by the Validator functions and save/restore code.
359: // Structure used to trap register accesses that must be done atomically.
360: //
361:
362: #define VGA_MAX_VALIDATOR_DATA 100
363:
364: #define VGA_VALIDATOR_UCHAR_ACCESS 1
365: #define VGA_VALIDATOR_USHORT_ACCESS 2
366: #define VGA_VALIDATOR_ULONG_ACCESS 3
367:
368: typedef struct _VGA_VALIDATOR_DATA {
369: ULONG Port;
370: UCHAR AccessType;
371: ULONG Data;
372: } VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA;
373:
374:
375: //
376: // Info for the save and restore state functions.
377: //
378:
379: //
380: // Number of bytes to save in each plane.
381: //
382:
383: #define VGA_PLANE_SIZE 0x10000
384:
385: //
386: // These constants determine the offsets within the
387: // VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
388: // restore the VGA's state.
389: //
390:
391: #define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
392:
393: #define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
394: #define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
395: VGA_NUM_SEQUENCER_PORTS)
396: #define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
397: VGA_NUM_CRTC_PORTS)
398: #define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
399: VGA_NUM_GRAPH_CONT_PORTS)
400: #define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
401: VGA_NUM_ATTRIB_CONT_PORTS)
402: #define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
403: (3 * VGA_NUM_DAC_ENTRIES))
404:
405: #define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
406: #define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
407: EXT_NUM_SEQUENCER_PORTS)
408: #define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
409: EXT_NUM_CRTC_PORTS)
410: #define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET + \
411: EXT_NUM_GRAPH_CONT_PORTS)
412: #define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
413: EXT_NUM_ATTRIB_CONT_PORTS)
414:
415: #define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
416:
417: #define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
418: sizeof (VGA_VALIDATOR_DATA)) + \
419: sizeof (ULONG) + \
420: sizeof (ULONG) + \
421: sizeof (PVIDEO_ACCESS_RANGE)
422:
423: #define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
424:
425: #define VGA_MISC_DATA_AREA_SIZE 0
426:
427: #define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
428:
429: #define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
430: #define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
431: #define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
432:
433: //
434: // Space needed to store all state data.
435: //
436:
437: #define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
438:
439:
440: //
441: // Device extension for the driver object. This data is only used
442: // locally, so this structure can be added to as needed.
443: //
444:
445: typedef struct _HW_DEVICE_EXTENSION {
446:
447: PUCHAR IOAddress; // base I/O address of VGA ports
448: PVOID VideoMemoryAddress; // base virtual memory address of VGA memory
449: ULONG AdapterMemorySize; // size, in bytes, of the memory on the
450: // board.
451: ULONG ModeIndex; // index of current mode in ModesVGA[]
452: ULONG NumAvailableModes; // number of valid modes on this device
453: PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
454: // current mode
455:
456: USHORT FontPelColumns; // Width of the font in pels
457: USHORT FontPelRows; // height of the font in pels
458:
459: VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
460:
461: UCHAR CursorEnable; // whether cursor is enabled or not
462: UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
463: UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
464:
465: UCHAR BoardID; // Used to identify different boards
466: // supported.
467:
468: BOOLEAN ExtendedRegisters; // Determines if extended registers have
469: // been claimed.
470:
471: PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
472: ULONG PhysicalVideoMemoryLength; // length of display memory
473: PHYSICAL_ADDRESS PhysicalFrameBase; // physical memory address and
474: ULONG PhysicalFrameLength; // length of display memory for
475: // the current mode.
476:
477: //
478: // These 4 fields must be at the end of the device extension and must be
479: // kept in this order since this data will be copied to and from the save
480: // state buffer that is passed to and from the VDM.
481: //
482:
483: ULONG TrappedValidatorCount; // number of entries in the Trapped
484: // validator data Array.
485: VGA_VALIDATOR_DATA TrappedValidatorData[VGA_MAX_VALIDATOR_DATA];
486: // Data trapped by the validator routines
487: // but not yet played back into the VGA
488: // register.
489:
490: ULONG SequencerAddressValue; // Determines if the Sequencer Address Port
491: // is currently selecting the SyncReset data
492: // register.
493:
494: ULONG CurrentNumVdmAccessRanges; // Number of access ranges in
495: // the access range array pointed
496: // to by the next field
497: PVIDEO_ACCESS_RANGE CurrentVdmAccessRange; // Access range currently
498: // associated to the VDM
499:
500:
501: } HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
502:
503:
504: //
505: // Function prototypes.
506: //
507:
508: //
509: // Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
510: //
511:
512: VP_STATUS
513: VgaValidatorUcharEntry (
514: ULONG Context,
515: ULONG Port,
516: UCHAR AccessMode,
517: PUCHAR Data
518: );
519:
520: VP_STATUS
521: VgaValidatorUshortEntry (
522: ULONG Context,
523: ULONG Port,
524: UCHAR AccessMode,
525: PUSHORT Data
526: );
527:
528: VP_STATUS
529: VgaValidatorUlongEntry (
530: ULONG Context,
531: ULONG Port,
532: UCHAR AccessMode,
533: PULONG Data
534: );
535:
536: BOOLEAN
537: VgaPlaybackValidatorData (
538: PVOID Context
539: );
540:
541: //
542: // Bank switch code start and end labels, define in HARDWARE.ASM
543: //
544:
545: extern UCHAR BankSwitchStart;
546: extern UCHAR BankSwitchEnd;
547:
548: //
549: // Vga init scripts for font loading
550: //
551:
552: extern USHORT EnableA000Data[];
553: extern USHORT DisableA000Color[];
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