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1.1 root 1:
2: STATIC_INLINE uae_u32 get_word_prefetch (int o)
3: {
4: uae_u32 v = regs.irc;
5: regs.irc = get_wordi (m68k_getpc () + o);
6: return v;
7: }
8: STATIC_INLINE uae_u32 get_long_prefetch (int o)
9: {
10: uae_u32 v = get_word_prefetch (o) << 16;
11: v |= get_word_prefetch (o + 2);
12: return v;
13: }
14:
15: #ifdef CPUEMU_20
16:
17: STATIC_INLINE void checkcycles_ce020 (void)
18: {
19: if (regs.ce020memcycles > 0)
20: do_cycles_ce (regs.ce020memcycles);
21: regs.ce020memcycles = 0;
22: }
23:
24: STATIC_INLINE uae_u32 mem_access_delay_long_read_ce020 (uaecptr addr)
25: {
26: checkcycles_ce020 ();
27: switch (ce_banktype[addr >> 16])
28: {
29: case CE_MEMBANK_CHIP:
30: if ((addr & 3) != 0) {
31: uae_u32 v;
32: v = wait_cpu_cycle_read_ce020 (addr + 0, 1) << 16;
33: v |= wait_cpu_cycle_read_ce020 (addr + 2, 1) << 0;
34: return v;
35: } else {
36: return wait_cpu_cycle_read_ce020 (addr, -1);
37: }
38: case CE_MEMBANK_FAST:
39: if ((addr & 3) != 0)
40: do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE);
41: else
42: do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE);
43: break;
44: case CE_MEMBANK_FAST16BIT:
45: do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE);
46: break;
47: }
48: return get_long (addr);
49: }
50:
51: STATIC_INLINE uae_u32 mem_access_delay_longi_read_ce020 (uaecptr addr)
52: {
53: checkcycles_ce020 ();
54: switch (ce_banktype[addr >> 16])
55: {
56: case CE_MEMBANK_CHIP:
57: if ((addr & 3) != 0) {
58: uae_u32 v;
59: v = wait_cpu_cycle_read_ce020 (addr + 0, 1) << 16;
60: v |= wait_cpu_cycle_read_ce020 (addr + 2, 1) << 0;
61: return v;
62: } else {
63: return wait_cpu_cycle_read_ce020 (addr, -1);
64: }
65: case CE_MEMBANK_FAST:
66: if ((addr & 3) != 0)
67: do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE);
68: else
69: do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE);
70: break;
71: case CE_MEMBANK_FAST16BIT:
72: do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE);
73: break;
74: }
75: return get_longi (addr);
76: }
77:
78: STATIC_INLINE uae_u32 mem_access_delay_word_read_ce020 (uaecptr addr)
79: {
80: checkcycles_ce020 ();
81: switch (ce_banktype[addr >> 16])
82: {
83: case CE_MEMBANK_CHIP:
84: if ((addr & 3) == 3) {
85: uae_u16 v;
86: v = wait_cpu_cycle_read_ce020 (addr + 0, 0) << 8;
87: v |= wait_cpu_cycle_read_ce020 (addr + 1, 0) << 0;
88: return v;
89: } else {
90: return wait_cpu_cycle_read_ce020 (addr, 1);
91: }
92: case CE_MEMBANK_FAST:
93: case CE_MEMBANK_FAST16BIT:
94: if ((addr & 3) == 3)
95: do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE);
96: else
97: do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE);
98: break;
99: }
100: return get_word (addr);
101: }
102:
103: STATIC_INLINE uae_u32 mem_access_delay_wordi_read_ce020 (uaecptr addr)
104: {
105: checkcycles_ce020 ();
106: switch (ce_banktype[addr >> 16])
107: {
108: case CE_MEMBANK_CHIP:
109: return wait_cpu_cycle_read_ce020 (addr, 1);
110: case CE_MEMBANK_FAST:
111: case CE_MEMBANK_FAST16BIT:
112: do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE);
113: break;
114: }
115: return get_wordi (addr);
116: }
117:
118: STATIC_INLINE uae_u32 mem_access_delay_byte_read_ce020 (uaecptr addr)
119: {
120: checkcycles_ce020 ();
121: switch (ce_banktype[addr >> 16])
122: {
123: case CE_MEMBANK_CHIP:
124: return wait_cpu_cycle_read_ce020 (addr, 0);
125: case CE_MEMBANK_FAST:
126: case CE_MEMBANK_FAST16BIT:
127: do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE);
128: break;
129:
130: }
131: return get_byte (addr);
132: }
133:
134: STATIC_INLINE void mem_access_delay_byte_write_ce020 (uaecptr addr, uae_u32 v)
135: {
136: checkcycles_ce020 ();
137: switch (ce_banktype[addr >> 16])
138: {
139: case CE_MEMBANK_CHIP:
140: wait_cpu_cycle_write_ce020 (addr, 0, v);
141: return;
142: case CE_MEMBANK_FAST:
143: case CE_MEMBANK_FAST16BIT:
144: do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE);
145: break;
146: }
147: put_byte (addr, v);
148: }
149:
150: STATIC_INLINE void mem_access_delay_word_write_ce020 (uaecptr addr, uae_u32 v)
151: {
152: checkcycles_ce020 ();
153: switch (ce_banktype[addr >> 16])
154: {
155: case CE_MEMBANK_CHIP:
156: if ((addr & 3) == 3) {
157: wait_cpu_cycle_write_ce020 (addr + 0, 0, (v >> 8) & 0xff);
158: wait_cpu_cycle_write_ce020 (addr + 1, 0, (v >> 0) & 0xff);
159: } else {
160: wait_cpu_cycle_write_ce020 (addr + 0, 1, v);
161: }
162: return;
163: break;
164: case CE_MEMBANK_FAST:
165: case CE_MEMBANK_FAST16BIT:
166: if ((addr & 3) == 3)
167: do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE);
168: else
169: do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE);
170: break;
171: }
172: put_word (addr, v);
173: }
174:
175: STATIC_INLINE void mem_access_delay_long_write_ce020 (uaecptr addr, uae_u32 v)
176: {
177: checkcycles_ce020 ();
178: switch (ce_banktype[addr >> 16])
179: {
180: case CE_MEMBANK_CHIP:
181: if ((addr & 3) == 3) {
182: wait_cpu_cycle_write_ce020 (addr + 0, 1, (v >> 16) & 0xffff);
183: wait_cpu_cycle_write_ce020 (addr + 2, 1, (v >> 0) & 0xffff);
184: } else {
185: wait_cpu_cycle_write_ce020 (addr + 0, -1, v);
186: }
187: return;
188: break;
189: case CE_MEMBANK_FAST:
190: if ((addr & 3) != 0)
191: do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE);
192: else
193: do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE);
194: break;
195: case CE_MEMBANK_FAST16BIT:
196: do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE);
197: break;
198: }
199: put_long (addr, v);
200: }
201:
202: STATIC_INLINE uae_u32 get_long_ce020 (uaecptr addr)
203: {
204: return mem_access_delay_long_read_ce020 (addr);
205: }
206: STATIC_INLINE uae_u32 get_word_ce020 (uaecptr addr)
207: {
208: return mem_access_delay_word_read_ce020 (addr);
209: }
210: STATIC_INLINE uae_u32 get_byte_ce020 (uaecptr addr)
211: {
212: return mem_access_delay_byte_read_ce020 (addr);
213: }
214:
215: STATIC_INLINE void put_long_ce020 (uaecptr addr, uae_u32 v)
216: {
217: mem_access_delay_long_write_ce020 (addr, v);
218: }
219: STATIC_INLINE void put_word_ce020 (uaecptr addr, uae_u32 v)
220: {
221: mem_access_delay_word_write_ce020 (addr, v);
222: }
223: STATIC_INLINE void put_byte_ce020 (uaecptr addr, uae_u32 v)
224: {
225: mem_access_delay_byte_write_ce020 (addr, v);
226: }
227:
228: extern uae_u32 get_word_ce020_prefetch (int);
229:
230: STATIC_INLINE uae_u32 get_long_ce020_prefetch (int o)
231: {
232: uae_u32 v;
233: v = get_word_ce020_prefetch (o) << 16;
234: v |= get_word_ce020_prefetch (o + 2);
235: return v;
236: }
237:
238: STATIC_INLINE uae_u32 next_iword_020ce (void)
239: {
240: uae_u32 r = get_word_ce020_prefetch (0);
241: m68k_incpc (2);
242: return r;
243: }
244: STATIC_INLINE uae_u32 next_ilong_020ce (void)
245: {
246: uae_u32 r = get_long_ce020_prefetch (0);
247: m68k_incpc (4);
248: return r;
249: }
250:
251: STATIC_INLINE void m68k_do_bsr_ce020 (uaecptr oldpc, uae_s32 offset)
252: {
253: m68k_areg (regs, 7) -= 4;
254: put_long_ce020 (m68k_areg (regs, 7), oldpc);
255: m68k_incpc (offset);
256: }
257: STATIC_INLINE void m68k_do_rts_ce020 (void)
258: {
259: m68k_setpc (get_long_ce020 (m68k_areg (regs, 7)));
260: m68k_areg (regs, 7) += 4;
261: }
262: #endif
263:
264: #ifdef CPUEMU_21
265:
266: extern uae_u32 get_word_ce030_prefetch (int);
267: extern void write_dcache030 (uaecptr, uae_u32, int);
268: extern uae_u32 read_dcache030 (uaecptr, int);
269:
270: STATIC_INLINE void put_long_ce030 (uaecptr addr, uae_u32 v)
271: {
272: write_dcache030 (addr, v, 2);
273: mem_access_delay_long_write_ce020 (addr, v);
274: }
275: STATIC_INLINE void put_word_ce030 (uaecptr addr, uae_u32 v)
276: {
277: write_dcache030 (addr, v, 1);
278: mem_access_delay_word_write_ce020 (addr, v);
279: }
280: STATIC_INLINE void put_byte_ce030 (uaecptr addr, uae_u32 v)
281: {
282: write_dcache030 (addr, v, 0);
283: mem_access_delay_byte_write_ce020 (addr, v);
284: }
285: STATIC_INLINE uae_u32 get_long_ce030 (uaecptr addr)
286: {
287: return read_dcache030 (addr, 2);
288: }
289: STATIC_INLINE uae_u32 get_word_ce030 (uaecptr addr)
290: {
291: return read_dcache030 (addr, 1);
292: }
293: STATIC_INLINE uae_u32 get_byte_ce030 (uaecptr addr)
294: {
295: return read_dcache030 (addr, 0);
296: }
297:
298: STATIC_INLINE uae_u32 get_long_ce030_prefetch (int o)
299: {
300: uae_u32 v;
301: v = get_word_ce030_prefetch (o) << 16;
302: v |= get_word_ce030_prefetch (o + 2);
303: return v;
304: }
305:
306: STATIC_INLINE uae_u32 next_iword_030ce (void)
307: {
308: uae_u32 r = get_word_ce030_prefetch (0);
309: m68k_incpc (2);
310: return r;
311: }
312: STATIC_INLINE uae_u32 next_ilong_030ce (void)
313: {
314: uae_u32 r = get_long_ce030_prefetch (0);
315: m68k_incpc (4);
316: return r;
317: }
318:
319: STATIC_INLINE void m68k_do_bsr_ce030 (uaecptr oldpc, uae_s32 offset)
320: {
321: m68k_areg (regs, 7) -= 4;
322: put_long_ce030 (m68k_areg (regs, 7), oldpc);
323: m68k_incpc (offset);
324: }
325: STATIC_INLINE void m68k_do_rts_ce030 (void)
326: {
327: m68k_setpc (get_long_ce030 (m68k_areg (regs, 7)));
328: m68k_areg (regs, 7) += 4;
329: }
330: #endif
331:
332: #ifdef CPUEMU_12
333:
334: STATIC_INLINE void ipl_fetch (void)
335: {
336: regs.ipl = regs.ipl_pin;
337: }
338:
339: STATIC_INLINE uae_u32 mem_access_delay_word_read (uaecptr addr)
340: {
341: switch (ce_banktype[addr >> 16])
342: {
343: case CE_MEMBANK_CHIP:
344: return wait_cpu_cycle_read (addr, 1);
345: case CE_MEMBANK_FAST:
346: case CE_MEMBANK_FAST16BIT:
347: do_cycles_ce000 (4);
348: break;
349: }
350: return get_word (addr);
351: }
352: STATIC_INLINE uae_u32 mem_access_delay_wordi_read (uaecptr addr)
353: {
354: switch (ce_banktype[addr >> 16])
355: {
356: case CE_MEMBANK_CHIP:
357: return wait_cpu_cycle_read (addr, 1);
358: case CE_MEMBANK_FAST:
359: case CE_MEMBANK_FAST16BIT:
360: do_cycles_ce000 (4);
361: break;
362: }
363: return get_wordi (addr);
364: }
365:
366: STATIC_INLINE uae_u32 mem_access_delay_byte_read (uaecptr addr)
367: {
368: switch (ce_banktype[addr >> 16])
369: {
370: case CE_MEMBANK_CHIP:
371: return wait_cpu_cycle_read (addr, 0);
372: case CE_MEMBANK_FAST:
373: case CE_MEMBANK_FAST16BIT:
374: do_cycles_ce000 (4);
375: break;
376:
377: }
378: return get_byte (addr);
379: }
380: STATIC_INLINE void mem_access_delay_byte_write (uaecptr addr, uae_u32 v)
381: {
382: switch (ce_banktype[addr >> 16])
383: {
384: case CE_MEMBANK_CHIP:
385: wait_cpu_cycle_write (addr, 0, v);
386: return;
387: case CE_MEMBANK_FAST:
388: case CE_MEMBANK_FAST16BIT:
389: do_cycles_ce000 (4);
390: break;
391: }
392: put_byte (addr, v);
393: }
394: STATIC_INLINE void mem_access_delay_word_write (uaecptr addr, uae_u32 v)
395: {
396: switch (ce_banktype[addr >> 16])
397: {
398: case CE_MEMBANK_CHIP:
399: wait_cpu_cycle_write (addr, 1, v);
400: return;
401: break;
402: case CE_MEMBANK_FAST:
403: case CE_MEMBANK_FAST16BIT:
404: do_cycles_ce000 (4);
405: break;
406: }
407: put_word (addr, v);
408: }
409:
410: STATIC_INLINE uae_u32 get_long_ce (uaecptr addr)
411: {
412: uae_u32 v = mem_access_delay_word_read (addr) << 16;
413: v |= mem_access_delay_word_read (addr + 2);
414: return v;
415: }
416: STATIC_INLINE uae_u32 get_word_ce (uaecptr addr)
417: {
418: return mem_access_delay_word_read (addr);
419: }
420: STATIC_INLINE uae_u32 get_wordi_ce (uaecptr addr)
421: {
422: return mem_access_delay_wordi_read (addr);
423: }
424: STATIC_INLINE uae_u32 get_byte_ce (uaecptr addr)
425: {
426: return mem_access_delay_byte_read (addr);
427: }
428: STATIC_INLINE uae_u32 get_word_ce_prefetch (int o)
429: {
430: uae_u32 v = regs.irc;
431: regs.irc = get_wordi_ce (m68k_getpc () + o);
432: return v;
433: }
434:
435: STATIC_INLINE void put_long_ce (uaecptr addr, uae_u32 v)
436: {
437: mem_access_delay_word_write (addr, v >> 16);
438: mem_access_delay_word_write (addr + 2, v);
439: }
440: STATIC_INLINE void put_word_ce (uaecptr addr, uae_u32 v)
441: {
442: mem_access_delay_word_write (addr, v);
443: }
444: STATIC_INLINE void put_byte_ce (uaecptr addr, uae_u32 v)
445: {
446: mem_access_delay_byte_write (addr, v);
447: }
448:
449: STATIC_INLINE void m68k_do_rts_ce (void)
450: {
451: uaecptr pc;
452: pc = get_word_ce (m68k_areg (regs, 7)) << 16;
453: pc |= get_word_ce (m68k_areg (regs, 7) + 2);
454: m68k_areg (regs, 7) += 4;
455: if (pc & 1)
456: exception3 (0x4e75, m68k_getpc (), pc);
457: else
458: m68k_setpc (pc);
459: }
460:
461: STATIC_INLINE void m68k_do_bsr_ce (uaecptr oldpc, uae_s32 offset)
462: {
463: m68k_areg (regs, 7) -= 4;
464: put_word_ce (m68k_areg (regs, 7), oldpc >> 16);
465: put_word_ce (m68k_areg (regs, 7) + 2, oldpc);
466: m68k_incpc (offset);
467: }
468:
469: STATIC_INLINE void m68k_do_jsr_ce (uaecptr oldpc, uaecptr dest)
470: {
471: m68k_areg (regs, 7) -= 4;
472: put_word_ce (m68k_areg (regs, 7), oldpc >> 16);
473: put_word_ce (m68k_areg (regs, 7) + 2, oldpc);
474: m68k_setpc (dest);
475: }
476: #endif
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