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1.1.1.4 root 1: /*
1.1.1.5 root 2: * UAE - The Un*x Amiga Emulator
3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
19: */
1.1.1.4 root 20:
21: #include "sysconfig.h"
22: #include "sysdeps.h"
23: #include <ctype.h>
24: #include <string.h>
25:
26: #include "readcpu.h"
27:
1.1.1.5 root 28: char *ua (const char *s) {
29: return strdup(s);
30: }
31:
1.1.1.4 root 32: #define BOOL_TYPE "int"
33: /* Define the minimal 680x0 where NV flags are not affected by xBCD instructions. */
1.1.1.6 ! root 34: #define xBCD_KEEPS_N_FLAG 4
! 35: #define xBCD_KEEPS_V_FLAG 2
1.1.1.4 root 36:
37: static FILE *headerfile;
38: static FILE *stblfile;
39:
40: static int using_prefetch, using_indirect, using_mmu;
41: static int using_prefetch_020, using_ce020;
42: static int using_exception_3;
1.1.1.5 root 43: static int using_bus_error;
1.1.1.4 root 44: static int using_ce;
45: static int using_tracer;
46: static int using_waitstates;
1.1.1.5 root 47: static int using_simple_cycles;
48: static int cpu_level, cpu_generic;
1.1.1.4 root 49: static int count_read, count_write, count_cycles, count_ncycles;
50: static int count_cycles_ce020;
51: static int count_read_ea, count_write_ea, count_cycles_ea;
52: static const char *mmu_postfix;
53: static int memory_cycle_cnt;
54: static int did_prefetch;
1.1.1.5 root 55: static int ipl_fetched;
1.1.1.4 root 56:
57: static int optimized_flags;
58:
59: #define GF_APDI 1
60: #define GF_AD8R 2
61: #define GF_PC8R 4
62: #define GF_AA 7
63: #define GF_NOREFILL 8
64: #define GF_PREFETCH 16
65: #define GF_FC 32
66: #define GF_MOVE 64
67: #define GF_IR2IRC 128
68: #define GF_LRMW 256
69: #define GF_NOFAULTPC 512
70: #define GF_RMW 1024
71: #define GF_OPCE020 2048
1.1.1.6 ! root 72: #define GF_REVERSE 4096
! 73: #define GF_REVERSE2 8192
1.1.1.4 root 74:
75: /* For the current opcode, the next lower level that will have different code.
1.1.1.5 root 76: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
77: * are done with that opcode. */
1.1.1.4 root 78: static int next_cpu_level;
79:
80: static int *opcode_map;
81: static int *opcode_next_clev;
82: static int *opcode_last_postfix;
83: static unsigned long *counts;
84: static int generate_stbl;
85: static int mmufixupcnt;
86: static int mmufixupstate;
1.1.1.5 root 87: static int disp020cnt;
1.1.1.4 root 88: static bool candormw;
89: static bool genastore_done;
90: static char rmw_varname[100];
1.1.1.5 root 91: static unsigned long current_opcode;
1.1.1.4 root 92:
93: #define GENA_GETV_NO_FETCH 0
94: #define GENA_GETV_FETCH 1
95: #define GENA_GETV_FETCH_ALIGN 2
96: #define GENA_MOVEM_DO_INC 0
97: #define GENA_MOVEM_NO_INC 1
98: #define GENA_MOVEM_MOVE16 2
99:
1.1.1.5 root 100: static const char *srcl, *dstl;
101: static const char *srcw, *dstw;
102: static const char *srcb, *dstb;
103: static const char *srcblrmw, *srcwlrmw, *srcllrmw;
104: static const char *dstblrmw, *dstwlrmw, *dstllrmw;
105: static const char *srcbrmw, *srcwrmw, *srclrmw;
106: static const char *dstbrmw, *dstwrmw, *dstlrmw;
1.1.1.6 ! root 107: static const char *prefetch_long, *prefetch_word, *prefetch_opcode;
1.1.1.5 root 108: static const char *srcli, *srcwi, *srcbi, *nextl, *nextw;
109: static const char *srcld, *dstld;
110: static const char *srcwd, *dstwd;
111: static const char *do_cycles, *disp000, *disp020, *getpc;
1.1.1.4 root 112:
113: #define fetchmode_fea 1
114: #define fetchmode_cea 2
115: #define fetchmode_fiea 3
116: #define fetchmode_ciea 4
117: #define fetchmode_jea 5
118:
1.1.1.5 root 119: /* (SC) central hacking place for 030/040 instruction timinigs. This is carefully adjusted
120: in order to
121: - make all ROM POST happy
122: - make diagnostic kernels (diagnostics and dvt040) happy
123: - give reasonable results in NXbench
124: */
125: static int adjust_cycles(int cycles) {
126: struct instr *curi = table68k + current_opcode;
127: // General instruction timing scaling factors for 030/040. Mostly guesswork based
128: // on NXbench scores
129: switch(cpu_level) {
130: case 3: cycles *= 3; cycles /= 2; break;
131: case 4: cycles *= 1; cycles /= 3; break;
132: }
133: if(cycles == 0) cycles = 1;
134: // special cases for timing loops, ROM POST depend on these
135: switch (cpu_level) {
136: case 3: // MC68030
137: switch(curi->mnemo) {
138: case i_DBcc: cycles = 6; break;
139: case i_Bcc: cycles = 4; break;
140: case i_ASL: cycles = 2; break;
141: case i_MOVE: cycles /= 5; break;
142: }
143: break;
144: case 4: // MC68040
145: switch(curi->mnemo) {
146: case i_DBcc: cycles = 4; break;
147: }
148: break;
149: }
150: return cycles;
151: }
152:
153: /*NORETURN */static void term (void)
1.1.1.4 root 154: {
1.1.1.5 root 155: printf("Abort!\n");
156: abort ();
1.1.1.4 root 157: }
1.1.1.5 root 158: /*NORETURN */static void term_err (const char *err)
1.1.1.4 root 159: {
1.1.1.5 root 160: printf ("%s\n", err);
161: term ();
1.1.1.4 root 162: }
163:
164: static void read_counts (void)
165: {
1.1.1.5 root 166: FILE *file;
167: unsigned int opcode, count, total;
168: char name[20];
169: int nr = 0;
170: memset (counts, 0, 65536 * sizeof *counts);
171:
172: count = 0;
173: file = fopen ("frequent.68k", "r");
174: if (file) {
175: if (fscanf (file, "Total: %u\n", &total) == 0) {
176: abort ();
177: }
178: while (fscanf (file, "%x: %u %s\n", &opcode, &count, name) == 3) {
179: opcode_next_clev[nr] = 5;
180: opcode_last_postfix[nr] = -1;
181: opcode_map[nr++] = opcode;
182: counts[opcode] = count;
183: }
184: fclose (file);
185: }
186: if (nr == nr_cpuop_funcs)
187: return;
188: for (opcode = 0; opcode < 0x10000; opcode++) {
189: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
190: && counts[opcode] == 0)
191: {
192: opcode_next_clev[nr] = 5;
193: opcode_last_postfix[nr] = -1;
194: opcode_map[nr++] = opcode;
195: counts[opcode] = count;
196: }
197: }
198: if (nr != nr_cpuop_funcs)
199: term ();
1.1.1.4 root 200: }
201:
202: static char endlabelstr[80];
203: static int endlabelno = 0;
204: static int need_endlabel;
1.1.1.5 root 205: static int genamode_cnt, genamode8r_offset[2];
1.1.1.4 root 206:
207: static int n_braces, limit_braces;
208: static int m68k_pc_offset, m68k_pc_offset_old;
1.1.1.5 root 209: static int m68k_pc_total;
210: static int branch_inst;
1.1.1.4 root 211: static int insn_n_cycles, insn_n_cycles020;
212: static int ir2irc;
213:
214: static int tail_ce020, total_ce020, head_in_ea_ce020;
215: static bool head_ce020_cycs_done, tail_ce020_done;
216: static int subhead_ce020;
217: static struct instr *curi_ce020;
218: static bool no_prefetch_ce020;
219: static bool got_ea_ce020;
220:
221: static void fpulimit (void)
222: {
1.1.1.5 root 223: if (limit_braces)
224: return;
225: printf ("\n#ifdef FPUEMU\n");
226: limit_braces = n_braces;
227: n_braces = 0;
228: }
229:
230: static int s_count_read, s_count_write, s_count_cycles, s_count_ncycles;
231:
232: static void push_ins_cnt(void)
233: {
234: s_count_read = count_read;
235: s_count_write = count_write;
236: s_count_cycles = count_cycles;
237: s_count_ncycles = count_ncycles;
1.1.1.4 root 238: }
1.1.1.5 root 239: static void pop_ins_cnt(void)
1.1.1.4 root 240: {
1.1.1.5 root 241: count_read = s_count_read;
242: count_write = s_count_write;
243: count_cycles = s_count_cycles;
244: count_ncycles = s_count_ncycles;
1.1.1.4 root 245: }
246:
1.1.1.5 root 247: static bool isce020(void)
248: {
249: if (!using_ce020)
250: return false;
251: if (using_ce020 >= 3)
252: return false;
253: return true;
254: }
255: static bool isprefetch020(void)
256: {
257: if (!using_prefetch_020)
258: return false;
259: if (using_prefetch_020 >= 3)
260: return false;
261: return true;
262: }
1.1.1.4 root 263:
1.1.1.5 root 264: static void addcycles_ce020_2 (int cycles, const char *s)
1.1.1.4 root 265: {
1.1.1.5 root 266: if (!isce020())
267: return;
268: if (cycles > 0) {
269: if (s == NULL)
270: printf ("\t%s (%d);\n", do_cycles, cycles);
271: else
272: printf ("\t%s (%d); /* %s */\n", do_cycles, cycles, s);
273: }
274: count_cycles += cycles;
275: count_cycles_ce020 += cycles;
1.1.1.4 root 276: }
1.1.1.5 root 277: static void addcycles_ce020 (int cycles)
1.1.1.4 root 278: {
1.1.1.5 root 279: addcycles_ce020_2 (cycles, NULL);
1.1.1.4 root 280: }
281:
282: static void get_prefetch_020 (void)
283: {
1.1.1.5 root 284: if (!isprefetch020() || no_prefetch_ce020)
285: return;
1.1.1.6 ! root 286: printf ("\tregs.irc = %s (%d);\n", prefetch_opcode, m68k_pc_offset);
1.1.1.5 root 287: }
288: static void get_prefetch_020_continue(void)
289: {
290: if (!isprefetch020())
291: return;
1.1.1.6 ! root 292: if (using_ce020) {
! 293: if (using_ce020 > 1)
! 294: printf("\tcontinue_ce030_prefetch();\n");
! 295: else
1.1.1.5 root 296: printf("\tcontinue_ce020_prefetch();\n");
1.1.1.6 ! root 297: } else {
! 298: if (using_prefetch_020 > 1)
! 299: printf ("\tcontinue_030_prefetch();\n");
1.1.1.5 root 300: else
301: printf ("\tcontinue_020_prefetch();\n");
1.1.1.4 root 302: }
1.1.1.6 ! root 303: }
1.1.1.4 root 304:
305: static void returntail (bool iswrite)
306: {
1.1.1.5 root 307: if (!isce020()) {
308: if (isprefetch020()) {
309: if (!tail_ce020_done) {
310: if (!did_prefetch)
311: get_prefetch_020 ();
312: did_prefetch = 1;
313: tail_ce020_done = true;
314: }
315: }
316: return;
317: }
318: if (!tail_ce020_done) {
319: total_ce020 -= 2;
1.1.1.4 root 320: #if 0
1.1.1.5 root 321: if (iswrite) {
322: printf("\t/* C - %d = %d */\n", memory_cycle_cnt, total_ce020 - memory_cycle_cnt);
323: total_ce020 -= memory_cycle_cnt;
324: } else {
325: printf("\t/* C = %d */\n", total_ce020);
326: }
1.1.1.4 root 327: #endif
1.1.1.5 root 328: if (0 && total_ce020 <= 0) {
329: printf ("\t/* C was zero */\n");
330: total_ce020 = 1;
331: }
332: if (!did_prefetch)
333: get_prefetch_020 ();
334: if (total_ce020 > 0)
335: addcycles_ce020 (total_ce020);
336:
1.1.1.6 ! root 337: //printf ("\tregs.irc = %s;\n", prefetch_opcode);
1.1.1.5 root 338: if (0 && total_ce020 >= 2) {
339: printf ("\top_cycles = get_cycles () - op_cycles;\n");
340: printf ("\top_cycles /= cpucycleunit;\n");
341: printf ("\tif (op_cycles < %d) {\n", total_ce020);
342: printf ("\t\tdo_cycles_ce020 ((%d) - op_cycles);\n", total_ce020);
343: printf ("\t}\n");
344: }
1.1.1.4 root 345: #if 0
1.1.1.5 root 346: if (tail_ce020 > 0) {
347: printf ("\tregs.ce020_tail = %d * cpucycleunit;\n", tail_ce020);
348: printf ("\tregs.ce020_tail_cycles = get_cycles () + regs.ce020_tail;\n");
349: } else {
350: printf ("\tregs.ce020_tail = 0;\n");
351: }
1.1.1.4 root 352: #endif
1.1.1.5 root 353: tail_ce020_done = true;
354: }
1.1.1.4 root 355: }
356:
1.1.1.5 root 357: static void returncycles (const char *s, int cycles)
1.1.1.4 root 358: {
1.1.1.5 root 359: if (using_ce || using_ce020) {
1.1.1.4 root 360: #if 0
1.1.1.5 root 361: if (tail_ce020 == 0)
362: printf ("\tregs.ce020memcycles -= 2 * cpucycleunit; /* T=0 */ \n");
363: else if (tail_ce020 == 1)
364: printf ("\tregs.ce020memcycles -= 1 * cpucycleunit; /* T=1 */ \n");
365: else if (tail_ce020 == 2)
366: printf ("\tregs.ce020memcycles -= 0 * cpucycleunit; /* T=2 */\n");
1.1.1.4 root 367: #endif
1.1.1.5 root 368: printf ("%sreturn;\n", s);
369: return;
370: }
371: if (using_simple_cycles)
372: printf ("%sreturn %d + count_cycles;\n", s, adjust_cycles(cycles));
373: else
374: printf ("%sreturn %d;\n", s, adjust_cycles(cycles));
375: }
376:
377: static void addcycles_ce020_4 (const char *name, int head, int tail, int cycles)
378: {
379: if (!isce020())
380: return;
381: if (!head && !tail && !cycles)
382: return;
383: printf ("\t/* %s H:%d,T:%d,C:%d */\n", name, head, tail, cycles);
384: }
385: static void addcycles_ce020_5 (const char *name, int head, int tail, int cycles, int ophead)
386: {
387: if (!isce020())
388: return;
389: if (!head && !tail && !cycles && !ophead) {
390: printf ("\t/* OP zero */\n");
391: return;
392: }
393: count_cycles += cycles;
394: if (!ophead) {
395: addcycles_ce020_4 (name, head, tail, cycles);
396: } else if (ophead > 0) {
397: printf ("\t/* %s H:%d-,T:%d,C:%d */\n", name, head, tail, cycles);
398: } else {
399: printf ("\t/* %s H:%d+,T:%d,C:%d */\n", name, head, tail, cycles);
400: }
401: }
402:
403: static void addcycles000_nonces(const char *s, const char *sc)
404: {
405: if (using_simple_cycles) {
406: printf("%scount_cycles += (%s) * CYCLE_UNIT / 2;\n", s, sc);
407: count_ncycles++;
408: }
409: }
410: static void addcycles000_nonce(const char *s, int c)
411: {
412: if (using_simple_cycles) {
413: printf("%scount_cycles += %d * CYCLE_UNIT / 2;\n", s, c);
414: count_ncycles++;
415: }
416: }
417:
418: static void addcycles000_onlyce (int cycles)
419: {
420: if (using_ce) {
421: printf ("\t%s (%d);\n", do_cycles, cycles);
422: }
1.1.1.4 root 423: }
424:
425: static void addcycles000 (int cycles)
426: {
1.1.1.5 root 427: if (using_ce) {
428: printf ("\t%s (%d);\n", do_cycles, cycles);
429: }
430: count_cycles += cycles;
1.1.1.4 root 431: }
432:
1.1.1.5 root 433: static void addcycles000_3 (const char *s)
434: {
435: if (using_ce) {
436: printf ("%sif (cycles > 0) %s (cycles);\n", s, do_cycles);
437: }
438: count_ncycles++;
1.1.1.4 root 439: }
440:
441: static int isreg (amodes mode)
442: {
1.1.1.5 root 443: if (mode == Dreg || mode == Areg)
444: return 1;
445: return 0;
1.1.1.4 root 446: }
447:
448: static void start_brace (void)
449: {
1.1.1.5 root 450: n_braces++;
451: printf ("{");
1.1.1.4 root 452: }
453:
454: static void close_brace (void)
455: {
1.1.1.5 root 456: assert (n_braces > 0);
457: n_braces--;
458: printf ("}");
1.1.1.4 root 459: }
460:
461: static void finish_braces (void)
462: {
1.1.1.5 root 463: while (n_braces > 0)
464: close_brace ();
1.1.1.4 root 465: }
466:
467: static void pop_braces (int to)
468: {
1.1.1.5 root 469: while (n_braces > to)
470: close_brace ();
1.1.1.4 root 471: }
472:
473: static int bit_size (int size)
474: {
1.1.1.5 root 475: switch (size) {
476: case sz_byte: return 8;
477: case sz_word: return 16;
478: case sz_long: return 32;
479: default: term ();
480: }
481: return 0;
1.1.1.4 root 482: }
483:
484: static const char *bit_mask (int size)
485: {
1.1.1.5 root 486: switch (size) {
487: case sz_byte: return "0xff";
488: case sz_word: return "0xffff";
489: case sz_long: return "0xffffffff";
490: default: term ();
491: }
492: return 0;
1.1.1.4 root 493: }
494:
495: static void add_mmu040_movem (int movem)
496: {
1.1.1.5 root 497: if (movem != 3)
498: return;
499: printf ("\tif (mmu040_movem) {\n");
500: printf ("\t\tsrca = mmu040_movem_ea;\n");
501: printf ("\t} else\n");
502: start_brace ();
503: }
504:
505: static void gen_nextilong2 (const char *type, const char *name, int flags, int movem)
506: {
507: int r = m68k_pc_offset;
508: m68k_pc_offset += 4;
509:
510: printf ("\t%s %s;\n", type, name);
511: add_mmu040_movem (movem);
512: if (using_ce020) {
513: if (flags & GF_NOREFILL)
514: printf("\t%s = %s (%d);\n", name, prefetch_long, r);
515: else
516: printf("\t%s = %s (%d);\n", name, prefetch_long, r);
517: count_read += 2;
518: } else if (using_ce) {
519: /* we must do this because execution order of (something | something2) is not defined */
520: if (flags & GF_NOREFILL) {
521: printf ("\t%s = %s (%d) << 16;\n", name, prefetch_word, r + 2);
522: count_read++;
523: printf ("\t%s |= regs.irc;\n", name);
524: } else {
525: printf ("\t%s = %s (%d) << 16;\n", name, prefetch_word, r + 2);
526: count_read++;
527: printf ("\t%s |= %s (%d);\n", name, prefetch_word, r + 4);
528: count_read++;
529: }
530: } else {
531: if (using_prefetch) {
532: if (flags & GF_NOREFILL) {
533: printf ("\t%s = %s (%d) << 16;\n", name, prefetch_word, r + 2);
534: count_read++;
535: printf ("\t%s |= regs.irc;\n", name);
536: insn_n_cycles += 4;
537: } else {
538: printf ("\t%s = %s (%d) << 16;\n", name, prefetch_word, r + 2);
539: count_read += 2;
540: printf ("\t%s |= %s (%d);\n", name, prefetch_word, r + 4);
541: insn_n_cycles += 8;
542: }
543: } else {
544: insn_n_cycles += 8;
545: printf ("\t%s = %s (%d);\n", name, prefetch_long, r);
546: }
547: }
1.1.1.4 root 548: }
1.1.1.5 root 549: static void gen_nextilong (const char *type, const char *name, int flags)
1.1.1.4 root 550: {
1.1.1.5 root 551: gen_nextilong2 (type, name, flags, 0);
1.1.1.4 root 552: }
553:
554: static const char *gen_nextiword (int flags)
555: {
1.1.1.5 root 556: static char buffer[80];
557: int r = m68k_pc_offset;
558: m68k_pc_offset += 2;
559:
560: if (using_ce020) {
561: if (flags & GF_NOREFILL)
562: sprintf(buffer, "%s (%d)", prefetch_word, r);
563: else
564: sprintf(buffer, "%s (%d)", prefetch_word, r);
565: count_read++;
566: } else if (using_ce) {
567: if (flags & GF_NOREFILL) {
568: strcpy (buffer, "regs.irc");
569: } else {
570: sprintf (buffer, "%s (%d)", prefetch_word, r + 2);
571: count_read++;
572: }
573: } else {
574: if (using_prefetch) {
575: if (flags & GF_NOREFILL) {
576: strcpy (buffer, "regs.irc");
577: } else {
578: sprintf (buffer, "%s (%d)", prefetch_word, r + 2);
579: count_read++;
580: insn_n_cycles += 4;
581: }
582: } else {
583: sprintf (buffer, "%s (%d)", prefetch_word, r);
584: insn_n_cycles += 4;
585: }
586: }
587: return buffer;
1.1.1.4 root 588: }
589:
590: static const char *gen_nextibyte (int flags)
591: {
1.1.1.5 root 592: static char buffer[80];
593: int r = m68k_pc_offset;
594: m68k_pc_offset += 2;
595:
596: if (using_ce020 || using_prefetch_020) {
597: if (flags & GF_NOREFILL)
598: sprintf(buffer, "(uae_u8)%s (%d)", prefetch_word, r);
599: else
600: sprintf(buffer, "(uae_u8)%s (%d)", prefetch_word, r);
601: count_read++;
602: } else if (using_ce) {
603: if (flags & GF_NOREFILL) {
604: strcpy (buffer, "(uae_u8)regs.irc");
605: } else {
606: sprintf (buffer, "(uae_u8)%s (%d)", prefetch_word, r + 2);
607: count_read++;
608: }
609: } else {
610: insn_n_cycles += 4;
611: if (using_prefetch) {
612: if (flags & GF_NOREFILL) {
613: strcpy (buffer, "(uae_u8)regs.irc");
614: } else {
615: sprintf (buffer, "(uae_u8)%s (%d)", prefetch_word, r + 2);
616: insn_n_cycles += 4;
617: count_read++;
618: }
619: } else {
620: sprintf (buffer, "%s (%d)", srcbi, r);
621: insn_n_cycles += 4;
622: }
623: }
624: return buffer;
1.1.1.4 root 625: }
626:
1.1.1.6 ! root 627: static void makefromsr(void)
1.1.1.4 root 628: {
1.1.1.5 root 629: printf ("\tMakeFromSR();\n");
630: if (using_ce || isce020())
631: printf ("\tregs.ipl_pin = intlev ();\n");
1.1.1.4 root 632: }
633:
1.1.1.6 ! root 634: static void makefromsr_t0(void)
! 635: {
! 636: printf ("\tMakeFromSR_T0();\n");
! 637: if (using_ce || isce020())
! 638: printf ("\tregs.ipl_pin = intlev ();\n");
! 639: }
! 640:
1.1.1.4 root 641: static void check_ipl (void)
642: {
1.1.1.5 root 643: if (ipl_fetched)
644: return;
645: if (using_ce || isce020())
646: printf ("\tipl_fetch ();\n");
647: ipl_fetched = 1;
648: }
649:
650: static void single_check_ipl(void)
651: {
652: check_ipl();
653: ipl_fetched = 2;
654:
655: }
656: /* this is not true, it seems to be microcode controller */
657:
658: /* Apparently interrupt state is sampled
659: * during any memory access. Because we don't
660: * know if there are future memory accesses,
661: * we'll check each memory access after prefetch
662: * and recheck interrupt state again.
663: */
664: static void check_ipl_again (void)
1.1.1.4 root 665: {
1.1.1.5 root 666: if (ipl_fetched != 1)
667: return;
668: if (using_ce)
669: printf ("\tipl_fetch ();\n");
670: }
671:
672: static void irc2ir_2 (bool dozero)
673: {
674: if (!using_prefetch)
675: return;
676: if (ir2irc)
677: return;
678: ir2irc = 1;
679: printf ("\tregs.ir = regs.irc;\n");
680: if (dozero)
681: printf ("\tregs.irc = 0;\n");
682: check_ipl ();
1.1.1.4 root 683: }
684: static void irc2ir (void)
685: {
1.1.1.5 root 686: irc2ir_2 (false);
1.1.1.4 root 687: }
688:
689: static void fill_prefetch_2 (void)
690: {
1.1.1.5 root 691: if (!using_prefetch)
692: return;
693: printf ("\t%s (%d);\n", prefetch_word, m68k_pc_offset + 2);
694: did_prefetch = 1;
695: ir2irc = 0;
696: count_read++;
697: insn_n_cycles += 4;
1.1.1.4 root 698: }
699:
700: static void fill_prefetch_1 (int o)
701: {
1.1.1.5 root 702: if (using_prefetch) {
703: printf ("\t%s (%d);\n", prefetch_word, o);
704: did_prefetch = 1;
705: ir2irc = 0;
706: count_read++;
707: insn_n_cycles += 4;
708: }
1.1.1.4 root 709: }
710:
1.1.1.6 ! root 711: // don't check trace bits
! 712: static void fill_prefetch_full_ntx (void)
! 713: {
! 714: if (using_prefetch) {
! 715: fill_prefetch_1 (0);
! 716: irc2ir ();
! 717: fill_prefetch_1 (2);
! 718: } else if (isprefetch020()) {
! 719: did_prefetch = 2;
! 720: total_ce020 -= 4;
! 721: returntail (false);
! 722: if (cpu_level >= 3)
! 723: printf ("\tfill_prefetch_030_ntx();\n");
! 724: else if (cpu_level == 2)
! 725: printf ("\tfill_prefetch_020_ntx();\n");
! 726: }
! 727: }
! 728:
! 729: // check trace bits
1.1.1.4 root 730: static void fill_prefetch_full (void)
731: {
1.1.1.5 root 732: if (using_prefetch) {
733: fill_prefetch_1 (0);
734: irc2ir ();
735: fill_prefetch_1 (2);
736: } else if (isprefetch020()) {
737: did_prefetch = 2;
738: total_ce020 -= 4;
739: returntail (false);
740: if (cpu_level >= 3)
1.1.1.6 ! root 741: printf ("\tfill_prefetch_030();\n");
1.1.1.5 root 742: else if (cpu_level == 2)
1.1.1.6 ! root 743: printf ("\tfill_prefetch_020();\n");
! 744: } else if (!using_prefetch_020 && cpu_level >= 2) {
! 745: printf("\tif(regs.t0) check_t0_trace();\n");
1.1.1.5 root 746: }
1.1.1.4 root 747: }
748:
749: // 68000 and 68010 only
750: static void fill_prefetch_full_000 (void)
751: {
1.1.1.5 root 752: if (!using_prefetch)
753: return;
754: fill_prefetch_full ();
1.1.1.4 root 755: }
756:
757: // 68020+
758: static void fill_prefetch_full_020 (void)
759: {
1.1.1.6 ! root 760: if (!using_prefetch_020) {
! 761: printf("\tif(regs.t0) check_t0_trace();\n");
1.1.1.5 root 762: return;
1.1.1.6 ! root 763: }
1.1.1.5 root 764: fill_prefetch_full ();
1.1.1.4 root 765: }
766:
767: static void fill_prefetch_0 (void)
768: {
1.1.1.5 root 769: if (!using_prefetch)
770: return;
771: printf ("\t%s (0);\n", prefetch_word);
772: did_prefetch = 1;
773: ir2irc = 0;
774: count_read++;
775: insn_n_cycles += 4;
1.1.1.4 root 776: }
777:
778: static void fill_prefetch_next_1 (void)
779: {
1.1.1.5 root 780: irc2ir ();
781: fill_prefetch_1 (m68k_pc_offset + 2);
1.1.1.4 root 782: }
783:
784: static void fill_prefetch_next (void)
785: {
1.1.1.5 root 786: if (using_prefetch) {
787: fill_prefetch_next_1 ();
788: }
789: // if (using_prefetch_020) {
790: // printf ("\t%s (%d);\n", prefetch_word, m68k_pc_offset);
791: // did_prefetch = 1;
792: // }
1.1.1.4 root 793: }
794:
795: static void fill_prefetch_finish (void)
796: {
1.1.1.5 root 797: if (did_prefetch)
798: return;
799: if (using_prefetch) {
800: fill_prefetch_1 (m68k_pc_offset);
801: }
802: if (using_prefetch_020) {
803: did_prefetch = 1;
804: }
1.1.1.4 root 805: }
806:
807: static void setpc (const char *format, ...)
808: {
1.1.1.5 root 809: va_list parms;
810: char buffer[1000];
811:
812: va_start (parms, format);
813: _vsnprintf (buffer, 1000 - 1, format, parms);
814: va_end (parms);
815:
816: if (using_mmu || using_prefetch || using_prefetch_020)
817: printf ("\tm68k_setpci (%s);\n", buffer);
818: else
819: printf ("\tm68k_setpc (%s);\n", buffer);
1.1.1.4 root 820: }
821:
822: static void incpc (const char *format, ...)
823: {
1.1.1.5 root 824: va_list parms;
825: char buffer[1000];
826:
827: va_start (parms, format);
828: _vsnprintf (buffer, 1000 - 1, format, parms);
829: va_end (parms);
830:
831: if (using_mmu || using_prefetch || using_prefetch_020)
832: printf ("\tm68k_incpci (%s);\n", buffer);
833: else
834: printf ("\tm68k_incpc (%s);\n", buffer);
1.1.1.4 root 835: }
836:
837: static void sync_m68k_pc (void)
838: {
1.1.1.5 root 839: m68k_pc_offset_old = m68k_pc_offset;
840: if (m68k_pc_offset == 0)
841: return;
842: incpc ("%d", m68k_pc_offset);
843: m68k_pc_total += m68k_pc_offset;
844: m68k_pc_offset = 0;
845: }
846:
847: static void clear_m68k_offset(void)
848: {
849: m68k_pc_total += m68k_pc_offset;
850: m68k_pc_offset = 0;
1.1.1.4 root 851: }
852:
853: static void sync_m68k_pc_noreset (void)
854: {
1.1.1.5 root 855: sync_m68k_pc ();
856: m68k_pc_offset = m68k_pc_offset_old;
1.1.1.4 root 857: }
858:
1.1.1.5 root 859: static void addmmufixup (const char *reg)
1.1.1.4 root 860: {
1.1.1.5 root 861: if (!using_mmu)
862: return;
863: if (using_mmu == 68040 && (mmufixupstate || mmufixupcnt > 0))
864: return;
865: printf ("\tmmufixup[%d].reg = %s;\n", mmufixupcnt, reg);
866: printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", mmufixupcnt, reg);
867: mmufixupstate |= 1 << mmufixupcnt;
868: mmufixupcnt++;
1.1.1.4 root 869: }
870:
871: static void clearmmufixup (int cnt)
872: {
1.1.1.5 root 873: if (mmufixupstate & (1 << cnt)) {
874: printf ("\tmmufixup[%d].reg = -1;\n", cnt);
875: mmufixupstate &= ~(1 << cnt);
876: }
1.1.1.4 root 877: }
878:
879: static void gen_set_fault_pc (void)
880: {
1.1.1.5 root 881: if (using_mmu != 68040)
882: return;
883: sync_m68k_pc ();
884: printf ("\tregs.instruction_pc = %s;\n", getpc);
885: printf ("\tmmu_restart = false;\n");
886: m68k_pc_offset = 0;
887: clearmmufixup (0);
1.1.1.4 root 888: }
889:
890: static void syncmovepc (int getv, int flags)
891: {
892: #if 0
1.1.1.5 root 893: if (!(flags & GF_MOVE))
894: return;
895: if (getv == 1) {
896: sync_m68k_pc ();
897: //fill_prefetch_next ();
898: }
1.1.1.4 root 899: #endif
900: }
901:
902: static void head_cycs (int h)
903: {
1.1.1.5 root 904: if (head_ce020_cycs_done)
905: return;
906: if (h < 0)
907: return;
908: //printf ("\tdo_sync_tail (%d);\n", h);
909: //printf ("\tdo_head_cycles_ce020 (%d);\n", h);
910: head_ce020_cycs_done = true;
911: tail_ce020 = -1;
1.1.1.4 root 912: }
913:
914: static void add_head_cycs (int h)
915: {
1.1.1.5 root 916: if (!isce020())
917: return;
918: head_ce020_cycs_done = false;
919: head_cycs (h);
1.1.1.4 root 920: }
921:
922: static void addopcycles_ce20 (int h, int t, int c, int subhead)
923: {
1.1.1.5 root 924: head_cycs (h);
925:
926: //c = 0;
1.1.1.4 root 927: #if 0
1.1.1.5 root 928: if (tail_ce020 == 1)
929: printf ("\tregs.ce020memcycles -= 1 * cpucycleunit; /* T=1 */ \n");
930: else if (tail_ce020 == 2)
931: printf ("\tregs.ce020memcycles -= 2 * cpucycleunit; /* T=2 */\n");
1.1.1.4 root 932: #endif
1.1.1.5 root 933: if (1 && !subhead && (h > 0 || t > 0 || c > 0) && got_ea_ce020) {
934: if (!did_prefetch) {
935: get_prefetch_020 ();
936: did_prefetch = 1;
937: }
938: if (1) {
939: if (h > 0) {
1.1.1.6 ! root 940: printf ("\tlimit_cycles_ce020(%d);\n", h);
1.1.1.5 root 941: } else {
1.1.1.6 ! root 942: printf ("\tlimit_all_cycles_ce020();\n");
1.1.1.5 root 943: }
944: }
945: }
946:
1.1.1.4 root 947: #if 0
1.1.1.5 root 948: if (tail_ce020 >= 0 && h >= 0 && head_in_ea_ce020 == 0) {
949: int largest = tail_ce020 > h ? tail_ce020: h;
950: if (tail_ce020 != h) {
951: //printf ("\tdo_cycles_ce020 (%d - %d);\n", tail_ce020 > h ? tail_ce020 : h, tail_ce020 > h ? h : tail_ce020);
952: //printf ("\tdo_cycles_ce020 (%d - %d);\n", tail_ce020 > h ? tail_ce020 : h, tail_ce020 > h ? h : tail_ce020);
953: if (h) {
954: printf ("\tregs.ce020memcycles -= %d * cpucycleunit;\n", h);
955: printf ("\tif (regs.ce020memcycles < 0) {\n");
956: //printf ("\t\tx_do_cycles (-regs.ce020memcycles);\n");
957: printf ("\t\tregs.ce020memcycles = 0;\n");
958: printf ("\t}\n");
959: } else {
960: printf ("\tregs.ce020memcycles = 0;\n");
961: }
962: //printf ("\tregs.ce020memcycles = 0;\n");
963:
1.1.1.4 root 964: #if 0
1.1.1.5 root 965: if (tail_ce020)
966: printf ("\tregs.ce020_tail = get_cycles () - regs.ce020_tail;\n");
967: else
968: printf ("\tregs.ce020_tail = 0;\n");
969: printf ("\tif (regs.ce020_tail < %d * cpucycleunit)\n", largest);
970: printf ("\t\tx_do_cycles (%d * cpucycleunit - regs.ce020_tail);\n", largest);
1.1.1.4 root 971: #endif
1.1.1.5 root 972: } else if (h) {
973: printf ("\t/* ea tail == op head (%d) */\n", h);
974:
975: printf ("\tregs.ce020memcycles -= %d * cpucycleunit;\n", h);
976: printf ("\tif (regs.ce020memcycles < 0) {\n");
977: //printf ("\t\tx_do_cycles (-regs.ce020memcycles);\n");
978: printf ("\t\tregs.ce020memcycles = 0;\n");
979: printf ("\t}\n");
980: }
981: }
1.1.1.4 root 982: #endif
1.1.1.5 root 983:
984: if (h < 0)
985: h = 0;
986:
1.1.1.6 ! root 987: if (c < 8) // HACK
! 988: c = 0;
1.1.1.5 root 989:
990: // c = internal cycles needed after head cycles and before tail cycles. Not total cycles.
991: addcycles_ce020_5 ("op", h, t, c - h - t, -subhead);
992: //printf ("\tregs.irc = get_word_ce020_prefetch (%d);\n", m68k_pc_offset);
1.1.1.4 root 993: #if 0
1.1.1.5 root 994: if (c - h - t > 0) {
995: printf ("\t%s (%d);\n", do_cycles, c - h - t);
996: count_cycles_ce020 += c;
997: count_cycles += c;
998: }
1.1.1.4 root 999: #endif
1.1.1.5 root 1000: //printf ("\tregs.ce020_tail = 0;\n");
1001: total_ce020 = c;
1002: tail_ce020 = t;
1003: // if (total_ce020 >= 2)
1004: // printf ("\tint op_cycles = get_cycles ();\n");
1.1.1.4 root 1005: }
1006:
1007: static void addop_ce020 (struct instr *curi, int subhead)
1008: {
1.1.1.6 ! root 1009: if (isce020()) {
1.1.1.5 root 1010: int h = curi->head;
1011: int t = curi->tail;
1012: int c = curi->clocks;
1.1.1.4 root 1013: #if 0
1.1.1.5 root 1014: if ((((curi->sduse & 2) && !isreg (curi->smode)) || (((curi->sduse >> 4) & 2) && !isreg (curi->dmode))) && using_waitstates) {
1015: t += using_waitstates;
1016: c += using_waitstates;
1017: }
1.1.1.4 root 1018: #endif
1.1.1.5 root 1019: addopcycles_ce20 (h, t, c, -subhead);
1.1.1.4 root 1020: }
1.1.1.6 ! root 1021: }
1.1.1.4 root 1022:
1.1.1.5 root 1023: static void addcycles_ea_ce020_5 (const char *ea, int h, int t, int c, int oph)
1.1.1.4 root 1024: {
1.1.1.6 ! root 1025: if (!isce020())
! 1026: return;
! 1027:
1.1.1.5 root 1028: head_cycs (h + oph);
1029:
1030: // if (!h && !h && !c && !oph)
1031: // return;
1032:
1033: c = c - h - t;
1034:
1.1.1.6 ! root 1035: c = 0; // HACK
1.1.1.5 root 1036:
1037: if (!oph) {
1038: printf ("\t/* ea H:%d,T:%d,C:%d %s */\n", h, t, c, ea);
1039: } else {
1040: if (oph && t)
1041: term_err ("Both op head and tail can't be non-zero");
1042: if (oph > 0) {
1043: printf ("\t/* ea H:%d+%d=%d,T:%d,C:%d %s */\n", h, oph, h + oph, t, c, ea);
1044: h += oph;
1045: } else {
1046: printf ("\t/* ea H:%d-%d=%d,T:%d,C:%d %s */\n", h, -oph, h + oph, t, c, ea);
1047: h += oph;
1048: }
1049: }
1050:
1051: if (h) {
1.1.1.6 ! root 1052: printf ("\tlimit_cycles_ce020(%d);\n", h);
1.1.1.5 root 1053: } else {
1.1.1.6 ! root 1054: printf ("\tlimit_all_cycles_ce020();\n");
1.1.1.5 root 1055: }
1056:
1057: if (1 && c > 0) {
1058: printf ("\t%s (%d);\n", do_cycles, c);
1059: count_cycles += c;
1060: }
1061: tail_ce020 = t;
1062: head_in_ea_ce020 = oph;
1063: got_ea_ce020 = true;
1064: // if (t > 0)
1065: // printf ("\tregs.ce020_tail = get_cycles () + %d * cpucycleunit;\n", t);
1.1.1.4 root 1066: }
1.1.1.5 root 1067: static void addcycles_ea_ce020_4 (const char *ea, int h, int t, int c)
1.1.1.4 root 1068: {
1.1.1.5 root 1069: addcycles_ea_ce020_5 (ea, h, t, c, 0);
1.1.1.4 root 1070: }
1071:
1072: #define SETCE020(h2,t2,c2) { h = h2; t = t2; c = c2; }
1073: #define SETCE020H(h2,t2,c2) { h = h2; oph = curi ? curi->head : 0; t = t2; c = c2; }
1074:
1075: static int gence020cycles_fiea (struct instr *curi, wordsizes ssize, amodes dmode)
1076: {
1.1.1.5 root 1077: bool l = ssize == sz_long;
1078: int h = 0, t = 0, c = 0, oph = 0;
1079: switch ((int)dmode)
1080: {
1081: case Dreg:
1082: case Areg:
1083: if (!l)
1084: SETCE020H(2, 0, 2)
1085: else
1086: SETCE020H(4, 0, 4)
1087: break;
1088: case Aind: // (An)
1089: if (!l)
1090: SETCE020(1, 1, 3)
1091: else
1092: SETCE020(1, 0, 4)
1093: break;
1094: case Aipi: // (An)+
1095: if (!l)
1096: SETCE020(2, 1, 5)
1097: else
1098: SETCE020(4, 1, 7)
1099: break;
1100: case Apdi: // -(An)
1101: if (!l)
1102: SETCE020(2, 2, 4)
1103: else
1104: SETCE020(2, 0, 4)
1105: break;
1106: case Ad8r: // (d8,An,Xn)
1107: case PC8r: // (d8,PC,Xn)
1108: if (!l)
1109: SETCE020(6, 2, 8)
1110: else
1111: SETCE020(8, 2, 10)
1112: break;
1113: case Ad16: // (d16,An)
1114: case PC16: // (d16,PC)
1115: if (!l)
1116: SETCE020(2, 0, 4)
1117: else
1118: SETCE020(4, 0, 6)
1119: break;
1120: case absw:
1121: if (!l)
1122: SETCE020(4, 2, 6)
1123: else
1124: SETCE020(6, 2, 8)
1125: break;
1126: case absl:
1127: if (!l)
1128: SETCE020(3, 0, 6)
1129: else
1130: SETCE020(5, 0, 8)
1131: break;
1132: }
1133: addcycles_ea_ce020_5 ("fiea", h, t, c, oph);
1134: return oph;
1.1.1.4 root 1135: }
1136:
1137:
1138: static int gence020cycles_ciea (struct instr *curi, wordsizes ssize, amodes dmode)
1139: {
1.1.1.5 root 1140: int h = 0, t = 0, c = 0, oph = 0;
1141: bool l = ssize == sz_long;
1142: switch ((int)dmode)
1143: {
1144: case Dreg:
1145: case Areg:
1146: if (!l)
1147: SETCE020H(2, 0, 2)
1148: else
1149: SETCE020H(4, 0, 4)
1150: break;
1151: case Aind: // (An)
1152: if (!l)
1153: SETCE020H(2, 0, 2)
1154: else
1155: SETCE020H(4, 0, 4)
1156: break;
1157: case Aipi: // (An)+
1158: if (!l)
1159: SETCE020(2, 0, 4)
1160: else
1161: SETCE020(4, 0, 6)
1162: break;
1163: case Apdi: // -(An)
1164: if (!l)
1165: SETCE020H(2, 0, 2)
1166: else
1167: SETCE020H(4, 0, 4)
1168: break;
1169: case Ad8r: // (d8,An,Xn)
1170: case PC8r: // (d8,PC,Xn)
1171: if (!l)
1172: SETCE020H(6, 0, 6)
1173: else
1174: SETCE020H(8, 0, 8)
1175: break;
1176: case Ad16: // (d16,An)
1177: case PC16: // (d16,PC)
1178: if (!l)
1179: SETCE020H(4, 0, 4)
1180: else
1181: SETCE020H(6, 0, 6)
1182: break;
1183: case absw:
1184: if (!l)
1185: SETCE020H(4, 0, 4)
1186: else
1187: SETCE020H(6, 0, 6)
1188: break;
1189: case absl:
1190: if (!l)
1191: SETCE020H(6, 0, 6)
1192: else
1193: SETCE020H(8, 0, 8)
1194: break;
1195: }
1196: addcycles_ea_ce020_5 ("ciea", h, t, c, oph);
1197: return oph;
1.1.1.4 root 1198: }
1199:
1200:
1201: static int gence020cycles_fea (amodes mode)
1202: {
1.1.1.5 root 1203: int h = 0, t = 0, c = 0, ws = 0;
1204: switch ((int)mode)
1205: {
1206: case Dreg:
1207: case Areg:
1208: SETCE020(0, 0, 0)
1209: break;
1210: case Aind: // (An)
1211: ws++;
1212: SETCE020(1, 1, 3)
1213: break;
1214: case Aipi: // (An)+
1215: ws++;
1216: SETCE020(0, 1, 3)
1217: break;
1218: case Apdi: // -(An)
1219: ws++;
1220: SETCE020(2, 2, 4)
1221: break;
1222: case Ad8r: // (d8,An,Xn)
1223: case PC8r: // (d8,PC,Xn)
1224: ws++;
1225: SETCE020(4, 2, 6)
1226: break;
1227: case Ad16: // (d16,An)
1228: case PC16: // (d16,PC)
1229: ws++;
1230: SETCE020(2, 2, 4)
1231: break;
1232: case absw:
1233: ws++;
1234: SETCE020(2, 2, 4)
1235: break;
1236: case absl:
1237: ws++;
1238: SETCE020(1, 0, 4)
1239: break;
1240: }
1.1.1.4 root 1241: #if 0
1.1.1.5 root 1242: if (using_waitstates) {
1243: t += ws * using_waitstates;
1244: c += ws * using_waitstates;
1245: }
1.1.1.4 root 1246: #endif
1.1.1.5 root 1247: addcycles_ea_ce020_4 ("fea", h, t, c);
1248: return 0;
1.1.1.4 root 1249: }
1250:
1251: static int gence020cycles_cea (struct instr *curi, amodes mode)
1252: {
1.1.1.5 root 1253: int h = 0, t = 0, c = 0, oph = 0;
1254: switch ((int)mode)
1255: {
1256: case Dreg:
1257: case Areg:
1258: SETCE020(0, 0, 0);
1259: break;
1260: case Aind: // (An)
1261: SETCE020H(2 + h, 0, 2);
1262: break;
1263: case Aipi: // (An)+
1264: SETCE020(0, 0, 2);
1265: break;
1266: case Apdi: // -(An)
1267: SETCE020H(2, 0, 2)
1268: break;
1269: case Ad8r: // (d8,An,Xn)
1270: case PC8r: // (d8,PC,Xn)
1271: SETCE020H(4, 0, 4)
1272: break;
1273: case Ad16: // (d16,An)
1274: case PC16: // (d16,PC)
1275: SETCE020H(2, 0, 2)
1276: break;
1277: case absw:
1278: SETCE020H(2, 0, 2)
1279: break;
1280: case absl:
1281: SETCE020H(4, 0, 4)
1282: break;
1283: }
1284: addcycles_ea_ce020_5 ("cea", h, t, c, oph);
1285: return oph;
1.1.1.4 root 1286: }
1287:
1288: static int gence020cycles_jea (struct instr *curi, amodes mode)
1289: {
1.1.1.5 root 1290: int h = 0, t = 0, c = 0, oph = 0;
1291: switch ((int)mode)
1292: {
1293: case Aind: // (An)
1294: SETCE020H(2, 0, 2)
1295: break;
1296: case Ad16: // (d16,An)
1297: case PC16: // (d16,PC)
1298: SETCE020H(4, 0, 4)
1299: break;
1300: case absw:
1301: SETCE020H(2, 0, 2)
1302: break;
1303: case absl:
1304: SETCE020H(2, 0, 2)
1305: break;
1306: }
1307: addcycles_ea_ce020_5 ("jea", h, t, c, oph);
1308: return oph;
1.1.1.4 root 1309: }
1310:
1311: static void next_level_000 (void)
1312: {
1.1.1.5 root 1313: if (next_cpu_level < 0)
1314: next_cpu_level = 0;
1.1.1.4 root 1315: }
1316:
1317: static void maybeaddop_ce020 (int flags)
1318: {
1.1.1.5 root 1319: if (flags & GF_OPCE020)
1320: addop_ce020 (curi_ce020, subhead_ce020);
1.1.1.4 root 1321: }
1322:
1323:
1324: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
1.1.1.5 root 1325: * the calling routine handles Apdi and Aipi modes.
1326: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
1.1.1.4 root 1327:
1.1.1.6 ! root 1328: /* fixup indicates if we want to fix up address registers in pre decrement
1.1.1.5 root 1329: * or post increment mode now (0) or later (1). A value of 2 will then be
1330: * used to do the actual fix up. This allows to do all memory readings
1331: * before any register is modified, and so to rerun operation without
1332: * side effect in case a bus fault is generated by any memory access.
1333: * XJ - 2006/11/13 */
1334:
1335: static void genamode2x (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fetchmode)
1336: {
1337: char namea[100];
1338: bool rmw = false;
1339: int pc_68000_offset = m68k_pc_offset;
1340: int pc_68000_offset_fetch = 0;
1341: int pc_68000_offset_store = 0;
1342:
1343: sprintf (namea, "%sa", name);
1344: if ((flags & GF_RMW) && using_mmu == 68060) {
1345: strcpy (rmw_varname, name);
1346: candormw = true;
1347: rmw = true;
1348: }
1349:
1350: if (mode == Ad8r || mode == PC8r) {
1351: genamode8r_offset[genamode_cnt] = m68k_pc_total + m68k_pc_offset;
1352: genamode_cnt++;
1353: }
1354:
1355: start_brace ();
1356:
1357: switch (mode) {
1358: case Dreg:
1359: if (movem)
1360: term ();
1361: if (getv == 1)
1362: switch (size) {
1363: case sz_byte:
1.1.1.4 root 1364: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
1.1.1.5 root 1365: /* This causes the target compiler to generate better code on few systems */
1366: printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg (regs, %s))[3];\n", name, reg);
1.1.1.4 root 1367: #else
1.1.1.5 root 1368: printf ("\tuae_s8 %s = m68k_dreg (regs, %s);\n", name, reg);
1.1.1.4 root 1369: #endif
1.1.1.5 root 1370: break;
1371: case sz_word:
1.1.1.4 root 1372: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
1.1.1.5 root 1373: printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg (regs, %s))[1];\n", name, reg);
1.1.1.4 root 1374: #else
1.1.1.5 root 1375: printf ("\tuae_s16 %s = m68k_dreg (regs, %s);\n", name, reg);
1376: #endif
1377: break;
1378: case sz_long:
1379: printf ("\tuae_s32 %s = m68k_dreg (regs, %s);\n", name, reg);
1380: break;
1381: default:
1382: term ();
1383: }
1384: maybeaddop_ce020 (flags);
1385: syncmovepc (getv, flags);
1386: return;
1387: case Areg:
1388: if (movem)
1389: term ();
1390: if (getv == 1)
1391: switch (size) {
1392: case sz_word:
1393: printf ("\tuae_s16 %s = m68k_areg (regs, %s);\n", name, reg);
1394: break;
1395: case sz_long:
1396: printf ("\tuae_s32 %s = m68k_areg (regs, %s);\n", name, reg);
1397: break;
1398: default:
1399: term ();
1400: }
1401: maybeaddop_ce020 (flags);
1402: syncmovepc (getv, flags);
1403: return;
1404: case Aind: // (An)
1405: switch (fetchmode)
1406: {
1407: case fetchmode_fea:
1408: addcycles_ce020 (1);
1409: break;
1410: case fetchmode_cea:
1411: addcycles_ce020 (2);
1412: break;
1413: case fetchmode_jea:
1414: addcycles_ce020 (2);
1415: break;
1416: }
1417: printf ("\tuaecptr %sa;\n", name);
1418: add_mmu040_movem (movem);
1419: printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
1420: break;
1421: case Aipi: // (An)+
1422: switch (fetchmode)
1423: {
1424: case fetchmode_fea:
1425: addcycles_ce020 (1);
1426: break;
1427: case fetchmode_cea:
1428: break;
1429: }
1430: printf ("\tuaecptr %sa;\n", name);
1431: add_mmu040_movem (movem);
1432: printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
1433: break;
1434: case Apdi: // -(An)
1435: switch (fetchmode)
1436: {
1437: case fetchmode_fea:
1438: case fetchmode_cea:
1439: addcycles_ce020 (2);
1440: break;
1441: }
1442: printf ("\tuaecptr %sa;\n", name);
1443: add_mmu040_movem (movem);
1444: switch (size) {
1445: case sz_byte:
1446: if (movem)
1447: printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
1448: else
1449: printf ("\t%sa = m68k_areg (regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
1450: break;
1451: case sz_word:
1452: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
1453: break;
1454: case sz_long:
1455: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
1456: break;
1457: default:
1458: term ();
1459: }
1460: if (!(flags & GF_APDI)) {
1461: addcycles000 (2);
1462: insn_n_cycles += 2;
1463: count_cycles_ea += 2;
1464: pc_68000_offset_fetch += 2;
1465: }
1466: break;
1467: case Ad16: // (d16,An)
1468: printf ("\tuaecptr %sa;\n", name);
1469: add_mmu040_movem (movem);
1470: printf ("\t%sa = m68k_areg (regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags));
1471: count_read_ea++;
1472: break;
1473: case PC16: // (d16,PC)
1474: printf ("\tuaecptr %sa;\n", name);
1475: add_mmu040_movem (movem);
1476: printf ("\t%sa = %s + %d;\n", name, getpc, m68k_pc_offset);
1477: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
1478: break;
1479: case Ad8r: // (d8,An,Xn)
1480: switch (fetchmode)
1481: {
1482: case fetchmode_fea:
1483: addcycles_ce020 (4);
1484: break;
1485: case fetchmode_cea:
1486: case fetchmode_jea:
1487: break;
1488: }
1489: printf ("\tuaecptr %sa;\n", name);
1490: if (cpu_level > 1) {
1491: if (next_cpu_level < 1)
1492: next_cpu_level = 1;
1493: sync_m68k_pc ();
1494: add_mmu040_movem (movem);
1495: start_brace ();
1496: /* This would ordinarily be done in gen_nextiword, which we bypass. */
1497: insn_n_cycles += 4;
1498: printf ("\t%sa = %s (m68k_areg (regs, %s), %d);\n", name, disp020, reg, disp020cnt++);
1499: } else {
1500: if (!(flags & GF_AD8R)) {
1501: addcycles000 (2);
1502: insn_n_cycles += 2;
1503: count_cycles_ea += 2;
1504: }
1505: if ((flags & GF_NOREFILL) && using_prefetch) {
1506: printf ("\t%sa = %s (m68k_areg (regs, %s), regs.irc);\n", name, disp000, reg);
1507: } else {
1508: printf ("\t%sa = %s (m68k_areg (regs, %s), %s);\n", name, disp000, reg, gen_nextiword (flags));
1509: }
1510: count_read_ea++;
1511: }
1512: break;
1513: case PC8r: // (d8,PC,Xn)
1514: switch (fetchmode)
1515: {
1516: case fetchmode_fea:
1517: addcycles_ce020 (4);
1518: break;
1519: case fetchmode_cea:
1520: case fetchmode_jea:
1521: break;
1522: }
1523: printf ("\tuaecptr tmppc;\n");
1524: printf ("\tuaecptr %sa;\n", name);
1525: if (cpu_level > 1) {
1526: if (next_cpu_level < 1)
1527: next_cpu_level = 1;
1528: sync_m68k_pc ();
1529: add_mmu040_movem (movem);
1530: start_brace ();
1531: /* This would ordinarily be done in gen_nextiword, which we bypass. */
1532: insn_n_cycles += 4;
1533: printf ("\ttmppc = %s;\n", getpc);
1534: printf ("\t%sa = %s (tmppc, %d);\n", name, disp020, disp020cnt++);
1535: } else {
1536: printf ("\ttmppc = %s + %d;\n", getpc, m68k_pc_offset);
1537: if (!(flags & GF_PC8R)) {
1538: addcycles000 (2);
1539: insn_n_cycles += 2;
1540: count_cycles_ea += 2;
1541: }
1542: if ((flags & GF_NOREFILL) && using_prefetch) {
1543: printf ("\t%sa = %s (tmppc, regs.irc);\n", name, disp000);
1544: } else {
1545: printf ("\t%sa = %s (tmppc, %s);\n", name, disp000, gen_nextiword (flags));
1546: }
1547: }
1548:
1549: break;
1550: case absw:
1551: printf ("\tuaecptr %sa;\n", name);
1552: add_mmu040_movem (movem);
1553: printf ("\t%sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
1554: pc_68000_offset_fetch += 2;
1555: break;
1556: case absl:
1557: gen_nextilong2 ("uaecptr", namea, flags, movem);
1558: count_read_ea += 2;
1559: pc_68000_offset_fetch += 4;
1560: pc_68000_offset_store += 2;
1561: break;
1562: case imm:
1563: // fetch immediate address
1564: if (getv != 1)
1565: term ();
1566: insn_n_cycles020++;
1567: switch (size) {
1568: case sz_byte:
1569: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
1570: count_read_ea++;
1571: break;
1572: case sz_word:
1573: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
1574: count_read_ea++;
1575: break;
1576: case sz_long:
1577: gen_nextilong ("uae_s32", name, flags);
1578: count_read_ea += 2;
1579: break;
1580: default:
1581: term ();
1582: }
1583: maybeaddop_ce020 (flags);
1584: syncmovepc (getv, flags);
1585: return;
1586: case imm0:
1587: if (getv != 1)
1588: term ();
1589: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
1590: count_read_ea++;
1591: maybeaddop_ce020 (flags);
1592: syncmovepc (getv, flags);
1593: return;
1594: case imm1:
1595: if (getv != 1)
1596: term ();
1597: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
1598: count_read_ea++;
1599: maybeaddop_ce020 (flags);
1600: syncmovepc (getv, flags);
1601: return;
1602: case imm2:
1603: if (getv != 1)
1604: term ();
1605: gen_nextilong ("uae_s32", name, flags);
1606: count_read_ea += 2;
1607: maybeaddop_ce020 (flags);
1608: syncmovepc (getv, flags);
1609: return;
1610: case immi:
1611: if (getv != 1)
1612: term ();
1613: printf ("\tuae_u32 %s = %s;\n", name, reg);
1614: maybeaddop_ce020 (flags);
1615: syncmovepc (getv, flags);
1616: return;
1617: default:
1618: term ();
1619: }
1620:
1621: syncmovepc (getv, flags);
1622: maybeaddop_ce020 (flags);
1623:
1624: /* We get here for all non-reg non-immediate addressing modes to
1625: * actually fetch the value. */
1626:
1627: int exception_pc_offset = 0;
1628: if (getv == 2) {
1629: // store
1630: if (pc_68000_offset) {
1631: exception_pc_offset = pc_68000_offset + pc_68000_offset_store + 2;
1632: }
1633: } else {
1634: // fetch
1635: exception_pc_offset = pc_68000_offset + pc_68000_offset_fetch;
1636: }
1637:
1638: if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
1639: printf ("\tif (%sa & 1) {\n", name);
1640: if (exception_pc_offset)
1641: incpc("%d", exception_pc_offset);
1.1.1.6 ! root 1642: // MOVE.L EA,-(An) causing address error: stacked value is original An - 2, not An - 4.
! 1643: if ((flags & (GF_REVERSE | GF_REVERSE2)) && size == sz_long && mode == Apdi)
! 1644: printf("\t\t%sa += %d;\n", name, flags & GF_REVERSE2 ? -2 : 2);
1.1.1.5 root 1645: printf ("\t\texception3_%s(opcode, %sa);\n", getv == 2 ? "write" : "read", name);
1646: printf ("\t\tgoto %s;\n", endlabelstr);
1647: printf ("\t}\n");
1648: need_endlabel = 1;
1649: start_brace ();
1650: }
1651:
1652: if ((using_prefetch || using_ce) && using_bus_error && getv != 0) {
1653: if (exception_pc_offset)
1654: printf("\tbus_error_offset = %d;\n", exception_pc_offset);
1655: }
1656:
1657: if (flags & GF_PREFETCH)
1658: fill_prefetch_next ();
1659: else if (flags & GF_IR2IRC)
1660: irc2ir_2 (true);
1661:
1662: if (getv == 1) {
1663: start_brace ();
1.1.1.6 ! root 1664: if (using_mmu) {
1.1.1.5 root 1665: if (flags & GF_FC) {
1666: switch (size) {
1667: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = sfc%s_get_byte (%sa);\n", name, mmu_postfix, name); break;
1668: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = sfc%s_get_word (%sa);\n", name, mmu_postfix, name); break;
1669: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = sfc%s_get_long (%sa);\n", name, mmu_postfix, name); break;
1670: default: term ();
1671: }
1672: } else {
1673: switch (size) {
1674: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, (flags & GF_LRMW) ? srcblrmw : (rmw ? srcbrmw : srcb), name); break;
1675: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, (flags & GF_LRMW) ? srcwlrmw : (rmw ? srcwrmw : srcw), name); break;
1676: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, (flags & GF_LRMW) ? srcllrmw : (rmw ? srclrmw : srcl), name); break;
1677: default: term ();
1678: }
1679: }
1.1.1.6 ! root 1680: } else if (using_ce020 || using_prefetch_020) {
! 1681: switch (size) {
! 1682: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
! 1683: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
! 1684: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, srcl, name); count_read += 2; break;
! 1685: default: term ();
! 1686: }
! 1687: } else if (using_ce || using_prefetch) {
! 1688: switch (size) {
! 1689: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
! 1690: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
! 1691: case sz_long: {
! 1692: insn_n_cycles += 8;
! 1693: if ((flags & GF_REVERSE) && mode == Apdi)
! 1694: printf("\tuae_s32 %s = %s (%sa + 2); %s |= %s (%sa) << 16;\n", name, srcw, name, name, srcw, name);
! 1695: else
! 1696: printf("\tuae_s32 %s = %s (%sa) << 16; %s |= %s (%sa + 2);\n", name, srcw, name, name, srcw, name);
! 1697: count_read += 2;
! 1698: break;
! 1699: }
! 1700: default: term ();
! 1701: }
1.1.1.5 root 1702: } else {
1703: switch (size) {
1704: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
1705: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
1706: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, srcl, name); count_read += 2; break;
1707: default: term ();
1708: }
1709: }
1710: }
1711:
1712: /* We now might have to fix up the register for pre-dec or post-inc
1713: * addressing modes. */
1714: if (!movem)
1715: switch (mode) {
1716: case Aipi:
1717: addmmufixup (reg);
1718: switch (size) {
1719: case sz_byte:
1720: printf ("\tm68k_areg (regs, %s) += areg_byteinc[%s];\n", reg, reg);
1721: break;
1722: case sz_word:
1723: printf ("\tm68k_areg (regs, %s) += 2;\n", reg);
1724: break;
1725: case sz_long:
1726: printf ("\tm68k_areg (regs, %s) += 4;\n", reg);
1727: break;
1728: default:
1729: term ();
1730: }
1731: break;
1732: case Apdi:
1733: addmmufixup (reg);
1734: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
1735: break;
1736: default:
1737: break;
1738: }
1739:
1740: if (movem == 3) {
1741: close_brace ();
1742: }
1743: }
1744:
1745: static void genamode2 (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
1746: {
1747: genamode2x (mode, reg, size, name, getv, movem, flags, -1);
1748: }
1749:
1750: static void genamode (struct instr *curi, amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
1751: {
1752: int oldfixup = mmufixupstate;
1753: int subhead = 0;
1754: if (isce020() && curi) {
1755: switch (curi->fetchmode)
1756: {
1757: case fetchmode_fea:
1758: subhead = gence020cycles_fea (mode);
1759: break;
1760: case fetchmode_cea:
1761: subhead = gence020cycles_cea (curi, mode);
1762: break;
1763: case fetchmode_jea:
1764: subhead = gence020cycles_jea (curi, mode);
1765: break;
1766: }
1767: genamode2x (mode, reg, size, name, getv, movem, flags, curi->fetchmode);
1768: } else {
1769: genamode2 (mode, reg, size, name, getv, movem, flags);
1770: }
1771: if (using_mmu == 68040 && (oldfixup & 1)) {
1772: // we have fixup already active = this genamode call is destination mode and we can now clear previous source fixup.
1773: clearmmufixup (0);
1774: }
1.1.1.6 ! root 1775: if (curi)
1.1.1.5 root 1776: addop_ce020 (curi, subhead);
1777: }
1778:
1779: static void genamode3 (struct instr *curi, amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
1780: {
1781: int oldfixup = mmufixupstate;
1782: genamode2x (mode, reg, size, name, getv, movem, flags, curi ? curi->fetchmode : -1);
1783: if (using_mmu == 68040 && (oldfixup & 1)) {
1784: // we have fixup already active = this genamode call is destination mode and we can now clear previous source fixup.
1785: clearmmufixup (0);
1786: }
1787: }
1788:
1789: static void genamodedual (struct instr *curi, amodes smode, const char *sreg, wordsizes ssize, const char *sname, int sgetv, int sflags,
1790: amodes dmode, const char *dreg, wordsizes dsize, const char *dname, int dgetv, int dflags)
1791: {
1792: int subhead = 0;
1793: bool eadmode = false;
1794:
1795: if (isce020()) {
1796: switch (curi->fetchmode)
1797: {
1798: case fetchmode_fea:
1799: if (smode >= imm || isreg (smode)) {
1800: subhead = gence020cycles_fea (dmode);
1801: eadmode = true;
1802: } else {
1803: subhead = gence020cycles_fea (smode);
1804: }
1805: break;
1806: case fetchmode_cea:
1807: subhead = gence020cycles_cea (curi, smode);
1808: break;
1809: case fetchmode_fiea:
1810: subhead = gence020cycles_fiea (curi, ssize, dmode);
1811: break;
1812: case fetchmode_ciea:
1813: subhead = gence020cycles_ciea (curi, ssize, dmode);
1814: break;
1815: case fetchmode_jea:
1816: subhead = gence020cycles_jea (curi, smode);
1817: break;
1818: default:
1819: printf ("\t/* No EA */\n");
1820: break;
1821: }
1822: }
1823: subhead_ce020 = subhead;
1824: curi_ce020 = curi;
1825: genamode3 (curi, smode, sreg, ssize, sname, sgetv, 0, sflags);
1826: genamode3 (NULL, dmode, dreg, dsize, dname, dgetv, 0, dflags | (eadmode == true ? GF_OPCE020 : 0));
1827: if (eadmode == false)
1828: maybeaddop_ce020 (GF_OPCE020);
1829: }
1830:
1831: static void genastore_2 (const char *from, amodes mode, const char *reg, wordsizes size, const char *to, int store_dir, int flags)
1832: {
1833: if (candormw) {
1834: if (strcmp (rmw_varname, to) != 0)
1835: candormw = false;
1836: }
1837: genastore_done = true;
1838: returntail (mode != Dreg && mode != Areg);
1839:
1840: switch (mode) {
1841: case Dreg:
1842: switch (size) {
1843: case sz_byte:
1844: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
1845: break;
1846: case sz_word:
1847: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
1848: break;
1849: case sz_long:
1850: printf ("\tm68k_dreg (regs, %s) = (%s);\n", reg, from);
1851: break;
1852: default:
1853: term ();
1854: }
1855: break;
1856: case Areg:
1857: switch (size) {
1858: case sz_word:
1859: printf ("\tm68k_areg (regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
1860: break;
1861: case sz_long:
1862: printf ("\tm68k_areg (regs, %s) = (%s);\n", reg, from);
1863: break;
1864: default:
1865: term ();
1866: }
1867: break;
1868: case Aind:
1869: case Aipi:
1870: case Apdi:
1871: case Ad16:
1872: case Ad8r:
1873: case absw:
1874: case absl:
1875: case PC16:
1876: case PC8r:
1877: if (!(flags & GF_NOFAULTPC))
1878: gen_set_fault_pc ();
1.1.1.6 ! root 1879: if (using_mmu) {
! 1880: switch (size) {
! 1881: case sz_byte:
! 1882: insn_n_cycles += 4;
! 1883: if (flags & GF_FC)
! 1884: printf ("\tdfc%s_put_byte (%sa, %s);\n", mmu_postfix, to, from);
! 1885: else
! 1886: printf ("\t%s (%sa, %s);\n", (flags & GF_LRMW) ? dstblrmw : (candormw ? dstbrmw : dstb), to, from);
! 1887: break;
! 1888: case sz_word:
! 1889: insn_n_cycles += 4;
! 1890: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
! 1891: term ();
! 1892: if (flags & GF_FC)
! 1893: printf ("\tdfc%s_put_word (%sa, %s);\n", mmu_postfix, to, from);
! 1894: else
! 1895: printf ("\t%s (%sa, %s);\n", (flags & GF_LRMW) ? dstwlrmw : (candormw ? dstwrmw : dstw), to, from);
! 1896: break;
! 1897: case sz_long:
! 1898: insn_n_cycles += 8;
! 1899: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
! 1900: term ();
! 1901: if (flags & GF_FC)
! 1902: printf ("\tdfc%s_put_long (%sa, %s);\n", mmu_postfix, to, from);
! 1903: else
! 1904: printf ("\t%s (%sa, %s);\n", (flags & GF_LRMW) ? dstllrmw : (candormw ? dstlrmw : dstl), to, from);
! 1905: break;
! 1906: default:
! 1907: term ();
! 1908: }
! 1909: } else if (using_ce020 || using_prefetch_020) {
1.1.1.5 root 1910: switch (size) {
1911: case sz_byte:
1912: printf ("\t%s (%sa, %s);\n", dstb, to, from);
1913: count_write++;
1914: break;
1915: case sz_word:
1916: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1917: term ();
1918: printf ("\t%s (%sa, %s);\n", dstw, to, from);
1919: count_write++;
1920: break;
1921: case sz_long:
1922: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1923: term ();
1924: printf ("\t%s (%sa, %s);\n", dstl, to, from);
1925: count_write += 2;
1926: break;
1927: default:
1928: term ();
1929: }
1930: } else if (using_ce) {
1931: switch (size) {
1932: case sz_byte:
1933: check_ipl_again();
1934: printf ("\tx_put_byte (%sa, %s);\n", to, from);
1935: count_write++;
1936: break;
1937: case sz_word:
1938: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1939: term ();
1940: check_ipl_again();
1941: printf ("\tx_put_word (%sa, %s);\n", to, from);
1942: count_write++;
1943: break;
1944: case sz_long:
1945: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1946: term ();
1947: if (store_dir) {
1948: printf ("\t%s (%sa + 2, %s);\n", dstw, to, from);
1949: check_ipl_again();
1950: printf ("%s (%sa, %s >> 16);\n", dstw, to, from);
1951: } else {
1952: printf ("\t%s (%sa, %s >> 16);\n", dstw, to, from);
1953: check_ipl_again();
1954: printf ("\t%s (%sa + 2, %s);\n", dstw, to, from);
1955: }
1956: count_write += 2;
1957: break;
1958: default:
1959: term ();
1960: }
1961: } else if (using_prefetch) {
1962: switch (size) {
1963: case sz_byte:
1964: insn_n_cycles += 4;
1965: printf ("\t%s (%sa, %s);\n", dstb, to, from);
1966: count_write++;
1967: break;
1968: case sz_word:
1969: insn_n_cycles += 4;
1970: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1971: term ();
1972: printf ("\t%s (%sa, %s);\n", dstw, to, from);
1973: count_write++;
1974: break;
1975: case sz_long:
1976: insn_n_cycles += 8;
1977: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1978: term ();
1979: if (store_dir)
1980: printf ("\t%s (%sa + 2, %s); %s (%sa, %s >> 16);\n", dstw, to, from, dstw, to, from);
1981: else
1982: printf ("\t%s (%sa, %s >> 16); %s (%sa + 2, %s);\n", dstw, to, from, dstw, to, from);
1983: count_write += 2;
1984: break;
1985: default:
1986: term ();
1987: }
1988: } else {
1989: switch (size) {
1990: case sz_byte:
1991: insn_n_cycles += 4;
1992: printf ("\t%s (%sa, %s);\n", dstb, to, from);
1993: count_write++;
1994: break;
1995: case sz_word:
1996: insn_n_cycles += 4;
1997: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1998: term ();
1999: printf ("\t%s (%sa, %s);\n", dstw, to, from);
2000: count_write++;
2001: break;
2002: case sz_long:
2003: insn_n_cycles += 8;
2004: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
2005: term ();
2006: printf ("\t%s (%sa, %s);\n", dstl, to, from);
2007: count_write += 2;
2008: break;
2009: default:
2010: term ();
2011: }
2012: }
2013: break;
2014: case imm:
2015: case imm0:
2016: case imm1:
2017: case imm2:
2018: case immi:
2019: term ();
2020: break;
2021: default:
2022: term ();
2023: }
2024: }
2025:
2026: static void genastore (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
2027: {
2028: genastore_2 (from, mode, reg, size, to, 0, 0);
2029: }
2030: static void genastore_tas (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
2031: {
2032: genastore_2 (from, mode, reg, size, to, 0, GF_LRMW);
2033: }
2034: static void genastore_cas (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
2035: {
2036: genastore_2 (from, mode, reg, size, to, 0, GF_LRMW | GF_NOFAULTPC);
1.1.1.4 root 2037: }
1.1.1.5 root 2038: static void genastore_rev (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1.1.1.4 root 2039: {
1.1.1.5 root 2040: genastore_2 (from, mode, reg, size, to, 1, 0);
1.1.1.4 root 2041: }
1.1.1.5 root 2042: static void genastore_fc (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1.1.1.4 root 2043: {
1.1.1.5 root 2044: genastore_2 (from, mode, reg, size, to, 1, GF_FC);
1.1.1.4 root 2045: }
2046:
2047: static void movem_mmu060 (const char *code, int size, bool put, bool aipi, bool apdi)
2048: {
1.1.1.5 root 2049: const char *index;
2050: int dphase;
2051: int i;
2052: if (apdi) {
2053: dphase = 1;
2054: index = "movem_index2";
2055: } else {
2056: dphase = 0;
2057: index = "movem_index1";
2058: }
2059:
2060: if (!put) {
2061: printf("\tuae_u32 tmp[16];\n");
2062: printf("\tint tmpreg[16];\n");
2063: printf("\tint idx = 0;\n");
2064: for (i = 0; i < 2; i++) {
2065: char reg;
2066: if (i == dphase)
2067: reg = 'd';
2068: else
2069: reg = 'a';
2070: printf ("\twhile (%cmask) {\n", reg);
2071: if (apdi)
2072: printf ("\t\tsrca -= %d;\n", size);
2073: printf ("\t\ttmpreg[idx] = %s[%cmask] + %d;\n", index, reg, i == dphase ? 0 : 8);
2074: printf ("\t\ttmp[idx++] = %s;\n", code);
2075: if (!apdi)
2076: printf ("\t\tsrca += %d;\n", size);
2077: printf ("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
2078: printf ("\t}\n");
2079: }
2080: if (aipi || apdi)
2081: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
2082: printf ("\twhile (--idx >= 0) {\n");
2083: printf ("\t\tregs.regs[tmpreg[idx]] = tmp[idx];\n");
2084: printf ("\t}\n");
2085: } else {
2086: for (i = 0; i < 2; i++) {
2087: char reg;
2088: if (i == dphase)
2089: reg = 'd';
2090: else
2091: reg = 'a';
2092: printf ("\twhile (%cmask) {\n", reg);
2093: if (apdi)
2094: printf ("\t\tsrca -= %d;\n", size);
2095: if (put) {
2096: printf ("\t\t%s, m68k_%creg (regs, %s[%cmask]));\n", code, reg, index, reg);
2097: } else {
2098: printf ("\t\tm68k_%creg (regs, %s[%cmask]) = %s;\n", reg, index, reg, code);
2099: }
2100: if (!apdi)
2101: printf ("\t\tsrca += %d;\n", size);
2102: printf ("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
2103: printf ("\t}\n");
2104: }
2105: if (aipi || apdi)
2106: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
2107: }
1.1.1.4 root 2108: }
2109:
2110: static bool mmu040_special_movem (uae_u16 opcode)
2111: {
1.1.1.5 root 2112: if (using_mmu != 68040)
2113: return false;
2114: return true;
2115: // return (((((opcode >> 3) & 7) == 7) && ((opcode & 7) == 2 || (opcode & 7) == 3)) || ((opcode >> 3) & 7) == 6);
1.1.1.4 root 2116: }
2117:
2118: static void movem_mmu040 (const char *code, int size, bool put, bool aipi, bool apdi, uae_u16 opcode)
2119: {
1.1.1.5 root 2120: const char *index;
2121: int dphase;
2122: int i;
2123:
2124: if (apdi) {
2125: dphase = 1;
2126: index = "movem_index2";
2127: } else {
2128: dphase = 0;
2129: index = "movem_index1";
2130: }
2131:
2132: printf ("\tmmu040_movem = 1;\n");
2133: printf ("\tmmu040_movem_ea = srca;\n");
2134:
2135: for (i = 0; i < 2; i++) {
2136: char reg;
2137: if (i == dphase)
2138: reg = 'd';
2139: else
2140: reg = 'a';
2141: printf ("\twhile (%cmask) {\n", reg);
2142: if (apdi)
2143: printf ("\t\tsrca -= %d;\n", size);
2144: if (put) {
2145: printf ("\t\t%s, m68k_%creg (regs, %s[%cmask]));\n", code, reg, index, reg);
2146: } else {
2147: printf ("\t\tm68k_%creg (regs, %s[%cmask]) = %s;\n", reg, index, reg, code);
2148: }
2149: if (!apdi)
2150: printf ("\t\tsrca += %d;\n", size);
2151: printf ("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
2152: printf ("\t}\n");
2153: }
2154: if (aipi || apdi)
2155: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
2156: printf ("\tmmu040_movem = 0;\n");
1.1.1.4 root 2157: }
2158:
2159: /* 68030 MMU does not restore register state if it bus faults.
2160: * (also there wouldn't be enough space in stack frame to store all registers)
2161: */
2162: static void movem_mmu030 (const char *code, int size, bool put, bool aipi, bool apdi)
2163: {
1.1.1.5 root 2164: const char *index;
2165: int dphase;
2166: int i;
2167: if (apdi) {
2168: dphase = 1;
2169: index = "movem_index2";
2170: } else {
2171: dphase = 0;
2172: index = "movem_index1";
2173: }
2174: printf ("\tmmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;\n");
2175: printf ("\tint movem_cnt = 0;\n");
2176: if (!put) {
2177: printf ("\tuae_u32 val;\n");
2178: printf ("\tif (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)\n");
2179: printf ("\t\tsrca = mmu030_ad[mmu030_idx].val;\n");
2180: printf ("\telse\n");
2181: printf ("\t\tmmu030_ad[mmu030_idx].val = srca;\n");
2182: }
2183: for (i = 0; i < 2; i++) {
2184: char reg;
2185: if (i == dphase)
2186: reg = 'd';
2187: else
2188: reg = 'a';
2189: printf ("\twhile (%cmask) {\n", reg);
2190: if (apdi)
2191: printf ("\t\tsrca -= %d;\n", size);
2192: printf ("\t\tif (mmu030_state[0] == movem_cnt) {\n");
2193: printf ("\t\t\tif (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {\n");
2194: printf ("\t\t\t\tmmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;\n");
2195: if (!put)
2196: printf ("\t\t\t\tval = %smmu030_data_buffer;\n", size == 2 ? "(uae_s32)(uae_s16)" : "");
2197: printf ("\t\t\t} else {\n");
2198: if (put)
2199: printf ("\t\t\t\t%s, (mmu030_data_buffer = m68k_%creg (regs, %s[%cmask])));\n", code, reg, index, reg);
2200: else
2201: printf ("\t\t\t\tval = %s;\n", code);
2202: printf ("\t\t\t}\n");
2203: if (!put) {
2204: printf ("\t\t\tm68k_%creg (regs, %s[%cmask]) = val;\n", reg, index, reg);
2205: }
2206: printf ("\t\t\tmmu030_state[0]++;\n");
2207: printf ("\t\t}\n");
2208: if (!apdi)
2209: printf ("\t\tsrca += %d;\n", size);
2210: printf ("\t\tmovem_cnt++;\n");
2211: printf ("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
2212: printf ("\t}\n");
2213: }
2214: if (aipi || apdi)
2215: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1.1.1.4 root 2216: }
2217:
2218: static void genmovemel (uae_u16 opcode)
2219: {
1.1.1.5 root 2220: char getcode[100];
2221: int size = table68k[opcode].size == sz_long ? 4 : 2;
2222:
2223: if (table68k[opcode].size == sz_long) {
2224: sprintf (getcode, "%s (srca)", srcld);
2225: } else {
2226: sprintf (getcode, "(uae_s32)(uae_s16)%s (srca)", srcwd);
2227: }
2228: count_read += table68k[opcode].size == sz_long ? 2 : 1;
2229: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
2230: printf ("\tuae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
2231: genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? 3 : 1, GF_MOVE);
2232: addcycles_ce020 (8 - 2);
2233: start_brace ();
2234: if (using_mmu == 68030) {
2235: movem_mmu030 (getcode, size, false, table68k[opcode].dmode == Aipi, false);
2236: } else if (using_mmu == 68060) {
2237: movem_mmu060 (getcode, size, false, table68k[opcode].dmode == Aipi, false);
2238: } else if (using_mmu == 68040) {
2239: movem_mmu040 (getcode, size, false, table68k[opcode].dmode == Aipi, false, opcode);
2240: } else {
2241: printf ("\twhile (dmask) {\n");
2242: printf ("\t\tm68k_dreg (regs, movem_index1[dmask]) = %s; srca += %d; dmask = movem_next[dmask];\n", getcode, size);
2243: //addcycles_ce020 (1);
2244: printf ("\t}\n");
2245: printf ("\twhile (amask) {\n");
2246: printf ("\t\tm68k_areg (regs, movem_index1[amask]) = %s; srca += %d; amask = movem_next[amask];\n", getcode, size);
2247: //addcycles_ce020 (1);
2248: printf ("\t}\n");
2249: if (table68k[opcode].dmode == Aipi) {
2250: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
2251: count_read++;
2252: }
2253: }
2254: count_ncycles++;
2255: fill_prefetch_next ();
2256: get_prefetch_020 ();
1.1.1.4 root 2257: }
2258:
2259: static void genmovemel_ce (uae_u16 opcode)
2260: {
1.1.1.5 root 2261: int size = table68k[opcode].size == sz_long ? 4 : 2;
2262: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
2263: printf ("\tuae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
2264: printf ("\tuae_u32 v;\n");
2265: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
2266: addcycles000 (2);
2267: genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA | GF_MOVE);
2268: start_brace ();
2269: if (table68k[opcode].size == sz_long) {
2270: printf ("\twhile (dmask) {\n");
2271: printf ("\t\tv = %s (srca) << 16;\n", srcw);
2272: printf ("\t\tv |= %s (srca + 2);\n", srcw);
2273: printf ("\t\tm68k_dreg (regs, movem_index1[dmask]) = v;\n");
2274: printf ("\t\tsrca += %d;\n", size);
2275: printf ("\t\tdmask = movem_next[dmask];\n");
2276: addcycles000_nonce("\t\t", 8);
2277: printf ("\t}\n");
2278: printf ("\twhile (amask) {\n");
2279: printf ("\t\tv = %s (srca) << 16;\n", srcw);
2280: printf ("\t\tv |= %s (srca + 2);\n", srcw);
2281: printf ("\t\tm68k_areg (regs, movem_index1[amask]) = v;\n");
2282: printf ("\t\tsrca += %d;\n", size);
2283: printf ("\t\tamask = movem_next[amask];\n");
2284: addcycles000_nonce("\t\t", 8);
2285: printf ("\t}\n");
2286: } else {
2287: printf ("\twhile (dmask) {\n");
2288: printf ("\t\tm68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)%s (srca);\n", srcw);
2289: printf ("\t\tsrca += %d;\n", size);
2290: printf ("\t\tdmask = movem_next[dmask];\n");
2291: addcycles000_nonce("\t\t", 4);
2292: printf ("\t}\n");
2293: printf ("\twhile (amask) {\n");
2294: printf ("\t\tm68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)%s (srca);\n", srcw);
2295: printf ("\t\tsrca += %d;\n", size);
2296: printf ("\t\tamask = movem_next[amask];\n");
2297: addcycles000_nonce("\t\t", 4);
2298: printf ("\t}\n");
2299: }
2300: printf ("\t%s (srca);\n", srcw); // and final extra word fetch that goes nowhere..
2301: count_read++;
2302: if (table68k[opcode].dmode == Aipi)
2303: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
2304: count_ncycles++;
2305: fill_prefetch_next ();
1.1.1.4 root 2306: }
2307:
2308: static void genmovemle (uae_u16 opcode)
2309: {
1.1.1.5 root 2310: char putcode[100];
2311: int size = table68k[opcode].size == sz_long ? 4 : 2;
2312:
2313: if (table68k[opcode].size == sz_long) {
2314: sprintf (putcode, "%s (srca", dstld);
2315: } else {
2316: sprintf (putcode, "%s (srca", dstwd);
2317: }
2318: count_write += table68k[opcode].size == sz_long ? 2 : 1;
2319:
2320: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
2321: genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? 3 : 1, GF_MOVE);
2322: addcycles_ce020 (4 - 2);
2323: start_brace ();
2324: if (using_mmu >= 68030) {
2325: if (table68k[opcode].dmode == Apdi)
2326: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
2327: else
2328: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
2329: if (using_mmu == 68030)
2330: movem_mmu030 (putcode, size, true, false, table68k[opcode].dmode == Apdi);
2331: else if (using_mmu == 68060)
2332: movem_mmu060 (putcode, size, true, false, table68k[opcode].dmode == Apdi);
2333: else if (using_mmu == 68040)
2334: movem_mmu040 (putcode, size, true, false, table68k[opcode].dmode == Apdi, opcode);
2335: } else {
2336: if (table68k[opcode].dmode == Apdi) {
2337: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
2338: if (!using_mmu)
2339: printf ("\tint type = get_cpu_model () >= 68020;\n");
2340: printf ("\twhile (amask) {\n");
2341: printf ("\t\tsrca -= %d;\n", size);
2342:
2343: printf ("\t\tif (!type || movem_index2[amask] != dstreg)\n");
2344: printf ("\t\t\t%s, m68k_areg (regs, movem_index2[amask]));\n", putcode);
2345: printf ("\t\telse\n");
2346: printf ("\t\t\t%s, m68k_areg (regs, movem_index2[amask]) - %d);\n", putcode, size);
2347:
2348: printf ("\t\tamask = movem_next[amask];\n");
2349: printf ("\t}\n");
2350: printf ("\twhile (dmask) { srca -= %d; %s, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }\n",
2351: size, putcode);
2352: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
2353: } else {
2354: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
2355: printf ("\twhile (dmask) { %s, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
2356: putcode, size);
2357: printf ("\twhile (amask) { %s, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; }\n",
2358: putcode, size);
2359: }
2360: }
2361: count_ncycles++;
2362: fill_prefetch_next ();
2363: get_prefetch_020 ();
1.1.1.4 root 2364: }
2365:
2366: static void genmovemle_ce (uae_u16 opcode)
2367: {
1.1.1.5 root 2368: int size = table68k[opcode].size == sz_long ? 4 : 2;
2369:
2370: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
2371: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
2372: addcycles000 (2);
1.1.1.6 ! root 2373: genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA | GF_MOVE | GF_REVERSE | GF_REVERSE2);
1.1.1.5 root 2374: start_brace ();
2375: if (table68k[opcode].size == sz_long) {
2376: if (table68k[opcode].dmode == Apdi) {
2377: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
2378: printf ("\twhile (amask) {\n");
1.1.1.6 ! root 2379: printf ("\t\t%s (srca - 2, m68k_areg (regs, movem_index2[amask]));\n", dstw);
! 2380: printf ("\t\t%s (srca - 4, m68k_areg (regs, movem_index2[amask]) >> 16);\n", dstw);
1.1.1.5 root 2381: printf ("\t\tsrca -= %d;\n", size);
2382: printf ("\t\tamask = movem_next[amask];\n");
2383: addcycles000_nonce("\t\t", 8);
2384: printf ("\t}\n");
2385: printf ("\twhile (dmask) {\n");
1.1.1.6 ! root 2386: printf ("\t\t%s (srca - 2, m68k_dreg (regs, movem_index2[dmask]));\n", dstw);
! 2387: printf ("\t\t%s (srca - 4, m68k_dreg (regs, movem_index2[dmask]) >> 16);\n", dstw);
1.1.1.5 root 2388: printf ("\t\tsrca -= %d;\n", size);
2389: printf ("\t\tdmask = movem_next[dmask];\n");
2390: addcycles000_nonce("\t\t", 8);
2391: printf ("\t}\n");
2392: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
2393: } else {
2394: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
2395: printf ("\twhile (dmask) {\n");
2396: printf ("\t\t%s (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);\n", dstw);
2397: printf ("\t\t%s (srca + 2, m68k_dreg (regs, movem_index1[dmask]));\n", dstw);
2398: printf ("\t\tsrca += %d;\n", size);
2399: printf ("\t\tdmask = movem_next[dmask];\n");
2400: addcycles000_nonce("\t\t", 8);
2401: printf ("\t}\n");
2402: printf ("\twhile (amask) {\n");
2403: printf ("\t\t%s (srca, m68k_areg (regs, movem_index1[amask]) >> 16);\n", dstw);
2404: printf ("\t\t%s (srca + 2, m68k_areg (regs, movem_index1[amask]));\n", dstw);
2405: printf ("\t\tsrca += %d;\n", size);
2406: printf ("\t\tamask = movem_next[amask];\n");
2407: addcycles000_nonce("\t\t", 8);
2408: printf ("\t}\n");
2409: }
2410: } else {
2411: if (table68k[opcode].dmode == Apdi) {
2412: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
2413: printf ("\twhile (amask) {\n");
2414: printf ("\t\tsrca -= %d;\n", size);
2415: printf ("\t\t%s (srca, m68k_areg (regs, movem_index2[amask]));\n", dstw);
2416: printf ("\tamask = movem_next[amask];\n");
2417: addcycles000_nonce("\t\t", 4);
2418: printf ("\t}\n");
2419: printf ("\twhile (dmask) {\n");
2420: printf ("\t\tsrca -= %d;\n", size);
2421: printf ("\t\t%s (srca, m68k_dreg (regs, movem_index2[dmask]));\n", dstw);
2422: printf ("\t\tdmask = movem_next[dmask];\n");
2423: addcycles000_nonce("\t\t", 4);
2424: printf ("\t}\n");
2425: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
2426: } else {
2427: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
2428: printf ("\twhile (dmask) {\n");
2429: printf ("\t\t%s (srca, m68k_dreg (regs, movem_index1[dmask]));\n", dstw);
2430: printf ("\t\tsrca += %d;\n", size);
2431: printf ("\t\tdmask = movem_next[dmask];\n");
2432: addcycles000_nonce("\t\t", 4);
2433: printf ("\t}\n");
2434: printf ("\twhile (amask) {\n");
2435: printf ("\t\t%s (srca, m68k_areg (regs, movem_index1[amask]));\n", dstw);
2436: printf ("\t\tsrca += %d;\n", size);
2437: printf ("\t\tamask = movem_next[amask];\n");
2438: addcycles000_nonce("\t\t", 4);
2439: printf ("\t}\n");
2440: }
2441: }
2442: count_ncycles++;
2443: fill_prefetch_next ();
1.1.1.4 root 2444: }
2445:
2446: static void duplicate_carry (int n)
2447: {
1.1.1.5 root 2448: int i;
2449: for (i = 0; i <= n; i++)
2450: printf ("\t");
2451: printf ("COPY_CARRY ();\n");
1.1.1.4 root 2452: }
2453:
2454: typedef enum
2455: {
1.1.1.5 root 2456: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_z, flag_zn,
2457: flag_av, flag_sv
1.1.1.4 root 2458: }
2459: flagtypes;
2460:
1.1.1.5 root 2461: static void genflags_normal (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
1.1.1.4 root 2462: {
1.1.1.5 root 2463: char vstr[100], sstr[100], dstr[100];
2464: char usstr[100], udstr[100];
2465: char unsstr[100], undstr[100];
2466:
2467: switch (size) {
2468: case sz_byte:
2469: strcpy (vstr, "((uae_s8)(");
2470: strcpy (usstr, "((uae_u8)(");
2471: break;
2472: case sz_word:
2473: strcpy (vstr, "((uae_s16)(");
2474: strcpy (usstr, "((uae_u16)(");
2475: break;
2476: case sz_long:
2477: strcpy (vstr, "((uae_s32)(");
2478: strcpy (usstr, "((uae_u32)(");
2479: break;
2480: default:
2481: term ();
2482: }
2483: strcpy (unsstr, usstr);
2484:
2485: strcpy (sstr, vstr);
2486: strcpy (dstr, vstr);
2487: strcat (vstr, value);
2488: strcat (vstr, "))");
2489: strcat (dstr, dst);
2490: strcat (dstr, "))");
2491: strcat (sstr, src);
2492: strcat (sstr, "))");
2493:
2494: strcpy (udstr, usstr);
2495: strcat (udstr, dst);
2496: strcat (udstr, "))");
2497: strcat (usstr, src);
2498: strcat (usstr, "))");
2499:
2500: strcpy (undstr, unsstr);
2501: strcat (unsstr, "-");
2502: strcat (undstr, "~");
2503: strcat (undstr, dst);
2504: strcat (undstr, "))");
2505: strcat (unsstr, src);
2506: strcat (unsstr, "))");
2507:
2508: switch (type) {
2509: case flag_logical_noclobber:
2510: case flag_logical:
2511: case flag_z:
2512: case flag_zn:
2513: case flag_av:
2514: case flag_sv:
2515: case flag_addx:
2516: case flag_subx:
2517: break;
2518:
2519: case flag_add:
2520: start_brace ();
2521: printf ("uae_u32 %s = %s + %s;\n", value, udstr, usstr);
2522: break;
2523: case flag_sub:
2524: case flag_cmp:
2525: start_brace ();
2526: printf ("uae_u32 %s = %s - %s;\n", value, udstr, usstr);
2527: break;
2528: }
2529:
2530: switch ((int)type) {
2531: case flag_logical_noclobber:
2532: case flag_logical:
2533: case flag_zn:
2534: break;
2535:
2536: case flag_add:
2537: case flag_sub:
2538: case flag_addx:
2539: case flag_subx:
2540: case flag_cmp:
2541: case flag_av:
2542: case flag_sv:
2543: start_brace ();
2544: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
2545: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
2546: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
2547: break;
2548: }
2549:
2550: switch (type) {
2551: case flag_logical:
2552: printf ("\tCLEAR_CZNV ();\n");
2553: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
2554: printf ("\tSET_NFLG (%s < 0);\n", vstr);
2555: break;
2556: case flag_logical_noclobber:
2557: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
2558: printf ("\tSET_NFLG (%s < 0);\n", vstr);
2559: break;
2560: case flag_av:
2561: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
2562: break;
2563: case flag_sv:
2564: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
2565: break;
2566: case flag_z:
2567: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
2568: break;
2569: case flag_zn:
2570: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
2571: printf ("\tSET_NFLG (%s < 0);\n", vstr);
2572: break;
2573: case flag_add:
2574: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
2575: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
2576: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
2577: duplicate_carry (0);
2578: printf ("\tSET_NFLG (flgn != 0);\n");
2579: break;
2580: case flag_sub:
2581: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
2582: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
2583: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
2584: duplicate_carry (0);
2585: printf ("\tSET_NFLG (flgn != 0);\n");
2586: break;
2587: case flag_addx:
2588: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
2589: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
2590: duplicate_carry (0);
2591: break;
2592: case flag_subx:
2593: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
2594: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
2595: duplicate_carry (0);
2596: break;
2597: case flag_cmp:
2598: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
2599: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
2600: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
2601: printf ("\tSET_NFLG (flgn != 0);\n");
2602: break;
2603: }
2604: }
2605:
2606: static void genflags (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
2607: {
2608: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
2609: them in the appropriate m68k.h files and use just one copy of this
2610: code here. The API can be changed if necessary. */
2611: if (optimized_flags) {
2612: switch (type) {
2613: case flag_add:
2614: case flag_sub:
2615: start_brace ();
2616: printf ("\tuae_u32 %s;\n", value);
2617: break;
2618:
2619: default:
2620: break;
2621: }
2622:
2623: /* At least some of those casts are fairly important! */
2624: switch (type) {
2625: case flag_logical_noclobber:
2626: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
2627: if (strcmp (value, "0") == 0) {
2628: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
2629: } else {
2630: switch ((int)size) {
2631: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
2632: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
2633: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
2634: }
2635: printf ("\tIOR_CZNV (oldcznv);\n");
2636: }
2637: printf ("\t}\n");
2638: return;
2639: case flag_logical:
2640: if (strcmp (value, "0") == 0) {
2641: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
2642: } else {
2643: switch ((int)size) {
2644: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
2645: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
2646: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
2647: }
2648: }
2649: return;
2650:
2651: case flag_add:
2652: switch ((int)size) {
2653: case sz_byte: printf ("\toptflag_addb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
2654: case sz_word: printf ("\toptflag_addw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
2655: case sz_long: printf ("\toptflag_addl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
2656: }
2657: return;
2658:
2659: case flag_sub:
2660: switch ((int)size) {
2661: case sz_byte: printf ("\toptflag_subb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
2662: case sz_word: printf ("\toptflag_subw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
2663: case sz_long: printf ("\toptflag_subl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
2664: }
2665: return;
2666:
2667: case flag_cmp:
2668: switch ((int)size) {
2669: case sz_byte: printf ("\toptflag_cmpb (regs, (uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
2670: case sz_word: printf ("\toptflag_cmpw (regs, (uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
2671: case sz_long: printf ("\toptflag_cmpl (regs, (uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
2672: }
2673: return;
2674:
2675: default:
2676: break;
2677: }
2678: }
2679:
2680: genflags_normal (type, size, value, src, dst);
1.1.1.4 root 2681: }
2682:
2683: static void force_range_for_rox (const char *var, wordsizes size)
2684: {
1.1.1.5 root 2685: /* Could do a modulo operation here... which one is faster? */
2686: switch ((int)size) {
2687: case sz_long:
2688: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
2689: break;
2690: case sz_word:
2691: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
2692: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
2693: break;
2694: case sz_byte:
2695: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
2696: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
2697: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
2698: break;
2699: }
1.1.1.4 root 2700: }
2701:
2702: static const char *cmask (wordsizes size)
2703: {
1.1.1.5 root 2704: switch (size) {
2705: case sz_byte: return "0x80";
2706: case sz_word: return "0x8000";
2707: case sz_long: return "0x80000000";
2708: default: term (); return 0;
2709: }
1.1.1.4 root 2710: }
2711:
2712: static int source_is_imm1_8 (struct instr *i)
2713: {
1.1.1.5 root 2714: return i->stype == 3;
1.1.1.4 root 2715: }
2716:
2717: static void shift_ce (amodes dmode, int size)
2718: {
1.1.1.5 root 2719: if (isreg (dmode)) {
2720: int c = size == sz_long ? 4 : 2;
2721: if (using_ce) {
2722: printf ("\t{\n");
2723: printf ("\t\tint cycles = %d;\n", c);
2724: printf ("\t\tcycles += 2 * ccnt;\n");
2725: addcycles000_3 ("\t\t");
2726: printf ("\t}\n");
2727: }
2728: addcycles000_nonces("\t", "2 * ccnt");
2729: count_cycles += c;
2730: count_ncycles++;
2731: }
1.1.1.4 root 2732: }
2733:
1.1.1.5 root 2734: // BCHG/BSET/BCLR Dx,Dx or #xx,Dx adds 2 cycles if bit number > 15
1.1.1.4 root 2735: static void bsetcycles (struct instr *curi)
2736: {
1.1.1.5 root 2737: if (curi->size == sz_byte) {
2738: printf ("\tsrc &= 7;\n");
2739: } else {
2740: printf ("\tsrc &= 31;\n");
2741: if (isreg (curi->dmode)) {
2742: addcycles000 (2);
2743: if (curi->mnemo != i_BTST) {
2744: if (using_ce)
2745: printf ("\tif (src > 15) %s (2);\n", do_cycles);
2746: addcycles000_nonce("\tif (src > 15) ", 2);
2747: count_ncycles++;
2748: }
2749: }
2750: }
1.1.1.4 root 2751: }
2752:
2753: static int islongimm (struct instr *curi)
2754: {
1.1.1.5 root 2755: return (curi->size == sz_long && (curi->smode == Dreg || curi->smode == imm || curi->smode == Areg));
1.1.1.4 root 2756: }
2757:
2758:
2759: static void resetvars (void)
2760: {
1.1.1.5 root 2761: insn_n_cycles = using_prefetch ? 0 : 4;
2762: insn_n_cycles020 = 0;
2763: genamode_cnt = 0;
2764: genamode8r_offset[0] = genamode8r_offset[1] = 0;
2765: m68k_pc_total = 0;
2766: branch_inst = 0;
2767:
2768: ir2irc = 0;
2769: mmufixupcnt = 0;
2770: mmufixupstate = 0;
2771: disp020cnt = 0;
2772: candormw = false;
2773: genastore_done = false;
2774: rmw_varname[0] = 0;
2775: tail_ce020 = 0;
2776: total_ce020 = 0;
2777: tail_ce020_done = false;
2778: head_in_ea_ce020 = 0;
2779: head_ce020_cycs_done = false;
2780: no_prefetch_ce020 = false;
2781: got_ea_ce020 = false;
2782:
2783: prefetch_long = NULL;
1.1.1.6 ! root 2784: prefetch_opcode = NULL;
1.1.1.5 root 2785: srcli = NULL;
2786: srcbi = NULL;
2787: disp000 = "get_disp_ea_000";
2788: disp020 = "get_disp_ea_020";
2789: nextw = NULL;
2790: nextl = NULL;
2791: do_cycles = "do_cycles";
2792: srcwd = srcld = NULL;
2793: dstwd = dstld = NULL;
2794: srcblrmw = NULL;
2795: srcwlrmw = NULL;
2796: srcllrmw = NULL;
2797: dstblrmw = NULL;
2798: dstwlrmw = NULL;
2799: dstllrmw = NULL;
2800: getpc = "m68k_getpc ()";
2801:
2802: if (using_indirect > 0) {
2803: // tracer
2804: getpc = "m68k_getpci ()";
1.1.1.6 ! root 2805: if (using_mmu == 68030) {
! 2806: // 68030 cache MMU / CE cache MMU
! 2807: disp020 = "get_disp_ea_020_mmu030c";
! 2808: prefetch_long = "get_ilong_mmu030c_state";
! 2809: prefetch_word = "get_iword_mmu030c_state";
! 2810: prefetch_opcode = "get_iword_mmu030c_opcode_state";
! 2811: nextw = "next_iword_mmu030c_state";
! 2812: nextl = "next_ilong_mmu030c_state";
! 2813: srcli = "get_ilong_mmu030c_state";
! 2814: srcwi = "get_iword_mmu030c_state";
! 2815: srcbi = "get_ibyte_mmu030c_state";
! 2816: srcl = "get_long_mmu030c_state";
! 2817: dstl = "put_long_mmu030c_state";
! 2818: srcw = "get_word_mmu030c_state";
! 2819: dstw = "put_word_mmu030c_state";
! 2820: srcb = "get_byte_mmu030c_state";
! 2821: dstb = "put_byte_mmu030c_state";
! 2822: srcblrmw = "get_lrmw_byte_mmu030c_state";
! 2823: srcwlrmw = "get_lrmw_word_mmu030c_state";
! 2824: srcllrmw = "get_lrmw_long_mmu030c_state";
! 2825: dstblrmw = "put_lrmw_byte_mmu030c_state";
! 2826: dstwlrmw = "put_lrmw_word_mmu030c_state";
! 2827: dstllrmw = "put_lrmw_long_mmu030c_state";
! 2828: srcld = "get_long_mmu030c";
! 2829: srcwd = "get_word_mmu030c";
! 2830: dstld = "put_long_mmu030c";
! 2831: dstwd = "put_word_mmu030c";
! 2832: getpc = "m68k_getpci ()";
! 2833: } else if (!using_ce020 && !using_prefetch_020 && !using_ce) {
1.1.1.5 root 2834: // generic + indirect
2835: disp020 = "x_get_disp_ea_020";
2836: prefetch_long = "get_iilong_jit";
2837: prefetch_word = "get_iiword_jit";
2838: nextw = "next_iiword_jit";
2839: nextl = "next_iilong_jit";
2840: srcli = "get_iilong_jit";
2841: srcwi = "get_iiword_jit";
2842: srcbi = "get_iibyte_jit";
2843: srcl = "x_get_long";
2844: dstl = "x_put_long";
2845: srcw = "x_get_word";
2846: dstw = "x_put_word";
2847: srcb = "x_get_byte";
2848: dstb = "x_put_byte";
2849: getpc = "m68k_getpc()"; // special jit support
2850: } else if (!using_ce020 && !using_prefetch_020) {
2851: prefetch_word = "get_word_ce000_prefetch";
2852: srcli = "x_get_ilong";
2853: srcwi = "x_get_iword";
2854: srcbi = "x_get_ibyte";
2855: srcl = "x_get_long";
2856: dstl = "x_put_long";
2857: srcw = "x_get_word";
2858: dstw = "x_put_word";
2859: srcb = "x_get_byte";
2860: dstb = "x_put_byte";
2861: do_cycles = "do_cycles_ce000_internal";
2862: } else if (using_ce020 == 1) {
2863: /* x_ not used if it redirects to
2864: * get_word_ce020_prefetch()
2865: */
2866: disp020 = "x_get_disp_ea_ce020";
2867: prefetch_word = "get_word_ce020_prefetch";
2868: prefetch_long = "get_long_ce020_prefetch";
1.1.1.6 ! root 2869: prefetch_opcode = "get_word_ce020_prefetch_opcode";
1.1.1.5 root 2870: srcli = "x_get_ilong";
2871: srcwi = "x_get_iword";
2872: srcbi = "x_get_ibyte";
2873: srcl = "x_get_long";
2874: dstl = "x_put_long";
2875: srcw = "x_get_word";
2876: dstw = "x_put_word";
2877: srcb = "x_get_byte";
2878: dstb = "x_put_byte";
2879: do_cycles = "do_cycles_ce020_internal";
2880: nextw = "next_iword_020ce";
2881: nextl = "next_ilong_020ce";
2882: } else if (using_ce020 == 2) {
2883: // 68030 CE
2884: disp020 = "x_get_disp_ea_ce030";
2885: prefetch_long = "get_long_ce030_prefetch";
2886: prefetch_word = "get_word_ce030_prefetch";
1.1.1.6 ! root 2887: prefetch_opcode = "get_word_ce030_prefetch_opcode";
1.1.1.5 root 2888: srcli = "x_get_ilong";
2889: srcwi = "x_get_iword";
2890: srcbi = "x_get_ibyte";
2891: srcl = "x_get_long";
2892: dstl = "x_put_long";
2893: srcw = "x_get_word";
2894: dstw = "x_put_word";
2895: srcb = "x_get_byte";
2896: dstb = "x_put_byte";
2897: do_cycles = "do_cycles_ce020_internal";
2898: nextw = "next_iword_030ce";
2899: nextl = "next_ilong_030ce";
2900: } else if (using_ce020 == 3) {
2901: // 68040/060 CE
2902: disp020 = "x_get_disp_ea_040";
2903: prefetch_long = "get_ilong_cache_040";
2904: prefetch_word = "get_iword_cache_040";
2905: srcli = "x_get_ilong";
2906: srcwi = "x_get_iword";
2907: srcbi = "x_get_ibyte";
2908: srcl = "x_get_long";
2909: dstl = "x_put_long";
2910: srcw = "x_get_word";
2911: dstw = "x_put_word";
2912: srcb = "x_get_byte";
2913: dstb = "x_put_byte";
2914: do_cycles = "do_cycles_ce020_internal";
2915: nextw = "next_iword_cache040";
2916: nextl = "next_ilong_cache040";
2917: } else if (using_prefetch_020 == 1) {
2918: disp020 = "x_get_disp_ea_020";
2919: prefetch_word = "get_word_020_prefetch";
2920: prefetch_long = "get_long_020_prefetch";
2921: srcli = "x_get_ilong";
2922: srcwi = "x_get_iword";
2923: srcbi = "x_get_ibyte";
2924: srcl = "x_get_long";
2925: dstl = "x_put_long";
2926: srcw = "x_get_word";
2927: dstw = "x_put_word";
2928: srcb = "x_get_byte";
2929: dstb = "x_put_byte";
2930: nextw = "next_iword_020_prefetch";
2931: nextl = "next_ilong_020_prefetch";
2932: } else if (using_prefetch_020 == 2) {
2933: disp020 = "x_get_disp_ea_020";
2934: prefetch_word = "get_word_030_prefetch";
2935: prefetch_long = "get_long_030_prefetch";
2936: srcli = "x_get_ilong";
2937: srcwi = "x_get_iword";
2938: srcbi = "x_get_ibyte";
2939: srcl = "x_get_long";
2940: dstl = "x_put_long";
2941: srcw = "x_get_word";
2942: dstw = "x_put_word";
2943: srcb = "x_get_byte";
2944: dstb = "x_put_byte";
2945: nextw = "next_iword_030_prefetch";
2946: nextl = "next_ilong_030_prefetch";
2947: }
1.1.1.4 root 2948: #if 0
1.1.1.5 root 2949: } else if (using_ce020) {
2950: disp020 = "x_get_disp_ea_020";
2951: do_cycles = "do_cycles_ce020";
2952: if (using_ce020 == 2) {
2953: // 68030/40/60 CE
2954: prefetch_long = "get_long_ce030_prefetch";
2955: prefetch_word = "get_word_ce030_prefetch";
2956: nextw = "next_iword_030ce";
2957: nextl = "next_ilong_030ce";
2958: srcli = "get_word_ce030_prefetch";
2959: srcwi = "get_long_ce030_prefetch";
2960: srcl = "get_long_ce030";
2961: dstl = "put_long_ce030";
2962: srcw = "get_word_ce030";
2963: dstw = "put_word_ce030";
2964: srcb = "get_byte_ce030";
2965: dstb = "put_byte_ce030";
2966: } else {
2967: // 68020 CE
2968: prefetch_long = "get_long_ce020_prefetch";
2969: prefetch_word = "get_word_ce020_prefetch";
2970: nextw = "next_iword_020ce";
2971: nextl = "next_ilong_020ce";
2972: srcli = "get_word_ce020_prefetch";
2973: srcwi = "get_long_ce020_prefetch";
2974: srcl = "get_long_ce020";
2975: dstl = "put_long_ce020";
2976: srcw = "get_word_ce020";
2977: dstw = "put_word_ce020";
2978: srcb = "get_byte_ce020";
2979: dstb = "put_byte_ce020";
2980: }
2981: #endif
2982: } else if (using_mmu == 68030) {
2983: // 68030 MMU
2984: disp020 = "get_disp_ea_020_mmu030";
2985: prefetch_long = "get_ilong_mmu030_state";
2986: prefetch_word = "get_iword_mmu030_state";
2987: nextw = "next_iword_mmu030_state";
2988: nextl = "next_ilong_mmu030_state";
2989: srcli = "get_ilong_mmu030_state";
2990: srcwi = "get_iword_mmu030_state";
2991: srcbi = "get_ibyte_mmu030_state";
2992: srcl = "get_long_mmu030_state";
2993: dstl = "put_long_mmu030_state";
2994: srcw = "get_word_mmu030_state";
2995: dstw = "put_word_mmu030_state";
2996: srcb = "get_byte_mmu030_state";
2997: dstb = "put_byte_mmu030_state";
2998: srcblrmw = "get_lrmw_byte_mmu030_state";
2999: srcwlrmw = "get_lrmw_word_mmu030_state";
3000: srcllrmw = "get_lrmw_long_mmu030_state";
3001: dstblrmw = "put_lrmw_byte_mmu030_state";
3002: dstwlrmw = "put_lrmw_word_mmu030_state";
3003: dstllrmw = "put_lrmw_long_mmu030_state";
3004: srcld = "get_long_mmu030";
3005: srcwd = "get_word_mmu030";
3006: dstld = "put_long_mmu030";
3007: dstwd = "put_word_mmu030";
3008: getpc = "m68k_getpci ()";
3009: } else if (using_mmu == 68040) {
3010: // 68040 MMU
3011: disp020 = "x_get_disp_ea_020";
3012: prefetch_long = "get_ilong_mmu040";
3013: prefetch_word = "get_iword_mmu040";
3014: nextw = "next_iword_mmu040";
3015: nextl = "next_ilong_mmu040";
3016: srcli = "get_ilong_mmu040";
3017: srcwi = "get_iword_mmu040";
3018: srcbi = "get_ibyte_mmu040";
3019: srcl = "get_long_mmu040";
3020: dstl = "put_long_mmu040";
3021: srcw = "get_word_mmu040";
3022: dstw = "put_word_mmu040";
3023: srcb = "get_byte_mmu040";
3024: dstb = "put_byte_mmu040";
3025: srcblrmw = "get_lrmw_byte_mmu040";
3026: srcwlrmw = "get_lrmw_word_mmu040";
3027: srcllrmw = "get_lrmw_long_mmu040";
3028: dstblrmw = "put_lrmw_byte_mmu040";
3029: dstwlrmw = "put_lrmw_word_mmu040";
3030: dstllrmw = "put_lrmw_long_mmu040";
3031: getpc = "m68k_getpci ()";
3032: } else if (using_mmu) {
3033: // 68060 MMU
3034: disp020 = "x_get_disp_ea_020";
3035: prefetch_long = "get_ilong_mmu060";
3036: prefetch_word = "get_iword_mmu060";
3037: nextw = "next_iword_mmu060";
3038: nextl = "next_ilong_mmu060";
3039: srcli = "get_ilong_mmu060";
3040: srcwi = "get_iword_mmu060";
3041: srcbi = "get_ibyte_mmu060";
3042: srcl = "get_long_mmu060";
3043: dstl = "put_long_mmu060";
3044: srcw = "get_word_mmu060";
3045: dstw = "put_word_mmu060";
3046: srcb = "get_byte_mmu060";
3047: dstb = "put_byte_mmu060";
3048: srcblrmw = "get_lrmw_byte_mmu060";
3049: srcwlrmw = "get_lrmw_word_mmu060";
3050: srcllrmw = "get_lrmw_long_mmu060";
3051: dstblrmw = "put_lrmw_byte_mmu060";
3052: dstwlrmw = "put_lrmw_word_mmu060";
3053: dstllrmw = "put_lrmw_long_mmu060";
3054: // 68060 only: also non-locked read-modify-write accesses are reported
3055: srcbrmw = "get_rmw_byte_mmu060";
3056: srcwrmw = "get_rmw_word_mmu060";
3057: srclrmw = "get_rmw_long_mmu060";
3058: dstbrmw = "put_rmw_byte_mmu060";
3059: dstwrmw = "put_rmw_word_mmu060";
3060: dstlrmw = "put_rmw_long_mmu060";
3061: getpc = "m68k_getpci ()";
3062: } else if (using_ce) {
3063: // 68000 ce
3064: prefetch_word = "get_word_ce000_prefetch";
3065: srcwi = "get_wordi_ce000";
3066: srcl = "get_long_ce000";
3067: dstl = "put_long_ce000";
3068: srcw = "get_word_ce000";
3069: dstw = "put_word_ce000";
3070: srcb = "get_byte_ce000";
3071: dstb = "put_byte_ce000";
3072: do_cycles = "do_cycles_ce000";
3073: getpc = "m68k_getpci ()";
3074: } else if (using_prefetch) {
3075: // 68000 prefetch
3076: prefetch_word = "get_word_000_prefetch";
3077: prefetch_long = "get_long_000_prefetch";
3078: srcwi = "get_wordi_000";
3079: srcl = "get_long_000";
3080: dstl = "put_long_000";
3081: srcw = "get_word_000";
3082: dstw = "put_word_000";
3083: srcb = "get_byte_000";
3084: dstb = "put_byte_000";
3085: getpc = "m68k_getpci ()";
3086: } else {
3087: // generic + direct
3088: prefetch_long = "get_dilong";
3089: prefetch_word = "get_diword";
3090: nextw = "next_diword";
3091: nextl = "next_dilong";
3092: srcli = "get_dilong";
3093: srcwi = "get_diword";
3094: srcbi = "get_dibyte";
3095: if (using_indirect < 0) {
3096: srcl = "get_long_jit";
3097: dstl = "put_long_jit";
3098: srcw = "get_word_jit";
3099: dstw = "put_word_jit";
3100: srcb = "get_byte_jit";
3101: dstb = "put_byte_jit";
3102: } else {
3103: srcl = "get_long";
3104: dstl = "put_long";
3105: srcw = "get_word";
3106: dstw = "put_word";
3107: srcb = "get_byte";
3108: dstb = "put_byte";
3109: }
3110: }
3111: if (!dstld)
3112: dstld = dstl;
3113: if (!dstwd)
3114: dstwd = dstw;
3115: if (!srcld)
3116: srcld = srcl;
3117: if (!srcwd)
3118: srcwd = srcw;
3119: if (!srcblrmw) {
3120: srcblrmw = srcb;
3121: srcwlrmw = srcw;
3122: srcllrmw = srcl;
3123: dstblrmw = dstb;
3124: dstwlrmw = dstw;
3125: dstllrmw = dstl;
3126: }
1.1.1.6 ! root 3127: if (!prefetch_opcode)
! 3128: prefetch_opcode = prefetch_word;
1.1.1.5 root 3129:
3130: }
3131:
3132: static void gen_opcode (unsigned int opcode)
3133: {
3134: current_opcode = opcode;
3135: struct instr *curi = table68k + opcode;
3136:
3137: resetvars ();
3138:
3139: start_brace ();
3140:
3141: m68k_pc_offset = 2;
3142:
3143: // do not unnecessarily create useless mmuop030
3144: // functions when CPU is not 68030
3145: if (curi->mnemo == i_MMUOP030 && cpu_level != 3 && !cpu_generic) {
3146: printf("\top_illg (opcode);\n");
3147: did_prefetch = -1;
3148: goto end;
3149: }
3150:
3151: switch (curi->plev) {
3152: case 0: /* not privileged */
3153: break;
3154: case 1: /* unprivileged only on 68000 */
3155: if (cpu_level == 0)
3156: break;
3157: if (next_cpu_level < 0)
3158: next_cpu_level = 0;
3159:
3160: /* fall through */
3161: case 2: /* priviledged */
3162: printf ("if (!regs.s) { Exception (8); goto %s; }\n", endlabelstr);
3163: need_endlabel = 1;
3164: start_brace ();
3165: break;
3166: case 3: /* privileged if size == word */
3167: if (curi->size == sz_byte)
3168: break;
3169: printf ("if (!regs.s) { Exception (8); goto %s; }\n", endlabelstr);
3170: need_endlabel = 1;
3171: start_brace ();
3172: break;
3173: }
3174: switch (curi->mnemo) {
3175: case i_OR:
3176: case i_AND:
3177: case i_EOR:
3178: {
3179: // documentaion error: and.l #imm,dn = 2 idle, not 1 idle (same as OR and EOR)
3180: int c = 0;
3181: genamodedual (curi,
3182: curi->smode, "srcreg", curi->size, "src", 1, 0,
3183: curi->dmode, "dstreg", curi->size, "dst", 1, GF_RMW);
3184: // genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3185: // genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_RMW);
3186: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
3187: genflags (flag_logical, curi->size, "src", "", "");
3188: if (curi->dmode == Dreg && curi->size == sz_long) {
3189: c += 2;
3190: if (curi->smode == imm || curi->smode == Dreg)
3191: c += 2;
3192: }
3193: fill_prefetch_next ();
3194: if (c > 0)
3195: addcycles000 (c);
3196: genastore_rev ("src", curi->dmode, "dstreg", curi->size, "dst");
3197: break;
3198: }
3199: // all SR/CCR modifications does full prefetch
3200: case i_ORSR:
3201: case i_EORSR:
3202: printf ("\tMakeSR ();\n");
3203: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3204: if (curi->size == sz_byte) {
3205: printf ("\tsrc &= 0xFF;\n");
3206: }
3207: addcycles000 (8);
3208: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
1.1.1.6 ! root 3209: makefromsr_t0();
! 3210: sync_m68k_pc ();
! 3211: fill_prefetch_full_ntx();
1.1.1.5 root 3212: break;
3213: case i_ANDSR:
3214: printf ("\tMakeSR ();\n");
3215: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3216: if (curi->size == sz_byte) {
3217: printf ("\tsrc |= 0xFF00;\n");
3218: }
3219: addcycles000 (8);
3220: printf ("\tregs.sr &= src;\n");
1.1.1.6 ! root 3221: makefromsr_t0();
! 3222: sync_m68k_pc ();
! 3223: fill_prefetch_full_ntx();
1.1.1.5 root 3224: break;
3225: case i_SUB:
3226: {
3227: int c = 0;
3228: genamodedual (curi,
3229: curi->smode, "srcreg", curi->size, "src", 1, 0,
3230: curi->dmode, "dstreg", curi->size, "dst", 1, GF_RMW);
3231: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3232: //genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_RMW);
3233: if (curi->dmode == Dreg) {
3234: if (curi->size == sz_long) {
3235: c += 2;
3236: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg || curi->smode == Areg)
3237: c += 2;
3238: }
3239: }
3240: fill_prefetch_next ();
3241: if (c > 0)
3242: addcycles000 (c);
3243: start_brace ();
3244: genflags (flag_sub, curi->size, "newv", "src", "dst");
3245: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
3246: break;
3247: }
3248: case i_SUBA:
3249: {
3250: int c = 0;
3251: genamodedual (curi,
3252: curi->smode, "srcreg", curi->size, "src", 1, 0,
3253: curi->dmode, "dstreg", sz_long, "dst", 1, GF_RMW);
3254: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3255: //genamode (curi, curi->dmode, "dstreg", sz_long, "dst", 1, 0, GF_RMW);
3256: if (curi->smode == immi) {
3257: // SUBAQ.x is always 8 cycles
3258: c += 4;
3259: } else {
3260: c = curi->size == sz_long ? 2 : 4;
3261: if (islongimm (curi))
3262: c += 2;
3263: }
3264: fill_prefetch_next ();
3265: if (c > 0)
3266: addcycles000 (c);
3267: start_brace ();
3268: printf ("\tuae_u32 newv = dst - src;\n");
3269: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
3270: break;
3271: }
3272: case i_SUBX:
3273: if (!isreg (curi->smode))
3274: addcycles000 (2);
1.1.1.6 ! root 3275: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_REVERSE);
! 3276: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_REVERSE | GF_RMW);
1.1.1.5 root 3277: fill_prefetch_next ();
3278: if (curi->size == sz_long && isreg (curi->smode))
3279: addcycles000 (4);
3280: start_brace ();
3281: printf ("\tuae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);\n");
3282: genflags (flag_subx, curi->size, "newv", "src", "dst");
3283: genflags (flag_zn, curi->size, "newv", "", "");
3284: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
3285: break;
3286: case i_SBCD:
3287: if (!isreg (curi->smode))
3288: addcycles000 (2);
3289: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
3290: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_RMW);
3291: fill_prefetch_next ();
3292: start_brace ();
3293: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
3294: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
3295: printf ("\tuae_u16 newv, tmp_newv;\n");
3296: printf ("\tint bcd = 0;\n");
3297: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
3298: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
3299: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
3300: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);\n");
3301: duplicate_carry (0);
1.1.1.6 ! root 3302: /* Manual says bits NV are undefined though a real 68030 doesn't change V and 68040/060 don't change both */
! 3303: if (cpu_level >= xBCD_KEEPS_N_FLAG) {
! 3304: if (next_cpu_level < xBCD_KEEPS_N_FLAG)
! 3305: next_cpu_level = xBCD_KEEPS_N_FLAG - 1;
1.1.1.5 root 3306: genflags (flag_z, curi->size, "newv", "", "");
3307: } else {
3308: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.6 ! root 3309: }
! 3310: if (cpu_level >= xBCD_KEEPS_V_FLAG) {
! 3311: if (next_cpu_level < xBCD_KEEPS_V_FLAG)
! 3312: next_cpu_level = xBCD_KEEPS_V_FLAG - 1;
! 3313: } else {
1.1.1.5 root 3314: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
3315: }
3316: if (isreg (curi->smode)) {
3317: addcycles000 (2);
3318: }
3319: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
3320: break;
3321: case i_ADD:
3322: {
3323: int c = 0;
3324: genamodedual (curi,
3325: curi->smode, "srcreg", curi->size, "src", 1, 0,
3326: curi->dmode, "dstreg", curi->size, "dst", 1, GF_RMW);
3327: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3328: //genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_RMW);
3329: if (curi->dmode == Dreg) {
3330: if (curi->size == sz_long) {
3331: c += 2;
3332: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg || curi->smode == Areg)
3333: c += 2;
3334: }
3335: }
3336: fill_prefetch_next ();
3337: if (c > 0)
3338: addcycles000 (c);
3339: start_brace ();
3340: genflags (flag_add, curi->size, "newv", "src", "dst");
3341: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
3342: break;
3343: }
3344: case i_ADDA:
3345: {
3346: int c = 0;
3347: genamodedual (curi,
3348: curi->smode, "srcreg", curi->size, "src", 1, 0,
3349: curi->dmode, "dstreg", sz_long, "dst", 1, GF_RMW);
3350: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3351: //genamode (curi, curi->dmode, "dstreg", sz_long, "dst", 1, 0, GF_RMW);
3352: if (curi->smode == immi) {
3353: // ADDAQ.x is always 8 cycles
3354: c += 4;
3355: } else {
3356: c = curi->size == sz_long ? 2 : 4;
3357: if (islongimm (curi))
3358: c += 2;
3359: }
3360: fill_prefetch_next ();
3361: if (c > 0)
3362: addcycles000 (c);
3363: start_brace ();
3364: printf ("\tuae_u32 newv = dst + src;\n");
3365: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
3366: break;
3367: }
3368: case i_ADDX:
3369: if (!isreg (curi->smode))
3370: addcycles000 (2);
1.1.1.6 ! root 3371: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_REVERSE);
! 3372: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_REVERSE | GF_RMW);
1.1.1.5 root 3373: fill_prefetch_next ();
3374: if (curi->size == sz_long && isreg (curi->smode))
3375: addcycles000 (4);
3376: start_brace ();
3377: printf ("\tuae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);\n");
3378: genflags (flag_addx, curi->size, "newv", "src", "dst");
3379: genflags (flag_zn, curi->size, "newv", "", "");
3380: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
3381: break;
3382: case i_ABCD:
3383: if (!isreg (curi->smode))
3384: addcycles000 (2);
3385: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
3386: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_RMW);
3387: fill_prefetch_next ();
3388: start_brace ();
3389: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);\n");
3390: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
3391: printf ("\tuae_u16 newv, tmp_newv;\n");
3392: printf ("\tint cflg;\n");
3393: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
3394: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
3395: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
3396: printf ("\tif (cflg) newv += 0x60;\n");
3397: printf ("\tSET_CFLG (cflg);\n");
3398: duplicate_carry (0);
1.1.1.6 ! root 3399: /* Manual says bits NV are undefined though a real 68030 doesn't change V and 68040/060 don't change both */
! 3400: if (cpu_level >= xBCD_KEEPS_N_FLAG) {
! 3401: if (next_cpu_level < xBCD_KEEPS_N_FLAG)
! 3402: next_cpu_level = xBCD_KEEPS_N_FLAG - 1;
1.1.1.5 root 3403: genflags (flag_z, curi->size, "newv", "", "");
1.1.1.6 ! root 3404: } else {
1.1.1.5 root 3405: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.6 ! root 3406: }
! 3407: if (cpu_level >= xBCD_KEEPS_V_FLAG) {
! 3408: if (next_cpu_level < xBCD_KEEPS_V_FLAG)
! 3409: next_cpu_level = xBCD_KEEPS_V_FLAG - 1;
! 3410: } else {
1.1.1.5 root 3411: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
3412: }
3413: if (isreg (curi->smode)) {
3414: addcycles000 (2);
3415: }
3416: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
3417: break;
3418: case i_NEG:
3419: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
3420: fill_prefetch_next ();
3421: if (isreg (curi->smode) && curi->size == sz_long)
3422: addcycles000 (2);
3423: start_brace ();
3424: genflags (flag_sub, curi->size, "dst", "src", "0");
3425: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
3426: break;
3427: case i_NEGX:
3428: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
3429: fill_prefetch_next ();
3430: if (isreg (curi->smode) && curi->size == sz_long)
3431: addcycles000 (2);
3432: start_brace ();
3433: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);\n");
3434: genflags (flag_subx, curi->size, "newv", "src", "0");
3435: genflags (flag_zn, curi->size, "newv", "", "");
3436: genastore_rev ("newv", curi->smode, "srcreg", curi->size, "src");
3437: break;
3438: case i_NBCD:
3439: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
3440: if (isreg (curi->smode))
3441: addcycles000 (2);
3442: fill_prefetch_next ();
3443: start_brace ();
3444: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
3445: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
3446: printf ("\tuae_u16 newv;\n");
3447: printf ("\tint cflg, tmp_newv;\n");
1.1.1.6 ! root 3448: printf ("\ttmp_newv = newv_hi + newv_lo;\n");
1.1.1.5 root 3449: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1.1.1.6 ! root 3450: printf ("\tnewv = newv_hi + newv_lo;\n");
1.1.1.5 root 3451: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
3452: printf ("\tif (cflg) newv -= 0x60;\n");
3453: printf ("\tSET_CFLG (cflg);\n");
3454: duplicate_carry(0);
1.1.1.6 ! root 3455: /* Manual says bits NV are undefined though a real 68030 doesn't change V and 68040/060 don't change both */
! 3456: if (cpu_level >= xBCD_KEEPS_N_FLAG) {
! 3457: if (next_cpu_level < xBCD_KEEPS_N_FLAG)
! 3458: next_cpu_level = xBCD_KEEPS_N_FLAG - 1;
1.1.1.5 root 3459: genflags (flag_z, curi->size, "newv", "", "");
1.1.1.6 ! root 3460: } else {
1.1.1.5 root 3461: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.6 ! root 3462: }
! 3463: if (cpu_level >= xBCD_KEEPS_V_FLAG) {
! 3464: if (next_cpu_level < xBCD_KEEPS_V_FLAG)
! 3465: next_cpu_level = xBCD_KEEPS_V_FLAG - 1;
! 3466: } else {
1.1.1.5 root 3467: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
3468: }
3469: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
3470: break;
3471: case i_CLR:
3472: next_level_000 ();
3473: genamode (curi, curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
3474: fill_prefetch_next ();
3475: if (isreg (curi->smode) && curi->size == sz_long)
3476: addcycles000 (2);
3477: genflags (flag_logical, curi->size, "0", "", "");
3478: genastore_rev ("0", curi->smode, "srcreg", curi->size, "src");
3479: break;
3480: case i_NOT:
3481: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
3482: fill_prefetch_next ();
3483: if (isreg (curi->smode) && curi->size == sz_long)
3484: addcycles000 (2);
3485: start_brace ();
3486: printf ("\tuae_u32 dst = ~src;\n");
3487: genflags (flag_logical, curi->size, "dst", "", "");
3488: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
3489: break;
3490: case i_TST:
3491: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3492: fill_prefetch_next ();
3493: genflags (flag_logical, curi->size, "src", "", "");
3494: break;
3495: case i_BTST:
3496: genamodedual (curi,
3497: curi->smode, "srcreg", curi->size, "src", 1, 0,
3498: curi->dmode, "dstreg", curi->size, "dst", 1, 0);
3499: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3500: //genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_IR2IRC);
3501: fill_prefetch_next ();
3502: bsetcycles (curi);
3503: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
3504: break;
3505: case i_BCHG:
3506: case i_BCLR:
3507: case i_BSET:
3508: // on 68000 these have weird side-effect, if EA points to write-only custom register
3509: //during instruction's read access CPU data lines appear as zero to outside world,
3510: // (normally previously fetched data appears in data lines if reading write-only register)
3511: // this allows stupid things like bset #2,$dff096 to work "correctly"
3512: // NOTE: above can't be right.
3513: genamodedual (curi,
3514: curi->smode, "srcreg", curi->size, "src", 1, 0,
3515: curi->dmode, "dstreg", curi->size, "dst", 1, GF_RMW);
3516: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3517: //genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_IR2IRC | GF_RMW);
3518: fill_prefetch_next ();
3519: bsetcycles (curi);
3520: // bclr needs 1 extra cycle
3521: if (curi->mnemo == i_BCLR && curi->dmode == Dreg)
3522: addcycles000 (2);
3523: if (curi->mnemo == i_BCHG) {
3524: printf ("\tdst ^= (1 << src);\n");
3525: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
3526: } else if (curi->mnemo == i_BCLR) {
3527: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
3528: printf ("\tdst &= ~(1 << src);\n");
3529: } else if (curi->mnemo == i_BSET) {
3530: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
3531: printf ("\tdst |= (1 << src);\n");
3532: }
3533: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
3534: break;
3535: case i_CMPM:
3536: // confirmed
3537: genamodedual (curi,
3538: curi->smode, "srcreg", curi->size, "src", 1, GF_AA,
3539: curi->dmode, "dstreg", curi->size, "dst", 1, GF_AA);
3540: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
3541: //genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
3542: fill_prefetch_next ();
3543: start_brace ();
3544: genflags (flag_cmp, curi->size, "newv", "src", "dst");
3545: break;
3546: case i_CMP:
3547: genamodedual (curi,
3548: curi->smode, "srcreg", curi->size, "src", 1, 0,
3549: curi->dmode, "dstreg", curi->size, "dst", 1, 0);
3550: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3551: //genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3552: fill_prefetch_next ();
3553: if (curi->dmode == Dreg && curi->size == sz_long)
3554: addcycles000 (2);
3555: start_brace ();
3556: genflags (flag_cmp, curi->size, "newv", "src", "dst");
3557: break;
3558: case i_CMPA:
3559: genamodedual (curi,
3560: curi->smode, "srcreg", curi->size, "src", 1, 0,
3561: curi->dmode, "dstreg", sz_long, "dst", 1, 0);
3562: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3563: //genamode (curi, curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
3564: fill_prefetch_next ();
3565: addcycles000 (2);
3566: start_brace ();
3567: genflags (flag_cmp, sz_long, "newv", "src", "dst");
3568: break;
3569: /* The next two are coded a little unconventional, but they are doing
3570: * weird things... */
3571: case i_MVPRM: // MOVEP R->M
3572: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3573: printf ("\tuaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
3574: if (curi->size == sz_word) {
3575: printf ("\t%s (memp, src >> 8);\n\t%s (memp + 2, src);\n", dstb, dstb);
3576: count_write += 2;
3577: } else {
3578: printf ("\t%s (memp, src >> 24);\n\t%s (memp + 2, src >> 16);\n", dstb, dstb);
3579: printf ("\t%s (memp + 4, src >> 8);\n\t%s (memp + 6, src);\n", dstb, dstb);
3580: count_write += 4;
3581: }
3582: fill_prefetch_next ();
3583: break;
3584: case i_MVPMR: // MOVEP M->R
3585: printf ("\tuaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
3586: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
3587: if (curi->size == sz_word) {
3588: printf ("\tuae_u16 val = (%s (memp) & 0xff) << 8;\n", srcb);
3589: printf ("\t val |= (%s (memp + 2) & 0xff);\n", srcb);
3590: count_read += 2;
3591: } else {
3592: printf ("\tuae_u32 val = (%s (memp) & 0xff) << 24;\n", srcb);
3593: printf ("\t val |= (%s (memp + 2) & 0xff) << 16;\n", srcb);
3594: printf ("\t val |= (%s (memp + 4) & 0xff) << 8;\n", srcb);
3595: printf ("\t val |= (%s (memp + 6) & 0xff);\n", srcb);
3596: count_read += 4;
3597: }
3598: fill_prefetch_next ();
3599: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
3600: break;
3601: case i_MOVE:
3602: case i_MOVEA:
3603: {
3604: /* 2 MOVE instruction variants have special prefetch sequence:
3605: * - MOVE <ea>,-(An) = prefetch is before writes (Apdi)
3606: * - MOVE memory,(xxx).L = 2 prefetches after write
3607: * - move.x #imm = prefetch is done before write
3608: * - all others = prefetch is done after writes
3609: *
3610: * - move.x xxx,[at least 1 extension word here] = fetch 1 extension word before (xxx)
3611: *
3612: */
3613: if (isce020()) {
3614: // MOVE is too complex to handle in table68k
3615: int h = 0, t = 0, c = 0, subhead = 0;
3616: bool fea = false;
3617: if (curi->smode == immi && isreg (curi->dmode)) {
3618: // MOVEQ
3619: h = 2; t = 0; c = 0;
3620: } else if (isreg (curi->smode) && isreg (curi->dmode)) {
3621: // MOVE Rn,Rn
3622: h = 2; t = 0; c = 2;
3623: } else if (isreg (curi->dmode)) {
3624: // MOVE EA,Rn
3625: h = 0; t = 0; c = 2;
3626: fea = true;
3627: } else if (curi->dmode == Aind) {
3628: if (isreg (curi->smode)) {
3629: // MOVE Rn,(An)
3630: h = 0; t = 1; c = 3;
3631: } else {
3632: // MOVE SOURCE,(An)
3633: h = 2; t = 0; c = 4;
3634: fea = true;
3635: }
3636: } else if (curi->dmode == Aipi) {
3637: if (isreg (curi->smode)) {
3638: // MOVE Rn,(An)+
3639: h = 0; t = 1; c = 3;
3640: } else {
3641: // MOVE SOURCE,(An)+
3642: h = 2; t = 0; c = 4;
3643: fea = true;
3644: }
3645: } else if (curi->dmode == Apdi) {
3646: if (isreg (curi->smode)) {
3647: // MOVE Rn,-(An)
3648: h = 0; t = 2; c = 4;
3649: } else {
3650: // MOVE SOURCE,-(An)
3651: h = 2; t = 0; c = 4;
3652: fea = true;
3653: }
3654: } else if (curi->dmode == Ad16) {
3655: // MOVE EA,(d16,An)
3656: h = 2; t = 0; c = 4;
3657: fea = true;
3658: } else if (curi->dmode == Ad8r) {
3659: h = 4; t = 0; c = 6;
3660: fea = true;
3661: } else if (curi->dmode == absw) {
3662: // MOVE EA,xxx.W
3663: h = 2; t = 0; c = 4;
3664: fea = true;
3665: } else if (curi->dmode == absl) {
3666: // MOVE EA,xxx.L
3667: h = 0; t = 0; c = 6;
3668: fea = true;
3669: } else {
3670: h = 4; t = 0; c = 6;
3671: fea = true;
3672: }
3673: if (fea) {
3674: if (curi->smode == imm)
3675: subhead = gence020cycles_fiea (curi, curi->size, Dreg);
3676: else
3677: subhead = gence020cycles_fea (curi->smode);
3678: }
3679: genamode2x (curi->smode, "srcreg", curi->size, "src", 1, 0, 0, fea ? fetchmode_fea : -1);
3680: genamode2 (curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_MOVE);
3681: addopcycles_ce20 (h, t, c, -subhead);
3682: if (curi->mnemo == i_MOVEA && curi->size == sz_word)
3683: printf ("\tsrc = (uae_s32)(uae_s16)src;\n");
3684: if (curi->mnemo == i_MOVE)
3685: genflags (flag_logical, curi->size, "src", "", "");
3686: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
3687: sync_m68k_pc ();
3688:
3689: } else {
3690: int prefetch_done = 0, flags;
3691: int dualprefetch = curi->dmode == absl && (curi->smode != Dreg && curi->smode != Areg && curi->smode != imm);
3692: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3693: flags = GF_MOVE | GF_APDI;
3694: //if (curi->size == sz_long && (curi->smode == Dreg || curi->smode == Areg))
3695: // flags &= ~GF_APDI;
3696: flags |= dualprefetch ? GF_NOREFILL : 0;
1.1.1.6 ! root 3697: if (curi->dmode == Apdi && curi->size == sz_long)
! 3698: flags |= GF_REVERSE;
1.1.1.5 root 3699: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, flags);
3700: if (curi->mnemo == i_MOVEA && curi->size == sz_word)
3701: printf ("\tsrc = (uae_s32)(uae_s16)src;\n");
3702: if (curi->dmode == Apdi) {
3703: fill_prefetch_next ();
3704: prefetch_done = 1;
3705: }
3706: if (curi->mnemo == i_MOVE)
3707: genflags (flag_logical, curi->size, "src", "", "");
3708:
3709: if (curi->size == sz_long) {
3710: if ((curi->dmode == Ad16 || curi->dmode == PC16) && curi->smode == imm) {
3711: // lots more needed..
3712: // move.l x,absl
3713: // move.l (an),x(an)
3714: single_check_ipl();
3715: }
3716: }
1.1.1.6 ! root 3717: // MOVE EA,-(An) long writes are always reversed. Reads are normal.
! 3718: if (curi->dmode == Apdi && curi->size == sz_long) {
! 3719: genastore_rev("src", curi->dmode, "dstreg", curi->size, "dst");
! 3720: } else {
1.1.1.5 root 3721: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.6 ! root 3722: }
1.1.1.5 root 3723: sync_m68k_pc ();
3724: if (dualprefetch) {
3725: fill_prefetch_full_000 ();
3726: prefetch_done = 1;
3727: }
3728: if (!prefetch_done)
3729: fill_prefetch_next ();
3730: }
3731: }
3732: break;
3733: case i_MVSR2: // MOVE FROM SR
3734: genamode (curi, curi->smode, "srcreg", sz_word, "src", 2, 0, 0);
3735: if (isreg (curi->smode)) {
3736: fill_prefetch_next ();
3737: addcycles000 (2);
3738: } else {
3739: // write to memory, dummy write to same address, X-flag seems to be always set
3740: if (cpu_level <= 1 && curi->size == sz_word) {
3741: printf ("\t%s (srca, regs.sr | 0x0010);\n", dstw);
3742: count_write++;
3743: }
3744: fill_prefetch_next ();
3745: }
3746: printf ("\tMakeSR ();\n");
3747: // real write
3748: if (curi->size == sz_byte)
3749: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
3750: else
3751: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
3752: break;
3753: case i_MV2SR: // MOVE TO SR
3754: genamode (curi, curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
3755: if (curi->size == sz_byte) {
3756: // MOVE TO CCR
3757: addcycles000 (4);
3758: printf ("\tMakeSR ();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
3759: } else {
3760: // MOVE TO SR
3761: addcycles000 (4);
3762: printf ("\tregs.sr = src;\n");
3763: }
1.1.1.6 ! root 3764: makefromsr_t0();
! 3765: // does full prefetch because S-bit change may change memory mapping under the CPU
! 3766: sync_m68k_pc ();
! 3767: fill_prefetch_full_ntx();
1.1.1.5 root 3768: break;
3769: case i_SWAP:
3770: genamode (curi, curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
3771: fill_prefetch_next ();
3772: start_brace ();
3773: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
3774: genflags (flag_logical, sz_long, "dst", "", "");
3775: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
3776: break;
3777: case i_EXG:
3778: // confirmed
3779: genamodedual (curi,
3780: curi->smode, "srcreg", curi->size, "src", 1, 0,
3781: curi->dmode, "dstreg", curi->size, "dst", 1, 0);
3782: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3783: //genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3784: fill_prefetch_next ();
3785: addcycles000 (2);
3786: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
3787: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
3788: break;
3789: case i_EXT:
3790: // confirmed
3791: genamode (curi, curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
3792: fill_prefetch_next ();
3793: start_brace ();
3794: switch (curi->size) {
3795: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
3796: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
3797: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
3798: default: term ();
3799: }
3800: genflags (flag_logical,
3801: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
3802: genastore ("dst", curi->smode, "srcreg",
3803: curi->size == sz_word ? sz_word : sz_long, "src");
3804: break;
3805: case i_MVMEL:
3806: // confirmed
3807: if (using_ce || using_prefetch)
3808: genmovemel_ce (opcode);
3809: else
3810: genmovemel (opcode);
3811: tail_ce020_done = true;
3812: break;
3813: case i_MVMLE:
3814: // confirmed
3815: if (using_ce || using_prefetch)
3816: genmovemle_ce (opcode);
3817: else
3818: genmovemle (opcode);
3819: tail_ce020_done = true;
3820: break;
3821: case i_TRAP:
3822: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3823: gen_set_fault_pc ();
3824: sync_m68k_pc ();
1.1.1.6 ! root 3825: printf ("\tException_cpu(src + 32);\n");
1.1.1.5 root 3826: did_prefetch = 1;
3827: clear_m68k_offset();
3828: break;
3829: case i_MVR2USP:
3830: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3831: fill_prefetch_next ();
3832: printf ("\tregs.usp = src;\n");
3833: break;
3834: case i_MVUSP2R:
3835: genamode (curi, curi->smode, "srcreg", curi->size, "src", 2, 0, 0);
3836: fill_prefetch_next ();
3837: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
3838: break;
3839: case i_RESET:
3840: fill_prefetch_next ();
3841: printf ("\tcpureset ();\n");
3842: sync_m68k_pc ();
3843: addcycles000 (128);
3844: if (using_prefetch) {
3845: printf ("\t%s (2);\n", prefetch_word);
3846: clear_m68k_offset();
3847: }
3848: break;
3849: case i_NOP:
3850: fill_prefetch_next ();
3851: break;
3852: case i_STOP:
1.1.1.6 ! root 3853: next_level_000();
1.1.1.5 root 3854: if (using_prefetch) {
1.1.1.6 ! root 3855: printf("\tuae_u16 sr = regs.irc;\n");
1.1.1.5 root 3856: m68k_pc_offset += 2;
3857: } else {
3858: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1.1.1.6 ! root 3859: printf("\tuae_u16 sr = src;\n");
! 3860: }
! 3861: // STOP undocumented features:
! 3862: // if SR is not set:
! 3863: // 68000 (68010?): Update SR, increase PC and then cause privilege violation exception (handled in newcpu)
! 3864: // 68000 (68010?): Traced STOP also runs 4 cycles faster.
! 3865: // 68020 68030: STOP works normally
! 3866: // 68040 68060: Immediate privilege violation exception
! 3867: if ((cpu_level == 0 || cpu_level == 1) && using_ce) {
! 3868: printf("\t%s(regs.t1 ? 4 : 8);\n", do_cycles);
1.1.1.5 root 3869: }
1.1.1.6 ! root 3870: if (cpu_level >= 4) {
! 3871: printf("\tif (!(sr & 0x2000)) {\n");
! 3872: incpc("%d", m68k_pc_offset);
! 3873: printf("\t\tException(8); goto %s;\n", endlabelstr);
! 3874: printf("\t}\n");
! 3875: }
! 3876: printf("\tregs.sr = sr;\n");
! 3877: makefromsr();
1.1.1.5 root 3878: printf ("\tm68k_setstopped ();\n");
3879: sync_m68k_pc ();
3880: // STOP does not prefetch anything
3881: did_prefetch = -1;
1.1.1.6 ! root 3882: next_cpu_level = cpu_level - 1;
1.1.1.5 root 3883: break;
3884: case i_LPSTOP: /* 68060 */
3885: printf ("\tuae_u16 sw = %s (2);\n", srcwi);
3886: printf ("\tif (sw != (0x100|0x80|0x40)) { Exception (4); goto %s; }\n", endlabelstr);
1.1.1.6 ! root 3887: printf("\tif (!(regs.sr & 0x2000)) {\n");
! 3888: printf("\t\tException(8); goto %s;\n", endlabelstr);
! 3889: printf("\t}\n");
! 3890: printf("\tregs.sr = %s (4);\n", srcwi);
! 3891: makefromsr();
1.1.1.5 root 3892: printf ("\tm68k_setstopped();\n");
3893: m68k_pc_offset += 4;
3894: sync_m68k_pc ();
1.1.1.6 ! root 3895: fill_prefetch_full_ntx();
1.1.1.5 root 3896: break;
3897: case i_RTE:
3898: addop_ce020 (curi, 0);
3899: next_level_000 ();
3900: if (cpu_level == 0) {
3901: genamode (NULL, Aipi, "7", sz_word, "sr", 1, 0, GF_NOREFILL);
3902: genamode (NULL, Aipi, "7", sz_long, "pc", 1, 0, GF_NOREFILL);
3903: printf ("\tregs.sr = sr;\n");
3904: printf ("\tif (pc & 1) {\n");
3905: printf ("\t\texception3i (0x%04X, pc);\n", opcode);
3906: printf ("\t\tgoto %s;\n", endlabelstr);
3907: printf ("\t}\n");
3908: setpc ("pc");
1.1.1.6 ! root 3909: makefromsr();
1.1.1.5 root 3910: } else if (cpu_level == 1 && using_prefetch) {
3911: int old_brace_level = n_braces;
3912: printf ("\tuae_u16 newsr; uae_u32 newpc;\n");
3913: printf ("\tfor (;;) {\n");
3914: printf ("\t\tuaecptr a = m68k_areg (regs, 7);\n");
3915: printf ("\t\tuae_u16 sr = %s (a);\n", srcw);
3916: count_read++;
3917: printf ("\t\tuae_u32 pc = %s (a + 2) << 16; pc |= %s (a + 4);\n", srcw, srcw);
3918: count_read += 2;
3919: printf ("\t\tuae_u16 format = %s (a + 2 + 4);\n", srcw);
3920: count_read++;
3921: printf ("\t\tint frame = format >> 12;\n");
3922: printf ("\t\tint offset = 8;\n");
3923: printf ("\t\tnewsr = sr; newpc = pc;\n");
3924: printf ("\t\tif (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }\n");
3925: printf ("\t\telse if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }\n");
1.1.1.6 ! root 3926: printf ("\t\telse { m68k_areg (regs, 7) += offset; Exception_cpu(14); goto %s; }\n", endlabelstr);
1.1.1.5 root 3927: printf ("\t\tregs.sr = newsr; MakeFromSR ();\n}\n");
3928: pop_braces (old_brace_level);
3929: printf ("\tregs.sr = newsr;\n");
1.1.1.6 ! root 3930: makefromsr();
1.1.1.5 root 3931: printf ("\tif (newpc & 1) {\n");
3932: printf ("\t\texception3i (0x%04X, newpc);\n", opcode);
3933: printf ("\t\tgoto %s;\n", endlabelstr);
3934: printf ("\t}\n");
3935: setpc ("newpc");
3936: check_ipl ();
3937: need_endlabel = 1;
3938: } else {
3939: int old_brace_level = n_braces;
3940: printf ("\tuae_u16 newsr; uae_u32 newpc;\n");
3941: printf ("\tfor (;;) {\n");
3942: printf ("\t\tuaecptr a = m68k_areg (regs, 7);\n");
3943: printf ("\t\tuae_u16 sr = %s (a);\n", srcw);
3944: count_read++;
3945: printf ("\t\tuae_u32 pc = %s (a + 2);\n", srcl);
3946: count_read += 2;
3947: printf ("\t\tuae_u16 format = %s (a + 2 + 4);\n", srcw);
3948: count_read++;
3949: printf ("\t\tint frame = format >> 12;\n");
3950: printf ("\t\tint offset = 8;\n");
3951: printf ("\t\tnewsr = sr; newpc = pc;\n");
3952: addcycles_ce020 (6);
3953: printf ("\t\tif (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }\n");
3954: printf ("\t\telse if (frame == 0x1) { m68k_areg (regs, 7) += offset; }\n");
3955: printf ("\t\telse if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }\n");
3956: if (cpu_level >= 4) {
3957: printf ("\t\telse if (frame == 0x3) { m68k_areg (regs, 7) += offset + 4; break; }\n");
3958: }
3959: if (using_mmu == 68060) {
3960: printf ("\t\telse if (frame == 0x4) { m68k_do_rte_mmu060 (a); m68k_areg (regs, 7) += offset + 8; break; }\n");
3961: } else if (cpu_level >= 4) {
3962: printf ("\t\telse if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }\n");
3963: }
3964: if (cpu_level == 1) // 68010 only
3965: printf ("\t\telse if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }\n");
3966: if (using_mmu == 68040) {
3967: printf ("\t\telse if (frame == 0x7) { m68k_do_rte_mmu040 (a); m68k_areg (regs, 7) += offset + 52; break; }\n");
3968: } else if (cpu_level >= 4) {
3969: printf ("\t\telse if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }\n");
3970: }
3971: if (cpu_level == 2 || cpu_level == 3) { // 68020/68030 only
3972: printf ("\t\telse if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }\n");
3973: if (using_mmu == 68030) {
1.1.1.6 ! root 3974: if (using_prefetch_020) {
! 3975: printf ("\t\telse if (frame == 0xa) { m68k_do_rte_mmu030c (a); break; }\n");
! 3976: printf ("\t\telse if (frame == 0xb) { m68k_do_rte_mmu030c (a); goto %s; }\n", endlabelstr);
! 3977: } else {
1.1.1.5 root 3978: printf ("\t\telse if (frame == 0xa) { m68k_do_rte_mmu030 (a); break; }\n");
3979: printf ("\t\telse if (frame == 0xb) { m68k_do_rte_mmu030 (a); break; }\n");
1.1.1.6 ! root 3980: }
1.1.1.5 root 3981: } else {
3982: printf ("\t\telse if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }\n");
3983: printf ("\t\telse if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }\n");
3984: }
3985: }
1.1.1.6 ! root 3986: printf ("\t\telse { m68k_areg (regs, 7) += offset; Exception_cpu(14); goto %s; }\n", endlabelstr);
1.1.1.5 root 3987: printf ("\t\tregs.sr = newsr;\n");
1.1.1.6 ! root 3988: makefromsr_t0();
1.1.1.5 root 3989: printf ("}\n");
3990: pop_braces (old_brace_level);
3991: printf ("\tregs.sr = newsr;\n");
3992: addcycles_ce020 (4);
1.1.1.6 ! root 3993: makefromsr_t0();
1.1.1.5 root 3994: printf ("\tif (newpc & 1) {\n");
3995: printf ("\t\texception3i (0x%04X, newpc);\n", opcode);
3996: printf ("\t\tgoto %s;\n", endlabelstr);
3997: printf ("\t}\n");
3998: setpc ("newpc");
3999: check_ipl ();
4000: need_endlabel = 1;
4001: }
4002: /* PC is set and prefetch filled. */
4003: clear_m68k_offset();
4004: tail_ce020_done = true;
1.1.1.6 ! root 4005: fill_prefetch_full_ntx();
1.1.1.5 root 4006: branch_inst = 1;
4007: next_cpu_level = cpu_level - 1;
4008: break;
4009: case i_RTD:
4010: addop_ce020 (curi, 0);
4011: if (using_mmu) {
4012: genamode (curi, curi->smode, "srcreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
4013: genamode (NULL, Aipi, "7", sz_long, "pc", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
4014: printf ("\tm68k_areg(regs, 7) += offs;\n");
4015: } else {
4016: genamode (NULL, Aipi, "7", sz_long, "pc", 1, 0, 0);
4017: genamode (curi, curi->smode, "srcreg", curi->size, "offs", 1, 0, 0);
4018: printf ("\tm68k_areg (regs, 7) += offs;\n");
4019: }
4020: printf ("\tif (pc & 1) {\n");
4021: printf ("\t\texception3i (0x%04X, pc);\n", opcode);
4022: printf ("\t\tgoto %s;\n", endlabelstr);
4023: printf ("\t}\n");
4024: setpc ("pc");
4025: /* PC is set and prefetch filled. */
4026: clear_m68k_offset();
4027: tail_ce020_done = true;
4028: fill_prefetch_full ();
4029: need_endlabel = 1;
4030: branch_inst = 1;
4031: break;
4032: case i_LINK:
4033: // ce confirmed
4034: if (using_mmu) {
4035: addmmufixup ("srcreg");
4036: genamode (NULL, curi->dmode, "dstreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
4037: genamode (NULL, Apdi, "7", sz_long, "old", GENA_GETV_FETCH_ALIGN, GENA_MOVEM_DO_INC, 0);
4038: genamode (NULL, curi->smode, "srcreg", sz_long, "src", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
4039: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
4040: printf ("\tm68k_areg(regs, 7) += offs;\n");
4041: genastore ("src", Apdi, "7", sz_long, "old");
4042: } else {
4043: addop_ce020 (curi, 0);
4044: genamode (NULL, Apdi, "7", sz_long, "old", 2, 0, GF_AA);
4045: genamode (NULL, curi->smode, "srcreg", sz_long, "src", 1, 0, GF_AA);
4046: genamode (NULL, curi->dmode, "dstreg", curi->size, "offs", 1, 0, 0);
4047: genastore ("src", Apdi, "7", sz_long, "old");
4048: genastore ("m68k_areg (regs, 7)", curi->smode, "srcreg", sz_long, "src");
4049: printf ("\tm68k_areg (regs, 7) += offs;\n");
4050: fill_prefetch_next ();
4051: }
4052: break;
4053: case i_UNLK:
4054: // ce confirmed
4055: if (using_mmu) {
4056: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
4057: printf ("\tuae_s32 old = %s (src);\n", srcl);
4058: printf ("\tm68k_areg (regs, 7) = src + 4;\n");
4059: printf ("\tm68k_areg (regs, srcreg) = old;\n");
4060: } else {
4061: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
4062: printf ("\tm68k_areg (regs, 7) = src;\n");
4063: genamode (NULL, Aipi, "7", sz_long, "old", 1, 0, 0);
4064: fill_prefetch_next ();
4065: genastore ("old", curi->smode, "srcreg", curi->size, "src");
4066: }
4067: break;
4068: case i_RTS:
4069: addop_ce020 (curi, 0);
4070: printf ("\tuaecptr pc = %s;\n", getpc);
4071: if (using_indirect > 0 && !using_ce020 && !using_prefetch_020 && !using_ce) {
4072: printf("\tm68k_do_rtsi_jit ();\n");
1.1.1.6 ! root 4073: } else if (using_mmu) {
! 4074: printf ("\tm68k_do_rts_mmu%s ();\n", mmu_postfix);
1.1.1.5 root 4075: } else if (using_ce020 == 1) {
4076: add_head_cycs (1);
4077: printf ("\tm68k_do_rts_ce020 ();\n");
4078: } else if (using_ce020 == 2) {
4079: add_head_cycs (1);
4080: printf ("\tm68k_do_rts_ce030 ();\n");
4081: } else if (using_ce) {
4082: printf ("\tm68k_do_rts_ce ();\n");
4083: } else if (using_prefetch || using_prefetch_020) {
4084: printf ("\tm68k_do_rtsi ();\n");
4085: } else {
4086: printf ("\tm68k_do_rts ();\n");
4087: }
4088: printf ("\tif (%s & 1) {\n", getpc);
4089: printf ("\t\tuaecptr faultpc = %s;\n", getpc);
4090: setpc ("pc");
4091: printf ("\t\texception3i (0x%04X, faultpc);\n", opcode);
4092: printf ("\t\tgoto %s;\n", endlabelstr);
4093: printf ("\t}\n");
4094: count_read += 2;
4095: clear_m68k_offset();
4096: fill_prefetch_full ();
4097: need_endlabel = 1;
4098: branch_inst = 1;
4099: break;
4100: case i_TRAPV:
4101: sync_m68k_pc ();
4102: fill_prefetch_next ();
4103: printf ("\tif (GET_VFLG ()) {\n");
1.1.1.6 ! root 4104: printf ("\t\tException_cpu(7);\n");
1.1.1.5 root 4105: printf ("\t\tgoto %s;\n", endlabelstr);
4106: printf ("\t}\n");
4107: need_endlabel = 1;
4108: break;
4109: case i_RTR:
4110: printf ("\tuaecptr oldpc = %s;\n", getpc);
4111: printf ("\tMakeSR ();\n");
4112: genamode (NULL, Aipi, "7", sz_word, "sr", 1, 0, 0);
4113: genamode (NULL, Aipi, "7", sz_long, "pc", 1, 0, 0);
4114: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
4115: printf ("\tregs.sr |= sr;\n");
4116: setpc ("pc");
1.1.1.6 ! root 4117: makefromsr();
1.1.1.5 root 4118: printf ("\tif (%s & 1) {\n", getpc);
4119: printf ("\t\tuaecptr faultpc = %s;\n", getpc);
4120: setpc ("oldpc");
4121: printf ("\t\texception3i (0x%04X, faultpc);\n", opcode);
4122: printf ("\t\tgoto %s;\n", endlabelstr);
4123: printf ("\t}\n");
4124: clear_m68k_offset();
4125: fill_prefetch_full ();
4126: need_endlabel = 1;
4127: branch_inst = 1;
4128: tail_ce020_done = true;
4129: break;
4130: case i_JSR:
4131: // possible idle cycle, prefetch from new address, stack high return addr, stack low, prefetch
4132: no_prefetch_ce020 = true;
4133: genamode (curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA|GF_NOREFILL);
4134: start_brace ();
4135: printf ("\tuaecptr oldpc = %s + %d;\n", getpc, m68k_pc_offset);
4136: if (using_exception_3) {
4137: printf ("\tif (srca & 1) {\n");
4138: printf ("\t\texception3i (opcode, srca);\n");
4139: printf ("\t\tgoto %s;\n", endlabelstr);
4140: printf ("\t}\n");
4141: need_endlabel = 1;
4142: }
4143: if (using_mmu) {
4144: printf ("\t%s (m68k_areg (regs, 7) - 4, oldpc);\n", dstl);
4145: printf ("\tm68k_areg (regs, 7) -= 4;\n");
4146: setpc ("srca");
4147: clear_m68k_offset();
4148: } else {
4149: if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16)
4150: addcycles000 (2);
4151: if (curi->smode == Ad8r || curi->smode == PC8r) {
4152: addcycles000 (6);
4153: if (cpu_level <= 1 && using_prefetch)
4154: printf ("\toldpc += 2;\n");
4155: }
4156: setpc ("srca");
4157: clear_m68k_offset();
4158: fill_prefetch_1 (0);
4159: printf ("\tm68k_areg (regs, 7) -= 4;\n");
4160: if (using_ce || using_prefetch) {
4161: printf ("\t%s (m68k_areg (regs, 7), oldpc >> 16);\n", dstw);
4162: printf ("\t%s (m68k_areg (regs, 7) + 2, oldpc);\n", dstw);
4163: } else {
4164: printf ("\t%s (m68k_areg (regs, 7), oldpc);\n", dstl);
4165: }
4166: }
4167: count_write += 2;
4168: fill_prefetch_full_020 ();
4169: fill_prefetch_next ();
4170: branch_inst = 1;
4171: break;
4172: case i_JMP:
4173: no_prefetch_ce020 = true;
4174: genamode (curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA|GF_NOREFILL);
4175: if (using_exception_3) {
4176: printf ("\tif (srca & 1) {\n");
4177: printf ("\t\texception3i (opcode, srca);\n");
4178: printf ("\t\tgoto %s;\n", endlabelstr);
4179: printf ("\t}\n");
4180: need_endlabel = 1;
4181: }
4182: if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16)
4183: addcycles000 (2);
1.1.1.6 ! root 4184: if (curi->smode == Ad8r || curi->smode == PC8r)
1.1.1.5 root 4185: addcycles000 (6);
4186: setpc ("srca");
4187: clear_m68k_offset();
4188: fill_prefetch_full ();
4189: branch_inst = 1;
4190: break;
4191: case i_BSR:
4192: // .b/.w = idle cycle, store high, store low, 2xprefetch
4193: if (isce020())
4194: no_prefetch_ce020 = true;
4195: printf ("\tuae_s32 s;\n");
4196: if (curi->size == sz_long) {
4197: if (next_cpu_level < 1)
4198: next_cpu_level = 1;
4199: }
4200: if (curi->size == sz_long && cpu_level < 2) {
4201: printf ("\tuae_u32 src = 0xffffffff;\n");
4202: } else {
4203: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA|GF_NOREFILL);
4204: }
4205: printf ("\ts = (uae_s32)src + 2;\n");
4206: if (using_exception_3) {
4207: printf ("\tif (src & 1) {\n");
4208: printf ("\t\texception3b (opcode, %s + s, 0, 1, %s + s);\n", getpc, getpc);
4209: printf ("\t\tgoto %s;\n", endlabelstr);
4210: printf ("\t}\n");
4211: need_endlabel = 1;
4212: }
4213: addcycles000 (2);
4214: if (using_indirect > 0 && !using_ce020 && !using_prefetch_020 && !using_ce) {
4215: printf("\tm68k_do_bsri_jit (%s + %d, s);\n", getpc, m68k_pc_offset);
1.1.1.6 ! root 4216: } else if (using_mmu) {
! 4217: printf ("\tm68k_do_bsr_mmu%s (%s + %d, s);\n", mmu_postfix, getpc, m68k_pc_offset);
1.1.1.5 root 4218: } else if (using_ce020 == 1) {
4219: printf ("\tm68k_do_bsr_ce020 (%s + %d, s);\n", getpc, m68k_pc_offset);
4220: } else if (using_ce020 == 2) {
4221: printf ("\tm68k_do_bsr_ce030 (%s + %d, s);\n", getpc, m68k_pc_offset);
4222: } else if (using_ce) {
4223: printf ("\tm68k_do_bsr_ce (%s + %d, s);\n", getpc, m68k_pc_offset);
4224: } else if (using_prefetch || using_prefetch_020) {
4225: printf ("\tm68k_do_bsri (%s + %d, s);\n", getpc, m68k_pc_offset);
4226: } else {
4227: printf ("\tm68k_do_bsr (%s + %d, s);\n", getpc, m68k_pc_offset);
4228: }
4229: count_write += 2;
4230: clear_m68k_offset();
4231: fill_prefetch_full ();
4232: branch_inst = 1;
4233: break;
4234: case i_Bcc:
4235: tail_ce020_done = true;
4236: if (curi->size == sz_long) {
4237: if (cpu_level < 2) {
4238: addcycles000 (2);
4239: printf ("\tif (cctrue (%d)) {\n", curi->cc);
4240: printf ("\t\texception3i (opcode, %s + 1);\n", getpc);
4241: printf ("\t\tgoto %s;\n", endlabelstr);
4242: printf ("\t}\n");
4243: sync_m68k_pc ();
4244: addcycles000 (2);
4245: irc2ir ();
4246: fill_prefetch_2 ();
4247: need_endlabel = 1;
4248: goto bccl_not68020;
4249: } else {
4250: if (next_cpu_level < 1)
4251: next_cpu_level = 1;
4252: }
4253: }
4254: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0));
4255: addcycles000 (2);
4256: printf ("\tif (!cctrue (%d)) goto didnt_jump;\n", curi->cc);
4257: if (using_exception_3) {
4258: printf ("\tif (src & 1) {\n");
4259: printf ("\t\texception3i (opcode, %s + 2 + (uae_s32)src);\n", getpc);
4260: printf ("\t\tgoto %s;\n", endlabelstr);
4261: printf ("\t}\n");
4262: need_endlabel = 1;
4263: }
4264: push_ins_cnt();
4265: if (using_prefetch) {
4266: incpc ("(uae_s32)src + 2");
4267: fill_prefetch_full_000 ();
4268: if (using_ce)
4269: printf ("\treturn;\n");
4270: else
4271: printf ("\treturn %d;\n", adjust_cycles(10));
4272: } else {
4273: incpc ("(uae_s32)src + 2");
4274: add_head_cycs (6);
4275: fill_prefetch_full_020 ();
4276: returncycles ("\t", 10);
4277: }
4278: pop_ins_cnt();
4279: printf ("didnt_jump:;\n");
4280: need_endlabel = 1;
4281: sync_m68k_pc ();
4282: addcycles000 (2);
4283: get_prefetch_020_continue ();
4284: if (curi->size == sz_byte) {
4285: irc2ir ();
4286: add_head_cycs (4);
4287: fill_prefetch_2 ();
4288: } else if (curi->size == sz_word) {
4289: add_head_cycs (6);
4290: fill_prefetch_full_000 ();
4291: } else {
4292: add_head_cycs (6);
4293: fill_prefetch_full_000 ();
4294: }
4295: insn_n_cycles = curi->size == sz_byte ? 8 : 12;
4296: branch_inst = 1;
4297: bccl_not68020:
4298: break;
4299: case i_LEA:
4300: if (curi->smode == Ad8r || curi->smode == PC8r)
4301: addcycles000 (2);
4302: genamodedual (curi,
4303: curi->smode, "srcreg", curi->size, "src", 0, GF_AA,
4304: curi->dmode, "dstreg", curi->size, "dst", 2, GF_AA);
4305: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
4306: //genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_AA);
1.1.1.6 ! root 4307: if (curi->smode == Ad8r || curi->smode == PC8r)
1.1.1.5 root 4308: addcycles000 (2);
4309: fill_prefetch_next ();
4310: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
4311: break;
4312: case i_PEA:
4313: if (curi->smode == Ad8r || curi->smode == PC8r)
4314: addcycles000 (2);
4315: genamode (curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
4316: genamode (NULL, Apdi, "7", sz_long, "dst", 2, 0, GF_AA);
4317: if (!(curi->smode == absw || curi->smode == absl))
4318: fill_prefetch_next ();
1.1.1.6 ! root 4319: if (curi->smode == Ad8r || curi->smode == PC8r)
1.1.1.5 root 4320: addcycles000 (2);
4321: genastore ("srca", Apdi, "7", sz_long, "dst");
4322: if ((curi->smode == absw || curi->smode == absl))
4323: fill_prefetch_next ();
4324: break;
4325: case i_DBcc:
4326: // cc true: idle cycle, prefetch
4327: // cc false, counter expired: idle cycle, prefetch (from branch address), 2xprefetch (from next address)
4328: // cc false, counter not expired: idle cycle, prefetch
4329: tail_ce020_done = true;
4330: genamodedual (curi,
4331: curi->smode, "srcreg", curi->size, "src", 1, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0),
4332: curi->dmode, "dstreg", curi->size, "offs", 1, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0));
4333: //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
4334: //genamode (curi, curi->dmode, "dstreg", curi->size, "offs", 1, 0, GF_AA | GF_NOREFILL);
4335: printf ("\tuaecptr oldpc = %s;\n", getpc);
4336: addcycles000 (2);
4337: push_ins_cnt();
4338: printf ("\tif (!cctrue (%d)) {\n", curi->cc);
4339: incpc ("(uae_s32)offs + 2");
4340: printf ("\t");
4341: fill_prefetch_1 (0);
4342: printf ("\t");
4343: genastore ("(src - 1)", curi->smode, "srcreg", curi->size, "src");
4344:
4345: printf ("\t\tif (src) {\n");
4346: if (using_exception_3) {
4347: printf ("\t\t\tif (offs & 1) {\n");
4348: printf ("\t\t\t\texception3i (opcode, %s + 2 + (uae_s32)offs + 2);\n", getpc);
4349: printf ("\t\t\t\tgoto %s;\n", endlabelstr);
4350: printf ("\t\t\t}\n");
4351: need_endlabel = 1;
4352: }
4353: irc2ir ();
4354: add_head_cycs (6);
4355: fill_prefetch_1 (2);
4356: fill_prefetch_full_020 ();
4357: returncycles ("\t\t\t", 10);
4358: printf ("\t\t}\n");
4359: add_head_cycs (10);
4360: addcycles000_nonce("\t\t", 2 + 2);
4361: printf ("\t} else {\n");
4362: addcycles000_onlyce(2);
4363: addcycles000_nonce("\t\t", 2);
4364: printf ("\t}\n");
4365: pop_ins_cnt();
4366: setpc ("oldpc + %d", m68k_pc_offset);
4367: clear_m68k_offset();
4368: get_prefetch_020_continue ();
4369: fill_prefetch_full_000 ();
4370: insn_n_cycles = 12;
4371: need_endlabel = 1;
4372: branch_inst = 1;
4373: break;
4374: case i_Scc:
4375: // confirmed
4376: next_level_000 ();
4377: genamode (curi, curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
4378: start_brace ();
4379: fill_prefetch_next();
4380: start_brace ();
4381: printf ("\tint val = cctrue (%d) ? 0xff : 0;\n", curi->cc);
4382: if (isreg (curi->smode)) {
4383: if (using_ce)
4384: printf ("\tint cycles = val ? 2 : 0;\n");
4385: addcycles000_3 ("\t");
4386: addcycles000_nonces("\t", "(val ? 2 : 0)");
4387: }
4388: genastore ("val", curi->smode, "srcreg", curi->size, "src");
4389: break;
4390: case i_DIVU:
4391: tail_ce020_done = true;
4392: genamodedual (curi,
4393: curi->smode, "srcreg", sz_word, "src", 1, 0,
4394: curi->dmode, "dstreg", sz_long, "dst", 1, 0);
4395: printf ("\tCLEAR_CZNV ();\n");
4396: printf ("\tif (src == 0) {\n");
4397: if (cpu_level > 1)
4398: printf ("\t\tdivbyzero_special (0, dst);\n");
4399: incpc ("%d", m68k_pc_offset);
1.1.1.6 ! root 4400: printf ("\t\tException_cpu(5);\n");
1.1.1.5 root 4401: printf ("\t\tgoto %s;\n", endlabelstr);
4402: printf ("\t} else {\n");
4403: printf ("\t\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
4404: printf ("\t\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
4405: if (using_ce) {
4406: start_brace ();
4407: printf ("\t\tint cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;\n");
4408: addcycles000_3 ("\t\t");
4409: }
4410: addcycles000_nonces("\t\t", "(getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4");
4411: fill_prefetch_next ();
4412: /* The N flag appears to be set each time there is an overflow.
4413: * Weird. but 68020 only sets N when dst is negative.. */
4414: printf ("\t\tif (newv > 0xffff) {\n");
1.1.1.6 ! root 4415: printf ("\t\t\tsetdivuoverflowflags((uae_u32)dst, (uae_u16)src);\n");
1.1.1.5 root 4416: printf ("\t\t} else {\n");
4417: printf ("\t\t"); genflags (flag_logical, sz_word, "newv", "", "");
4418: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
4419: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
4420: printf ("\t\t}\n");
4421: sync_m68k_pc ();
4422: printf ("\t}\n");
4423: count_ncycles++;
4424: insn_n_cycles += 136 - (136 - 76) / 2; /* average */
4425: need_endlabel = 1;
4426: tail_ce020_done = false;
4427: returntail (false);
4428: break;
4429: case i_DIVS:
4430: tail_ce020_done = true;
4431: genamodedual (curi,
4432: curi->smode, "srcreg", sz_word, "src", 1, 0,
4433: curi->dmode, "dstreg", sz_long, "dst", 1, 0);
4434: printf ("\tif (src == 0) {\n");
4435: if (cpu_level > 1)
4436: printf ("\t\tdivbyzero_special (1, dst);\n");
4437: incpc ("%d", m68k_pc_offset);
1.1.1.6 ! root 4438: printf ("\t\tException_cpu(5);\n");
1.1.1.5 root 4439: printf ("\t\tgoto %s;\n", endlabelstr);
4440: printf ("\t}\n");
4441: printf ("\tCLEAR_CZNV ();\n");
4442: if (using_ce) {
4443: start_brace ();
4444: printf ("\t\tint cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;\n");
4445: addcycles000_3 ("\t\t");
4446: }
4447: addcycles000_nonces("\t\t", "(getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4");
4448: fill_prefetch_next ();
4449: printf ("\tif (dst == 0x80000000 && src == -1) {\n");
1.1.1.6 ! root 4450: printf ("\t\tsetdivsoverflowflags((uae_s32)dst, (uae_s16)src);\n");
1.1.1.5 root 4451: printf ("\t} else {\n");
4452: printf ("\t\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
4453: printf ("\t\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
4454: printf ("\t\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {\n");
1.1.1.6 ! root 4455: printf ("\t\t\tsetdivsoverflowflags((uae_s32)dst, (uae_s16)src);\n");
1.1.1.5 root 4456: printf ("\t\t} else {\n");
4457: printf ("\t\t\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
4458: genflags (flag_logical, sz_word, "newv", "", "");
4459: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
4460: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
4461: printf ("\t\t}\n");
4462: printf ("\t}\n");
4463: sync_m68k_pc ();
4464: count_ncycles++;
4465: insn_n_cycles += 156 - (156 - 120) / 2; /* average */
4466: need_endlabel = 1;
4467: tail_ce020_done = false;
4468: returntail (false);
4469: break;
4470: case i_MULU:
4471: genamodedual (curi,
4472: curi->smode, "srcreg", sz_word, "src", 1, 0,
4473: curi->dmode, "dstreg", sz_word, "dst", 1, 0);
4474: fill_prefetch_next();
4475: start_brace ();
4476: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
4477: if (using_ce)
4478: printf ("\tint cycles = 38 - 4, bits;\n");
4479: else if (using_prefetch)
4480: printf ("\tint bits;\n");
4481: genflags (flag_logical, sz_long, "newv", "", "");
4482: if (using_ce) {
4483: printf ("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n");
4484: printf ("\t\tif (src & 1) cycles += 2;\n");
4485: addcycles000_3 ("\t");
4486: }
4487: addcycles000_nonce("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n\t\tif (src & 1) ", 2);
4488: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
4489: sync_m68k_pc ();
4490: count_cycles += 38 - 4;
4491: count_ncycles++;
4492: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
4493: break;
4494: case i_MULS:
4495: genamodedual (curi,
4496: curi->smode, "srcreg", sz_word, "src", 1, 0,
4497: curi->dmode, "dstreg", sz_word, "dst", 1, 0);
4498: fill_prefetch_next();
4499: start_brace ();
4500: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
4501: if (using_ce) {
4502: printf ("\tint cycles = 38 - 4, bits;\n");
4503: printf ("\tuae_u32 usrc;\n");
4504: } else if (using_prefetch) {
4505: printf ("\tint bits;\n");
4506: printf ("\tuae_u32 usrc;\n");
4507: }
4508: genflags (flag_logical, sz_long, "newv", "", "");
4509: if (using_ce) {
4510: printf ("\tusrc = ((uae_u32)src) << 1;\n");
4511: printf ("\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n");
4512: printf ("\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;\n");
4513: addcycles000_3 ("\t");
4514: }
4515: addcycles000_nonce("\tusrc = ((uae_u32)src) << 1;\n\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) ", 2);
4516: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
4517: count_cycles += 38 - 4;
4518: count_ncycles++;
4519: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
4520: break;
4521: case i_CHK:
4522: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
4523: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
4524: sync_m68k_pc ();
4525: addcycles000 (4);
4526: printf ("\tif (dst > src) {\n");
4527: printf ("\t\tSET_NFLG (0);\n");
1.1.1.6 ! root 4528: printf ("\t\tException_cpu(6);\n");
1.1.1.5 root 4529: printf ("\t\tgoto %s;\n", endlabelstr);
4530: printf ("\t}\n");
4531: addcycles000 (2);
4532: printf ("\tif ((uae_s32)dst < 0) {\n");
4533: printf ("\t\tSET_NFLG (1);\n");
1.1.1.6 ! root 4534: printf ("\t\tException_cpu(6);\n");
1.1.1.5 root 4535: printf ("\t\tgoto %s;\n", endlabelstr);
4536: printf ("\t}\n");
4537: fill_prefetch_next ();
4538: need_endlabel = 1;
4539: break;
4540: case i_CHK2:
4541: genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
4542: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
4543: fill_prefetch_0 ();
4544: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
4545: switch (curi->size) {
4546: case sz_byte:
4547: printf ("\tlower = (uae_s32)(uae_s8)%s (dsta); upper = (uae_s32)(uae_s8)%s (dsta + 1);\n", srcb, srcb);
4548: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
4549: break;
4550: case sz_word:
4551: printf ("\tlower = (uae_s32)(uae_s16)%s (dsta); upper = (uae_s32)(uae_s16)%s (dsta + 2);\n", srcw, srcw);
4552: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
4553: break;
4554: case sz_long:
4555: printf ("\tlower = %s (dsta); upper = %s (dsta + 4);\n", srcl, srcl);
4556: break;
4557: default:
4558: term ();
4559: }
4560: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
4561: printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1.1.1.6 ! root 4562: printf ("\tif ((extra & 0x800) && GET_CFLG ()) { Exception_cpu(6); goto %s; }\n}\n", endlabelstr);
1.1.1.5 root 4563: need_endlabel = 1;
4564: break;
4565:
4566: case i_ASR:
4567: genamodedual (curi,
4568: curi->smode, "srcreg", curi->size, "cnt", 1, 0,
4569: curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
4570: //genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
4571: //genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
4572: fill_prefetch_next();
4573: start_brace ();
4574: switch (curi->size) {
4575: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4576: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4577: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4578: default: term ();
4579: }
4580: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
4581: printf ("\tint ccnt = cnt & 63;\n");
4582: printf ("\tcnt &= 63;\n");
4583: printf ("\tCLEAR_CZNV ();\n");
4584: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
4585: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
4586: printf ("\t\tSET_CFLG (sign);\n");
4587: duplicate_carry (1);
4588: if (source_is_imm1_8 (curi))
4589: printf ("\t} else {\n");
4590: else
4591: printf ("\t} else if (cnt > 0) {\n");
4592: printf ("\t\tval >>= cnt - 1;\n");
4593: printf ("\t\tSET_CFLG (val & 1);\n");
4594: duplicate_carry (1);
4595: printf ("\t\tval >>= 1;\n");
4596: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
4597: bit_mask (curi->size),
4598: bit_size (curi->size));
4599: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
4600: printf ("\t}\n");
4601: genflags (flag_logical_noclobber, curi->size, "val", "", "");
4602: shift_ce (curi->dmode, curi->size);
4603: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
4604: break;
4605: case i_ASL:
4606: genamodedual (curi,
4607: curi->smode, "srcreg", curi->size, "cnt", 1, 0,
4608: curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
4609: //genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
4610: //genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
4611: fill_prefetch_next();
4612: start_brace ();
4613: switch (curi->size) {
4614: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4615: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4616: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4617: default: term ();
4618: }
4619: printf ("\tint ccnt = cnt & 63;\n");
4620: printf ("\tcnt &= 63;\n");
4621: printf ("\tCLEAR_CZNV ();\n");
4622: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
4623: printf ("\t\tSET_VFLG (val != 0);\n");
4624: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
4625: bit_size (curi->size));
4626: duplicate_carry (1);
4627: printf ("\t\tval = 0;\n");
4628: if (source_is_imm1_8 (curi))
4629: printf ("\t} else {\n");
4630: else
4631: printf ("\t} else if (cnt > 0) {\n");
4632: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
4633: bit_mask (curi->size),
4634: bit_size (curi->size) - 1,
4635: bit_mask (curi->size));
4636: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
4637: printf ("\t\tval <<= cnt - 1;\n");
4638: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
4639: duplicate_carry (1);
4640: printf ("\t\tval <<= 1;\n");
4641: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
4642: printf ("\t}\n");
4643: genflags (flag_logical_noclobber, curi->size, "val", "", "");
4644: shift_ce (curi->dmode, curi->size);
4645: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
4646: break;
4647: case i_LSR:
4648: genamodedual (curi,
4649: curi->smode, "srcreg", curi->size, "cnt", 1, 0,
4650: curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
4651: //genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
4652: //genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
4653: fill_prefetch_next();
4654: start_brace ();
4655: switch (curi->size) {
4656: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4657: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4658: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4659: default: term ();
4660: }
4661: printf ("\tint ccnt = cnt & 63;\n");
4662: printf ("\tcnt &= 63;\n");
4663: printf ("\tCLEAR_CZNV ();\n");
4664: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
4665: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
4666: bit_size (curi->size), bit_size (curi->size) - 1);
4667: duplicate_carry (1);
4668: printf ("\t\tval = 0;\n");
4669: if (source_is_imm1_8 (curi))
4670: printf ("\t} else {\n");
4671: else
4672: printf ("\t} else if (cnt > 0) {\n");
4673: printf ("\t\tval >>= cnt - 1;\n");
4674: printf ("\t\tSET_CFLG (val & 1);\n");
4675: duplicate_carry (1);
4676: printf ("\t\tval >>= 1;\n");
4677: printf ("\t}\n");
4678: genflags (flag_logical_noclobber, curi->size, "val", "", "");
4679: shift_ce (curi->dmode, curi->size);
4680: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
4681: break;
4682: case i_LSL:
4683: genamodedual (curi,
4684: curi->smode, "srcreg", curi->size, "cnt", 1, 0,
4685: curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
4686: //genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
4687: //genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
4688: fill_prefetch_next();
4689: start_brace ();
4690: switch (curi->size) {
4691: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4692: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4693: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4694: default: term ();
4695: }
4696: printf ("\tint ccnt = cnt & 63;\n");
4697: printf ("\tcnt &= 63;\n");
4698: printf ("\tCLEAR_CZNV ();\n");
4699: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
4700: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", bit_size (curi->size));
4701: duplicate_carry (1);
4702: printf ("\t\tval = 0;\n");
4703: if (source_is_imm1_8 (curi))
4704: printf ("\t} else {\n");
4705: else
4706: printf ("\t} else if (cnt > 0) {\n");
4707: printf ("\t\tval <<= (cnt - 1);\n");
4708: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
4709: duplicate_carry (1);
4710: printf ("\t\tval <<= 1;\n");
4711: printf ("\tval &= %s;\n", bit_mask (curi->size));
4712: printf ("\t}\n");
4713: genflags (flag_logical_noclobber, curi->size, "val", "", "");
4714: shift_ce (curi->dmode, curi->size);
4715: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
4716: break;
4717: case i_ROL:
4718: genamodedual (curi,
4719: curi->smode, "srcreg", curi->size, "cnt", 1, 0,
4720: curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
4721: //genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
4722: //genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
4723: fill_prefetch_next ();
4724: start_brace ();
4725: switch (curi->size) {
4726: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4727: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4728: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4729: default: term ();
4730: }
4731: printf ("\tint ccnt = cnt & 63;\n");
4732: printf ("\tcnt &= 63;\n");
4733: printf ("\tCLEAR_CZNV ();\n");
4734: if (source_is_imm1_8 (curi))
4735: printf ("{");
4736: else
4737: printf ("\tif (cnt > 0) {\n");
4738: printf ("\tuae_u32 loval;\n");
4739: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
4740: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
4741: printf ("\tval <<= cnt;\n");
4742: printf ("\tval |= loval;\n");
4743: printf ("\tval &= %s;\n", bit_mask (curi->size));
4744: printf ("\tSET_CFLG (val & 1);\n");
4745: printf ("}\n");
4746: genflags (flag_logical_noclobber, curi->size, "val", "", "");
4747: shift_ce (curi->dmode, curi->size);
4748: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
4749: break;
4750: case i_ROR:
4751: genamodedual (curi,
4752: curi->smode, "srcreg", curi->size, "cnt", 1, 0,
4753: curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
4754: //genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
4755: //genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
4756: fill_prefetch_next ();
4757: start_brace ();
4758: switch (curi->size) {
4759: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4760: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4761: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4762: default: term ();
4763: }
4764: printf ("\tint ccnt = cnt & 63;\n");
4765: printf ("\tcnt &= 63;\n");
4766: printf ("\tCLEAR_CZNV ();\n");
4767: if (source_is_imm1_8 (curi))
4768: printf ("{");
4769: else
4770: printf ("\tif (cnt > 0) {");
4771: printf ("\tuae_u32 hival;\n");
4772: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
4773: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
4774: printf ("\tval >>= cnt;\n");
4775: printf ("\tval |= hival;\n");
4776: printf ("\tval &= %s;\n", bit_mask (curi->size));
4777: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
4778: printf ("\t}\n");
4779: genflags (flag_logical_noclobber, curi->size, "val", "", "");
4780: shift_ce (curi->dmode, curi->size);
4781: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
4782: break;
4783: case i_ROXL:
4784: genamodedual (curi,
4785: curi->smode, "srcreg", curi->size, "cnt", 1, 0,
4786: curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
4787: //genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
4788: //genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
4789: fill_prefetch_next ();
4790: start_brace ();
4791: switch (curi->size) {
4792: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4793: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4794: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4795: default: term ();
4796: }
4797: printf ("\tint ccnt = cnt & 63;\n");
4798: printf ("\tcnt &= 63;\n");
4799: printf ("\tCLEAR_CZNV ();\n");
4800: if (source_is_imm1_8 (curi))
4801: printf ("{");
4802: else {
4803: force_range_for_rox ("cnt", curi->size);
4804: printf ("\tif (cnt > 0) {\n");
4805: }
4806: printf ("\tcnt--;\n");
4807: printf ("\t{\n\tuae_u32 carry;\n");
4808: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
4809: printf ("\tcarry = loval & 1;\n");
4810: printf ("\tval = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);\n");
4811: printf ("\tSET_XFLG (carry);\n");
4812: printf ("\tval &= %s;\n", bit_mask (curi->size));
4813: printf ("\t} }\n");
4814: printf ("\tSET_CFLG (GET_XFLG ());\n");
4815: genflags (flag_logical_noclobber, curi->size, "val", "", "");
4816: shift_ce (curi->dmode, curi->size);
4817: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
4818: break;
4819: case i_ROXR:
4820: genamodedual (curi,
4821: curi->smode, "srcreg", curi->size, "cnt", 1, 0,
4822: curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
4823: //genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
4824: //genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
4825: fill_prefetch_next ();
4826: start_brace ();
4827: switch (curi->size) {
4828: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4829: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4830: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4831: default: term ();
4832: }
4833: printf ("\tint ccnt = cnt & 63;\n");
4834: printf ("\tcnt &= 63;\n");
4835: printf ("\tCLEAR_CZNV ();\n");
4836: if (source_is_imm1_8 (curi))
4837: printf ("{");
4838: else {
4839: force_range_for_rox ("cnt", curi->size);
4840: printf ("\tif (cnt > 0) {\n");
4841: }
4842: printf ("\tcnt--;\n");
4843: printf ("\t{\n\tuae_u32 carry;\n");
4844: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG ();\n");
4845: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
4846: printf ("\tval >>= cnt;\n");
4847: printf ("\tcarry = val & 1;\n");
4848: printf ("\tval >>= 1;\n");
4849: printf ("\tval |= hival;\n");
4850: printf ("\tSET_XFLG (carry);\n");
4851: printf ("\tval &= %s;\n", bit_mask (curi->size));
4852: printf ("\t} }\n");
4853: printf ("\tSET_CFLG (GET_XFLG ());\n");
4854: genflags (flag_logical_noclobber, curi->size, "val", "", "");
4855: shift_ce (curi->dmode, curi->size);
4856: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
4857: break;
4858: case i_ASRW:
4859: genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
4860: fill_prefetch_next ();
4861: start_brace ();
4862: switch (curi->size) {
4863: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4864: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4865: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4866: default: term ();
4867: }
4868: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
4869: printf ("\tuae_u32 cflg = val & 1;\n");
4870: printf ("\tval = (val >> 1) | sign;\n");
4871: genflags (flag_logical, curi->size, "val", "", "");
4872: printf ("\tSET_CFLG (cflg);\n");
4873: duplicate_carry (0);
4874: genastore ("val", curi->smode, "srcreg", curi->size, "data");
4875: break;
4876: case i_ASLW:
4877: genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
4878: fill_prefetch_next ();
4879: start_brace ();
4880: switch (curi->size) {
4881: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4882: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4883: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4884: default: term ();
4885: }
4886: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
4887: printf ("\tuae_u32 sign2;\n");
4888: printf ("\tval <<= 1;\n");
4889: genflags (flag_logical, curi->size, "val", "", "");
4890: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
4891: printf ("\tSET_CFLG (sign != 0);\n");
4892: duplicate_carry (0);
4893: printf ("\tSET_VFLG (GET_VFLG () | (sign2 != sign));\n");
4894: genastore ("val", curi->smode, "srcreg", curi->size, "data");
4895: break;
4896: case i_LSRW:
4897: genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
4898: fill_prefetch_next ();
4899: start_brace ();
4900: switch (curi->size) {
4901: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
4902: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
4903: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4904: default: term ();
4905: }
4906: printf ("\tuae_u32 carry = val & 1;\n");
4907: printf ("\tval >>= 1;\n");
4908: genflags (flag_logical, curi->size, "val", "", "");
4909: printf ("\tSET_CFLG (carry);\n");
4910: duplicate_carry (0);
4911: genastore ("val", curi->smode, "srcreg", curi->size, "data");
4912: break;
4913: case i_LSLW:
4914: genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
4915: fill_prefetch_next ();
4916: start_brace ();
4917: switch (curi->size) {
4918: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
4919: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
4920: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4921: default: term ();
4922: }
4923: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
4924: printf ("\tval <<= 1;\n");
4925: genflags (flag_logical, curi->size, "val", "", "");
4926: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
4927: duplicate_carry (0);
4928: genastore ("val", curi->smode, "srcreg", curi->size, "data");
4929: break;
4930: case i_ROLW:
4931: genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
4932: fill_prefetch_next ();
4933: start_brace ();
4934: switch (curi->size) {
4935: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
4936: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
4937: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4938: default: term ();
4939: }
4940: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
4941: printf ("\tval <<= 1;\n");
4942: printf ("\tif (carry) val |= 1;\n");
4943: genflags (flag_logical, curi->size, "val", "", "");
4944: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
4945: genastore ("val", curi->smode, "srcreg", curi->size, "data");
4946: break;
4947: case i_RORW:
4948: genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
4949: fill_prefetch_next ();
4950: start_brace ();
4951: switch (curi->size) {
4952: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
4953: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
4954: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4955: default: term ();
4956: }
4957: printf ("\tuae_u32 carry = val & 1;\n");
4958: printf ("\tval >>= 1;\n");
4959: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
4960: genflags (flag_logical, curi->size, "val", "", "");
4961: printf ("\tSET_CFLG (carry);\n");
4962: genastore ("val", curi->smode, "srcreg", curi->size, "data");
4963: break;
4964: case i_ROXLW:
4965: genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
4966: fill_prefetch_next ();
4967: start_brace ();
4968: switch (curi->size) {
4969: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
4970: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
4971: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4972: default: term ();
4973: }
4974: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
4975: printf ("\tval <<= 1;\n");
4976: printf ("\tif (GET_XFLG ()) val |= 1;\n");
4977: genflags (flag_logical, curi->size, "val", "", "");
4978: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
4979: duplicate_carry (0);
4980: genastore ("val", curi->smode, "srcreg", curi->size, "data");
4981: break;
4982: case i_ROXRW:
4983: genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
4984: fill_prefetch_next ();
4985: start_brace ();
4986: switch (curi->size) {
4987: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
4988: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
4989: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
4990: default: term ();
4991: }
4992: printf ("\tuae_u32 carry = val & 1;\n");
4993: printf ("\tval >>= 1;\n");
4994: printf ("\tif (GET_XFLG ()) val |= %s;\n", cmask (curi->size));
4995: genflags (flag_logical, curi->size, "val", "", "");
4996: printf ("\tSET_CFLG (carry);\n");
4997: duplicate_carry (0);
4998: genastore ("val", curi->smode, "srcreg", curi->size, "data");
4999: break;
5000: case i_MOVEC2:
5001: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
5002: fill_prefetch_next ();
5003: start_brace ();
5004: printf ("\tint regno = (src >> 12) & 15;\n");
5005: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
5006: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
5007: break;
5008: case i_MOVE2C:
5009: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
5010: fill_prefetch_next ();
5011: start_brace ();
5012: printf ("\tint regno = (src >> 12) & 15;\n");
5013: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
5014: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
5015: break;
5016: case i_CAS:
5017: {
5018: int old_brace_level;
5019: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_LRMW);
5020: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_LRMW);
5021: if (cpu_level == 5 && curi->size > 0) {
5022: printf ("\tif ((dsta & %d) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {\n", curi->size == 1 ? 1 : 3);
5023: if (curi->dmode == Aipi || curi->dmode == Apdi)
5024: printf ("\t\tm68k_areg (regs, dstreg) %c= %d;\n", curi->dmode == Aipi ? '-' : '+', 1 << curi->size);
5025: sync_m68k_pc_noreset ();
5026: printf ("\t\top_unimpl (opcode);\n");
5027: printf ("\t\tgoto %s;\n", endlabelstr);
5028: printf ("\t}\n");
5029: need_endlabel = 1;
5030: }
5031: fill_prefetch_0 ();
5032: start_brace ();
5033: printf ("\tint ru = (src >> 6) & 7;\n");
5034: printf ("\tint rc = src & 7;\n");
5035: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, rc)", "dst");
5036: gen_set_fault_pc ();
5037: printf ("\tif (GET_ZFLG ()) ");
5038: old_brace_level = n_braces;
5039: start_brace ();
5040: printf ("\n\t");
5041: genastore_cas ("(m68k_dreg (regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
5042: printf ("\t");
5043: pop_braces (old_brace_level);
5044: printf ("else");
5045: start_brace ();
5046: printf ("\n");
5047: get_prefetch_020 ();
5048: if (cpu_level >= 4) {
5049: // apparently 68040/060 needs to always write at the end of RMW cycle
5050: printf ("\t");
5051: genastore_cas ("dst", curi->dmode, "dstreg", curi->size, "dst");
5052: }
5053: switch (curi->size) {
5054: case sz_byte:
5055: printf ("\t\tm68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);\n");
5056: break;
5057: case sz_word:
5058: printf ("\t\tm68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);\n");
5059: break;
5060: default:
5061: printf ("\t\tm68k_dreg(regs, rc) = dst;\n");
5062: break;
5063: }
5064: pop_braces (old_brace_level);
5065: }
5066: break;
5067: case i_CAS2:
5068: genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, GF_LRMW);
5069: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
5070: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
5071: if (curi->size == sz_word) {
5072: int old_brace_level = n_braces;
5073: printf ("\tuae_u16 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcwlrmw, srcwlrmw);
5074: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
5075: printf ("\tif (GET_ZFLG ()) {\n");
5076: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
5077: printf ("\tif (GET_ZFLG ()) {\n");
5078: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstwlrmw);
5079: printf ("\t%s (rn2, m68k_dreg (regs, (extra >> 6) & 7));\n", dstwlrmw);
5080: printf ("\t}}\n");
5081: pop_braces (old_brace_level);
5082: printf ("\tif (! GET_ZFLG ()) {\n");
5083: printf ("\tm68k_dreg (regs, (extra >> 0) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
5084: printf ("\tm68k_dreg (regs, (extra >> 16) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
5085: printf ("\t}\n");
5086: } else {
5087: int old_brace_level = n_braces;
5088: printf ("\tuae_u32 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcllrmw, srcllrmw);
5089: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
5090: printf ("\tif (GET_ZFLG ()) {\n");
5091: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
5092: printf ("\tif (GET_ZFLG ()) {\n");
5093: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstllrmw);
5094: printf ("\t%s (rn2, m68k_dreg (regs, (extra >> 6) & 7));\n", dstllrmw);
5095: printf ("\t}}\n");
5096: pop_braces (old_brace_level);
5097: printf ("\tif (! GET_ZFLG ()) {\n");
5098: printf ("\tm68k_dreg (regs, (extra >> 0) & 7) = dst2;\n");
5099: printf ("\tm68k_dreg (regs, (extra >> 16) & 7) = dst1;\n");
5100: printf ("\t}\n");
5101: }
5102: break;
5103: case i_MOVES: /* ignore DFC and SFC when using_mmu == false */
5104: {
5105: int old_brace_level;
5106: tail_ce020_done = true;
5107: genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
5108: printf ("\tif (extra & 0x800)\n");
5109: {
5110: int old_m68k_pc_offset = m68k_pc_offset;
5111: old_brace_level = n_braces;
5112: start_brace ();
5113: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
5114: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
5115: genastore_fc ("src", curi->dmode, "dstreg", curi->size, "dst");
5116: pop_braces (old_brace_level);
5117: m68k_pc_offset = old_m68k_pc_offset;
5118: }
5119: printf ("else");
5120: {
5121: start_brace ();
5122: genamode (curi, curi->dmode, "dstreg", curi->size, "src", 1, 0, GF_FC);
5123: printf ("\tif (extra & 0x8000) {\n");
5124: switch (curi->size) {
5125: case sz_byte: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
5126: case sz_word: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
5127: case sz_long: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = src;\n"); break;
5128: default: term ();
5129: }
5130: printf ("\t} else {\n");
5131: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
5132: printf ("\t}\n");
5133: if (using_mmu == 68040)
5134: sync_m68k_pc ();
5135: pop_braces (old_brace_level);
5136: }
5137: tail_ce020_done = false;
5138: returntail (false);
5139: }
5140: break;
5141: case i_BKPT: /* only needed for hardware emulators */
5142: sync_m68k_pc ();
5143: printf ("\top_illg (opcode);\n");
5144: did_prefetch = -1;
5145: break;
5146: case i_CALLM: /* not present in 68030 */
5147: sync_m68k_pc ();
5148: printf ("\top_illg (opcode);\n");
5149: did_prefetch = -1;
5150: break;
5151: case i_RTM: /* not present in 68030 */
5152: sync_m68k_pc ();
5153: printf ("\top_illg (opcode);\n");
5154: did_prefetch = -1;
5155: break;
5156: case i_TRAPcc:
5157: if (curi->smode != am_unknown && curi->smode != am_illg)
5158: genamode (curi, curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
5159: fill_prefetch_0 ();
1.1.1.6 ! root 5160: printf ("\tif (cctrue (%d)) { Exception_cpu(7); goto %s; }\n", curi->cc, endlabelstr);
1.1.1.5 root 5161: need_endlabel = 1;
5162: break;
5163: case i_DIVL:
5164: genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
5165: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
5166: sync_m68k_pc ();
5167: printf ("\tif (!m68k_divl(opcode, dst, extra)) goto %s;\n", endlabelstr);
5168: need_endlabel = 1;
5169: break;
5170: case i_MULL:
5171: genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
5172: genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
5173: sync_m68k_pc ();
5174: printf ("\tif (!m68k_mull(opcode, dst, extra)) goto %s;\n", endlabelstr);
5175: need_endlabel = 1;
5176: break;
5177: case i_BFTST:
5178: case i_BFEXTU:
5179: case i_BFCHG:
5180: case i_BFEXTS:
5181: case i_BFCLR:
5182: case i_BFFFO:
5183: case i_BFSET:
5184: case i_BFINS:
5185: {
5186: const char *getb, *putb;
5187:
5188: if (using_mmu == 68060 && (curi->mnemo == i_BFCHG || curi->mnemo == i_BFCLR || curi->mnemo == i_BFSET || curi->mnemo == i_BFINS)) {
5189: getb = "mmu060_get_rmw_bitfield";
5190: putb = "mmu060_put_rmw_bitfield";
5191: } else if (using_mmu || using_ce020 || using_indirect > 0) {
5192: getb = "x_get_bitfield";
5193: putb = "x_put_bitfield";
5194: } else {
5195: getb = "get_bitfield";
5196: putb = "put_bitfield";
5197: }
5198:
5199: genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
5200: genamode (curi, curi->dmode, "dstreg", sz_long, "dst", 2, 0, 0);
5201: start_brace ();
5202: printf ("\tuae_u32 bdata[2];\n");
5203: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
5204: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
5205: if (curi->mnemo == i_BFFFO)
5206: printf("\tuae_u32 offset2 = offset;\n");
5207: if (curi->dmode == Dreg) {
5208: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg);\n");
5209: printf ("\toffset &= 0x1f;\n");
5210: printf ("\ttmp = (tmp << offset) | (tmp >> (32 - offset));\n");
5211: printf ("\tbdata[0] = tmp & ((1 << (32 - width)) - 1);\n");
5212: } else {
5213: printf ("\tuae_u32 tmp;\n");
5214: printf ("\tdsta += offset >> 3;\n");
5215: printf ("\ttmp = %s (dsta, bdata, offset, width);\n", getb);
5216: }
5217: printf ("\tSET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);\n");
5218: if (curi->mnemo == i_BFEXTS)
5219: printf ("\ttmp = (uae_s32)tmp >> (32 - width);\n");
5220: else
5221: printf ("\ttmp >>= (32 - width);\n");
5222: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
5223: switch (curi->mnemo) {
5224: case i_BFTST:
5225: break;
5226: case i_BFEXTU:
5227: case i_BFEXTS:
5228: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = tmp;\n");
5229: break;
5230: case i_BFCHG:
5231: printf ("\ttmp = tmp ^ (0xffffffffu >> (32 - width));\n");
5232: break;
5233: case i_BFCLR:
5234: printf ("\ttmp = 0;\n");
5235: break;
5236: case i_BFFFO:
5237: printf ("\t{ uae_u32 mask = 1 << (width - 1);\n");
5238: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}\n");
5239: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = offset2;\n");
5240: break;
5241: case i_BFSET:
5242: printf ("\ttmp = 0xffffffffu >> (32 - width);\n");
5243: break;
5244: case i_BFINS:
5245: printf ("\ttmp = m68k_dreg (regs, (extra >> 12) & 7);\n");
5246: printf ("\ttmp = tmp & (0xffffffffu >> (32 - width));\n");
5247: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
5248: printf ("\tSET_ZFLG (tmp == 0);\n");
5249: break;
5250: default:
5251: break;
5252: }
5253: if (curi->mnemo == i_BFCHG
5254: || curi->mnemo == i_BFCLR
5255: || curi->mnemo == i_BFSET
5256: || curi->mnemo == i_BFINS) {
5257: if (curi->dmode == Dreg) {
5258: printf ("\ttmp = bdata[0] | (tmp << (32 - width));\n");
5259: printf ("\tm68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));\n");
5260: } else {
5261: printf ("\t%s(dsta, bdata, tmp, offset, width);\n", putb);
5262: }
5263: }
5264: }
5265: break;
5266: case i_PACK:
5267: if (curi->smode == Dreg) {
5268: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg) + %s;\n", gen_nextiword (0));
5269: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
5270: } else {
5271: printf ("\tuae_u16 val;\n");
5272: addmmufixup ("srcreg");
5273: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
5274: printf ("\tval = (uae_u16)(%s (m68k_areg (regs, srcreg)) & 0xff);\n", srcb);
5275: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
5276: printf ("\tval = (val | ((uae_u16)(%s (m68k_areg (regs, srcreg)) & 0xff) << 8)) + %s;\n", srcb, gen_nextiword (0));
5277: addmmufixup ("dstreg");
5278: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
5279: gen_set_fault_pc ();
5280: printf ("\t%s (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n", dstb);
5281: }
5282: break;
5283: case i_UNPK:
5284: if (curi->smode == Dreg) {
5285: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg);\n");
5286: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
5287: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
5288: } else {
5289: printf ("\tuae_u16 val;\n");
5290: addmmufixup ("srcreg");
5291: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
5292: printf ("\tval = (uae_u16)(%s (m68k_areg (regs, srcreg)) & 0xff);\n", srcb);
5293: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
5294: addmmufixup ("dstreg");
5295: if (cpu_level >= 2) {
5296: printf ("\tm68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];\n");
5297: printf ("\t%s (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);\n", dstb);
5298: printf ("\t%s (m68k_areg (regs, dstreg), val >> 8);\n", dstb);
5299: } else {
5300: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
5301: printf ("\t%s (m68k_areg (regs, dstreg),val);\n", dstb);
5302: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
5303: gen_set_fault_pc ();
5304: printf ("\t%s (m68k_areg (regs, dstreg),val >> 8);\n", dstb);
5305: }
5306: }
5307: break;
5308: case i_TAS:
5309: genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_LRMW);
5310: genflags (flag_logical, curi->size, "src", "", "");
5311: if (!isreg (curi->smode))
5312: addcycles000 (2);
5313: fill_prefetch_next ();
5314: printf ("\tsrc |= 0x80;\n");
5315: if (cpu_level >= 2 || curi->smode == Dreg || !using_ce) {
5316: if (next_cpu_level < 2)
5317: next_cpu_level = 2 - 1;
5318: genastore_tas ("src", curi->smode, "srcreg", curi->size, "src");
5319: } else {
5320: printf ("\tif (!is_cycle_ce ()) {\n");
5321: genastore ("src", curi->smode, "srcreg", curi->size, "src");
5322: printf ("\t} else {\n");
5323: printf ("\t\t%s (4);\n", do_cycles);
5324: addcycles000_nonce("\t\t", 4);
5325: printf ("\t}\n");
5326: }
5327: break;
5328: case i_FPP:
5329: fpulimit();
5330: genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
5331: sync_m68k_pc ();
5332: printf ("\tfpuop_arithmetic(opcode, extra);\n");
5333: if (using_prefetch || using_prefetch_020) {
5334: printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
5335: need_endlabel = 1;
5336: }
5337: break;
5338: case i_FDBcc:
5339: fpulimit();
5340: genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
5341: sync_m68k_pc ();
5342: printf ("\tfpuop_dbcc (opcode, extra);\n");
5343: if (using_prefetch || using_prefetch_020) {
5344: printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
5345: printf ("\tif (regs.fp_branch) {\n");
5346: printf ("\t\tregs.fp_branch = false;\n");
5347: printf ("\t\tfill_prefetch();\n");
5348: printf ("\t\tgoto %s;\n", endlabelstr);
5349: printf ("\t}\n");
5350: need_endlabel = 1;
1.1.1.6 ! root 5351: } else {
! 5352: printf ("\tif (regs.fp_branch) {\n");
! 5353: printf ("\t\tregs.fp_branch = false;\n");
! 5354: printf ("\t\tif(regs.t0) check_t0_trace();\n");
! 5355: printf ("\t}\n");
1.1.1.5 root 5356: }
5357: break;
5358: case i_FScc:
5359: fpulimit();
5360: genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
5361: sync_m68k_pc ();
5362: printf ("\tfpuop_scc (opcode, extra);\n");
5363: if (using_prefetch || using_prefetch_020) {
5364: printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
5365: need_endlabel = 1;
5366: }
5367: break;
5368: case i_FTRAPcc:
5369: fpulimit();
5370: printf ("\tuaecptr oldpc = %s;\n", getpc);
5371: printf ("\tuae_u16 extra = %s;\n", gen_nextiword (0));
5372: if (curi->smode != am_unknown && curi->smode != am_illg)
5373: genamode (curi, curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
5374: sync_m68k_pc ();
5375: printf ("\tfpuop_trapcc (opcode, oldpc, extra);\n");
5376: if (using_prefetch || using_prefetch_020) {
5377: printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
5378: need_endlabel = 1;
5379: }
5380: break;
5381: case i_FBcc:
5382: fpulimit();
5383: sync_m68k_pc ();
5384: start_brace ();
5385: printf ("\tuaecptr pc = %s;\n", getpc);
5386: genamode (curi, curi->dmode, "srcreg", curi->size, "extra", 1, 0, 0);
5387: sync_m68k_pc ();
5388: printf ("\tfpuop_bcc (opcode, pc,extra);\n");
5389: if (using_prefetch || using_prefetch_020) {
5390: printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
5391: printf ("\tif (regs.fp_branch) {\n");
5392: printf ("\t\tregs.fp_branch = false;\n");
5393: printf ("\t\tfill_prefetch();\n");
5394: printf ("\t\tgoto %s;\n", endlabelstr);
5395: printf ("\t}\n");
5396: need_endlabel = 1;
1.1.1.6 ! root 5397: } else {
! 5398: printf ("\tif (regs.fp_branch) {\n");
! 5399: printf ("\t\tregs.fp_branch = false;\n");
! 5400: printf ("\t\tif(regs.t0) check_t0_trace();\n");
! 5401: printf ("\t}\n");
1.1.1.5 root 5402: }
5403: break;
5404: case i_FSAVE:
5405: fpulimit();
5406: sync_m68k_pc ();
5407: printf ("\tfpuop_save (opcode);\n");
5408: if (using_prefetch || using_prefetch_020) {
5409: printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
5410: need_endlabel = 1;
5411: }
5412: break;
5413: case i_FRESTORE:
5414: fpulimit();
5415: sync_m68k_pc ();
5416: printf ("\tfpuop_restore (opcode);\n");
5417: if (using_prefetch || using_prefetch_020) {
5418: printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
5419: need_endlabel = 1;
5420: }
5421: break;
5422:
5423: case i_CINVL:
5424: case i_CINVP:
5425: case i_CINVA:
5426: case i_CPUSHL:
5427: case i_CPUSHP:
5428: case i_CPUSHA:
5429: printf ("\tflush_cpu_caches_040(opcode);\n");
5430: if (using_mmu)
5431: printf ("\tflush_mmu%s(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n", mmu_postfix);
5432: printf ("\tif (opcode & 0x80)\n");
5433: printf ("\t\tflush_icache((opcode >> 6) & 3);\n");
5434: break;
5435:
5436: case i_MOVE16:
5437: {
5438: if ((opcode & 0xfff8) == 0xf620) {
5439: /* MOVE16 (Ax)+,(Ay)+ */
5440: printf ("\tuae_u32 v[4];\n");
5441: printf ("\tuaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;\n");
5442: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword (0));
5443: printf ("\tmemd = m68k_areg (regs, dstreg) & ~15;\n");
5444: if (using_mmu >= 68040) {
5445: printf ("\tget_move16_mmu (mems, v);\n");
5446: printf ("\tput_move16_mmu (memd, v);\n");
5447: } else {
5448: printf ("\tv[0] = %s (mems);\n", srcl);
5449: printf ("\tv[1] = %s (mems + 4);\n", srcl);
5450: printf ("\tv[2] = %s (mems + 8);\n", srcl);
5451: printf ("\tv[3] = %s (mems + 12);\n", srcl);
5452: printf ("\t%s (memd , v[0]);\n", dstl);
5453: printf ("\t%s (memd + 4, v[1]);\n", dstl);
5454: printf ("\t%s (memd + 8, v[2]);\n", dstl);
5455: printf ("\t%s (memd + 12, v[3]);\n", dstl);
5456: }
5457: printf ("\tif (srcreg != dstreg)\n");
5458: printf ("\t\tm68k_areg (regs, srcreg) += 16;\n");
5459: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
5460: } else {
5461: /* Other variants */
5462: printf ("\tuae_u32 v[4];\n");
5463: genamode (curi, curi->smode, "srcreg", curi->size, "mems", 0, 2, 0);
5464: genamode (curi, curi->dmode, "dstreg", curi->size, "memd", 0, 2, 0);
5465: if (using_mmu == 68040) {
5466: printf ("\tget_move16_mmu (memsa, mmu040_move16);\n");
5467: printf ("\tput_move16_mmu (memda, mmu040_move16);\n");
5468: } else if (using_mmu == 68060) {
5469: printf ("\tget_move16_mmu (memsa, v);\n");
5470: printf ("\tput_move16_mmu (memda, v);\n");
5471: } else {
5472: printf ("\tmemsa &= ~15;\n");
5473: printf ("\tmemda &= ~15;\n");
5474: printf ("\tv[0] = %s (memsa);\n", srcl);
5475: printf ("\tv[1] = %s (memsa + 4);\n", srcl);
5476: printf ("\tv[2] = %s (memsa + 8);\n", srcl);
5477: printf ("\tv[3] = %s (memsa + 12);\n", srcl);
5478: printf ("\t%s (memda , v[0]);\n", dstl);
5479: printf ("\t%s (memda + 4, v[1]);\n", dstl);
5480: printf ("\t%s (memda + 8, v[2]);\n", dstl);
5481: printf ("\t%s (memda + 12, v[3]);\n", dstl);
5482: }
5483: if ((opcode & 0xfff8) == 0xf600)
5484: printf ("\tm68k_areg (regs, srcreg) += 16;\n");
5485: else if ((opcode & 0xfff8) == 0xf608)
5486: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
5487: }
5488: }
5489: break;
5490:
5491: case i_PFLUSHN:
5492: case i_PFLUSH:
5493: case i_PFLUSHAN:
5494: case i_PFLUSHA:
5495: case i_PLPAR:
5496: case i_PLPAW:
5497: case i_PTESTR:
5498: case i_PTESTW:
5499: sync_m68k_pc ();
5500: printf ("\tmmu_op (opcode, 0);\n");
5501: break;
5502: case i_MMUOP030:
5503: printf("\tuaecptr pc = %s;\n", getpc);
5504: printf("\tuae_u16 extra = %s (2);\n", prefetch_word);
5505: m68k_pc_offset += 2;
5506: sync_m68k_pc();
5507: if (curi->smode == Areg || curi->smode == Dreg)
5508: printf("\tuae_u16 extraa = 0;\n");
5509: else
5510: genamode(curi, curi->smode, "srcreg", curi->size, "extra", 0, 0, 0);
5511: sync_m68k_pc();
5512: if (using_ce020 || using_prefetch_020) {
5513: printf("\tif (mmu_op30 (pc, opcode, extra, extraa)) goto %s;\n", endlabelstr);
5514: need_endlabel = 1;
5515: } else {
5516: printf("\tmmu_op30 (pc, opcode, extra, extraa);\n");
5517: }
5518: break;
5519: default:
5520: term ();
5521: break;
5522: }
5523: end:
5524: if (!genastore_done)
5525: returntail (0);
5526: finish_braces ();
5527: if (limit_braces) {
5528: printf ("\n#endif\n");
5529: n_braces = limit_braces;
5530: limit_braces = 0;
5531: finish_braces ();
5532: }
5533: if (did_prefetch >= 0)
5534: fill_prefetch_finish ();
5535: sync_m68k_pc ();
5536: did_prefetch = 0;
5537: ipl_fetched = 0;
1.1.1.6 ! root 5538: #if 0 // Andreas Grabher: Disabled this part for Previous */
! 5539: if (cpu_level >= 2 && !using_ce && !using_ce020) {
! 5540: int v = curi->clocks;
! 5541: if (v < 4)
! 5542: v = 4;
! 5543: count_cycles = insn_n_cycles = v;
! 5544: }
! 5545: #endif
1.1.1.4 root 5546: }
5547:
5548: static void generate_includes (FILE * f, int id)
5549: {
1.1.1.5 root 5550: fprintf (f, "#include \"main.h\"\n");
5551: fprintf (f, "#include \"sysdeps.h\"\n");
5552: fprintf (f, "#include \"hatari-glue.h\"\n");
5553: fprintf (f, "#include \"maccess.h\"\n");
5554: fprintf (f, "#include \"memory.h\"\n");
5555: fprintf (f, "#include \"newcpu.h\"\n");
5556: fprintf (f, "#include \"cputbl.h\"\n");
5557: if (id == 31 || id == 33)
5558: fprintf (f, "#include \"cpummu.h\"\n");
1.1.1.6 ! root 5559: else if (id == 32 || id == 34 || id == 35)
1.1.1.5 root 5560: fprintf (f, "#include \"cpummu030.h\"\n");
5561:
5562: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
5563: "#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n"
5564: "#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n"
5565: "#ifdef NOFLAGS\n"
5566: "#include \"noflags.h\"\n"
5567: "#endif\n");
1.1.1.4 root 5568: }
5569:
5570: static int postfix;
5571:
5572:
5573: static char *decodeEA (amodes mode, wordsizes size)
5574: {
1.1.1.5 root 5575: static char buffer[80];
5576:
5577: buffer[0] = 0;
5578: switch (mode){
5579: case Dreg:
5580: strcpy (buffer,"Dn");
5581: break;
5582: case Areg:
5583: strcpy (buffer,"An");
5584: break;
5585: case Aind:
5586: strcpy (buffer,"(An)");
5587: break;
5588: case Aipi:
5589: strcpy (buffer,"(An)+");
5590: break;
5591: case Apdi:
5592: strcpy (buffer,"-(An)");
5593: break;
5594: case Ad16:
5595: strcpy (buffer,"(d16,An)");
5596: break;
5597: case Ad8r:
5598: strcpy (buffer,"(d8,An,Xn)");
5599: break;
5600: case PC16:
5601: strcpy (buffer,"(d16,PC)");
5602: break;
5603: case PC8r:
5604: strcpy (buffer,"(d8,PC,Xn)");
5605: break;
5606: case absw:
5607: strcpy (buffer,"(xxx).W");
5608: break;
5609: case absl:
5610: strcpy (buffer,"(xxx).L");
5611: break;
5612: case imm:
5613: switch (size){
5614: case sz_byte:
5615: strcpy (buffer,"#<data>.B");
5616: break;
5617: case sz_word:
5618: strcpy (buffer,"#<data>.W");
5619: break;
5620: case sz_long:
5621: strcpy (buffer,"#<data>.L");
5622: break;
5623: default:
5624: break;
5625: }
5626: break;
5627: case imm0:
5628: strcpy (buffer,"#<data>.B");
5629: break;
5630: case imm1:
5631: strcpy (buffer,"#<data>.W");
5632: break;
5633: case imm2:
5634: strcpy (buffer,"#<data>.L");
5635: break;
5636: case immi:
5637: strcpy (buffer,"#<data>");
5638: break;
5639:
5640: default:
5641: break;
5642: }
5643: return buffer;
5644: }
5645:
5646: static const char *m68k_cc[] = {
5647: "T",
5648: "F",
5649: "HI",
5650: "LS",
5651: "CC",
5652: "CS",
5653: "NE",
5654: "EQ",
5655: "VC",
5656: "VS",
5657: "PL",
5658: "MI",
5659: "GE",
5660: "LT",
5661: "GT",
5662: "LE"
1.1.1.4 root 5663: };
5664:
5665: static char *outopcode (int opcode)
5666: {
1.1.1.5 root 5667: static char out[100];
5668: struct instr *ins;
5669: int i;
5670:
5671: ins = &table68k[opcode];
5672: for (i = 0; lookuptab[i].name[0]; i++) {
5673: if (ins->mnemo == lookuptab[i].mnemo)
5674: break;
5675: }
5676: {
5677: char *s = ua (lookuptab[i].name);
5678: strcpy (out, s);
5679: xfree (s);
5680: }
5681: if (ins->smode == immi)
5682: strcat (out, "Q");
5683: if (ins->size == sz_byte)
5684: strcat (out,".B");
5685: if (ins->size == sz_word)
5686: strcat (out,".W");
5687: if (ins->size == sz_long)
5688: strcat (out,".L");
5689: strcat (out," ");
5690: if (ins->suse)
5691: strcat (out, decodeEA (ins->smode, ins->size));
5692: if (ins->duse) {
5693: if (ins->suse) strcat (out,",");
5694: strcat (out, decodeEA (ins->dmode, ins->size));
5695: }
5696: if (ins->mnemo == i_DBcc || ins->mnemo == i_Scc || ins->mnemo == i_Bcc || ins->mnemo == i_TRAPcc) {
5697: strcat (out, " (");
5698: strcat (out, m68k_cc[table68k[opcode].cc]);
5699: strcat (out, ")");
5700: }
5701:
5702: return out;
5703: }
5704:
5705: struct cputbl_tmp
5706: {
5707: uae_s16 length;
5708: uae_s8 disp020[2];
5709: uae_u8 branch;
5710: };
5711: static struct cputbl_tmp cputbltmp[65536];
1.1.1.4 root 5712:
1.1.1.5 root 5713: static void generate_one_opcode (int rp, const char *extra)
5714: {
5715: int idx;
5716: uae_u16 smsk, dmsk;
5717: unsigned int opcode = opcode_map[rp];
5718: int i68000 = table68k[opcode].clev > 0;
5719:
5720: if (table68k[opcode].mnemo == i_ILLG
5721: || table68k[opcode].clev > cpu_level)
5722: return;
5723:
5724: for (idx = 0; lookuptab[idx].name[0]; idx++) {
5725: if (table68k[opcode].mnemo == lookuptab[idx].mnemo)
5726: break;
5727: }
5728:
5729: if (table68k[opcode].handler != -1)
5730: return;
5731:
5732: if (opcode_next_clev[rp] != cpu_level) {
5733: char *name = ua (lookuptab[idx].name);
5734: if (generate_stbl)
5735: fprintf (stblfile, "{ %sCPUFUNC(op_%04x_%d%s), 0x%04x, %d, { %d, %d }, %d }, /* %s */\n",
5736: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
5737: opcode, opcode_last_postfix[rp],
5738: extra, opcode,
5739: cputbltmp[opcode].length, cputbltmp[opcode].disp020[0], cputbltmp[opcode].disp020[1], cputbltmp[opcode].branch, name);
5740: xfree (name);
5741: return;
5742: }
5743: fprintf (headerfile, "extern %s op_%04x_%d%s_nf;\n",
5744: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix, extra);
5745: fprintf (headerfile, "extern %s op_%04x_%d%s_ff;\n",
5746: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix, extra);
5747: printf ("/* %s */\n", outopcode (opcode));
5748: if (i68000)
5749: printf("#ifndef CPUEMU_68000_ONLY\n");
5750: printf ("%s REGPARAM2 CPUFUNC(op_%04x_%d%s)(uae_u32 opcode)\n{\n", (using_ce || using_ce020) ? "void" : "uae_u32", opcode, postfix, extra);
5751: if (using_simple_cycles)
5752: printf("\tint count_cycles = 0;\n");
5753:
5754: switch (table68k[opcode].stype) {
5755: case 0: smsk = 7; break;
5756: case 1: smsk = 255; break;
5757: case 2: smsk = 15; break;
5758: case 3: smsk = 7; break;
5759: case 4: smsk = 7; break;
5760: case 5: smsk = 63; break;
5761: case 7: smsk = 3; break;
5762: default: term ();
5763: }
5764: dmsk = 7;
5765:
5766: next_cpu_level = -1;
5767: if (table68k[opcode].suse
5768: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
5769: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
5770: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
5771: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
5772: {
5773: if (table68k[opcode].spos == -1) {
5774: if (((int) table68k[opcode].sreg) >= 128)
5775: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
5776: else
5777: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
5778: } else {
5779: char source[100];
5780: int pos = table68k[opcode].spos;
5781:
5782: if (pos)
5783: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
5784: else
5785: sprintf (source, "(opcode & %d)", smsk);
5786:
5787: if (table68k[opcode].stype == 3)
5788: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
5789: else if (table68k[opcode].stype == 1)
5790: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
5791: else
5792: printf ("\tuae_u32 srcreg = %s;\n", source);
5793: }
5794: }
5795: if (table68k[opcode].duse
5796: /* Yes, the dmode can be imm, in case of LINK or DBcc */
5797: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
5798: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
5799: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
5800: {
5801: if (table68k[opcode].dpos == -1) {
5802: if (((int) table68k[opcode].dreg) >= 128)
5803: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
5804: else
5805: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
5806: } else {
5807: int pos = table68k[opcode].dpos;
5808: if (pos)
5809: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
5810: pos, dmsk);
5811: else
5812: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
5813: }
5814: }
5815: need_endlabel = 0;
5816: endlabelno++;
5817: sprintf (endlabelstr, "l_%d", endlabelno);
5818: count_read = count_write = count_ncycles = count_cycles = 0;
5819: count_cycles_ce020 = 0;
5820: count_read_ea = count_write_ea = count_cycles_ea = 0;
5821: gen_opcode (opcode);
5822: if (need_endlabel)
5823: printf ("%s: ;\n", endlabelstr);
5824: clearmmufixup (0);
5825: clearmmufixup (1);
5826: if (using_ce || using_prefetch) {
5827: if (count_read + count_write + count_cycles == 0)
5828: count_cycles = 4;
5829: returncycles ("", (count_read + count_write) * 4 + count_cycles);
5830: printf ("}");
5831: printf (" /* %d%s (%d/%d)",
5832: (count_read + count_write) * 4 + count_cycles, count_ncycles ? "+" : "", count_read, count_write);
5833: printf (" */\n");
5834: } else if (count_read + count_write) {
5835: returncycles ("", (count_read + count_write) * 4 + count_cycles);
5836: printf ("}");
5837: printf("\n");
5838: } else {
5839: returncycles ("", insn_n_cycles);
5840: printf ("}");
5841: printf("\n");
5842: }
5843: printf ("\n");
5844: if (i68000)
5845: printf("#endif\n");
5846: opcode_next_clev[rp] = next_cpu_level;
5847: opcode_last_postfix[rp] = postfix;
5848:
5849: if ((opcode & 0xf000) == 0xf000)
5850: m68k_pc_total = -1;
5851: cputbltmp[opcode].length = m68k_pc_total;
5852:
5853: cputbltmp[opcode].disp020[0] = 0;
5854: if (genamode8r_offset[0] > 0)
5855: cputbltmp[opcode].disp020[0] = m68k_pc_total - genamode8r_offset[0] + 2;
5856: cputbltmp[opcode].disp020[1] = 0;
5857: if (genamode8r_offset[1] > 0)
5858: cputbltmp[opcode].disp020[1] = m68k_pc_total - genamode8r_offset[1] + 2;
5859:
5860: cputbltmp[opcode].branch = branch_inst;
5861:
5862: if (generate_stbl) {
5863: char *name = ua (lookuptab[idx].name);
5864: if (i68000)
5865: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
5866: fprintf (stblfile, "{ %sCPUFUNC(op_%04x_%d%s), 0x%04x, %d, { %d, %d }, %d }, /* %s */\n",
5867: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
5868: opcode, postfix, extra, opcode,
5869: cputbltmp[opcode].length, cputbltmp[opcode].disp020[0], cputbltmp[opcode].disp020[1], cputbltmp[opcode].branch, name);
5870: if (i68000)
5871: fprintf (stblfile, "#endif\n");
5872: xfree (name);
5873: }
5874: }
5875:
5876: static void generate_func (const char *extra)
5877: {
5878: int j, rp;
5879:
5880: /* sam: this is for people with low memory (eg. me :)) */
5881: printf ("\n"
5882: "#if !defined(PART_1) && !defined(PART_2) && "
5883: "!defined(PART_3) && !defined(PART_4) && "
5884: "!defined(PART_5) && !defined(PART_6) && "
5885: "!defined(PART_7) && !defined(PART_8)"
5886: "\n"
5887: "#define PART_1 1\n"
5888: "#define PART_2 1\n"
5889: "#define PART_3 1\n"
5890: "#define PART_4 1\n"
5891: "#define PART_5 1\n"
5892: "#define PART_6 1\n"
5893: "#define PART_7 1\n"
5894: "#define PART_8 1\n"
5895: "#endif\n\n");
5896:
5897: rp = 0;
5898: for(j = 1; j <= 8; ++j) {
5899: int k = (j * nr_cpuop_funcs) / 8;
5900: printf ("#ifdef PART_%d\n",j);
5901: for (; rp < k; rp++)
5902: generate_one_opcode (rp, extra);
5903: printf ("#endif\n\n");
5904: }
5905:
5906: if (generate_stbl)
5907: fprintf (stblfile, "{ 0, 0 }};\n");
1.1.1.4 root 5908: }
5909:
5910: static void generate_cpu (int id, int mode)
5911: {
1.1.1.5 root 5912: char fname[100];
5913: const char *extra, *extraup;
5914: static int postfix2 = -1;
5915: int rp;
5916:
5917: using_tracer = mode;
5918: extra = "";
5919: extraup = "";
5920: if (using_tracer) {
5921: extra = "_t";
5922: extraup = "_T";
5923: }
5924:
5925: postfix = id;
1.1.1.6 ! root 5926: if (id == 0 || id == 11 || id == 13 ||
! 5927: id == 20 || id == 21 || id == 22 || id == 23 || id == 24 ||
! 5928: id == 31 || id == 32 || id == 33 || id == 34 || id == 35 ||
! 5929: id == 40 || id == 50) {
1.1.1.5 root 5930: if (generate_stbl)
5931: fprintf (stblfile, "#ifdef CPUEMU_%d%s\n", postfix, extraup);
5932: postfix2 = postfix;
5933: sprintf (fname, "cpuemu_%d%s.c", postfix, extra);
5934: if (freopen (fname, "wb", stdout) == NULL) {
5935: abort ();
5936: }
5937: generate_includes (stdout, id);
5938: }
5939:
5940: using_exception_3 = 1;
5941: using_prefetch = 0;
5942: using_prefetch_020 = 0;
5943: using_ce = 0;
5944: using_ce020 = 0;
5945: using_mmu = 0;
5946: using_waitstates = 0;
5947: memory_cycle_cnt = 4;
5948: mmu_postfix = "";
5949: using_simple_cycles = 0;
5950: using_indirect = 0;
5951: cpu_generic = false;
5952:
5953: if (id == 11 || id == 12) { // 11 = 68010 prefetch, 12 = 68000 prefetch
5954: cpu_level = id == 11 ? 1 : 0;
5955: using_prefetch = 1;
5956: using_exception_3 = 1;
5957: using_simple_cycles = 1;
5958: if (id == 11) {
5959: read_counts ();
5960: for (rp = 0; rp < nr_cpuop_funcs; rp++)
5961: opcode_next_clev[rp] = cpu_level;
5962: }
5963: } else if (id == 13 || id == 14) { // 13 = 68010 cycle-exact, 14 = 68000 cycle-exact
5964: cpu_level = id == 13 ? 1 : 0;
5965: using_prefetch = 1;
5966: using_exception_3 = 1;
5967: using_ce = 1;
5968: if (id == 13) {
5969: read_counts ();
5970: for (rp = 0; rp < nr_cpuop_funcs; rp++)
5971: opcode_next_clev[rp] = cpu_level;
5972: }
5973: } else if (id == 20) { // 68020 prefetch
5974: cpu_level = 2;
5975: using_prefetch_020 = 1;
5976: read_counts ();
5977: for (rp = 0; rp < nr_cpuop_funcs; rp++)
5978: opcode_next_clev[rp] = cpu_level;
5979: } else if (id == 21) { // 68020 cycle-exact
5980: cpu_level = 2;
5981: using_ce020 = 1;
5982: using_prefetch_020 = 1;
5983: // timing tables are from 030 which has 2
5984: // clock memory accesses, 68020 has 3 clock
5985: // memory accesses
5986: using_waitstates = 1;
5987: memory_cycle_cnt = 3;
5988: read_counts ();
5989: for (rp = 0; rp < nr_cpuop_funcs; rp++)
5990: opcode_next_clev[rp] = cpu_level;
5991: } else if (id == 22) { // 68030 prefetch
5992: cpu_level = 3;
5993: using_prefetch_020 = 2;
5994: read_counts ();
5995: for (rp = 0; rp < nr_cpuop_funcs; rp++)
5996: opcode_next_clev[rp] = cpu_level;
5997: } else if (id == 23) { // 68030 "cycle-exact"
5998: cpu_level = 3;
5999: using_ce020 = 2;
6000: using_prefetch_020 = 2;
6001: memory_cycle_cnt = 2;
6002: read_counts ();
6003: for (rp = 0; rp < nr_cpuop_funcs; rp++)
6004: opcode_next_clev[rp] = cpu_level;
6005: } else if (id == 24 || id == 25) { // 68040/060 "cycle-exact"
6006: cpu_level = id == 24 ? 5 : 4;
6007: using_ce020 = 3;
6008: using_prefetch_020 = 3;
6009: memory_cycle_cnt = 0;
6010: if (id == 24) {
6011: read_counts();
6012: for (rp = 0; rp < nr_cpuop_funcs; rp++)
6013: opcode_next_clev[rp] = cpu_level;
6014: }
6015: } else if (id == 31) { // 31 = 68040 MMU
6016: mmu_postfix = "040";
6017: cpu_level = 4;
6018: using_mmu = 68040;
6019: read_counts ();
6020: for (rp = 0; rp < nr_cpuop_funcs; rp++)
6021: opcode_next_clev[rp] = cpu_level;
6022: } else if (id == 32) { // 32 = 68030 MMU
6023: mmu_postfix = "030";
6024: cpu_level = 3;
6025: using_mmu = 68030;
6026: read_counts ();
6027: for (rp = 0; rp < nr_cpuop_funcs; rp++)
6028: opcode_next_clev[rp] = cpu_level;
6029: } else if (id == 33) { // 33 = 68060 MMU
6030: mmu_postfix = "060";
6031: cpu_level = 5;
6032: using_mmu = 68060;
6033: read_counts ();
6034: for (rp = 0; rp < nr_cpuop_funcs; rp++)
6035: opcode_next_clev[rp] = cpu_level;
1.1.1.6 ! root 6036: } else if (id == 34) { // 34 = 68030 MMU + caches
! 6037: mmu_postfix = "030c";
! 6038: cpu_level = 3;
! 6039: using_prefetch_020 = 2;
! 6040: using_mmu = 68030;
! 6041: read_counts ();
! 6042: for (rp = 0; rp < nr_cpuop_funcs; rp++)
! 6043: opcode_next_clev[rp] = cpu_level;
! 6044: } else if (id == 35) { // 35 = 68030 MMU + caches + CE
! 6045: mmu_postfix = "030c";
! 6046: cpu_level = 3;
! 6047: using_ce020 = 2;
! 6048: using_prefetch_020 = 2;
! 6049: using_mmu = 68030;
! 6050: read_counts ();
! 6051: for (rp = 0; rp < nr_cpuop_funcs; rp++)
! 6052: opcode_next_clev[rp] = cpu_level;
1.1.1.5 root 6053: } else if (id < 6) {
6054: cpu_level = 5 - (id - 0); // "generic"
6055: cpu_generic = true;
6056: } else if (id >= 40 && id < 46) {
6057: cpu_level = 5 - (id - 40); // "generic" + direct
6058: cpu_generic = true;
6059: if (id == 40) {
6060: read_counts();
6061: for (rp = 0; rp < nr_cpuop_funcs; rp++)
6062: opcode_next_clev[rp] = cpu_level;
6063: }
6064: using_indirect = -1;
6065: } else if (id >= 50 && id < 56) {
6066: cpu_level = 5 - (id - 50); // "generic" + indirect
6067: cpu_generic = true;
6068: if (id == 50) {
6069: read_counts();
6070: for (rp = 0; rp < nr_cpuop_funcs; rp++)
6071: opcode_next_clev[rp] = cpu_level;
6072: }
6073: }
6074:
6075: if (!using_indirect)
6076: using_indirect = using_ce || using_ce020 || using_prefetch_020 || id >= 50;
6077:
6078: if (generate_stbl) {
6079: if ((id > 0 && id < 6) || (id >= 20 && id < 40) || (id > 40 && id < 46) || (id > 50 && id < 56))
6080: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
6081: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d%s)[] = {\n", postfix, extra);
6082: }
6083: endlabelno = id * 10000;
6084: generate_func (extra);
6085: if (generate_stbl) {
6086: if ((id > 0 && id < 6) || (id >= 20 && id < 40) || (id > 40 && id < 46) || (id > 50 && id < 56))
6087: fprintf (stblfile, "#endif /* CPUEMU_68000_ONLY */\n");
6088: if (postfix2 >= 0)
6089: fprintf (stblfile, "#endif /* CPUEMU_%d%s */\n", postfix2, extraup);
6090: }
6091: postfix2 = -1;
6092: }
6093:
6094: int main(int argc, char *argv[])
6095: {
6096: int i;
6097:
6098: read_table68k ();
6099: do_merges ();
6100:
6101: opcode_map = xmalloc (int, nr_cpuop_funcs);
6102: opcode_last_postfix = xmalloc (int, nr_cpuop_funcs);
6103: opcode_next_clev = xmalloc (int, nr_cpuop_funcs);
6104: counts = xmalloc (unsigned long, 65536);
6105: read_counts ();
6106:
6107: /* It would be a lot nicer to put all in one file (we'd also get rid of
6108: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
6109: * I don't dare to touch the 68k version. */
6110:
6111: headerfile = fopen ("cputbl.h", "wb");
6112:
6113: stblfile = fopen ("cpustbl.c", "wb");
6114: generate_includes (stblfile, 0);
6115:
6116: for (i = 0; i <= 55; i++) {
1.1.1.4 root 6117: if (i!=31 && i!=32)
1.1.1.5 root 6118: continue;
6119: generate_stbl = 1;
6120: generate_cpu (i, 0);
6121: }
6122:
6123: free (table68k);
6124: return 0;
1.1.1.4 root 6125: }
6126:
6127: void write_log (const TCHAR *format,...)
6128: {
6129: }
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