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1.1.1.4 root 1: /*
2: * UAE - The Un*x Amiga Emulator - CPU core
3: *
4: * Memory management
5: *
6: * (c) 1995 Bernd Schmidt
7: *
8: * Adaptation to Hatari by Thomas Huth
9: * Adaptation to Previous by Andreas Grabher
10: *
11: * This file is distributed under the GNU Public License, version 2 or at
12: * your option any later version. Read the file gpl.txt for details.
13: */
14: const char Memory_fileid[] = "Previous memory.c : " __DATE__ " " __TIME__;
1.1 root 15:
16: #include "config.h"
17: #include "sysdeps.h"
18: #include "hatari-glue.h"
19: #include "maccess.h"
20: #include "memory.h"
21:
22: #include "main.h"
23: #include "ioMem.h"
1.1.1.4 root 24: #include "bmap.h"
25: #include "tmc.h"
26: #include "nbic.h"
1.1 root 27: #include "reset.h"
28: #include "nextMemory.h"
29: #include "m68000.h"
30: #include "configuration.h"
31:
32: #include "newcpu.h"
33:
34:
35: /* Set illegal_mem to 1 for debug output: */
36: #define illegal_mem 1
37:
1.1.1.2 root 38: #define illegal_trace(s) {static int count=0; if (count++<50) { s; }}
1.1 root 39:
40: /*
1.1.1.4 root 41: * NeXT memory map (example for 68030 NeXT Computer)
42: *
43: * Local bus:
44: * 0x00000000 - 0x0001FFFF: ROM
45: * 0x01000000 - 0x0101FFFF: ROM mirror
46: *
47: * 0x02000000 - 0x020FFFFF: Device space
48: *
49: * 0x04000000 - 0x04FFFFFF: RAM bank 0
50: * 0x05000000 - 0x05FFFFFF: RAM bank 1
51: * 0x06000000 - 0x06FFFFFF: RAM bank 2
52: * 0x07000000 - 0x07FFFFFF: RAM bank 3
53: *
54: * 0x0B000000 - 0x0B03FFFF: VRAM
55: *
56: * 0x0C000000 - 0x0C03FFFF: VRAM mirror for MWF0
57: * 0x0D000000 - 0x0D03FFFF: VRAM mirror for MWF1
58: * 0x0E000000 - 0x0E03FFFF: VRAM mirror for MWF2
59: * 0x0F000000 - 0x0F03FFFF: VRAM mirror for MWF3
60: *
61: * 0x10000000 - 0x13FFFFFF: RAM mirror for MWF0
62: * 0x14000000 - 0x17FFFFFF: RAM mirror for MWF1
63: * 0x18000000 - 0x1BFFFFFF: RAM mirror for MWF2
64: * 0x1C000000 - 0x1FFFFFFF: RAM mirror for MWF3
65: *
66: * NeXTbus: (Note: Boards can be configured to occupy 2 slots)
67: * 0x00000000 - 0x1FFFFFFF: NeXTbus board space for slot 0
68: * 0x20000000 - 0x3FFFFFFF: NeXTbus board space for slot 2
69: * 0x40000000 - 0x5FFFFFFF: NeXTbus board space for slot 4
70: * 0x60000000 - 0x7FFFFFFF: NeXTbus board space for slot 6
71: *
72: * 0xF0000000 - 0xF0FFFFFF: NeXTbus slot space for slot 0
73: * 0xF2000000 - 0xF2FFFFFF: NeXTbus slot space for slot 2
74: * 0xF4000000 - 0xF4FFFFFF: NeXTbus slot space for slot 4
75: * 0xF6000000 - 0xF6FFFFFF: NeXTbus slot space for slot 6
1.1 root 76: */
77:
1.1.1.4 root 78:
79: /* ROM */
80: #define NEXT_EPROM_START 0x00000000
81: #define NEXT_EPROM_DIAG_START 0x01000000
82: #define NEXT_EPROM_BMAP_START 0x01000000
83: #define NEXT_EPROM_SIZE 0x00020000
84: #define NEXT_EPROM_MASK 0x0001FFFF
85:
1.1.1.2 root 86: /* Main memory */
1.1.1.4 root 87: #define NEXT_RAM_START 0x04000000
88:
89: #define N_BANKS 4
90: #define NEXT_RAM_BANK_MAX 0x01000000
91: #define NEXT_RAM_BANK_MAX_C 0x00800000
92: #define NEXT_RAM_BANK_MAX_T 0x02000000
93:
94: #define NEXT_RAM_BANK_SEL 0x03000000
95: #define NEXT_RAM_BANK_SEL_C 0x01800000
96: #define NEXT_RAM_BANK_SEL_T 0x06000000
97:
98: uae_u32 NEXT_ram_bank_size;
99: uae_u32 NEXT_ram_bank_mask;
100: uae_u32 NEXT_ram_bank0_mask;
101: uae_u32 NEXT_ram_bank1_mask;
102: uae_u32 NEXT_ram_bank2_mask;
103: uae_u32 NEXT_ram_bank3_mask;
104:
105: /* Main memory with memory write functions */
106: #define NEXT_RAM_MWF0_START 0x10000000
107: #define NEXT_RAM_MWF1_START 0x14000000
108: #define NEXT_RAM_MWF2_START 0x18000000
109: #define NEXT_RAM_MWF3_START 0x1C000000
110:
111: /* VRAM monochrome */
112: #define NEXT_VRAM_START 0x0B000000
113: #define NEXT_VRAM_SIZE 0x00040000
114: #define NEXT_VRAM_MASK 0x0003FFFF
115:
116: /* VRAM monochrome with memory write functions */
117: #define NEXT_VRAM_MWF0_START 0x0C000000
118: #define NEXT_VRAM_MWF1_START 0x0D000000
119: #define NEXT_VRAM_MWF2_START 0x0E000000
120: #define NEXT_VRAM_MWF3_START 0x0F000000
121:
122: /* VRAM color */
123: #define NEXT_VRAM_COLOR_START 0x2C000000
124: #define NEXT_VRAM_COLOR_SIZE 0x00200000
125: #define NEXT_VRAM_COLOR_MASK 0x001FFFFF
126:
127: /* VRAM turbo monochrome and color */
128: #define NEXT_VRAM_TURBO_START 0x0C000000
129:
130: /* IO memory */
131: #define NEXT_IO_START 0x02000000
132: #define NEXT_IO_BMAP_START 0x02100000
133: #define NEXT_IO_TMC_START 0x02200000
134: #define NEXT_IO_SIZE 0x00020000
135: #define NEXT_IO_MASK 0x0001FFFF
136:
137: #define NEXT_BMAP_START 0x020C0000
138: #define NEXT_BMAP_SIZE 0x00000040
139: #define NEXT_BMAP_MASK 0x0000003F
140:
141: #define NEXT_BMAP_MAP_SIZE 0x00010000
142:
143: #define NEXT_NBIC_START 0x02020000
144: #define NEXT_NBIC_SIZE 0x00000008
145: #define NEXT_NBIC_MASK 0x00000007
146:
147: #define NEXT_NBIC_MAP_SIZE 0x00010000
148:
149: /* Cache memory for nitro systems */
150: #define NEXT_CACHE_TAG_START 0x03E00000
151: #define NEXT_CACHE_TAG_SIZE 0x00100000
152: #define NEXT_CACHE_TAG_MASK 0x000FFFFF
153:
154: #define NEXT_CACHE_START 0x03F00000
155: #define NEXT_CACHE_SIZE 0x00100000
156: #define NEXT_CACHE_MASK 0x000FFFFF
157:
158: /* NeXTbus slot memory space */
159: #define NEXTBUS_SLOT_START(x) (0xF0000000|((x)<<24))
160: #define NEXTBUS_SLOT_SIZE 0x01000000
161: #define NEXTBUS_SLOT_MASK 0x00FFFFFF
162:
163: /* NeXTbus board memory space */
164: #define NEXTBUS_BOARD_START(x) ((x)<<28)
165: #define NEXTBUS_BOARD_SIZE 0x10000000
166: #define NEXTBUS_BOARD_MASK 0x0FFFFFFF
1.1 root 167:
168:
1.1.1.4 root 169: uae_u8 NEXTVideo[256*1024];
170:
171: uae_u8 NEXTColorVideo[2*1024*1024];
1.1 root 172:
173:
174: #ifdef SAVE_MEMORY_BANKS
175: addrbank *mem_banks[65536];
176: #else
177: addrbank mem_banks[65536];
178: #endif
179:
180: #ifdef NO_INLINE_MEMORY_ACCESS
181: __inline__ uae_u32 longget (uaecptr addr)
182: {
1.1.1.4 root 183: return call_mem_get_func (get_mem_bank (addr).lget, addr);
1.1 root 184: }
185: __inline__ uae_u32 wordget (uaecptr addr)
186: {
1.1.1.4 root 187: return call_mem_get_func (get_mem_bank (addr).wget, addr);
1.1 root 188: }
189: __inline__ uae_u32 byteget (uaecptr addr)
190: {
1.1.1.4 root 191: return call_mem_get_func (get_mem_bank (addr).bget, addr);
1.1 root 192: }
193: __inline__ void longput (uaecptr addr, uae_u32 l)
194: {
1.1.1.4 root 195: call_mem_put_func (get_mem_bank (addr).lput, addr, l);
1.1 root 196: }
197: __inline__ void wordput (uaecptr addr, uae_u32 w)
198: {
1.1.1.4 root 199: call_mem_put_func (get_mem_bank (addr).wput, addr, w);
1.1 root 200: }
201: __inline__ void byteput (uaecptr addr, uae_u32 b)
202: {
1.1.1.4 root 203: call_mem_put_func (get_mem_bank (addr).bput, addr, b);
1.1 root 204: }
205: #endif
206:
207:
208: /* Some prototypes: */
1.1.1.5 ! root 209: void SDL_Quit(void);
1.1 root 210:
211: uae_u8 ce_cachable[65536];
212:
213:
1.1.1.4 root 214: /* **** A dummy bank that only contains zeros **** */
1.1 root 215:
216: static uae_u32 dummy_lget(uaecptr addr)
217: {
1.1.1.4 root 218: illegal_trace(write_log ("Illegal lget at %08lx PC=%08x\n", (long)addr,m68k_getpc()));
219: return 0;
1.1 root 220: }
221:
222: static uae_u32 dummy_wget(uaecptr addr)
223: {
1.1.1.4 root 224: illegal_trace(write_log ("Illegal wget at %08lx PC=%08x\n", (long)addr,m68k_getpc()));
225: return 0;
1.1 root 226: }
227:
228: static uae_u32 dummy_bget(uaecptr addr)
229: {
1.1.1.4 root 230: illegal_trace(write_log ("Illegal bget at %08lx PC=%08x\n", (long)addr,m68k_getpc()));
231: return 0;
1.1 root 232: }
233:
234: static void dummy_lput(uaecptr addr, uae_u32 l)
235: {
1.1.1.4 root 236: illegal_trace(write_log ("Illegal lput at %08lx PC=%08x\n", (long)addr,m68k_getpc()));
1.1 root 237: }
238:
239: static void dummy_wput(uaecptr addr, uae_u32 w)
240: {
1.1.1.4 root 241: illegal_trace(write_log ("Illegal wput at %08lx PC=%08x\n", (long)addr,m68k_getpc()));
1.1 root 242: }
243:
244: static void dummy_bput(uaecptr addr, uae_u32 b)
245: {
1.1.1.4 root 246: illegal_trace(write_log ("Illegal bput at %08lx PC=%08x\n", (long)addr,m68k_getpc()));
1.1 root 247: }
248:
249:
250: /* **** This memory bank only generates bus errors **** */
251:
252: static uae_u32 BusErrMem_lget(uaecptr addr)
253: {
1.1.1.4 root 254: if (illegal_mem)
255: write_log ("Bus error lget at %08lx\n", (long)addr);
256:
257: M68000_BusError(addr, 1);
258: return 0;
1.1 root 259: }
260:
261: static uae_u32 BusErrMem_wget(uaecptr addr)
262: {
1.1.1.4 root 263: if (illegal_mem)
264: write_log ("Bus error wget at %08lx\n", (long)addr);
265:
266: M68000_BusError(addr, 1);
267: return 0;
1.1 root 268: }
269:
270: static uae_u32 BusErrMem_bget(uaecptr addr)
271: {
1.1.1.4 root 272: if (illegal_mem)
273: write_log ("Bus error bget at %08lx\n", (long)addr);
274:
275: M68000_BusError(addr, 1);
276: return 0;
1.1 root 277: }
278:
279: static void BusErrMem_lput(uaecptr addr, uae_u32 l)
280: {
1.1.1.4 root 281: if (illegal_mem)
282: write_log ("Bus error lput at %08lx\n", (long)addr);
283:
284: M68000_BusError(addr, 0);
1.1 root 285: }
286:
287: static void BusErrMem_wput(uaecptr addr, uae_u32 w)
288: {
1.1.1.4 root 289: if (illegal_mem)
290: write_log ("Bus error wput at %08lx\n", (long)addr);
291:
292: M68000_BusError(addr, 0);
1.1 root 293: }
294:
295: static void BusErrMem_bput(uaecptr addr, uae_u32 b)
296: {
1.1.1.4 root 297: if (illegal_mem)
298: write_log ("Bus error bput at %08lx\n", (long)addr);
299:
300: M68000_BusError(addr, 0);
1.1 root 301: }
302:
303:
1.1.1.4 root 304: /* **** ROM memory **** */
1.1 root 305:
1.1.1.4 root 306: extern int SCR_ROM_overlay;
1.1 root 307:
1.1.1.4 root 308: uae_u8 *ROMmemory;
1.1 root 309:
1.1.1.4 root 310: static uae_u32 mem_rom_lget(uaecptr addr)
1.1 root 311: {
1.1.1.4 root 312: // if ((addr<0x2000) && (SCR_ROM_overlay)) {do_get_mem_long(NEXTRam + 0x03FFE000 +addr);}
313: addr &= NEXT_EPROM_MASK;
314: return do_get_mem_long(ROMmemory + addr);
1.1 root 315: }
316:
1.1.1.4 root 317: static uae_u32 mem_rom_wget(uaecptr addr)
1.1 root 318: {
1.1.1.4 root 319: // if ((addr<0x2000) && (SCR_ROM_overlay)) {do_get_mem_word(NEXTRam + 0x03FFE000 +addr);}
320: addr &= NEXT_EPROM_MASK;
321: return do_get_mem_word(ROMmemory + addr);
322:
1.1 root 323: }
324:
1.1.1.4 root 325: static uae_u32 mem_rom_bget(uaecptr addr)
1.1 root 326: {
1.1.1.4 root 327: // if ((addr<0x2000) && (SCR_ROM_overlay)) {return NEXTRam[0x03FFE000 +addr];}
328: addr &= NEXT_EPROM_MASK;
329: return ROMmemory[addr];
1.1 root 330: }
331:
1.1.1.4 root 332: static void mem_rom_lput(uaecptr addr, uae_u32 b)
1.1 root 333: {
1.1.1.4 root 334: illegal_trace(write_log ("Illegal ROMmem lput at %08lx\n", (long)addr));
335: M68000_BusError(addr, 0);
1.1 root 336: }
337:
1.1.1.4 root 338: static void mem_rom_wput(uaecptr addr, uae_u32 b)
1.1 root 339: {
1.1.1.4 root 340: illegal_trace(write_log ("Illegal ROMmem wput at %08lx\n", (long)addr));
341: M68000_BusError(addr, 0);
1.1 root 342: }
343:
1.1.1.4 root 344: static void mem_rom_bput(uaecptr addr, uae_u32 b)
1.1 root 345: {
1.1.1.4 root 346: illegal_trace(write_log ("Illegal ROMmem bput at %08lx\n", (long)addr));
347: M68000_BusError(addr, 0);
1.1 root 348: }
349:
1.1.1.2 root 350:
1.1.1.4 root 351: /* **** NEXT RAM memory **** */
1.1.1.2 root 352:
1.1.1.4 root 353: static uae_u32 mem_ram_bank0_lget(uaecptr addr)
1.1.1.2 root 354: {
1.1.1.4 root 355: addr &= NEXT_ram_bank0_mask;
356: return do_get_mem_long(NEXTRam + addr);
1.1.1.2 root 357: }
358:
1.1.1.4 root 359: static uae_u32 mem_ram_bank0_wget(uaecptr addr)
1.1.1.2 root 360: {
1.1.1.4 root 361: addr &= NEXT_ram_bank0_mask;
362: return do_get_mem_word(NEXTRam + addr);
1.1.1.2 root 363: }
364:
1.1.1.4 root 365: static uae_u32 mem_ram_bank0_bget(uaecptr addr)
1.1.1.2 root 366: {
1.1.1.4 root 367: addr &= NEXT_ram_bank0_mask;
368: return NEXTRam[addr];
1.1.1.2 root 369: }
370:
1.1.1.4 root 371: static void mem_ram_bank0_lput(uaecptr addr, uae_u32 l)
1.1.1.2 root 372: {
1.1.1.4 root 373: addr &= NEXT_ram_bank0_mask;
374: do_put_mem_long(NEXTRam + addr, l);
1.1.1.2 root 375: }
376:
1.1.1.4 root 377: static void mem_ram_bank0_wput(uaecptr addr, uae_u32 w)
1.1.1.2 root 378: {
1.1.1.4 root 379: addr &= NEXT_ram_bank0_mask;
380: do_put_mem_word(NEXTRam + addr, w);
1.1.1.2 root 381: }
382:
1.1.1.4 root 383: static void mem_ram_bank0_bput(uaecptr addr, uae_u32 b)
1.1.1.2 root 384: {
1.1.1.4 root 385: addr &= NEXT_ram_bank0_mask;
386: NEXTRam[addr] = b;
1.1.1.2 root 387: }
388:
389:
1.1.1.4 root 390: static uae_u32 mem_ram_bank1_lget(uaecptr addr)
1.1.1.2 root 391: {
1.1.1.4 root 392: addr &= NEXT_ram_bank1_mask;
393: return do_get_mem_long(NEXTRam + addr);
1.1.1.2 root 394: }
395:
1.1.1.4 root 396: static uae_u32 mem_ram_bank1_wget(uaecptr addr)
1.1 root 397: {
1.1.1.4 root 398: addr &= NEXT_ram_bank1_mask;
399: return do_get_mem_word(NEXTRam + addr);
1.1 root 400: }
401:
1.1.1.4 root 402: static uae_u32 mem_ram_bank1_bget(uaecptr addr)
1.1 root 403: {
1.1.1.4 root 404: addr &= NEXT_ram_bank1_mask;
405: return NEXTRam[addr];
1.1 root 406: }
407:
1.1.1.4 root 408: static void mem_ram_bank1_lput(uaecptr addr, uae_u32 l)
1.1 root 409: {
1.1.1.4 root 410: addr &= NEXT_ram_bank1_mask;
411: do_put_mem_long(NEXTRam + addr, l);
1.1 root 412: }
413:
1.1.1.4 root 414: static void mem_ram_bank1_wput(uaecptr addr, uae_u32 w)
1.1 root 415: {
1.1.1.4 root 416: addr &= NEXT_ram_bank1_mask;
417: do_put_mem_word(NEXTRam + addr, w);
1.1 root 418: }
419:
1.1.1.4 root 420: static void mem_ram_bank1_bput(uaecptr addr, uae_u32 b)
1.1 root 421: {
1.1.1.4 root 422: addr &= NEXT_ram_bank1_mask;
423: NEXTRam[addr] = b;
1.1 root 424: }
425:
426:
1.1.1.4 root 427: static uae_u32 mem_ram_bank2_lget(uaecptr addr)
1.1 root 428: {
1.1.1.4 root 429: addr &= NEXT_ram_bank2_mask;
430: return do_get_mem_long(NEXTRam + addr);
1.1 root 431: }
432:
1.1.1.4 root 433: static uae_u32 mem_ram_bank2_wget(uaecptr addr)
1.1 root 434: {
1.1.1.4 root 435: addr &= NEXT_ram_bank2_mask;
436: return do_get_mem_word(NEXTRam + addr);
1.1 root 437: }
438:
1.1.1.4 root 439: static uae_u32 mem_ram_bank2_bget(uaecptr addr)
1.1 root 440: {
1.1.1.4 root 441: addr &= NEXT_ram_bank2_mask;
442: return NEXTRam[addr];
1.1 root 443: }
444:
1.1.1.4 root 445: static void mem_ram_bank2_lput(uaecptr addr, uae_u32 l)
1.1 root 446: {
1.1.1.4 root 447: addr &= NEXT_ram_bank2_mask;
448: do_put_mem_long(NEXTRam + addr, l);
1.1 root 449: }
450:
1.1.1.4 root 451: static void mem_ram_bank2_wput(uaecptr addr, uae_u32 w)
1.1 root 452: {
1.1.1.4 root 453: addr &= NEXT_ram_bank2_mask;
454: do_put_mem_word(NEXTRam + addr, w);
1.1 root 455: }
456:
1.1.1.4 root 457: static void mem_ram_bank2_bput(uaecptr addr, uae_u32 b)
1.1 root 458: {
1.1.1.4 root 459: addr &= NEXT_ram_bank2_mask;
460: NEXTRam[addr] = b;
1.1 root 461: }
462:
1.1.1.4 root 463:
464: static uae_u32 mem_ram_bank3_lget(uaecptr addr)
1.1 root 465: {
1.1.1.4 root 466: addr &= NEXT_ram_bank3_mask;
467: return do_get_mem_long(NEXTRam + addr);
1.1 root 468: }
469:
1.1.1.4 root 470: static uae_u32 mem_ram_bank3_wget(uaecptr addr)
1.1 root 471: {
1.1.1.4 root 472: addr &= NEXT_ram_bank3_mask;
473: return do_get_mem_word(NEXTRam + addr);
1.1 root 474: }
475:
1.1.1.4 root 476: static uae_u32 mem_ram_bank3_bget(uaecptr addr)
1.1 root 477: {
1.1.1.4 root 478: addr &= NEXT_ram_bank3_mask;
479: return NEXTRam[addr];
1.1 root 480: }
481:
1.1.1.4 root 482: static void mem_ram_bank3_lput(uaecptr addr, uae_u32 l)
1.1 root 483: {
1.1.1.4 root 484: addr &= NEXT_ram_bank3_mask;
485: do_put_mem_long(NEXTRam + addr, l);
1.1 root 486: }
487:
1.1.1.4 root 488: static void mem_ram_bank3_wput(uaecptr addr, uae_u32 w)
1.1.1.2 root 489: {
1.1.1.4 root 490: addr &= NEXT_ram_bank3_mask;
491: do_put_mem_word(NEXTRam + addr, w);
1.1.1.2 root 492: }
493:
1.1.1.4 root 494: static void mem_ram_bank3_bput(uaecptr addr, uae_u32 b)
1.1.1.2 root 495: {
1.1.1.4 root 496: addr &= NEXT_ram_bank3_mask;
497: NEXTRam[addr] = b;
1.1.1.2 root 498: }
499:
1.1.1.4 root 500: /* **** NEXT RAM empty areas **** */
501:
502: static uae_u32 mem_ram_empty_lget(uaecptr addr)
1.1.1.2 root 503: {
1.1.1.4 root 504: if (illegal_mem)
505: write_log ("Empty mem area lget at %08lx\n", (long)addr);
506:
507: return addr;
1.1.1.2 root 508: }
509:
1.1.1.4 root 510: static uae_u32 mem_ram_empty_wget(uaecptr addr)
1.1.1.2 root 511: {
1.1.1.4 root 512: if (illegal_mem)
513: write_log ("Empty mem area wget at %08lx\n", (long)addr);
514:
515: return addr;
1.1.1.2 root 516: }
517:
1.1.1.4 root 518: static uae_u32 mem_ram_empty_bget(uaecptr addr)
1.1.1.2 root 519: {
1.1.1.4 root 520: if (illegal_mem)
521: write_log ("Empty mem area bget at %08lx\n", (long)addr);
522:
523: return addr;
1.1.1.2 root 524: }
525:
1.1.1.4 root 526: static void mem_ram_empty_lput(uaecptr addr, uae_u32 l)
1.1.1.2 root 527: {
1.1.1.4 root 528: if (illegal_mem)
529: write_log ("Empty mem area lput at %08lx\n", (long)addr);
1.1.1.2 root 530: }
531:
1.1.1.4 root 532: static void mem_ram_empty_wput(uaecptr addr, uae_u32 w)
1.1.1.2 root 533: {
1.1.1.4 root 534: if (illegal_mem)
535: write_log ("Empty mem area wput at %08lx\n", (long)addr);
1.1.1.2 root 536: }
537:
1.1.1.4 root 538: static void mem_ram_empty_bput(uaecptr addr, uae_u32 b)
1.1.1.2 root 539: {
1.1.1.4 root 540: if (illegal_mem)
541: write_log ("Empty mem area bput at %08lx\n", (long)addr);
1.1.1.2 root 542: }
543:
544:
1.1.1.4 root 545: /* **** NEXT VRAM memory for monochrome systems **** */
1.1 root 546:
1.1.1.4 root 547: static uae_u32 mem_video_lget(uaecptr addr)
1.1 root 548: {
1.1.1.4 root 549: addr &= NEXT_VRAM_MASK;
550: return do_get_mem_long(NEXTVideo + addr);
1.1 root 551: }
552:
1.1.1.4 root 553: static uae_u32 mem_video_wget(uaecptr addr)
1.1 root 554: {
1.1.1.4 root 555: addr &= NEXT_VRAM_MASK;
556: return do_get_mem_word(NEXTVideo + addr);
1.1 root 557: }
558:
1.1.1.4 root 559: static uae_u32 mem_video_bget(uaecptr addr)
1.1 root 560: {
1.1.1.4 root 561: addr &= NEXT_VRAM_MASK;
562: return NEXTVideo[addr];
1.1 root 563: }
564:
1.1.1.4 root 565: static void mem_video_lput(uaecptr addr, uae_u32 l)
1.1 root 566: {
1.1.1.4 root 567: addr &= NEXT_VRAM_MASK;
568: do_put_mem_long(NEXTVideo + addr, l);
1.1 root 569: }
570:
1.1.1.4 root 571: static void mem_video_wput(uaecptr addr, uae_u32 w)
1.1 root 572: {
1.1.1.4 root 573: addr &= NEXT_VRAM_MASK;
574: do_put_mem_word(NEXTVideo + addr, w);
1.1 root 575: }
576:
1.1.1.4 root 577: static void mem_video_bput(uaecptr addr, uae_u32 b)
1.1 root 578: {
1.1.1.4 root 579: addr &= NEXT_VRAM_MASK;
580: NEXTVideo[addr] = b;
1.1 root 581: }
582:
1.1.1.4 root 583:
584: /* **** NEXT memory banks with write functions **** */
585:
586: static uae_u8 mwf0[4][4] = { /* AB */
587: { 0, 0, 0, 0 },
588: { 0, 0, 1, 1 },
589: { 0, 1, 1, 2 },
590: { 0, 1, 2, 3 }
591: };
592:
593: static uae_u8 mwf1[4][4] = { /* ceil(A+B) */
594: { 0, 1, 2, 3 },
595: { 1, 2, 3, 3 },
596: { 2, 3, 3, 3 },
597: { 3, 3, 3, 3 }
598: };
599:
600: static uae_u8 mwf2[4][4] = { /* (1-A)B */
601: { 0, 0, 0, 0 },
602: { 1, 1, 0, 0 },
603: { 2, 1, 1, 0 },
604: { 3, 2, 1, 0 }
605: };
606:
607: static uae_u8 mwf3[4][4] = { /* A+B-AB */
608: { 0, 1, 2, 3 },
609: { 1, 2, 2, 3 },
610: { 2, 2, 3, 3 },
611: { 3, 3, 3, 3 }
612: };
613:
614: static uae_u32 memory_write_func(uae_u32 old, uae_u32 new, int function, int size)
1.1 root 615: {
1.1.1.4 root 616: int a,b,i;
617: uae_u32 v=0;
618: #if 0
619: write_log("[MWF] Function%i: size=%i, old=%08X, new=%08X\n",function,size,old,new);
620: #endif
621:
622: switch (function) {
623: case 0:
624: for (i=0; i<(size*4); i++) {
625: a=old>>(i*2)&3;
626: b=new>>(i*2)&3;
627: v|=mwf0[a][b]<<(i*2);
628: }
629: return v;
630: case 1:
631: for (i=0; i<(size*4); i++) {
632: a=old>>(i*2)&3;
633: b=new>>(i*2)&3;
634: v|=mwf1[a][b]<<(i*2);
635: }
636: return v;
637: case 2:
638: for (i=0; i<(size*4); i++) {
639: a=old>>(i*2)&3;
640: b=new>>(i*2)&3;
641: v|=mwf2[a][b]<<(i*2);
642: }
643: return v;
644: case 3:
645: for (i=0; i<(size*4); i++) {
646: a=old>>(i*2)&3;
647: b=new>>(i*2)&3;
648: v|=mwf3[a][b]<<(i*2);
649: }
650: return v;
651:
652: default:
653: write_log("Unknown memory write function!\n");
654: abort();
655: }
1.1 root 656: }
657:
1.1.1.4 root 658: static uae_u32 mem_ram_mwf_lget(uaecptr addr)
1.1 root 659: {
1.1.1.4 root 660: int function = (addr>>26)&0x3;
661: addr = NEXT_RAM_START|(addr&0x03FFFFFF);
662:
663: return function==0?0xFFFFFFFF:0;
1.1 root 664: }
665:
1.1.1.4 root 666: static uae_u32 mem_ram_mwf_wget(uaecptr addr)
1.1 root 667: {
1.1.1.4 root 668: int function = (addr>>26)&0x3;
669: addr = NEXT_RAM_START|(addr&0x03FFFFFF);
670:
671: return function==0?0xFFFF:0;
1.1 root 672: }
673:
1.1.1.4 root 674: static uae_u32 mem_ram_mwf_bget(uaecptr addr)
1.1 root 675: {
1.1.1.4 root 676: int function = (addr>>26)&0x3;
677: addr = NEXT_RAM_START|(addr&0x03FFFFFF);
678:
679: return function==0?0xFF:0;
1.1 root 680: }
681:
1.1.1.4 root 682: static void mem_ram_mwf_lput(uaecptr addr, uae_u32 l)
1.1 root 683: {
1.1.1.4 root 684: int function = (addr>>26)&0x3;
685: addr = NEXT_RAM_START|(addr&0x03FFFFFF);
686:
687: uae_u32 old = longget(addr);
688: uae_u32 val = memory_write_func(old, l, function, 4);
689:
690: longput(addr, val);
1.1 root 691: }
692:
1.1.1.4 root 693: static void mem_ram_mwf_wput(uaecptr addr, uae_u32 w)
1.1 root 694: {
1.1.1.4 root 695: int function = (addr>>26)&0x3;
696: addr = NEXT_RAM_START|(addr&0x03FFFFFF);
697:
698: uae_u32 old = wordget(addr);
699: uae_u32 val = memory_write_func(old, w, function, 2);
700:
701: wordput(addr, val);
1.1 root 702: }
703:
1.1.1.4 root 704: static void mem_ram_mwf_bput(uaecptr addr, uae_u32 b)
1.1 root 705: {
1.1.1.4 root 706: int function = (addr>>26)&0x3;
707: addr = NEXT_RAM_START|(addr&0x03FFFFFF);
708:
709: uae_u32 old = byteget(addr);
710: uae_u32 val = memory_write_func(old, b, function, 1);
711:
712: byteput(addr, val);
1.1 root 713: }
714:
1.1.1.4 root 715:
716: static uae_u32 mem_video_mwf_lget(uaecptr addr)
1.1 root 717: {
1.1.1.4 root 718: int function = (addr>>24)&0x3;
719: addr = NEXT_VRAM_START|(addr&NEXT_VRAM_MASK);
720:
721: return function==0?0xFFFFFFFF:0;
1.1 root 722: }
723:
1.1.1.4 root 724: static uae_u32 mem_video_mwf_wget(uaecptr addr)
1.1 root 725: {
1.1.1.4 root 726: int function = (addr>>24)&0x3;
727: addr = NEXT_VRAM_START|(addr&NEXT_VRAM_MASK);
728:
729: return function==0?0xFFFF:0;
1.1 root 730: }
731:
1.1.1.4 root 732: static uae_u32 mem_video_mwf_bget(uaecptr addr)
1.1 root 733: {
1.1.1.4 root 734: int function = (addr>>24)&0x3;
735: addr = NEXT_VRAM_START|(addr&NEXT_VRAM_MASK);
736:
737: return function==0?0xFF:0;
1.1 root 738: }
739:
1.1.1.4 root 740: static void mem_video_mwf_lput(uaecptr addr, uae_u32 l)
1.1 root 741: {
1.1.1.4 root 742: int function = (addr>>24)&0x3;
743: addr = NEXT_VRAM_START|(addr&NEXT_VRAM_MASK);
744:
745: uae_u32 old = longget(addr);
746: uae_u32 val = memory_write_func(old, l, function, 4);
747:
748: longput(addr, val);
1.1 root 749: }
750:
1.1.1.4 root 751: static void mem_video_mwf_wput(uaecptr addr, uae_u32 w)
1.1 root 752: {
1.1.1.4 root 753: int function = (addr>>24)&0x3;
754: addr = NEXT_VRAM_START|(addr&NEXT_VRAM_MASK);
755:
756: uae_u32 old = wordget(addr);
757: uae_u32 val = memory_write_func(old, w, function, 2);
758:
759: wordput(addr, val);
1.1 root 760: }
761:
1.1.1.4 root 762: static void mem_video_mwf_bput(uaecptr addr, uae_u32 b)
1.1 root 763: {
1.1.1.4 root 764: int function = (addr>>24)&0x3;
765: addr = NEXT_VRAM_START|(addr&NEXT_VRAM_MASK);
766:
767: uae_u32 old = byteget(addr);
768: uae_u32 val = memory_write_func(old, b, function, 1);
769:
770: byteput(addr, val);
1.1 root 771: }
772:
1.1.1.4 root 773:
774: /* **** NEXT VRAM memory for color systems **** */
775:
776: static uae_u32 mem_color_video_lget(uaecptr addr)
1.1 root 777: {
1.1.1.4 root 778: addr &= NEXT_VRAM_COLOR_MASK;
779: return do_get_mem_long(NEXTColorVideo + addr);
1.1 root 780: }
781:
1.1.1.4 root 782: static uae_u32 mem_color_video_wget(uaecptr addr)
1.1 root 783: {
1.1.1.4 root 784: addr &= NEXT_VRAM_COLOR_MASK;
785: return do_get_mem_word(NEXTColorVideo + addr);
1.1 root 786: }
787:
1.1.1.4 root 788: static uae_u32 mem_color_video_bget(uaecptr addr)
1.1 root 789: {
1.1.1.4 root 790: addr &= NEXT_VRAM_COLOR_MASK;
791: return NEXTColorVideo[addr];
1.1 root 792: }
793:
1.1.1.4 root 794: static void mem_color_video_lput(uaecptr addr, uae_u32 l)
1.1 root 795: {
1.1.1.4 root 796: addr &= NEXT_VRAM_COLOR_MASK;
797: do_put_mem_long(NEXTColorVideo + addr, l);
1.1 root 798: }
799:
1.1.1.4 root 800: static void mem_color_video_wput(uaecptr addr, uae_u32 w)
1.1 root 801: {
1.1.1.4 root 802: addr &= NEXT_VRAM_COLOR_MASK;
803: do_put_mem_word(NEXTColorVideo + addr, w);
1.1 root 804: }
805:
1.1.1.4 root 806: static void mem_color_video_bput(uaecptr addr, uae_u32 b)
807: {
808: addr &= NEXT_VRAM_COLOR_MASK;
809: NEXTColorVideo[addr] = b;
810: }
1.1 root 811:
812:
1.1.1.4 root 813: /* Hardware IO memory */
814: /* --> see ioMem.c */
815: uae_u8 *IOmemory;
1.1.1.2 root 816:
1.1 root 817:
1.1.1.4 root 818: /* **** NEXT BMAP memory **** */
1.1 root 819:
1.1.1.4 root 820: static uae_u32 mem_bmap_lget(uaecptr addr)
1.1 root 821: {
1.1.1.4 root 822: if ((addr&NEXT_BMAP_MASK)>NEXT_BMAP_SIZE) {
823: write_log ("bmap bus error at %08lx PC=%08x\n", (long)addr,m68k_getpc());
824: M68000_BusError(addr, 0);
825: return 0;
826: }
1.1.1.5 ! root 827: //write_log ("bmap lget at %08lx PC=%08x\n", (long)addr,m68k_getpc());
1.1.1.4 root 828: addr &= NEXT_BMAP_MASK;
829: return bmap_lget(addr);
1.1 root 830: }
831:
1.1.1.4 root 832: static uae_u32 mem_bmap_wget(uaecptr addr)
1.1 root 833: {
1.1.1.4 root 834: if ((addr&NEXT_BMAP_MASK)>NEXT_BMAP_SIZE) {
835: write_log ("bmap bus error at %08lx PC=%08x\n", (long)addr,m68k_getpc());
836: M68000_BusError(addr, 0);
837: return 0;
838: }
1.1.1.5 ! root 839: //write_log ("bmap wget at %08lx PC=%08x\n", (long)addr,m68k_getpc());
1.1.1.4 root 840: addr &= NEXT_BMAP_MASK;
841: return bmap_wget(addr);
1.1 root 842: }
843:
1.1.1.4 root 844: static uae_u32 mem_bmap_bget(uaecptr addr)
1.1 root 845: {
1.1.1.4 root 846: if ((addr&NEXT_BMAP_MASK)>NEXT_BMAP_SIZE) {
847: write_log ("bmap bus error at %08lx PC=%08x\n", (long)addr,m68k_getpc());
848: M68000_BusError(addr, 0);
849: return 0;
850: }
1.1.1.5 ! root 851: //write_log ("bmap bget at %08lx PC=%08x\n", (long)addr,m68k_getpc());
1.1.1.4 root 852: addr &= NEXT_BMAP_MASK;
853: return bmap_bget(addr);
1.1 root 854: }
855:
1.1.1.4 root 856: static void mem_bmap_lput(uaecptr addr, uae_u32 l)
1.1 root 857: {
1.1.1.4 root 858: if ((addr&NEXT_BMAP_MASK)>NEXT_BMAP_SIZE) {
859: write_log ("bmap bus error at %08lx PC=%08x\n", (long)addr,m68k_getpc());
860: M68000_BusError(addr, 0);
861: }
1.1.1.5 ! root 862: //write_log ("bmap lput at %08lx val=%x PC=%08x\n", (long)addr,l,m68k_getpc());
1.1.1.4 root 863: addr &= NEXT_BMAP_MASK;
864: bmap_lput(addr, l);
1.1 root 865: }
866:
1.1.1.4 root 867: static void mem_bmap_wput(uaecptr addr, uae_u32 w)
1.1 root 868: {
1.1.1.4 root 869: if ((addr&NEXT_BMAP_MASK)>NEXT_BMAP_SIZE) {
870: write_log ("bmap bus error at %08lx PC=%08x\n", (long)addr,m68k_getpc());
871: M68000_BusError(addr, 0);
872: }
1.1.1.5 ! root 873: //write_log ("bmap wput at %08lx val=%x PC=%08x\n", (long)addr,w,m68k_getpc());
1.1.1.4 root 874: addr &= NEXT_BMAP_MASK;
875: bmap_wput(addr, w);
1.1 root 876: }
877:
1.1.1.4 root 878: static void mem_bmap_bput(uaecptr addr, uae_u32 b)
1.1 root 879: {
1.1.1.4 root 880: if ((addr&NEXT_BMAP_MASK)>NEXT_BMAP_SIZE) {
881: write_log ("bmap bus error at %08lx PC=%08x\n", (long)addr,m68k_getpc());
882: M68000_BusError(addr, 0);
883: }
1.1.1.5 ! root 884: //write_log ("bmap bput at %08lx val=%x PC=%08x\n", (long)addr,b,m68k_getpc());
1.1.1.4 root 885: addr &= NEXT_BMAP_MASK;
886: bmap_bput(addr, b);
1.1 root 887: }
888:
889:
890:
1.1.1.4 root 891: /* **** Address banks **** */
1.1 root 892:
1.1.1.4 root 893: static addrbank dummy_bank =
1.1 root 894: {
1.1.1.4 root 895: dummy_lget, dummy_wget, dummy_bget,
896: dummy_lput, dummy_wput, dummy_bput,
897: dummy_lget, dummy_wget, ABFLAG_NONE
898: };
1.1 root 899:
1.1.1.4 root 900: static addrbank BusErrMem_bank =
1.1 root 901: {
1.1.1.4 root 902: BusErrMem_lget, BusErrMem_wget, BusErrMem_bget,
903: BusErrMem_lput, BusErrMem_wput, BusErrMem_bput,
904: BusErrMem_lget, BusErrMem_wget, ABFLAG_NONE
905: };
1.1 root 906:
1.1.1.4 root 907: static addrbank ROM_bank =
908: {
909: mem_rom_lget, mem_rom_wget, mem_rom_bget,
910: mem_rom_lput, mem_rom_wput, mem_rom_bput,
911: mem_rom_lget, mem_rom_wget, ABFLAG_ROM
912: };
1.1 root 913:
1.1.1.4 root 914: static addrbank RAM_bank0 =
915: {
916: mem_ram_bank0_lget, mem_ram_bank0_wget, mem_ram_bank0_bget,
917: mem_ram_bank0_lput, mem_ram_bank0_wput, mem_ram_bank0_bput,
918: mem_ram_bank0_lget, mem_ram_bank0_wget, ABFLAG_RAM
919:
920: };
1.1 root 921:
1.1.1.4 root 922: static addrbank RAM_bank1 =
923: {
924: mem_ram_bank1_lget, mem_ram_bank1_wget, mem_ram_bank1_bget,
925: mem_ram_bank1_lput, mem_ram_bank1_wput, mem_ram_bank1_bput,
926: mem_ram_bank1_lget, mem_ram_bank1_wget, ABFLAG_RAM
927:
928: };
1.1 root 929:
1.1.1.4 root 930: static addrbank RAM_bank2 =
1.1 root 931: {
1.1.1.4 root 932: mem_ram_bank2_lget, mem_ram_bank2_wget, mem_ram_bank2_bget,
933: mem_ram_bank2_lput, mem_ram_bank2_wput, mem_ram_bank2_bput,
934: mem_ram_bank2_lget, mem_ram_bank2_wget, ABFLAG_RAM
935:
1.1 root 936: };
937:
1.1.1.4 root 938: static addrbank RAM_bank3 =
1.1 root 939: {
1.1.1.4 root 940: mem_ram_bank3_lget, mem_ram_bank3_wget, mem_ram_bank3_bget,
941: mem_ram_bank3_lput, mem_ram_bank3_wput, mem_ram_bank3_bput,
942: mem_ram_bank3_lget, mem_ram_bank3_wget, ABFLAG_RAM
943:
1.1 root 944: };
945:
1.1.1.4 root 946: static addrbank RAM_empty_bank =
1.1 root 947: {
1.1.1.4 root 948: mem_ram_empty_lget, mem_ram_empty_wget, mem_ram_empty_bget,
949: mem_ram_empty_lput, mem_ram_empty_wput, mem_ram_empty_bput,
950: mem_ram_empty_lget, mem_ram_empty_wget, ABFLAG_RAM
951: };
1.1 root 952:
1.1.1.4 root 953: static addrbank RAM_mwf_bank =
954: {
955: mem_ram_mwf_lget, mem_ram_mwf_wget, mem_ram_mwf_bget,
956: mem_ram_mwf_lput, mem_ram_mwf_wput, mem_ram_mwf_bput,
957: mem_ram_mwf_lget, mem_ram_mwf_wget, ABFLAG_RAM
1.1 root 958: };
959:
1.1.1.4 root 960: static addrbank VRAM_bank =
1.1.1.2 root 961: {
1.1.1.4 root 962: mem_video_lget, mem_video_wget, mem_video_bget,
963: mem_video_lput, mem_video_wput, mem_video_bput,
964: mem_video_lget, mem_video_wget, ABFLAG_RAM
1.1.1.2 root 965: };
966:
1.1.1.4 root 967: static addrbank VRAM_mwf_bank =
1.1 root 968: {
1.1.1.4 root 969: mem_video_mwf_lget, mem_video_mwf_wget, mem_video_mwf_bget,
970: mem_video_mwf_lput, mem_video_mwf_wput, mem_video_mwf_bput,
971: mem_video_mwf_lget, mem_video_mwf_wget, ABFLAG_RAM
1.1 root 972: };
973:
1.1.1.4 root 974: static addrbank VRAM_color_bank =
1.1 root 975: {
1.1.1.4 root 976: mem_color_video_lget, mem_color_video_wget, mem_color_video_bget,
977: mem_color_video_lput, mem_color_video_wput, mem_color_video_bput,
978: mem_color_video_lget, mem_color_video_wget, ABFLAG_RAM
1.1 root 979: };
980:
1.1.1.4 root 981: static addrbank IO_bank =
1.1 root 982: {
1.1.1.4 root 983: IoMem_lget, IoMem_wget, IoMem_bget,
984: IoMem_lput, IoMem_wput, IoMem_bput,
985: IoMem_lget, IoMem_wget, ABFLAG_IO
1.1 root 986: };
987:
1.1.1.4 root 988: static addrbank BMAP_bank =
1.1.1.2 root 989: {
1.1.1.4 root 990: mem_bmap_lget, mem_bmap_wget, mem_bmap_bget,
991: mem_bmap_lput, mem_bmap_wput, mem_bmap_bput,
992: mem_bmap_lget, mem_bmap_wget, ABFLAG_IO
1.1.1.2 root 993: };
994:
1.1.1.4 root 995: static addrbank TMC_bank =
1.1 root 996: {
1.1.1.4 root 997: tmc_lget, tmc_wget, tmc_bget,
998: tmc_lput, tmc_wput, tmc_bput,
999: tmc_lget, tmc_wget, ABFLAG_IO
1.1 root 1000: };
1001:
1.1.1.4 root 1002: static addrbank NBIC_bank =
1.1 root 1003: {
1.1.1.4 root 1004: nbic_reg_lget, nbic_reg_wget, nbic_reg_bget,
1005: nbic_reg_lput, nbic_reg_wput, nbic_reg_bput,
1006: nbic_reg_lget, nbic_reg_wget, ABFLAG_IO
1.1 root 1007: };
1008:
1.1.1.4 root 1009: static addrbank NEXTBUS_slot_bank =
1.1 root 1010: {
1.1.1.4 root 1011: nextbus_slot_lget, nextbus_slot_wget, nextbus_slot_bget,
1012: nextbus_slot_lput, nextbus_slot_wput, nextbus_slot_bput,
1013: nextbus_slot_lget, nextbus_slot_wget, ABFLAG_IO
1.1 root 1014: };
1015:
1.1.1.4 root 1016: static addrbank NEXTBUS_board_bank =
1.1 root 1017: {
1.1.1.4 root 1018: nextbus_board_lget, nextbus_board_wget, nextbus_board_bget,
1019: nextbus_board_lput, nextbus_board_wput, nextbus_board_bput,
1020: nextbus_board_lget, nextbus_board_wget, ABFLAG_IO
1.1 root 1021: };
1022:
1023:
1024:
1025: static void init_mem_banks (void)
1026: {
1.1.1.4 root 1027: int i;
1028: for (i = 0; i < 65536; i++)
1029: put_mem_bank (i<<16, &BusErrMem_bank);
1.1 root 1030: }
1031:
1032:
1033: /*
1034: * Initialize the memory banks
1035: */
1.1.1.2 root 1036: const char* memory_init(int *nNewNEXTMemSize)
1.1 root 1037: {
1.1.1.4 root 1038: int i;
1039: uae_u32 bankstart[4];
1040:
1041: /* Set machine dependent variables */
1042: if (ConfigureParams.System.bTurbo) {
1043: NEXT_ram_bank_size = NEXT_RAM_BANK_MAX_T;
1044: NEXT_ram_bank_mask = NEXT_RAM_BANK_SEL_T;
1045: } else if (ConfigureParams.System.bColor) {
1046: NEXT_ram_bank_size = NEXT_RAM_BANK_MAX_C;
1047: NEXT_ram_bank_mask = NEXT_RAM_BANK_SEL_C;
1.1.1.3 root 1048: } else {
1.1.1.4 root 1049: NEXT_ram_bank_size = NEXT_RAM_BANK_MAX;
1050: NEXT_ram_bank_mask = NEXT_RAM_BANK_SEL;
1051: }
1052:
1053: write_log("Memory init: Memory size: %iMB\n", Configuration_CheckMemory(nNewNEXTMemSize));
1054:
1055: /* Convert values from MB to byte */
1056: for (i=0; i<N_BANKS; i++) {
1057: bankstart[i] = NEXT_RAM_START + (NEXT_ram_bank_size * i);
1058: }
1059:
1060: /* Fill every 65536 bank with dummy */
1061: init_mem_banks();
1062:
1063: /* Map ROM */
1064: map_banks(&ROM_bank, NEXT_EPROM_START >> 16, NEXT_EPROM_SIZE>>16);
1065: write_log("Mapping ROM at $%08x: %ikB\n", NEXT_EPROM_START, NEXT_EPROM_SIZE/1024);
1066: if (ConfigureParams.System.nMachineType != NEXT_CUBE030) {
1067: map_banks(&ROM_bank, NEXT_EPROM_BMAP_START >> 16, NEXT_EPROM_SIZE>>16);
1068: write_log("Mapping ROM trough BMAP at $%08x: %ikB\n", NEXT_EPROM_BMAP_START, NEXT_EPROM_SIZE/1024);
1069: }
1070:
1071: /* Map main memory */
1072: if (nNewNEXTMemSize[0]) {
1073: NEXT_ram_bank0_mask = NEXT_ram_bank_mask|((nNewNEXTMemSize[0]<<20)-1);
1074: map_banks(&RAM_bank0, bankstart[0]>>16, NEXT_ram_bank_size >> 16);
1075: write_log("Mapping main memory bank0 at $%08x: %iMB\n", bankstart[0], nNewNEXTMemSize[0]);
1076: } else {
1077: NEXT_ram_bank0_mask = 0;
1078: map_banks(&RAM_empty_bank, bankstart[0]>>16, NEXT_ram_bank_size >> 16);
1079: write_log("Mapping main memory bank0 at $%08x: empty\n", bankstart[0]);
1080: }
1081:
1082: if (nNewNEXTMemSize[1]) {
1083: NEXT_ram_bank1_mask = NEXT_ram_bank_mask|((nNewNEXTMemSize[1]<<20)-1);
1084: map_banks(&RAM_bank1, bankstart[1]>>16, NEXT_ram_bank_size >> 16);
1085: write_log("Mapping main memory bank1 at $%08x: %iMB\n", bankstart[1], nNewNEXTMemSize[1]);
1086: } else {
1087: NEXT_ram_bank1_mask = 0;
1088: map_banks(&RAM_empty_bank, bankstart[1]>>16, NEXT_ram_bank_size >> 16);
1089: write_log("Mapping main memory bank1 at $%08x: empty\n", bankstart[1]);
1090: }
1091:
1092: if (nNewNEXTMemSize[2]) {
1093: NEXT_ram_bank2_mask = NEXT_ram_bank_mask|((nNewNEXTMemSize[2]<<20)-1);
1094: map_banks(&RAM_bank2, bankstart[2]>>16, NEXT_ram_bank_size >> 16);
1095: write_log("Mapping main memory bank2 at $%08x: %iMB\n", bankstart[2], nNewNEXTMemSize[2]);
1096: } else {
1097: NEXT_ram_bank2_mask = 0;
1098: map_banks(&RAM_empty_bank, bankstart[2]>>16, NEXT_ram_bank_size >> 16);
1099: write_log("Mapping main memory bank2 at $%08x: empty\n", bankstart[2]);
1100: }
1101:
1102: if (nNewNEXTMemSize[3]) {
1103: NEXT_ram_bank3_mask = NEXT_ram_bank_mask|((nNewNEXTMemSize[3]<<20)-1);
1104: map_banks(&RAM_bank3, bankstart[3]>>16, NEXT_ram_bank_size >> 16);
1105: write_log("Mapping main memory bank3 at $%08x: %iMB\n", bankstart[3], nNewNEXTMemSize[3]);
1106: } else {
1107: NEXT_ram_bank3_mask = 0;
1108: map_banks(&RAM_empty_bank, bankstart[3]>>16, NEXT_ram_bank_size >> 16);
1109: write_log("Mapping main memory bank3 at $%08x: empty\n", bankstart[3]);
1110: }
1111:
1112: /* Map mirrors of main memory for memory write functions */
1113: if (!ConfigureParams.System.bColor && !ConfigureParams.System.bTurbo) {
1114: map_banks(&RAM_mwf_bank, NEXT_RAM_MWF0_START>>16, (NEXT_RAM_BANK_MAX*N_BANKS) >> 16);
1115: map_banks(&RAM_mwf_bank, NEXT_RAM_MWF1_START>>16, (NEXT_RAM_BANK_MAX*N_BANKS) >> 16);
1116: map_banks(&RAM_mwf_bank, NEXT_RAM_MWF2_START>>16, (NEXT_RAM_BANK_MAX*N_BANKS) >> 16);
1117: map_banks(&RAM_mwf_bank, NEXT_RAM_MWF3_START>>16, (NEXT_RAM_BANK_MAX*N_BANKS) >> 16);
1118: write_log("Mapping mirrors of main memory for memory write functions:\n");
1119: for (i = 0; i<4; i++)
1120: write_log("Function%i at $%08X\n",i,0x10000000+0x04000000*i);
1121: }
1122:
1123: /* Map video memory */
1124: if (ConfigureParams.System.bTurbo && ConfigureParams.System.bColor) {
1125: map_banks(&VRAM_color_bank, NEXT_VRAM_TURBO_START>>16, NEXT_VRAM_COLOR_SIZE >> 16);
1126: write_log("Mapping video memory at $%08x: %ikB\n", NEXT_VRAM_TURBO_START, NEXT_VRAM_COLOR_SIZE/1024);
1127: } else if (ConfigureParams.System.bTurbo) {
1128: map_banks(&VRAM_bank, NEXT_VRAM_TURBO_START>>16, NEXT_VRAM_SIZE >> 16);
1129: write_log("Mapping video memory at $%08x: %ikB\n", NEXT_VRAM_TURBO_START, NEXT_VRAM_SIZE/1024);
1130: } else if (ConfigureParams.System.bColor) {
1131: map_banks(&VRAM_color_bank, NEXT_VRAM_COLOR_START>>16, NEXT_VRAM_COLOR_SIZE >> 16);
1132: write_log("Mapping video memory at $%08x: %ikB\n", NEXT_VRAM_COLOR_START, NEXT_VRAM_COLOR_SIZE/1024);
1133: } else {
1134: map_banks(&VRAM_bank, NEXT_VRAM_START>>16, NEXT_VRAM_SIZE >> 16);
1135: write_log("Mapping video memory at $%08x: %ikB\n", NEXT_VRAM_START, NEXT_VRAM_SIZE/1024);
1136:
1137: map_banks(&VRAM_mwf_bank, NEXT_VRAM_MWF0_START>>16, NEXT_VRAM_SIZE >> 16);
1138: map_banks(&VRAM_mwf_bank, NEXT_VRAM_MWF1_START>>16, NEXT_VRAM_SIZE >> 16);
1139: map_banks(&VRAM_mwf_bank, NEXT_VRAM_MWF2_START>>16, NEXT_VRAM_SIZE >> 16);
1140: map_banks(&VRAM_mwf_bank, NEXT_VRAM_MWF3_START>>16, NEXT_VRAM_SIZE >> 16);
1141: write_log("Mapping mirrors of video memory for memory write functions:\n");
1142: for (i = 0; i<4; i++)
1143: write_log("Function%i at $%08X\n",i,0x0C000000+0x01000000*i);
1144: }
1145:
1146: /* Map device space */
1147: map_banks(&IO_bank, NEXT_IO_START >> 16, NEXT_IO_SIZE>>16);
1148: write_log("Mapping device space at $%08X\n", NEXT_IO_START);
1149:
1150: if (ConfigureParams.System.nMachineType != NEXT_CUBE030) {
1151: map_banks(&IO_bank, NEXT_IO_BMAP_START >> 16, NEXT_IO_SIZE>>16);
1152: if (!ConfigureParams.System.bTurbo) {
1153: map_banks(&BMAP_bank, NEXT_BMAP_START >> 16, NEXT_BMAP_MAP_SIZE>>16);
1154: map_banks(&BMAP_bank, (0x80000000|NEXT_BMAP_START) >> 16, NEXT_BMAP_MAP_SIZE>>16);
1155: write_log("Mapping BMAP device space at $%08X\n", NEXT_IO_BMAP_START);
1156: } else {
1157: write_log("Mapping device space at $%08X\n", NEXT_IO_BMAP_START);
1158: }
1159: }
1.1.1.5 ! root 1160: bmap_init();
1.1.1.4 root 1161:
1162: if (ConfigureParams.System.bTurbo) {
1163: map_banks(&TMC_bank, NEXT_IO_TMC_START >> 16, NEXT_IO_SIZE>>16);
1164: write_log("Mapping TMC device space at $%08X\n", NEXT_IO_TMC_START);
1165:
1166: if (ConfigureParams.System.nCpuFreq==40) {
1167: map_banks(&dummy_bank, NEXT_CACHE_START>>16, NEXT_CACHE_SIZE>>16);
1168: write_log("Mapping cache memory at $%08x: %ikB\n", NEXT_CACHE_START, NEXT_CACHE_SIZE/1024);
1169: map_banks(&dummy_bank, NEXT_CACHE_TAG_START>>16, NEXT_CACHE_TAG_SIZE>>16);
1170: write_log("Mapping cache tag memory at $%08x: %ikB\n", NEXT_CACHE_TAG_START, NEXT_CACHE_TAG_SIZE/1024);
1171: }
1.1.1.3 root 1172: }
1173:
1.1.1.4 root 1174: /* Map NBIC and board spaces via NextBus */
1175: if (ConfigureParams.System.nMachineType!=NEXT_STATION && ConfigureParams.System.bNBIC) {
1176: if (!ConfigureParams.System.bTurbo) {
1177: map_banks(&NBIC_bank, NEXT_NBIC_START>>16, NEXT_NBIC_MAP_SIZE>>16);
1178: write_log("Mapping NextBus interface chip at $%08x\n", NEXT_NBIC_START);
1179: }
1180: for (i = 2; i < 8; i++) {
1181: if (i==8 && ConfigureParams.System.nMachineType!=NEXT_CUBE030 && !ConfigureParams.System.bTurbo) {
1182: /* FIXME: conflict with BMAP. Implement: only SCR2 ROM_OVERLAY enables NBIC */
1183: continue;
1184: }
1185: map_banks(&NEXTBUS_board_bank, NEXTBUS_BOARD_START(i)>>16, NEXTBUS_BOARD_SIZE>>16);
1186: write_log("Mapping NextBus board memory for slot %i at $%08x\n", i, NEXTBUS_BOARD_START(i));
1187: }
1188: for (i = 0; i < 16; i++) {
1189: map_banks(&NEXTBUS_slot_bank, NEXTBUS_SLOT_START(i)>>16, NEXTBUS_SLOT_SIZE>>16);
1190: }
1191: write_log("Mapping NextBus slot memory at $%08x\n", NEXTBUS_SLOT_START(i));
1192: }
1.1.1.5 ! root 1193: nextbus_init();
1.1 root 1194:
1195: ROMmemory=NEXTRom;
1196: IOmemory=NEXTIo;
1.1.1.4 root 1197:
1.1 root 1198: {
1199: FILE* fin;
1200: int ret;
1.1.1.4 root 1201: /* Loading ROM depending on emulated system */
1202: if(ConfigureParams.System.nMachineType == NEXT_CUBE030)
1203: fin=fopen(ConfigureParams.Rom.szRom030FileName,"rb");
1204: else if(ConfigureParams.System.bTurbo == true)
1205: fin=fopen(ConfigureParams.Rom.szRomTurboFileName,"rb");
1206: else
1207: fin=fopen(ConfigureParams.Rom.szRom040FileName, "rb");
1208:
1209: if (fin==NULL) {
1210: return "Cannot open ROM file";
1211: }
1212:
1.1 root 1213: ret=fread(ROMmemory,1,0x20000,fin);
1.1.1.4 root 1214:
1.1 root 1215: write_log("Read ROM %d\n",ret);
1216: fclose(fin);
1217: }
1218:
1219: {
1220: int i;
1.1.1.4 root 1221: for (i=0;i<sizeof(NEXTVideo);i++) NEXTVideo[i]=0;
1222: for (i=0;i<sizeof(NEXTRam);i++) NEXTRam[i]=0;
1223: for (i=0;i<sizeof(NEXTIo);i++) NEXTIo[i]=0;
1.1 root 1224: }
1.1.1.4 root 1225:
1226: IoMem_Init();
1227:
1.1.1.2 root 1228: return NULL;
1.1 root 1229: }
1230:
1231:
1232: /*
1233: * Uninitialize the memory banks.
1234: */
1235: void memory_uninit (void)
1236: {
1237: }
1238:
1239:
1240: void map_banks (addrbank *bank, int start, int size)
1241: {
1.1.1.4 root 1242: int bnr;
1243:
1.1 root 1244: for (bnr = start; bnr < start + size; bnr++)
1.1.1.4 root 1245: put_mem_bank (bnr << 16, bank);
1.1 root 1246: return;
1247: }
1248:
1249: void memory_hardreset (void)
1250: {
1.1.1.2 root 1251: }
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