--- previous/src/cpu/newcpu.c 2018/04/24 19:31:50 1.1.1.5 +++ previous/src/cpu/newcpu.c 2018/04/24 19:33:39 1.1.1.6 @@ -28,16 +28,16 @@ #endif #include "main.h" #include "dsp.h" -#include "dimension.h" +#include "dimension.hpp" #include "reset.h" #include "cycInt.h" #include "dialog.h" #include "screen.h" #include "video.h" -#include "options.h" #include "log.h" #include "debugui.h" #include "debugcpu.h" +#include "sysReg.h" /* Opcode of faulting instruction */ @@ -188,28 +188,6 @@ void set_cpu_caches (bool flush) dcaches030[(regs.caar >> 4) & (CACHELINES030 - 1)].valid[(regs.caar >> 2) & 3] = 0; regs.cacr &= ~0x400; } - } else if (currprefs.cpu_model == 68040) { - if(ConfigureParams.System.bRealtime) { -#if 0 /* FIXME */ - if(regs.cacr & 0x8000) { - flush_icache(0, -1); - x_prefetch = getc_iword_mmu040; - x_get_ilong = getc_ilong_mmu040; - x_get_iword = getc_iword_mmu040; - x_get_ibyte = getc_ibyte_mmu040; - x_next_iword = nextc_iword_mmu040; - x_next_ilong = nextc_ilong_mmu040; - } else -#endif - { - x_prefetch = get_iword_mmu040; - x_get_ilong = get_ilong_mmu040; - x_get_iword = get_iword_mmu040; - x_get_ibyte = get_ibyte_mmu040; - x_next_iword = next_iword_mmu040; - x_next_ilong = next_ilong_mmu040; - } - } } } @@ -283,11 +261,9 @@ void build_cpufunctbl (void) } write_log ("Building CPU, %d opcodes (%d %d)\n", opcnt, lvl, currprefs.cpu_compatible ? 1 : 0); - write_log ("CPU=%d, MMU=%d, FPU=%d ($%02x), JIT%s=%d, realtime=%d\n", + write_log ("CPU=%d, MMU=%d, FPU=%d ($%02x)\n", currprefs.cpu_model, currprefs.mmu_model, - currprefs.fpu_model, currprefs.fpu_revision, - currprefs.cachesize ? (currprefs.compfpu ? "=CPU/FPU" : "=CPU") : "", - currprefs.cachesize, ConfigureParams.System.bRealtime); + currprefs.fpu_model, currprefs.fpu_revision); set_cpu_caches (0); if (currprefs.mmu_model) { if (currprefs.cpu_model >= 68040) { @@ -588,6 +564,20 @@ static uaecptr ShowEA (void *f, uaecptr return pc; } +static void activate_trace(void) +{ + unset_special (SPCFLAG_TRACE); + set_special (SPCFLAG_DOTRACE); +} + +void check_t0_trace(void) +{ + if (regs.t0 && currprefs.cpu_model >= 68020) { + unset_special (SPCFLAG_TRACE); + set_special (SPCFLAG_DOTRACE); + } +} + void REGPARAM2 MakeSR (void) { regs.sr = ((regs.t1 << 15) | (regs.t0 << 14) @@ -597,10 +587,12 @@ void REGPARAM2 MakeSR (void) | GET_CFLG ()); } -void REGPARAM2 MakeFromSR (void) +static void MakeFromSR_x(int t0trace) { int oldm = regs.m; int olds = regs.s; + int oldt0 = regs.t0; + int oldt1 = regs.t1; SET_XFLG ((regs.sr >> 4) & 1); SET_NFLG ((regs.sr >> 3) & 1); @@ -655,12 +647,29 @@ void REGPARAM2 MakeFromSR (void) mmu_set_super (regs.s != 0); doint (); - if (regs.t1 || regs.t0) + if (regs.t1 || regs.t0) { set_special (SPCFLAG_TRACE); - else + } else { /* Keep SPCFLAG_DOTRACE, we still want a trace exception for SR-modifying instructions (including STOP). */ unset_special (SPCFLAG_TRACE); + } + // Stop SR-modification does not generate T0 + // If this SR modification set Tx bit, no trace until next instruction. + if ((oldt0 && t0trace && currprefs.cpu_model >= 68020) || oldt1) { + // Always trace if Tx bits were already set, even if this SR modification cleared them. + activate_trace(); + } +} + +void REGPARAM2 MakeFromSR_T0(void) +{ + MakeFromSR_x(1); +} +void REGPARAM2 MakeFromSR(void) +{ + MakeFromSR_x(0); + } static void exception_check_trace (int nr) @@ -846,7 +855,6 @@ static void Exception_build_stack_frame x_put_word (m68k_areg (regs, 7), regs.sr); } - // 68030 MMU static void Exception_mmu030 (int nr, uaecptr oldpc) { @@ -1005,6 +1013,15 @@ static void ExceptionX (int nr, uaecptr Exception_mmu (nr, m68k_getpc ()); } +void REGPARAM2 Exception_cpu(int nr) +{ + bool t0 = currprefs.cpu_model >= 68020 && regs.t0; + ExceptionX (nr, -1); + // check T0 trace + if (t0) { + activate_trace(); + } +} void REGPARAM2 Exception (int nr) { ExceptionX (nr, -1); @@ -1161,40 +1178,15 @@ void mmu_op (uae_u32 opcode, uae_u32 ext #endif -static uaecptr last_trace_ad = 0; - static void do_trace (void) { if (regs.t0 && currprefs.cpu_model >= 68020) { - uae_u16 opcode; - /* should also include TRAP, CHK, SR modification FPcc */ - /* probably never used so why bother */ - /* We can afford this to be inefficient... */ - m68k_setpc (m68k_getpc ()); - opcode = x_get_word (regs.pc); - if (opcode == 0x4e73 /* RTE */ - || opcode == 0x4e74 /* RTD */ - || opcode == 0x4e75 /* RTS */ - || opcode == 0x4e77 /* RTR */ - || opcode == 0x4e76 /* TRAPV */ - || (opcode & 0xffc0) == 0x4e80 /* JSR */ - || (opcode & 0xffc0) == 0x4ec0 /* JMP */ - || (opcode & 0xff00) == 0x6100 /* BSR */ - || ((opcode & 0xf000) == 0x6000 /* Bcc */ - && cctrue ((opcode >> 8) & 0xf)) - || ((opcode & 0xf0f0) == 0x5050 /* DBcc */ - && !cctrue ((opcode >> 8) & 0xf) - && (uae_s16)m68k_dreg (regs, opcode & 7) != 0)) - { - last_trace_ad = m68k_getpc (); - unset_special (SPCFLAG_TRACE); - set_special (SPCFLAG_DOTRACE); - } - } else if (regs.t1) { - last_trace_ad = m68k_getpc (); - unset_special (SPCFLAG_TRACE); - set_special (SPCFLAG_DOTRACE); - } + // this is obsolete + return; + } + if (regs.t1) { + activate_trace(); + } } void doint (void) @@ -1211,6 +1203,8 @@ void doint (void) * Handle special flags */ +static int vpos = 0; + static int do_specialties (int cycles) { if (regs.spcflags & SPCFLAG_DOTRACE) @@ -1280,6 +1274,34 @@ static int do_specialties (int cycles) #else +static int ndCycles = 0; +// give other MPUs (DSP, i860) some time to run on m68k thread +static inline void run_other_MPUs() { + ndCycles += cpu_cycles; + // bundle some 68k cycles for MPUs + + if(dsp_core.running) + DSP_Run(cpu_cycles); + + if(ndCycles > 100) { + i860_Run(ndCycles); + ndCycles = 0; + } +} + +/** + * Return interrupt number (1 - 7), 0 means no interrupt. + * Note that the interrupt stays pending if it can't be executed yet + * due to the interrupt level field in the SR. + */ +static inline int intlev(void) { + /* Poll interrupt level from interrupt status and mask registers + * --> see sysReg.c + */ + Uint32 interrupt = scrIntStat&scrIntMask; + return interrupt ? scr_get_interrupt_level(interrupt) : 0; +} + static int lastRegsS = 0; // Previous MMU 68030 @@ -1337,8 +1359,7 @@ insretry: M68000_AddCycles(cpu_cycles); cpu_cycles = nCyclesMainCounter - beforeCycles; - DSP_Run(cpu_cycles); - i860_Run(cpu_cycles); + run_other_MPUs(); /* We can have several interrupts at the same time before the next CPU instruction */ /* We must check for pending interrupt and call do_specialties_interrupt() only */ @@ -1406,7 +1427,7 @@ static void m68k_run_mmu040 (void) uaecptr pc; int intr = 0; int lastintr = 0; - + for (;;) { TRY (prb) { for (;;) { @@ -1417,15 +1438,13 @@ static void m68k_run_mmu040 (void) Uint64 beforeCycles = nCyclesMainCounter; mmu_opcode = -1; - mmu_opcode = opcode = x_prefetch (0); + mmu_opcode = opcode = get_iword_mmu040(0); cpu_cycles = (*cpufunctbl[opcode])(opcode); M68000_AddCycles(cpu_cycles); - cpu_cycles = nCyclesMainCounter - beforeCycles; - DSP_Run(cpu_cycles); - i860_Run(cpu_cycles); - + run_other_MPUs(); + /* We can have several interrupts at the same time before the next CPU instruction */ /* We must check for pending interrupt and call do_specialties_interrupt() only */ /* if the cpu is not in the STOP state. Else, the int could be acknowledged now */ @@ -1514,7 +1533,6 @@ void m68k_go (int may_quit) break; } - quit_program = 0; hardboot = 0; #ifdef DEBUGGER