--- previous/src/cpu/newcpu.h	2018/04/24 19:31:48	1.1.1.5
+++ previous/src/cpu/newcpu.h	2018/04/24 19:33:37	1.1.1.6
@@ -610,6 +610,7 @@ STATIC_INLINE void m68k_setpc_normal(uae
 	}
 }
 
+extern void check_t0_trace(void);
 extern void write_dcache030(uaecptr, uae_u32, int);
 extern uae_u32 read_dcache030(uaecptr, int);
 extern uae_u32 get_word_icache030(uaecptr addr);
@@ -657,10 +658,12 @@ extern void set_cpu_caches (bool flush);
 extern void flush_cpu_caches(bool flush);
 extern void flush_cpu_caches_040(uae_u16 opcode);
 extern void REGPARAM3 MakeSR (void) REGPARAM;
-extern void REGPARAM3 MakeFromSR (void) REGPARAM;
+extern void REGPARAM3 MakeFromSR(void) REGPARAM;
+extern void REGPARAM3 MakeFromSR_T0(void) REGPARAM;
 extern void MakeSR (void);
 extern void MakeFromSR (void);
 extern void REGPARAM3 Exception (int) REGPARAM;
+extern void REGPARAM3 Exception_cpu(int) REGPARAM;
 extern void REGPARAM3 ExceptionL (int, uaecptr) REGPARAM;
 extern void NMI (void);
 extern void NMI_delayed (void);
@@ -680,7 +683,9 @@ extern void m68k_dumpstate_file (FILE *f
 extern void m68k_dumpcache (void);
 extern int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor);
 extern int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor);
-extern void divbyzero_special (bool issigned, uae_s32 dst);
+extern void divbyzero_special(bool issigned, uae_s32 dst);
+extern void setdivuoverflowflags(uae_u32 dividend, uae_u16 divisor);
+extern void setdivsoverflowflags(uae_s32 dividend, uae_s16 divisor);
 extern void m68k_do_rte (void);
 extern void protect_roms (bool);
 extern void unprotect_maprom (void);
@@ -718,8 +723,10 @@ extern void cpu_change(int newmodel);
 extern void cpu_fallback(int mode);
 
 extern void fill_prefetch (void);
-extern void fill_prefetch_020 (void);
-extern void fill_prefetch_030 (void);
+extern void fill_prefetch_020_ntx(void);
+extern void fill_prefetch_030_ntx(void);
+extern void fill_prefetch_020(void);
+extern void fill_prefetch_030(void);
 
 #define CPU_OP_NAME(a) op ## a