![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to table68k CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Previous NeXT emulator] / previous / src / cpu|
Return to table68k CVS log | Up to [Previous NeXT emulator] / previous / src / cpu |
1.1 root 1: % 0: bit 0
2: % 1: bit 1
3: % c: condition code
4: % C: condition codes, except F
5: % f: direction
6: % i: immediate
7: % I: immediate, except 00 and ff
8: % j: immediate 1..8
9: % J: immediate 0..15
10: % k: immediate 0..7
11: % K: immediate 0..63
12: % p: immediate 0..3 (CINV and CPUSH: cache field)
13: % s: source mode
14: % S: source reg
15: % d: dest mode
16: % D: dest reg
17: % r: reg
18: % z: size
19: %
20: % Actually, a sssSSS may appear as a destination, and
21: % vice versa. The only difference between sssSSS and
22: % dddDDD are the valid addressing modes. There is
23: % no match for immediate and pc-rel. addressing modes
24: % in case of dddDDD.
25: %
26: % Arp: --> -(Ar)
27: % ArP: --> (Ar)+
28: % Ara: --> (Ar)
29: % L: (xxx.L)
30: %
31: % Fields on a line:
32: % 16 chars bitpattern :
33: % CPU level / privilege level :
34: % CPU level 0: 68000
35: % 1: 68010
36: % 2: 68020
37: % 3: 68030
38: % 4: 68040
1.1.1.3 root 39: % 5: 68060
1.1 root 40: % [Everything from 68020 possibly allows for FPU emulation]
1.1.1.3 root 41: % Unimplemented after:
42: % 0: Normal
43: % 3: Not implemented in 68030 and later
44: % 4: Not implemented in 68040 and later
45: % 5: Not implemented in 68060
1.1 root 46: % privilege level 0: not privileged
47: % 1: unprivileged only on 68000 (check regs.s)
48: % 2: privileged (check regs.s)
49: % 3: privileged if size == word (check regs.s)
50: % Flags set by instruction: XNZVC :
51: % Flags used by instruction: XNZVC :
52: % - means flag unaffected / unused
53: % 0 means flag reset
54: % 1 means flag set
55: % ? means programmer was too lazy to check or instruction may trap
56: % + means instruction is conditional branch
57: % everything else means flag set/used
58: % / means instruction is unconditional branch/call
59: % x means flag is unknown and well-behaved programs shouldn't check it
60: % srcaddr status destaddr status :
61: % bitmasks of
62: % 1 means fetched
63: % 2 means stored
64: % 4 means jump offset
65: % 8 means jump address
66: % instruction
1.1.1.3 root 67: % optional line feed and 68030 Head/Tail/Cycles/ea calculation
1.1 root 68: %
69:
1.1.1.3 root 70: 0000 0000 0011 1100:000:XNZVC:XNZVC:10: ORSR.B #1
71: 0000 0000 0111 1100:002:?????:?????:10: ORSR.W #1
72: 0000 0zz0 11ss sSSS:250:?????:?????:11: CHK2.z #1,s[!Dreg,Areg,Aipi,Apdi,Immd]
73:
74: 0000 0000 zzdd dDDD:000:-NZ00:-----:13: OR.z #z,d[Dreg]
75: - 2 0 2 fiea
76: 0000 0000 zzdd dDDD:000:-NZ00:-----:13: OR.z #z,d[!Areg,Dreg]
77: - 0 1 3 fiea
78:
79: 0000 0010 0011 1100:000:XNZVC:XNZVC:10: ANDSR.B #1
80: 0000 0010 0111 1100:002:?????:?????:10: ANDSR.W #1
81:
82: 0000 0010 zzdd dDDD:000:-NZ00:-----:13: AND.z #z,d[Dreg]
83: - 2 0 2 fiea
84: 0000 0010 zzdd dDDD:000:-NZ00:-----:13: AND.z #z,d[!Areg,Dreg]
85: - 0 1 3 fiea
86: 0000 0100 zzdd dDDD:000:XNZVC:-----:13: SUB.z #z,d[Dreg]
87: - 2 0 2 fiea
88: 0000 0100 zzdd dDDD:000:XNZVC:-----:13: SUB.z #z,d[!Areg,Dreg]
89: - 0 1 3 fiea
90: 0000 0110 zzdd dDDD:000:XNZVC:-----:13: ADD.z #z,d[Dreg]
91: - 2 0 2 fiea
92: 0000 0110 zzdd dDDD:000:XNZVC:-----:13: ADD.z #z,d[!Areg,Dreg]
93: - 0 1 3 fiea
94:
95: 0000 0110 11ss sSSS:230:?????:?????:10: CALLM s[!Dreg,Areg,Aipi,Apdi,Immd]
96: 0000 0110 11ss sSSS:230:?????:?????:10: RTM s[Dreg,Areg]
97:
98: 0000 1000 00ss sSSS:000:--Z--:-----:11: BTST #1,s[Dreg]
99: - 4 0 4
100: 0000 1000 00ss sSSS:000:--Z--:-----:11: BTST #1,s[!Areg,Dreg,Immd]
101: - 0 0 4 fiea
102: 0000 1000 01ss sSSS:000:--Z--:-----:13: BCHG #1,s[Dreg]
103: - 6 0 6
104: 0000 1000 01ss sSSS:000:--Z--:-----:13: BCHG #1,s[!Areg,Dreg,Immd,PC8r,PC16]
105: - 0 0 6 fiea
106: 0000 1000 10ss sSSS:000:--Z--:-----:13: BCLR #1,s[Dreg]
107: - 6 0 6
108: 0000 1000 10ss sSSS:000:--Z--:-----:13: BCLR #1,s[!Areg,Dreg,Immd,PC8r,PC16]
109: - 0 0 6 fiea
110: 0000 1000 11ss sSSS:000:--Z--:-----:13: BSET #1,s[Dreg]
111: - 6 0 6
112: 0000 1000 11ss sSSS:000:--Z--:-----:13: BSET #1,s[!Areg,Dreg,Immd,PC8r,PC16]
113: - 0 0 6 fiea
114:
115: 0000 1010 0011 1100:000:XNZVC:XNZVC:10: EORSR.B #1
116: 0000 1010 0111 1100:002:?????:?????:10: EORSR.W #1
117:
118: 0000 1010 zzdd dDDD:000:-NZ00:-----:13: EOR.z #z,d[Dreg]
119: - 2 0 2 fiea
120: 0000 1010 zzdd dDDD:000:-NZ00:-----:13: EOR.z #z,d[!Areg,Dreg]
121: - 0 1 3 fiea
122: 0000 1100 zzss sSSS:000:-NZVC:-----:11: CMP.z #z,s[Dreg]
123: - 2 0 2 fiea
124: 0000 1100 zzss sSSS:000:-NZVC:-----:11: CMP.z #z,s[!Areg,Dreg,Immd,PC8r,PC16]
125: - 0 0 2 fiea
126: 0000 1100 zzss sSSS:200:-NZVC:-----:11: CMP.z #z,s[PC8r,PC16]
127: - 0 0 2 fiea
128:
129: 0000 1010 11ss sSSS:200:?????:?????:13: CAS.B #1,s[!Dreg,Areg,Immd,PC8r,PC16]
130: 0000 1100 11ss sSSS:200:?????:?????:13: CAS.W #1,s[!Dreg,Areg,Immd,PC8r,PC16]
131: 0000 1100 1111 1100:250:?????:?????:10: CAS2.W #2
132: 0000 1110 zzss sSSS:202:?????:?????:13: MOVES.z #1,s[!Dreg,Areg,Immd,PC8r,PC16]
133: 0000 1110 11ss sSSS:200:?????:?????:13: CAS.L #1,s[!Dreg,Areg,Immd,PC8r,PC16]
134: 0000 1110 1111 1100:250:?????:?????:10: CAS2.L #2
135:
136: 0000 rrr1 00dd dDDD:050:-----:-----:12: MVPMR.W d[Areg-Ad16],Dr
137: 0000 rrr1 01dd dDDD:050:-----:-----:12: MVPMR.L d[Areg-Ad16],Dr
138: 0000 rrr1 10dd dDDD:050:-----:-----:12: MVPRM.W Dr,d[Areg-Ad16]
139: 0000 rrr1 11dd dDDD:050:-----:-----:12: MVPRM.L Dr,d[Areg-Ad16]
140:
141: 0000 rrr1 00ss sSSS:000:--Z--:-----:11: BTST Dr,s[Dreg]
142: - 4 0 4
143: 0000 rrr1 00ss sSSS:000:--Z--:-----:11: BTST Dr,s[!Areg,Dreg]
144: - 0 0 4 fea
145: 0000 rrr1 01ss sSSS:000:--Z--:-----:13: BCHG Dr,s[Dreg]
146: - 6 0 6
147: 0000 rrr1 01ss sSSS:000:--Z--:-----:13: BCHG Dr,s[!Areg,Dreg,Immd,PC8r,PC16]
148: - 0 0 6 fea
149: 0000 rrr1 10ss sSSS:000:--Z--:-----:13: BCLR Dr,s[Dreg]
150: - 6 0 6
151: 0000 rrr1 10ss sSSS:000:--Z--:-----:13: BCLR Dr,s[!Areg,Dreg,Immd,PC8r,PC16]
152: - 0 0 6 fea
153: 0000 rrr1 11ss sSSS:000:--Z--:-----:13: BSET Dr,s[Dreg]
154: - 6 0 6
155: 0000 rrr1 11ss sSSS:000:--Z--:-----:13: BSET Dr,s[!Areg,Dreg,Immd,PC8r,PC16]
156: - 0 0 6 fea
157:
158: % Move cycles are special cased in gencpu.c
159: 0001 DDDd ddss sSSS:000:-NZ00:-----:12: MOVE.B s,d[!Areg]
160: 0011 DDDd ddss sSSS:000:-----:-----:12: MOVEA.W s,d[Areg]
161: 0011 DDDd ddss sSSS:000:-NZ00:-----:12: MOVE.W s,d[!Areg]
162: 0010 DDDd ddss sSSS:000:-----:-----:12: MOVEA.L s,d[Areg]
163: 0010 DDDd ddss sSSS:000:-NZ00:-----:12: MOVE.L s,d[!Areg]
164:
165: 0100 0000 zzdd dDDD:000:XxZxC:X-Z--:30: NEGX.z d[Dreg]
166: - 2 0 2
167: 0100 0000 zzdd dDDD:000:XxZxC:X-Z--:30: NEGX.z d[!Areg,Dreg]
168: - 0 1 3 fea
169: 0100 0000 11dd dDDD:001:?????:?????:10: MVSR2.W d[Dreg]
170: - 2 0 4
171: 0100 0000 11dd dDDD:001:?????:?????:10: MVSR2.W d[!Areg,Dreg]
172: - 2 0 4 cea
173: 0100 0010 zzdd dDDD:000:-0100:-----:20: CLR.z d[Dreg]
174: - 2 0 2
175: 0100 0010 zzdd dDDD:000:-0100:-----:20: CLR.z d[!Areg,Dreg]
176: - 0 1 3 cea
177: 0100 0010 11dd dDDD:100:?????:?????:10: MVSR2.B d[Dreg]
178: - 2 0 4
179: 0100 0010 11dd dDDD:100:?????:?????:10: MVSR2.B d[!Areg,Dreg]
180: - 2 0 4 cea
181: 0100 0100 zzdd dDDD:000:XNZVC:-----:30: NEG.z d[Dreg]
182: - 2 0 2
183: 0100 0100 zzdd dDDD:000:XNZVC:-----:30: NEG.z d[!Areg,Dreg]
184: - 0 1 3 fea
185: 0100 0100 11ss sSSS:000:XNZVC:-----:10: MV2SR.B s[Dreg]
186: - 4 0 4
187: 0100 0100 11ss sSSS:000:XNZVC:-----:10: MV2SR.B s[!Areg,Dreg]
188: - 0 0 4 fea
189: 0100 0110 zzdd dDDD:000:-NZ00:-----:30: NOT.z d[Dreg]
190: - 2 0 2
191: 0100 0110 zzdd dDDD:000:-NZ00:-----:30: NOT.z d[!Areg,Dreg]
192: - 0 1 3 fea
193: 0100 0110 11ss sSSS:002:?????:?????:10: MV2SR.W s[!Areg]
194: - 0 0 8 fea
195: 0100 1000 0000 1rrr:200:-----:-----:31: LINK.L Ar,#2
196: - 2 0 6
197: 0100 1000 00dd dDDD:000:X?Z?C:X-Z--:30: NBCD.B d[!Areg]
198: - 0 0 6
199:
200: 0100 1000 0100 1kkk:200:?????:?????:10: BKPT #k
201:
202: 0100 1000 01ss sSSS:000:-NZ00:-----:30: SWAP.W s[Dreg]
203: - 4 0 4
204: 0100 1000 01ss sSSS:000:-----:-----:00: PEA.L s[!Dreg,Areg,Aipi,Apdi,Immd]
205: - 0 2 4 cea
206: 0100 1000 10dd dDDD:000:-NZ00:-----:30: EXT.W d[Dreg]
207: - 4 0 4
208:
209: 0100 1000 10dd dDDD:000:-----:-----:02: MVMLE.W #1,d[!Dreg,Areg,Aipi]
210:
211: 0100 1000 11dd dDDD:000:-NZ00:-----:30: EXT.L d[Dreg]
212: - 4 0 4
213:
214: 0100 1000 11dd dDDD:000:-----:-----:02: MVMLE.L #1,d[!Dreg,Areg,Aipi]
215:
216: 0100 1001 11dd dDDD:200:-NZ00:-----:30: EXT.B d[Dreg]
217: - 4 0 4
218: 0100 1010 zzss sSSS:000:-NZ00:-----:10: TST.z s[Dreg]
219: - 0 0 2
220: 0100 1010 zzss sSSS:000:-NZ00:-----:10: TST.z s[!Areg,Dreg,PC16,PC8r,Immd]
221: - 0 0 2 fea
1.1.1.4 ! root 222: 0100 1010 zzss sSSS:200:-NZ00:-----:10: TST.z s[Areg,PC16,PC8r,Immd]
1.1.1.3 root 223: - 0 0 2 fea
224: 0100 1010 11dd dDDD:000:?????:?????:30: TAS.B d[Dreg]
225: - 0 0 2
226: 0100 1010 11dd dDDD:000:?????:?????:30: TAS.B d[!Areg,Dreg]
227: - 0 0 2 fea
228:
229: 0100 1010 1111 1100:000:?????:?????:00: ILLEGAL
230:
231: 0100 1100 00ss sSSS:200:-NZVC:-----:13: MULL.L #1,s[!Areg]
232: - 2 0 30 fiea
233: 0100 1100 01ss sSSS:200:?????:?????:13: DIVL.L #1,s[!Areg]
234: - 0 0 50 fiea
235:
236: 0100 1100 10ss sSSS:000:-----:-----:01: MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd]
237: 0100 1100 11ss sSSS:000:-----:-----:01: MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd]
238: 0100 1110 0100 JJJJ:000:-----:XNZVC:10: TRAP #J
239:
240: 0100 1110 0101 0rrr:000:-----:-----:31: LINK.W Ar,#1
241: - 0 0 4
242: 0100 1110 0101 1rrr:000:-----:-----:30: UNLK.L Ar
243: - 0 0 5
244: 0100 1110 0110 0rrr:002:-----:-----:10: MVR2USP.L Ar
245: - 4 0 4
246: 0100 1110 0110 1rrr:002:-----:-----:20: MVUSP2R.L Ar
247: - 4 0 4
248: 0100 1110 0111 0000:002:-----:-----:00: RESET
249: - 0 0 518
250: 0100 1110 0111 0001:000:-----:-----:00: NOP
251: - 0 0 2
252: 0100 1110 0111 0010:002:XNZVC:-----:10: STOP #1
253: - 0 0 8
254: 0100 1110 0111 0011:002:XNZVC:-----:00: RTE
255: - 1 9 18
1.1.1.4 ! root 256: 0100 1110 0111 0100:100:?????:?????:10: RTD #1
! 257:
1.1.1.3 root 258: - 2 0 10
259: 0100 1110 0111 0101:000:-----:-----:00: RTS
260: - 1 0 9
261:
262: 0100 1110 0111 0110:000:-----:XNZVC:00: TRAPV
263:
264: 0100 1110 0111 0111:000:XNZVC:-----:00: RTR
265: - 1 0 12
266:
267: 0100 1110 0111 1010:102:?????:?????:10: MOVEC2 #1
268: - 6 0 6
269: 0100 1110 0111 1011:102:?????:?????:10: MOVE2C #1
270: - 6 0 6
271: 0100 1110 10ss sSSS:000://///://///:80: JSR.L s[!Dreg,Areg,Aipi,Apdi,Immd]
272: - 0 0 4 jea
273:
274: 0100 rrr1 00ss sSSS:200:?????:?????:11: CHK.L s[!Areg],Dr
275: 0100 rrr1 10ss sSSS:000:?????:?????:11: CHK.W s[!Areg],Dr
276:
277: 0100 1110 11ss sSSS:000://///://///:80: JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd]
278: - 4 0 4 jea
279: 0100 rrr1 11ss sSSS:000:-----:-----:02: LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar
280: - 2 0 2 cea
281:
282: 0101 jjj0 01dd dDDD:000:-----:-----:13: ADDA.W #j,d[Areg]
283: - 2 0 2
284: 0101 jjj0 10dd dDDD:000:-----:-----:13: ADDA.L #j,d[Areg]
285: - 2 0 2
286: 0101 jjj0 zzdd dDDD:000:XNZVC:-----:13: ADD.z #j,d[Dreg]
287: - 2 0 2
288: 0101 jjj0 zzdd dDDD:000:XNZVC:-----:13: ADD.z #j,d[!Areg,Dreg]
289: - 0 1 3 fea
290: 0101 jjj1 01dd dDDD:000:-----:-----:13: SUBA.W #j,d[Areg]
291: - 2 0 2
292: 0101 jjj1 10dd dDDD:000:-----:-----:13: SUBA.L #j,d[Areg]
293: - 2 0 2
294: 0101 jjj1 zzdd dDDD:000:XNZVC:-----:13: SUB.z #j,d[Dreg]
295: - 2 0 2
296: 0101 jjj1 zzdd dDDD:000:XNZVC:-----:13: SUB.z #j,d[!Areg,Dreg]
297: - 0 1 3 fea
298: 0101 cccc 1100 1rrr:000:-----:-++++:31: DBcc.W Dr,#1
299: - -1 0 0
300: 0101 cccc 11dd dDDD:000:-----:-++++:20: Scc.B d[Dreg]
301: - 0 0 2
302: 0101 cccc 11dd dDDD:000:-----:-++++:20: Scc.B d[!Areg,Dreg]
303: - 0 0 2 cea
304:
305: 0101 cccc 1111 1010:200:?????:?????:10: TRAPcc #1
306: 0101 cccc 1111 1011:200:?????:?????:10: TRAPcc #2
307: 0101 cccc 1111 1100:200:?????:?????:00: TRAPcc
1.1 root 308:
309: % Bxx.L is 68020 only, but setting the CPU level to 2 would give illegal
310: % instruction exceptions when compiling a 68000 only emulation, which isn't
311: % what we want either.
1.1.1.3 root 312: 0110 0001 0000 0000:000://///://///:40: BSR.W #1
313: - 2 0 6
314: 0110 0001 IIII IIII:000://///://///:40: BSR.B #i
315: - 2 0 6
316: 0110 0001 1111 1111:000://///://///:40: BSR.L #2
317: - 2 0 6
318: 0110 CCCC 0000 0000:000:-----:-++++:40: Bcc.W #1
319: - -1 0 0
320: 0110 CCCC IIII IIII:000:-----:-++++:40: Bcc.B #i
321: - -1 0 0
322: 0110 CCCC 1111 1111:000:-----:-++++:40: Bcc.L #2
323: - -1 0 0
324:
325: 0111 rrr0 iiii iiii:000:-NZ00:-----:12: MOVE.L #i,Dr
326:
327: 1000 rrr0 zzss sSSS:000:-NZ00:-----:13: OR.z s[Dreg],Dr
328: - 2 0 2
329: 1000 rrr0 zzss sSSS:000:-NZ00:-----:13: OR.z s[!Areg,Dreg],Dr
330: - 0 0 2 fea
331:
332: 1000 rrr0 11ss sSSS:000:?????:?????:13: DIVU.W s[Dreg],Dr
333: - 2 0 54
334: 1000 rrr0 11ss sSSS:000:?????:?????:13: DIVU.W s[!Areg,Dreg],Dr
335: - 0 0 54 fea
336:
337: 1000 rrr1 00dd dDDD:000:XxZxC:X-Z--:13: SBCD.B d[Dreg],Dr
338: - 0 0 4
339: 1000 rrr1 00dd dDDD:000:XxZxC:X-Z--:13: SBCD.B d[Areg-Apdi],Arp
340: - 2 1 13
341:
342: 1000 rrr1 zzdd dDDD:000:-NZ00:-----:13: OR.z Dr,d[!Areg,Dreg]
343: - 0 1 3 fea
344:
345: 1000 rrr1 01dd dDDD:200:?????:?????:12: PACK d[Dreg],Dr
346: - 6 0 6
347: 1000 rrr1 01dd dDDD:200:?????:?????:12: PACK d[Areg-Apdi],Arp
348: - 2 1 11
349: 1000 rrr1 10dd dDDD:200:?????:?????:12: UNPK d[Dreg],Dr
350: - 8 0 8
351: 1000 rrr1 10dd dDDD:200:?????:?????:12: UNPK d[Areg-Apdi],Arp
352: - 2 1 11
353:
354: 1000 rrr1 11ss sSSS:000:?????:?????:13: DIVS.W s[Dreg],Dr
355: - 2 0 54
356: 1000 rrr1 11ss sSSS:000:?????:?????:13: DIVS.W s[!Areg,Dreg],Dr
357: - 0 0 54 fea
358:
359: 1001 rrr0 zzss sSSS:000:XNZVC:-----:13: SUB.z s[Areg,Dreg],Dr
360: - 2 0 2
361: 1001 rrr0 zzss sSSS:000:XNZVC:-----:13: SUB.z s[!Areg,Dreg],Dr
362: - 0 0 2 fea
363: 1001 rrr0 11ss sSSS:000:-----:-----:13: SUBA.W s[Areg,Dreg],Ar
364: - 4 0 4
365: 1001 rrr0 11ss sSSS:000:-----:-----:13: SUBA.W s[!Areg,Dreg],Ar
366: - 0 0 4 fea
367:
368: 1001 rrr1 zzdd dDDD:000:XNZVC:X-Z--:13: SUBX.z d[Dreg],Dr
369: - 2 0 2
370: 1001 rrr1 zzdd dDDD:000:XNZVC:X-Z--:13: SUBX.z d[Areg-Apdi],Arp
371: - 2 1 9
372:
373: 1001 rrr1 zzdd dDDD:000:XNZVC:-----:13: SUB.z Dr,d[!Areg,Dreg]
374: - 0 1 3 fea
375: 1001 rrr1 11ss sSSS:000:-----:-----:13: SUBA.L s[Areg,Dreg],Ar
376: - 2 0 2
377: 1001 rrr1 11ss sSSS:000:-----:-----:13: SUBA.L s[!Areg,Dreg],Ar
378: - 0 0 2 fea
379:
380: 1011 rrr0 zzss sSSS:000:-NZVC:-----:11: CMP.z s[Areg,Dreg],Dr
381: - 2 0 2
382: 1011 rrr0 zzss sSSS:000:-NZVC:-----:11: CMP.z s[!Areg,Dreg],Dr
383: - 0 0 2 fea
384: 1011 rrr0 11ss sSSS:000:-NZVC:-----:11: CMPA.W s[Areg,Dreg],Ar
385: - 4 0 4
386: 1011 rrr0 11ss sSSS:000:-NZVC:-----:11: CMPA.W s[!Areg,Dreg],Ar
387: - 0 0 4 fea
388: 1011 rrr1 11ss sSSS:000:-NZVC:-----:11: CMPA.L s[Areg,Dreg],Ar
389: - 4 0 4
390: 1011 rrr1 11ss sSSS:000:-NZVC:-----:11: CMPA.L s[!Areg,Dreg],Ar
391: - 0 0 4 fea
392: 1011 rrr1 zzdd dDDD:000:-NZVC:-----:11: CMPM.z d[Areg-Aipi],ArP
393: - 0 0 8
394: 1011 rrr1 zzdd dDDD:000:-NZ00:-----:13: EOR.z Dr,d[Dreg]
395: - 2 0 2
396: 1011 rrr1 zzdd dDDD:000:-NZ00:-----:13: EOR.z Dr,d[!Areg,Dreg]
397: - 0 1 3 fea
398:
399: 1100 rrr0 zzss sSSS:000:-NZ00:-----:13: AND.z s[Dreg],Dr
400: - 2 0 2 fea
401: 1100 rrr0 zzss sSSS:000:-NZ00:-----:13: AND.z s[!Areg,Dreg],Dr
402: - 0 1 3 fea
403: 1100 rrr0 11ss sSSS:000:-NZ00:-----:13: MULU.W s[!Areg],Dr
404: - 2 0 25 fea
405:
406: 1100 rrr1 00dd dDDD:000:XxZxC:X-Z--:13: ABCD.B d[Dreg],Dr
407: - 0 0 4
408: 1100 rrr1 00dd dDDD:000:XxZxC:X-Z--:13: ABCD.B d[Areg-Apdi],Arp
409: - 2 1 13
410:
411: 1100 rrr1 zzdd dDDD:000:-NZ00:-----:13: AND.z Dr,d[!Areg,Dreg]
412: - 0 1 3 fea
413: 1100 rrr1 01dd dDDD:000:-----:-----:33: EXG.L Dr,d[Dreg]
414: - 4 0 4
415: 1100 rrr1 01dd dDDD:000:-----:-----:33: EXG.L Ar,d[Areg]
416: - 4 0 4
417: 1100 rrr1 10dd dDDD:000:-----:-----:33: EXG.L Dr,d[Areg]
418: - 4 0 4
419: 1100 rrr1 11ss sSSS:000:-NZ00:-----:13: MULS.W s[!Areg],Dr
420: - 2 0 25 fea
421:
422: 1101 rrr0 zzss sSSS:000:XNZVC:-----:13: ADD.z s[Areg,Dreg],Dr
423: - 2 0 2
424: 1101 rrr0 zzss sSSS:000:XNZVC:-----:13: ADD.z s[!Areg,Dreg],Dr
425: - 0 0 2 fea
426: 1101 rrr0 11ss sSSS:000:-----:-----:13: ADDA.W s[Areg,Dreg],Ar
427: - 0 0 4
428: 1101 rrr0 11ss sSSS:000:-----:-----:13: ADDA.W s[!Areg,Dreg],Ar
429: - 4 0 4 fea
430:
431: 1101 rrr1 zzdd dDDD:000:XNZVC:X-Z--:13: ADDX.z d[Dreg],Dr
432: - 2 0 2
433: 1101 rrr1 zzdd dDDD:000:XNZVC:X-Z--:13: ADDX.z d[Areg-Apdi],Arp
434: - 2 1 9
435:
436: 1101 rrr1 zzdd dDDD:000:XNZVC:-----:13: ADD.z Dr,d[!Areg,Dreg]
437: - 0 1 3 fea
438: 1101 rrr1 11ss sSSS:000:-----:-----:13: ADDA.L s[Areg,Dreg],Ar
439: - 2 0 2
440: 1101 rrr1 11ss sSSS:000:-----:-----:13: ADDA.L s[!Areg,Dreg],Ar
441: - 0 0 2 fea
442:
443: 1110 jjjf zz00 0RRR:000:XNZVC:-----:13: ASf.z #j,DR
444: - 2 0 6
445: 1110 jjjf zz00 1RRR:000:XNZ0C:-----:13: LSf.z #j,DR
446: - 4 0 4
447: 1110 jjjf zz01 0RRR:000:XNZ0C:X----:13: ROXf.z #j,DR
448: - 10 0 12
449: 1110 jjjf zz01 1RRR:000:-NZ0C:-----:13: ROf.z #j,DR
450: - 4 0 6
451: 1110 rrrf zz10 0RRR:000:XNZVC:X----:13: ASf.z Dr,DR
452: - 4 0 6
453: 1110 rrrf zz10 1RRR:000:XNZ0C:X----:13: LSf.z Dr,DR
454: - 6 0 6
455: 1110 rrrf zz11 0RRR:000:XNZ0C:X----:13: ROXf.z Dr,DR
456: - 10 0 12
457: 1110 rrrf zz11 1RRR:000:-NZ0C:-----:13: ROf.z Dr,DR
458: - 6 0 8
459: 1110 000f 11dd dDDD:000:XNZVC:-----:13: ASfW.W d[!Dreg,Areg]
460: - 0 0 4 fea
461: 1110 001f 11dd dDDD:000:XNZ0C:-----:13: LSfW.W d[!Dreg,Areg]
462: - 0 0 4 fea
463: 1110 010f 11dd dDDD:000:XNZ0C:X----:13: ROXfW.W d[!Dreg,Areg]
464: - 0 0 4 fea
465: 1110 011f 11dd dDDD:000:-NZ0C:-----:13: ROfW.W d[!Dreg,Areg]
466: - 0 0 6 fea
467:
468: 1110 1000 11ss sSSS:200:?????:?????:11: BFTST #1,s[!Areg,Apdi,Aipi,Immd]
469: 1110 1001 11ss sSSS:200:?????:?????:11: BFEXTU #1,s[!Areg,Apdi,Aipi,Immd]
470: 1110 1010 11ss sSSS:200:?????:?????:13: BFCHG #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
471: 1110 1011 11ss sSSS:200:?????:?????:11: BFEXTS #1,s[!Areg,Apdi,Aipi,Immd]
472: 1110 1100 11ss sSSS:200:?????:?????:13: BFCLR #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
473: 1110 1101 11ss sSSS:200:?????:?????:11: BFFFO #1,s[!Areg,Apdi,Aipi,Immd]
474: 1110 1110 11ss sSSS:200:?????:?????:13: BFSET #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
475: 1110 1111 11ss sSSS:200:?????:?????:13: BFINS #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
1.1 root 476:
477: % floating point co processor
1.1.1.3 root 478: 1111 0010 00ss sSSS:200:?????:?????:11: FPP #1,s
479: 1111 0010 01ss sSSS:200:?????:?????:11: FDBcc #1,s[Areg-Dreg]
480: 1111 0010 01ss sSSS:200:?????:?????:11: FScc #1,s[!Areg,Immd,PC8r,PC16]
481: 1111 0010 0111 1010:200:?????:?????:10: FTRAPcc #1
482: 1111 0010 0111 1011:200:?????:?????:10: FTRAPcc #2
483: 1111 0010 0111 1100:200:?????:?????:00: FTRAPcc
484: 1111 0010 10KK KKKK:200:?????:?????:11: FBcc #K,#1
485: 1111 0010 11KK KKKK:200:?????:?????:11: FBcc #K,#2
486: 1111 0011 00ss sSSS:202:?????:?????:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]
487: 1111 0011 01ss sSSS:202:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
1.1 root 488:
489: % 68030 MMU (allowed addressing modes not checked!)
1.1.1.3 root 490: 1111 0000 00ss sSSS:342:?????:?????:11: MMUOP030 s[Dreg,Areg,Apdi,Aipi,Aind,Ad16,Ad8r,absl,absw],#1
1.1 root 491:
492: % 68040/68060 instructions
1.1.1.3 root 493: 1111 0100 pp00 1rrr:402:-----:-----:02: CINVL #p,Ar
494: 1111 0100 pp01 0rrr:402:-----:-----:02: CINVP #p,Ar
495: 1111 0100 pp01 1rrr:402:-----:-----:00: CINVA #p
496: 1111 0100 pp10 1rrr:402:-----:-----:02: CPUSHL #p,Ar
497: 1111 0100 pp11 0rrr:402:-----:-----:02: CPUSHP #p,Ar
498: 1111 0100 pp11 1rrr:402:-----:-----:00: CPUSHA #p
499: 1111 0101 0000 0rrr:402:-----:-----:00: PFLUSHN Ara
500: 1111 0101 0000 1rrr:402:-----:-----:00: PFLUSH Ara
501: 1111 0101 0001 0rrr:402:-----:-----:00: PFLUSHAN Ara
502: 1111 0101 0001 1rrr:402:-----:-----:00: PFLUSHA Ara
503: % 68040 only
504: 1111 0101 0100 1rrr:452:-----:-----:00: PTESTW Ara
505: 1111 0101 0110 1rrr:452:-----:-----:00: PTESTR Ara
1.1 root 506:
507: % destination register number is encoded in the following word
1.1.1.3 root 508: 1111 0110 0010 0rrr:400:-----:-----:12: MOVE16 ArP,AxP
509: 1111 0110 00ss sSSS:400:-----:-----:12: MOVE16 s[Dreg-Aipi],L
510: 1111 0110 00dd dDDD:400:-----:-----:12: MOVE16 L,d[Areg-Aipi]
511: 1111 0110 00ss sSSS:400:-----:-----:12: MOVE16 s[Aind],L
512: 1111 0110 00dd dDDD:400:-----:-----:12: MOVE16 L,d[Aipi-Aind]
1.1 root 513:
514: % 68060
1.1.1.3 root 515: 1111 1000 0000 0000:502:?????:?????:10: LPSTOP #1
516: 1111 0101 1000 1rrr:502:-----:-----:00: PLPAW Ara
517: 1111 0101 1100 1rrr:502:-----:-----:00: PLPAR Ara
1.1 root 518:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.