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1.1 root 1: /***
2: * 68k disassembler, written 2010 by Markus Fritze, www.sarnau.com
3: *
4: * This file is distributed under the GNU Public License, version 2 or at
5: * your option any later version. Read the file gpl.txt for details.
6: ***/
7:
8: #include <stdio.h>
9: #include <ctype.h>
10: #include <strings.h>
11: #include <stdlib.h>
12:
13: #include "config.h"
14: #include "sysdeps.h"
15: #include "main.h"
16: #include "newcpu.h"
17: #include "paths.h"
18: #include "68kDisass.h"
19:
20: #define ADDRESS_ON_PC 1
21: #define USE_SYMBOLS 1
22:
23: typedef enum {
24: doptNoBrackets = 1, // hide brackets around absolute addressing
25: doptOpcodesSmall = 2, // opcodes are small letters
26: doptRegisterSmall = 4, // register names are small letters
27: doptStackSP = 8, // stack pointer is named "SP" instead of "A7" (except for MOVEM)
28: } Diss68kOptions;
29:
30: static Diss68kOptions options = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
31:
32: // values <0 will hide the group
33: static int optionPosAddress = 0; // current address
34: static int optionPosHexdump = 10; // 16-bit words at this address
35: static int optionPosLabel = 35; // label, if defined
36: static int optionPosOpcode = 47; // opcode
37: static int optionPosOperand = 57; // operands for the opcode
38: static int optionPosComment = 82; // comment, if defined
39:
40: /***
41: * Motorola 16-/32-Bit Microprocessor and coprocessor types
42: ***/
43: #define MC68000 0x000001 // 16-/32-Bit Microprocessor
44: #define MC68EC000 0x000002 // 16-/32-Bit Embedded Controller
45: #define MC68HC000 0x000004 // Low Power 16-/32-Bit Microprocessor
46: #define MC68008 0x000008 // 16-Bit Microprocessor with 8-Bit Data Bus
47: #define MC68010 0x000010 // 16-/32-Bit Virtual Memory Microprocessor
48: #define MC68020 0x000020 // 32-Bit Virtual Memory Microprocessor
49: #define MC68EC020 0x000040 // 32-Bit Embedded Controller (no PMMU)
50: #define MC68030 0x000080 // Second-Generation 32-Bit Enhanced Microprocessor
51: #define MC68EC030 0x000100 // 32-Bit Embedded Controller (no PMMU)
52: #define MC68040 0x000200 // Third-Generation 32-Bit Microprocessor
53: #define MC68LC040 0x000400 // Third-Generation 32-Bit Microprocessor (no FPU)
54: #define MC68EC040 0x000800 // 32-Bit Embedded Controller (no FPU, no PMMU)
55: #define MC68330 0x001000 // CPU32 Integrated CPU32 Processor
56: #define MC68340 0x002000 // CPU32 Integrated Processor with DMA
57: #define MC68060 0x004000 // Fourth-Generation 32-Bit Microprocessor
58: #define MC68LC060 0x008000 // Fourth-Generation 32-Bit Microprocessor (no FPU)
59: #define MC68EC060 0x010000 // Fourth-Generation 32-Bit Microprocessor (no FPU, no PMMU)
60: #define MC_CPU32 (MC68330|MC68340)
61:
62: #define MC_020 (MC68020|MC68EC020|MC68030|MC68EC030|MC68040|MC68LC040|MC68EC040|MC_CPU32|MC68060|MC68LC060|MC68EC060)
63: #define MC_ALL (MC68000|MC68EC000|MC68HC000|MC68008|MC68010|MC_020)
64:
65: #define MC68851 0x020000 // Paged Memory Management Unit
66:
67: #define MC68881 0x040000 // Floating-PointCoprocessor
68: #define MC68882 0x080000 // Enhanced Floating-Point Coprocessor
69:
70: #define MC_PMMU (MC68881|MC68882)
71: #define MC_FPU (MC68881|MC68882)
72:
73: static int optionCPUTypeMask = ( MC_ALL & ~MC68040 & ~MC_CPU32 & ~MC68060 ) | MC_PMMU | MC_FPU;
74:
75:
76: typedef enum {
77: dtNone,
78: dtByte, // a specific number of bytes, usually 1
79: dtWord, // one 16-bit value
80: dtLong, // one 32-bit value
81: dtOpcode, // an opcode of variable length
82: dtASCString, // a 0-byte terminated ASCII string
83: dtPointer, // a generic 32-bit pointer
84: dtFunctionPointer, // a 32-bit pointer to a function
85: dtStringArray, // a specific number of ASCII bytes
86: } Disass68kDataType;
87:
88: typedef struct {
89: char *name;
90: char *comment;
91: Disass68kDataType type;
92: int size;
93: } disStructElement;
94:
95: typedef struct {
96: char *name; // name of the structure
97: int size; // size of structure
98: int count; // number of lines
99: disStructElement *elements; // array of all elements of the struct
100: } disStructEntry;
101:
102: static int disStructCounts;
103: static disStructEntry *disStructEntries;
104:
105: typedef struct {
106: long addr; // address of the label
107: Disass68kDataType type; // type of the data on the address
108: int size; // size of the label, references inside it are addressed via base address + offset
109: int count; // number of elements at this address with the given size
110: int structIndex; // -1 no struct to describe the element
111: char *name; // name of the label
112: char *comment; // optional comment
113: } disSymbolEntry;
114:
115: static int disSymbolCounts;
116: static disSymbolEntry *disSymbolEntries;
117:
118:
119: static inline unsigned short Disass68kGetWord(long addr)
120: {
121: return get_word(addr);
122: }
123:
124: // Load a text file into memory, count the lines and replace the LF with 0-bytes.
125: static int Disass68kLoadTextFile(const char *filename, char **filebuf)
126: {
127: long index;
128:
129: if(filebuf)
130: *filebuf = NULL;
131: FILE *f = fopen(filename, "r");
132: if(!f) return 0;
133: if(fseek(f, 0, SEEK_END))
134: return 0;
135: long fileLength = ftell(f);
136: if(!fileLength) return 0;
137: if(fseek(f, 0, SEEK_SET))
138: return 0;
139: char *fbuf = malloc(fileLength);
140: if(!fbuf) return 0;
141: if((size_t)fileLength != fread(fbuf, sizeof(char), fileLength, f))
142: return 0;
143: int lineCount = 0;
144: for(index=0; index<fileLength; ++index)
145: {
146: if(fbuf[index] == '\r') // convert potential CR into a space (which we ignore at the end of the line anyway)
147: fbuf[index] = ' ';
148: if(fbuf[index] == '\n') // count LF and terminate line
149: {
150: ++lineCount;
151: fbuf[index] = 0;
152: }
153: }
154: if(filebuf)
155: *filebuf = fbuf;
156: return lineCount;
157: }
158:
159: static void Disass68kLoadStructInfo(const char *filename)
160: {
161: char *fbuf = NULL;
162: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
163: if(!lineCount) { if(fbuf) free(fbuf); return; }
164: disStructEntry *se = NULL;
165: disStructEntries = realloc(disStructEntries, sizeof(disStructEntry) * (disStructCounts + lineCount));
166: if(!disStructEntries) { free(fbuf); return; }
167: char *line = fbuf;
168: char *nextLine;
169: int i,j;
170:
171: for(i=0; i<lineCount; line = nextLine, ++i)
172: {
173: // strip spaces at the end of the line, remember the ptr to the next line
174: char *sp = line;
175: while(*sp++)
176: ;
177: nextLine = sp--;
178: while(isspace(*--sp))
179: *sp = 0;
180:
181: if(line[0] == '{')
182: {
183: se = &disStructEntries[disStructCounts];
184: se->name = strdup(line+1);
185: se->count = 0;
186: se->elements = malloc(sizeof(disStructElement) * lineCount); // lineCount is way too much, but safe
187: } else if(line[0] == '}') {
188: if(se)
189: {
190: se->size = 0;
191: for(j=0; j<se->count; ++j)
192: se->size += se->elements[j].size;
193: // printf("%s : %d bytes\n", se->name, se->size);
194: ++disStructCounts;
195: se = NULL;
196: }
197: } else if(line[0] == '#') {
198: disStructElement dse;
199: int val = 0;
200: int index = 2;
201: if(line[1] == 'A' || line[1] == 'B')
202: {
203: for(; isdigit(line[index]); ++index)
204: {
205: val *= 10;
206: val += line[index] - '0';
207: }
208: }
209: if(val == 0) val = 1;
210: dse.name = NULL;
211: switch(line[1])
212: {
213: case 'A': dse.type = dtStringArray; dse.size = val; dse.name = strdup(line + index + 1); break;
214: case 'B': dse.type = dtByte; dse.size = val; break;
215: case 'W': dse.type = dtWord; dse.size = 2; break;
216: case 'L': dse.type = dtLong; dse.size = 4; break;
217: case 'C': dse.type = dtOpcode; dse.size = 2; break;
218: case 'f': dse.type = dtFunctionPointer; dse.size = 4; break;
219: case 'p': dse.type = dtPointer; dse.size = 4; break;
220: default: dse.type = dtNone; dse.size = 0;
221: printf("Unknown type in \"%s\"\n", line); break;
222: }
223: if(!dse.name)
224: dse.name = strdup(line+3);
225: dse.comment = NULL;
226: if(se)
227: se->elements[se->count++] = dse;
228: }
229: }
230: free(fbuf);
231: }
232:
233: static void Disass68kLoadSymbols(const char *filename)
234: {
235: char *fbuf = NULL;
236: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
237: if(!lineCount) { if(fbuf) free(fbuf); return; }
238: disSymbolEntries = realloc(disSymbolEntries, sizeof(disSymbolEntry) * (disSymbolCounts + lineCount));
239: if(!disSymbolEntries) { free(fbuf); return; }
240: char *line = fbuf;
241: char *nextLine;
242: int i,j;
243:
244: for(i=0; i<lineCount; line = nextLine, ++i)
245: {
246: // strip spaces at the end of the line, remember the ptr to the next line
247: char *sp = line;
248: while(*sp++)
249: ;
250: nextLine = sp--;
251: while(isspace(*--sp))
252: *sp = 0;
253:
254: // ignore empty lines
255: if(line[0] == 0)
256: continue;
257:
258: long addr;
259: sscanf(line, "%lx",&addr);
260: disSymbolEntries[disSymbolCounts].addr = addr;
261: disSymbolEntries[disSymbolCounts].structIndex = -1;
262:
263: char *parameterPtr[10];
264: int parameterCount = 0;
265: char *str = line;
266: do {
267: str = strchr(str, ',');
268: if(str)
269: {
270: char *ep = str;
271: while(isspace(*--ep))
272: *ep = 0;
273: *str++ = 0;
274: while(*str && isspace(*str))
275: ++str;
276: parameterPtr[parameterCount++] = str;
277: }
278: } while(str != NULL && parameterCount < 10);
279:
280: if(parameterCount != 3 && parameterCount != 4)
281: continue; // ignore line
282:
283: long size = 0;
284: int type = 0;
285: if(strlen(parameterPtr[0]) == 1)
286: {
287: switch(parameterPtr[0][0])
288: {
289: case 'A': type = dtASCString; size = 1; break; // ascii NULL
290: case 'B': type = dtByte; size = 1; break; // byte
291: case 'W': type = dtWord; size = 2; break; // word
292: case 'L': type = dtLong; size = 4; break; // long
293: case 'C': type = dtOpcode; size = 2; break; // code
294: case 'f': type = dtFunctionPointer; size = 4; break; // function pointer
295: case 'p': type = dtPointer; size = 4; break; // regular pointer
296: default: printf("ERROR: $%lx : %s\n", addr, parameterPtr[0]); continue;
297: }
298: } else {
299: for(j=0; j<disStructCounts; ++j)
300: {
301: disStructEntry *se = &disStructEntries[j];
302: if(se->name == NULL)
303: break;
304: if(strcmp(parameterPtr[0], se->name))
305: continue;
306: size = se->size;
307: disSymbolEntries[disSymbolCounts].structIndex = j;
308: }
309: }
310: if(!size)
311: continue;
312:
313: disSymbolEntries[disSymbolCounts].type = type;
314: disSymbolEntries[disSymbolCounts].size = size;
315: disSymbolEntries[disSymbolCounts].count = atol(parameterPtr[1]);
316: disSymbolEntries[disSymbolCounts].name = strdup(parameterPtr[2]);
317: disSymbolEntries[disSymbolCounts].comment = NULL;
318: if(parameterCount == 4)
319: disSymbolEntries[disSymbolCounts].comment = strdup(parameterPtr[3]);
320: ++disSymbolCounts;
321: }
322: free(fbuf);
323: }
324:
325: static void Disass68kInit(const char *baseDirectory)
326: {
327: char filename[PATH_MAX];
328:
329: disStructCounts = 0;
330: sprintf(filename, "%s/DisassStructs.txt", baseDirectory);
331: Disass68kLoadStructInfo(filename);
332: // sprintf(filename, "%s/DisassStructs_%4.4X.txt", baseDirectory, TosVersion);
333: Disass68kLoadStructInfo(filename);
334:
335: disSymbolCounts = 0;
336: sprintf(filename, "%s/DisassSymbols.txt", baseDirectory);
337: Disass68kLoadSymbols(filename);
338: // sprintf(filename, "%s/DisassSymbols_%4.4X.txt", baseDirectory, TosVersion);
339: Disass68kLoadSymbols(filename);
340: }
341:
342:
343:
344: static Disass68kDataType Disass68kType(long addr, char *addressLabel, char *commentBuffer, int *count)
345: {
346: int i,j;
347:
348: addressLabel[0] = 0;
349: commentBuffer[0] = 0;
350: for(i=0; i<disSymbolCounts; ++i)
351: {
352: const disSymbolEntry *dse = &disSymbolEntries[i];
353: int offset = addr - dse->addr;
354: if(offset < 0 || offset >= dse->count * dse->size)
355: continue;
356:
357: // no special struct that devices this value?
358: if(dse->structIndex < 0)
359: {
360: offset = (offset + dse->size - 1) / dse->size;
361: *count = dse->count - offset;
362: if(offset == 0) // only in the first line
363: {
364: strcpy(addressLabel, dse->name);
365: if(dse->comment)
366: strcpy(commentBuffer, dse->comment);
367: }
368: return dse->type;
369: }
370:
371: *count = 1;
372: const disStructEntry *se = &disStructEntries[dse->structIndex];
373: for(j=0; j<se->count; ++j)
374: {
375: const disStructElement *e = &se->elements[j];
376: if(offset < e->size)
377: {
378: if(e->type == dtStringArray)
379: *count = e->size;
380: if(j == 0)
381: strcpy(addressLabel, dse->name);
382:
383: sprintf(commentBuffer, "[%s]", e->name);
384: if(e->comment)
385: strcat(commentBuffer, e->comment);
386: return e->type;
387: }
388: offset -= e->size;
389: }
390: return dse->size;
391: }
392: return dtNone;
393: }
394:
395: /***
396: * Lookup a symbol name
397: ***/
398: static const char *Disass68kSymbolName(long addr, int size)
399: {
400: int i;
401:
402: for(i=0; i<disSymbolCounts; ++i)
403: {
404: const disSymbolEntry *dse = &disSymbolEntries[i];
405: int offset = addr - dse->addr;
406: if(offset < 0 || offset >= dse->count * dse->size)
407: continue;
408:
409: if(dse->name[0] == 0)
410: return NULL;
411:
412: int reminder = offset % dse->size;
413: offset /= dse->size;
414:
415: static char symbolName[128];
416: strcpy(symbolName, dse->name);
417: if(offset)
418: sprintf(symbolName+strlen(symbolName), "+%d*%d", dse->size, offset);
419: if(reminder)
420: sprintf(symbolName+strlen(symbolName), "+%d", reminder);
421: return symbolName;
422: }
423: return NULL;
424: }
425:
426: /***
427: * return a string pointer to display a register name
428: ***/
429: static const char *Disass68kRegname(int reg)
430: {
431: static char regName[3];
432: switch(reg)
433: {
434: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
435: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'd' : 'D'), reg);
436: break;
437:
438: case 0x0F:
439: if(options & doptStackSP) // display A7 as SP
440: {
441: if(options & doptRegisterSmall)
442: return "sp";
443: return "SP";
444: }
445: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E:
446: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'a' : 'A'), reg & 7);
447: break;
448: }
449: return regName;
450: }
451:
452: /***
453: * return a string pointer to display a register name
454: ***/
455: static const char *Disass68kNumber(int val)
456: {
457: static char numString[32];
458: if(val >= -9 && val <= 9)
459: {
460: sprintf(numString, "%d", val);
461: } else {
462: // 4 characters/numbers or underscore (e.g. for cookies)
463: char c0 = (val >> 24) & 0xFF;
464: char c1 = (val >> 16) & 0xFF;
465: char c2 = (val >> 8) & 0xFF;
466: char c3 = (val >> 0) & 0xFF;
467: if((isalnum(c0) || c0 == '_') && (isalnum(c1) || c1 == '_') && (isalnum(c2) || c2 == '_') && (isalnum(c3) || c3 == '_'))
468: {
469: sprintf(numString, "'%c%c%c%c'", c0, c1, c2, c3);
470: } else {
471: sprintf(numString, "$%x", val);
472: }
473: }
474: return numString;
475: }
476:
477: /***
478: * Supported registers for e.g. MOVEC
479: ***/
480: #define REG_CCR -1
481: #define REG_SR -2
482: #define REG_PC -3
483: #define REG_ZPC -4
484: #define REG_TT0 -8
485: #define REG_TT1 -9
486: #define REG_MMUSR -10
487: #define REG_USP 0x800
488: #define REG_SFC 0x000
489: #define REG_DFC 0x001
490: #define REG_TC 0x10000
491: #define REG_SRP 0x10002
492: #define REG_CRP 0x10003
493: #define REG_VAL 0x20000
494: #define REG_CACHES_NONE 0x20010
495: #define REG_CACHES_IC 0x20011
496: #define REG_CACHES_DC 0x20012
497: #define REG_CACHES_ICDC 0x20013
498: #define REG_FPU_FPCR 0x30004
499: #define REG_FPU_FPSR 0x30002
500: #define REG_FPU_FPIAR 0x30001
501:
502: static const char *Disass68kSpecialRegister(int reg)
503: {
504: static char buf[8];
505: const char *sp = NULL;
506: switch (reg)
507: {
508: case 0x000: sp = "SFC"; break;
509: case 0x001: sp = "DFC"; break;
510: case 0x002: sp = "CACR"; break;
511: case 0x003: sp = "TC"; break;
512: case 0x004: sp = "ITT0"; break; // IACR0 on an 68EC040 only
513: case 0x005: sp = "ITT1"; break; // IACR1 on an 68EC040 only
514: case 0x006: sp = "DTT0"; break; // DACR0 on an 68EC040 only
515: case 0x007: sp = "DTT1"; break; // DACR1 on an 68EC040 only
516: case 0x008: sp = "BUSCR"; break;
517:
518: case 0x800: sp = "USP"; break;
519: case 0x801: sp = "VBR"; break;
520: case 0x802: sp = "CAAR"; break;
521: case 0x803: sp = "MSP"; break;
522: case 0x804: sp = "ISP"; break;
523: case 0x805: sp = "MMUSR"; break;
524: case 0x806: sp = "URP"; break;
525: case 0x807: sp = "SRP"; break;
526: case 0x808: sp = "PCR"; break;
527:
528: // MMU register
529: case 0x10000: sp = "TC"; break;
530: case 0x10001: sp = "DRP"; break;
531: case 0x10002: sp = "SRP"; break;
532: case 0x10003: sp = "CRP"; break;
533: case 0x10004: sp = "CAL"; break;
534: case 0x10005: sp = "VAL"; break;
535: case 0x10006: sp = "SCCR"; break;
536: case 0x10007: sp = "ACR"; break;
537:
538: case REG_CCR: sp = "CCR"; break;
539: case REG_SR: sp = "SR"; break;
540: case REG_PC: sp = "PC"; break;
541: case REG_ZPC: sp = "ZPC"; break;
542: case REG_TT0: sp = "TT0"; break;
543: case REG_TT1: sp = "TT1"; break;
544: case REG_MMUSR: sp = "MMUSR"; break;
545:
546: case REG_VAL: sp = "VAL"; break;
547:
548: case REG_CACHES_NONE: sp = "NC"; break;
549: case REG_CACHES_IC: sp = "IC"; break;
550: case REG_CACHES_DC: sp = "DC"; break;
551: case REG_CACHES_ICDC: sp = "IC/DC"; break; // GCC lists this as "BC"
552:
553: case REG_FPU_FPCR: sp = "FPCR"; break;
554: case REG_FPU_FPSR: sp = "FPSR"; break;
555: case REG_FPU_FPIAR: sp = "FPIAR"; break;
556:
557: // unknown register => unknown opcode!
558: default: break;
559: }
560: if(options & doptRegisterSmall)
561: {
562: strcpy(buf, sp);
563: char *bp = buf;
564: for(; *bp; ++bp)
565: *bp = tolower(*bp);
566: return buf;
567: }
568: return sp;
569: }
570:
571: /***
572: * 680x0 EA disassembly, supports all address modes
573: *
574: * disassbuf = output buffer for the EA, empty string in case of an illegal EA
575: * addr = pointer to the address, which Disass68kGetWord() will allow to read memory.
576: * Incremented by the function to point behind the opcode, when done
577: * ea = 6-bit ea from the opcode
578: * size = addressed size of the opcode in bytes (e.g. 1,2,4 for MOVE.B, MOVE.W, MOVE.L), only used for immediate addressing
579: ***/
580:
581: #define EA_Dn 0x00001 // Dn
582: #define EA_An 0x00002 // An
583: #define EA_Ani 0x00004 // (An)
584: #define EA_Anip 0x00008 // (An)+
585: #define EA_piAn 0x00010 // -(An)
586: #define EA_dAn 0x00020 // d(An), d(An,Dn), etc.
587: #define EA_PCRel 0x00040 // d(PC), d(PC,Dn), etc.
588: #define EA_Abs 0x00080 // abs.w, abs.l
589: #define EA_Immed 0x00100 // #<val>
590:
591: #define EA_ImmedParameter 0x0200 // an immediate value as a parameter
592: #define EA_ValueParameter 0x0400 // an immediate value as a parameter without the "#"
593: #define EA_SpecialRegister 0x0800 // any special register e.g. SR,CCR,USP,etc
594: #define EA_PCDisplacement 0x1000 // PC relative jump, like for BRA and friends
595:
596: #define EA_All (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs | EA_Immed | EA_PCRel)
597: #define EA_Dest (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs)
598:
599: static char *Disass68kEA(char *disassbuf, char *commentBuffer, long *addr, long opcodeAddr, int ea, int size, int allowedEAs, int parameterValue, int disassFlag)
600: {
601: unsigned short eWord1;
602: unsigned short eWord2;
603: int xn,c,scale;
604: int reg = ea & 7;
605: const char *sp;
606: long val;
607: val = 0;
608:
609: disassbuf[0] = 0;
610: switch(ea)
611: {
612: // M=000 = 0 Dn
613: // Data Register Direct Mode
614: // Dn
615: // M=001 = 1 An
616: // Address Register Direct Mode
617: // An
618: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
619: if((allowedEAs & EA_Dn) != EA_Dn)
620: break;
621: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
622: break;
623: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E: case 0x0F:
624: if((allowedEAs & EA_An) != EA_An)
625: break;
626: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
627: break;
628:
629: // M=010 = 2
630: // Address Register Indirect Mode
631: // (An)
632: case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
633: if((allowedEAs & EA_Ani) != EA_Ani)
634: break;
635: sprintf(disassbuf, "(%s)", Disass68kRegname(reg | 8));
636: break;
637:
638: // M=011 = 3
639: // Address Register Indirect with Postincrement Mode
640: // (An) +
641: case 0x18: case 0x19: case 0x1A: case 0x1B: case 0x1C: case 0x1D: case 0x1E: case 0x1F:
642: if((allowedEAs & EA_Anip) != EA_Anip)
643: break;
644: sprintf(disassbuf, "(%s)+", Disass68kRegname(reg | 8));
645: break;
646:
647: // M=100 = 4
648: // Address Register Indirect with Predecrement Mode
649: // – (An)
650: case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
651: if((allowedEAs & EA_piAn) != EA_piAn)
652: break;
653: sprintf(disassbuf, "-(%s)", Disass68kRegname(reg | 8));
654: break;
655:
656: // M=101 = 5
657: // Address Register Indirect with Displacement Mode
658: // (d16,An)
659: case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F:
660: if((allowedEAs & EA_dAn) != EA_dAn)
661: break;
662: eWord1 = Disass68kGetWord(*addr); *addr += 2;
663: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1), Disass68kRegname(reg | 8));
664: break;
665:
666: // M=111 = 7, Xn/reg = 011 = 3
667: // Program Counter Indirect with Index (Base Displacement) Mode
668: // (bd, PC, Xn. SIZE*SCALE)
669: // Program Counter Memory Indirect Postindexed Mode
670: // ([bd,PC],Xn.SIZE*SCALE,od)
671: // Program Counter Memory Indirect Preindexed Mode
672: // ([bd,PC,Xn.SIZE*SCALE],od)
673: case 0x3B:
674: // This is equal to the following, except that instead of An, it is PC relative
675:
676: // M=110 = 6
677: // Address Register Indirect with Index (Base Displacement) Mode
678: // (bd,An,Xn.SIZE*SCALE)
679: // Memory Indirect Postindexed Mode
680: // ([bd,An],Xn.SIZE*SCALE,od)
681: // Memory Indirect Preindexed Mode
682: // ([bd, An, Xn.SIZE*SCALE], od)
683: case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
684: eWord1 = Disass68kGetWord(*addr); *addr += 2;
685: xn = (eWord1 >> 12) & 0x0F; // Register D0..D7/A0..A7
686: c = ((eWord1 >> 11) & 1) ? 'l' : 'w'; // Word/Long-Word Index Size 0 = Sign-Extended Word 1 = Long Word
687: scale = (eWord1 >> 9) & 3; // Scale Factor 00 = 1 01 = 2 10 = 4 11 = 8
688: char regName[3];
689: if(ea == 0x3B)
690: {
691: sp = Disass68kSpecialRegister(REG_PC);
692: if(!sp) return NULL;
693: strcpy(regName, sp);
694: } else {
695: sprintf(regName, "%s", Disass68kRegname(reg | 8));
696: }
697:
698: if((eWord1 & 0x0100) == 0)
699: {
700: // BRIEF EXTENSION WORD FORMAT
701: if(ea == 0x3B)
702: {
703: if((allowedEAs & EA_PCRel) != EA_PCRel)
704: break;
705: } else {
706: if((allowedEAs & EA_dAn) != EA_dAn)
707: break;
708: }
709:
710: // Address Register Indirect with Index (8-Bit Displacement) Mode
711: // (d8 ,An, Xn.SIZE*SCALE)
712: const char *numStr = Disass68kNumber(eWord1 & 0xFF);
713: if(numStr[0] == '0' && numStr[1] == 0)
714: numStr = "";
715:
716: // scale is only on 68020 and later supported
717: if(scale != 0 && (optionCPUTypeMask & MC_020) == 0)
718: return NULL;
719:
720: if(scale == 0)
721: {
722: #if ADDRESS_ON_PC
723: if(ea == 0x3B)
724: sprintf(disassbuf, "$%lx(%s,%s.%c)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c);
725: else
726: #endif
727: sprintf(disassbuf, "%s(%s,%s.%c)", numStr, regName, Disass68kRegname(xn), c);
728: } else
729: {
730: #if ADDRESS_ON_PC
731: if(ea == 0x3B)
732: sprintf(disassbuf, "$%lx(%s,%s.%c*%d)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c, 1 << scale);
733: else
734: #endif
735: sprintf(disassbuf, "%s(%s,%s.%c*%d)", numStr, regName, Disass68kRegname(xn), c, 1 << scale);
736: }
737: #if USE_SYMBOLS
738: if(ea == 0x3B)
739: {
740: const char *symStr = Disass68kSymbolName((signed char)(eWord1 & 0xFF) + opcodeAddr + 2, size);
741: if(symStr)
742: {
743: commentBuffer += strlen(commentBuffer);
744: sprintf(commentBuffer+strlen(commentBuffer), "%s", symStr);
745: }
746: }
747: #endif
748: #if !ADDRESS_ON_PC
749: if(ea == 0x3B)
750: {
751: commentBuffer += strlen(commentBuffer);
752: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2);
753: }
754: #endif
755: } else {
756: // FULL EXTENSION WORD FORMAT
757:
758: int bs = (eWord1 >> 7) & 1; // Base Register Suppress 0 = Base Register Added 1 = Base Register Suppressed
759: int is = (eWord1 >> 6) & 1; // Index Suppress 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand
760: int bdSize = (eWord1 >> 4) & 3; // Base Displacement Size 00 = Reserved 01 = Null Displacement 10 = Word Displacement 11 = Long Displacement
761: int iis = eWord1 & 7; // Index/Indirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
762: bool prefixComma;
763:
764: // reserved, has to be 0
765: if((eWord1 & 8) != 0 || bdSize == 0 || (is && iis > 3) || iis == 4)
766: break;
767:
768: // full extension format is only supported on 68020 or later
769: if((optionCPUTypeMask & MC_020) == 0)
770: return NULL;
771:
772: if(ea == 0x3B)
773: {
774: if((allowedEAs & EA_PCRel) != EA_PCRel)
775: break;
776: } else {
777: if((allowedEAs & EA_dAn) != EA_dAn)
778: break;
779: }
780:
781: long bd = 0;
782: switch(bdSize)
783: {
784: case 3:
785: bd = Disass68kGetWord(*addr); *addr += 2;
786: bd <<= 16;
787: case 2:
788: bd |= Disass68kGetWord(*addr); *addr += 2;
789: break;
790: default:
791: break;
792: }
793:
794: prefixComma = false;
795: if(bdSize >= 2 && iis == 0)
796: sprintf(disassbuf, "%s", Disass68kNumber(bd));
797: strcat(disassbuf, "(");
798: if(iis != 0)
799: {
800: // the CPU32 doesn't support the memory indirect mode
801: if(optionCPUTypeMask & MC_CPU32)
802: return NULL;
803:
804: strcat(disassbuf, "[");
805: }
806: if(bdSize >= 2 && iis != 0)
807: {
808: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(bd));
809: prefixComma = true;
810: }
811: if(bdSize == 1 && ((bs && is && iis > 0) || (bs && iis >= 5)))
812: {
813: if(ea == 0x3B)
814: {
815: sp = Disass68kSpecialRegister(REG_ZPC);
816: if(!sp) return NULL;
817: strcat(disassbuf, sp);
818: } else {
819: strcat(disassbuf, "0");
820: }
821: }
822: if(!bs)
823: {
824: if(prefixComma)
825: strcat(disassbuf, ",");
826: strcat(disassbuf, regName);
827: prefixComma = true;
828: }
829: if(iis >= 5 && iis <= 7)
830: {
831: strcat(disassbuf, "]");
832: prefixComma = true;
833: }
834: if(!is)
835: {
836: if(prefixComma)
837: strcat(disassbuf, ",");
838: if(scale == 0)
839: {
840: sprintf(disassbuf+strlen(disassbuf), "%s.%c", Disass68kRegname(xn), c);
841: } else
842: {
843: sprintf(disassbuf+strlen(disassbuf), "%s.%c*%d", Disass68kRegname(xn), c, 1 << scale);
844: }
845: }
846: if(iis >= 1 && iis <= 3)
847: {
848: strcat(disassbuf, "]");
849: prefixComma = true;
850: }
851: long od = 0;
852: switch(iis & 3)
853: {
854: case 3:
855: od = Disass68kGetWord(*addr); *addr += 2;
856: od <<= 16;
857: case 2:
858: od |= Disass68kGetWord(*addr); *addr += 2;
859: if(prefixComma)
860: strcat(disassbuf, ",");
861: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(od));
862: break;
863: default:
864: break;
865: }
866: strcat(disassbuf, ")");
867: }
868: break;
869:
870: // M=111 = 7, Xn/reg = 000 = 0
871: // Absolute Short Addressing Mode
872: // (xxx).W
873: case 0x38:
874: if((allowedEAs & EA_Abs) != EA_Abs)
875: break;
876: eWord1 = Disass68kGetWord(*addr); *addr += 2;
877: val = eWord1;
878: if(eWord1 & 0x8000)
879: val |= 0xFFFF0000;
880: #if USE_SYMBOLS
881: sp = Disass68kSymbolName(val, size);
882: if(sp)
883: {
884: if(options & doptNoBrackets)
885: sprintf(disassbuf, "%s.w", sp);
886: else
887: sprintf(disassbuf, "(%s).w", sp);
888: break;
889: }
890: #endif
891: if(options & doptNoBrackets)
892: {
893: if(val & 0x80000000)
894: sprintf(disassbuf, "$%8.8lx.w", val);
895: else
896: sprintf(disassbuf, "$%4.4lx.w", val);
897: } else {
898: if(val & 0x80000000)
899: sprintf(disassbuf, "($%8.8lx).w", val);
900: else
901: sprintf(disassbuf, "($%4.4lx).w", val);
902: }
903: break;
904:
905: // M=111 = 7, Xn/reg = 001 = 1
906: // Absolute Long Addressing Mode
907: // (xxx).L
908: case 0x39:
909: if((allowedEAs & EA_Abs) != EA_Abs)
910: break;
911: eWord1 = Disass68kGetWord(*addr); *addr += 2;
912: eWord2 = Disass68kGetWord(*addr); *addr += 2;
913: #if USE_SYMBOLS
914: val = (eWord1 << 16) | eWord2;
915: sp = Disass68kSymbolName(val, size);
916: if(sp)
917: {
918: if(options & doptNoBrackets)
919: sprintf(disassbuf, "%s", sp);
920: else
921: sprintf(disassbuf, "(%s).l", sp);
922: break;
923: }
924: #endif
925: if(options & doptNoBrackets)
926: sprintf(disassbuf, "%s", Disass68kNumber((eWord1 << 16) | eWord2));
927: else
928: sprintf(disassbuf, "(%s).l", Disass68kNumber((eWord1 << 16) | eWord2));
929: break;
930:
931: // M=111 = 7, Xn/reg = 010 = 2
932: // Program Counter Indirect with Displacement Mode
933: // (d16,PC)
934: case 0x3A:
935: if((allowedEAs & EA_PCRel) != EA_PCRel)
936: break;
937: eWord1 = Disass68kGetWord(*addr); *addr += 2;
938: sp = Disass68kSpecialRegister(REG_PC);
939: if(!sp) return NULL;
940: #if ADDRESS_ON_PC
941: #if USE_SYMBOLS
942: sp = Disass68kSymbolName(((signed short)eWord1 + *addr - 2), size);
943: if(sp)
944: {
945: sprintf(disassbuf, "%s(%s)", sp, Disass68kSpecialRegister(REG_PC));
946: } else {
947: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
948: }
949: #else
950: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
951: #endif
952: #else
953: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1),sp);
954: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed short)eWord1 + *addr - 2);
955: #endif
956: break;
957:
958: // M=111 = 7, Xn/reg = 100 = 4
959: // Immediate Data
960: // #<xxx>
961: case 0x3C:
962: if((allowedEAs & EA_Immed) != EA_Immed)
963: break;
964: eWord1 = Disass68kGetWord(*addr); *addr += 2;
965: goto immed;
966:
967: case 0x0100: // Immediate Value as a parameter
968: if((allowedEAs & EA_ImmedParameter) != EA_ImmedParameter)
969: break;
970: eWord1 = parameterValue;
971: immed:
972: switch(size)
973: {
974: case 1: eWord1 &= 0xFF;
975: case 2:
976: #if USE_SYMBOLS
977: if(disassFlag)
978: {
979: val = eWord1;
980: if(eWord1 & 0x8000)
981: val |= 0xFFFF0000;
982: sp = Disass68kSymbolName(val, size);
983: if(sp)
984: {
985: sprintf(disassbuf, "#%s", sp);
986: break;
987: }
988: }
989: #endif
990: sprintf(disassbuf, "#%s", Disass68kNumber(eWord1));
991: break;
992: case 4: eWord2 = Disass68kGetWord(*addr); *addr += 2;
993: #if USE_SYMBOLS
994: if(disassFlag)
995: {
996: val = (eWord1 << 16) | eWord2;
997: sp = Disass68kSymbolName(val, size);
998: if(sp)
999: {
1000: sprintf(disassbuf, "#%s", sp);
1001: break;
1002: }
1003: }
1004: #endif
1005: sprintf(disassbuf, "#%s", Disass68kNumber((eWord1 << 16) | eWord2));
1006: break;
1007: }
1008: break;
1009:
1010: case 0x0103:
1011: if((allowedEAs & EA_ValueParameter) != EA_ValueParameter)
1012: break;
1013: sprintf(disassbuf, "%d", parameterValue);
1014: break;
1015:
1016: case 0x0101: // Special Registers as in the parameter
1017: if((allowedEAs & EA_SpecialRegister) != EA_SpecialRegister)
1018: break;
1019: sp = Disass68kSpecialRegister(parameterValue);
1020: if(!sp) return NULL;
1021: strcpy(disassbuf, sp);
1022: break;
1023:
1024: case 0x0102: // PC relative jump, like for BRA and friends
1025: if((allowedEAs & EA_PCDisplacement) != EA_PCDisplacement)
1026: break;
1027: signed long pcoffset = 0;
1028: switch(size)
1029: {
1030: case 1: pcoffset = (signed char)parameterValue;
1031: break;
1032: case 2: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1033: pcoffset = (signed short)eWord1;
1034: pcoffset -= 2;
1035: break;
1036: case 4: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1037: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1038: pcoffset = (signed int)((eWord1 << 16) | eWord2);
1039: pcoffset -= 4;
1040: break;
1041: }
1042: #if ADDRESS_ON_PC
1043: #if USE_SYMBOLS
1044: sp = Disass68kSymbolName((*addr + pcoffset), size);
1045: if(sp)
1046: {
1047: strcat(disassbuf, sp);
1048: } else {
1049: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1050: }
1051: #else
1052: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1053: #endif
1054: #else
1055: if(pcoffset < 0)
1056: {
1057: sprintf(disassbuf, "*-$%lx", -pcoffset - 2);
1058: } else {
1059: sprintf(disassbuf, "*+$%lx", pcoffset + 2);
1060: }
1061: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", *addr + pcoffset);
1062: #endif
1063: break;
1064:
1065: default: // 0x3D..0x3F are reserved
1066: break;
1067:
1068: }
1069: if(disassbuf[0] == 0)
1070: return NULL;
1071: return disassbuf + strlen(disassbuf);
1072: }
1073:
1074: /***
1075: * Create a register list for the MOVEM opcode
1076: ***/
1077: static char *Disass68kReglist(char *buf, unsigned short reglist)
1078: {
1079: int bit;
1080: int lastBit = -99;
1081: int lastBitStart = -99;
1082: char regD = options & doptRegisterSmall ? 'd' : 'D';
1083: char regA = options & doptRegisterSmall ? 'a' : 'A';
1084: for(bit=0; bit<=15; ++bit)
1085: {
1086: // bit clear?
1087: if((reglist & (1 << bit)) == 0)
1088: {
1089: // do we have a run? => close it!
1090: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1091: {
1092: *buf++ = '-';
1093: *buf++ = ((bit-1) >= 8) ? regA : regD;
1094: *buf++ = '0' + ((bit-1) & 7);
1095: }
1096: lastBitStart = -1;
1097: continue;
1098: }
1099: // reset when switching from D to A
1100: if(bit == 8 && lastBitStart >= 0)
1101: {
1102: *buf++ = '-';
1103: *buf++ = regD;
1104: *buf++ = '7';
1105: lastBit = 0;
1106: lastBitStart = -99;
1107: }
1108: // separate bits, skip runs of bits to merge them later
1109: if(lastBit >= 0)
1110: {
1111: if(lastBit == bit - 1)
1112: {
1113: lastBit = bit;
1114: continue;
1115: }
1116: *buf++ = '/';
1117: }
1118: *buf++ = (bit >= 8) ? regA : regD;
1119: *buf++ = '0' + (bit & 7);
1120: lastBit = bit;
1121: lastBitStart = bit;
1122: }
1123: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1124: {
1125: *buf++ = '-';
1126: *buf++ = regA;
1127: *buf++ = '7';
1128: }
1129: if(lastBit < 0)
1130: {
1131: *buf++ = '0';
1132: }
1133: *buf = 0;
1134: return buf;
1135: }
1136:
1137: /***
1138: * Flip the bits in an unsigned short, for MOVEM RegList,-(An)
1139: ***/
1140: static unsigned short Disass68kFlipBits(unsigned short mask)
1141: {
1142: unsigned short retMask = 0;
1143: int i;
1144:
1145: for(i=0; i<=15; ++i)
1146: if(mask & (1 << i))
1147: retMask |= (1 << (15-i));
1148: return retMask;
1149: }
1150:
1151: /***
1152: * Create a register list for the MOVEM opcode
1153: ***/
1154: static char *Disass68kFPUReglist(char *buf, unsigned char reglist)
1155: {
1156: int bit;
1157: int lastBit = -99;
1158: int lastBitStart = -99;
1159: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
1160: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
1161: for(bit=0; bit<=7; ++bit)
1162: {
1163: // bit clear?
1164: if((reglist & (1 << bit)) == 0)
1165: {
1166: // do we have a run? => close it!
1167: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1168: {
1169: *buf++ = '-';
1170: *buf++ = regFP1;
1171: *buf++ = regFP2;
1172: *buf++ = '0' + ((bit-1) & 7);
1173: }
1174: lastBitStart = -1;
1175: continue;
1176: }
1177: // separate bits, skip runs of bits to merge them later
1178: if(lastBit >= 0)
1179: {
1180: if(lastBit == bit - 1)
1181: {
1182: lastBit = bit;
1183: continue;
1184: }
1185: *buf++ = '/';
1186: }
1187: *buf++ = regFP1;
1188: *buf++ = regFP2;
1189: *buf++ = '0' + (bit & 7);
1190: lastBit = bit;
1191: lastBitStart = bit;
1192: }
1193: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1194: {
1195: *buf++ = '-';
1196: *buf++ = regFP1;
1197: *buf++ = regFP2;
1198: *buf++ = '7';
1199: }
1200: if(lastBit < 0)
1201: {
1202: *buf++ = '0';
1203: }
1204: *buf = 0;
1205: return buf;
1206: }
1207:
1208:
1209: /***
1210: * List of special cases for the operands
1211: ***/
1212: typedef enum {
1213: ofNone,
1214: ofEa,
1215: ofDn,
1216: ofAn,
1217: ofAni,
1218: ofI,
1219: ofSpecReg,
1220: ofSpecExtReg,
1221: ofD16An,
1222: ofDestDn,
1223: ofDestAn,
1224: ofExtReg,
1225: ofExtAnip,
1226: ofExtReg0,
1227: ofExtRegA0,
1228: ofExtRegD04,
1229: ofExtRegA05,
1230: ofFPUReglist,
1231: ofFPUSRRegList,
1232: ofDestEa6,
1233: ofDestAbsL,
1234: ofIOpcode,
1235: ofCAS,
1236: ofCAS2,
1237: ofI3,
1238: ofExtIm,
1239: ofExtIm32,
1240: ofExtIm4,
1241: ofExtIm10,
1242: ofDisp,
1243: ofPiAn,
1244: ofDestPiAn,
1245: ofAnip,
1246: ofDestAnip,
1247: ofBFEa,
1248: ofRegList,
1249: ofExt4Dn,
1250: ofFPU,
1251: ofFPUMOVE,
1252: ofFMOVECR,
1253: ofFPU3Reg,
1254: ofLineA,
1255: } Disass68kOpcodeFormat;
1256:
1257:
1258: /***
1259: * The order of the table is not important (with the exception of some FPU opcodes, which are commented further down),
1260: * as each opcode should decline if it doesn't match 100%. The 68k CPU also doesn't do guessing based on the context!
1261: ***/
1262: typedef const struct {
1263: int cpuMask;
1264: unsigned long opcodeMask[2*5];
1265: char operationSize[4];
1266: char op[5];
1267: const char *opcodeName;
1268: int parameter[5];
1269: int disassFlag;
1270: } OpcodeTableStruct;
1271:
1272: static const OpcodeTableStruct OpcodeTable[] = {
1273: { MC_ALL, {0xff00, 0x0000}, {-1,6,2,0}, {ofI,ofEa}, "ORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1274: { MC_ALL, {0xf1c0, 0x0100}, {4}, {ofDestDn,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1275: { MC_ALL, {0xf1c0, 0x0140}, {4}, {ofDestDn,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1276: { MC_ALL, {0xf1c0, 0x0180}, {4}, {ofDestDn,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1277: { MC_ALL, {0xf1c0, 0x01C0}, {4}, {ofDestDn,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1278: { MC_ALL-MC68060, {0xf1f8, 0x0108}, {2}, {ofD16An,ofDestDn}, "MOVEP.W"},
1279: { MC_ALL-MC68060, {0xf1f8, 0x0148}, {4}, {ofD16An,ofDestDn}, "MOVEP.L"},
1280: { MC_ALL-MC68060, {0xf1f8, 0x0188}, {2}, {ofDestDn,ofD16An}, "MOVEP.W"},
1281: { MC_ALL-MC68060, {0xf1f8, 0x01C8}, {4}, {ofDestDn,ofD16An}, "MOVEP.L"},
1282: { MC_ALL, {0xff00, 0x0200}, {-1,6,2,0}, {ofI,ofEa}, "ANDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1283: { MC_ALL, {0xff00, 0x0400}, {-1,6,2,0}, {ofI,ofEa}, "SUBI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1284: { MC_ALL, {0xff00, 0x0600}, {-1,6,2,0}, {ofI,ofEa}, "ADDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1285: { MC_ALL, {0xffc0, 0x0800}, {1}, {ofI,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1286: { MC_ALL, {0xffc0, 0x0840}, {1}, {ofI,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1287: { MC_ALL, {0xffc0, 0x0880}, {1}, {ofI,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1288: { MC_ALL, {0xffc0, 0x08C0}, {1}, {ofI,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1289: { MC_ALL, {0xff00, 0x0A00}, {-1,6,2,0}, {ofI,ofEa}, "EORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1290: { MC_ALL, {0xff00, 0x0C00}, {-1,6,2,0}, {ofI,ofEa}, "CMPI.?",{0,EA_Immed|EA_An}},
1291: { MC_ALL, {0xffff, 0x003C}, {1}, {ofEa,ofSpecReg}, "ORI",{0,REG_CCR} },
1292: { MC_ALL, {0xffff, 0x007C}, {2}, {ofEa,ofSpecReg}, "ORI",{0,REG_SR} },
1293: { MC_ALL, {0xffff, 0x023C}, {1}, {ofEa,ofSpecReg}, "ANDI",{0,REG_CCR} },
1294: { MC_ALL, {0xffff, 0x027C}, {2}, {ofEa,ofSpecReg}, "ANDI",{0,REG_SR} },
1295: { MC_ALL, {0xffff, 0x0A3C}, {1}, {ofEa,ofSpecReg}, "EORI",{0,REG_CCR} },
1296: { MC_ALL, {0xffff, 0x0A7C}, {2}, {ofEa,ofSpecReg}, "EORI",{0,REG_SR} },
1297: { MC68020, {0xffc0, 0x06C0}, {1}, {ofEa}, "CALLM",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1298: { MC68020, {0xfff0, 0x06C0}, {1}, {ofEa}, "RTM"},
1299: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0000}, {-1,9,2,0}, {ofEa,ofExtReg}, "CMP2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1300: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0800}, {-1,9,2,0}, {ofEa,ofExtReg}, "CHK2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1301: { MC_020&~MC_CPU32, {0xffc0, 0x0AC0, 0xFE38,0x0000}, {1}, {ofCAS,ofEa}, "CAS.B",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1302: { MC_020&~MC_CPU32, {0xffc0, 0x0CC0, 0xFE38,0x0000}, {2}, {ofCAS,ofEa}, "CAS.W",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1303: { MC_020&~MC_CPU32, {0xffc0, 0x0EC0, 0xFE38,0x0000}, {4}, {ofCAS,ofEa}, "CAS.L",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1304: { MC_020&~MC_CPU32, {0xffff, 0x0CFC, 0x0E38,0x0000, 0x0E38,0x0000}, {2}, {ofCAS2}, "CAS2.W"},
1305: { MC_020&~MC_CPU32, {0xffff, 0x0EFC, 0x0E38,0x0000, 0x0E38,0x0000}, {4}, {ofCAS2}, "CAS2.L"},
1306: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0000}, {-1,6,2,0}, {ofEa,ofExtReg}, "MOVES.?",{EA_Immed|EA_PCRel|EA_An|EA_Dn,0}},
1307: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0800}, {-1,6,2,0}, {ofExtReg,ofEa}, "MOVES.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1308:
1309: { MC_ALL, {0xf000, 0x1000}, {1}, {ofEa,ofDestEa6}, "MOVE.B"},
1310:
1311: { MC_ALL, {0xf000, 0x2000}, {4}, {ofEa,ofDestEa6}, "MOVE.L"},
1312: { MC_ALL, {0xf1c0, 0x2040}, {4}, {ofEa,ofDestAn}, "MOVEA.L",{0},1},
1313:
1314: { MC_ALL, {0xf000, 0x3000}, {2}, {ofEa,ofDestEa6}, "MOVE.W"},
1315: { MC_ALL, {0xf1c0, 0x3040}, {2}, {ofEa,ofDestAn}, "MOVEA.W",{0},1},
1316:
1317: { MC_ALL, {0xff00, 0x4000}, {-1,6,2,0}, {ofEa}, "NEGX.?",{EA_Immed|EA_PCRel|EA_An}},
1318: { MC_020, {0xf1c0, 0x4100}, {4}, {ofEa,ofDestDn}, "CHK.L", {EA_An,0}},
1319: { MC_ALL, {0xf1c0, 0x4180}, {2}, {ofEa,ofDestDn}, "CHK.W", {EA_An,0}},
1320: { MC_ALL, {0xf1c0, 0x41c0}, {4}, {ofEa,ofDestAn}, "LEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn,0},1 },
1321: { MC_ALL, {0xff00, 0x4200}, {-1,6,2,0}, {ofEa}, "CLR.?",{EA_Immed|EA_PCRel|EA_An}},
1322: { MC_ALL, {0xff00, 0x4400}, {-1,6,2,0}, {ofEa}, "NEG.?",{EA_Immed|EA_PCRel|EA_An}},
1323: { MC_ALL, {0xff00, 0x4600}, {-1,6,2,0}, {ofEa}, "NOT.?",{EA_Immed|EA_PCRel|EA_An}},
1324: { MC_ALL, {0xffc0, 0x40c0}, {2}, {ofSpecReg,ofEa}, "MOVE",{REG_SR,EA_Immed|EA_PCRel|EA_An} },
1325: { MC_ALL, {0xffc0, 0x42c0}, {1}, {ofSpecReg,ofEa}, "MOVE",{REG_CCR,EA_Immed|EA_PCRel|EA_An} },
1326: { MC_ALL, {0xffc0, 0x44c0}, {1}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_CCR} },
1327: { MC_ALL, {0xffc0, 0x46c0}, {2}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_SR} },
1328: { MC_ALL, {0xffc0, 0x4800}, {1}, {ofEa}, "NBCD",{EA_Immed|EA_PCRel|EA_An}},
1329: { MC_020, {0xfff8, 0x4808}, {4}, {ofEa,ofI}, "LINK.L"},
1330: { MC_ALL, {0xffc0, 0x4840}, {0}, {ofEa}, "PEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn},1 },
1331: { MC_ALL, {0xfff8, 0x4840}, {4}, {ofEa}, "SWAP"},
1332: { MC68010|MC_020, {0xfff8, 0x4848}, {0}, {ofIOpcode}, "BKPT",{0x07} },
1333: { MC_ALL, {0xffc0, 0x4880, 0x10000}, {2}, {ofRegList,ofEa}, "MOVEM.W",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1334: { MC_ALL, {0xffc0, 0x48c0, 0x10000}, {4}, {ofRegList,ofEa}, "MOVEM.L",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1335: { MC_ALL, {0xfff8, 0x4880}, {2}, {ofEa}, "EXT.W"},
1336: { MC_ALL, {0xfff8, 0x48c0}, {4}, {ofEa}, "EXT.L"},
1337: { MC_020, {0xfff8, 0x49c0}, {4}, {ofEa}, "EXTB.L"},
1338: { MC_ALL, {0xff00, 0x4a00}, {-1,6,2,0}, {ofEa}, "TST.?"},
1339: { MC_ALL, {0xffc0, 0x4ac0}, {1}, {ofEa}, "TAS",{EA_Immed|EA_PCRel|EA_An}},
1340: { MC_CPU32, {0xffff, 0x4afa}, {0}, {ofNone}, "BGND"},
1341: { MC_ALL, {0xffff, 0x4afc}, {0}, {ofNone}, "ILLEGAL"},
1342: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "MULU.L", {EA_An,0}},
1343: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "MULS.L", {EA_An,0}},
1344: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "DIVU.L", {EA_An,0}},
1345: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "DIVS.L", {EA_An,0}},
1346: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULU.L", {EA_An,0,0}},
1347: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULS.L", {EA_An,0,0}},
1348: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVU.L", {EA_An,0,0}},
1349: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVS.L", {EA_An,0,0}},
1350: { MC_ALL, {0xffc0, 0x4c80, 0x10000}, {2}, {ofEa,ofRegList}, "MOVEM.W",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1351: { MC_ALL, {0xffc0, 0x4cc0, 0x10000}, {4}, {ofEa,ofRegList}, "MOVEM.L",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1352: { MC_ALL, {0xfff0, 0x4e40}, {0}, {ofIOpcode}, "TRAP",{0x0f} },
1353: { MC_ALL, {0xfff8, 0x4e50}, {2}, {ofAn,ofI}, "LINK"},
1354: { MC_ALL, {0xfff8, 0x4e58}, {4}, {ofAn}, "UNLK"},
1355: { MC_ALL, {0xfff8, 0x4e60}, {4}, {ofAn,ofSpecReg}, "MOVE",{0,REG_USP} },
1356: { MC_ALL, {0xfff8, 0x4e68}, {4}, {ofSpecReg,ofAn}, "MOVE",{REG_USP,0} },
1357: { MC_ALL, {0xffff, 0x4e70}, {0}, {ofNone}, "RESET"},
1358: { MC_ALL, {0xffff, 0x4e71}, {0}, {ofNone}, "NOP"},
1359: { MC_ALL, {0xffff, 0x4e72}, {2}, {ofI}, "STOP"},
1360: { MC_ALL, {0xffff, 0x4e73}, {0}, {ofNone}, "RTE"},
1361: { MC68010|MC_020, {0xffff, 0x4e74}, {2}, {ofI}, "RTD"},
1362: { MC_ALL, {0xffff, 0x4e75}, {0}, {ofNone}, "RTS"},
1363: { MC_ALL, {0xffff, 0x4e76}, {0}, {ofNone}, "TRAPV"},
1364: { MC_ALL, {0xffff, 0x4e77}, {0}, {ofNone}, "RTR"},
1365: { MC68010|MC_020, {0xffff, 0x4e7a, 0x10000}, {4}, {ofSpecExtReg,ofExtReg}, "MOVEC"},
1366: { MC68010|MC_020, {0xffff, 0x4e7b, 0x10000}, {4}, {ofExtReg,ofSpecExtReg}, "MOVEC"},
1367: { MC_ALL, {0xffc0, 0x4e80}, {0}, {ofEa}, "JSR",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1368: { MC_ALL, {0xffc0, 0x4ec0}, {0}, {ofEa}, "JMP",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1369:
1370: { MC_ALL, {0xf1c0, 0x5000}, {1}, {ofI3,ofEa}, "ADDQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1371: { MC_ALL, {0xf1c0, 0x5040}, {2}, {ofI3,ofEa}, "ADDQ.W",{0,EA_Immed|EA_PCRel} },
1372: { MC_ALL, {0xf1c0, 0x5080}, {4}, {ofI3,ofEa}, "ADDQ.L",{0,EA_Immed|EA_PCRel} },
1373: { MC_ALL, {0xf0c0, 0x50C0}, {1}, {ofEa}, "Sci",{EA_Immed|EA_PCRel|EA_An}},
1374: { MC_ALL, {0xf0f8, 0x50C8}, {2}, {ofDn,ofDisp}, "DBcd"},
1375: { MC_020, {0xf0ff, 0x50fa}, {2}, {ofI}, "TRAPci.W"},
1376: { MC_020, {0xf0ff, 0x50fb}, {4}, {ofI}, "TRAPci.L"},
1377: { MC_020, {0xf0ff, 0x50fc}, {0}, {ofNone}, "TRAPci"},
1378: { MC_ALL, {0xf1c0, 0x5100}, {1}, {ofI3,ofEa}, "SUBQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1379: { MC_ALL, {0xf1c0, 0x5140}, {2}, {ofI3,ofEa}, "SUBQ.W",{0,EA_Immed|EA_PCRel} },
1380: { MC_ALL, {0xf1c0, 0x5180}, {4}, {ofI3,ofEa}, "SUBQ.L",{0,EA_Immed|EA_PCRel} },
1381:
1382: { MC_ALL, {0xf0ff, 0x6000}, {2}, {ofDisp}, "Bcb"},
1383: { MC_ALL, {0xf000, 0x6000}, {1}, {ofDisp}, "Bcb.S"},
1384: { MC_020, {0xf0ff, 0x60FF}, {4}, {ofDisp}, "Bcb.L"},
1385:
1386: { MC_ALL, {0xf100, 0x7000}, {0}, {ofIOpcode,ofDestDn}, "MOVEQ", {0xFF,0}},
1387:
1388: { MC_ALL, {0xf100, 0x8000}, {-1,6,2,0}, {ofEa,ofDestDn}, "OR.?", {EA_An,0}},
1389: { MC_ALL, {0xf100, 0x8100}, {-1,6,2,0}, {ofDestDn,ofEa}, "OR.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1390: { MC_ALL, {0xf1f8, 0x8100}, {1}, {ofDn,ofDestDn}, "SBCD"},
1391: { MC_ALL, {0xf1f8, 0x8108}, {1}, {ofPiAn,ofDestPiAn}, "SBCD"},
1392: { MC_020&~MC_CPU32, {0xf1f8, 0x8140, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "PACK"},
1393: { MC_020&~MC_CPU32, {0xf1f8, 0x8148, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "PACK"},
1394: { MC_020&~MC_CPU32, {0xf1f8, 0x8180, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "UNPK"},
1395: { MC_020&~MC_CPU32, {0xf1f8, 0x8188, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "UNPK"},
1396: { MC_ALL, {0xf1c0, 0x80c0}, {2}, {ofEa,ofDestDn}, "DIVU.W", {EA_An,0}},
1397: { MC_ALL, {0xf1c0, 0x81c0}, {2}, {ofEa,ofDestDn}, "DIVS.W", {EA_An,0}},
1398:
1399: { MC_ALL, {0xf1c0, 0x9000}, {1}, {ofEa,ofDestDn}, "SUB.B", {EA_An,0}},
1400: { MC_ALL, {0xf1c0, 0x9040}, {2}, {ofEa,ofDestDn}, "SUB.W"},
1401: { MC_ALL, {0xf1c0, 0x9080}, {4}, {ofEa,ofDestDn}, "SUB.L"},
1402: { MC_ALL, {0xf1c0, 0x90c0}, {2}, {ofEa,ofDestAn}, "SUBA.W"},
1403: { MC_ALL, {0xf1c0, 0x91c0}, {4}, {ofEa,ofDestAn}, "SUBA.L"},
1404: { MC_ALL, {0xf100, 0x9100}, {-1,6,2,0}, {ofDestDn,ofEa}, "SUB.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1405: { MC_ALL, {0xf138, 0x9100}, {-1,6,2,0}, {ofDn,ofDestDn}, "SUBX.?"},
1406: { MC_ALL, {0xf138, 0x9108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "SUBX.?"},
1407:
1408: { MC_ALL, {0xf000, 0xa000}, {0}, {ofLineA}, "LINEA"},
1409:
1410: { MC_ALL, {0xf1c0, 0xb000}, {1}, {ofEa,ofDestDn}, "CMP.B", {EA_An,0}},
1411: { MC_ALL, {0xf1c0, 0xb040}, {2}, {ofEa,ofDestDn}, "CMP.W"},
1412: { MC_ALL, {0xf1c0, 0xb080}, {4}, {ofEa,ofDestDn}, "CMP.L"},
1413: { MC_ALL, {0xf1c0, 0xb0c0}, {2}, {ofEa,ofDestAn}, "CMPA.W"},
1414: { MC_ALL, {0xf1c0, 0xb1c0}, {4}, {ofEa,ofDestAn}, "CMPA.L"},
1415: { MC_ALL, {0xf100, 0xb100}, {-1,6,2,0}, {ofDestDn,ofEa}, "EOR.?",{0,EA_An|EA_Immed|EA_PCRel} },
1416: { MC_ALL, {0xf138, 0xb108}, {-1,6,2,0}, {ofAnip,ofDestAnip}, "CMPM.?"},
1417:
1418: { MC_ALL, {0xf100, 0xc000}, {-1,6,2,0}, {ofEa,ofDestDn}, "AND.?", {EA_An,0}},
1419: { MC_ALL, {0xf100, 0xc100}, {-1,6,2,0}, {ofDestDn,ofEa}, "AND.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1420: { MC_ALL, {0xf1f8, 0xc100}, {1}, {ofDn,ofDestDn}, "ABCD"},
1421: { MC_ALL, {0xf1f8, 0xc108}, {1}, {ofPiAn,ofDestPiAn}, "ABCD"},
1422: { MC_ALL, {0xf1f8, 0xc140}, {1}, {ofDestDn,ofDn}, "EXG"},
1423: { MC_ALL, {0xf1f8, 0xc148}, {1}, {ofDestAn,ofAn}, "EXG"},
1424: { MC_ALL, {0xf1f8, 0xc188}, {1}, {ofDestDn,ofAn}, "EXG"},
1425: { MC_ALL, {0xf1c0, 0xc0c0}, {2}, {ofEa,ofDestDn}, "MULU.W", {EA_An,0}},
1426: { MC_ALL, {0xf1c0, 0xc1c0}, {2}, {ofEa,ofDestDn}, "MULS.W", {EA_An,0}},
1427:
1428: { MC_ALL, {0xf1c0, 0xd000}, {1}, {ofEa,ofDestDn}, "ADD.B", {EA_An,0}},
1429: { MC_ALL, {0xf1c0, 0xd040}, {2}, {ofEa,ofDestDn}, "ADD.W"},
1430: { MC_ALL, {0xf1c0, 0xd080}, {4}, {ofEa,ofDestDn}, "ADD.L"},
1431: { MC_ALL, {0xf1c0, 0xd0c0}, {2}, {ofEa,ofDestAn}, "ADDA.W"},
1432: { MC_ALL, {0xf1c0, 0xd1c0}, {4}, {ofEa,ofDestAn}, "ADDA.L"},
1433: { MC_ALL, {0xf100, 0xd100}, {-1,6,2,0}, {ofDestDn,ofEa}, "ADD.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1434: { MC_ALL, {0xf138, 0xd100}, {-1,6,2,0}, {ofDn,ofDestDn}, "ADDX.?"},
1435: { MC_ALL, {0xf138, 0xd108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "ADDX.?"},
1436:
1437: { MC_ALL, {0xf138, 0xe000}, {-1,6,2,0}, {ofI3,ofDn}, "ASR.?"},
1438: { MC_ALL, {0xf138, 0xe008}, {-1,6,2,0}, {ofI3,ofDn}, "LSR.?"},
1439: { MC_ALL, {0xf138, 0xe010}, {-1,6,2,0}, {ofI3,ofDn}, "ROXR.?"},
1440: { MC_ALL, {0xf138, 0xe018}, {-1,6,2,0}, {ofI3,ofDn}, "ROR.?"},
1441: { MC_ALL, {0xf138, 0xe020}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASR.?"},
1442: { MC_ALL, {0xf138, 0xe028}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSR.?"},
1443: { MC_ALL, {0xf138, 0xe030}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXR.?"},
1444: { MC_ALL, {0xf138, 0xe038}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROR.?"},
1445: { MC_ALL, {0xf138, 0xe100}, {-1,6,2,0}, {ofI3,ofDn}, "ASL.?"},
1446: { MC_ALL, {0xf138, 0xe108}, {-1,6,2,0}, {ofI3,ofDn}, "LSL.?"},
1447: { MC_ALL, {0xf138, 0xe110}, {-1,6,2,0}, {ofI3,ofDn}, "ROXL.?"},
1448: { MC_ALL, {0xf138, 0xe118}, {-1,6,2,0}, {ofI3,ofDn}, "ROL.?"},
1449: { MC_ALL, {0xf138, 0xe120}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASL.?"},
1450: { MC_ALL, {0xf138, 0xe128}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSL.?"},
1451: { MC_ALL, {0xf138, 0xe130}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXL.?"},
1452: { MC_ALL, {0xf138, 0xe138}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROL.?"},
1453: { MC_ALL, {0xffc0, 0xe0c0}, {1}, {ofEa}, "ASR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1454: { MC_ALL, {0xffc0, 0xe1c0}, {1}, {ofEa}, "ASL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1455: { MC_ALL, {0xffc0, 0xe2c0}, {1}, {ofEa}, "LSR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1456: { MC_ALL, {0xffc0, 0xe3c0}, {1}, {ofEa}, "LSL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1457: { MC_ALL, {0xffc0, 0xe4c0}, {1}, {ofEa}, "ROXR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1458: { MC_ALL, {0xffc0, 0xe5c0}, {1}, {ofEa}, "ROXL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1459: { MC_ALL, {0xffc0, 0xe6c0}, {1}, {ofEa}, "ROR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1460: { MC_ALL, {0xffc0, 0xe7c0}, {1}, {ofEa}, "ROL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1461: { MC_020&~MC_CPU32, {0xffc0, 0xe8c0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFTST",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1462: { MC_020&~MC_CPU32, {0xffc0, 0xe9c0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTU",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1463: { MC_020&~MC_CPU32, {0xffc0, 0xeac0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCHG",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1464: { MC_020&~MC_CPU32, {0xffc0, 0xebc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTS",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1465: { MC_020&~MC_CPU32, {0xffc0, 0xecc0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCLR",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1466: { MC_020&~MC_CPU32, {0xffc0, 0xedc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFFFO",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1467: { MC_020&~MC_CPU32, {0xffc0, 0xeec0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFSET",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1468: { MC_020&~MC_CPU32, {0xffc0, 0xefc0, 0x8000, 0x0000}, {1}, {ofExtReg,ofBFEa}, "BFINS",{0,EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1469:
1470:
1471: #define PMMU_COPROC_ID 0 // 0 is the standard PMMU
1472:
1473: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2000}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1474: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2001}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1475: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2008}, {0}, {ofExtReg0,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1476: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2010}, {0}, {ofExtIm4,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1477:
1478: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2200}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1479: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2201}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1480: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2208}, {0}, {ofExtReg0,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1481: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2210}, {0}, {ofExtIm4,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1482:
1483: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0xa000}, {0}, {ofEa}, "PFLUSHR",{EA_Dn|EA_An} },
1484:
1485: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1486: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1487: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1488: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1489: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1490: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1491: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0E00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1492: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0F00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1493: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1494: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4100}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1495: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1496: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4300}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1497: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1498: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1499: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4A00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1500: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1501: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1502: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1503: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4e00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1504: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4f00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1505: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1506: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1507:
1508: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2800}, {0}, {ofSpecReg,ofEa}, "PVALID",{REG_VAL,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1509: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2C00}, {0}, {ofExtRegA0,ofEa}, "PVALID",{0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1510:
1511: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8000}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1512: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8001}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1513: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8008}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1514: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8010}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1515:
1516: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8200}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1517: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8201}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1518: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8208}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1519: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8210}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1520:
1521: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8100}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1522: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8101}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1523: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8108}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1524: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8110}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1525:
1526: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8300}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1527: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8301}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1528: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8308}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1529: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8310}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1530:
1531: { MC_PMMU, {0xffc0, 0xf040|(PMMU_COPROC_ID<<9), 0xfff0, 0x8310}, {0}, {ofEa}, "PScp",{EA_An|EA_Immed|EA_PCRel} },
1532: { MC_PMMU, {0xfff8, 0xf048|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {2}, {ofDn,ofDisp}, "PDBcp"},
1533: { MC_PMMU, {0xffff, 0xf07A|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "PTRAPcp.W" },
1534: { MC_PMMU, {0xffff, 0xf07B|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "PTRAPcp.L" },
1535: { MC_PMMU, {0xffff, 0xf07C|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "PTRAPcp" },
1536: { MC_PMMU, {0xfff0, 0xf080|(PMMU_COPROC_ID<<9)}, {2}, {ofDisp}, "PBcp.W"},
1537: { MC_PMMU, {0xfff0, 0xf0C0|(PMMU_COPROC_ID<<9)}, {4}, {ofDisp}, "PBcp.L"},
1538: { MC_PMMU, {0xffc0, 0xf100|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PSAVE",{EA_Dn|EA_An|EA_Anip|EA_Immed} },
1539: { MC_PMMU, {0xffc0, 0xf140|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PRESTORE",{EA_Dn|EA_An|EA_piAn|EA_Immed} },
1540:
1541:
1542: #define MC040_COPROC_ID 3 // 3 is the code for some 68040/68060 opcodes
1543:
1544: { MC68040|MC68060, {0xfff8, 0xf000|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofDestAbsL}, "MOVE16"},
1545: { MC68040|MC68060, {0xfff8, 0xf008|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAnip}, "MOVE16"},
1546: { MC68040|MC68060, {0xfff8, 0xf010|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAni,ofDestAbsL}, "MOVE16"},
1547: { MC68040|MC68060, {0xfff8, 0xf018|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAni}, "MOVE16"},
1548: { MC68040|MC68060, {0xfff8, 0xf020|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofExtAnip}, "MOVE16"},
1549:
1550:
1551: #define CPU32_COPROC_ID 4 // 4 is the code for some CPU32 opcodes
1552:
1553: { MC68040|MC68060, {0xfff8, 0xf008|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_NONE} },
1554: { MC68040|MC68060, {0xfff8, 0xf048|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_DC} },
1555: { MC68040|MC68060, {0xfff8, 0xf088|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_IC} },
1556: { MC68040|MC68060, {0xfff8, 0xf0C8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_ICDC} },
1557:
1558: { MC68040|MC68060, {0xfff8, 0xf010|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_NONE} },
1559: { MC68040|MC68060, {0xfff8, 0xf050|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_DC} },
1560: { MC68040|MC68060, {0xfff8, 0xf090|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_IC} },
1561: { MC68040|MC68060, {0xfff8, 0xf0D0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_ICDC} },
1562:
1563: { MC68040|MC68060, {0xfff8, 0xf018|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_NONE} },
1564: { MC68040|MC68060, {0xfff8, 0xf058|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_DC} },
1565: { MC68040|MC68060, {0xfff8, 0xf098|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_IC} },
1566: { MC68040|MC68060, {0xfff8, 0xf0D8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_ICDC} },
1567:
1568: { MC68040|MC68060, {0xfff8, 0xf028|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_NONE} },
1569: { MC68040|MC68060, {0xfff8, 0xf068|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_DC} },
1570: { MC68040|MC68060, {0xfff8, 0xf0A8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_IC} },
1571: { MC68040|MC68060, {0xfff8, 0xf0E8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_ICDC} },
1572:
1573: { MC68040|MC68060, {0xfff8, 0xf030|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_NONE} },
1574: { MC68040|MC68060, {0xfff8, 0xf070|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_DC} },
1575: { MC68040|MC68060, {0xfff8, 0xf0B0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_IC} },
1576: { MC68040|MC68060, {0xfff8, 0xf0F0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_ICDC} },
1577:
1578: { MC68040|MC68060, {0xfff8, 0xf038|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_NONE} },
1579: { MC68040|MC68060, {0xfff8, 0xf078|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_DC} },
1580: { MC68040|MC68060, {0xfff8, 0xf0B8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_IC} },
1581: { MC68040|MC68060, {0xfff8, 0xf0F8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_ICDC} },
1582:
1583: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0100}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLU.?" },
1584: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0100}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLU.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1585: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0500}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLUN.?" },
1586: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0500}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLUN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1587:
1588: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0900}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLS.?" },
1589: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0900}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLS.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1590: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0D00}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLSN.?" },
1591: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0D00}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLSN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1592:
1593: { MC_CPU32, {0xffff, 0xf000|(CPU32_COPROC_ID<<9), 0xffff, 0x01C0}, {2}, {ofI}, "LPSTOP" },
1594:
1595:
1596: #define FPU_COPROC_ID 1 // 1 is the standard FPU, required to be 1 for the 68040 anyway
1597:
1598: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0000}, {-1,16+10,3,1}, {ofFPU}, "FMOVE.?" },
1599: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0001}, {-1,16+10,3,1}, {ofFPU}, "FINT.?" },
1600: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0002}, {-1,16+10,3,1}, {ofFPU}, "FSINH.?" },
1601: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0003}, {-1,16+10,3,1}, {ofFPU}, "FINTRZ.?" },
1602: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0004}, {-1,16+10,3,1}, {ofFPU}, "FSQRT.?" },
1603: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0006}, {-1,16+10,3,1}, {ofFPU}, "FLOGNP1.?" },
1604: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0008}, {-1,16+10,3,1}, {ofFPU}, "FETOXM1.?" },
1605: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0009}, {-1,16+10,3,1}, {ofFPU}, "FTANH.?" },
1606: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000A}, {-1,16+10,3,1}, {ofFPU}, "FATAN.?" },
1607: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000C}, {-1,16+10,3,1}, {ofFPU}, "FASIN.?" },
1608: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000D}, {-1,16+10,3,1}, {ofFPU}, "FATANH.?" },
1609: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000E}, {-1,16+10,3,1}, {ofFPU}, "FSIN.?" },
1610: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000F}, {-1,16+10,3,1}, {ofFPU}, "FTAN.?" },
1611: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0010}, {-1,16+10,3,1}, {ofFPU}, "FETOX.?" },
1612: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0011}, {-1,16+10,3,1}, {ofFPU}, "FTWOTOX.?" },
1613: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0012}, {-1,16+10,3,1}, {ofFPU}, "FTENTOX.?" },
1614: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0014}, {-1,16+10,3,1}, {ofFPU}, "FLOGN.?" },
1615: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0015}, {-1,16+10,3,1}, {ofFPU}, "FLOG10.?" },
1616: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0016}, {-1,16+10,3,1}, {ofFPU}, "FLOG2.?" },
1617: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0018}, {-1,16+10,3,1}, {ofFPU}, "FABS.?" },
1618: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0019}, {-1,16+10,3,1}, {ofFPU}, "FCOSH.?" },
1619: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001A}, {-1,16+10,3,1}, {ofFPU}, "FNEG.?" },
1620: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001C}, {-1,16+10,3,1}, {ofFPU}, "FACOS.?" },
1621: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001D}, {-1,16+10,3,1}, {ofFPU}, "FCOS.?" },
1622: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001E}, {-1,16+10,3,1}, {ofFPU}, "FGETEXP.?" },
1623: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001F}, {-1,16+10,3,1}, {ofFPU}, "FGETMAN.?" },
1624: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0020}, {-1,16+10,3,1}, {ofFPU}, "FDIV.?" },
1625: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0021}, {-1,16+10,3,1}, {ofFPU}, "FMOD.?" },
1626: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0022}, {-1,16+10,3,1}, {ofFPU}, "FADD.?" },
1627: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0023}, {-1,16+10,3,1}, {ofFPU}, "FMUL.?" },
1628: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0024}, {-1,16+10,3,1}, {ofFPU}, "FSGLDIV.?" },
1629: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0025}, {-1,16+10,3,1}, {ofFPU}, "FREM.?" },
1630: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0026}, {-1,16+10,3,1}, {ofFPU}, "FSCALE.?" },
1631: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0027}, {-1,16+10,3,1}, {ofFPU}, "FSGLMUL.?" },
1632: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0028}, {-1,16+10,3,1}, {ofFPU}, "FSUB.?" },
1633: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA078,0x0030}, {-1,16+10,3,1}, {ofFPU3Reg}, "FSINCOS.?" },
1634: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0038}, {-1,16+10,3,1}, {ofFPU}, "FCMP.?" },
1635: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x003A}, {-1,16+10,3,1}, {ofFPU}, "FTST.?" },
1636: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0040}, {-1,16+10,3,1}, {ofFPU}, "FSMOVE.?" },
1637: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0041}, {-1,16+10,3,1}, {ofFPU}, "FSSQRT.?" },
1638: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0042}, {-1,16+10,3,1}, {ofFPU}, "FSADD.?" },
1639: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0044}, {-1,16+10,3,1}, {ofFPU}, "FDMOVE.?" },
1640: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0045}, {-1,16+10,3,1}, {ofFPU}, "FDSQRT.?" },
1641: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0046}, {-1,16+10,3,1}, {ofFPU}, "FDADD.?" },
1642: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0058}, {-1,16+10,3,1}, {ofFPU}, "FSABS.?" },
1643: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005A}, {-1,16+10,3,1}, {ofFPU}, "FSNEG.?" },
1644: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005C}, {-1,16+10,3,1}, {ofFPU}, "FDABS.?" },
1645: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005E}, {-1,16+10,3,1}, {ofFPU}, "FDNEG.?" },
1646: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0060}, {-1,16+10,3,1}, {ofFPU}, "FSDIV.?" },
1647: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0063}, {-1,16+10,3,1}, {ofFPU}, "FSMUL.?" },
1648: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0064}, {-1,16+10,3,1}, {ofFPU}, "FDDIV.?" },
1649: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0067}, {-1,16+10,3,1}, {ofFPU}, "FDMUL.?" },
1650: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0068}, {-1,16+10,3,1}, {ofFPU}, "FSSUB.?" },
1651: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x006C}, {-1,16+10,3,1}, {ofFPU}, "FDSUB.?" },
1652: { MC68040|MC_FPU, {0xffff, 0xf000|(FPU_COPROC_ID<<9),0xFC00,0x5C00}, {0}, {ofFMOVECR}, "FMOVECR" },
1653:
1654: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE000,0x6000}, {-1,16+10,3,1}, {ofFPUMOVE}, "FMOVE.?" },
1655:
1656: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1657: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8400}, {0}, {ofEa,ofSpecReg}, "FMOVE", {0,REG_FPU_FPIAR} },
1658: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8800}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPSR} },
1659: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x9000}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPCR} },
1660: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0x8000}, {0}, {ofEa,ofFPUSRRegList}, "FMOVEM", {EA_Dn|EA_An,0} },
1661: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1662: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA400}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPIAR,EA_Immed|EA_PCRel} },
1663: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA800}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPSR,EA_An|EA_Immed|EA_PCRel} },
1664: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xB000}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPCR,EA_An|EA_Immed|EA_PCRel} },
1665: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0xA000}, {0}, {ofFPUSRRegList,ofEa}, "FMOVEM", {0,EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1666:
1667: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xC000}, {0}, {ofFPUReglist,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_Anip|EA_Immed} },
1668: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xC800}, {0}, {ofExtRegD04,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_piAn|EA_Immed} },
1669: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xE000}, {0}, {ofEa,ofFPUReglist}, "FMOVEM.X",{EA_Dn|EA_An|EA_piAn|EA_Immed,0} },
1670: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xE800}, {0}, {ofEa,ofExtRegD04}, "FMOVEM.X",{EA_Dn|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1671:
1672: { MC68040|MC_FPU, {0xffc0, 0xf040|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {0}, {ofEa}, "FScf.B",{EA_An|EA_Immed|EA_PCRel} },
1673: { MC68040|MC_FPU, {0xfff8, 0xf048|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {2}, {ofDn,ofDisp}, "FDBcf" },
1674: { MC68040|MC_FPU, {0xffff, 0xf07A|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "FTRAPcf.W" },
1675: { MC68040|MC_FPU, {0xffff, 0xf07B|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "FTRAPcf.L" },
1676: { MC68040|MC_FPU, {0xffff, 0xf07C|(FPU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "FTRAPcf" },
1677:
1678: // FNOP _has_ to be before FBcf.W, not worth to have a special case for that one
1679: { MC68040|MC_FPU, {0xffff, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {0}, {ofNone}, "FNOP" },
1680: { MC68040|MC_FPU, {0xffc0, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {2}, {ofDisp}, "FBcF.W" },
1681: { MC68040|MC_FPU, {0xffc0, 0xf0c0|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {4}, {ofDisp}, "FBcF.L" },
1682: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf100|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FSAVE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1683: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf140|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FRESTORE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1684:
1685: { }
1686: };
1687:
1688: static int Disass68k(long addr, char *labelBuffer, char *opcodeBuffer, char *operandBuffer, char *commentBuffer)
1689: {
1690: long baseAddr = addr;
1691: int val;
1692: const char *sp;
1693: labelBuffer[0] = 0;
1694: opcodeBuffer[0] = 0;
1695: operandBuffer[0] = 0;
1696: commentBuffer[0] = 0;
1697: int i;
1698:
1699: int count = 0;
1700: char addressLabel[256];
1701: char cmtBuffer[256];
1702: Disass68kDataType type = Disass68kType(baseAddr, addressLabel, cmtBuffer, &count);
1703: if(addressLabel[0])
1704: sprintf(labelBuffer, "%s:", addressLabel);
1705: sprintf(commentBuffer, "%s", cmtBuffer);
1706: switch(type)
1707: {
1708: case dtByte:if(count > 8)
1709: count = 8;
1710: strcpy(opcodeBuffer,"DC.B");
1711: for(i=0; i<count; ++i)
1712: {
1713: if((i & 7) > 0)
1714: strcat(operandBuffer, ",");
1715: char hbuf[16];
1716: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1717: if(i & 1)
1718: val &= 0xFF;
1719: else
1720: val = val >> 8;
1721: sprintf(hbuf,"$%2.2x", val);
1722: strcat(operandBuffer, hbuf);
1723: }
1724: return count;
1725:
1726: case dtWord:if(count > 4)
1727: count = 4;
1728: strcpy(opcodeBuffer,"DC.W");
1729: for(i=0; i<count; ++i)
1730: {
1731: if((i & 3) > 0)
1732: strcat(operandBuffer, ",");
1733: char hbuf[16];
1734: sprintf(hbuf,"$%4.4x", Disass68kGetWord(addr+i*2));
1735: strcat(operandBuffer, hbuf);
1736: }
1737: return count * 2;
1738:
1739: case dtLong:if(count > 2)
1740: count = 2;
1741: strcpy(opcodeBuffer,"DC.L");
1742: for(i=0; i<count; ++i)
1743: {
1744: if((i & 1) > 0)
1745: strcat(operandBuffer, ",");
1746: char hbuf[16];
1747: sprintf(hbuf,"$%8.8x", (Disass68kGetWord(addr+i*4) << 16) | Disass68kGetWord(addr+i*4+2));
1748: strcat(operandBuffer, hbuf);
1749: }
1750: return count * 4;
1751:
1752: case dtStringArray:
1753: {
1754: strcpy(opcodeBuffer,"DC.B");
1755: strcat(operandBuffer, "'");
1756: char *sp = operandBuffer + strlen(operandBuffer);
1757: for(i=0; i < count; ++i)
1758: {
1759: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1760: if(i & 1)
1761: val &= 0xFF;
1762: else
1763: val = val >> 8;
1764: if(val == 0)
1765: break;
1766: switch(val)
1767: {
1768: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1769: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1770: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1771: default:
1772: if(val >= 0x20 && val <= 0x7E)
1773: *sp++ = val;
1774: }
1775: }
1776: *sp = 0;
1777: strcat(sp, "'");
1778: return count;
1779: }
1780:
1781: case dtASCString:
1782: {
1783: int count = 1;
1784: unsigned short val = Disass68kGetWord(addr+0);
1785: strcpy(opcodeBuffer,"DC.B");
1786: if((val >> 8) == 0)
1787: {
1788: strcat(operandBuffer, "0");
1789: } else {
1790: strcat(operandBuffer, "'");
1791: char *sp = operandBuffer + strlen(operandBuffer);
1792: for(i=0; ; ++i)
1793: {
1794: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1795: if(i & 1)
1796: val &= 0xFF;
1797: else
1798: val = val >> 8;
1799: if(val == 0)
1800: break;
1801: switch(val)
1802: {
1803: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1804: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1805: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1806: default:
1807: if(val >= 0x20 && val <= 0x7E)
1808: *sp++ = val;
1809: }
1810: ++count;
1811: }
1812: *sp = 0;
1813: strcat(sp, "',0");
1814: }
1815: return (count + 1) & ~1;
1816: }
1817:
1818: case dtPointer:
1819: case dtFunctionPointer:
1820: val = (Disass68kGetWord(addr) << 16) | Disass68kGetWord(addr+2);
1821: sp = Disass68kSymbolName(val, 2);
1822: strcpy(opcodeBuffer,"DC.L");
1823: if(sp)
1824: sprintf(operandBuffer,"%s", sp);
1825: else
1826: sprintf(operandBuffer,"$%6.6x", val);
1827: return 4;
1828:
1829: default: break;
1830: }
1831:
1832: int index = 0;
1833: long opcodeAddr = addr;
1834: more:
1835: addr = opcodeAddr;
1836:
1837: opcodeBuffer[0] = 0;
1838: operandBuffer[0] = 0;
1839:
1840: commentBuffer[0] = 0;
1841: if(cmtBuffer[0])
1842: sprintf(commentBuffer, "%s ", cmtBuffer);
1843:
1844: while(1)
1845: {
1846: OpcodeTableStruct *ots = &OpcodeTable[index++];
1847: if(ots->opcodeName == NULL)
1848: break;
1849: if((ots->cpuMask & optionCPUTypeMask) == 0) // CPU doesn't match?
1850: continue;
1851:
1852: // search for the opcode plus up to 2 extension words
1853: unsigned short opcode[5] = {};
1854: unsigned int i;
1855: for(i=0; i<5; ++i)
1856: {
1857: if(!ots->opcodeMask[i*2])
1858: break;
1859: opcode[i] = Disass68kGetWord(addr);
1860: if(((ots->opcodeMask[i*2] & 0xFFFF) & opcode[i]) != ots->opcodeMask[i*2+1])
1861: goto more;
1862: addr += 2;
1863: }
1864:
1865: // find out the size of the opcode operand
1866: int size = ots->operationSize[0];
1867: char sizeChar = 0;
1868: if(size < 0) // custom size?
1869: {
1870: int opcodeOffset = ots->operationSize[1] >> 4;
1871: int bitShiftOffset = ots->operationSize[1] & 0x0F;
1872: int sizeBitMask = (opcode[opcodeOffset] >> bitShiftOffset) & ((1 << ots->operationSize[2]) - 1);
1873: switch(ots->operationSize[3])
1874: {
1875: case 0: // 2 Bit Size
1876: switch(sizeBitMask)
1877: {
1878: case 0: size = 1; sizeChar = 'B'; break;
1879: case 1: size = 2; sizeChar = 'W'; break;
1880: case 2: size = 4; sizeChar = 'L'; break;
1881: case 3: goto more; // illegal size mask
1882: }
1883: break;
1884: case 1: // 3 Bit FPU Size
1885: if((opcode[1] & 0x4000) == 0x0000) // Register => Register?
1886: sizeBitMask = 2; // => 'X' Format
1887: switch(sizeBitMask)
1888: {
1889: case 0: size = 4; sizeChar = 'L'; break;
1890: case 1: size = 4; sizeChar = 'S'; break;
1891: case 2: size = 12; sizeChar = 'X'; break;
1892: case 7: if((opcode[1] & 0xE000) != 0x6000) // MOVE.P <ea>,FPn{Dn-Factor}
1893: goto more; // illegal size mask
1894: case 3: size = 12; sizeChar = 'P'; break;
1895: case 4: size = 2; sizeChar = 'W'; break;
1896: case 5: size = 8; sizeChar = 'D'; break;
1897: case 6: size = 1; sizeChar = 'B'; break;
1898: }
1899: break;
1900: }
1901: }
1902:
1903: // copy the opcode plus a necessary TAB for the operand
1904: char *dbuf = opcodeBuffer;
1905: for(i=0; ots->opcodeName[i]; ++i)
1906: {
1907: char c = ots->opcodeName[i];
1908: if(c == 'c') // condition code
1909: {
1910: static const char *pmmuCond[16] = { "BS", "BC", "LS", "LC", "SS", "SC", "AS", "AC", "WS", "WC", "IS", "IC", "GS", "GC", "CS", "CC" };
1911: static const char *braCond[16] = { "RA", "SR", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1912: static const char *sccCond[16] = { "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1913: static const char *dbCond[16] = { "T", "RA", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1914: static const char *fpuCond[64] = { "F", "EQ", "OGT", "OGE", "OLT", "OLE", "OGL", "OR", "UN", "UEQ", "UGT", "UGE", "ULT", "ULE", "NE", "T", "SF", "SEQ", "GT", "GE", "LT", "LE", "GL", "GLE", "NGLE", "NGL", "NLE", "NLT", "NGE", "NGT", "SNE", "ST" };
1915:
1916: const char *sp = NULL;
1917: switch(ots->opcodeName[++i])
1918: {
1919: case 'p': // PMMU conditions
1920: sp = pmmuCond[opcode[1] & 0xF];
1921: break;
1922: case 'b': // BRA conditions
1923: sp = braCond[(opcode[0] >> 8) & 0xF];
1924: break;
1925: case 'i': // Scc,TRAPcc conditions
1926: sp = sccCond[(opcode[0] >> 8) & 0xF];
1927: break;
1928: case 'd': // DBcc conditions
1929: sp = dbCond[(opcode[0] >> 8) & 0xF];
1930: break;
1931: case 'F': // FPU conditions (first word)
1932: sp = fpuCond[opcode[0] & 0x3F];
1933: break;
1934: case 'f': // FPU conditions (second word)
1935: sp = fpuCond[opcode[1] & 0x3F];
1936: break;
1937: }
1938: if(sp)
1939: {
1940: if(options & doptOpcodesSmall)
1941: {
1942: char buf[8];
1943: strcpy(buf, sp);
1944: sp = buf;
1945: char *bp = buf;
1946: for(; *bp; ++bp)
1947: *bp = tolower(*bp);
1948: }
1949: strcpy(dbuf, sp);
1950: dbuf += strlen(sp);
1951: continue;
1952: }
1953: goto more;
1954: }
1955: if(c == '?') // size mask
1956: c = sizeChar;
1957: if(options & doptOpcodesSmall)
1958: c = tolower(c);
1959: *dbuf++ = c;
1960: }
1961: *dbuf = 0;
1962:
1963: // Parse the EAs for all operands
1964: int ea = opcode[0] & 0x3F;
1965: dbuf = operandBuffer;
1966: for(i=0; i<(sizeof(ots->op)/sizeof(ots->op[0])); ++i)
1967: {
1968: switch(ots->op[i])
1969: {
1970: case ofNone: // nothing
1971: break;
1972:
1973: case ofEa:
1974: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
1975: break;
1976:
1977: case ofDn:
1978: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
1979: break;
1980: case ofAn:
1981: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
1982: break;
1983: case ofAni:
1984: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x10, size, EA_Ani, 0, ots->disassFlag);
1985: break;
1986: case ofAnip:
1987: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
1988: break;
1989: case ofPiAn:
1990: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
1991: break;
1992: case ofD16An:
1993: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x28, size, EA_dAn, 0, ots->disassFlag);
1994: break;
1995:
1996: case ofI:
1997: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x3C, size, EA_Immed, 0, ots->disassFlag);
1998: break;
1999:
2000: case ofDestDn:
2001: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2002: break;
2003: case ofDestAn:
2004: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2005: break;
2006: case ofDestAnip:
2007: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2008: break;
2009: case ofDestPiAn:
2010: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2011: break;
2012: case ofDestEa6:
2013: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | (((opcode[0] >> 6) & 0x7) << 3), size, EA_Dest-EA_An, 0, ots->disassFlag);
2014: break;
2015: case ofDestAbsL:
2016: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x39, size, EA_Abs, 0, ots->disassFlag);
2017: break;
2018:
2019: case ofIOpcode:
2020: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[0] & ots->parameter[i], ots->disassFlag);
2021: break;
2022: case ofI3:
2023: val = ((opcode[0] >> 9) & 7);
2024: if(!val) val = 8;
2025: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, val, ots->disassFlag);
2026: break;
2027: case ofExtIm:
2028: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1], ots->disassFlag);
2029: break;
2030: case ofExtIm32:
2031: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, size, EA_ImmedParameter, opcode[2], ots->disassFlag);
2032: break;
2033: case ofExtIm4:
2034: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1] & 0x0F, ots->disassFlag);
2035: break;
2036: case ofExtIm10:
2037: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, (opcode[1] >> 10) & 0x07, ots->disassFlag);
2038: break;
2039: case ofSpecReg:
2040: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, ots->parameter[i], ots->disassFlag);
2041: break;
2042: case ofSpecExtReg:
2043: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, opcode[1] & 0xFFF, ots->disassFlag);
2044: break;
2045: case ofExtReg0:
2046: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2047: break;
2048: case ofExtRegA0:
2049: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2050: break;
2051: case ofExtRegD04:
2052: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 4) & 0x07) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2053: break;
2054: case ofExtRegA05:
2055: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 5) & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2056: break;
2057: case ofExtReg:
2058: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2059: break;
2060: case ofExtAnip:
2061: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2062: break;
2063:
2064: case ofDisp:
2065: // branch treats the displacement 0x00 and 0xFF as an indicator how many words follow
2066: // This test will decline a displacement with the wrong word offset
2067: if((opcode[0] & 0xF000) == 0x6000)
2068: {
2069: val = opcode[0] & 0xFF;
2070: if(val == 0x00 && size != 2) goto more;
2071: if(val == 0xFF && size != 4) goto more;
2072: }
2073: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0102, size, EA_PCDisplacement, opcode[0] & 0xFF, ots->disassFlag);
2074: break;
2075:
2076: case ofRegList:
2077: val = opcode[1];
2078: if((ea & 0x38) == 0x20) // -(An) has a flipped bitmask
2079: val = Disass68kFlipBits(val);
2080: dbuf = Disass68kReglist(dbuf, val);
2081: break;
2082:
2083: case ofFPU:
2084: { // default FPU opcode modes
2085: int src = (opcode[1] >> 10) & 7;
2086: int dest = (opcode[1] >> 7) & 7;
2087: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2088: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2089: if(opcode[1] & 0x4000)
2090: {
2091: // <ea>,FPn
2092: int mask = EA_All - EA_An;
2093: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2094: mask -= EA_Dn;
2095: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2096: if(!dbuf) goto more;
2097: *dbuf++ = ',';
2098: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2099: *dbuf = 0;
2100: } else {
2101: // FPn,FPn or FPn
2102:
2103: // <ea> has to be 0
2104: if((opcode[0] & 0x3F) != 0) goto more;
2105:
2106: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2107: if(src != dest)
2108: {
2109: *dbuf++ = ',';
2110: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2111: }
2112: *dbuf = 0;
2113: }
2114: }
2115: break;
2116: case ofFPUMOVE:
2117: { // MOVE <ea>,FPn{k-Factor}
2118: int src = (opcode[1] >> 10) & 7;
2119: // <ea>,FPn
2120: int mask = EA_All - EA_An;
2121: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2122: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2123: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2124: mask -= EA_Dn;
2125: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2126: if(!dbuf) goto more;
2127: *dbuf++ = ',';
2128: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+((opcode[1] >> 7) & 7);
2129: if(src == 3)
2130: {
2131: int kFactor = opcode[1] & 0x7F;
2132: if(kFactor & 0x40)
2133: kFactor |= 0x80;
2134: *dbuf++ = '{';
2135: sprintf(dbuf, "%d", (signed char)kFactor);
2136: dbuf += strlen(dbuf);
2137: *dbuf++ = '}';
2138: } else if(src == 7)
2139: {
2140: if((opcode[1] & 0x0F) != 0) goto more;
2141: *dbuf++ = '{';
2142: *dbuf++ = options & doptRegisterSmall ? 'd' : 'D';
2143: *dbuf++ = '0' + ((opcode[1] >> 4) & 7);
2144: *dbuf++ = '}';
2145: } else {
2146: if((opcode[1] & 0x7F) != 0) goto more;
2147: }
2148: *dbuf = 0;
2149: }
2150: break;
2151: case ofFMOVECR:
2152: { // MOVECR #const,FPn
2153: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2154: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2155: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[1] & 0x7F, ots->disassFlag);
2156: if(!dbuf) goto more;
2157: int reg = (opcode[1] >> 7) & 7;
2158: *dbuf++ = ',';
2159: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+reg;
2160: *dbuf = 0;
2161: switch(opcode[1] & 0x7F) // document the well-known constants
2162: {
2163: case 0x00: strcat(commentBuffer, "PI"); break;
2164: case 0x0B: strcat(commentBuffer, "Log10(2)"); break;
2165: case 0x0C: strcat(commentBuffer, "e"); break;
2166: case 0x0D: strcat(commentBuffer, "Log2(e)"); break;
2167: case 0x0E: strcat(commentBuffer, "Log10(e)"); break;
2168: case 0x0F: strcat(commentBuffer, "0.0"); break;
2169: case 0x30: strcat(commentBuffer, "1n(2)"); break;
2170: case 0x31: strcat(commentBuffer, "1n(10)"); break;
2171: case 0x32: strcat(commentBuffer, "100"); break;
2172: case 0x33: strcat(commentBuffer, "10^1"); break;
2173: case 0x34: strcat(commentBuffer, "10^2"); break;
2174: case 0x35: strcat(commentBuffer, "10^4"); break;
2175: case 0x36: strcat(commentBuffer, "10^8"); break;
2176: case 0x37: strcat(commentBuffer, "10^16"); break;
2177: case 0x38: strcat(commentBuffer, "10^32"); break;
2178: case 0x39: strcat(commentBuffer, "10^64"); break;
2179: case 0x3A: strcat(commentBuffer, "10^128"); break;
2180: case 0x3B: strcat(commentBuffer, "10^256"); break;
2181: case 0x3C: strcat(commentBuffer, "10^512"); break;
2182: case 0x3D: strcat(commentBuffer, "10^1024"); break;
2183: case 0x3E: strcat(commentBuffer, "10^2048"); break;
2184: case 0x3F: strcat(commentBuffer, "10^4096"); break;
2185: }
2186: }
2187: break;
2188: case ofFPUSRRegList:
2189: {
2190: int hasReg = 0;
2191: *dbuf = 0;
2192: if(opcode[1] & 0x0400)
2193: {
2194: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPIAR));
2195: hasReg = 1;
2196: }
2197: if(opcode[1] & 0x0800)
2198: {
2199: if(hasReg) strcat(dbuf, "/");
2200: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPSR));
2201: hasReg = 1;
2202: }
2203: if(opcode[1] & 0x1000)
2204: {
2205: if(hasReg) strcat(dbuf, "/");
2206: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPCR));
2207: hasReg = 1;
2208: }
2209: if(!hasReg)
2210: strcat(dbuf, "0");
2211: dbuf += strlen(dbuf);
2212: }
2213: break;
2214: case ofFPUReglist: // FMOVEM
2215: {
2216: int mask = opcode[1] & 0xFF;
2217: if(opcode[1] & 0x0100)
2218: mask = Disass68kFlipBits(mask) >> 8;
2219: dbuf = Disass68kFPUReglist(dbuf, mask);
2220: }
2221: break;
2222: case ofFPU3Reg:
2223: { // FSINCOS
2224: int src = (opcode[1] >> 10) & 7;
2225: int dest = (opcode[1] >> 7) & 7;
2226: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2227: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2228: if(opcode[1] & 0x4000)
2229: {
2230: // <ea>,FPn
2231: int mask = EA_All - EA_An;
2232: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2233: mask -= EA_Dn;
2234: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2235: if(!dbuf) goto more;
2236: *dbuf++ = ',';
2237: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2238: *dbuf++ = ',';
2239: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2240: *dbuf = 0;
2241: } else {
2242: // FPn,FPn or FPn
2243:
2244: // <ea> has to be 0
2245: if((opcode[0] & 0x3F) != 0) goto more;
2246:
2247: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2248: *dbuf++ = ',';
2249: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2250: *dbuf++ = ',';
2251: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2252: *dbuf = 0;
2253: }
2254: }
2255: break;
2256:
2257: case ofCAS:
2258: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2259: if(!dbuf) goto more;
2260: *dbuf++ = ',';
2261: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2262: break;
2263: case ofCAS2:
2264: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2265: if(!dbuf) goto more;
2266: *dbuf++ = ':';
2267: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[2] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2268: if(!dbuf) goto more;
2269: *dbuf++ = ',';
2270: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2271: if(!dbuf) goto more;
2272: *dbuf++ = ':';
2273: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2274: if(!dbuf) goto more;
2275: *dbuf++ = ',';
2276: *dbuf++ = '(';
2277: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2278: if(!dbuf) goto more;
2279: *dbuf++ = ')';
2280: *dbuf++ = ':';
2281: *dbuf++ = '(';
2282: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2283: if(!dbuf) goto more;
2284: *dbuf++ = ')';
2285: *dbuf = 0;
2286: break;
2287: case ofExt4Dn:
2288: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[0] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2289: if(!dbuf) goto more;
2290: *dbuf++ = ':';
2291: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2292: if(!dbuf) goto more;
2293: *dbuf++ = ',';
2294: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2295: if(!dbuf) goto more;
2296: *dbuf = 0;
2297: break;
2298: case ofBFEa:
2299: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2300: if(!dbuf) goto more;
2301: *dbuf++ = '{';
2302: val = (opcode[1] >> 6) & 0x1F;
2303: if(opcode[1] & 0x0800)
2304: {
2305: if(val & 0x18) goto more;
2306: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2307: } else {
2308: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2309: }
2310: *dbuf++ = ':';
2311: val = opcode[1] & 0x1F;
2312: if(opcode[1] & 0x0020)
2313: {
2314: if(val & 0x18) goto more;
2315: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2316: } else {
2317: if(val == 0) val = 32;
2318: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2319: }
2320: *dbuf++ = '}';
2321: *dbuf = 0;
2322: break;
2323: case ofLineA:
2324: {
2325: int lineAVal = opcode[0] & 0xFFF;
2326: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, lineAVal, ots->disassFlag);
2327: const char *lineAStr[16] = { "Line-A Initialization",
2328: "Put pixel",
2329: "Get pixel",
2330: "Arbitrary line",
2331: "Horizontal line",
2332: "Filled rectangle",
2333: "Filled polygon",
2334: "Bit block transfer",
2335: "Text block transfer",
2336: "Show mouse",
2337: "Hide mouse",
2338: "Transform mouse",
2339: "Undraw sprite",
2340: "Draw sprite",
2341: "Copy raster form",
2342: "Seedfill"
2343: };
2344: if(lineAVal < 16)
2345: strcat(commentBuffer, lineAStr[lineAVal]);
2346: }
2347: break;
2348:
2349: default:
2350: goto more;
2351: }
2352: if(!dbuf) goto more;
2353:
2354: // does another operand follow => add separator
2355: if(ots->op[i+1] != ofNone)
2356: *dbuf++ = ',';
2357: }
2358: return addr-baseAddr;
2359: }
2360:
2361: // unknown opcode
2362: strcpy(opcodeBuffer, "DC.W");
2363: sprintf(operandBuffer,"$%4.4x", Disass68kGetWord(addr));
2364: return 2;
2365: }
2366:
2367: static void Disass68kComposeStr(char *dbuf, const char *str, int position, int maxPos)
2368: {
2369: int i;
2370: int len = strlen(dbuf);
2371: while(len < position) {
2372: dbuf[len++] = ' '; /* Will give harmless warning from GCC */
2373: }
2374: for(i=0; str[i] && (!maxPos || len+i<maxPos); ++i)
2375: dbuf[len+i] = str[i];
2376: if(str[i])
2377: dbuf[len+i-1] = '+';
2378: dbuf[len+i] = 0;
2379: }
2380:
2381: static void Disass68k_loop (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
2382: {
2383: static bool isInit = false;
2384: if(!isInit)
2385: {
2386: Disass68kInit(Paths_GetHatariHome());
2387: isInit = true;
2388: }
2389:
2390: while (cnt-- > 0) {
2391: int addrWidth = 6; // 6 on an ST, 8 on a TT
2392: char lineBuffer[1024];
2393:
2394: char addressBuffer[32];
2395: char hexdumpBuffer[256];
2396: char labelBuffer[256];
2397: char opcodeBuffer[64];
2398: char operandBuffer[256];
2399: char commentBuffer[256];
2400: int len = Disass68k(addr, labelBuffer, opcodeBuffer, operandBuffer, commentBuffer);
2401: if(!len) break;
2402:
2403: sprintf(addressBuffer, "$%*.*x :", addrWidth,addrWidth, addr);
2404:
2405: hexdumpBuffer[0] = 0;
2406: int plen = len;
2407: if(plen > 80 && (!strncmp(opcodeBuffer, "DC.", 3) || !strncmp(opcodeBuffer, "dc.", 3)))
2408: plen = ((optionPosLabel - optionPosHexdump) / 5) * 2;
2409: int j;
2410: for(j=0; j<plen; j += 2)
2411: {
2412: if(j > 0)
2413: strcat(hexdumpBuffer, " ");
2414: if(j + 2 > plen)
2415: {
2416: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%2.2x", Disass68kGetWord(addr+j) >> 8);
2417: } else {
2418: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%4.4x", Disass68kGetWord(addr+j));
2419: }
2420: }
2421:
2422: lineBuffer[0] = 0;
2423: if(optionPosAddress >= 0)
2424: Disass68kComposeStr(lineBuffer, addressBuffer, optionPosAddress, 0);
2425: if(optionPosHexdump >= 0)
2426: Disass68kComposeStr(lineBuffer, hexdumpBuffer, optionPosHexdump, optionPosLabel);
2427: if(optionPosLabel >= 0)
2428: Disass68kComposeStr(lineBuffer, labelBuffer, optionPosLabel, 0);
2429: if(optionPosOpcode >= 0)
2430: Disass68kComposeStr(lineBuffer, opcodeBuffer, optionPosOpcode, 0);
2431: if(optionPosOperand >= 0)
2432: {
2433: size_t l = strlen(lineBuffer);
2434: if(lineBuffer[l-1] != ' ') // force at least one space between opcode and operand
2435: {
2436: lineBuffer[l++] = ' ';
2437: lineBuffer[l] = 0;
2438: }
2439: Disass68kComposeStr(lineBuffer, operandBuffer, optionPosOperand, 0);
2440: }
2441: if(commentBuffer[0] && optionPosComment >= 0)
2442: {
2443: Disass68kComposeStr(lineBuffer, " ;", optionPosComment, 0);
2444: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+3, 0);
2445: }
2446:
2447: fprintf(f, "%s\n", lineBuffer);
2448: // if(strstr(opcodeBuffer, "RTS") || strstr(opcodeBuffer, "RTE") || strstr(opcodeBuffer, "JMP")
2449: // || strstr(opcodeBuffer, "rts") || strstr(opcodeBuffer, "rte") || strstr(opcodeBuffer, "jmp"))
2450: // fprintf(f, "\n");
2451: addr += len;
2452: }
2453: if (nextpc)
2454: *nextpc = addr;
2455: }
2456:
2457:
2458: /*
2459: * Disasm should be called from Hatari's sources to use either uae's built in
2460: * disassembler (DISASM_ENGINE_UAE) or the stand alone disassembler above (DISASM_ENGINE_EXT)
2461: */
2462:
2463: void Disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt , int DisasmEngine)
2464: {
2465: if ( DisasmEngine == DISASM_ENGINE_UAE )
2466: return m68k_disasm (f, addr, nextpc, cnt);
2467: else if ( DisasmEngine == DISASM_ENGINE_EXT )
2468: return Disass68k_loop (f, addr, nextpc, cnt);
2469: }
2470:
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