--- previous/src/dimension/nd_devs.c 2018/04/24 19:30:01 1.1.1.1 +++ previous/src/dimension/nd_devs.c 2018/04/24 19:31:37 1.1.1.2 @@ -7,12 +7,13 @@ #include "m68000.h" #include "sysdeps.h" #include "dimension.h" +#include "nd_vio.h" #include "nd_devs.h" #include "nd_nbic.h" #include "i860cfg.h" #include "nd_sdl.h" - -#if ENABLE_DIMENSION +#include "ramdac.h" +#include "host.h" /* --------- NEXTDIMENSION DEVICES ---------- */ @@ -48,6 +49,9 @@ #define CSR2_GLOBAL_ACCESS 0x00000001 +#define SID_SID_MASK 0x0000000F +#define SID_STEP_MASK 0x000000F0 + #define CSRDMA_VISIBLE_EN 0x00000001 #define CSRDMA_BLANKED_EN 0x00000002 #define CSRDMA_READ_EN 0x00000004 @@ -58,11 +62,7 @@ #define CSRDRAM_4MBIT 0x00000001 -static -#if ENABLE_I860_THREAD -volatile -#endif -struct { +static volatile struct { uae_u32 csr0; uae_u32 csr1; uae_u32 csr2; @@ -85,14 +85,18 @@ struct { uae_u32 vram; uae_u32 dram; } nd_mc; -static lock_t nd_mc_lock; #define DP_IIC_MORE 0x20000000 #define DP_IIC_BUSY 0x80000000 +#define DP_CSR_MASK_DIS 0x01 +#define DP_CSR_NTSC 0x02 /* 0 = NTSC, 1 = PAL */ +#define DP_CSR_JPEG_MASK 0xFC + + static struct { uae_u8 iic_addr; - uae_u8 iic_msg[4096]; + uae_u8 iic_msg; uae_u32 iic_msgsz; int iic_busy; uae_u32 doff; // (SC) wild guess - vram offset in pixels? @@ -107,47 +111,11 @@ static struct { uae_u32 iic_data; } nd_dp; -/* nd_display_blank_start is called from SDL. See nd_sdl.c */ -void nd_display_blank_start() { - lock(&nd_mc_lock); - Uint32 csr0 = nd_mc.csr0; - csr0 |= CSR0_VBL_INT | CSR0_VBLANK; - nd_mc.csr0 = csr0; - unlock(&nd_mc_lock); - i860_tick((csr0 & CSR0_VBL_IMASK) != 0); -} - -/* nd_display_blank_start is called from SDL. See nd_sdl.c */ -void nd_display_blank_end() { - lock(&nd_mc_lock); - nd_mc.csr0 &= ~CSR0_VBLANK; - unlock(&nd_mc_lock); -} - -/* nd_video_vbl is called from SDL. See nd_sdl.c */ -Uint32 nd_video_vbl(Uint32 interval, void *param) { - lock(&nd_mc_lock); - Uint32 csr0 = nd_mc.csr0; - if(csr0 & CSR0_VIOBLANK) { - csr0 &= ~CSR0_VIOBLANK; - interval = VIDEO_VBL_MS-BLANK_MS; - } else { - csr0 |= CSR0_VIOVBL_INT | CSR0_VIOBLANK; - interval = BLANK_MS; - } - nd_mc.csr0 = csr0; - unlock(&nd_mc_lock); - i860_tick((csr0 & CSR0_VIOVBL_IMASK) != 0); - return interval; -} - void nd_devs_init() { - nd_set_speed_hack(0); - - nd_mc.csr0 = 0; + nd_mc.csr0 = CSR0_i860PIN_CS8; nd_mc.csr1 = 0; nd_mc.csr2 = 0; - nd_mc.sid = ND_SLOT; + nd_mc.sid = ND_SLOT|(ND_STEP<<4); nd_mc.dma_csr = 0; nd_mc.dma_start = 0; nd_mc.dma_width = 0; @@ -269,7 +237,7 @@ static const char* decodeBits(const char static const char* MC_RD_FORMAT = "[ND] Memory controller %s read %08X at %08X"; static const char* MC_RD_FORMAT_S = "[ND] Memory controller %s read (%s) at %08X"; -uae_u32 nd_mc_read_register(uaecptr addr) { +static uae_u32 nd_mc_read_register(uaecptr addr) { switch (addr&0x3FFF) { case 0x0000: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr0", decodeBits(ND_CSR0_BITS, nd_mc.csr0),addr); @@ -347,8 +315,7 @@ uae_u32 nd_mc_read_register(uaecptr addr static const char* MC_WR_FORMAT = "[ND] Memory controller %s write %08X at %08X"; static const char* MC_WR_FORMAT_S = "[ND] Memory controller %s write (%s) at %08X"; -void nd_mc_write_register(uaecptr addr, uae_u32 val) { - lock(&nd_mc_lock); +static void nd_mc_write_register(uaecptr addr, uae_u32 val) { switch (addr&0x3FFF) { case 0x0000: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr0", decodeBits(ND_CSR0_BITS, val), addr); @@ -356,13 +323,12 @@ void nd_mc_write_register(uaecptr addr, i860_reset(); val &= ~CSR0_i860PIN_RESET; } - if ((nd_mc.csr0 & CSR0_i860_INT) && (nd_mc.csr0 & CSR0_i860_IMASK)) - i860_tick(true); + if ((val & CSR0_i860_INT) && (val & CSR0_i860_IMASK)) + i860_interrupt(); - if((nd_mc.csr0 & CSR0_BE_INT) && (nd_mc.csr0 & CSR0_BE_IMASK)) - i860_tick(true); + if((val & CSR0_BE_INT) && (val & CSR0_BE_IMASK)) + i860_interrupt(); - nd_set_speed_hack((val & 0x00008000) ? 0 : 1); nd_mc.csr0 = val; break; case 0x0010: @@ -458,7 +424,6 @@ void nd_mc_write_register(uaecptr addr, Log_Printf(LOG_WARN, "[ND] Memory controller UNKNOWN write at %08X",addr); break; } - unlock(&nd_mc_lock); } /* NeXTdimension device space */ @@ -488,71 +453,41 @@ inline void nd_io_bput(uaecptr addr, uae /* NeXTdimension RAMDAC */ -static struct { - int addr; - int idx; - Uint8 regs[0x1000]; -} nd_ramdac; - -static void nd_ramdac_autoinc() { - nd_ramdac.idx++; - if(nd_ramdac.idx == 3) { - nd_ramdac.idx = 0; - nd_ramdac.addr++; - } +bt463 nd_ramdac; + +inline uae_u32 nd_ramdac_lget(uaecptr addr) { + return bt463_bget(&nd_ramdac, addr) << 24; +} + +inline uae_u32 nd_ramdac_wget(uaecptr addr) { + return bt463_bget(&nd_ramdac, addr) << 8; } inline uae_u32 nd_ramdac_bget(uaecptr addr) { - uae_u32 result = 0; - switch(addr & 0xF) { - case 0: - return nd_ramdac.addr & 0xFF; - case 0x4: - return (nd_ramdac.addr >> 8) & 0xFF; - case 0x8: - result = nd_ramdac.regs[nd_ramdac.addr*3]; - if(nd_ramdac.addr == 0x100 || nd_ramdac.addr == 0x101) - nd_ramdac_autoinc(); - break; - case 0xC: - result = nd_ramdac.regs[nd_ramdac.addr*3+nd_ramdac.idx]; - nd_ramdac_autoinc(); - break; - } - return result; + return bt463_bget(&nd_ramdac, addr); +} + +inline void nd_ramdac_lput(uaecptr addr, uae_u32 l) { + bt463_bput(&nd_ramdac, addr, l >> 24); +} + +inline void nd_ramdac_wput(uaecptr addr, uae_u32 w) { + bt463_bput(&nd_ramdac, addr, w >> 8); } inline void nd_ramdac_bput(uaecptr addr, uae_u32 b) { - switch(addr & 0xF) { - case 0x0: - nd_ramdac.addr &= 0xFF00; - nd_ramdac.addr |= b & 0xFF; - nd_ramdac.idx = 0; - break; - case 0x4: - nd_ramdac.addr &= 0x000F; - nd_ramdac.addr |= (b & 0x0F) << 8; - nd_ramdac.idx = 0; - break; - case 0x8: - nd_ramdac.regs[nd_ramdac.addr*3] = b; - if(nd_ramdac.addr == 0x100 || nd_ramdac.addr == 0x101) - nd_ramdac_autoinc(); - break; - case 0xC: - nd_ramdac.regs[nd_ramdac.addr*3+nd_ramdac.idx] = b; - nd_ramdac_autoinc(); - break; - } + bt463_bput(&nd_ramdac, addr, b); } /* NeXTdimension data path */ -static void nd_dp_iicmsg() { - Log_Printf(LOG_WARN, "[ND] data path IIC msg addr:%02X msg[%d]=%02X", nd_dp.iic_addr, nd_dp.iic_msgsz-1, nd_dp.iic_msg[nd_dp.iic_msgsz-1]); +static void nd_dp_iicmsg(void) { + Log_Printf(LOG_NONE, "[ND] data path IIC msg addr:%02X msg[%d]=%02X", nd_dp.iic_addr, nd_dp.iic_msgsz-1, nd_dp.iic_msg); + + nd_video_dev_write(nd_dp.iic_addr, nd_dp.iic_msgsz-1, nd_dp.iic_msg); } -inline uae_u32 nd_dp_lget(uaecptr addr) { +uae_u32 nd_dp_lget(uaecptr addr) { switch(addr) { case 0x300: case 0x304: case 0x308: case 0x30C: case 0x310: case 0x314: case 0x318: case 0x31C: @@ -587,13 +522,12 @@ inline uae_u32 nd_dp_lget(uaecptr addr) return 0; } -inline void nd_dp_lput(uaecptr addr, uae_u32 v) { +void nd_dp_lput(uaecptr addr, uae_u32 v) { switch(addr) { case 0x300: case 0x304: case 0x308: case 0x30C: case 0x310: case 0x314: case 0x318: case 0x31C: case 0x320: case 0x324: case 0x328: case 0x32C: case 0x330: case 0x334: case 0x338: case 0x33C: - ND_vram_off = v * 4; nd_dp.doff = v; break; case 0x340: @@ -619,14 +553,16 @@ inline void nd_dp_lput(uaecptr addr, uae break; case 0x360: nd_dp.iic_msgsz = 0; - nd_dp.iic_addr = v >> 8; - nd_dp.iic_msg[nd_dp.iic_msgsz++] = v; + nd_dp.iic_addr = (v >> 8) & 0xFF; + nd_dp.iic_msg = v; + nd_dp.iic_msgsz++; nd_dp.iic_stat_addr |= DP_IIC_BUSY; nd_dp.iic_busy = 10; nd_dp_iicmsg(); break; case 0x364: - nd_dp.iic_msg[nd_dp.iic_msgsz++] = v; + nd_dp.iic_msg = v; + nd_dp.iic_msgsz++; nd_dp.iic_stat_addr |= DP_IIC_BUSY; nd_dp.iic_busy = 10; nd_dp_iicmsg(); @@ -636,6 +572,31 @@ inline void nd_dp_lput(uaecptr addr, uae } } +void nd_set_blank_state(int src, bool state) { + switch (src) { + case ND_DISPLAY: + if(state) { + nd_mc.csr0 |= CSR0_VBL_INT | CSR0_VBLANK; + if (nd_mc.csr0 & CSR0_VBL_IMASK) { + i860_interrupt(); + } + } else { + nd_mc.csr0 &= ~CSR0_VBLANK; + } + break; + case ND_VIDEO: + if(state) { + nd_mc.csr0 |= CSR0_VIOVBL_INT | CSR0_VIOBLANK; + if (nd_mc.csr0 & CSR0_VIOVBL_IMASK) { + i860_interrupt(); + } + } else { + nd_mc.csr0 &= ~CSR0_VIOBLANK; + } + break; + } +} + static const char* nd_dump_path = "nd_memory.bin"; /* debugger stuff */ @@ -650,13 +611,12 @@ bool nd_dbg_cmd(const char* buf) { switch(buf[0]) { case 'w': { - char tmp[PATH_MAX]; FILE* fp = fopen(nd_dump_path, "wb"); size_t size = ConfigureParams.Dimension.nMemoryBankSize[0]; size += ConfigureParams.Dimension.nMemoryBankSize[1]; size += ConfigureParams.Dimension.nMemoryBankSize[2]; size += ConfigureParams.Dimension.nMemoryBankSize[3]; - fprintf(stderr, "Writing %luMB to '%s'...", size, realpath(nd_dump_path, tmp)); + fprintf(stderr, "Writing %"FMT_zu"MB to '%s'...", size, nd_dump_path); size <<= 20; fwrite(ND_ram, sizeof(Uint8), size, fp); fclose(fp); @@ -692,4 +652,3 @@ bool nd_dbg_cmd(const char* buf) { } } -#endif