![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to nd_devs.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Previous NeXT emulator] / previous / src / dimension|
Return to nd_devs.c CVS log | Up to [Previous NeXT emulator] / previous / src / dimension |
1.1 root 1: #include <stdio.h>
2: #include <limits.h>
3: #include <stdlib.h>
4:
5: #include "main.h"
6: #include "configuration.h"
7: #include "m68000.h"
8: #include "sysdeps.h"
9: #include "dimension.h"
1.1.1.2 ! root 10: #include "nd_vio.h"
1.1 root 11: #include "nd_devs.h"
12: #include "nd_nbic.h"
13: #include "i860cfg.h"
14: #include "nd_sdl.h"
1.1.1.2 ! root 15: #include "ramdac.h"
! 16: #include "host.h"
1.1 root 17:
18: /* --------- NEXTDIMENSION DEVICES ---------- */
19:
20: /* Device registers */
21:
22: /* Memory controller */
23: #define ND_MC_CSR0 0xFF800000
24: #define ND_MC_CSR1 0xFF800010
25: #define ND_MC_CSR2 0xFF800020
26: #define ND_MC_SID 0xFF800030
27:
28: #define ND_MC_DMA_CSR 0xFF801000
29:
30: #define ND_MC_VRAM_TIMING 0xFF802000
31: #define ND_MC_DRAM_SIZE 0xFF803000
32:
33: /* CSR bits */
34: #define CSR0_i860PIN_RESET 0x00000001
35: #define CSR0_i860PIN_CS8 0x00000002
36: #define CSR0_i860_IMASK 0x00000004
37: #define CSR0_i860_INT 0x00000008
38: #define CSR0_BE_IMASK 0x00000010
39: #define CSR0_BE_INT 0x00000020
40: #define CSR0_VBL_IMASK 0x00000040
41: #define CSR0_VBL_INT 0x00000080
42: #define CSR0_VBLANK 0x00000100 /* ro */
43: #define CSR0_VIOVBL_IMASK 0x00000200
44: #define CSR0_VIOVBL_INT 0x00000400
45: #define CSR0_VIOBLANK 0x00000800 /* ro */
46: #define CSR0_i860_CACHE_EN 0x00001000
47:
48: #define CSR1_CPU_INT 0x00000001
49:
50: #define CSR2_GLOBAL_ACCESS 0x00000001
51:
1.1.1.2 ! root 52: #define SID_SID_MASK 0x0000000F
! 53: #define SID_STEP_MASK 0x000000F0
! 54:
1.1 root 55: #define CSRDMA_VISIBLE_EN 0x00000001
56: #define CSRDMA_BLANKED_EN 0x00000002
57: #define CSRDMA_READ_EN 0x00000004
58:
59: #define CSRVRAM_VBLANK 0x00000001
60: #define CSRVRAM_60HZ 0x00000002
61: #define CSRVRAM_EXT_SYNC 0x00000004
62:
63: #define CSRDRAM_4MBIT 0x00000001
64:
1.1.1.2 ! root 65: static volatile struct {
1.1 root 66: uae_u32 csr0;
67: uae_u32 csr1;
68: uae_u32 csr2;
69: uae_u32 sid;
70: uae_u32 dma_csr;
71: uae_u32 dma_start;
72: uae_u32 dma_width;
73: uae_u32 dma_pstart;
74: uae_u32 dma_pwidth;
75: uae_u32 dma_sstart;
76: uae_u32 dma_swidth;
77: uae_u32 dma_bsstart;
78: uae_u32 dma_bswidth;
79: uae_u32 dma_top;
80: uae_u32 dma_bottom;
81: uae_u32 dma_line_a;
82: uae_u32 dma_curr_a;
83: uae_u32 dma_scurr_a;
84: uae_u32 dma_out_a;
85: uae_u32 vram;
86: uae_u32 dram;
87: } nd_mc;
88:
89: #define DP_IIC_MORE 0x20000000
90: #define DP_IIC_BUSY 0x80000000
91:
1.1.1.2 ! root 92: #define DP_CSR_MASK_DIS 0x01
! 93: #define DP_CSR_NTSC 0x02 /* 0 = NTSC, 1 = PAL */
! 94: #define DP_CSR_JPEG_MASK 0xFC
! 95:
! 96:
1.1 root 97: static struct {
98: uae_u8 iic_addr;
1.1.1.2 ! root 99: uae_u8 iic_msg;
1.1 root 100: uae_u32 iic_msgsz;
101: int iic_busy;
102: uae_u32 doff; // (SC) wild guess - vram offset in pixels?
103: uae_u32 csr;
104: uae_u32 alpha;
105: uae_u32 dma;
106: uae_u32 cpu_x;
107: uae_u32 cpu_y;
108: uae_u32 dma_x;
109: uae_u32 dma_y;
110: uae_u32 iic_stat_addr;
111: uae_u32 iic_data;
112: } nd_dp;
113:
114: void nd_devs_init() {
1.1.1.2 ! root 115: nd_mc.csr0 = CSR0_i860PIN_CS8;
1.1 root 116: nd_mc.csr1 = 0;
117: nd_mc.csr2 = 0;
1.1.1.2 ! root 118: nd_mc.sid = ND_SLOT|(ND_STEP<<4);
1.1 root 119: nd_mc.dma_csr = 0;
120: nd_mc.dma_start = 0;
121: nd_mc.dma_width = 0;
122: nd_mc.dma_pstart = 0;
123: nd_mc.dma_pwidth = 0;
124: nd_mc.dma_sstart = 0;
125: nd_mc.dma_swidth = 0;
126: nd_mc.dma_bsstart = 0;
127: nd_mc.dma_bswidth = 0;
128: nd_mc.dma_top = 0;
129: nd_mc.dma_bottom = 0;
130: nd_mc.dma_line_a = 0;
131: nd_mc.dma_curr_a = 0;
132: nd_mc.dma_scurr_a = 0;
133: nd_mc.dma_out_a = 0;
134: nd_mc.vram = 0;
135: nd_mc.dram = 0;
136: nd_dp.iic_msgsz = 0;
137: nd_dp.iic_addr = 0;
138: nd_dp.csr = 0;
139: nd_dp.alpha = 0;
140: nd_dp.dma = 0;
141: nd_dp.cpu_x = 0xc;
142: nd_dp.cpu_y = 0xc;
143: nd_dp.dma_x = 0xd;
144: nd_dp.dma_y = 0xd;
145: nd_dp.iic_stat_addr = 0;
146: nd_dp.iic_data = 0;
147: }
148:
149:
150: static const char* ND_CSR0_BITS[] = {
151: "i860PIN_RESET", "i860PIN_CS8", "i860_IMASK", "i860_INT",
152: "BE_IMASK", "BE_INT", "VBL_IMASK", "VBL_INT",
153: "VBLANK", "VIOVBL_IMASK", "VIOVBL_INT", "VIOBLANK",
154: "i860_CACHE_EN", "00002000", "00004000", "00008000",
155: "00010000", "00020000", "00040000", "00080000",
156: "00100000", "00200000", "00400000", "00800000",
157: "01000000", "02000000", "04000000", "08000000",
158: "10000000", "20000000", "40000000", "80000000",
159: };
160:
161: static const char* ND_CSR1_BITS[] = {
162: "CPU_INT", "00000002", "00000004", "00000008",
163: "00000010", "00000020", "00000040", "00000080",
164: "00000100", "00000200", "00000400", "00000800",
165: "00001000", "00002000", "00004000", "00008000",
166: "00010000", "00020000", "00040000", "00080000",
167: "00100000", "00200000", "00400000", "00800000",
168: "01000000", "02000000", "04000000", "08000000",
169: "10000000", "20000000", "40000000", "80000000",
170: };
171:
172: static const char* ND_CSR2_BITS[] = {
173: "GLOBAL_ACCESS", "00000002", "00000004", "00000008",
174: "00000010", "00000020", "00000040", "00000080",
175: "00000100", "00000200", "00000400", "00000800",
176: "00001000", "00002000", "00004000", "00008000",
177: "00010000", "00020000", "00040000", "00080000",
178: "00100000", "00200000", "00400000", "00800000",
179: "01000000", "02000000", "04000000", "08000000",
180: "10000000", "20000000", "40000000", "80000000",
181: };
182:
183: static const char* ND_DMA_CSR_BITS[] = {
184: "VISIBLE_EN", "BLANKED_EN", "READ_EN", "00000008",
185: "00000010", "00000020", "00000040", "00000080",
186: "00000100", "00000200", "00000400", "00000800",
187: "00001000", "00002000", "00004000", "00008000",
188: "00010000", "00020000", "00040000", "00080000",
189: "00100000", "00200000", "00400000", "00800000",
190: "01000000", "02000000", "04000000", "08000000",
191: "10000000", "20000000", "40000000", "80000000",
192: };
193:
194: static const char* ND_VRAM_BITS[] = {
195: "VBLANK", "60HZ", "EXT_SYNC", "00000008",
196: "00000010", "00000020", "00000040", "00000080",
197: "00000100", "00000200", "00000400", "00000800",
198: "00001000", "00002000", "00004000", "00008000",
199: "00010000", "00020000", "00040000", "00080000",
200: "00100000", "00200000", "00400000", "00800000",
201: "01000000", "02000000", "04000000", "08000000",
202: "10000000", "20000000", "40000000", "80000000",
203: };
204:
205: static const char* ND_DRAM_BITS[] = {
206: "4MBIT", "00000002", "00000004", "00000008",
207: "00000010", "00000020", "00000040", "00000080",
208: "00000100", "00000200", "00000400", "00000800",
209: "00001000", "00002000", "00004000", "00008000",
210: "00010000", "00020000", "00040000", "00080000",
211: "00100000", "00200000", "00400000", "00800000",
212: "01000000", "02000000", "04000000", "08000000",
213: "10000000", "20000000", "40000000", "80000000",
214: };
215:
216: static const char* decodeBits(const char** bits, uae_u32 val) {
217: static char buffer[512];
218: char* result = buffer;
219:
220: if(bits) {
221: *result = 0;
222: for(int i = 0; i < 32; i++) {
223: if(val & (1 << i)) {
224: const char* str = bits[i];
225: while(*str) *result++ = *str++;
226: *result++ = '|';
227: }
228: }
229: if(result != buffer)
230: *--result = 0;
231: }
232: else
233: sprintf(buffer, "%08X", val);
234: return buffer;
235: }
236:
237: static const char* MC_RD_FORMAT = "[ND] Memory controller %s read %08X at %08X";
238: static const char* MC_RD_FORMAT_S = "[ND] Memory controller %s read (%s) at %08X";
239:
1.1.1.2 ! root 240: static uae_u32 nd_mc_read_register(uaecptr addr) {
1.1 root 241: switch (addr&0x3FFF) {
242: case 0x0000:
243: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr0", decodeBits(ND_CSR0_BITS, nd_mc.csr0),addr);
244: return nd_mc.csr0;
245: case 0x0010:
246: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr1", decodeBits(ND_CSR1_BITS, nd_mc.csr1),addr);
247: return nd_mc.csr1;
248: case 0x0020:
249: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr2", decodeBits(ND_CSR2_BITS, nd_mc.csr2),addr);
250: return nd_mc.csr2;
251: case 0x0030:
252: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"sid", nd_mc.sid,addr);
253: return nd_mc.sid;
254: case 0x1000:
255: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"dma_csr", decodeBits(ND_DMA_CSR_BITS, nd_mc.dma_csr),addr);
256: return nd_mc.dma_csr;
257: case 0x1010:
258: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_start", nd_mc.dma_start,addr);
259: return nd_mc.dma_start;
260: case 0x1020:
261: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_width", nd_mc.dma_width,addr);
262: return nd_mc.dma_width;
263: case 0x1030:
264: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_pstart", nd_mc.dma_pstart,addr);
265: return nd_mc.dma_pstart;
266: case 0x1040:
267: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_pwidth", nd_mc.dma_pwidth,addr);
268: return nd_mc.dma_pwidth;
269: case 0x1050:
270: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_sstart", nd_mc.dma_sstart,addr);
271: return nd_mc.dma_sstart;
272: case 0x1060:
273: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_swidth", nd_mc.dma_swidth,addr);
274: return nd_mc.dma_swidth;
275: case 0x1070:
276: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_bsstart", nd_mc.dma_bsstart,addr);
277: return nd_mc.dma_bsstart;
278: case 0x1080:
279: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_bswidth", nd_mc.dma_bswidth,addr);
280: return nd_mc.dma_bswidth;
281: case 0x1090:
282: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_top", nd_mc.dma_top,addr);
283: return nd_mc.dma_top;
284: case 0x10A0:
285: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_bottom", nd_mc.dma_bottom,addr);
286: return nd_mc.dma_bottom;
287: case 0x10B0:
288: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_line_a", nd_mc.dma_line_a,addr);
289: return nd_mc.dma_line_a;
290: case 0x10C0:
291: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_curr_a", nd_mc.dma_curr_a,addr);
292: return nd_mc.dma_curr_a;
293: case 0x10D0:
294: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_line_a", nd_mc.dma_line_a,addr);
295: return nd_mc.dma_line_a;
296: case 0x10E0:
297: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_scurr_a", nd_mc.dma_scurr_a,addr);
298: return nd_mc.dma_scurr_a;
299: case 0x10F0:
300: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_out_a", nd_mc.dma_out_a,addr);
301: return nd_mc.dma_out_a;
302: case 0x2000:
303: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"vram", decodeBits(ND_VRAM_BITS, nd_mc.vram),addr);
304: return nd_mc.vram;
305: case 0x3000:
306: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"dram", decodeBits(ND_DRAM_BITS, nd_mc.dram),addr);
307: return nd_mc.dram;
308: default:
309: Log_Printf(LOG_WARN, "[ND] Memory controller UNKNOWN read at %08X",addr);
310: break;
311: }
312: return 0;
313: }
314:
315: static const char* MC_WR_FORMAT = "[ND] Memory controller %s write %08X at %08X";
316: static const char* MC_WR_FORMAT_S = "[ND] Memory controller %s write (%s) at %08X";
317:
1.1.1.2 ! root 318: static void nd_mc_write_register(uaecptr addr, uae_u32 val) {
1.1 root 319: switch (addr&0x3FFF) {
320: case 0x0000:
321: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr0", decodeBits(ND_CSR0_BITS, val), addr);
322: if(val & CSR0_i860PIN_RESET) {
323: i860_reset();
324: val &= ~CSR0_i860PIN_RESET;
325: }
1.1.1.2 ! root 326: if ((val & CSR0_i860_INT) && (val & CSR0_i860_IMASK))
! 327: i860_interrupt();
1.1 root 328:
1.1.1.2 ! root 329: if((val & CSR0_BE_INT) && (val & CSR0_BE_IMASK))
! 330: i860_interrupt();
1.1 root 331:
332: nd_mc.csr0 = val;
333: break;
334: case 0x0010:
335: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr1", decodeBits(ND_CSR1_BITS, val),addr);
336: nd_mc.csr1 = val;
337: if (nd_mc.csr1&CSR1_CPU_INT) {
338: nd_nbic_set_intstatus(true);
339: } else {
340: nd_nbic_set_intstatus(false);
341: }
342: break;
343: case 0x0020:
344: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr2", decodeBits(ND_CSR2_BITS, val),addr);
345: nd_mc.csr2 = val;
346: break;
347: case 0x0030:
348: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"sid", val,addr);
349: nd_mc.sid = val;
350: break;
351: case 0x1000:
352: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"dma_csr", decodeBits(ND_DMA_CSR_BITS, val),addr);
353: nd_mc.dma_csr = val;
354: break;
355: case 0x1010:
356: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_start", val,addr);
357: nd_mc.dma_start = val;
358: break;
359: case 0x1020:
360: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_width", val,addr);
361: nd_mc.dma_width = val;
362: break;
363: case 0x1030:
364: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_pstart", val,addr);
365: nd_mc.dma_pstart = val;
366: break;
367: case 0x1040:
368: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_pwidth", val,addr);
369: nd_mc.dma_pwidth = val;
370: break;
371: case 0x1050:
372: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_sstart", val,addr);
373: nd_mc.dma_sstart = val;
374: break;
375: case 0x1060:
376: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_swidth", val,addr);
377: nd_mc.dma_swidth = val;
378: break;
379: case 0x1070:
380: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_bsstart", val,addr);
381: nd_mc.dma_bsstart = val;
382: break;
383: case 0x1080:
384: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_bswidth", val,addr);
385: nd_mc.dma_bswidth = val;
386: break;
387: case 0x1090:
388: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_top", val,addr);
389: nd_mc.dma_top = val;
390: break;
391: case 0x10A0:
392: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_bottom", val,addr);
393: nd_mc.dma_bottom = val;
394: break;
395: case 0x10B0:
396: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_line_a", val,addr);
397: nd_mc.dma_line_a = val;
398: break;
399: case 0x10C0:
400: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_curr_a", val,addr);
401: nd_mc.dma_curr_a = val;
402: break;
403: case 0x10D0:
404: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_line_a", val,addr);
405: nd_mc.dma_line_a = val;
406: break;
407: case 0x10E0:
408: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_scurr_a", val,addr);
409: nd_mc.dma_scurr_a = val;
410: break;
411: case 0x10F0:
412: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_out_a", val,addr);
413: nd_mc.dma_out_a = val;
414: break;
415: case 0x2000:
416: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"vram", decodeBits(ND_VRAM_BITS, val),addr);
417: nd_mc.vram = val;
418: break;
419: case 0x3000:
420: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"dram", decodeBits(ND_DRAM_BITS, val),addr);
421: nd_mc.dram = val;
422: break;
423: default:
424: Log_Printf(LOG_WARN, "[ND] Memory controller UNKNOWN write at %08X",addr);
425: break;
426: }
427: }
428:
429: /* NeXTdimension device space */
430: inline uae_u32 nd_io_lget(uaecptr addr) {
431: return nd_mc_read_register(addr);
432: }
433:
434: inline uae_u32 nd_io_wget(uaecptr addr) {
435: return 0;
436: }
437:
438: inline uae_u32 nd_io_bget(uaecptr addr) {
439: return 0;
440: }
441:
442: inline void nd_io_lput(uaecptr addr, uae_u32 l) {
443: nd_mc_write_register(addr, l);
444: }
445:
446: inline void nd_io_wput(uaecptr addr, uae_u32 w) {
447:
448: }
449:
450: inline void nd_io_bput(uaecptr addr, uae_u32 b) {
451:
452: }
453:
454: /* NeXTdimension RAMDAC */
455:
1.1.1.2 ! root 456: bt463 nd_ramdac;
! 457:
! 458: inline uae_u32 nd_ramdac_lget(uaecptr addr) {
! 459: return bt463_bget(&nd_ramdac, addr) << 24;
! 460: }
! 461:
! 462: inline uae_u32 nd_ramdac_wget(uaecptr addr) {
! 463: return bt463_bget(&nd_ramdac, addr) << 8;
1.1 root 464: }
465:
466: inline uae_u32 nd_ramdac_bget(uaecptr addr) {
1.1.1.2 ! root 467: return bt463_bget(&nd_ramdac, addr);
! 468: }
! 469:
! 470: inline void nd_ramdac_lput(uaecptr addr, uae_u32 l) {
! 471: bt463_bput(&nd_ramdac, addr, l >> 24);
! 472: }
! 473:
! 474: inline void nd_ramdac_wput(uaecptr addr, uae_u32 w) {
! 475: bt463_bput(&nd_ramdac, addr, w >> 8);
1.1 root 476: }
477:
478: inline void nd_ramdac_bput(uaecptr addr, uae_u32 b) {
1.1.1.2 ! root 479: bt463_bput(&nd_ramdac, addr, b);
1.1 root 480: }
481:
482: /* NeXTdimension data path */
483:
1.1.1.2 ! root 484: static void nd_dp_iicmsg(void) {
! 485: Log_Printf(LOG_NONE, "[ND] data path IIC msg addr:%02X msg[%d]=%02X", nd_dp.iic_addr, nd_dp.iic_msgsz-1, nd_dp.iic_msg);
! 486:
! 487: nd_video_dev_write(nd_dp.iic_addr, nd_dp.iic_msgsz-1, nd_dp.iic_msg);
1.1 root 488: }
489:
1.1.1.2 ! root 490: uae_u32 nd_dp_lget(uaecptr addr) {
1.1 root 491: switch(addr) {
492: case 0x300: case 0x304: case 0x308: case 0x30C:
493: case 0x310: case 0x314: case 0x318: case 0x31C:
494: case 0x320: case 0x324: case 0x328: case 0x32C:
495: case 0x330: case 0x334: case 0x338: case 0x33C:
496: return nd_dp.doff;
497: case 0x340:
498: return nd_dp.csr;
499: case 0x344:
500: return nd_dp.alpha;
501: case 0x348:
502: return nd_dp.dma;
503: case 0x350:
504: return nd_dp.cpu_x;
505: case 0x354:
506: return nd_dp.cpu_y;
507: case 0x358:
508: return nd_dp.dma_x;
509: case 0x35C:
510: return nd_dp.dma_y;
511: case 0x360:
512: if(nd_dp.iic_busy <= 0)
513: nd_dp.iic_stat_addr &= ~DP_IIC_BUSY;
514: else
515: nd_dp.iic_busy--;
516: return nd_dp.iic_stat_addr;
517: case 0x364:
518: return 0;
519: default:
520: Log_Printf(LOG_WARN, "[ND] data path UNKNOWN read at %08X",addr);
521: }
522: return 0;
523: }
524:
1.1.1.2 ! root 525: void nd_dp_lput(uaecptr addr, uae_u32 v) {
1.1 root 526: switch(addr) {
527: case 0x300: case 0x304: case 0x308: case 0x30C:
528: case 0x310: case 0x314: case 0x318: case 0x31C:
529: case 0x320: case 0x324: case 0x328: case 0x32C:
530: case 0x330: case 0x334: case 0x338: case 0x33C:
531: nd_dp.doff = v;
532: break;
533: case 0x340:
534: nd_dp.csr = v;
535: break;
536: case 0x344:
537: nd_dp.alpha = v;
538: break;
539: case 0x348:
540: nd_dp.dma = v;
541: break;
542: case 0x350:
543: nd_dp.cpu_x = v;
544: break;
545: case 0x354:
546: nd_dp.cpu_y = v;
547: break;
548: case 0x358:
549: nd_dp.dma_x = v;
550: break;
551: case 0x35C:
552: nd_dp.dma_y = v;
553: break;
554: case 0x360:
555: nd_dp.iic_msgsz = 0;
1.1.1.2 ! root 556: nd_dp.iic_addr = (v >> 8) & 0xFF;
! 557: nd_dp.iic_msg = v;
! 558: nd_dp.iic_msgsz++;
1.1 root 559: nd_dp.iic_stat_addr |= DP_IIC_BUSY;
560: nd_dp.iic_busy = 10;
561: nd_dp_iicmsg();
562: break;
563: case 0x364:
1.1.1.2 ! root 564: nd_dp.iic_msg = v;
! 565: nd_dp.iic_msgsz++;
1.1 root 566: nd_dp.iic_stat_addr |= DP_IIC_BUSY;
567: nd_dp.iic_busy = 10;
568: nd_dp_iicmsg();
569: break;
570: default:
571: Log_Printf(LOG_WARN, "[ND] data path UNKNOWN write at %08X %08X",addr,v);
572: }
573: }
574:
1.1.1.2 ! root 575: void nd_set_blank_state(int src, bool state) {
! 576: switch (src) {
! 577: case ND_DISPLAY:
! 578: if(state) {
! 579: nd_mc.csr0 |= CSR0_VBL_INT | CSR0_VBLANK;
! 580: if (nd_mc.csr0 & CSR0_VBL_IMASK) {
! 581: i860_interrupt();
! 582: }
! 583: } else {
! 584: nd_mc.csr0 &= ~CSR0_VBLANK;
! 585: }
! 586: break;
! 587: case ND_VIDEO:
! 588: if(state) {
! 589: nd_mc.csr0 |= CSR0_VIOVBL_INT | CSR0_VIOBLANK;
! 590: if (nd_mc.csr0 & CSR0_VIOVBL_IMASK) {
! 591: i860_interrupt();
! 592: }
! 593: } else {
! 594: nd_mc.csr0 &= ~CSR0_VIOBLANK;
! 595: }
! 596: break;
! 597: }
! 598: }
! 599:
1.1 root 600: static const char* nd_dump_path = "nd_memory.bin";
601:
602: /* debugger stuff */
603: bool nd_dbg_cmd(const char* buf) {
604: if(!(buf)) {
605: fprintf(stderr,
606: " w: write NeXTdimension DRAM to file '%s'\n"
607: " n: dump NeXTdimension registers\n"
608: , nd_dump_path);
609: return false;
610: }
611:
612: switch(buf[0]) {
613: case 'w': {
614: FILE* fp = fopen(nd_dump_path, "wb");
615: size_t size = ConfigureParams.Dimension.nMemoryBankSize[0];
616: size += ConfigureParams.Dimension.nMemoryBankSize[1];
617: size += ConfigureParams.Dimension.nMemoryBankSize[2];
618: size += ConfigureParams.Dimension.nMemoryBankSize[3];
1.1.1.2 ! root 619: fprintf(stderr, "Writing %"FMT_zu"MB to '%s'...", size, nd_dump_path);
1.1 root 620: size <<= 20;
621: fwrite(ND_ram, sizeof(Uint8), size, fp);
622: fclose(fp);
623: fprintf(stderr, "done.");
624: return true;
625: }
626: case 'n': {
627: fprintf(stderr, "csr0 (%s)\n", decodeBits(ND_CSR0_BITS, nd_mc.csr0));
628: fprintf(stderr, "csr1 (%s)\n", decodeBits(ND_CSR1_BITS, nd_mc.csr1));
629: fprintf(stderr, "csr2 (%s)\n", decodeBits(ND_CSR2_BITS, nd_mc.csr2));
630: fprintf(stderr, "sid (%s)\n", decodeBits(0, nd_mc.sid));
631: fprintf(stderr, "dma_csr (%s)\n", decodeBits(ND_DMA_CSR_BITS, nd_mc.dma_csr));
632: fprintf(stderr, "dma_start (%s)\n", decodeBits(0, nd_mc.dma_start));
633: fprintf(stderr, "dma_width (%s)\n", decodeBits(0, nd_mc.dma_width));
634: fprintf(stderr, "dma_pstart (%s)\n", decodeBits(0, nd_mc.dma_pstart));
635: fprintf(stderr, "dma_pwidth (%s)\n", decodeBits(0, nd_mc.dma_pwidth));
636: fprintf(stderr, "dma_sstart (%s)\n", decodeBits(0, nd_mc.dma_sstart));
637: fprintf(stderr, "dma_swidth (%s)\n", decodeBits(0, nd_mc.dma_swidth));
638: fprintf(stderr, "dma_bsstart (%s)\n", decodeBits(0, nd_mc.dma_bsstart));
639: fprintf(stderr, "dma_bswidth (%s)\n", decodeBits(0, nd_mc.dma_bswidth));
640: fprintf(stderr, "dma_top (%s)\n", decodeBits(0, nd_mc.dma_top));
641: fprintf(stderr, "dma_bottom (%s)\n", decodeBits(0, nd_mc.dma_bottom));
642: fprintf(stderr, "dma_line_a (%s)\n", decodeBits(0, nd_mc.dma_line_a));
643: fprintf(stderr, "dma_curr_a (%s)\n", decodeBits(0, nd_mc.dma_curr_a));
644: fprintf(stderr, "dma_scurr_a (%s)\n", decodeBits(0, nd_mc.dma_scurr_a));
645: fprintf(stderr, "dma_out_a (%s)\n", decodeBits(0, nd_mc.dma_out_a));
646: fprintf(stderr, "vram (%s)\n", decodeBits(ND_VRAM_BITS, nd_mc.vram));
647: fprintf(stderr, "dram (%s)\n", decodeBits(ND_DRAM_BITS, nd_mc.dram));
648: return true;
649: }
650: default:
651: return false;
652: }
653: }
654:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.