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1.1 root 1: #include <stdio.h>
2: #include <limits.h>
3: #include <stdlib.h>
4:
5: #include "main.h"
6: #include "configuration.h"
7: #include "m68000.h"
8: #include "sysdeps.h"
9: #include "dimension.hpp"
10: #include "nd_mem.hpp"
11: #include "nd_nbic.hpp"
12: #include "i860cfg.h"
13: #include "nd_sdl.hpp"
14: #include "ramdac.h"
15: #include "host.h"
16: #include "log.h"
17:
18: /* --------- NEXTDIMENSION DEVICES ---------- */
19:
20: /* Device registers */
21:
22: /* Memory controller */
23: #define ND_MC_CSR0 0xFF800000
24: #define ND_MC_CSR1 0xFF800010
25: #define ND_MC_CSR2 0xFF800020
26: #define ND_MC_SID 0xFF800030
27:
28: #define ND_MC_DMA_CSR 0xFF801000
29:
30: #define ND_MC_VRAM_TIMING 0xFF802000
31: #define ND_MC_DRAM_SIZE 0xFF803000
32:
33: /* CSR bits */
34: #define CSR0_i860PIN_RESET 0x00000001
35: #define CSR0_i860PIN_CS8 0x00000002
36: #define CSR0_i860_IMASK 0x00000004
37: #define CSR0_i860_INT 0x00000008
38: #define CSR0_BE_IMASK 0x00000010
39: #define CSR0_BE_INT 0x00000020
40: #define CSR0_VBL_IMASK 0x00000040
41: #define CSR0_VBL_INT 0x00000080
42: #define CSR0_VBLANK 0x00000100 /* ro */
43: #define CSR0_VIOVBL_IMASK 0x00000200
44: #define CSR0_VIOVBL_INT 0x00000400
45: #define CSR0_VIOBLANK 0x00000800 /* ro */
46: #define CSR0_i860_CACHE_EN 0x00001000
47:
48: #define CSR1_CPU_INT 0x00000001
49:
50: #define CSR2_GLOBAL_ACCESS 0x00000001
51:
52: #define SID_SID_MASK 0x0000000F
53: #define SID_STEP_MASK 0x000000F0
54:
55: #define CSRDMA_VISIBLE_EN 0x00000001
56: #define CSRDMA_BLANKED_EN 0x00000002
57: #define CSRDMA_READ_EN 0x00000004
58:
59: #define CSRVRAM_VBLANK 0x00000001
60: #define CSRVRAM_60HZ 0x00000002
61: #define CSRVRAM_EXT_SYNC 0x00000004
62:
63: #define CSRDRAM_4MBIT 0x00000001
64:
65: #define DP_IIC_MORE 0x20000000
66: #define DP_IIC_BUSY 0x80000000
67:
68: #define DP_CSR_MASK_DIS 0x01
69: #define DP_CSR_NTSC 0x02 /* 0 = NTSC, 1 = PAL */
70: #define DP_CSR_JPEG_MASK 0xFC
71:
72: MC::MC(NextDimension* nd) : nd(nd) {}
73:
74: void MC::init(void) {
75: csr0 = CSR0_i860PIN_CS8;
76: csr1 = 0;
77: csr2 = 0;
78: sid = nd->slot|(ND_STEP<<4);
79: dma_csr = 0;
80: dma_start = 0;
81: dma_width = 0;
82: dma_pstart = 0;
83: dma_pwidth = 0;
84: dma_sstart = 0;
85: dma_swidth = 0;
86: dma_bsstart = 0;
87: dma_bswidth = 0;
88: dma_top = 0;
89: dma_bottom = 0;
90: dma_line_a = 0;
91: dma_curr_a = 0;
92: dma_scurr_a = 0;
93: dma_out_a = 0;
94: vram = 0;
95: dram = 0;
96: }
97:
98: DP::DP(NextDimension* nd) : nd(nd) {}
99:
100: void DP::init(void) {
101: iic_msgsz = 0;
102: iic_addr = 0;
103: csr = 0;
104: alpha = 0;
105: dma = 0;
106: cpu_x = 0xc;
107: cpu_y = 0xc;
108: dma_x = 0xd;
109: dma_y = 0xd;
110: iic_stat_addr = 0;
111: iic_data = 0;
112: }
113:
114:
115: static const char* ND_CSR0_BITS[] = {
116: "i860PIN_RESET", "i860PIN_CS8", "i860_IMASK", "i860_INT",
117: "BE_IMASK", "BE_INT", "VBL_IMASK", "VBL_INT",
118: "VBLANK", "VIOVBL_IMASK", "VIOVBL_INT", "VIOBLANK",
119: "i860_CACHE_EN", "00002000", "00004000", "00008000",
120: "00010000", "00020000", "00040000", "00080000",
121: "00100000", "00200000", "00400000", "00800000",
122: "01000000", "02000000", "04000000", "08000000",
123: "10000000", "20000000", "40000000", "80000000",
124: };
125:
126: static const char* ND_CSR1_BITS[] = {
127: "CPU_INT", "00000002", "00000004", "00000008",
128: "00000010", "00000020", "00000040", "00000080",
129: "00000100", "00000200", "00000400", "00000800",
130: "00001000", "00002000", "00004000", "00008000",
131: "00010000", "00020000", "00040000", "00080000",
132: "00100000", "00200000", "00400000", "00800000",
133: "01000000", "02000000", "04000000", "08000000",
134: "10000000", "20000000", "40000000", "80000000",
135: };
136:
137: static const char* ND_CSR2_BITS[] = {
138: "GLOBAL_ACCESS", "00000002", "00000004", "00000008",
139: "00000010", "00000020", "00000040", "00000080",
140: "00000100", "00000200", "00000400", "00000800",
141: "00001000", "00002000", "00004000", "00008000",
142: "00010000", "00020000", "00040000", "00080000",
143: "00100000", "00200000", "00400000", "00800000",
144: "01000000", "02000000", "04000000", "08000000",
145: "10000000", "20000000", "40000000", "80000000",
146: };
147:
148: static const char* ND_DMA_CSR_BITS[] = {
149: "VISIBLE_EN", "BLANKED_EN", "READ_EN", "00000008",
150: "00000010", "00000020", "00000040", "00000080",
151: "00000100", "00000200", "00000400", "00000800",
152: "00001000", "00002000", "00004000", "00008000",
153: "00010000", "00020000", "00040000", "00080000",
154: "00100000", "00200000", "00400000", "00800000",
155: "01000000", "02000000", "04000000", "08000000",
156: "10000000", "20000000", "40000000", "80000000",
157: };
158:
159: static const char* ND_VRAM_BITS[] = {
160: "VBLANK", "60HZ", "EXT_SYNC", "00000008",
161: "00000010", "00000020", "00000040", "00000080",
162: "00000100", "00000200", "00000400", "00000800",
163: "00001000", "00002000", "00004000", "00008000",
164: "00010000", "00020000", "00040000", "00080000",
165: "00100000", "00200000", "00400000", "00800000",
166: "01000000", "02000000", "04000000", "08000000",
167: "10000000", "20000000", "40000000", "80000000",
168: };
169:
170: static const char* ND_DRAM_BITS[] = {
171: "4MBIT", "00000002", "00000004", "00000008",
172: "00000010", "00000020", "00000040", "00000080",
173: "00000100", "00000200", "00000400", "00000800",
174: "00001000", "00002000", "00004000", "00008000",
175: "00010000", "00020000", "00040000", "00080000",
176: "00100000", "00200000", "00400000", "00800000",
177: "01000000", "02000000", "04000000", "08000000",
178: "10000000", "20000000", "40000000", "80000000",
179: };
180:
181: static const char* decodeBits(const char** bits, uae_u32 val) {
182: static char buffer[512];
183: char* result = buffer;
184:
185: if(bits) {
186: *result = 0;
187: for(int i = 0; i < 32; i++) {
188: if(val & (1 << i)) {
189: const char* str = bits[i];
190: while(*str) *result++ = *str++;
191: *result++ = '|';
192: }
193: }
194: if(result != buffer)
195: *--result = 0;
196: }
197: else
198: sprintf(buffer, "%08X", val);
199: return buffer;
200: }
201:
202: static const char* MC_RD_FORMAT = "[ND] Memory controller %s read %08X at %08X";
203: static const char* MC_RD_FORMAT_S = "[ND] Memory controller %s read (%s) at %08X";
204:
205: Uint32 MC::read(Uint32 addr) {
206: switch (addr&0x3FFF) {
207: case 0x0000:
208: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr0", decodeBits(ND_CSR0_BITS, csr0),addr);
209: return csr0;
210: case 0x0010:
211: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr1", decodeBits(ND_CSR1_BITS, csr1),addr);
212: return csr1;
213: case 0x0020:
214: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr2", decodeBits(ND_CSR2_BITS, csr2),addr);
215: return csr2;
216: case 0x0030:
217: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"sid", sid,addr);
218: return sid;
219: case 0x1000:
220: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"dma_csr", decodeBits(ND_DMA_CSR_BITS, dma_csr),addr);
221: return dma_csr;
222: case 0x1010:
223: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_start", dma_start,addr);
224: return dma_start;
225: case 0x1020:
226: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_width", dma_width,addr);
227: return dma_width;
228: case 0x1030:
229: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_pstart", dma_pstart,addr);
230: return dma_pstart;
231: case 0x1040:
232: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_pwidth", dma_pwidth,addr);
233: return dma_pwidth;
234: case 0x1050:
235: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_sstart", dma_sstart,addr);
236: return dma_sstart;
237: case 0x1060:
238: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_swidth", dma_swidth,addr);
239: return dma_swidth;
240: case 0x1070:
241: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_bsstart", dma_bsstart,addr);
242: return dma_bsstart;
243: case 0x1080:
244: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_bswidth", dma_bswidth,addr);
245: return dma_bswidth;
246: case 0x1090:
247: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_top", dma_top,addr);
248: return dma_top;
249: case 0x10A0:
250: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_bottom", dma_bottom,addr);
251: return dma_bottom;
252: case 0x10B0:
253: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_line_a", dma_line_a,addr);
254: return dma_line_a;
255: case 0x10C0:
256: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_curr_a", dma_curr_a,addr);
257: return dma_curr_a;
258: case 0x10D0:
259: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_line_a", dma_line_a,addr);
260: return dma_line_a;
261: case 0x10E0:
262: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_scurr_a", dma_scurr_a,addr);
263: return dma_scurr_a;
264: case 0x10F0:
265: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_out_a", dma_out_a,addr);
266: return dma_out_a;
267: case 0x2000:
268: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"vram", decodeBits(ND_VRAM_BITS, vram),addr);
269: return vram;
270: case 0x3000:
271: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"dram", decodeBits(ND_DRAM_BITS, dram),addr);
272: return dram;
273: default:
274: Log_Printf(LOG_WARN, "[ND] Memory controller UNKNOWN read at %08X",addr);
275: break;
276: }
277: return 0;
278: }
279:
280: static const char* MC_WR_FORMAT = "[ND] Memory controller %s write %08X at %08X";
281: static const char* MC_WR_FORMAT_S = "[ND] Memory controller %s write (%s) at %08X";
282:
283: void MC::write(Uint32 addr, Uint32 val) {
284: switch (addr&0x3FFF) {
285: case 0x0000:
286: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr0", decodeBits(ND_CSR0_BITS, val), addr);
287: if(val & CSR0_i860PIN_RESET) {
288: nd->send_msg(MSG_I860_RESET);
289: val &= ~CSR0_i860PIN_RESET;
290: }
291: if ((val & CSR0_i860_INT) && (val & CSR0_i860_IMASK))
292: nd->send_msg(MSG_INTR);
293:
294: if((val & CSR0_BE_INT) && (val & CSR0_BE_IMASK))
295: nd->send_msg(MSG_INTR);
296:
297: csr0 = val;
298: break;
299: case 0x0010:
300: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr1", decodeBits(ND_CSR1_BITS, val),addr);
301: csr1 = val;
302: if (csr1&CSR1_CPU_INT) {
303: nd->nbic.set_intstatus(true);
304: } else {
305: nd->nbic.set_intstatus(false);
306: }
307: break;
308: case 0x0020:
309: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr2", decodeBits(ND_CSR2_BITS, val),addr);
310: csr2 = val;
311: break;
312: case 0x0030:
313: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"sid", val,addr);
314: sid = val;
315: break;
316: case 0x1000:
317: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"dma_csr", decodeBits(ND_DMA_CSR_BITS, val),addr);
318: dma_csr = val;
319: break;
320: case 0x1010:
321: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_start", val,addr);
322: dma_start = val;
323: break;
324: case 0x1020:
325: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_width", val,addr);
326: dma_width = val;
327: break;
328: case 0x1030:
329: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_pstart", val,addr);
330: dma_pstart = val;
331: break;
332: case 0x1040:
333: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_pwidth", val,addr);
334: dma_pwidth = val;
335: break;
336: case 0x1050:
337: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_sstart", val,addr);
338: dma_sstart = val;
339: break;
340: case 0x1060:
341: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_swidth", val,addr);
342: dma_swidth = val;
343: break;
344: case 0x1070:
345: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_bsstart", val,addr);
346: dma_bsstart = val;
347: break;
348: case 0x1080:
349: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_bswidth", val,addr);
350: dma_bswidth = val;
351: break;
352: case 0x1090:
353: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_top", val,addr);
354: dma_top = val;
355: break;
356: case 0x10A0:
357: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_bottom", val,addr);
358: dma_bottom = val;
359: break;
360: case 0x10B0:
361: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_line_a", val,addr);
362: dma_line_a = val;
363: break;
364: case 0x10C0:
365: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_curr_a", val,addr);
366: dma_curr_a = val;
367: break;
368: case 0x10D0:
369: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_line_a", val,addr);
370: dma_line_a = val;
371: break;
372: case 0x10E0:
373: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_scurr_a", val,addr);
374: dma_scurr_a = val;
375: break;
376: case 0x10F0:
377: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_out_a", val,addr);
378: dma_out_a = val;
379: break;
380: case 0x2000:
381: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"vram", decodeBits(ND_VRAM_BITS, val),addr);
382: vram = val;
383: break;
384: case 0x3000:
385: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"dram", decodeBits(ND_DRAM_BITS, val),addr);
386: dram = val;
387: break;
388: default:
389: Log_Printf(LOG_WARN, "[ND] Memory controller UNKNOWN write at %08X",addr);
390: break;
391: }
392: }
393:
394: /* NeXTdimension data path */
395:
396: void DP::iicmsg(void) {
397: Log_Printf(LOG_NONE, "[ND] data path IIC msg addr:%02X msg[%d]=%02X",
398: iic_addr, iic_msgsz-1, iic_msg);
399:
400: nd->video_dev_write(iic_addr, iic_msgsz-1, iic_msg);
401: }
402:
403: Uint32 DP::lget(Uint32 addr) {
404: switch(addr) {
405: case 0x300: case 0x304: case 0x308: case 0x30C:
406: case 0x310: case 0x314: case 0x318: case 0x31C:
407: case 0x320: case 0x324: case 0x328: case 0x32C:
408: case 0x330: case 0x334: case 0x338: case 0x33C:
409: return doff;
410: case 0x340:
411: return csr;
412: case 0x344:
413: return alpha;
414: case 0x348:
415: return dma;
416: case 0x350:
417: return cpu_x;
418: case 0x354:
419: return cpu_y;
420: case 0x358:
421: return dma_x;
422: case 0x35C:
423: return dma_y;
424: case 0x360:
425: if(iic_busy <= 0)
426: iic_stat_addr &= ~DP_IIC_BUSY;
427: else
428: iic_busy--;
429: return iic_stat_addr;
430: case 0x364:
431: return 0;
432: default:
433: Log_Printf(LOG_WARN, "[ND] data path UNKNOWN read at %08X",addr);
434: }
435: return 0;
436: }
437:
438: void DP::lput(Uint32 addr, Uint32 v) {
439: switch(addr) {
440: case 0x300: case 0x304: case 0x308: case 0x30C:
441: case 0x310: case 0x314: case 0x318: case 0x31C:
442: case 0x320: case 0x324: case 0x328: case 0x32C:
443: case 0x330: case 0x334: case 0x338: case 0x33C:
444: doff = v;
445: break;
446: case 0x340:
447: csr = v;
448: break;
449: case 0x344:
450: alpha = v;
451: break;
452: case 0x348:
453: dma = v;
454: break;
455: case 0x350:
456: cpu_x = v;
457: break;
458: case 0x354:
459: cpu_y = v;
460: break;
461: case 0x358:
462: dma_x = v;
463: break;
464: case 0x35C:
465: dma_y = v;
466: break;
467: case 0x360:
468: iic_msgsz = 0;
469: iic_addr = (v >> 8) & 0xFF;
470: iic_msg = v;
471: iic_msgsz++;
472: iic_stat_addr |= DP_IIC_BUSY;
473: iic_busy = 10;
474: iicmsg();
475: break;
476: case 0x364:
477: iic_msg = v;
478: iic_msgsz++;
479: iic_stat_addr |= DP_IIC_BUSY;
480: iic_busy = 10;
481: iicmsg();
482: break;
483: default:
484: Log_Printf(LOG_WARN, "[ND] data path UNKNOWN write at %08X %08X",addr,v);
485: }
486: }
487:
488: void NextDimension::set_blank_state(int src, bool state) {
489: switch (src) {
490: case ND_DISPLAY:
491: if(state) {
492: mc.csr0 |= CSR0_VBL_INT | CSR0_VBLANK;
493: if (mc.csr0 & CSR0_VBL_IMASK) {
494: send_msg(MSG_INTR);
495: }
496: } else {
497: mc.csr0 &= ~CSR0_VBLANK;
498: }
499: break;
500: case ND_VIDEO:
501: if(state) {
502: mc.csr0 |= CSR0_VIOVBL_INT | CSR0_VIOBLANK;
503: if (mc.csr0 & CSR0_VIOVBL_IMASK) {
504: send_msg(MSG_INTR);
505: }
506: } else {
507: mc.csr0 &= ~CSR0_VIOBLANK;
508: }
509: break;
510: }
511: }
512:
513: static const char* nd_dump_path = "nd_memory.bin";
514:
515: /* debugger stuff */
516: bool NextDimension::dbg_cmd(const char* buf) {
517: if(!(buf)) {
518: fprintf(stderr,
519: " w: write NeXTdimension DRAM to file '%s'\n"
520: " n: dump NeXTdimension registers\n"
521: , nd_dump_path);
522: return false;
523: }
524:
525: switch(buf[0]) {
526: case 'w': {
527: FILE* fp = fopen(nd_dump_path, "wb");
528: size_t size = ConfigureParams.Dimension.board[ND_NUM(slot)].nMemoryBankSize[0];
529: size += ConfigureParams.Dimension.board[ND_NUM(slot)].nMemoryBankSize[1];
530: size += ConfigureParams.Dimension.board[ND_NUM(slot)].nMemoryBankSize[2];
531: size += ConfigureParams.Dimension.board[ND_NUM(slot)].nMemoryBankSize[3];
532: fprintf(stderr, "Writing %"FMT_zu"MB to '%s'...", size, nd_dump_path);
533: size <<= 20;
534: fwrite(ram, sizeof(Uint8), size, fp);
535: fclose(fp);
536: fprintf(stderr, "done.");
537: return true;
538: }
539: case 'n': {
540: fprintf(stderr, "csr0 (%s)\n", decodeBits(ND_CSR0_BITS, mc.csr0));
541: fprintf(stderr, "csr1 (%s)\n", decodeBits(ND_CSR1_BITS, mc.csr1));
542: fprintf(stderr, "csr2 (%s)\n", decodeBits(ND_CSR2_BITS, mc.csr2));
543: fprintf(stderr, "sid (%s)\n", decodeBits(0, mc.sid));
544: fprintf(stderr, "dma_csr (%s)\n", decodeBits(ND_DMA_CSR_BITS, mc.dma_csr));
545: fprintf(stderr, "dma_start (%s)\n", decodeBits(0, mc.dma_start));
546: fprintf(stderr, "dma_width (%s)\n", decodeBits(0, mc.dma_width));
547: fprintf(stderr, "dma_pstart (%s)\n", decodeBits(0, mc.dma_pstart));
548: fprintf(stderr, "dma_pwidth (%s)\n", decodeBits(0, mc.dma_pwidth));
549: fprintf(stderr, "dma_sstart (%s)\n", decodeBits(0, mc.dma_sstart));
550: fprintf(stderr, "dma_swidth (%s)\n", decodeBits(0, mc.dma_swidth));
551: fprintf(stderr, "dma_bsstart (%s)\n", decodeBits(0, mc.dma_bsstart));
552: fprintf(stderr, "dma_bswidth (%s)\n", decodeBits(0, mc.dma_bswidth));
553: fprintf(stderr, "dma_top (%s)\n", decodeBits(0, mc.dma_top));
554: fprintf(stderr, "dma_bottom (%s)\n", decodeBits(0, mc.dma_bottom));
555: fprintf(stderr, "dma_line_a (%s)\n", decodeBits(0, mc.dma_line_a));
556: fprintf(stderr, "dma_curr_a (%s)\n", decodeBits(0, mc.dma_curr_a));
557: fprintf(stderr, "dma_scurr_a (%s)\n", decodeBits(0, mc.dma_scurr_a));
558: fprintf(stderr, "dma_out_a (%s)\n", decodeBits(0, mc.dma_out_a));
559: fprintf(stderr, "vram (%s)\n", decodeBits(ND_VRAM_BITS, mc.vram));
560: fprintf(stderr, "dram (%s)\n", decodeBits(ND_DRAM_BITS, mc.dram));
561: return true;
562: }
563: default:
564: return false;
565: }
566: }
567:
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