--- previous/src/dimension/nd_mem.c 2018/04/24 19:30:01 1.1 +++ previous/src/dimension/nd_mem.c 2018/04/24 19:31:35 1.1.1.2 @@ -7,8 +7,6 @@ #include "nd_devs.h" #include "nd_rom.h" -#if ENABLE_DIMENSION - #define write_log printf /* --------- NEXTDIMENSION MEMORY ---------- */ @@ -22,7 +20,7 @@ #define ND_VRAM_SIZE 0x00400000 #define ND_VRAM_MASK 0x003FFFFF -#define ND_EEPROM_START 0xFFFE0000 +#define ND_EEPROM_START 0xFFF00000 #define ND_EEPROM_SIZE 0x00020000 #define ND_EEPROM_MASK 0x0001FFFF @@ -35,7 +33,6 @@ uae_u32 ND_RAM_bankmask2; uae_u32 ND_RAM_bankmask3; Uint8 ND_ram[64*1024*1024]; -Uint32 ND_vram_off; Uint8 ND_vram[4*1024*1024]; Uint8 ND_rom[128*1024]; @@ -61,16 +58,29 @@ Uint8 ND_dmem[512]; #define ND_DP_SIZE 0x00001000 #define ND_DP_MASK 0x00000FFF -/* NeXTdimension EEPROM access */ -#define ND_EEPROM2_STRT 0xFFF00000 -#define ND_EEPROM2_SIZE 0x00080000 -#define ND_EEPROM2_MASK 0x0007FFFC +/* NeXTdimension unknown registers */ +#define ND_UNKNWN_START 0xFF400000 +#define ND_UNKNWN_SIZE 0x00000200 +#define ND_UNKNWN_MASK 0x000001FF + +/* Function to fix address for ROM access */ +static uaecptr nd_rom_addr_fix(uaecptr addr) +{ +#if ND_STEP + addr >>= 2; +#else + addr &= ~3; + addr |= (addr>>17)&3; +#endif + addr &= ND_EEPROM_MASK; + return addr; +} /* Memory banks */ nd_addrbank *nd_mem_banks[65536]; -void nd_map_banks (nd_addrbank *bank, int start, int size) +static void nd_map_banks (nd_addrbank *bank, int start, int size) { int bnr; @@ -297,23 +307,44 @@ static void nd_vram_bput(uaecptr addr, u /* NeXTdimension ROM */ static uae_u32 nd_rom_lget(uaecptr addr) { - addr &= ND_EEPROM_MASK; - addr |= 3; /* byte lane at msb */ - return (ND_rom[addr] << 24); + addr = nd_rom_addr_fix(addr); + + return (nd_rom_read(addr) << 24); /* byte lane at msb */ } static uae_u32 nd_rom_wget(uaecptr addr) { - addr &= ND_EEPROM_MASK; - addr |= 3; /* byte lane at msb */ - return (ND_rom[addr] << 8); + addr = nd_rom_addr_fix(addr); + + return (nd_rom_read(addr) << 8); /* byte lane at msb */ } static uae_u32 nd_rom_bget(uaecptr addr) { - addr &= ND_EEPROM_MASK; - addr |= 3; /* byte lane at msb */ - return ND_rom[addr]; + addr = nd_rom_addr_fix(addr); + + return nd_rom_read(addr); +} + +static void nd_rom_lput(uaecptr addr, uae_u32 l) +{ + addr = nd_rom_addr_fix(addr); + + nd_rom_write(addr, l >> 24); +} + +static void nd_rom_wput(uaecptr addr, uae_u32 w) +{ + addr = nd_rom_addr_fix(addr); + + nd_rom_write(addr, w >> 8); +} + +static void nd_rom_bput(uaecptr addr, uae_u32 b) +{ + addr = nd_rom_addr_fix(addr); + + nd_rom_write(addr, b); } static uae_u32 nd_rom_cs8get(uaecptr addr) @@ -357,25 +388,42 @@ static void nd_illegal_bput(uaecptr addr write_log("[ND] Illegal bput at %08X\n",addr); } +/* Unknown register access functions (memory controller step 1) */ +#if ND_STEP +static uae_u32 nd_unknown_lget(uaecptr addr) +{ + write_log("[ND] Unknown lget at %08X\n",addr); + return 0; +} +static uae_u32 nd_unknown_wget(uaecptr addr) +{ + write_log("[ND] Unknown wget at %08X\n",addr); + return 0; +} -/* NeXTdimension ROM access */ -static uae_u32 nd_rom_access_bget(uaecptr addr) +static uae_u32 nd_unknown_bget(uaecptr addr) { - addr &= ND_EEPROM2_MASK; - addr |= (addr>>17)&3; - addr &= ~(3<<17); - return nd_rom_read(addr); + write_log("[ND] Unknown bget at %08X\n",addr); + return 0; } -static void nd_rom_access_bput(uaecptr addr, uae_u32 b) +static void nd_unknown_lput(uaecptr addr, uae_u32 l) { - addr &= ND_EEPROM2_MASK; - addr |= (addr>>17)&3; - addr &= ~(3<<17); - nd_rom_write(addr, b); + write_log("[ND] Unknown lput at %08X: %08X\n",addr,l); } +static void nd_unknown_wput(uaecptr addr, uae_u32 w) +{ + write_log("[ND] Unknown wput at %08X: %04X\n",addr,w); +} + +static void nd_unknown_bput(uaecptr addr, uae_u32 b) +{ + write_log("[ND] Unknown bput at %08X: %02X\n",addr,b); +} +#endif + /* NeXTdimension dither memory & datapath */ static uae_u32 nd_dmem_lget(uaecptr addr) @@ -468,18 +516,11 @@ static nd_addrbank nd_vram_bank = static nd_addrbank nd_rom_bank = { nd_rom_lget, nd_rom_wget, nd_rom_bget, - nd_illegal_lput, nd_illegal_wput, nd_illegal_bput, + nd_rom_lput, nd_rom_wput, nd_rom_bput, nd_rom_cs8get }; -static nd_addrbank nd_rom_access_bank = -{ - nd_illegal_lget, nd_illegal_wget, nd_rom_access_bget, - nd_illegal_lput, nd_illegal_wput, nd_rom_access_bput, - nd_illegal_bget -}; - static nd_addrbank nd_dmem_bank = { nd_dmem_lget, nd_dmem_wget, nd_dmem_bget, @@ -496,8 +537,8 @@ static nd_addrbank nd_io_bank = static nd_addrbank nd_ramdac_bank = { - nd_ramdac_bget, nd_ramdac_bget, nd_ramdac_bget, - nd_ramdac_bput, nd_ramdac_bput, nd_ramdac_bput, + nd_ramdac_lget, nd_ramdac_wget, nd_ramdac_bget, + nd_ramdac_lput, nd_ramdac_wput, nd_ramdac_bput, nd_ramdac_bget }; @@ -508,6 +549,15 @@ static nd_addrbank nd_illegal_bank = nd_illegal_bget }; +#if ND_STEP +static nd_addrbank nd_unknown_bank = +{ + nd_unknown_lget, nd_unknown_wget, nd_unknown_bget, + nd_unknown_lput, nd_unknown_wput, nd_unknown_bput, + nd_unknown_bget +}; +#endif + static void nd_init_mem_banks (void) { int i; @@ -523,6 +573,9 @@ void nd_memory_init(void) { /* Initialize banks with error memory */ nd_init_mem_banks(); + /* Clear first 4k of memory for m68k ROM polling code */ + memset(ND_ram, 0, 4096 * sizeof(Uint8)); + /* Map main memory */ if (ConfigureParams.Dimension.nMemoryBankSize[0]) { ND_RAM_bankmask0 = ND_RAM_BANKMASK|((ConfigureParams.Dimension.nMemoryBankSize[0]<<20)-1); @@ -567,11 +620,9 @@ void nd_memory_init(void) { write_log("[ND] Mapping video memory at $%08x: %iMB\n", ND_VRAM_START, ND_VRAM_SIZE/(1024*1024)); nd_map_banks(&nd_vram_bank, ND_VRAM_START>>16, (4*ND_VRAM_SIZE)>>16); - ND_vram_off = 0; write_log("[ND] Mapping ROM at $%08x: %ikB\n", ND_EEPROM_START, ND_EEPROM_SIZE/1024); - nd_map_banks(&nd_rom_bank, ND_EEPROM_START>>16, ND_EEPROM_SIZE>>16); - nd_map_banks(&nd_rom_access_bank, ND_EEPROM2_STRT>>16, ND_EEPROM2_SIZE>>16); + nd_map_banks(&nd_rom_bank, ND_EEPROM_START>>16, (ND_EEPROM_SIZE*8)>>16); nd_rom_load(); write_log("[ND] Mapping dither memory and data path at $%08x: %ibyte\n", ND_DMEM_START, ND_DMEM_SIZE); @@ -582,6 +633,8 @@ void nd_memory_init(void) { write_log("[ND] Mapping RAMDAC registers at $%08x\n", ND_RAMDAC_START); nd_map_banks(&nd_ramdac_bank, ND_RAMDAC_START>>16, 1); -} - +#if ND_STEP + write_log("[ND] Mapping Unknown register at $%08x\n", ND_UNKNWN_START); + nd_map_banks(&nd_unknown_bank, ND_UNKNWN_START>>16, 1); #endif +}