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Annotation of previous/src/dimension/nd_mem.c, revision 1.1

1.1     ! root        1: #include "main.h"
        !             2: #include "configuration.h"
        !             3: #include "m68000.h"
        !             4: #include "sysdeps.h"
        !             5: #include "dimension.h"
        !             6: #include "nd_mem.h"
        !             7: #include "nd_devs.h"
        !             8: #include "nd_rom.h"
        !             9: 
        !            10: #if ENABLE_DIMENSION
        !            11: 
        !            12: #define write_log printf
        !            13: 
        !            14: /* --------- NEXTDIMENSION MEMORY ---------- */
        !            15: 
        !            16: /* NeXTdimension board memory */
        !            17: #define ND_RAM_START   0xF8000000
        !            18: #define ND_RAM_SIZE            0x04000000
        !            19: #define ND_RAM_MASK            0x03FFFFFF
        !            20: 
        !            21: #define ND_VRAM_START  0xFE000000
        !            22: #define ND_VRAM_SIZE   0x00400000
        !            23: #define ND_VRAM_MASK   0x003FFFFF
        !            24: 
        !            25: #define ND_EEPROM_START        0xFFFE0000
        !            26: #define ND_EEPROM_SIZE 0x00020000
        !            27: #define ND_EEPROM_MASK 0x0001FFFF
        !            28: 
        !            29: /* RAM banks */
        !            30: #define ND_RAM_BANKSIZE 0x01000000
        !            31: #define ND_RAM_BANKMASK 0x03000000
        !            32: uae_u32 ND_RAM_bankmask0;
        !            33: uae_u32 ND_RAM_bankmask1;
        !            34: uae_u32 ND_RAM_bankmask2;
        !            35: uae_u32 ND_RAM_bankmask3;
        !            36: 
        !            37: Uint8  ND_ram[64*1024*1024];
        !            38: Uint32 ND_vram_off;
        !            39: Uint8  ND_vram[4*1024*1024];
        !            40: Uint8  ND_rom[128*1024];
        !            41: 
        !            42: Uint8 ND_dmem[512];
        !            43: 
        !            44: /* NeXTdimension dither memory */
        !            45: #define ND_DMEM_START   0xFF000000
        !            46: #define ND_DMEM_SIZE    0x00000200
        !            47: #define ND_DMEM_MASK    0x000001FF
        !            48: 
        !            49: /* NeXTdimension board devices */
        !            50: #define ND_IO_START            0xFF800000
        !            51: #define ND_IO_SIZE             0x00004000
        !            52: #define ND_IO_MASK             0x00003FFF
        !            53: 
        !            54: /* NeXTdimension board RAMDAC */
        !            55: #define ND_RAMDAC_START        0xFF200000
        !            56: #define ND_RAMDAC_SIZE  0x00001000
        !            57: #define ND_RAMDAC_MASK  0x00000FFF
        !            58: 
        !            59: /* NeXTdimension board data path */
        !            60: #define ND_DP_START    0xF0000000
        !            61: #define ND_DP_SIZE  0x00001000
        !            62: #define ND_DP_MASK  0x00000FFF
        !            63: 
        !            64: /* NeXTdimension EEPROM access */
        !            65: #define ND_EEPROM2_STRT 0xFFF00000
        !            66: #define ND_EEPROM2_SIZE 0x00080000
        !            67: #define ND_EEPROM2_MASK 0x0007FFFC
        !            68: 
        !            69: /* Memory banks */
        !            70: 
        !            71: nd_addrbank *nd_mem_banks[65536];
        !            72: 
        !            73: void nd_map_banks (nd_addrbank *bank, int start, int size)
        !            74: {
        !            75:        int bnr;
        !            76:        
        !            77:        for (bnr = start; bnr < start + size; bnr++)
        !            78:                nd_put_mem_bank (bnr << 16, bank);
        !            79:        return;
        !            80: }
        !            81: 
        !            82: /* NeXTdimension RAM */
        !            83: static uae_u32 nd_ram_bank0_lget(uaecptr addr)
        !            84: {
        !            85:        addr &= ND_RAM_bankmask0;
        !            86:        return do_get_mem_long(ND_ram + addr);
        !            87: }
        !            88: 
        !            89: static uae_u32 nd_ram_bank0_wget(uaecptr addr)
        !            90: {
        !            91:        addr &= ND_RAM_bankmask0;
        !            92:        return do_get_mem_word(ND_ram + addr);
        !            93: }
        !            94: 
        !            95: static uae_u32 nd_ram_bank0_bget(uaecptr addr)
        !            96: {
        !            97:        addr &= ND_RAM_bankmask0;
        !            98:        return ND_ram[addr];
        !            99: }
        !           100: 
        !           101: static void nd_ram_bank0_lput(uaecptr addr, uae_u32 l)
        !           102: {
        !           103:        addr &= ND_RAM_bankmask0;
        !           104:        do_put_mem_long(ND_ram + addr, l);
        !           105: }
        !           106: 
        !           107: static void nd_ram_bank0_wput(uaecptr addr, uae_u32 w)
        !           108: {
        !           109:        addr &= ND_RAM_bankmask0;
        !           110:        do_put_mem_word(ND_ram + addr, w);
        !           111: }
        !           112: 
        !           113: static void nd_ram_bank0_bput(uaecptr addr, uae_u32 b)
        !           114: {
        !           115:        addr &= ND_RAM_bankmask0;
        !           116:        ND_ram[addr] = b;
        !           117: }
        !           118: 
        !           119: static uae_u32 nd_ram_bank1_lget(uaecptr addr)
        !           120: {
        !           121:     addr &= ND_RAM_bankmask1;
        !           122:     return do_get_mem_long(ND_ram + addr);
        !           123: }
        !           124: 
        !           125: static uae_u32 nd_ram_bank1_wget(uaecptr addr)
        !           126: {
        !           127:     addr &= ND_RAM_bankmask1;
        !           128:     return do_get_mem_word(ND_ram + addr);
        !           129: }
        !           130: 
        !           131: static uae_u32 nd_ram_bank1_bget(uaecptr addr)
        !           132: {
        !           133:     addr &= ND_RAM_bankmask1;
        !           134:     return ND_ram[addr];
        !           135: }
        !           136: 
        !           137: static void nd_ram_bank1_lput(uaecptr addr, uae_u32 l)
        !           138: {
        !           139:     addr &= ND_RAM_bankmask1;
        !           140:     do_put_mem_long(ND_ram + addr, l);
        !           141: }
        !           142: 
        !           143: static void nd_ram_bank1_wput(uaecptr addr, uae_u32 w)
        !           144: {
        !           145:     addr &= ND_RAM_bankmask1;
        !           146:     do_put_mem_word(ND_ram + addr, w);
        !           147: }
        !           148: 
        !           149: static void nd_ram_bank1_bput(uaecptr addr, uae_u32 b)
        !           150: {
        !           151:     addr &= ND_RAM_bankmask1;
        !           152:     ND_ram[addr] = b;
        !           153: }
        !           154: 
        !           155: static uae_u32 nd_ram_bank2_lget(uaecptr addr)
        !           156: {
        !           157:     addr &= ND_RAM_bankmask2;
        !           158:     return do_get_mem_long(ND_ram + addr);
        !           159: }
        !           160: 
        !           161: static uae_u32 nd_ram_bank2_wget(uaecptr addr)
        !           162: {
        !           163:     addr &= ND_RAM_bankmask2;
        !           164:     return do_get_mem_word(ND_ram + addr);
        !           165: }
        !           166: 
        !           167: static uae_u32 nd_ram_bank2_bget(uaecptr addr)
        !           168: {
        !           169:     addr &= ND_RAM_bankmask2;
        !           170:     return ND_ram[addr];
        !           171: }
        !           172: 
        !           173: static void nd_ram_bank2_lput(uaecptr addr, uae_u32 l)
        !           174: {
        !           175:     addr &= ND_RAM_bankmask2;
        !           176:     do_put_mem_long(ND_ram + addr, l);
        !           177: }
        !           178: 
        !           179: static void nd_ram_bank2_wput(uaecptr addr, uae_u32 w)
        !           180: {
        !           181:     addr &= ND_RAM_bankmask2;
        !           182:     do_put_mem_word(ND_ram + addr, w);
        !           183: }
        !           184: 
        !           185: static void nd_ram_bank2_bput(uaecptr addr, uae_u32 b)
        !           186: {
        !           187:     addr &= ND_RAM_bankmask2;
        !           188:     ND_ram[addr] = b;
        !           189: }
        !           190: 
        !           191: static uae_u32 nd_ram_bank3_lget(uaecptr addr)
        !           192: {
        !           193:     addr &= ND_RAM_bankmask3;
        !           194:     return do_get_mem_long(ND_ram + addr);
        !           195: }
        !           196: 
        !           197: static uae_u32 nd_ram_bank3_wget(uaecptr addr)
        !           198: {
        !           199:     addr &= ND_RAM_bankmask3;
        !           200:     return do_get_mem_word(ND_ram + addr);
        !           201: }
        !           202: 
        !           203: static uae_u32 nd_ram_bank3_bget(uaecptr addr)
        !           204: {
        !           205:     addr &= ND_RAM_bankmask3;
        !           206:     return ND_ram[addr];
        !           207: }
        !           208: 
        !           209: static void nd_ram_bank3_lput(uaecptr addr, uae_u32 l)
        !           210: {
        !           211:     addr &= ND_RAM_bankmask3;
        !           212:     do_put_mem_long(ND_ram + addr, l);
        !           213: }
        !           214: 
        !           215: static void nd_ram_bank3_wput(uaecptr addr, uae_u32 w)
        !           216: {
        !           217:     addr &= ND_RAM_bankmask3;
        !           218:     do_put_mem_word(ND_ram + addr, w);
        !           219: }
        !           220: 
        !           221: static void nd_ram_bank3_bput(uaecptr addr, uae_u32 b)
        !           222: {
        !           223:     addr &= ND_RAM_bankmask3;
        !           224:     ND_ram[addr] = b;
        !           225: }
        !           226: 
        !           227: static uae_u32 nd_ram_empty_lget(uaecptr addr)
        !           228: {
        !           229:     write_log("[ND] empty memory bank lget at %08X\n",addr);
        !           230:     return 0;
        !           231: }
        !           232: 
        !           233: static uae_u32 nd_ram_empty_wget(uaecptr addr)
        !           234: {
        !           235:     write_log("[ND] empty memory bank wget at %08X\n",addr);
        !           236:     return 0;
        !           237: }
        !           238: 
        !           239: static uae_u32 nd_ram_empty_bget(uaecptr addr)
        !           240: {
        !           241:     write_log("[ND] empty memory bank bget at %08X\n",addr);
        !           242:     return 0;
        !           243: }
        !           244: 
        !           245: static void nd_ram_empty_lput(uaecptr addr, uae_u32 l)
        !           246: {
        !           247:     write_log("[ND] empty memory bank lput at %08X\n",addr);
        !           248: }
        !           249: 
        !           250: static void nd_ram_empty_wput(uaecptr addr, uae_u32 w)
        !           251: {
        !           252:     write_log("[ND] empty memory bank wput at %08X\n",addr);
        !           253: }
        !           254: 
        !           255: static void nd_ram_empty_bput(uaecptr addr, uae_u32 b)
        !           256: {
        !           257:     write_log("[ND] empty memory bank bput at %08X\n",addr);
        !           258: }
        !           259: 
        !           260: /* NeXTdimension VRAM */
        !           261: static uae_u32 nd_vram_lget(uaecptr addr)
        !           262: {
        !           263:     addr &= ND_VRAM_MASK;
        !           264:     return do_get_mem_long(ND_vram + addr);
        !           265: }
        !           266: 
        !           267: static uae_u32 nd_vram_wget(uaecptr addr)
        !           268: {
        !           269:     addr &= ND_VRAM_MASK;
        !           270:     return do_get_mem_word(ND_vram + addr);
        !           271: }
        !           272: 
        !           273: static uae_u32 nd_vram_bget(uaecptr addr)
        !           274: {
        !           275:     addr &= ND_VRAM_MASK;
        !           276:     return ND_vram[addr];
        !           277: }
        !           278: 
        !           279: static void nd_vram_lput(uaecptr addr, uae_u32 l)
        !           280: {
        !           281:     addr &= ND_VRAM_MASK;
        !           282:     do_put_mem_long(ND_vram + addr, l);
        !           283: }
        !           284: 
        !           285: static void nd_vram_wput(uaecptr addr, uae_u32 w)
        !           286: {
        !           287:     addr &= ND_VRAM_MASK;
        !           288:     do_put_mem_word(ND_vram + addr, w);
        !           289: }
        !           290: 
        !           291: static void nd_vram_bput(uaecptr addr, uae_u32 b)
        !           292: {
        !           293:     addr &= ND_VRAM_MASK;
        !           294:     ND_vram[addr] = b;
        !           295: }
        !           296: 
        !           297: /* NeXTdimension ROM */
        !           298: static uae_u32 nd_rom_lget(uaecptr addr)
        !           299: {
        !           300:        addr &= ND_EEPROM_MASK;
        !           301:     addr |= 3; /* byte lane at msb */
        !           302:        return (ND_rom[addr] << 24);
        !           303: }
        !           304: 
        !           305: static uae_u32 nd_rom_wget(uaecptr addr)
        !           306: {
        !           307:        addr &= ND_EEPROM_MASK;
        !           308:     addr |= 3; /* byte lane at msb */
        !           309:        return (ND_rom[addr] << 8);
        !           310: }
        !           311: 
        !           312: static uae_u32 nd_rom_bget(uaecptr addr)
        !           313: {
        !           314:        addr &= ND_EEPROM_MASK;
        !           315:     addr |= 3; /* byte lane at msb */
        !           316:        return ND_rom[addr];
        !           317: }
        !           318: 
        !           319: static uae_u32 nd_rom_cs8get(uaecptr addr)
        !           320: {
        !           321:     addr &= ND_EEPROM_MASK;
        !           322:     return ND_rom[addr];
        !           323: }
        !           324: 
        !           325: /* Illegal access functions */
        !           326: 
        !           327: static uae_u32 nd_illegal_lget(uaecptr addr)
        !           328: {
        !           329:     write_log("[ND] Illegal lget at %08X\n",addr);
        !           330:     return 0;
        !           331: }
        !           332: 
        !           333: static uae_u32 nd_illegal_wget(uaecptr addr)
        !           334: {
        !           335:     write_log("[ND] Illegal wget at %08X\n",addr);
        !           336:     return 0;
        !           337: }
        !           338: 
        !           339: static uae_u32 nd_illegal_bget(uaecptr addr)
        !           340: {
        !           341:     write_log("[ND] Illegal bget at %08X\n",addr);
        !           342:     return 0;
        !           343: }
        !           344: 
        !           345: static void nd_illegal_lput(uaecptr addr, uae_u32 l)
        !           346: {
        !           347:     write_log("[ND] Illegal lput at %08X\n",addr);
        !           348: }
        !           349: 
        !           350: static void nd_illegal_wput(uaecptr addr, uae_u32 w)
        !           351: {
        !           352:     write_log("[ND] Illegal wput at %08X\n",addr);
        !           353: }
        !           354: 
        !           355: static void nd_illegal_bput(uaecptr addr, uae_u32 b)
        !           356: {
        !           357:     write_log("[ND] Illegal bput at %08X\n",addr);
        !           358: }
        !           359: 
        !           360: 
        !           361: 
        !           362: /* NeXTdimension ROM access */
        !           363: static uae_u32 nd_rom_access_bget(uaecptr addr)
        !           364: {
        !           365:     addr &= ND_EEPROM2_MASK;
        !           366:     addr |= (addr>>17)&3;
        !           367:     addr &= ~(3<<17);
        !           368:     return nd_rom_read(addr);
        !           369: }
        !           370: 
        !           371: static void nd_rom_access_bput(uaecptr addr, uae_u32 b)
        !           372: {
        !           373:     addr &= ND_EEPROM2_MASK;
        !           374:     addr |= (addr>>17)&3;
        !           375:     addr &= ~(3<<17);
        !           376:     nd_rom_write(addr, b);
        !           377: }
        !           378: 
        !           379: /* NeXTdimension dither memory & datapath */
        !           380: 
        !           381: static uae_u32 nd_dmem_lget(uaecptr addr)
        !           382: {
        !           383:     addr &= ND_DP_MASK;
        !           384:     return addr < ND_DMEM_SIZE ? do_get_mem_long(ND_dmem + addr) : nd_dp_lget(addr);
        !           385: }
        !           386: 
        !           387: static uae_u32 nd_dmem_wget(uaecptr addr)
        !           388: {
        !           389:     addr &= ND_DP_MASK;
        !           390:     return addr < ND_DMEM_SIZE ? do_get_mem_word(ND_dmem + addr) : nd_dp_lget(addr);
        !           391: }
        !           392: 
        !           393: static uae_u32 nd_dmem_bget(uaecptr addr)
        !           394: {
        !           395:     addr &= ND_DP_MASK;
        !           396:     return addr < ND_DMEM_SIZE ? do_get_mem_byte(ND_dmem + addr) : nd_dp_lget(addr);
        !           397: }
        !           398: 
        !           399: static void nd_dmem_lput(uaecptr addr, uae_u32 l)
        !           400: {
        !           401:     addr &= ND_DP_MASK;
        !           402:     if(addr < ND_DMEM_SIZE)
        !           403:         do_put_mem_long(ND_dmem + addr, l);
        !           404:     else
        !           405:         nd_dp_lput(addr, l);
        !           406: }
        !           407: 
        !           408: static void nd_dmem_wput(uaecptr addr, uae_u32 w)
        !           409: {
        !           410:     addr &= ND_DP_MASK;
        !           411:     if(addr < ND_DMEM_SIZE)
        !           412:         do_put_mem_word(ND_dmem + addr, w);
        !           413:     else
        !           414:         nd_dp_lput(addr, w);
        !           415: }
        !           416: 
        !           417: static void nd_dmem_bput(uaecptr addr, uae_u32 b)
        !           418: {
        !           419:     addr &= ND_DP_MASK;
        !           420:     if(addr < ND_DMEM_SIZE)
        !           421:         do_put_mem_byte(ND_dmem + addr, b);
        !           422:     else
        !           423:         nd_dp_lput(addr, b);
        !           424: }
        !           425: 
        !           426: static nd_addrbank nd_ram_bank0 =
        !           427: {
        !           428:        nd_ram_bank0_lget, nd_ram_bank0_wget, nd_ram_bank0_bget,
        !           429:        nd_ram_bank0_lput, nd_ram_bank0_wput, nd_ram_bank0_bput,
        !           430:        nd_ram_bank0_bget
        !           431: };
        !           432: 
        !           433: static nd_addrbank nd_ram_bank1 =
        !           434: {
        !           435:     nd_ram_bank1_lget, nd_ram_bank1_wget, nd_ram_bank1_bget,
        !           436:     nd_ram_bank1_lput, nd_ram_bank1_wput, nd_ram_bank1_bput,
        !           437:     nd_ram_bank1_bget
        !           438: };
        !           439: 
        !           440: static nd_addrbank nd_ram_bank2 =
        !           441: {
        !           442:     nd_ram_bank2_lget, nd_ram_bank2_wget, nd_ram_bank2_bget,
        !           443:     nd_ram_bank2_lput, nd_ram_bank2_wput, nd_ram_bank2_bput,
        !           444:     nd_ram_bank2_bget
        !           445: };
        !           446: 
        !           447: static nd_addrbank nd_ram_bank3 =
        !           448: {
        !           449:     nd_ram_bank3_lget, nd_ram_bank3_wget, nd_ram_bank3_bget,
        !           450:     nd_ram_bank3_lput, nd_ram_bank3_wput, nd_ram_bank3_bput,
        !           451:     nd_ram_bank3_bget
        !           452: };
        !           453: 
        !           454: static nd_addrbank nd_ram_empty =
        !           455: {
        !           456:     nd_ram_empty_lget, nd_ram_empty_wget, nd_ram_empty_bget,
        !           457:     nd_ram_empty_lput, nd_ram_empty_wput, nd_ram_empty_bput,
        !           458:     nd_ram_empty_bget
        !           459: };
        !           460: 
        !           461: static nd_addrbank nd_vram_bank =
        !           462: {
        !           463:     nd_vram_lget, nd_vram_wget, nd_vram_bget,
        !           464:     nd_vram_lput, nd_vram_wput, nd_vram_bput,
        !           465:     nd_vram_bget
        !           466: };
        !           467: 
        !           468: static nd_addrbank nd_rom_bank =
        !           469: {
        !           470:        nd_rom_lget, nd_rom_wget, nd_rom_bget,
        !           471:     nd_illegal_lput, nd_illegal_wput, nd_illegal_bput,
        !           472:     nd_rom_cs8get
        !           473: 
        !           474: };
        !           475: 
        !           476: static nd_addrbank nd_rom_access_bank =
        !           477: {
        !           478:     nd_illegal_lget, nd_illegal_wget, nd_rom_access_bget,
        !           479:     nd_illegal_lput, nd_illegal_wput, nd_rom_access_bput,
        !           480:     nd_illegal_bget
        !           481: };
        !           482: 
        !           483: static nd_addrbank nd_dmem_bank =
        !           484: {
        !           485:     nd_dmem_lget, nd_dmem_wget, nd_dmem_bget,
        !           486:     nd_dmem_lput, nd_dmem_wput, nd_dmem_bput,
        !           487:     nd_dmem_bget
        !           488: };
        !           489: 
        !           490: static nd_addrbank nd_io_bank =
        !           491: {
        !           492:        nd_io_lget, nd_io_wget, nd_io_bget,
        !           493:        nd_io_lput, nd_io_wput, nd_io_bput,
        !           494:        nd_io_bget
        !           495: };
        !           496: 
        !           497: static nd_addrbank nd_ramdac_bank =
        !           498: {
        !           499:     nd_ramdac_bget, nd_ramdac_bget, nd_ramdac_bget,
        !           500:     nd_ramdac_bput, nd_ramdac_bput, nd_ramdac_bput,
        !           501:     nd_ramdac_bget
        !           502: };
        !           503: 
        !           504: static nd_addrbank nd_illegal_bank =
        !           505: {
        !           506:     nd_illegal_lget, nd_illegal_wget, nd_illegal_bget,
        !           507:     nd_illegal_lput, nd_illegal_wput, nd_illegal_bput,
        !           508:     nd_illegal_bget
        !           509: };
        !           510: 
        !           511: static void nd_init_mem_banks (void)
        !           512: {
        !           513:     int i;
        !           514:     for (i = 0; i < 65536; i++)
        !           515:         nd_put_mem_bank (i<<16, &nd_illegal_bank);
        !           516: }
        !           517: 
        !           518: void nd_memory_init(void) {
        !           519:        
        !           520:        write_log("[ND] Memory init: Memory size: %iMB\n",
        !           521:               Configuration_CheckDimensionMemory(ConfigureParams.Dimension.nMemoryBankSize));
        !           522: 
        !           523:     /* Initialize banks with error memory */
        !           524:     nd_init_mem_banks();
        !           525:     
        !           526:     /* Map main memory */
        !           527:     if (ConfigureParams.Dimension.nMemoryBankSize[0]) {
        !           528:         ND_RAM_bankmask0 = ND_RAM_BANKMASK|((ConfigureParams.Dimension.nMemoryBankSize[0]<<20)-1);
        !           529:         nd_map_banks(&nd_ram_bank0, (ND_RAM_START+(0*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
        !           530:         write_log("[ND] Mapping main memory bank0 at $%08x: %iMB\n",
        !           531:                   (ND_RAM_START+(0*ND_RAM_BANKSIZE)), ConfigureParams.Dimension.nMemoryBankSize[0]);
        !           532:     } else {
        !           533:         ND_RAM_bankmask0 = 0;
        !           534:         nd_map_banks(&nd_ram_empty, (ND_RAM_START+(0*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
        !           535:         write_log("[ND] Mapping main memory bank0 at $%08x: empty\n", (ND_RAM_START+(0*ND_RAM_BANKSIZE)));
        !           536:     }
        !           537:     if (ConfigureParams.Dimension.nMemoryBankSize[1]) {
        !           538:         ND_RAM_bankmask1 = ND_RAM_BANKMASK|((ConfigureParams.Dimension.nMemoryBankSize[1]<<20)-1);
        !           539:         nd_map_banks(&nd_ram_bank1, (ND_RAM_START+(1*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
        !           540:         write_log("[ND] Mapping main memory bank1 at $%08x: %iMB\n",
        !           541:                   (ND_RAM_START+(1*ND_RAM_BANKSIZE)), ConfigureParams.Dimension.nMemoryBankSize[1]);
        !           542:     } else {
        !           543:         ND_RAM_bankmask1 = 0;
        !           544:         nd_map_banks(&nd_ram_empty, (ND_RAM_START+(1*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
        !           545:         write_log("[ND] Mapping main memory bank1 at $%08x: empty\n", (ND_RAM_START+(1*ND_RAM_BANKSIZE)));
        !           546:     }
        !           547:     if (ConfigureParams.Dimension.nMemoryBankSize[2]) {
        !           548:         ND_RAM_bankmask2 = ND_RAM_BANKMASK|((ConfigureParams.Dimension.nMemoryBankSize[2]<<20)-1);
        !           549:         nd_map_banks(&nd_ram_bank2, (ND_RAM_START+(2*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
        !           550:         write_log("[ND] Mapping main memory bank2 at $%08x: %iMB\n",
        !           551:                   (ND_RAM_START+(2*ND_RAM_BANKSIZE)), ConfigureParams.Dimension.nMemoryBankSize[2]);
        !           552:     } else {
        !           553:         ND_RAM_bankmask2 = 0;
        !           554:         nd_map_banks(&nd_ram_empty, (ND_RAM_START+(2*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
        !           555:         write_log("[ND] Mapping main memory bank2 at $%08x: empty\n", (ND_RAM_START+(2*ND_RAM_BANKSIZE)));
        !           556:     }
        !           557:     if (ConfigureParams.Dimension.nMemoryBankSize[3]) {
        !           558:         ND_RAM_bankmask3 = ND_RAM_BANKMASK|((ConfigureParams.Dimension.nMemoryBankSize[3]<<20)-1);
        !           559:         nd_map_banks(&nd_ram_bank3, (ND_RAM_START+(3*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
        !           560:         write_log("[ND] Mapping main memory bank3 at $%08x: %iMB\n",
        !           561:                   (ND_RAM_START+(3*ND_RAM_BANKSIZE)), ConfigureParams.Dimension.nMemoryBankSize[3]);
        !           562:     } else {
        !           563:         ND_RAM_bankmask3 = 0;
        !           564:         nd_map_banks(&nd_ram_empty, (ND_RAM_START+(3*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
        !           565:         write_log("[ND] Mapping main memory bank3 at $%08x: empty\n", (ND_RAM_START+(3*ND_RAM_BANKSIZE)));
        !           566:     }
        !           567:     
        !           568:     write_log("[ND] Mapping video memory at $%08x: %iMB\n", ND_VRAM_START, ND_VRAM_SIZE/(1024*1024));
        !           569:     nd_map_banks(&nd_vram_bank, ND_VRAM_START>>16, (4*ND_VRAM_SIZE)>>16);
        !           570:     ND_vram_off = 0;
        !           571:     
        !           572:        write_log("[ND] Mapping ROM at $%08x: %ikB\n", ND_EEPROM_START, ND_EEPROM_SIZE/1024);
        !           573:        nd_map_banks(&nd_rom_bank, ND_EEPROM_START>>16, ND_EEPROM_SIZE>>16);
        !           574:     nd_map_banks(&nd_rom_access_bank, ND_EEPROM2_STRT>>16, ND_EEPROM2_SIZE>>16);
        !           575:     nd_rom_load();
        !           576:        
        !           577:     write_log("[ND] Mapping dither memory and data path at $%08x: %ibyte\n", ND_DMEM_START, ND_DMEM_SIZE);
        !           578:     nd_map_banks(&nd_dmem_bank, ND_DMEM_START>>16, 1);
        !           579: 
        !           580:        write_log("[ND] Mapping IO memory at $%08x\n", ND_IO_START);
        !           581:        nd_map_banks(&nd_io_bank, ND_IO_START>>16, 1);
        !           582:     
        !           583:     write_log("[ND] Mapping RAMDAC registers at $%08x\n", ND_RAMDAC_START);
        !           584:     nd_map_banks(&nd_ramdac_bank, ND_RAMDAC_START>>16, 1);
        !           585: }
        !           586: 
        !           587: #endif

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