![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to nd_mem.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Previous NeXT emulator] / previous / src / dimension|
Return to nd_mem.c CVS log | Up to [Previous NeXT emulator] / previous / src / dimension |
1.1 root 1: #include "main.h"
2: #include "configuration.h"
3: #include "m68000.h"
4: #include "sysdeps.h"
5: #include "dimension.h"
6: #include "nd_mem.h"
7: #include "nd_devs.h"
8: #include "nd_rom.h"
9:
10: #define write_log printf
11:
12: /* --------- NEXTDIMENSION MEMORY ---------- */
13:
14: /* NeXTdimension board memory */
15: #define ND_RAM_START 0xF8000000
16: #define ND_RAM_SIZE 0x04000000
17: #define ND_RAM_MASK 0x03FFFFFF
18:
19: #define ND_VRAM_START 0xFE000000
20: #define ND_VRAM_SIZE 0x00400000
21: #define ND_VRAM_MASK 0x003FFFFF
22:
1.1.1.2 ! root 23: #define ND_EEPROM_START 0xFFF00000
1.1 root 24: #define ND_EEPROM_SIZE 0x00020000
25: #define ND_EEPROM_MASK 0x0001FFFF
26:
27: /* RAM banks */
28: #define ND_RAM_BANKSIZE 0x01000000
29: #define ND_RAM_BANKMASK 0x03000000
30: uae_u32 ND_RAM_bankmask0;
31: uae_u32 ND_RAM_bankmask1;
32: uae_u32 ND_RAM_bankmask2;
33: uae_u32 ND_RAM_bankmask3;
34:
35: Uint8 ND_ram[64*1024*1024];
36: Uint8 ND_vram[4*1024*1024];
37: Uint8 ND_rom[128*1024];
38:
39: Uint8 ND_dmem[512];
40:
41: /* NeXTdimension dither memory */
42: #define ND_DMEM_START 0xFF000000
43: #define ND_DMEM_SIZE 0x00000200
44: #define ND_DMEM_MASK 0x000001FF
45:
46: /* NeXTdimension board devices */
47: #define ND_IO_START 0xFF800000
48: #define ND_IO_SIZE 0x00004000
49: #define ND_IO_MASK 0x00003FFF
50:
51: /* NeXTdimension board RAMDAC */
52: #define ND_RAMDAC_START 0xFF200000
53: #define ND_RAMDAC_SIZE 0x00001000
54: #define ND_RAMDAC_MASK 0x00000FFF
55:
56: /* NeXTdimension board data path */
57: #define ND_DP_START 0xF0000000
58: #define ND_DP_SIZE 0x00001000
59: #define ND_DP_MASK 0x00000FFF
60:
1.1.1.2 ! root 61: /* NeXTdimension unknown registers */
! 62: #define ND_UNKNWN_START 0xFF400000
! 63: #define ND_UNKNWN_SIZE 0x00000200
! 64: #define ND_UNKNWN_MASK 0x000001FF
! 65:
! 66: /* Function to fix address for ROM access */
! 67: static uaecptr nd_rom_addr_fix(uaecptr addr)
! 68: {
! 69: #if ND_STEP
! 70: addr >>= 2;
! 71: #else
! 72: addr &= ~3;
! 73: addr |= (addr>>17)&3;
! 74: #endif
! 75: addr &= ND_EEPROM_MASK;
! 76: return addr;
! 77: }
1.1 root 78:
79: /* Memory banks */
80:
81: nd_addrbank *nd_mem_banks[65536];
82:
1.1.1.2 ! root 83: static void nd_map_banks (nd_addrbank *bank, int start, int size)
1.1 root 84: {
85: int bnr;
86:
87: for (bnr = start; bnr < start + size; bnr++)
88: nd_put_mem_bank (bnr << 16, bank);
89: return;
90: }
91:
92: /* NeXTdimension RAM */
93: static uae_u32 nd_ram_bank0_lget(uaecptr addr)
94: {
95: addr &= ND_RAM_bankmask0;
96: return do_get_mem_long(ND_ram + addr);
97: }
98:
99: static uae_u32 nd_ram_bank0_wget(uaecptr addr)
100: {
101: addr &= ND_RAM_bankmask0;
102: return do_get_mem_word(ND_ram + addr);
103: }
104:
105: static uae_u32 nd_ram_bank0_bget(uaecptr addr)
106: {
107: addr &= ND_RAM_bankmask0;
108: return ND_ram[addr];
109: }
110:
111: static void nd_ram_bank0_lput(uaecptr addr, uae_u32 l)
112: {
113: addr &= ND_RAM_bankmask0;
114: do_put_mem_long(ND_ram + addr, l);
115: }
116:
117: static void nd_ram_bank0_wput(uaecptr addr, uae_u32 w)
118: {
119: addr &= ND_RAM_bankmask0;
120: do_put_mem_word(ND_ram + addr, w);
121: }
122:
123: static void nd_ram_bank0_bput(uaecptr addr, uae_u32 b)
124: {
125: addr &= ND_RAM_bankmask0;
126: ND_ram[addr] = b;
127: }
128:
129: static uae_u32 nd_ram_bank1_lget(uaecptr addr)
130: {
131: addr &= ND_RAM_bankmask1;
132: return do_get_mem_long(ND_ram + addr);
133: }
134:
135: static uae_u32 nd_ram_bank1_wget(uaecptr addr)
136: {
137: addr &= ND_RAM_bankmask1;
138: return do_get_mem_word(ND_ram + addr);
139: }
140:
141: static uae_u32 nd_ram_bank1_bget(uaecptr addr)
142: {
143: addr &= ND_RAM_bankmask1;
144: return ND_ram[addr];
145: }
146:
147: static void nd_ram_bank1_lput(uaecptr addr, uae_u32 l)
148: {
149: addr &= ND_RAM_bankmask1;
150: do_put_mem_long(ND_ram + addr, l);
151: }
152:
153: static void nd_ram_bank1_wput(uaecptr addr, uae_u32 w)
154: {
155: addr &= ND_RAM_bankmask1;
156: do_put_mem_word(ND_ram + addr, w);
157: }
158:
159: static void nd_ram_bank1_bput(uaecptr addr, uae_u32 b)
160: {
161: addr &= ND_RAM_bankmask1;
162: ND_ram[addr] = b;
163: }
164:
165: static uae_u32 nd_ram_bank2_lget(uaecptr addr)
166: {
167: addr &= ND_RAM_bankmask2;
168: return do_get_mem_long(ND_ram + addr);
169: }
170:
171: static uae_u32 nd_ram_bank2_wget(uaecptr addr)
172: {
173: addr &= ND_RAM_bankmask2;
174: return do_get_mem_word(ND_ram + addr);
175: }
176:
177: static uae_u32 nd_ram_bank2_bget(uaecptr addr)
178: {
179: addr &= ND_RAM_bankmask2;
180: return ND_ram[addr];
181: }
182:
183: static void nd_ram_bank2_lput(uaecptr addr, uae_u32 l)
184: {
185: addr &= ND_RAM_bankmask2;
186: do_put_mem_long(ND_ram + addr, l);
187: }
188:
189: static void nd_ram_bank2_wput(uaecptr addr, uae_u32 w)
190: {
191: addr &= ND_RAM_bankmask2;
192: do_put_mem_word(ND_ram + addr, w);
193: }
194:
195: static void nd_ram_bank2_bput(uaecptr addr, uae_u32 b)
196: {
197: addr &= ND_RAM_bankmask2;
198: ND_ram[addr] = b;
199: }
200:
201: static uae_u32 nd_ram_bank3_lget(uaecptr addr)
202: {
203: addr &= ND_RAM_bankmask3;
204: return do_get_mem_long(ND_ram + addr);
205: }
206:
207: static uae_u32 nd_ram_bank3_wget(uaecptr addr)
208: {
209: addr &= ND_RAM_bankmask3;
210: return do_get_mem_word(ND_ram + addr);
211: }
212:
213: static uae_u32 nd_ram_bank3_bget(uaecptr addr)
214: {
215: addr &= ND_RAM_bankmask3;
216: return ND_ram[addr];
217: }
218:
219: static void nd_ram_bank3_lput(uaecptr addr, uae_u32 l)
220: {
221: addr &= ND_RAM_bankmask3;
222: do_put_mem_long(ND_ram + addr, l);
223: }
224:
225: static void nd_ram_bank3_wput(uaecptr addr, uae_u32 w)
226: {
227: addr &= ND_RAM_bankmask3;
228: do_put_mem_word(ND_ram + addr, w);
229: }
230:
231: static void nd_ram_bank3_bput(uaecptr addr, uae_u32 b)
232: {
233: addr &= ND_RAM_bankmask3;
234: ND_ram[addr] = b;
235: }
236:
237: static uae_u32 nd_ram_empty_lget(uaecptr addr)
238: {
239: write_log("[ND] empty memory bank lget at %08X\n",addr);
240: return 0;
241: }
242:
243: static uae_u32 nd_ram_empty_wget(uaecptr addr)
244: {
245: write_log("[ND] empty memory bank wget at %08X\n",addr);
246: return 0;
247: }
248:
249: static uae_u32 nd_ram_empty_bget(uaecptr addr)
250: {
251: write_log("[ND] empty memory bank bget at %08X\n",addr);
252: return 0;
253: }
254:
255: static void nd_ram_empty_lput(uaecptr addr, uae_u32 l)
256: {
257: write_log("[ND] empty memory bank lput at %08X\n",addr);
258: }
259:
260: static void nd_ram_empty_wput(uaecptr addr, uae_u32 w)
261: {
262: write_log("[ND] empty memory bank wput at %08X\n",addr);
263: }
264:
265: static void nd_ram_empty_bput(uaecptr addr, uae_u32 b)
266: {
267: write_log("[ND] empty memory bank bput at %08X\n",addr);
268: }
269:
270: /* NeXTdimension VRAM */
271: static uae_u32 nd_vram_lget(uaecptr addr)
272: {
273: addr &= ND_VRAM_MASK;
274: return do_get_mem_long(ND_vram + addr);
275: }
276:
277: static uae_u32 nd_vram_wget(uaecptr addr)
278: {
279: addr &= ND_VRAM_MASK;
280: return do_get_mem_word(ND_vram + addr);
281: }
282:
283: static uae_u32 nd_vram_bget(uaecptr addr)
284: {
285: addr &= ND_VRAM_MASK;
286: return ND_vram[addr];
287: }
288:
289: static void nd_vram_lput(uaecptr addr, uae_u32 l)
290: {
291: addr &= ND_VRAM_MASK;
292: do_put_mem_long(ND_vram + addr, l);
293: }
294:
295: static void nd_vram_wput(uaecptr addr, uae_u32 w)
296: {
297: addr &= ND_VRAM_MASK;
298: do_put_mem_word(ND_vram + addr, w);
299: }
300:
301: static void nd_vram_bput(uaecptr addr, uae_u32 b)
302: {
303: addr &= ND_VRAM_MASK;
304: ND_vram[addr] = b;
305: }
306:
307: /* NeXTdimension ROM */
308: static uae_u32 nd_rom_lget(uaecptr addr)
309: {
1.1.1.2 ! root 310: addr = nd_rom_addr_fix(addr);
! 311:
! 312: return (nd_rom_read(addr) << 24); /* byte lane at msb */
1.1 root 313: }
314:
315: static uae_u32 nd_rom_wget(uaecptr addr)
316: {
1.1.1.2 ! root 317: addr = nd_rom_addr_fix(addr);
! 318:
! 319: return (nd_rom_read(addr) << 8); /* byte lane at msb */
1.1 root 320: }
321:
322: static uae_u32 nd_rom_bget(uaecptr addr)
323: {
1.1.1.2 ! root 324: addr = nd_rom_addr_fix(addr);
! 325:
! 326: return nd_rom_read(addr);
! 327: }
! 328:
! 329: static void nd_rom_lput(uaecptr addr, uae_u32 l)
! 330: {
! 331: addr = nd_rom_addr_fix(addr);
! 332:
! 333: nd_rom_write(addr, l >> 24);
! 334: }
! 335:
! 336: static void nd_rom_wput(uaecptr addr, uae_u32 w)
! 337: {
! 338: addr = nd_rom_addr_fix(addr);
! 339:
! 340: nd_rom_write(addr, w >> 8);
! 341: }
! 342:
! 343: static void nd_rom_bput(uaecptr addr, uae_u32 b)
! 344: {
! 345: addr = nd_rom_addr_fix(addr);
! 346:
! 347: nd_rom_write(addr, b);
1.1 root 348: }
349:
350: static uae_u32 nd_rom_cs8get(uaecptr addr)
351: {
352: addr &= ND_EEPROM_MASK;
353: return ND_rom[addr];
354: }
355:
356: /* Illegal access functions */
357:
358: static uae_u32 nd_illegal_lget(uaecptr addr)
359: {
360: write_log("[ND] Illegal lget at %08X\n",addr);
361: return 0;
362: }
363:
364: static uae_u32 nd_illegal_wget(uaecptr addr)
365: {
366: write_log("[ND] Illegal wget at %08X\n",addr);
367: return 0;
368: }
369:
370: static uae_u32 nd_illegal_bget(uaecptr addr)
371: {
372: write_log("[ND] Illegal bget at %08X\n",addr);
373: return 0;
374: }
375:
376: static void nd_illegal_lput(uaecptr addr, uae_u32 l)
377: {
378: write_log("[ND] Illegal lput at %08X\n",addr);
379: }
380:
381: static void nd_illegal_wput(uaecptr addr, uae_u32 w)
382: {
383: write_log("[ND] Illegal wput at %08X\n",addr);
384: }
385:
386: static void nd_illegal_bput(uaecptr addr, uae_u32 b)
387: {
388: write_log("[ND] Illegal bput at %08X\n",addr);
389: }
390:
1.1.1.2 ! root 391: /* Unknown register access functions (memory controller step 1) */
! 392: #if ND_STEP
! 393: static uae_u32 nd_unknown_lget(uaecptr addr)
! 394: {
! 395: write_log("[ND] Unknown lget at %08X\n",addr);
! 396: return 0;
! 397: }
1.1 root 398:
1.1.1.2 ! root 399: static uae_u32 nd_unknown_wget(uaecptr addr)
! 400: {
! 401: write_log("[ND] Unknown wget at %08X\n",addr);
! 402: return 0;
! 403: }
1.1 root 404:
1.1.1.2 ! root 405: static uae_u32 nd_unknown_bget(uaecptr addr)
1.1 root 406: {
1.1.1.2 ! root 407: write_log("[ND] Unknown bget at %08X\n",addr);
! 408: return 0;
1.1 root 409: }
410:
1.1.1.2 ! root 411: static void nd_unknown_lput(uaecptr addr, uae_u32 l)
1.1 root 412: {
1.1.1.2 ! root 413: write_log("[ND] Unknown lput at %08X: %08X\n",addr,l);
1.1 root 414: }
415:
1.1.1.2 ! root 416: static void nd_unknown_wput(uaecptr addr, uae_u32 w)
! 417: {
! 418: write_log("[ND] Unknown wput at %08X: %04X\n",addr,w);
! 419: }
! 420:
! 421: static void nd_unknown_bput(uaecptr addr, uae_u32 b)
! 422: {
! 423: write_log("[ND] Unknown bput at %08X: %02X\n",addr,b);
! 424: }
! 425: #endif
! 426:
1.1 root 427: /* NeXTdimension dither memory & datapath */
428:
429: static uae_u32 nd_dmem_lget(uaecptr addr)
430: {
431: addr &= ND_DP_MASK;
432: return addr < ND_DMEM_SIZE ? do_get_mem_long(ND_dmem + addr) : nd_dp_lget(addr);
433: }
434:
435: static uae_u32 nd_dmem_wget(uaecptr addr)
436: {
437: addr &= ND_DP_MASK;
438: return addr < ND_DMEM_SIZE ? do_get_mem_word(ND_dmem + addr) : nd_dp_lget(addr);
439: }
440:
441: static uae_u32 nd_dmem_bget(uaecptr addr)
442: {
443: addr &= ND_DP_MASK;
444: return addr < ND_DMEM_SIZE ? do_get_mem_byte(ND_dmem + addr) : nd_dp_lget(addr);
445: }
446:
447: static void nd_dmem_lput(uaecptr addr, uae_u32 l)
448: {
449: addr &= ND_DP_MASK;
450: if(addr < ND_DMEM_SIZE)
451: do_put_mem_long(ND_dmem + addr, l);
452: else
453: nd_dp_lput(addr, l);
454: }
455:
456: static void nd_dmem_wput(uaecptr addr, uae_u32 w)
457: {
458: addr &= ND_DP_MASK;
459: if(addr < ND_DMEM_SIZE)
460: do_put_mem_word(ND_dmem + addr, w);
461: else
462: nd_dp_lput(addr, w);
463: }
464:
465: static void nd_dmem_bput(uaecptr addr, uae_u32 b)
466: {
467: addr &= ND_DP_MASK;
468: if(addr < ND_DMEM_SIZE)
469: do_put_mem_byte(ND_dmem + addr, b);
470: else
471: nd_dp_lput(addr, b);
472: }
473:
474: static nd_addrbank nd_ram_bank0 =
475: {
476: nd_ram_bank0_lget, nd_ram_bank0_wget, nd_ram_bank0_bget,
477: nd_ram_bank0_lput, nd_ram_bank0_wput, nd_ram_bank0_bput,
478: nd_ram_bank0_bget
479: };
480:
481: static nd_addrbank nd_ram_bank1 =
482: {
483: nd_ram_bank1_lget, nd_ram_bank1_wget, nd_ram_bank1_bget,
484: nd_ram_bank1_lput, nd_ram_bank1_wput, nd_ram_bank1_bput,
485: nd_ram_bank1_bget
486: };
487:
488: static nd_addrbank nd_ram_bank2 =
489: {
490: nd_ram_bank2_lget, nd_ram_bank2_wget, nd_ram_bank2_bget,
491: nd_ram_bank2_lput, nd_ram_bank2_wput, nd_ram_bank2_bput,
492: nd_ram_bank2_bget
493: };
494:
495: static nd_addrbank nd_ram_bank3 =
496: {
497: nd_ram_bank3_lget, nd_ram_bank3_wget, nd_ram_bank3_bget,
498: nd_ram_bank3_lput, nd_ram_bank3_wput, nd_ram_bank3_bput,
499: nd_ram_bank3_bget
500: };
501:
502: static nd_addrbank nd_ram_empty =
503: {
504: nd_ram_empty_lget, nd_ram_empty_wget, nd_ram_empty_bget,
505: nd_ram_empty_lput, nd_ram_empty_wput, nd_ram_empty_bput,
506: nd_ram_empty_bget
507: };
508:
509: static nd_addrbank nd_vram_bank =
510: {
511: nd_vram_lget, nd_vram_wget, nd_vram_bget,
512: nd_vram_lput, nd_vram_wput, nd_vram_bput,
513: nd_vram_bget
514: };
515:
516: static nd_addrbank nd_rom_bank =
517: {
518: nd_rom_lget, nd_rom_wget, nd_rom_bget,
1.1.1.2 ! root 519: nd_rom_lput, nd_rom_wput, nd_rom_bput,
1.1 root 520: nd_rom_cs8get
521:
522: };
523:
524: static nd_addrbank nd_dmem_bank =
525: {
526: nd_dmem_lget, nd_dmem_wget, nd_dmem_bget,
527: nd_dmem_lput, nd_dmem_wput, nd_dmem_bput,
528: nd_dmem_bget
529: };
530:
531: static nd_addrbank nd_io_bank =
532: {
533: nd_io_lget, nd_io_wget, nd_io_bget,
534: nd_io_lput, nd_io_wput, nd_io_bput,
535: nd_io_bget
536: };
537:
538: static nd_addrbank nd_ramdac_bank =
539: {
1.1.1.2 ! root 540: nd_ramdac_lget, nd_ramdac_wget, nd_ramdac_bget,
! 541: nd_ramdac_lput, nd_ramdac_wput, nd_ramdac_bput,
1.1 root 542: nd_ramdac_bget
543: };
544:
545: static nd_addrbank nd_illegal_bank =
546: {
547: nd_illegal_lget, nd_illegal_wget, nd_illegal_bget,
548: nd_illegal_lput, nd_illegal_wput, nd_illegal_bput,
549: nd_illegal_bget
550: };
551:
1.1.1.2 ! root 552: #if ND_STEP
! 553: static nd_addrbank nd_unknown_bank =
! 554: {
! 555: nd_unknown_lget, nd_unknown_wget, nd_unknown_bget,
! 556: nd_unknown_lput, nd_unknown_wput, nd_unknown_bput,
! 557: nd_unknown_bget
! 558: };
! 559: #endif
! 560:
1.1 root 561: static void nd_init_mem_banks (void)
562: {
563: int i;
564: for (i = 0; i < 65536; i++)
565: nd_put_mem_bank (i<<16, &nd_illegal_bank);
566: }
567:
568: void nd_memory_init(void) {
569:
570: write_log("[ND] Memory init: Memory size: %iMB\n",
571: Configuration_CheckDimensionMemory(ConfigureParams.Dimension.nMemoryBankSize));
572:
573: /* Initialize banks with error memory */
574: nd_init_mem_banks();
575:
1.1.1.2 ! root 576: /* Clear first 4k of memory for m68k ROM polling code */
! 577: memset(ND_ram, 0, 4096 * sizeof(Uint8));
! 578:
1.1 root 579: /* Map main memory */
580: if (ConfigureParams.Dimension.nMemoryBankSize[0]) {
581: ND_RAM_bankmask0 = ND_RAM_BANKMASK|((ConfigureParams.Dimension.nMemoryBankSize[0]<<20)-1);
582: nd_map_banks(&nd_ram_bank0, (ND_RAM_START+(0*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
583: write_log("[ND] Mapping main memory bank0 at $%08x: %iMB\n",
584: (ND_RAM_START+(0*ND_RAM_BANKSIZE)), ConfigureParams.Dimension.nMemoryBankSize[0]);
585: } else {
586: ND_RAM_bankmask0 = 0;
587: nd_map_banks(&nd_ram_empty, (ND_RAM_START+(0*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
588: write_log("[ND] Mapping main memory bank0 at $%08x: empty\n", (ND_RAM_START+(0*ND_RAM_BANKSIZE)));
589: }
590: if (ConfigureParams.Dimension.nMemoryBankSize[1]) {
591: ND_RAM_bankmask1 = ND_RAM_BANKMASK|((ConfigureParams.Dimension.nMemoryBankSize[1]<<20)-1);
592: nd_map_banks(&nd_ram_bank1, (ND_RAM_START+(1*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
593: write_log("[ND] Mapping main memory bank1 at $%08x: %iMB\n",
594: (ND_RAM_START+(1*ND_RAM_BANKSIZE)), ConfigureParams.Dimension.nMemoryBankSize[1]);
595: } else {
596: ND_RAM_bankmask1 = 0;
597: nd_map_banks(&nd_ram_empty, (ND_RAM_START+(1*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
598: write_log("[ND] Mapping main memory bank1 at $%08x: empty\n", (ND_RAM_START+(1*ND_RAM_BANKSIZE)));
599: }
600: if (ConfigureParams.Dimension.nMemoryBankSize[2]) {
601: ND_RAM_bankmask2 = ND_RAM_BANKMASK|((ConfigureParams.Dimension.nMemoryBankSize[2]<<20)-1);
602: nd_map_banks(&nd_ram_bank2, (ND_RAM_START+(2*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
603: write_log("[ND] Mapping main memory bank2 at $%08x: %iMB\n",
604: (ND_RAM_START+(2*ND_RAM_BANKSIZE)), ConfigureParams.Dimension.nMemoryBankSize[2]);
605: } else {
606: ND_RAM_bankmask2 = 0;
607: nd_map_banks(&nd_ram_empty, (ND_RAM_START+(2*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
608: write_log("[ND] Mapping main memory bank2 at $%08x: empty\n", (ND_RAM_START+(2*ND_RAM_BANKSIZE)));
609: }
610: if (ConfigureParams.Dimension.nMemoryBankSize[3]) {
611: ND_RAM_bankmask3 = ND_RAM_BANKMASK|((ConfigureParams.Dimension.nMemoryBankSize[3]<<20)-1);
612: nd_map_banks(&nd_ram_bank3, (ND_RAM_START+(3*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
613: write_log("[ND] Mapping main memory bank3 at $%08x: %iMB\n",
614: (ND_RAM_START+(3*ND_RAM_BANKSIZE)), ConfigureParams.Dimension.nMemoryBankSize[3]);
615: } else {
616: ND_RAM_bankmask3 = 0;
617: nd_map_banks(&nd_ram_empty, (ND_RAM_START+(3*ND_RAM_BANKSIZE))>>16, ND_RAM_BANKSIZE >> 16);
618: write_log("[ND] Mapping main memory bank3 at $%08x: empty\n", (ND_RAM_START+(3*ND_RAM_BANKSIZE)));
619: }
620:
621: write_log("[ND] Mapping video memory at $%08x: %iMB\n", ND_VRAM_START, ND_VRAM_SIZE/(1024*1024));
622: nd_map_banks(&nd_vram_bank, ND_VRAM_START>>16, (4*ND_VRAM_SIZE)>>16);
623:
624: write_log("[ND] Mapping ROM at $%08x: %ikB\n", ND_EEPROM_START, ND_EEPROM_SIZE/1024);
1.1.1.2 ! root 625: nd_map_banks(&nd_rom_bank, ND_EEPROM_START>>16, (ND_EEPROM_SIZE*8)>>16);
1.1 root 626: nd_rom_load();
627:
628: write_log("[ND] Mapping dither memory and data path at $%08x: %ibyte\n", ND_DMEM_START, ND_DMEM_SIZE);
629: nd_map_banks(&nd_dmem_bank, ND_DMEM_START>>16, 1);
630:
631: write_log("[ND] Mapping IO memory at $%08x\n", ND_IO_START);
632: nd_map_banks(&nd_io_bank, ND_IO_START>>16, 1);
633:
634: write_log("[ND] Mapping RAMDAC registers at $%08x\n", ND_RAMDAC_START);
635: nd_map_banks(&nd_ramdac_bank, ND_RAMDAC_START>>16, 1);
1.1.1.2 ! root 636: #if ND_STEP
! 637: write_log("[ND] Mapping Unknown register at $%08x\n", ND_UNKNWN_START);
! 638: nd_map_banks(&nd_unknown_bank, ND_UNKNWN_START>>16, 1);
1.1 root 639: #endif
1.1.1.2 ! root 640: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.