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1.1 root 1: #include "main.h"
2: #include "configuration.h"
3: #include "m68000.h"
4: #include "dimension.h"
5: #include "sysdeps.h"
6: #include "sysReg.h"
7: #include "nd_nbic.h"
8: #include "i860cfg.h"
9:
10: /* NeXTdimention NBIC */
11: #define ND_NBIC_ID 0xC0000001
12: #define ND_NBIC_INTR 0x80
13:
1.1.1.2 ! root 14: static volatile struct {
1.1 root 15: Uint32 control;
16: Uint32 id;
17: Uint8 intstatus;
18: Uint8 intmask;
19: } nd_nbic;
20:
1.1.1.2 ! root 21: #if 0 // We keep this code around in case registers turn out to be accessible. For now, just for reference.
! 22: static Uint8 nd_nbic_control_read0(Uint32 addr) {
1.1 root 23: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC Control (byte 0) read at %08X",addr);
24: return (nd_nbic.control>>24);
25: }
1.1.1.2 ! root 26: static Uint8 nd_nbic_control_read1(Uint32 addr) {
1.1 root 27: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC Control (byte 1) read at %08X",addr);
28: return (nd_nbic.control>>16);
29: }
1.1.1.2 ! root 30: static Uint8 nd_nbic_control_read2(Uint32 addr) {
1.1 root 31: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC Control (byte 2) read at %08X",addr);
32: return (nd_nbic.control>>8);
33: }
1.1.1.2 ! root 34: static Uint8 nd_nbic_control_read3(Uint32 addr) {
1.1 root 35: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC Control (byte 3) read at %08X",addr);
36: return nd_nbic.control;
37: }
38:
1.1.1.2 ! root 39: static void nd_nbic_control_write0(Uint32 addr, Uint8 val) {
1.1 root 40: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC Control (byte 0) write %02X at %08X",val,addr);
41: nd_nbic.control &= 0x00FFFFFF;
42: nd_nbic.control |= (val&0xFF)<<24;
43: }
1.1.1.2 ! root 44: static void nd_nbic_control_write1(Uint32 addr, Uint8 val) {
1.1 root 45: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC Control (byte 1) write %02X at %08X",val,addr);
46: nd_nbic.control &= 0xFF00FFFF;
47: nd_nbic.control |= (val&0xFF)<<16;
48: }
1.1.1.2 ! root 49: static void nd_nbic_control_write2(Uint32 addr, Uint8 val) {
1.1 root 50: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC Control (byte 2) write %02X at %08X",val,addr);
51: nd_nbic.control &= 0xFFFF00FF;
52: nd_nbic.control |= (val&0xFF)<<8;
53: }
1.1.1.2 ! root 54: static void nd_nbic_control_write3(Uint32 addr, Uint8 val) {
1.1 root 55: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC Control (byte 3) write %02X at %08X",val,addr);
56: nd_nbic.control &= 0xFFFFFF00;
57: nd_nbic.control |= val&0xFF;
58: }
59:
1.1.1.2 ! root 60: static void nd_nbic_id_write0(Uint32 addr, Uint8 val) {
1.1 root 61: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC ID (byte 0) write %02X at %08X",val,addr);
62: nd_nbic.id &= 0x00FFFFFF;
63: nd_nbic.id |= (val&0xFF)<<24;
64: }
1.1.1.2 ! root 65: static void nd_nbic_id_write1(Uint32 addr, Uint8 val) {
1.1 root 66: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC ID (byte 1) write %02X at %08X",val,addr);
67: nd_nbic.id &= 0xFF00FFFF;
68: nd_nbic.id |= (val&0xFF)<<16;
69: }
1.1.1.2 ! root 70: static void nd_nbic_id_write2(Uint32 addr, Uint8 val) {
1.1 root 71: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC ID (byte 2) write %02X at %08X",val,addr);
72: nd_nbic.id &= 0xFFFF00FF;
73: nd_nbic.id |= (val&0xFF)<<8;
74: }
1.1.1.2 ! root 75: static void nd_nbic_id_write3(Uint32 addr, Uint8 val) {
1.1 root 76: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC ID (byte 3) write %02X at %08X",val,addr);
77: nd_nbic.id &= 0xFFFFFF00;
78: nd_nbic.id |= val&0xFF;
79: }
1.1.1.2 ! root 80: #endif
! 81:
! 82: static Uint8 nd_nbic_id_read0(Uint32 addr) {
! 83: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC ID (byte 0) read at %08X",addr);
! 84: return (nd_nbic.id>>24);
! 85: }
! 86: static Uint8 nd_nbic_id_read1(Uint32 addr) {
! 87: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC ID (byte 1) read at %08X",addr);
! 88: return (nd_nbic.id>>16);
! 89: }
! 90: static Uint8 nd_nbic_id_read2(Uint32 addr) {
! 91: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC ID (byte 2) read at %08X",addr);
! 92: return (nd_nbic.id>>8);
! 93: }
! 94: static Uint8 nd_nbic_id_read3(Uint32 addr) {
! 95: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC ID (byte 3) read at %08X",addr);
! 96: return nd_nbic.id;
! 97: }
1.1 root 98:
1.1.1.2 ! root 99: static Uint8 nd_nbic_intstatus_read(Uint32 addr) {
1.1 root 100: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC Interrupt status read at %08X",addr);
101: return nd_nbic.intstatus;
102: }
103:
1.1.1.2 ! root 104: static Uint8 nd_nbic_intmask_read(Uint32 addr) {
1.1 root 105: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC Interrupt mask read at %08X",addr);
106: return nd_nbic.intmask;
107: }
1.1.1.2 ! root 108: static void nd_nbic_intmask_write(Uint32 addr, Uint8 val) {
1.1 root 109: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC Interrupt mask write %02X at %08X",val,addr);
110: nd_nbic.intmask = val;
111: }
112:
1.1.1.2 ! root 113: static Uint8 nd_nbic_zero_read(Uint32 addr) {
1.1 root 114: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC zero read at %08X",addr);
115: return 0;
116: }
1.1.1.2 ! root 117: static void nd_nbic_zero_write(Uint32 addr, Uint8 val) {
1.1 root 118: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC zero write %02X at %08X",val,addr);
119: }
120:
1.1.1.2 ! root 121: static Uint8 nd_nbic_bus_error_read(Uint32 addr) {
1.1 root 122: Log_Printf(ND_LOG_IO_RD, "[ND] NBIC bus error read at %08X",addr);
123: M68000_BusError(addr, 1);
124: return 0;
125: }
1.1.1.2 ! root 126: static void nd_nbic_bus_error_write(Uint32 addr, Uint8 val) {
1.1 root 127: Log_Printf(ND_LOG_IO_WR, "[ND] NBIC bus error write at %08X",addr);
128: M68000_BusError(addr, 0);
129: }
130:
131: static Uint8 (*nd_nbic_read[32])(Uint32) = {
132: nd_nbic_bus_error_read, nd_nbic_bus_error_read, nd_nbic_bus_error_read, nd_nbic_bus_error_read,
133: nd_nbic_bus_error_read, nd_nbic_bus_error_read, nd_nbic_bus_error_read, nd_nbic_bus_error_read,
134: nd_nbic_intstatus_read, nd_nbic_zero_read, nd_nbic_zero_read, nd_nbic_zero_read,
135: nd_nbic_intmask_read, nd_nbic_zero_read, nd_nbic_zero_read, nd_nbic_zero_read,
136:
137: nd_nbic_id_read0, nd_nbic_zero_read, nd_nbic_zero_read, nd_nbic_zero_read,
138: nd_nbic_id_read1, nd_nbic_zero_read, nd_nbic_zero_read, nd_nbic_zero_read,
139: nd_nbic_id_read2, nd_nbic_zero_read, nd_nbic_zero_read, nd_nbic_zero_read,
140: nd_nbic_id_read3, nd_nbic_zero_read, nd_nbic_zero_read, nd_nbic_zero_read,
141: };
142:
143: static void (*nd_nbic_write[32])(Uint32, Uint8) = {
144: nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write,
145: nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write,
146: nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write,
147: nd_nbic_intmask_write, nd_nbic_zero_write, nd_nbic_zero_write, nd_nbic_zero_write,
148:
149: nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write,
150: nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write,
151: nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write,
152: nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write, nd_nbic_bus_error_write
153: };
154:
155:
156: /* NeXTdimension NBIC access */
157: Uint32 nd_nbic_lget(Uint32 addr) {
158: Uint32 val = 0;
159:
160: if (addr&3) {
161: Log_Printf(LOG_WARN, "[ND] NBIC Unaligned access at %08X.",addr);
162: abort();
163: }
164: val = nd_nbic_read[addr&0x1F](addr)<<24;
165: val |= nd_nbic_read[(addr&0x1F)+1](addr+1)<<16;
166: val |= nd_nbic_read[(addr&0x1F)+2](addr+2)<<8;
167: val |= nd_nbic_read[(addr&0x1F)+3](addr+3);
168:
169: return val;
170: }
171:
172: Uint16 nd_nbic_wget(Uint32 addr) {
173: Uint32 val = 0;
174:
175: if (addr&1) {
176: Log_Printf(LOG_WARN, "[ND] NBIC Unaligned access at %08X.",addr);
177: abort();
178: }
179: val = nd_nbic_read[addr&0x1F](addr)<<8;
180: val |= nd_nbic_read[(addr&0x1F)+1](addr+1)<<16;
181:
182: return val;
183: }
184:
185: Uint8 nd_nbic_bget(Uint32 addr) {
186: return nd_nbic_read[addr&0x1F](addr);
187: }
188:
189: void nd_nbic_lput(Uint32 addr, Uint32 l) {
190: if (addr&3) {
191: Log_Printf(LOG_WARN, "[ND] NBIC Unaligned access at %08X.",addr);
192: abort();
193: }
194: nd_nbic_write[addr&0x1F](addr,l>>24);
195: nd_nbic_write[(addr&0x1F)+1](addr,l>>16);
196: nd_nbic_write[(addr&0x1F)+2](addr,l>>8);
197: nd_nbic_write[(addr&0x1F)+3](addr,l);
198: }
199:
200: void nd_nbic_wput(Uint32 addr, Uint16 w) {
201: if (addr&1) {
202: Log_Printf(LOG_WARN, "[ND] NBIC Unaligned access at %08X.",addr);
203: abort();
204: }
205: nd_nbic_write[addr&0x1F](addr,w>>8);
206: nd_nbic_write[(addr&0x1F)+1](addr,w);
207: }
208:
209: void nd_nbic_bput(Uint32 addr, Uint8 b) {
210: nd_nbic_write[addr&0x1F](addr,b);
211: }
212:
213: void nd_nbic_set_intstatus(bool set) {
214: if (set) {
215: nd_nbic.intstatus |= ND_NBIC_INTR;
216: } else {
217: nd_nbic.intstatus &= ~ND_NBIC_INTR;
218: }
219: }
220:
221:
222: /* Reset function */
223:
224: void nd_nbic_init(void) {
225: nd_nbic.id = ND_NBIC_ID;
226: /* Release any interrupt that may be pending */
227: nd_nbic.intmask = 0;
228: nd_nbic.intstatus = 0;
229: set_interrupt(INT_REMOTE, RELEASE_INT);
230: }
231:
1.1.1.2 ! root 232: /* Interrupt functions */
! 233: void nd_nbic_interrupt(void) {
! 234: if (nd_nbic.intmask&nd_nbic.intstatus&ND_NBIC_INTR) {
! 235: set_interrupt(INT_REMOTE, SET_INT);
! 236: } else {
! 237: set_interrupt(INT_REMOTE, RELEASE_INT);
! 238: }
! 239: }
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