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1.1 root 1: /*
2: DSP M56001 emulation
3: Core of DSP emulation
4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this program; if not, write to the Free Software
19: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
22: #ifndef DSP_CORE_H
23: #define DSP_CORE_H
24:
25: #include <SDL.h>
26:
27: #ifdef __cplusplus
28: extern "C" {
29: #endif
30:
31: #define DSP_RAMSIZE_MAX (3*64*1024)
32: #define DSP_RAMSIZE_24kB 8192
33: #define DSP_RAMSIZE_96kB 32768
34:
35: extern Uint32 DSP_RAMSIZE;
36:
37: /* Host port, CPU side */
38: #define CPU_HOST_ICR 0x00
39: #define CPU_HOST_CVR 0x01
40: #define CPU_HOST_ISR 0x02
41: #define CPU_HOST_IVR 0x03
42: #define CPU_HOST_TRX0 0x04
43: #define CPU_HOST_TRXH 0x05
44: #define CPU_HOST_TRXM 0x06
45: #define CPU_HOST_TRXL 0x07
46: #define CPU_HOST_RX0 0x04
47: #define CPU_HOST_RXH 0x05
48: #define CPU_HOST_RXM 0x06
49: #define CPU_HOST_RXL 0x07
50: #define CPU_HOST_TXH 0x09
51: #define CPU_HOST_TXM 0x0a
52: #define CPU_HOST_TXL 0x0b
53:
54: #define CPU_HOST_ICR_RREQ 0x00
55: #define CPU_HOST_ICR_TREQ 0x01
56: #define CPU_HOST_ICR_HF0 0x03
57: #define CPU_HOST_ICR_HF1 0x04
58: #define CPU_HOST_ICR_HM0 0x05
59: #define CPU_HOST_ICR_HM1 0x06
60: #define CPU_HOST_ICR_INIT 0x07
61:
62: #define CPU_HOST_CVR_HC 0x07
63:
64: #define CPU_HOST_ISR_RXDF 0x00
65: #define CPU_HOST_ISR_TXDE 0x01
66: #define CPU_HOST_ISR_TRDY 0x02
67: #define CPU_HOST_ISR_HF2 0x03
68: #define CPU_HOST_ISR_HF3 0x04
69: #define CPU_HOST_ISR_DMA 0x06
70: #define CPU_HOST_ISR_HREQ 0x07
71:
72: /* Host port, DSP side, DSP addresses are 0xffc0+value */
73: #define DSP_PBC 0x20 /* Port B control register */
74: #define DSP_PCC 0x21 /* Port C control register */
75: #define DSP_PBDDR 0x22 /* Port B data direction register */
76: #define DSP_PCDDR 0x23 /* Port C data direction register */
77: #define DSP_PBD 0x24 /* Port B data register */
78: #define DSP_PCD 0x25 /* Port C data register */
79: #define DSP_HOST_HCR 0x28 /* Host control register */
80: #define DSP_HOST_HSR 0x29 /* Host status register */
81: #define DSP_HOST_HRX 0x2b /* Host receive register */
82: #define DSP_HOST_HTX 0x2b /* Host transmit register */
83: #define DSP_SSI_CRA 0x2c /* Ssi control register A */
84: #define DSP_SSI_CRB 0x2d /* Ssi control register B */
85: #define DSP_SSI_SR 0x2e /* Ssi status register */
86: #define DSP_SSI_TSR 0x2e /* Ssi time slot register */
87: #define DSP_SSI_RX 0x2f /* Ssi receive register */
88: #define DSP_SSI_TX 0x2f /* Ssi transmit register */
89: #define DSP_BCR 0x3e /* Port A bus control register */
90: #define DSP_IPR 0x3f /* Interrupt priority register */
91:
92: #define DSP_HOST_HCR_HRIE 0x00
93: #define DSP_HOST_HCR_HTIE 0x01
94: #define DSP_HOST_HCR_HCIE 0x02
95: #define DSP_HOST_HCR_HF2 0x03
96: #define DSP_HOST_HCR_HF3 0x04
97:
98: #define DSP_HOST_HSR_HRDF 0x00
99: #define DSP_HOST_HSR_HTDE 0x01
100: #define DSP_HOST_HSR_HCP 0x02
101: #define DSP_HOST_HSR_HF0 0x03
102: #define DSP_HOST_HSR_HF1 0x04
103: #define DSP_HOST_HSR_DMA 0x07
104:
105: #define DSP_SSI_CRA_DC0 0x8
106: #define DSP_SSI_CRA_DC1 0x9
107: #define DSP_SSI_CRA_DC2 0xa
108: #define DSP_SSI_CRA_DC3 0xb
109: #define DSP_SSI_CRA_DC4 0xc
110: #define DSP_SSI_CRA_WL0 0xd
111: #define DSP_SSI_CRA_WL1 0xe
112:
113: #define DSP_SSI_CRB_OF0 0x0
114: #define DSP_SSI_CRB_OF1 0x1
115: #define DSP_SSI_CRB_SCD0 0x2
116: #define DSP_SSI_CRB_SCD1 0x3
117: #define DSP_SSI_CRB_SCD2 0x4
118: #define DSP_SSI_CRB_SCKD 0x5
119: #define DSP_SSI_CRB_SHFD 0x6
120: #define DSP_SSI_CRB_FSL0 0x7
121: #define DSP_SSI_CRB_FSL1 0x8
122: #define DSP_SSI_CRB_SYN 0x9
123: #define DSP_SSI_CRB_GCK 0xa
124: #define DSP_SSI_CRB_MOD 0xb
125: #define DSP_SSI_CRB_TE 0xc
126: #define DSP_SSI_CRB_RE 0xd
127: #define DSP_SSI_CRB_TIE 0xe
128: #define DSP_SSI_CRB_RIE 0xf
129:
130: #define DSP_SSI_SR_IF0 0x0
131: #define DSP_SSI_SR_IF1 0x1
132: #define DSP_SSI_SR_TFS 0x2
133: #define DSP_SSI_SR_RFS 0x3
134: #define DSP_SSI_SR_TUE 0x4
135: #define DSP_SSI_SR_ROE 0x5
136: #define DSP_SSI_SR_TDE 0x6
137: #define DSP_SSI_SR_RDF 0x7
138:
139: #define DSP_INTERRUPT_NONE 0x0
140: #define DSP_INTERRUPT_DISABLED 0x1
141: #define DSP_INTERRUPT_LONG 0x2
142:
143: #define DSP_INTER_RESET 0
144: #define DSP_INTER_STACK_ERROR 1
145: #define DSP_INTER_TRACE 2
146: #define DSP_INTER_SWI 3
147: #define DSP_INTER_IRQA 4
148: #define DSP_INTER_IRQB 5
149: #define DSP_INTER_SSI_RCV_DATA 6
150: #define DSP_INTER_SSI_RCV_DATA_E 7
151: #define DSP_INTER_SSI_TRX_DATA 8
152: #define DSP_INTER_SSI_TRX_DATA_E 9
153: #define DSP_INTER_SCI_RCV_DATA 10
154: #define DSP_INTER_SCI_RCV_DATA_E 11
155: #define DSP_INTER_SCI_TRX_DATA 12
156: #define DSP_INTER_SCI_IDLE_LINE 13
157: #define DSP_INTER_SCI_TIMER 14
158: #define DSP_INTER_NMI 15
159: #define DSP_INTER_HOST_RCV_DATA 16
160: #define DSP_INTER_HOST_TRX_DATA 17
161: #define DSP_INTER_HOST_COMMAND 18
162: #define DSP_INTER_ILLEGAL 31
163:
164: #define DSP_INTER_NMI_MASK 0x8000800F
165: #define DSP_INTER_IRQA_MASK 0x00000010
166: #define DSP_INTER_IRQB_MASK 0x00000020
167: #define DSP_INTER_SSI_MASK 0x000003C0
168: #define DSP_INTER_SCI_MASK 0x00007C00
169: #define DSP_INTER_HOST_MASK 0x00070000
170:
171: #define DSP_INTER_EDGE_MASK 0x8004C00E
172:
173:
174: #define DSP_PRIORITY_LIST_EXIT 32
175: extern const char dsp_inter_priority_list[32];
176: extern const char *dsp_interrupt_name[32];
177:
178:
179: typedef struct dsp_core_ssi_s dsp_core_ssi_t;
180: typedef struct dsp_core_s dsp_core_t;
181:
182: struct dsp_core_ssi_s {
183: Uint16 cra_word_length;
184: Uint32 cra_word_mask;
185: Uint16 cra_frame_rate_divider;
186:
187: Uint16 crb_src_clock;
188: Uint16 crb_shifter;
189: Uint16 crb_synchro;
190: Uint16 crb_mode;
191: Uint16 crb_te;
192: Uint16 crb_re;
193: Uint16 crb_tie;
194: Uint16 crb_rie;
195:
196: Uint32 TX;
197: Uint32 RX;
198: Uint32 transmit_value; /* DSP Transmit --> SSI */
199: Uint32 received_value; /* DSP Receive --> SSI */
200: Uint16 waitFrameTX;
201: Uint16 waitFrameRX;
202: Uint32 dspPlay_handshakeMode_frame;
203: };
204:
205:
206: struct dsp_core_s {
207:
208: /* DSP executing instructions ? */
209: int running;
210:
211: /* DSP DMA variables */
212: int dma_mode;
213: int dma_direction;
214: int dma_request;
215: int dma_address_counter;
216:
217: /* DSP instruction Cycle counter */
218: Uint16 instr_cycle;
219:
220: /* Registers */
221: Uint16 pc;
222: Uint32 registers[64];
223:
224: /* stack[0=ssh], stack[1=ssl] */
225: Uint16 stack[2][16];
226:
227: /* External ram[] (mapped to p:) */
228: Uint32 ramext[DSP_RAMSIZE_MAX];
229:
230: /* rom[0] is x:, rom[1] is y: */
231: Uint32 rom[2][512];
232:
233: /* Internal ram[0] is x:, ram[1] is y:, ram[2] is p: */
234: Uint32 ramint[3][512];
235:
236: /* peripheral space, [x|y]:0xffc0-0xffff */
237: Uint32 periph[2][64];
238: Uint32 dsp_host_htx;
239: Uint32 dsp_host_rtx;
240: Uint16 dsp_host_isr_HREQ;
241:
242:
243: /* host port, CPU side */
244: Uint8 hostport[12];
245:
246: /* SSI */
247: dsp_core_ssi_t ssi;
248:
249: /* Misc */
250: Uint32 loop_rep; /* executing rep ? */
251: Uint32 pc_on_rep; /* True if PC is on REP instruction */
252:
253: /* For bootstrap routine */
254: Uint16 bootstrap_pos;
255:
256: /* Interruptions */
257: Uint16 interrupt_state; /* NONE, FAST or LONG interrupt */
258: Uint16 interrupt_instr_fetch; /* vector of the current interrupt */
259: Uint16 interrupt_save_pc; /* save next pc value before interrupt */
260: Uint16 interrupt_IplToRaise; /* save the IPL level to save in the SR register */
261: Uint16 interrupt_pipeline_count; /* used to prefetch correctly the 2 inter instructions */
262:
263: /* Interruptions new */
264: Uint32 interrupt_status;
265: Uint32 interrupt_enable;
266: Uint32 interrupt_mask;
267: Uint32 interrupt_mask_level[3];
268: Uint32 interrupt_edgetriggered_mask;
269: };
270:
271:
272: /* DSP */
273: extern dsp_core_t dsp_core;
274:
275: /* Emulator call these to init/stop/reset DSP emulation */
276: extern void dsp_core_init(void (*host_interrupt)(int set));
277: extern void dsp_core_shutdown(void);
278: extern void dsp_core_reset(void);
279: extern void dsp_core_start(Uint8 mode);
280:
281: /* host port read/write by emulator, addr is 0-7, not 0xffa200-0xffa207 */
282: extern Uint8 dsp_core_read_host(int addr);
283: extern void dsp_core_write_host(int addr, Uint8 value);
284:
285: /* dsp_cpu call these to read/write host port */
286: extern void dsp_core_hostport_dspread(void);
287: extern void dsp_core_hostport_dspwrite(void);
288:
289: /* dsp_cpu call these to read/write/configure SSI port */
290: extern void dsp_core_ssi_configure(Uint32 address, Uint32 value);
291: extern void dsp_core_ssi_writeTX(Uint32 value);
292: extern void dsp_core_ssi_writeTSR(void);
293: extern Uint32 dsp_core_ssi_readRX(void);
294: extern void dsp_core_ssi_Receive_SC0(void);
295: extern void dsp_core_ssi_Receive_SC1(Uint32 value);
296: extern void dsp_core_ssi_Receive_SC2(Uint32 value);
297: extern void dsp_core_ssi_Receive_SCK(void);
298: extern void dsp_core_setPortCDataRegister(Uint32 value);
299:
300: #ifdef __cplusplus
301: }
302: #endif
303:
304: #endif /* DSP_CORE_H */
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