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1.1 root 1: /*
2: Hatari - m68000.h
3:
4: This file is distributed under the GNU Public License, version 2 or at
5: your option any later version. Read the file gpl.txt for details.
6: */
7:
8: /* 2007/11/10 [NP] Add pairing for lsr / dbcc (and all variants */
9: /* working on register, not on memory). */
10: /* 2008/01/07 [NP] Use PairingArray to store all valid pairing */
11: /* combinations (in m68000.c) */
12: /* 2010/04/05 [NP] Rework the pairing code to take BusCyclePenalty */
13: /* into account when using d8(an,ix). */
14: /* 2010/05/07 [NP] Add BusCyclePenalty to LastInstrCycles to detect*/
15: /* a possible pairing between add.l (a5,d1.w),d0 */
16: /* and move.b 7(a5,d1.w),d5. */
17:
18:
19: #ifndef HATARI_M68000_H
20: #define HATARI_M68000_H
21:
22: #include "cycles.h" /* for nCyclesMainCounter */
23: #include "sysdeps.h"
24: #include "memory.h"
25: #include "newcpu.h" /* for regs */
26: #include "cycInt.h"
27: #include "log.h"
28:
29:
30: /* 68000 Register defines */
31: enum {
32: REG_D0, /* D0.. */
33: REG_D1,
34: REG_D2,
35: REG_D3,
36: REG_D4,
37: REG_D5,
38: REG_D6,
39: REG_D7, /* ..D7 */
40: REG_A0, /* A0.. */
41: REG_A1,
42: REG_A2,
43: REG_A3,
44: REG_A4,
45: REG_A5,
46: REG_A6,
47: REG_A7, /* ..A7 (also SP) */
48: };
49:
50: /* 68000 Condition code's */
51: #define SR_AUX 0x0010
52: #define SR_NEG 0x0008
53: #define SR_ZERO 0x0004
54: #define SR_OVERFLOW 0x0002
55: #define SR_CARRY 0x0001
56:
57: #define SR_CLEAR_AUX 0xffef
58: #define SR_CLEAR_NEG 0xfff7
59: #define SR_CLEAR_ZERO 0xfffb
60: #define SR_CLEAR_OVERFLOW 0xfffd
61: #define SR_CLEAR_CARRY 0xfffe
62:
63: #define SR_CCODE_MASK (SR_AUX|SR_NEG|SR_ZERO|SR_OVERFLOW|SR_CARRY)
64: #define SR_MASK 0xFFE0
65:
66: #define SR_TRACEMODE 0x8000
67: #define SR_SUPERMODE 0x2000
68: #define SR_IPL 0x0700
69:
70: #define SR_CLEAR_IPL 0xf8ff
71: #define SR_CLEAR_TRACEMODE 0x7fff
72: #define SR_CLEAR_SUPERMODE 0xdfff
73:
74: /* Exception vectors */
75: #define EXCEPTION_BUSERROR 0x00000008
76: #define EXCEPTION_ADDRERROR 0x0000000c
77: #define EXCEPTION_ILLEGALINS 0x00000010
78: #define EXCEPTION_DIVZERO 0x00000014
79: #define EXCEPTION_CHK 0x00000018
80: #define EXCEPTION_TRAPV 0x0000001c
81: #define EXCEPTION_TRACE 0x00000024
82: #define EXCEPTION_LINE_A 0x00000028
83: #define EXCEPTION_LINE_F 0x0000002c
84: #define EXCEPTION_HBLANK 0x00000068
85: #define EXCEPTION_VBLANK 0x00000070
86: #define EXCEPTION_TRAP0 0x00000080
87: #define EXCEPTION_TRAP1 0x00000084
88: #define EXCEPTION_TRAP2 0x00000088
89: #define EXCEPTION_TRAP13 0x000000B4
90: #define EXCEPTION_TRAP14 0x000000B8
91:
92:
93: /* Size of 68000 instructions */
94: #define MAX_68000_INSTRUCTION_SIZE 10 /* Longest 68000 instruction is 10 bytes(6+4) */
95: #define MIN_68000_INSTRUCTION_SIZE 2 /* Smallest 68000 instruction is 2 bytes(ie NOP) */
96:
97: /* Illegal Opcode used to help emulation. eg. free entries are 8 to 15 inc' */
98: #define GEMDOS_OPCODE 8 /* Free op-code to intercept GemDOS trap */
99: #define SYSINIT_OPCODE 10 /* Free op-code to initialize system (connected drives etc.) */
100: #define VDI_OPCODE 12 /* Free op-code to call VDI handlers AFTER Trap#2 */
101:
102:
103:
104: /* Ugly hacks to adapt the main code to the different CPU cores: */
105:
106: #define Regs regs.regs
107:
108: # define M68000_GetPC() m68k_getpc()
109: # define M68000_SetPC(val) m68k_setpc(val)
110:
111: static inline Uint16 M68000_GetSR(void)
112: {
113: MakeSR();
114: return regs.sr;
115: }
116: static inline void M68000_SetSR(Uint16 v)
117: {
118: regs.sr = v;
119: MakeFromSR();
120: }
121:
122: # define M68000_SetSpecial(flags) set_special(flags)
123: # define M68000_UnsetSpecial(flags) unset_special(flags)
124:
125:
126: /* bus error mode */
127: #define BUS_ERROR_WRITE 0
128: #define BUS_ERROR_READ 1
129:
130:
1.1.1.2 ! root 131: /* bus access mode */
1.1 root 132: #define BUS_MODE_CPU 0 /* bus is owned by the cpu */
133: #define BUS_MODE_BLITTER 1 /* bus is owned by the blitter */
134:
135:
136: extern Uint32 BusErrorAddress;
137: extern Uint32 BusErrorPC;
138: extern bool bBusErrorReadWrite;
139: extern int nCpuFreqShift;
140: extern int nWaitStateCycles;
141: extern int BusMode;
142:
143: extern int LastOpcodeFamily;
144: extern int LastInstrCycles;
145: extern int Pairing;
146: extern char PairingArray[ MAX_OPCODE_FAMILY ][ MAX_OPCODE_FAMILY ];
147: extern const char *OpcodeName[];
148:
149:
150: /*-----------------------------------------------------------------------*/
151: /**
152: * Add CPU cycles.
153: * NOTE: All times are rounded up to nearest 4 cycles.
154: */
155: static inline void M68000_AddCycles(int cycles)
156: {
157: cycles = (cycles + 3) & ~3;
158: cycles = cycles >> nCpuFreqShift;
159:
160: PendingInterruptCount -= INT_CONVERT_TO_INTERNAL(cycles, INT_CPU_CYCLE);
161: nCyclesMainCounter += cycles;
162: }
163:
164:
165: /*-----------------------------------------------------------------------*/
166: /**
167: * Add CPU cycles, take cycles pairing into account. Pairing will make
168: * some specific instructions take 4 cycles less when run one after the other.
169: * Pairing happens when the 2 instructions are "aligned" on different bus accesses.
170: * Candidates are :
171: * - 2 instructions taking 4n+2 cycles
172: * - 1 instruction taking 4n+2 cycles, followed by 1 instruction using d8(an,ix)
173: *
174: * Not all the candidate instructions can pair, only the opcodes listed in PairingArray.
175: * On ST, when using d8(an,ix), we get an extra 2 cycle penalty for misaligned bus access.
176: * The only instruction that can generate BusCyclePenalty=4 is move d8(an,ix),d8(an,ix)
177: * and although it takes 4n cycles (24 for .b/.w or 32 for .l) it can pair with
178: * a previous 4n+2 instruction (but it will still have 1 misaligned bus access in the end).
179: *
180: * Verified pairing on an STF :
181: * - lsl.w #4,d1 + move.w 0(a4,d2.w),d1 motorola=14+14=28 stf=28
182: * - lsl.w #4,d1 + move.w 0(a4,d2.w),(a4) motorola=14+18=32 stf=32
183: * - lsl.w #4,d1 + move.w 0(a4,d2.w),0(a4,d2.w) motorola=14+24=38 stf=40
184: * - add.l (a5,d1.w),d0 + move.b 7(a5,d1.w),d5) motorola=20+14=34 stf=36
185: *
186: * d8(an,ix) timings without pairing (2 cycles penalty) :
187: * - add.l 0(a4,d2.w),a1 motorola=20 stf=24
188: * - move.w 0(a4,d2.w),d1 motorola=14 stf=16
189: * - move.w 0(a4,d2.w),(a4) motorola=18 stf=20
190: * - move.w 0(a4,d2.w),0(a4,d2.w) motorola=24 stf=28
191: *
192: * NOTE: All times are rounded up to nearest 4 cycles.
193: */
194: static inline void M68000_AddCyclesWithPairing(int cycles)
195: {
196: Pairing = 0;
197: /* Check if number of cycles for current instr and for */
198: /* the previous one is of the form 4+2n */
199: /* If so, a pairing could be possible depending on the opcode */
200: /* A pairing is also possible if current instr is 4n but with BusCyclePenalty > 0 */
201: if ( ( PairingArray[ LastOpcodeFamily ][ OpcodeFamily ] == 1 )
202: && ( ( LastInstrCycles & 3 ) == 2 )
203: && ( ( ( cycles & 3 ) == 2 ) || ( BusCyclePenalty > 0 ) ) )
204: {
205: Pairing = 1;
206: LOG_TRACE(TRACE_CPU_PAIRING,
207: "cpu pairing detected pc=%x family %s/%s cycles %d/%d\n",
208: m68k_getpc(), OpcodeName[LastOpcodeFamily],
209: OpcodeName[OpcodeFamily], LastInstrCycles, cycles);
210: }
211:
212: /* [NP] This part is only needed to track possible pairing instructions, */
213: /* we can keep it disabled most of the time */
214: #if 0
215: if ( (LastOpcodeFamily!=OpcodeFamily) && ( Pairing == 0 )
216: && ( ( cycles & 3 ) == 2 ) && ( ( LastInstrCycles & 3 ) == 2 ) )
217: {
218: LOG_TRACE(TRACE_CPU_PAIRING,
219: "cpu could pair pc=%x family %s/%s cycles %d/%d\n",
220: m68k_getpc(), OpcodeName[LastOpcodeFamily],
221: OpcodeName[OpcodeFamily], LastInstrCycles, cycles);
222: }
223: #endif
224:
225: /* Store current instr (not rounded) to check next time */
226: LastInstrCycles = cycles + BusCyclePenalty;
227: LastOpcodeFamily = OpcodeFamily;
228:
229: /* If pairing is true, we need to substract 2 cycles for the */
230: /* previous instr which was rounded to 4 cycles while it wasn't */
231: /* needed (and we don't round the current one) */
232: /* -> both instr will take 4 cycles less on the ST than if ran */
233: /* separately. */
234: if (Pairing == 1)
235: {
236: if ( ( cycles & 3 ) == 2 ) /* pairing between 4n+2 and 4n+2 instructions */
237: cycles -= 2; /* if we have a pairing, we should not count the misaligned bus access */
238:
239: else /* this is the case of move d8(an,ix),d8(an,ix) where BusCyclePenalty=4 */
240: /*do nothing */; /* we gain 2 cycles for the pairing with 1st d8(an,ix) */
241: /* and we have 1 remaining misaligned access for the 2nd d8(an,ix). So in the end, we keep */
242: /* cycles unmodified as 4n cycles (eg lsl.w #4,d1 + move.w 0(a4,d2.w),0(a4,d2.w) takes 40 cycles) */
243: }
244: else
245: {
246: cycles += BusCyclePenalty; /* >0 if d8(an,ix) was used */
247: cycles = (cycles + 3) & ~3; /* no pairing, round current instr to 4 cycles */
248: }
249:
250: cycles = cycles >> nCpuFreqShift;
251:
252: PendingInterruptCount -= INT_CONVERT_TO_INTERNAL ( cycles , INT_CPU_CYCLE );
253:
254: nCyclesMainCounter += cycles;
255: BusCyclePenalty = 0;
256: }
257:
258:
259: extern void M68000_Init(void);
260: extern void M68000_Reset(bool bCold);
261: extern void M68000_Start(void);
1.1.1.2 ! root 262: extern void M68000_CheckCpuSettings(void);
1.1 root 263: extern void M68000_MemorySnapShot_Capture(bool bSave);
264: extern void M68000_BusError(Uint32 addr, bool bReadWrite);
265: extern void M68000_Exception(Uint32 ExceptionVector , int ExceptionSource);
266: extern void M68000_WaitState(int nCycles);
267:
268: #endif
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