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1.1 root 1: /* SCC Z8530 Registers and Values */
2:
3: /* Read Registers */
4: #define R_STATUS 0 // Transmit/Receive buffer status and External status
5: #define R_SPECSTAT 1 // Special receive condition status
6: #define R_INTVEC 2 // Interrupt vector
7: #define R_INTBITS 3 // Interrupt pending bits
8: #define R_RECBUF 8 // Receive buffer
9: #define R_MISCSTAT 10 // Miscellaneous status
10: #define R_BRG_LOW 12 // Lower byte of baud rate generator time constant
11: #define R_BRG_HIGH 13 // Upper byte of baud rate generator time constant
12: #define R_EXTSTAT 15 // External/Status interrupt information
13:
14: /* Write Registers */
15: #define W_INIT 0 // Initialization commands
16: #define W_MODE 1 // Transmit/Receive interrupt and data transfer mode
17: #define W_INTVEC 2 // Interrupt vector
18: #define W_RECCONT 3 // Receive parameters and control
19: #define W_MISCMODE 4 // Transmit/Receive miscellaneous parameters and modes
20: #define W_TRANSCONT 5 // Transmit parameters and controls
21: #define W_SYNCCHARA 6 // Sync characters or SDLC address field
22: #define W_SYNCCHARF 7 // Sync character or SDLC flag
23: #define W_TRANSBUF 8 // Transmit buffer
24: #define W_MASTERINT 9 // Master interrupt control and reset
25: #define W_MISCCONT 10 // Miscellaneous transmitter/receiver control bits
26: #define W_CLOCK 11 // Clock mode control
27: #define W_BRG_LOW 12 // Lower byte of baud rate generator time constant
28: #define W_BRG_HIGH 13 // Upper byte of baud rate generator time constant
29: #define W_MISC 14 // Miscellaneous control bits
30: #define W_EXTSTAT 15 // External/Status interrupt control
31:
32:
33: /* SCC clock select register (0x02018004) */
34: #define PCLK_ESCLK 0x00000010
35: #define PCLK_3684_MHZ 0x00000000
36: #define SCLKB_4_MHZ 0x00000008
37: #define SCLKB_ESCLK 0x00000004
38: #define SCLKB_3684_MHZ 0x00000000
39: #define SCLKA_4_MHZ 0x00000002
40: #define SCLKA_ESCLK 0x00000001
41: #define SCLKA_3684_MHZ 0x00000000
42:
43: /* Read register 0 */
44: #define RR0_RXAVAIL 0x01 /* Rx Character Available */
45: #define RR0_ZERO_COUNT 0x02 /* Zero count (timer) */
46: #define RR0_TXEMPTY 0x04 /* Tx Buffer Empty */
47: #define RR0_DCD 0x08 /* DCD changed */
48: #define RR0_SYNC_HUNT 0x10 /* Sync hunt mode */
49: #define RR0_CTS 0x20 /* CTS changed */
50: #define RR0_TXUNDER 0x40 /* Tx Underrun/EOM */
51: #define RR0_BREAK 0x80 /* Break/Abort */
52:
53: /* Read register 1 */
54: #define RR1_ALLSENT 0x01 /* All Sent */
55: #define RR1_RESCODE2 0x02 /* Residue Code 2 */
56: #define RR1_RESCODE1 0x04 /* Residue Code 1 */
57: #define RR1_RESCODE0 0x08 /* Residue Code 0 */
58: #define RR1_PARITY 0x10 /* Parity Error */
59: #define RR1_RXOVER 0x20 /* Rx Overrun Error */
60: #define RR1_FRAME 0x40 /* CRC/Framing Error */
61: #define RR1_EOF 0x80 /* End of Frame (SDLC) */
62:
63: /* Read/Write Register 2: 8 bits of interrupt vector
64: * Channel A unmodified, channel B is modified by current UART status */
65:
66: /* Read Register 3 -- ONLY CHANNEL A */
67: #define RR3_B_STATIP 0x01 /* Chanel B Ext/Status intr pending */
68: #define RR3_B_TXIP 0x02 /* Chanel B Tx interrupt pending */
69: #define RR3_B_RXIP 0x04 /* Chanel B Rx interrupt pending */
70: #define RR3_A_STATIP 0x08 /* Chanel A Ext/Status intr pending */
71: #define RR3_A_TXIP 0x10 /* Chanel A Tx interrupt pending */
72: #define RR3_A_RXIP 0x20 /* Chanel A Rx interrupt pending */
73:
74: #define RR3_A_IP (RR3_A_STATIP|RR3_A_TXIP|RR3_A_RXIP)
75: #define RR3_B_IP (RR3_B_STATIP|RR3_B_TXIP|RR3_B_RXIP)
76:
77: /* Read Register 8: same as data port (receive buffer) */
78:
79: /* Read Register 10 */
80: #define RR10_ONLOOP 0x02 /* On Loop */
81: #define RR10_LOOPSEND 0x10 /* Loop Sending */
82: #define RR10_MISS2 0x40 /* Two Clocks Missing */
83: #define RR10_MISS1 0x80 /* One Clock Missing */
84:
85: /* Read/Write Register 12/13 16 bits of time constant */
86:
87: /* Read/Write Register 15 */
88: #define RW15_ZEROCNTIE 0x02 /* Enable interrupt on timer zero */
89: #define RW15_DCDIE 0x08 /* Enable interrupt on DCD change */
90: #define RW15_SYNCIE 0x10 /* Enable interrupt on Sync Hunt */
91: #define RW15_CTSIE 0x20 /* Enable interrupt on CTS change */
92: #define RW15_TXUNDERIE 0x40 /* Enable interrupt on Tx Underrun/EOM*/
93: #define RW15_BREAKIE 0x80 /* Enable interrupt on Bread/Abort */
94:
95: /* Write register 0 */
96: #define WR0_REGMASK 0x0F /* Mask for register select */
97: #define WR0_RESET_STAT 0x10 /* Reset Ext/Status Interrupts */
98: #define WR0_ABORT 0x18 /* Send abort */
99: #define WR0_NEXTRXIE 0x20 /* Enable interrupt on next char Rx */
100: #define WR0_RESETTXPEND 0x28 /* Reset Pending Tx Interrupt */
101: #define WR0_RESET 0x30 /* Error Reset */
102: #define WR0_RESETIUS 0x38 /* Reset Interrupt Under Service */
103: #define WR0_RESETRXCRC 0x40 /* Reset Rx CRC Checker */
104: #define WR0_RESETTXCRC 0x80 /* Reset Rx CRC Generator */
105: #define WR0_RESETEOM 0xC0 /* Reset Underrun/EOM latch */
106:
107: /* Write register 1 */
108: #define WR1_EXTIE 0x01 /* External Interrupt Enable */
109: #define WR1_TXIE 0x02 /* Transmit Interrupt Enable */
110: #define WR1_PARSPEC 0x04 /* Parity is Special Condition */
111: #define WR1_RXFIRSTIE 0x08 /* Interrupt Enable on First Rx */
112: #define WR1_RXALLIE 0x10 /* Interrupt Enable on ALL Rx */
113: #define WR1_SPECIE 0x18 /* Interrupt on Special only */
114: #define WR1_REQRX 0x20 /* Request on Rx (else Tx) */
115: #define WR1_REQFUNC 0x40 /* DMA Request (else cpu wait) */
116: #define WR1_REQENABLE 0x80 /* Request/Wait enable */
117:
118: /* Read/Write register 2, interrupt vector */
119:
120: /* Write register 3 */
121: #define WR3_RXENABLE 0x01 /* Rx Enable */
122: #define WR3_SYNCINHIB 0x02 /* Sync Character Load Inhibit */
123: #define WR3_ADDRSRCH 0x04 /* Address search mode (SDLC) */
124: #define WR3_RXCRCENABLE 0x08 /* Rx CRC enable */
125: #define WR3_ENTERHUNT 0x10 /* Enter Hunt Mode */
126: #define WR3_AUTOENABLES 0x20 /* Auto Enables */
127: #define WR3_RX5 0x00 /* Rx 5 bit characters */
128: #define WR3_RX7 0x40 /* Rx 7 bit characters */
129: #define WR3_RX6 0x80 /* Rx 6 bit characters */
130: #define WR3_RX8 0xC0 /* Rx 8 bit characters */
131:
132: /* Write register 4 */
133: #define WR4_PARENABLE 0x01 /* Parity enable */
134: #define WR4_PAREVEN 0x02 /* Even parity */
135: #define WR4_STOP1 0x04 /* 1 stop bit */
136: #define WR4_STOP15 0x08 /* 1.5 stop bits */
137: #define WR4_STOP2 0x0C /* 2 stop bits */
138: #define WR4_SYNC8 0x00 /* 8 bit sync character */
139: #define WR4_SYNC16 0x10 /* 16 bit sync character */
140: #define WR4_SDLC 0x10 /* SDLC mode */
141: #define WR4_EXTSYNC 0x30 /* External sync */
142: #define WR4_X1CLOCK 0x00 /* x1 clock mode */
143: #define WR4_X16CLOCK 0x40 /* x16 clock mode */
144: #define WR4_X32CLOCK 0x80 /* x32 clock mode */
145: #define WR4_X64CLOCK 0xC0 /* x64 clock mode */
146:
147: /* Write register 5 */
148: #define WR5_TXCRCENABLE 0x01 /* Enable CRC on Rx */
149: #define WR5_RTS 0x02 /* RTS */
150: #define WR5_CRC16 0x04 /* SDLC/CRC-16 */
151: #define WR5_TXENABLE 0x08 /* Enable transmitter */
152: #define WR5_BREAK 0x10 /* Send a break */
153: #define WR5_TX5 0x00 /* Tx 5 bit characters */
154: #define WR5_TX7 0x20 /* Tx 7 bit characters */
155: #define WR5_TX6 0x40 /* Tx 6 bit characters */
156: #define WR5_TX8 0x60 /* Tx 8 bit characters */
157: #define WR5_DTR 0x80 /* DTR */
158:
159: /* Write register 6 (Sync characters or SDLC address) */
160:
161: /* Write register 7 more sync/SDLC */
162:
163: /* Write register 8, same as data port, (Tx buffer) */
164:
165: /* Write register 9 -- ONLY 1, SHARED BETWEEN CHANNELS, ACCESSABLE FROM BOTH */
166: #define WR9_VIS 0x01 /* Vector Includes Status */
167: #define WR9_NV 0x02 /* No Vector (don't respond to IACK) */
168: #define WR9_DLC 0x04 /* Disable Lower Chain */
169: #define WR9_MIE 0x08 /* Master Interrupt Enable */
170: #define WR9_STATHIGH 0x10 /* Status high */
171: #define WR9_RESETB 0x40 /* Reset channel B */
172: #define WR9_RESETA 0x80 /* Reset channel A */
173: #define WR9_RESETHARD 0xC0 /* Hardware reset */
174:
175: /* Write register 10 */
176: #define WR10_SYNC6 0x01 /* 6 bit sync */
177: #define WR10_LOOP 0x02 /* Loop mode */
178: #define WR10_ABORTUNDER 0x04 /* Abort on Underrun */
179: #define WR10_MARKIDLE 0x08 /* Mark Idle */
180: #define WR10_POLLACT 0x10 /* Go active on poll */
181: #define WR10_NRZ 0x00 /* NRZ */
182: #define WR10_NRZI 0x20 /* NRZI */
183: #define WR10_FM1 0x40 /* FM (Transition = 1) */
184: #define WR10_FM0 0x60 /* FM (Transition = 0) */
185: #define WR10_PRESET1 0x80 /* CRC Preset 1 */
186:
187: /* Write register 11 */
188: #define WR11_XTAL 0x00 /* TRxC Out = XTAL Output */
189: #define WR11_TXCLOCK 0x01 /* TRxC Out = Transmit clock */
190: #define WR11_BRGEN 0x02 /* TRxC Out = BR Generator Output */
191: #define WR11_DPLL 0x03 /* TRxC Out = DPLL Output */
192: #define WR11_TRXCOUTEN 0x04 /* Enable TRxC as output */
193: #define WR11_TXCLKRTXC 0x00 /* Tx clock = RTxC pin */
194: #define WR11_TXCLKTRXC 0x08 /* Tx clock = TRxC pin */
195: #define WR11_TXCLKBRGEN 0x10 /* Tx clock = BR Generator Output */
196: #define WR11_TXCLKDPLL 0x18 /* Tx clock = DPLL Output */
197: #define WR11_RXCLKRTXC 0x00 /* Rx clock = RTxC pin */
198: #define WR11_RXCLKTRXC 0x20 /* Rx clock = TRxC pin */
199: #define WR11_RXCLKBRGEN 0x40 /* Rx clock = BR Generator Output */
200: #define WR11_RXCLKDPLL 0x60 /* Rx clock = DPLL Output */
201: #define WR11_RTXCXTAL 0x80 /* Crystal RTxC in (else TTL) */
202:
203: /* Read/Write register 12/13 Time constant */
204:
205: /* Write register 14 */
206: #define WR14_BRENABLE 0x01 /* BR Generator Enable */
207: #define WR14_BRPCLK 0x02 /* BR Generator CLK from PCLK */
208: #define WR14_DTSREQ 0x04 /* DTR low is DMA request */
209: #define WR14_AUTOECHO 0x08 /* Auto echo */
210: #define WR14_LOOPBACK 0x10 /* Local loopback */
211: #define WR14_SEARCH 0x20 /* Enter Search mode */
212: #define WR14_RESET 0x40 /* Reset Missing Clock */
213: #define WR14_DPLLDISABLE 0x60 /* Disable DPLL */
214: #define WR14_SRCBR 0x80 /* Set DPLL CLK Src = BR Generator */
215: #define WR14_SRCRTXC 0xA0 /* Set DPLL CLK Src = RTxC */
216: #define WR14_FM 0xC0 /* Set FM mode */
217: #define WR14_NRZI 0xE0 /* Set NRZI mode */
218:
219: /* Clocks available to SCC */
220: #define PCLK_HZ 3684000
221: #define RTXC_HZ 4000000
222:
223:
224: /* Functions */
1.1.1.2 ! root 225: void SCC_ControlA_Read(void);
! 226: void SCC_ControlA_Write(void);
! 227: void SCC_ControlB_Read(void);
! 228: void SCC_ControlB_Write(void);
! 229: void SCC_DataA_Read(void);
! 230: void SCC_DataA_Write(void);
! 231: void SCC_DataB_Read(void);
! 232: void SCC_DataB_Write(void);
1.1 root 233:
1.1.1.2 ! root 234: void SCC_Reset(Uint8 mode);
! 235:
! 236:
! 237: /* SCC DMA buffer */
! 238: Uint8 scc_buf[1];
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