--- previous/src/includes/sysReg.h	2018/04/24 19:28:10	1.1
+++ previous/src/includes/sysReg.h	2018/04/24 19:30:36	1.1.1.2
@@ -1,6 +1,6 @@
 /* NeXT system registers emulation */
 
-
+/* Interrupts */
 #define INT_SOFT1       0x00000001  // level 1
 #define INT_SOFT2       0x00000002  // level 2
 #define INT_POWER       0x00000004  // level 3
@@ -34,10 +34,22 @@
 #define INT_PFAIL       0x40000000  // level 7
 #define INT_NMI         0x80000000
 
-#define SET_INT         0x01
-#define RELEASE_INT     0x00
+/* Interrupt Level Masks */
+#define INT_L7_MASK     0xC0000000
+#define INT_L6_MASK     0x3FFC0000
+#define INT_L5_MASK     0x00038000
+#define INT_L4_MASK     0x00004000
+#define INT_L3_MASK     0x00003FFC
+#define INT_L2_MASK     0x00000002
+#define INT_L1_MASK     0x00000001
+
+#define SET_INT         1
+#define RELEASE_INT     0
 
-Uint8 read_rtc_ram(Uint8 position);
+void set_interrupt(Uint32 intr, Uint8 state);
+int get_interrupt_level(void);
+
+void set_dsp_interrupt(Uint8 state);
 
 void SID_Read(void);
 
@@ -47,10 +59,6 @@ void SCR1_Read1(void);
 void SCR1_Read2(void);
 void SCR1_Read3(void);
 
-void TurboSCR1_Reset(void);
-void TurboSCR1_Read0(void);
-void TurboSCR1_Read2(void);
-
 void SCR2_Read0(void);
 void SCR2_Write0(void);
 void SCR2_Read1(void);
@@ -65,7 +73,7 @@ void IntRegStatWrite(void);
 void IntRegMaskRead(void);
 void IntRegMaskWrite(void);
 
-void Hardclock_InterruptHandler ( void );
+void Hardclock_InterruptHandler(void);
 void HardclockRead0(void);
 void HardclockRead1(void);
 
@@ -75,7 +83,7 @@ void HardclockWrite1(void);
 void HardclockWriteCSR(void);
 void HardclockReadCSR(void);
 
-void nvram_init(void);
-void rtc_checksum(int force);
+void System_Timer_Read(void);
 
-void set_interrupt(Uint32, Uint8);
+void ColorVideo_CMD_Write(void);
+void color_video_interrupt(void);