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Annotation of previous/src/ioMemTabNEXT.c, revision 1.1

1.1     ! root        1: /*
        !             2:   Previous - ioMemTabNEXT.c
        !             3: 
        !             4:   This file is distributed under the GNU Public License, version 2 or at
        !             5:   your option any later version. Read the file gpl.txt for details.
        !             6: 
        !             7:   Table with hardware IO handlers for the NEXT.
        !             8: */
        !             9: 
        !            10: 
        !            11: const char IoMemTabST_fileid[] = "Previous ioMemTabST.c : " __DATE__ " " __TIME__;
        !            12: 
        !            13: #include "main.h"
        !            14: #include "ioMem.h"
        !            15: #include "ioMemTables.h"
        !            16: #include "video.h"
        !            17: #include "configuration.h"
        !            18: #include "sysdeps.h"
        !            19: #include "m68000.h"
        !            20: 
        !            21: #define IO_SEG_MASK    0x1FFFF
        !            22: /*
        !            23:  *
        !            24:  */
        !            25: static Uint8 scr2_0=0;
        !            26: static Uint8 scr2_1=0;
        !            27: static Uint8 scr2_2=0;
        !            28: static Uint8 scr2_3=0;
        !            29: 
        !            30: static Uint32 intStat=0x04;
        !            31: static Uint32 intMask=0x00000000;
        !            32: 
        !            33: void SCR2_Write0(void)
        !            34: {      
        !            35: //     Log_Printf(LOG_WARN,"SCR2 write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress,IoMem[IoAccessCurrentAddress & IO_SEG_MASK],m68k_getpc());
        !            36:        scr2_0=IoMem[IoAccessCurrentAddress & 0x1FFFF];
        !            37: }
        !            38: 
        !            39: void SCR2_Read0(void)
        !            40: {
        !            41: //     Log_Printf(LOG_WARN,"SCR2 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
        !            42:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_0;
        !            43: }
        !            44: 
        !            45: void SCR2_Write1(void)
        !            46: {      
        !            47: //     Log_Printf(LOG_WARN,"SCR2 write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress,IoMem[IoAccessCurrentAddress & IO_SEG_MASK],m68k_getpc());
        !            48:        scr2_1=IoMem[IoAccessCurrentAddress & 0x1FFFF];
        !            49: }
        !            50: 
        !            51: void SCR2_Read1(void)
        !            52: {
        !            53: //     Log_Printf(LOG_WARN,"SCR2 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
        !            54:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_1;
        !            55: }
        !            56: 
        !            57: 
        !            58: #define SCR2_RTDATA            0x04
        !            59: #define SCR2_RTCLK             0x02
        !            60: #define SCR2_RTCE              0x01
        !            61: 
        !            62: #define SCR2_LED               0x01
        !            63: #define SCR2_ROM               0x80
        !            64: 
        !            65: 
        !            66: // file mon/nvram.h
        !            67: // struct nvram_info {
        !            68: // #define     NI_RESET        9
        !            69: //     u_int   ni_reset : 4,
        !            70: // #define     SCC_ALT_CONS    0x08000000
        !            71: //             ni_alt_cons : 1,
        !            72: // #define     ALLOW_EJECT     0x04000000
        !            73: //             ni_allow_eject : 1,
        !            74: //             ni_vol_r : 6,
        !            75: //             ni_brightness : 6,
        !            76: // #define     HW_PWD  0x6
        !            77: //             ni_hw_pwd : 4,
        !            78: //             ni_vol_l : 6,
        !            79: //             ni_spkren : 1,
        !            80: //             ni_lowpass : 1,
        !            81: // #define     BOOT_ANY        0x00000002
        !            82: //             ni_boot_any : 1,
        !            83: // #define     ANY_CMD         0x00000001
        !            84: //             ni_any_cmd : 1;
        !            85: // #define     NVRAM_HW_PASSWD 6
        !            86: //     u_char ni_ep[NVRAM_HW_PASSWD];
        !            87: // #define     ni_enetaddr     ni_ep
        !            88: // #define     ni_hw_passwd    ni_ep
        !            89: //     u_short ni_simm;                /* 4 SIMMs, 4 bits per SIMM */
        !            90: //     char ni_adobe[2];
        !            91: //     u_char ni_pot[3];
        !            92: //     u_char  ni_new_clock_chip : 1,
        !            93: //             ni_auto_poweron : 1,
        !            94: //             ni_use_console_slot : 1,        /* Console slot was set by user. */
        !            95: //             ni_console_slot : 2,            /* Preferred console dev slot>>1 */
        !            96: //             ni_use_parity_mem : 1,  /* Use parity RAM if available? */
        !            97: //             : 2;
        !            98: // #define     NVRAM_BOOTCMD   12
        !            99: //     char ni_bootcmd[NVRAM_BOOTCMD];
        !           100: //     u_short ni_cksum;
        !           101: // };
        !           102: 
        !           103: // #define     N_brightness    0
        !           104: // #define     N_volume_l      1
        !           105: // #define     N_volume_r      2
        !           106: 
        !           107: /* nominal values during self test */
        !           108: // #define     BRIGHT_NOM      20
        !           109: // #define     VOL_NOM         0
        !           110: 
        !           111: /* bits in ni_pot[0] */
        !           112: // #define POT_ON                      0x01
        !           113: // #define EXTENDED_POT                0x02
        !           114: // #define LOOP_POT            0x04
        !           115: // #define     VERBOSE_POT             0x08
        !           116: // #define     TEST_DRAM_POT           0x10
        !           117: // #define     BOOT_POT                0x20
        !           118: // #define     TEST_MONITOR_POT        0x40
        !           119: 
        !           120: // Uint8 rtc_ram[32];
        !           121: 
        !           122: Uint8 rtc_ram[32]={
        !           123: 0x94,0x0f,0x40,0x00,0x00,0x00,0x00,0x00,
        !           124: 0x00,0x00,0xfb,0x6d,0x00,0x00,0x7B,0x00,
        !           125: 0x00,0x00,0x65,0x6e,0x00,0x00,0x00,0x00,
        !           126: 0x00,0x00,0x00,0x00,0x00,0x00,0x50,0x13
        !           127: };
        !           128: 
        !           129: static char rtc_ram_info[1024];
        !           130: char * get_rtc_ram_info(void) {
        !           131:        char buf[256];
        !           132:        int sum;
        !           133:        int i;
        !           134:        int ni_vol_l,ni_vol_r,ni_brightness;
        !           135:        int ni_hw_pwd,ni_spkren,ni_lowpass;
        !           136:        sprintf(buf,"Rtc info:\n");
        !           137:        strcpy(rtc_ram_info,buf);
        !           138: 
        !           139: // struct nvram_info {
        !           140: // #define     NI_RESET        9
        !           141: //     u_int   ni_reset : 4,
        !           142: 
        !           143:        sprintf(buf,"RTC RESET:x%1X ",rtc_ram[0]>>4);
        !           144:        strcat(rtc_ram_info,buf);       
        !           145: 
        !           146: // #define     SCC_ALT_CONS    0x08000000
        !           147: //             ni_alt_cons : 1,
        !           148:        if (rtc_ram[0]&0x08) strcat(rtc_ram_info,"ALT_CONS ");
        !           149: // #define     ALLOW_EJECT     0x04000000
        !           150: //             ni_allow_eject : 1,
        !           151:        if (rtc_ram[0]&0x04) strcat(rtc_ram_info,"ALLOW_EJECT ");
        !           152: //             ni_vol_r : 6,
        !           153: //             ni_brightness : 6,
        !           154: // #define     HW_PWD  0x6
        !           155: //             ni_hw_pwd : 4,
        !           156: //             ni_vol_l : 6,
        !           157: //             ni_spkren : 1,
        !           158: //             ni_lowpass : 1,
        !           159: // #define     BOOT_ANY        0x00000002
        !           160: //             ni_boot_any : 1,
        !           161: // #define     ANY_CMD         0x00000001      
        !           162: //             ni_any_cmd : 1;
        !           163: 
        !           164:        ni_vol_r=(((rtc_ram[0]&0x3)<<4)|((rtc_ram[1]&0xF0)>>4));
        !           165:        ni_brightness=(((rtc_ram[1]&0xF)<<2)|((rtc_ram[2]&0xC0)>>6));
        !           166:        ni_vol_l=((rtc_ram[2]&0x3F)<<2);
        !           167:        ni_hw_pwd=(rtc_ram[3]&0xF0)>>4;
        !           168:        sprintf(buf,"VOL_R:x%1X BRIGHT:x%1X HWPWD:x%1X VOL_L:x%1X",ni_vol_r,ni_brightness,ni_vol_l,ni_hw_pwd);
        !           169:        strcat(rtc_ram_info,buf);       
        !           170: 
        !           171:        if (rtc_ram[3]&0x08) strcat(rtc_ram_info,"SPK_ENABLE ");
        !           172:        if (rtc_ram[3]&0x04) strcat(rtc_ram_info,"LOW_PASS ");
        !           173:        if (rtc_ram[3]&0x02) strcat(rtc_ram_info,"BOOT_ANY ");
        !           174:        if (rtc_ram[3]&0x01) strcat(rtc_ram_info,"ANY_CMD ");
        !           175:        
        !           176:        
        !           177: 
        !           178: // #define     NVRAM_HW_PASSWD 6
        !           179: //     u_char ni_ep[NVRAM_HW_PASSWD];
        !           180: 
        !           181:        sprintf(buf,"NVRAM_HW_PASSWD:%2X %2X %2X %2X %2X %2X ",rtc_ram[4],rtc_ram[5],rtc_ram[6],rtc_ram[7],rtc_ram[8],rtc_ram[9]);
        !           182:        strcat(rtc_ram_info,buf);       
        !           183: // #define     ni_enetaddr     ni_ep
        !           184: // #define     ni_hw_passwd    ni_ep
        !           185: //     u_short ni_simm;                /* 4 SIMMs, 4 bits per SIMM */
        !           186:        sprintf(buf,"SIMM:%1X %1X %1X %1X ",rtc_ram[10]>>4,rtc_ram[10]&0x0F,rtc_ram[11]>>4,rtc_ram[11]&0x0F);
        !           187:        strcat(rtc_ram_info,buf);
        !           188: 
        !           189: 
        !           190: //     char ni_adobe[2];
        !           191:        sprintf(buf,"ADOBE:%2X %2X ",rtc_ram[12],rtc_ram[13]);
        !           192:        strcat(rtc_ram_info,buf);
        !           193: 
        !           194: //     u_char ni_pot[3];
        !           195:        sprintf(buf,"POT:%2X %2X %2X ",rtc_ram[14],rtc_ram[15],rtc_ram[16]);
        !           196:        strcat(rtc_ram_info,buf);
        !           197: 
        !           198: //     u_char  ni_new_clock_chip : 1,
        !           199: //             ni_auto_poweron : 1,
        !           200: //             ni_use_console_slot : 1,        /* Console slot was set by user. */
        !           201: //             ni_console_slot : 2,            /* Preferred console dev slot>>1 */
        !           202: //             ni_use_parity_mem : 1,  /* Use parity RAM if available? */
        !           203: //             : 2;
        !           204:        if (rtc_ram[17]&0x80) strcat(rtc_ram_info,"NEW_CLOCK_CHIP ");
        !           205:        if (rtc_ram[17]&0x40) strcat(rtc_ram_info,"AUTO_POWERON ");
        !           206:        if (rtc_ram[17]&0x20) strcat(rtc_ram_info,"CONSOLE_SLOT ");
        !           207: 
        !           208:        sprintf(buf,"console_slot:%X ",(rtc_ram[17]&0x18)>>3);
        !           209:        strcat(rtc_ram_info,buf);
        !           210: 
        !           211:        if (rtc_ram[17]&0x04) strcat(rtc_ram_info,"USE_PARITY ");
        !           212: 
        !           213: 
        !           214:        strcat(rtc_ram_info,"boot_command:");
        !           215:        for (i=0;i<12;i++) {
        !           216:                if ((rtc_ram[18+i]>=0x20) && (rtc_ram[18+i]<=0x7F)) {
        !           217:                        sprintf(buf,"%c",rtc_ram[18+i]);
        !           218:                        strcat(rtc_ram_info,buf);
        !           219:                }
        !           220:        }
        !           221: 
        !           222:        strcat(rtc_ram_info," ");
        !           223:        sprintf(buf,"CKSUM:%2X %2X ",rtc_ram[30],rtc_ram[31]);
        !           224:        strcat(rtc_ram_info,buf);
        !           225: 
        !           226: 
        !           227:        sum=0;
        !           228:        for (i=0;i<30;i+=2) {
        !           229:                sum+=(rtc_ram[i]<<8)|(rtc_ram[i+1]);
        !           230:                if (sum>=0x10000) { sum-=0x10000;
        !           231:                        sum+=1;
        !           232:                }
        !           233:        }
        !           234: 
        !           235:        sum=0xFFFF-sum;
        !           236: 
        !           237:        sprintf(buf,"CALC_CKSUM:%04X ",sum&0xFFFF);
        !           238:        strcat(rtc_ram_info,buf);
        !           239: 
        !           240: // #define     NVRAM_BOOTCMD   12
        !           241: //     char ni_bootcmd[NVRAM_BOOTCMD];
        !           242: //     u_short ni_cksum;
        !           243: // };
        !           244: 
        !           245:        return rtc_ram_info;
        !           246: }
        !           247: 
        !           248: void SCR2_Write2(void)
        !           249: {      
        !           250:        static int phase=0;
        !           251:        static Uint8 rtc_command=0;
        !           252:        static Uint8 rtc_value=0;
        !           253:        static Uint8 rtc_return=0;
        !           254:        static Uint8 rtc_status=0x90;   // FTU at startup 0x90 for MCS1850
        !           255: 
        !           256:        Uint8 old_scr2_2=scr2_2;
        !           257: //     Log_Printf(LOG_WARN,"SCR2 write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress,IoMem[IoAccessCurrentAddress & IO_SEG_MASK],m68k_getpc());
        !           258:        scr2_2=IoMem[IoAccessCurrentAddress & 0x1FFFF];
        !           259: 
        !           260: /*
        !           261:        if ((old_scr2_2&SCR2_RTCE)!=(scr2_2&SCR2_RTCE))
        !           262:                Log_Printf(LOG_WARN,"SCR2 RTCE change at $%08x val=%x PC=$%08x\n",
        !           263:                           IoAccessCurrentAddress,scr2_2&SCR2_RTCE,m68k_getpc());
        !           264: 
        !           265:        if ((old_scr2_2&SCR2_RTCLK)!=(scr2_2&SCR2_RTCLK))
        !           266:                Log_Printf(LOG_WARN,"SCR2 RTCLK change at $%08x val=%x PC=$%08x\n",
        !           267:                           IoAccessCurrentAddress,scr2_2&SCR2_RTCLK,m68k_getpc());
        !           268: 
        !           269:        if ((old_scr2_2&SCR2_RTDATA)!=(scr2_2&SCR2_RTDATA))
        !           270:                Log_Printf(LOG_WARN,"SCR2 RTDATA change at $%08x val=%x PC=$%08x\n",
        !           271:                           IoAccessCurrentAddress,scr2_2&SCR2_RTDATA,m68k_getpc());
        !           272: */
        !           273: 
        !           274: // and now some primitive handling
        !           275: // treat only if CE is set to 1
        !           276:        if (scr2_2&SCR2_RTCE) {
        !           277:                        if (phase==-1) phase=0;
        !           278:                        // if we are in going down clock... do something
        !           279:                        if (((old_scr2_2&SCR2_RTCLK)!=(scr2_2&SCR2_RTCLK)) && ((scr2_2&SCR2_RTCLK)==0) ) {
        !           280:                                if (phase<8)
        !           281:                                        rtc_command=(rtc_command<<1)|((scr2_2&SCR2_RTDATA)?1:0);
        !           282:                                if ((phase>=8) && (phase<16)) {
        !           283:                                        rtc_value=(rtc_value<<1)|((scr2_2&SCR2_RTDATA)?1:0);
        !           284: 
        !           285:                                        // if we read RAM register, output RT_DATA bit
        !           286:                                        if (rtc_command<=0x1F) {
        !           287:                                                scr2_2=scr2_2&(~SCR2_RTDATA);
        !           288:                                                if (rtc_ram[rtc_command]&(0x80>>(phase-8)))
        !           289:                                                        scr2_2|=SCR2_RTDATA;
        !           290:                                                rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
        !           291:                                        }
        !           292:                                        // read the status 0x30
        !           293:                                        if (rtc_command==0x30) {
        !           294:                                                scr2_2=scr2_2&(~SCR2_RTDATA);
        !           295:                                                // for now status = 0x98 (new rtc + FTU)
        !           296:                                                if (rtc_status&(0x80>>(phase-8)))
        !           297:                                                        scr2_2|=SCR2_RTDATA;
        !           298:                                                rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
        !           299:                                        }
        !           300:                                        // read the status 0x31
        !           301:                                        if (rtc_command==0x31) {
        !           302:                                                scr2_2=scr2_2&(~SCR2_RTDATA);
        !           303:                                                // for now 0x00
        !           304:                                                if (0x00&(0x80>>(phase-8)))
        !           305:                                                        scr2_2|=SCR2_RTDATA;
        !           306:                                                rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
        !           307:                                        }
        !           308:                                        if ((rtc_command>=0x20) && (rtc_command<=0x2F)) {
        !           309:                                                scr2_2=scr2_2&(~SCR2_RTDATA);
        !           310:                                                // for now 0x00
        !           311:                                                if (0x00&(0x80>>(phase-8)))
        !           312:                                                        scr2_2|=SCR2_RTDATA;
        !           313:                                                rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
        !           314:                                        }
        !           315: 
        !           316:                                }
        !           317: 
        !           318:                                phase++;
        !           319:                                if (phase==16) {
        !           320:                                        Log_Printf(LOG_WARN,"SCR2 RTC command complete %x %x %x at PC=$%08x\n",
        !           321:                                                        rtc_command,rtc_value,rtc_return,m68k_getpc());
        !           322:                                        if ((rtc_command>=0x80) && (rtc_command<=0x9F))
        !           323:                                                rtc_ram[rtc_command-0x80]=rtc_value;
        !           324: 
        !           325:                                        // write to x30 register
        !           326:                                        if (rtc_command==0xB1) {
        !           327:                                                // clear FTU
        !           328:                                                if (rtc_value & 0x04) {
        !           329:                                                        rtc_status=rtc_status&(~0x18);
        !           330:                                                        intStat=intStat&(~0x04);
        !           331:                                                }
        !           332:                                        }
        !           333:                                }
        !           334:                        }
        !           335:        } else {
        !           336: // else end or abort
        !           337:                phase=-1;
        !           338:                rtc_command=0;
        !           339:                rtc_value=0;
        !           340:        }       
        !           341: 
        !           342: }
        !           343: 
        !           344: void SCR2_Read2(void)
        !           345: {
        !           346: //     Log_Printf(LOG_WARN,"SCR2 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
        !           347: //     IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_2 & (SCR2_RTDATA|SCR2_RTCLK|SCR2_RTCE)); // + data
        !           348:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_2;
        !           349: }
        !           350: 
        !           351: void SCR2_Write3(void)
        !           352: {      
        !           353:        Uint8 old_scr2_3=scr2_3;
        !           354: //     Log_Printf(LOG_WARN,"SCR2 write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress,IoMem[IoAccessCurrentAddress & IO_SEG_MASK],m68k_getpc());
        !           355:        scr2_3=IoMem[IoAccessCurrentAddress & 0x1FFFF];
        !           356:        if ((old_scr2_3&SCR2_ROM)!=(scr2_3&SCR2_ROM))
        !           357:                Log_Printf(LOG_WARN,"SCR2 ROM change at $%08x val=%x PC=$%08x\n",
        !           358:                           IoAccessCurrentAddress,scr2_3&SCR2_ROM,m68k_getpc());
        !           359:        if ((old_scr2_3&SCR2_LED)!=(scr2_3&SCR2_LED))
        !           360:                Log_Printf(LOG_WARN,"SCR2 LED change at $%08x val=%x PC=$%08x\n",
        !           361:                           IoAccessCurrentAddress,scr2_3&SCR2_LED,m68k_getpc());
        !           362: }
        !           363: 
        !           364: 
        !           365: void SCR2_Read3(void)
        !           366: {
        !           367: //     Log_Printf(LOG_WARN,"SCR2 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
        !           368:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_3;
        !           369: }
        !           370: 
        !           371: /*
        !           372: *
        !           373: bits 0:2 cpu speed 02 25MHz
        !           374: bits 3:4 mem speed 0 120ns
        !           375: bits 5:6 video mem speed 0 120ns
        !           376: bits 8:11 board revision 0
        !           377: bits 12:15 cpu type 30 : station non turbo rev 0
        !           378: bits 16:23 dma type 01
        !           379: bits 24:27 reserved 0
        !           380: bits 28:31 slot id 0
        !           381: 
        !           382:                        
        !           383: 0000 xxxxxxxxxx 0001  0001 xx 10 011
        !           384: 
        !           385: 00 00 11 2E
        !           386: */
        !           387: 
        !           388: 
        !           389: void SCR1_Read0(void)
        !           390: {
        !           391:        Log_Printf(LOG_WARN,"SCR1 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
        !           392:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=0x00; 
        !           393: }
        !           394: void SCR1_Read1(void)
        !           395: {
        !           396:        Log_Printf(LOG_WARN,"SCR1 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
        !           397:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=0x01; // dma rev
        !           398: }
        !           399: void SCR1_Read2(void)
        !           400: {
        !           401:        Log_Printf(LOG_WARN,"SCR1 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
        !           402:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=0x20; // cpu type + rev
        !           403: }
        !           404: void SCR1_Read3(void)
        !           405: {
        !           406:        Log_Printf(LOG_WARN,"SCR1 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
        !           407:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=0x02; // speed + memory
        !           408: }
        !           409: 
        !           410: void IntRegStatRead(void) {
        !           411:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=intStat;
        !           412: }
        !           413: 
        !           414: void IntRegStatWrite(void) {
        !           415:        intStat=IoMem[IoAccessCurrentAddress & 0x1FFFF];
        !           416: }
        !           417: 
        !           418: void IntRegMaskRead(void) {
        !           419:        IoMem[IoAccessCurrentAddress & 0x1FFFF]=intMask;
        !           420: }
        !           421: 
        !           422: void IntRegMaskWrite(void) {
        !           423:        intMask=IoMem[IoAccessCurrentAddress & 0x1FFFF];
        !           424: }
        !           425: 
        !           426: 
        !           427: /*-----------------------------------------------------------------------*/
        !           428: /*
        !           429:   List of functions to handle read/write hardware interceptions.
        !           430: */
        !           431: const INTERCEPT_ACCESS_FUNC IoMemTable_NEXT[] =
        !           432: {
        !           433:        { 0x02000150, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
        !           434:        { 0x02004150, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           435:        { 0x02004154, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           436:        { 0x02004158, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           437:        { 0x0200415c, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           438:        { 0x02004188, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           439:        { 0x02006000, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           440:        { 0x02006001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           441:        { 0x02006002, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           442:        { 0x02006003, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           443:        { 0x02006004, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           444:        { 0x02006005, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           445:        { 0x02006006, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           446:        { 0x02006008, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           447:        { 0x02006009, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           448:        { 0x0200600a, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           449:        { 0x0200600b, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           450:        { 0x0200600a, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           451:        { 0x0200600b, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           452:        { 0x0200600c, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           453:        { 0x0200600d, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           454:        { 0x0200600e, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           455:        { 0x0200600f, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           456:        { 0x02006010, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           457:        { 0x02006011, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           458:        { 0x02006012, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           459:        { 0x02006013, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           460:        { 0x02006014, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           461:        { 0x02007000, SIZE_LONG, IntRegStatRead, IntRegStatWrite },
        !           462:        { 0x02007800, SIZE_BYTE, IntRegMaskRead, IntRegMaskWrite },
        !           463:        { 0x0200c000, SIZE_BYTE, SCR1_Read0, IoMem_WriteWithoutInterceptionButTrace },
        !           464:        { 0x0200c001, SIZE_BYTE, SCR1_Read1, IoMem_WriteWithoutInterceptionButTrace },
        !           465:        { 0x0200c002, SIZE_BYTE, SCR1_Read2, IoMem_WriteWithoutInterceptionButTrace },
        !           466:        { 0x0200c003, SIZE_BYTE, SCR1_Read3, IoMem_WriteWithoutInterceptionButTrace },
        !           467:        { 0x0200c800, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           468:        { 0x0200d000, SIZE_BYTE, SCR2_Read0, SCR2_Write0 },
        !           469:        { 0x0200d001, SIZE_BYTE, SCR2_Read1, SCR2_Write1 },
        !           470:        { 0x0200d002, SIZE_BYTE, SCR2_Read2, SCR2_Write2 },
        !           471:        { 0x0200d003, SIZE_BYTE, SCR2_Read3, SCR2_Write3 },
        !           472:        { 0x0200e001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           473:        { 0x0200e002, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           474:        { 0x0200e003, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           475:        { 0x0200e004, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           476:        { 0x0200e005, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           477:        { 0x0200e006, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
        !           478:        { 0x02010000, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           479:        { 0x02012004, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           480:        { 0x02012005, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           481:        { 0x02012007, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           482:        { 0x02014003, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           483:        { 0x02018000, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           484:        { 0x02018001, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           485:        { 0x02018004, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
        !           486:        { 0, 0, NULL, NULL }
        !           487: };

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