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1.1 root 1: /*
2: Previous - ioMemTabNEXT.c
3:
4: This file is distributed under the GNU Public License, version 2 or at
5: your option any later version. Read the file gpl.txt for details.
6:
7: Table with hardware IO handlers for the NEXT.
8: */
9:
10:
11: const char IoMemTabST_fileid[] = "Previous ioMemTabST.c : " __DATE__ " " __TIME__;
12:
13: #include "main.h"
14: #include "ioMem.h"
15: #include "ioMemTables.h"
16: #include "video.h"
17: #include "configuration.h"
18: #include "sysdeps.h"
19: #include "m68000.h"
1.1.1.3 ! root 20: #include "keymap.h"
1.1 root 21:
22: #define IO_SEG_MASK 0x1FFFF
23: /*
24: *
25: */
26: static Uint8 scr2_0=0;
27: static Uint8 scr2_1=0;
28: static Uint8 scr2_2=0;
29: static Uint8 scr2_3=0;
30:
31: static Uint32 intStat=0x04;
32: static Uint32 intMask=0x00000000;
33:
34: void SCR2_Write0(void)
35: {
36: // Log_Printf(LOG_WARN,"SCR2 write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress,IoMem[IoAccessCurrentAddress & IO_SEG_MASK],m68k_getpc());
37: scr2_0=IoMem[IoAccessCurrentAddress & 0x1FFFF];
38: }
39:
40: void SCR2_Read0(void)
41: {
42: // Log_Printf(LOG_WARN,"SCR2 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
43: IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_0;
44: }
45:
46: void SCR2_Write1(void)
47: {
48: // Log_Printf(LOG_WARN,"SCR2 write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress,IoMem[IoAccessCurrentAddress & IO_SEG_MASK],m68k_getpc());
49: scr2_1=IoMem[IoAccessCurrentAddress & 0x1FFFF];
50: }
51:
52: void SCR2_Read1(void)
53: {
54: // Log_Printf(LOG_WARN,"SCR2 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
55: IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_1;
56: }
57:
58:
59: #define SCR2_RTDATA 0x04
60: #define SCR2_RTCLK 0x02
61: #define SCR2_RTCE 0x01
62:
63: #define SCR2_LED 0x01
64: #define SCR2_ROM 0x80
65:
66:
67: // file mon/nvram.h
68: // struct nvram_info {
69: // #define NI_RESET 9
70: // u_int ni_reset : 4,
71: // #define SCC_ALT_CONS 0x08000000
72: // ni_alt_cons : 1,
73: // #define ALLOW_EJECT 0x04000000
74: // ni_allow_eject : 1,
75: // ni_vol_r : 6,
76: // ni_brightness : 6,
77: // #define HW_PWD 0x6
78: // ni_hw_pwd : 4,
79: // ni_vol_l : 6,
80: // ni_spkren : 1,
81: // ni_lowpass : 1,
82: // #define BOOT_ANY 0x00000002
83: // ni_boot_any : 1,
84: // #define ANY_CMD 0x00000001
85: // ni_any_cmd : 1;
86: // #define NVRAM_HW_PASSWD 6
87: // u_char ni_ep[NVRAM_HW_PASSWD];
88: // #define ni_enetaddr ni_ep
89: // #define ni_hw_passwd ni_ep
90: // u_short ni_simm; /* 4 SIMMs, 4 bits per SIMM */
91: // char ni_adobe[2];
92: // u_char ni_pot[3];
93: // u_char ni_new_clock_chip : 1,
94: // ni_auto_poweron : 1,
95: // ni_use_console_slot : 1, /* Console slot was set by user. */
96: // ni_console_slot : 2, /* Preferred console dev slot>>1 */
97: // ni_use_parity_mem : 1, /* Use parity RAM if available? */
98: // : 2;
99: // #define NVRAM_BOOTCMD 12
100: // char ni_bootcmd[NVRAM_BOOTCMD];
101: // u_short ni_cksum;
102: // };
103:
104: // #define N_brightness 0
105: // #define N_volume_l 1
106: // #define N_volume_r 2
107:
108: /* nominal values during self test */
109: // #define BRIGHT_NOM 20
110: // #define VOL_NOM 0
111:
112: /* bits in ni_pot[0] */
113: // #define POT_ON 0x01
114: // #define EXTENDED_POT 0x02
115: // #define LOOP_POT 0x04
116: // #define VERBOSE_POT 0x08
117: // #define TEST_DRAM_POT 0x10
118: // #define BOOT_POT 0x20
119: // #define TEST_MONITOR_POT 0x40
120:
121: // Uint8 rtc_ram[32];
122:
1.1.1.3 ! root 123: Uint8 rtc_ram[32]={ // values from nextcomputers.org forums
1.1.1.2 root 124: 0x94,0x0f,0x40,0x03,0x00,0x00,0x00,0x00,
125: 0x00,0x00,0xfb,0x6d,0x00,0x00,0x4b,0x00,
126: 0x41,0x00,0x20,0x00,0x00,0x00,0x00,0x00,
127: 0x00,0x00,0x00,0x00,0x00,0x00,0x84,0x7e
1.1 root 128: };
129:
130: static char rtc_ram_info[1024];
131: char * get_rtc_ram_info(void) {
132: char buf[256];
133: int sum;
134: int i;
135: int ni_vol_l,ni_vol_r,ni_brightness;
136: int ni_hw_pwd,ni_spkren,ni_lowpass;
137: sprintf(buf,"Rtc info:\n");
138: strcpy(rtc_ram_info,buf);
139:
140: // struct nvram_info {
141: // #define NI_RESET 9
142: // u_int ni_reset : 4,
143:
144: sprintf(buf,"RTC RESET:x%1X ",rtc_ram[0]>>4);
145: strcat(rtc_ram_info,buf);
146:
147: // #define SCC_ALT_CONS 0x08000000
148: // ni_alt_cons : 1,
149: if (rtc_ram[0]&0x08) strcat(rtc_ram_info,"ALT_CONS ");
150: // #define ALLOW_EJECT 0x04000000
151: // ni_allow_eject : 1,
152: if (rtc_ram[0]&0x04) strcat(rtc_ram_info,"ALLOW_EJECT ");
153: // ni_vol_r : 6,
154: // ni_brightness : 6,
155: // #define HW_PWD 0x6
156: // ni_hw_pwd : 4,
157: // ni_vol_l : 6,
158: // ni_spkren : 1,
159: // ni_lowpass : 1,
160: // #define BOOT_ANY 0x00000002
161: // ni_boot_any : 1,
162: // #define ANY_CMD 0x00000001
163: // ni_any_cmd : 1;
164:
165: ni_vol_r=(((rtc_ram[0]&0x3)<<4)|((rtc_ram[1]&0xF0)>>4));
166: ni_brightness=(((rtc_ram[1]&0xF)<<2)|((rtc_ram[2]&0xC0)>>6));
167: ni_vol_l=((rtc_ram[2]&0x3F)<<2);
168: ni_hw_pwd=(rtc_ram[3]&0xF0)>>4;
169: sprintf(buf,"VOL_R:x%1X BRIGHT:x%1X HWPWD:x%1X VOL_L:x%1X",ni_vol_r,ni_brightness,ni_vol_l,ni_hw_pwd);
170: strcat(rtc_ram_info,buf);
171:
172: if (rtc_ram[3]&0x08) strcat(rtc_ram_info,"SPK_ENABLE ");
173: if (rtc_ram[3]&0x04) strcat(rtc_ram_info,"LOW_PASS ");
174: if (rtc_ram[3]&0x02) strcat(rtc_ram_info,"BOOT_ANY ");
175: if (rtc_ram[3]&0x01) strcat(rtc_ram_info,"ANY_CMD ");
176:
177:
178:
179: // #define NVRAM_HW_PASSWD 6
180: // u_char ni_ep[NVRAM_HW_PASSWD];
181:
182: sprintf(buf,"NVRAM_HW_PASSWD:%2X %2X %2X %2X %2X %2X ",rtc_ram[4],rtc_ram[5],rtc_ram[6],rtc_ram[7],rtc_ram[8],rtc_ram[9]);
183: strcat(rtc_ram_info,buf);
184: // #define ni_enetaddr ni_ep
185: // #define ni_hw_passwd ni_ep
186: // u_short ni_simm; /* 4 SIMMs, 4 bits per SIMM */
187: sprintf(buf,"SIMM:%1X %1X %1X %1X ",rtc_ram[10]>>4,rtc_ram[10]&0x0F,rtc_ram[11]>>4,rtc_ram[11]&0x0F);
188: strcat(rtc_ram_info,buf);
189:
190:
191: // char ni_adobe[2];
192: sprintf(buf,"ADOBE:%2X %2X ",rtc_ram[12],rtc_ram[13]);
193: strcat(rtc_ram_info,buf);
194:
195: // u_char ni_pot[3];
196: sprintf(buf,"POT:%2X %2X %2X ",rtc_ram[14],rtc_ram[15],rtc_ram[16]);
197: strcat(rtc_ram_info,buf);
198:
199: // u_char ni_new_clock_chip : 1,
200: // ni_auto_poweron : 1,
201: // ni_use_console_slot : 1, /* Console slot was set by user. */
202: // ni_console_slot : 2, /* Preferred console dev slot>>1 */
203: // ni_use_parity_mem : 1, /* Use parity RAM if available? */
204: // : 2;
205: if (rtc_ram[17]&0x80) strcat(rtc_ram_info,"NEW_CLOCK_CHIP ");
206: if (rtc_ram[17]&0x40) strcat(rtc_ram_info,"AUTO_POWERON ");
207: if (rtc_ram[17]&0x20) strcat(rtc_ram_info,"CONSOLE_SLOT ");
208:
209: sprintf(buf,"console_slot:%X ",(rtc_ram[17]&0x18)>>3);
210: strcat(rtc_ram_info,buf);
211:
212: if (rtc_ram[17]&0x04) strcat(rtc_ram_info,"USE_PARITY ");
213:
214:
215: strcat(rtc_ram_info,"boot_command:");
216: for (i=0;i<12;i++) {
217: if ((rtc_ram[18+i]>=0x20) && (rtc_ram[18+i]<=0x7F)) {
218: sprintf(buf,"%c",rtc_ram[18+i]);
219: strcat(rtc_ram_info,buf);
220: }
221: }
222:
223: strcat(rtc_ram_info," ");
224: sprintf(buf,"CKSUM:%2X %2X ",rtc_ram[30],rtc_ram[31]);
225: strcat(rtc_ram_info,buf);
226:
227:
228: sum=0;
229: for (i=0;i<30;i+=2) {
230: sum+=(rtc_ram[i]<<8)|(rtc_ram[i+1]);
231: if (sum>=0x10000) { sum-=0x10000;
232: sum+=1;
233: }
234: }
235:
236: sum=0xFFFF-sum;
237:
238: sprintf(buf,"CALC_CKSUM:%04X ",sum&0xFFFF);
239: strcat(rtc_ram_info,buf);
240:
241: // #define NVRAM_BOOTCMD 12
242: // char ni_bootcmd[NVRAM_BOOTCMD];
243: // u_short ni_cksum;
244: // };
245:
246: return rtc_ram_info;
247: }
248:
249: void SCR2_Write2(void)
250: {
251: static int phase=0;
252: static Uint8 rtc_command=0;
253: static Uint8 rtc_value=0;
254: static Uint8 rtc_return=0;
255: static Uint8 rtc_status=0x90; // FTU at startup 0x90 for MCS1850
256:
257: Uint8 old_scr2_2=scr2_2;
258: // Log_Printf(LOG_WARN,"SCR2 write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress,IoMem[IoAccessCurrentAddress & IO_SEG_MASK],m68k_getpc());
259: scr2_2=IoMem[IoAccessCurrentAddress & 0x1FFFF];
260:
261: /*
262: if ((old_scr2_2&SCR2_RTCE)!=(scr2_2&SCR2_RTCE))
263: Log_Printf(LOG_WARN,"SCR2 RTCE change at $%08x val=%x PC=$%08x\n",
264: IoAccessCurrentAddress,scr2_2&SCR2_RTCE,m68k_getpc());
265:
266: if ((old_scr2_2&SCR2_RTCLK)!=(scr2_2&SCR2_RTCLK))
267: Log_Printf(LOG_WARN,"SCR2 RTCLK change at $%08x val=%x PC=$%08x\n",
268: IoAccessCurrentAddress,scr2_2&SCR2_RTCLK,m68k_getpc());
269:
270: if ((old_scr2_2&SCR2_RTDATA)!=(scr2_2&SCR2_RTDATA))
271: Log_Printf(LOG_WARN,"SCR2 RTDATA change at $%08x val=%x PC=$%08x\n",
272: IoAccessCurrentAddress,scr2_2&SCR2_RTDATA,m68k_getpc());
273: */
274:
275: // and now some primitive handling
276: // treat only if CE is set to 1
277: if (scr2_2&SCR2_RTCE) {
278: if (phase==-1) phase=0;
279: // if we are in going down clock... do something
280: if (((old_scr2_2&SCR2_RTCLK)!=(scr2_2&SCR2_RTCLK)) && ((scr2_2&SCR2_RTCLK)==0) ) {
281: if (phase<8)
282: rtc_command=(rtc_command<<1)|((scr2_2&SCR2_RTDATA)?1:0);
283: if ((phase>=8) && (phase<16)) {
284: rtc_value=(rtc_value<<1)|((scr2_2&SCR2_RTDATA)?1:0);
285:
286: // if we read RAM register, output RT_DATA bit
287: if (rtc_command<=0x1F) {
288: scr2_2=scr2_2&(~SCR2_RTDATA);
289: if (rtc_ram[rtc_command]&(0x80>>(phase-8)))
290: scr2_2|=SCR2_RTDATA;
291: rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
292: }
293: // read the status 0x30
294: if (rtc_command==0x30) {
295: scr2_2=scr2_2&(~SCR2_RTDATA);
296: // for now status = 0x98 (new rtc + FTU)
297: if (rtc_status&(0x80>>(phase-8)))
298: scr2_2|=SCR2_RTDATA;
299: rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
300: }
301: // read the status 0x31
302: if (rtc_command==0x31) {
303: scr2_2=scr2_2&(~SCR2_RTDATA);
304: // for now 0x00
305: if (0x00&(0x80>>(phase-8)))
306: scr2_2|=SCR2_RTDATA;
307: rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
308: }
309: if ((rtc_command>=0x20) && (rtc_command<=0x2F)) {
310: scr2_2=scr2_2&(~SCR2_RTDATA);
311: // for now 0x00
312: if (0x00&(0x80>>(phase-8)))
313: scr2_2|=SCR2_RTDATA;
314: rtc_return=(rtc_return<<1)|((scr2_2&SCR2_RTDATA)?1:0);
315: }
316:
317: }
318:
319: phase++;
320: if (phase==16) {
321: Log_Printf(LOG_WARN,"SCR2 RTC command complete %x %x %x at PC=$%08x\n",
322: rtc_command,rtc_value,rtc_return,m68k_getpc());
323: if ((rtc_command>=0x80) && (rtc_command<=0x9F))
324: rtc_ram[rtc_command-0x80]=rtc_value;
325:
326: // write to x30 register
327: if (rtc_command==0xB1) {
328: // clear FTU
329: if (rtc_value & 0x04) {
330: rtc_status=rtc_status&(~0x18);
331: intStat=intStat&(~0x04);
332: }
333: }
334: }
335: }
336: } else {
337: // else end or abort
338: phase=-1;
339: rtc_command=0;
340: rtc_value=0;
341: }
342:
343: }
344:
345: void SCR2_Read2(void)
346: {
347: // Log_Printf(LOG_WARN,"SCR2 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
348: // IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_2 & (SCR2_RTDATA|SCR2_RTCLK|SCR2_RTCE)); // + data
349: IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_2;
350: }
351:
352: void SCR2_Write3(void)
353: {
354: Uint8 old_scr2_3=scr2_3;
355: // Log_Printf(LOG_WARN,"SCR2 write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress,IoMem[IoAccessCurrentAddress & IO_SEG_MASK],m68k_getpc());
356: scr2_3=IoMem[IoAccessCurrentAddress & 0x1FFFF];
357: if ((old_scr2_3&SCR2_ROM)!=(scr2_3&SCR2_ROM))
358: Log_Printf(LOG_WARN,"SCR2 ROM change at $%08x val=%x PC=$%08x\n",
359: IoAccessCurrentAddress,scr2_3&SCR2_ROM,m68k_getpc());
360: if ((old_scr2_3&SCR2_LED)!=(scr2_3&SCR2_LED))
361: Log_Printf(LOG_WARN,"SCR2 LED change at $%08x val=%x PC=$%08x\n",
362: IoAccessCurrentAddress,scr2_3&SCR2_LED,m68k_getpc());
363: }
364:
365:
366: void SCR2_Read3(void)
367: {
368: // Log_Printf(LOG_WARN,"SCR2 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
369: IoMem[IoAccessCurrentAddress & 0x1FFFF]=scr2_3;
370: }
371:
372: /*
373: *
1.1.1.2 root 374: bits 0:1 cpu speed; 0 = 40 MHz, 1 = 20 MHz, 2 = 25MHz, 3 = 33 MHz (meaningless on color Slab)
375: bits 2:3 reserved: 0
376: bits 4:5 mem speed; 0 = 120ns, 1 = 100ns, 2 = 80ns, 3 = 60ns (meaningless on color Slab)
377: bits 6:7 video mem speed; 0 = 120ns, 1 = 100ns, 2 = 80ns, 3 = 60ns (meaningless on color Slab)
378: bits 8:11 board revision; for 030 Cube: 0 = DCD input inverted, 1 = DCD polarity fixed, 2 = must disable DSP mem before reset; for all other systems: 0
379: bits 12:15 cpu type; 0 = Cube 030, 1 = mono Slab, 2 = Cube 040, 3 = color Slab
380: bits 16:23 dma rev: 1
381: bits 24:27 reserved: 0
382: bits 28:31 slot ID: 0
383:
384:
385: for Cube 040:
386: 0000 0000 0000 0001 0011 0000 0101 0011
387: 00 01 20 52
388:
389: for Cube 030:
390: 0000 0000 0000 0001 0000 0001 0101 0011
391: 00 01 01 52
1.1 root 392: */
393:
394:
395: void SCR1_Read0(void)
396: {
397: Log_Printf(LOG_WARN,"SCR1 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
1.1.1.2 root 398: IoMem[IoAccessCurrentAddress & 0x1FFFF]=0x00; // slot ID 0
1.1 root 399: }
400: void SCR1_Read1(void)
401: {
402: Log_Printf(LOG_WARN,"SCR1 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
1.1.1.2 root 403: IoMem[IoAccessCurrentAddress & 0x1FFFF]=0x01; // dma rev 1
1.1 root 404: }
405: void SCR1_Read2(void)
406: {
407: Log_Printf(LOG_WARN,"SCR1 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
1.1.1.2 root 408: if(ConfigureParams.System.nCpuLevel == 3)
409: IoMem[IoAccessCurrentAddress & 0x1FFFF]=0x01; // Cube 030, board rev 1
410: else
411: IoMem[IoAccessCurrentAddress & 0x1FFFF]=0x20; // Cube 040, board rev 0
1.1 root 412: }
413: void SCR1_Read3(void)
414: {
415: Log_Printf(LOG_WARN,"SCR1 read at $%08x PC=$%08x\n", IoAccessCurrentAddress,m68k_getpc());
1.1.1.2 root 416: IoMem[IoAccessCurrentAddress & 0x1FFFF]=0x52; // vmem speed 100ns, mem speed 100ns, cpu speed 25 MHz
1.1 root 417: }
418:
419: void IntRegStatRead(void) {
420: IoMem[IoAccessCurrentAddress & 0x1FFFF]=intStat;
421: }
422:
423: void IntRegStatWrite(void) {
424: intStat=IoMem[IoAccessCurrentAddress & 0x1FFFF];
425: }
426:
427: void IntRegMaskRead(void) {
428: IoMem[IoAccessCurrentAddress & 0x1FFFF]=intMask;
429: }
430:
431: void IntRegMaskWrite(void) {
432: intMask=IoMem[IoAccessCurrentAddress & 0x1FFFF];
433: }
434:
435:
436: /*-----------------------------------------------------------------------*/
437: /*
438: List of functions to handle read/write hardware interceptions.
439: */
440: const INTERCEPT_ACCESS_FUNC IoMemTable_NEXT[] =
441: {
442: { 0x02000150, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
443: { 0x02004150, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
444: { 0x02004154, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
445: { 0x02004158, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
446: { 0x0200415c, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
447: { 0x02004188, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
448: { 0x02006000, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
449: { 0x02006001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
450: { 0x02006002, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
451: { 0x02006003, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
452: { 0x02006004, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
453: { 0x02006005, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
454: { 0x02006006, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
455: { 0x02006008, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
456: { 0x02006009, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
457: { 0x0200600a, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
458: { 0x0200600b, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
459: { 0x0200600a, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
460: { 0x0200600b, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
461: { 0x0200600c, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
462: { 0x0200600d, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
463: { 0x0200600e, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
464: { 0x0200600f, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
465: { 0x02006010, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
466: { 0x02006011, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
467: { 0x02006012, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
468: { 0x02006013, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
469: { 0x02006014, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
470: { 0x02007000, SIZE_LONG, IntRegStatRead, IntRegStatWrite },
471: { 0x02007800, SIZE_BYTE, IntRegMaskRead, IntRegMaskWrite },
472: { 0x0200c000, SIZE_BYTE, SCR1_Read0, IoMem_WriteWithoutInterceptionButTrace },
473: { 0x0200c001, SIZE_BYTE, SCR1_Read1, IoMem_WriteWithoutInterceptionButTrace },
474: { 0x0200c002, SIZE_BYTE, SCR1_Read2, IoMem_WriteWithoutInterceptionButTrace },
475: { 0x0200c003, SIZE_BYTE, SCR1_Read3, IoMem_WriteWithoutInterceptionButTrace },
476: { 0x0200c800, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
477: { 0x0200d000, SIZE_BYTE, SCR2_Read0, SCR2_Write0 },
478: { 0x0200d001, SIZE_BYTE, SCR2_Read1, SCR2_Write1 },
479: { 0x0200d002, SIZE_BYTE, SCR2_Read2, SCR2_Write2 },
480: { 0x0200d003, SIZE_BYTE, SCR2_Read3, SCR2_Write3 },
1.1.1.3 ! root 481: { 0x0200e000, SIZE_BYTE, Keyboard_Read0, IoMem_WriteWithoutInterception },
! 482: { 0x0200e001, SIZE_BYTE, Keyboard_Read1, IoMem_WriteWithoutInterception },
! 483: { 0x0200e002, SIZE_BYTE, Keyboard_Read2, IoMem_WriteWithoutInterception },
! 484: { 0x0200e003, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
1.1 root 485: { 0x0200e004, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
486: { 0x0200e005, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
487: { 0x0200e006, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
1.1.1.3 ! root 488: { 0x0200e008, SIZE_LONG, Keycode_Read, IoMem_WriteWithoutInterception },
1.1 root 489: { 0x02010000, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
490: { 0x02012004, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
491: { 0x02012005, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
492: { 0x02012007, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
493: { 0x02014003, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
494: { 0x02018000, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
495: { 0x02018001, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
496: { 0x02018004, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
497: { 0, 0, NULL, NULL }
498: };
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.