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1.1 root 1: /*
2: Previous - ioMemTabNEXT.c
3:
4: This file is distributed under the GNU Public License, version 2 or at
5: your option any later version. Read the file gpl.txt for details.
6:
7: Table with hardware IO handlers for the NEXT.
8: */
9:
10:
11: const char IoMemTabST_fileid[] = "Previous ioMemTabST.c : " __DATE__ " " __TIME__;
12:
13: #include "main.h"
14: #include "ioMem.h"
15: #include "ioMemTables.h"
16: #include "video.h"
17: #include "configuration.h"
18: #include "sysdeps.h"
19: #include "m68000.h"
1.1.1.3 root 20: #include "keymap.h"
1.1.1.4 ! root 21: #include "esp.h"
! 22: #include "ethernet.h"
! 23: #include "sysReg.h"
! 24: #include "dma.h"
! 25: #include "scc.h"
! 26: #include "mo.h"
1.1 root 27:
28:
29:
1.1.1.4 ! root 30: /* Hack from QEMU-NeXT, Correct this later with the data below */
! 31:
! 32: /* system timer */
! 33: struct timer_reg {
! 34: unsigned char t_counter_latch[2]; /* counted up at 1 MHz */
! 35: unsigned char : 8;
! 36: unsigned char : 8;
! 37: unsigned char t_enable : 1, /* counter enable */
! 38: t_update : 1, /* copy latch to counter */
! 39: : 6;
1.1 root 40: };
41:
1.1.1.4 ! root 42: /* Functions to be moved to other places */
! 43: void System_Timer_Read(void);
! 44: void FDD_Main_Status_Read(void);
! 45: void DSP_icr_Read(void);
! 46: void DSP_icr_Write(void);
1.1 root 47:
1.1.1.4 ! root 48: Uint32 eventcounter; // debugging code
! 49: Uint32 lasteventc; // debugging code
1.1 root 50:
1.1.1.4 ! root 51: void System_Timer_Read(void) { // tuned for power-on test
! 52: // lasteventc = eventcounter; // debugging code
! 53: if (ConfigureParams.System.nCpuLevel == 3) {
! 54: // eventcounter = (nCyclesMainCounter/((128/ConfigureParams.System.nCpuFreq)*3))&0xFFFFF; // debugging code
! 55: IoMem_WriteLong(IoAccessCurrentAddress&0x1FFFF, (nCyclesMainCounter/((128/ConfigureParams.System.nCpuFreq)*3))&0xFFFFF);
! 56: } else { // System has 68040 CPU
! 57: // eventcounter = (nCyclesMainCounter/((64/ConfigureParams.System.nCpuFreq)*9))&0xFFFFF; // debugging code
! 58: IoMem_WriteLong(IoAccessCurrentAddress&0x1FFFF, (nCyclesMainCounter/((64/ConfigureParams.System.nCpuFreq)*9))&0xFFFFF);
! 59: }
! 60: // printf("DIFFERENCE = %i\n",eventcounter-lasteventc);
1.1 root 61: }
62:
1.1.1.4 ! root 63: /* Floppy Disk Drive - Work on this later */
! 64: void FDD_Main_Status_Read (void) {
! 65: IoMem[IoAccessCurrentAddress & 0x1FFFF] = 0x00;
1.1 root 66: }
67:
68:
1.1.1.4 ! root 69: static Uint32 DSP_icr=0;
1.1 root 70:
71:
1.1.1.4 ! root 72: /* DSP registers - Work on this later */
! 73: void DSP_icr_Read (void) {
! 74: Log_Printf(LOG_WARN, "[DSP] read val %d PC=%x %s at %d",DSP_icr,m68k_getpc(),__FILE__,__LINE__);
! 75: IoMem_WriteLong(IoAccessCurrentAddress & 0x1FFFF,0x7FFFFFFF);
1.1 root 76: }
77:
1.1.1.4 ! root 78: void DSP_icr_Write (void) {
! 79: DSP_icr=IoMem_ReadLong(IoAccessCurrentAddress & 0x1FFFF);
! 80: Log_Printf(LOG_WARN, "[DSP] write val %d PC=%x %s at %d",DSP_icr,m68k_getpc(),__FILE__,__LINE__);
1.1 root 81: }
82:
83:
1.1.1.4 ! root 84: #define P_VIDEO_CSR (SLOT_ID+0x02000180)
! 85: #define P_M2R_CSR (SLOT_ID+0x020001d0)
! 86: #define P_R2M_CSR (SLOT_ID+0x020001c0)
1.1 root 87:
1.1.1.4 ! root 88: /* DMA scratch pad (writes MUST be 32-bit) */
! 89: #define P_VIDEO_SPAD (SLOT_ID+0x02004180)
! 90: #define P_EVENT_SPAD (SLOT_ID+0x0200418c)
! 91: #define P_M2M_SPAD (SLOT_ID+0x020041e0)
1.1 root 92:
93: /*-----------------------------------------------------------------------*/
94: /*
95: List of functions to handle read/write hardware interceptions.
96: */
97: const INTERCEPT_ACCESS_FUNC IoMemTable_NEXT[] =
98: {
1.1.1.4 ! root 99: /* These registers are read on turbo machines, they are somehow related to SCR1 */
! 100: { 0x02000000, SIZE_WORD, TurboSCR1_Read0, IoMem_WriteWithoutInterceptionButTrace },
! 101: { 0x02000002, SIZE_WORD, TurboSCR1_Read2, IoMem_WriteWithoutInterceptionButTrace },
! 102:
! 103: /* Brightness */
! 104: { 0x02010000, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 105:
! 106: // this is for video DMA channel
1.1 root 107: { 0x02004188, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
1.1.1.4 ! root 108: { 0x02004189, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 109: { 0x0200418a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 110: { 0x0200418b, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 111:
! 112:
! 113: /* DSP (Motorola XSP56001) */
! 114: { 0x02008000, SIZE_LONG, DSP_icr_Read, DSP_icr_Write },
! 115:
! 116: /* Network Adapter (MB8795) */
! 117: { 0x02006000, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 118: { 0x02006001, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 119: { 0x02006002, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 120: { 0x02006003, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 121: { 0x02006004, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 122: { 0x02006005, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 123: { 0x02006006, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 124: { 0x02006008, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 125: { 0x02006009, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 126: { 0x0200600a, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 127: { 0x0200600b, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 128: { 0x0200600c, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 129: { 0x0200600d, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
! 130: { 0x0200600e, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 131: { 0x0200600f, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 132:
! 133: /* Memory Timing */
! 134: { 0x02006010, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 135: { 0x02006011, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 136: { 0x02006012, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 137: { 0x02006013, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 138: { 0x02006014, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 139:
! 140: /* Interrupt Status and Mask Registers */
1.1 root 141: { 0x02007000, SIZE_LONG, IntRegStatRead, IntRegStatWrite },
1.1.1.4 ! root 142: { 0x02007800, SIZE_LONG, IntRegMaskRead, IntRegMaskWrite },
! 143:
! 144: /* System Control Register 1 */
1.1 root 145: { 0x0200c000, SIZE_BYTE, SCR1_Read0, IoMem_WriteWithoutInterceptionButTrace },
146: { 0x0200c001, SIZE_BYTE, SCR1_Read1, IoMem_WriteWithoutInterceptionButTrace },
147: { 0x0200c002, SIZE_BYTE, SCR1_Read2, IoMem_WriteWithoutInterceptionButTrace },
148: { 0x0200c003, SIZE_BYTE, SCR1_Read3, IoMem_WriteWithoutInterceptionButTrace },
1.1.1.4 ! root 149:
! 150: /* Slot ID (NeXT Cube) */
! 151: { 0x0200c800, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace },
! 152: { 0x0200c801, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace },
! 153: { 0x0200c802, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace },
! 154: { 0x0200c803, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace },
! 155:
! 156: /* System Control Register 2 */
1.1 root 157: { 0x0200d000, SIZE_BYTE, SCR2_Read0, SCR2_Write0 },
158: { 0x0200d001, SIZE_BYTE, SCR2_Read1, SCR2_Write1 },
159: { 0x0200d002, SIZE_BYTE, SCR2_Read2, SCR2_Write2 },
160: { 0x0200d003, SIZE_BYTE, SCR2_Read3, SCR2_Write3 },
1.1.1.4 ! root 161:
! 162: /* Monitor Registers (Keyboard, Mouse, Sound) */
! 163: { 0x0200e000, SIZE_BYTE, Monitor_CSR_Read, Monitor_CSR_Write },
! 164: { 0x0200e001, SIZE_BYTE, Monitor_CSR_Read, Monitor_CSR_Write },
! 165: { 0x0200e002, SIZE_BYTE, Monitor_CSR_Read, Monitor_CSR_Write },
! 166: { 0x0200e003, SIZE_BYTE, Monitor_CSR_Read, Monitor_CSR_Write },
1.1 root 167: { 0x0200e004, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
168: { 0x0200e005, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
169: { 0x0200e006, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
1.1.1.4 ! root 170: { 0x0200e007, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 171: { 0x0200e008, SIZE_LONG, Keycode_Read, IoMem_WriteWithoutInterceptionButTrace },
! 172:
! 173: /* Event counter */
! 174: { 0x0201a000, SIZE_BYTE, System_Timer_Read, IoMem_WriteWithoutInterceptionButTrace },
! 175: { 0x0201a001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
! 176: { 0x0201a002, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
! 177: { 0x0201a003, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
! 178:
! 179: /* Internal Hardclock */
! 180: { 0x02016000, SIZE_BYTE, HardclockRead0, HardclockWrite0 },
! 181: { 0x02016001, SIZE_BYTE, HardclockRead1, HardclockWrite1 },
! 182: { 0x02016004, SIZE_BYTE, HardclockReadCSR, HardclockWriteCSR },
! 183:
! 184:
! 185: /* Magneto-Optical Drive */
! 186: { 0x02012000, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 187: { 0x02012001, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 188: { 0x02012002, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 189: { 0x02012003, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 190: { 0x02012004, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 191: { 0x02012005, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 192: { 0x02012006, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 193: { 0x02012007, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 194: { 0x02012008, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 195: { 0x02012009, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 196: { 0x0201200a, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 197: { 0x0201200b, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 198: { 0x0201200c, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 199: { 0x0201200d, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 200: { 0x0201200e, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 201: { 0x0201200f, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 202: { 0x02012010, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 203: { 0x02012011, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 204: { 0x02012012, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 205: { 0x02012013, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 206: { 0x02012014, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 207: { 0x02012015, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 208: { 0x02012016, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
! 209:
! 210:
! 211: /*------------------ DMA ------------------*/
! 212:
! 213: /* DMA Control/Status Registers (writes MUST be 32-bit) */
! 214: { 0x02000010, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
! 215: { 0x02000040, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
! 216: { 0x02000050, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
! 217: { 0x020000c0, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
! 218: { 0x02000110, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
! 219: { 0x02000150, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
! 220:
! 221: { 0x02000180, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 222: { 0x020001d0, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 223: { 0x020001c0, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 224:
! 225: /* Channel SCSI */
! 226: { 0x02004000, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write },
! 227: { 0x02004004, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write },
! 228: { 0x02004008, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write },
! 229: { 0x0200400c, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write },
! 230: { 0x02004010, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
! 231: { 0x02004014, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
! 232: { 0x02004018, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
! 233: { 0x0200401c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
! 234: { 0x02004210, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
! 235: { 0x02004214, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
! 236:
! 237: /* Channel Sound out */
! 238: { 0x02004040, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
! 239: { 0x02004044, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
! 240: { 0x02004048, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
! 241: { 0x0200404c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
! 242:
! 243: /* Channel MO Drive */
! 244: { 0x02004050, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
! 245: { 0x02004054, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
! 246: { 0x02004058, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
! 247: { 0x0200405c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
! 248: { 0x02004250, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
! 249: { 0x02004254, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
! 250:
! 251: /* Channel SCC */
! 252: { 0x020040c0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
! 253: { 0x020040c4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
! 254: // { 0x020040c8, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write },
! 255: // { 0x020040cc, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write },
! 256:
! 257: // { 0x020040d0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
! 258: // { 0x020040d4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
! 259: // { 0x020040d8, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
! 260: // { 0x020040dc, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
! 261: // { 0x020042d0, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
! 262: // { 0x020042d4, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
! 263:
! 264: /* Channel Ethernet Transmit */
! 265: { 0x02004100, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write },
! 266: { 0x02004104, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write },
! 267: { 0x02004108, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write },
! 268: { 0x0200410c, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write },
! 269: { 0x02004110, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
! 270: { 0x02004114, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
! 271: { 0x02004118, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
! 272: { 0x0200411c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
! 273: { 0x02004310, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
! 274: { 0x02004314, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
! 275:
! 276: /* Channel Ethernet Receive */
! 277: { 0x02004140, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write },
! 278: { 0x02004144, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write },
! 279: { 0x02004148, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write },
! 280: { 0x0200414c, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write },
! 281: { 0x02004150, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
! 282: { 0x02004154, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
! 283: { 0x02004158, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
! 284: { 0x0200415c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
! 285: { 0x02004350, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
! 286: { 0x02004354, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
! 287: /*-------------------- End of DMA -------------------*/
! 288:
! 289:
! 290: /* SCSI Command/Status Registers */
! 291: { 0x02014020, SIZE_BYTE, SCSI_CSR0_Read, SCSI_CSR0_Write },
! 292: { 0x02014021, SIZE_BYTE, SCSI_CSR1_Read, SCSI_CSR1_Write },
! 293:
! 294: /* SCSI Controller (NCR53C90) */
! 295: { 0x02014000, SIZE_BYTE, SCSI_TransCountL_Read, SCSI_TransCountL_Write },
! 296: { 0x02014001, SIZE_BYTE, SCSI_TransCountH_Read, SCSI_TransCountH_Write },
! 297: { 0x02014002, SIZE_BYTE, SCSI_FIFO_Read, SCSI_FIFO_Write },
! 298: { 0x02014003, SIZE_BYTE, SCSI_Command_Read, SCSI_Command_Write },
! 299: { 0x02014004, SIZE_BYTE, SCSI_Status_Read, SCSI_SelectBusID_Write },
! 300: { 0x02014005, SIZE_BYTE, SCSI_IntStatus_Read, SCSI_SelectTimeout_Write },
! 301: { 0x02014006, SIZE_BYTE, SCSI_SeqStep_Read, SCSI_SyncPeriod_Write },
! 302: { 0x02014007, SIZE_BYTE, SCSI_FIFOflags_Read, SCSI_SyncOffset_Write },
! 303: { 0x02014008, SIZE_BYTE, SCSI_Configuration_Read, SCSI_Configuration_Write },
! 304: { 0x02014009, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, SCSI_ClockConv_Write },
! 305: { 0x0201400a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, SCSI_Test_Write },
! 306: /* Additional Register for NCR53C90A (68040) */
! 307: { 0x0201400b, SIZE_BYTE, SCSI_Conf2_Read, IoMem_WriteWithoutInterceptionButTrace },
! 308: // { 0x0201400c, SIZE_BYTE, SCSI_CMD_Read, SCSI_CMD_Write },
! 309: // { 0x0201400d, SIZE_BYTE, SCSI_CMD_Read, SCSI_CMD_Write },
! 310: // { 0x0201400e, SIZE_BYTE, SCSI_CMD_Read, SCSI_CMD_Write },
! 311: // { 0x0201400f, SIZE_BYTE, SCSI_CMD_Read, SCSI_CMD_Write },
! 312:
! 313: /* Floppy Controller (82077AA) */
! 314: { 0x02014100, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 315: { 0x02014101, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 316: { 0x02014102, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 317: { 0x02014103, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 318: { 0x02014104, SIZE_BYTE, FDD_Main_Status_Read, IoMem_WriteWithoutInterceptionButTrace },
! 319: { 0x02014105, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 320: { 0x02014106, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 321: { 0x02014107, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 322:
! 323: /* Floppy External Control */
! 324: { 0x02014108, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 325:
! 326: /* Serial Communication Controller (Z8530) */
! 327: { 0x02018000, SIZE_BYTE, SCC_Read, SCC_Write },
! 328: { 0x02018001, SIZE_BYTE, SCC_Read, SCC_Write },
! 329: { 0x02018002, SIZE_BYTE, SCC_Read, SCC_Write },
! 330: { 0x02018003, SIZE_BYTE, SCC_Read, SCC_Write },
1.1 root 331: { 0x02018004, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
332: { 0, 0, NULL, NULL }
333: };
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