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1.1 root 1: /*
2: Previous - ioMemTabNEXT.c
3:
4: This file is distributed under the GNU Public License, version 2 or at
5: your option any later version. Read the file gpl.txt for details.
6:
7: Table with hardware IO handlers for the NEXT.
8: */
9:
10:
11: const char IoMemTabST_fileid[] = "Previous ioMemTabST.c : " __DATE__ " " __TIME__;
12:
13: #include "main.h"
14: #include "ioMem.h"
15: #include "ioMemTables.h"
16: #include "video.h"
17: #include "configuration.h"
18: #include "sysdeps.h"
19: #include "m68000.h"
1.1.1.3 root 20: #include "keymap.h"
1.1.1.4 root 21: #include "esp.h"
22: #include "ethernet.h"
23: #include "sysReg.h"
24: #include "dma.h"
25: #include "scc.h"
26: #include "mo.h"
1.1 root 27:
28:
29:
1.1.1.4 root 30: /* Hack from QEMU-NeXT, Correct this later with the data below */
31:
32: /* system timer */
33: struct timer_reg {
34: unsigned char t_counter_latch[2]; /* counted up at 1 MHz */
35: unsigned char : 8;
36: unsigned char : 8;
37: unsigned char t_enable : 1, /* counter enable */
38: t_update : 1, /* copy latch to counter */
39: : 6;
1.1 root 40: };
41:
1.1.1.4 root 42: /* Functions to be moved to other places */
43: void System_Timer_Read(void);
44: void FDD_Main_Status_Read(void);
45: void DSP_icr_Read(void);
46: void DSP_icr_Write(void);
1.1 root 47:
1.1.1.4 root 48: Uint32 eventcounter; // debugging code
49: Uint32 lasteventc; // debugging code
1.1 root 50:
1.1.1.4 root 51: void System_Timer_Read(void) { // tuned for power-on test
52: // lasteventc = eventcounter; // debugging code
53: if (ConfigureParams.System.nCpuLevel == 3) {
54: // eventcounter = (nCyclesMainCounter/((128/ConfigureParams.System.nCpuFreq)*3))&0xFFFFF; // debugging code
55: IoMem_WriteLong(IoAccessCurrentAddress&0x1FFFF, (nCyclesMainCounter/((128/ConfigureParams.System.nCpuFreq)*3))&0xFFFFF);
56: } else { // System has 68040 CPU
57: // eventcounter = (nCyclesMainCounter/((64/ConfigureParams.System.nCpuFreq)*9))&0xFFFFF; // debugging code
58: IoMem_WriteLong(IoAccessCurrentAddress&0x1FFFF, (nCyclesMainCounter/((64/ConfigureParams.System.nCpuFreq)*9))&0xFFFFF);
59: }
60: // printf("DIFFERENCE = %i\n",eventcounter-lasteventc);
1.1 root 61: }
62:
1.1.1.4 root 63: /* Floppy Disk Drive - Work on this later */
64: void FDD_Main_Status_Read (void) {
65: IoMem[IoAccessCurrentAddress & 0x1FFFF] = 0x00;
1.1 root 66: }
67:
68:
1.1.1.4 root 69: static Uint32 DSP_icr=0;
1.1 root 70:
71:
1.1.1.4 root 72: /* DSP registers - Work on this later */
73: void DSP_icr_Read (void) {
74: Log_Printf(LOG_WARN, "[DSP] read val %d PC=%x %s at %d",DSP_icr,m68k_getpc(),__FILE__,__LINE__);
75: IoMem_WriteLong(IoAccessCurrentAddress & 0x1FFFF,0x7FFFFFFF);
1.1 root 76: }
77:
1.1.1.4 root 78: void DSP_icr_Write (void) {
79: DSP_icr=IoMem_ReadLong(IoAccessCurrentAddress & 0x1FFFF);
80: Log_Printf(LOG_WARN, "[DSP] write val %d PC=%x %s at %d",DSP_icr,m68k_getpc(),__FILE__,__LINE__);
1.1 root 81: }
82:
83:
1.1.1.4 root 84: #define P_VIDEO_CSR (SLOT_ID+0x02000180)
85: #define P_M2R_CSR (SLOT_ID+0x020001d0)
86: #define P_R2M_CSR (SLOT_ID+0x020001c0)
1.1 root 87:
1.1.1.4 root 88: /* DMA scratch pad (writes MUST be 32-bit) */
89: #define P_VIDEO_SPAD (SLOT_ID+0x02004180)
90: #define P_EVENT_SPAD (SLOT_ID+0x0200418c)
91: #define P_M2M_SPAD (SLOT_ID+0x020041e0)
1.1 root 92:
93: /*-----------------------------------------------------------------------*/
94: /*
95: List of functions to handle read/write hardware interceptions.
96: */
97: const INTERCEPT_ACCESS_FUNC IoMemTable_NEXT[] =
98: {
1.1.1.4 root 99: /* These registers are read on turbo machines, they are somehow related to SCR1 */
100: { 0x02000000, SIZE_WORD, TurboSCR1_Read0, IoMem_WriteWithoutInterceptionButTrace },
101: { 0x02000002, SIZE_WORD, TurboSCR1_Read2, IoMem_WriteWithoutInterceptionButTrace },
1.1.1.5 ! root 102:
! 103: { 0x02008008, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 104: { 0x02008009, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 105: { 0x0200800a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 106: { 0x0200800b, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 107:
! 108: { 0x02008018, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 109: { 0x02008019, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 110: { 0x0200801a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 111: { 0x0200801b, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 112:
! 113: { 0x02008020, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 114: { 0x02008021, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 115: { 0x02008022, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 116: { 0x02008023, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 117:
! 118: { 0x02008028, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 119: { 0x02008029, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 120: { 0x0200802a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 121: { 0x0200802b, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 122:
! 123: { 0x02008030, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 124: { 0x02008031, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 125: { 0x02008032, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 126: { 0x02008033, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 127:
! 128: { 0x02008038, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 129: { 0x02008039, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 130: { 0x0200803a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 131: { 0x0200803b, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 132:
! 133: { 0x02000088, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 134: { 0x02000089, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 135: { 0x0200008a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 136: { 0x0200008b, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 137:
! 138: { 0x0200008c, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 139: { 0x0200008d, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 140: { 0x0200008e, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 141: { 0x0200008f, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 142:
1.1.1.4 root 143:
144: /* Brightness */
145: { 0x02010000, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
146:
147: // this is for video DMA channel
1.1 root 148: { 0x02004188, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
1.1.1.4 root 149: { 0x02004189, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
150: { 0x0200418a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
151: { 0x0200418b, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
152:
153:
154: /* DSP (Motorola XSP56001) */
155: { 0x02008000, SIZE_LONG, DSP_icr_Read, DSP_icr_Write },
156:
157: /* Network Adapter (MB8795) */
158: { 0x02006000, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
159: { 0x02006001, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
160: { 0x02006002, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
161: { 0x02006003, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
162: { 0x02006004, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
163: { 0x02006005, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
164: { 0x02006006, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
165: { 0x02006008, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
166: { 0x02006009, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
167: { 0x0200600a, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
168: { 0x0200600b, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
169: { 0x0200600c, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
170: { 0x0200600d, SIZE_BYTE, Ethernet_Read, Ethernet_Write },
171: { 0x0200600e, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
172: { 0x0200600f, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
173:
174: /* Memory Timing */
175: { 0x02006010, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
176: { 0x02006011, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
177: { 0x02006012, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
178: { 0x02006013, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
179: { 0x02006014, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
180:
181: /* Interrupt Status and Mask Registers */
1.1 root 182: { 0x02007000, SIZE_LONG, IntRegStatRead, IntRegStatWrite },
1.1.1.4 root 183: { 0x02007800, SIZE_LONG, IntRegMaskRead, IntRegMaskWrite },
184:
185: /* System Control Register 1 */
1.1 root 186: { 0x0200c000, SIZE_BYTE, SCR1_Read0, IoMem_WriteWithoutInterceptionButTrace },
187: { 0x0200c001, SIZE_BYTE, SCR1_Read1, IoMem_WriteWithoutInterceptionButTrace },
188: { 0x0200c002, SIZE_BYTE, SCR1_Read2, IoMem_WriteWithoutInterceptionButTrace },
189: { 0x0200c003, SIZE_BYTE, SCR1_Read3, IoMem_WriteWithoutInterceptionButTrace },
1.1.1.4 root 190:
191: /* Slot ID (NeXT Cube) */
192: { 0x0200c800, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace },
193: { 0x0200c801, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace },
194: { 0x0200c802, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace },
195: { 0x0200c803, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace },
196:
197: /* System Control Register 2 */
1.1 root 198: { 0x0200d000, SIZE_BYTE, SCR2_Read0, SCR2_Write0 },
199: { 0x0200d001, SIZE_BYTE, SCR2_Read1, SCR2_Write1 },
200: { 0x0200d002, SIZE_BYTE, SCR2_Read2, SCR2_Write2 },
201: { 0x0200d003, SIZE_BYTE, SCR2_Read3, SCR2_Write3 },
1.1.1.4 root 202:
203: /* Monitor Registers (Keyboard, Mouse, Sound) */
204: { 0x0200e000, SIZE_BYTE, Monitor_CSR_Read, Monitor_CSR_Write },
205: { 0x0200e001, SIZE_BYTE, Monitor_CSR_Read, Monitor_CSR_Write },
206: { 0x0200e002, SIZE_BYTE, Monitor_CSR_Read, Monitor_CSR_Write },
207: { 0x0200e003, SIZE_BYTE, Monitor_CSR_Read, Monitor_CSR_Write },
1.1 root 208: { 0x0200e004, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
209: { 0x0200e005, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
210: { 0x0200e006, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
1.1.1.4 root 211: { 0x0200e007, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
212: { 0x0200e008, SIZE_LONG, Keycode_Read, IoMem_WriteWithoutInterceptionButTrace },
213:
1.1.1.5 ! root 214: /* Printer Register */
! 215: { 0x0200f000, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 216:
1.1.1.4 root 217: /* Event counter */
218: { 0x0201a000, SIZE_BYTE, System_Timer_Read, IoMem_WriteWithoutInterceptionButTrace },
219: { 0x0201a001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
220: { 0x0201a002, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
221: { 0x0201a003, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
222:
223: /* Internal Hardclock */
224: { 0x02016000, SIZE_BYTE, HardclockRead0, HardclockWrite0 },
225: { 0x02016001, SIZE_BYTE, HardclockRead1, HardclockWrite1 },
226: { 0x02016004, SIZE_BYTE, HardclockReadCSR, HardclockWriteCSR },
227:
228:
229: /* Magneto-Optical Drive */
1.1.1.5 ! root 230: #if 0 /* temporary disabled */
1.1.1.4 root 231: { 0x02012000, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
232: { 0x02012001, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
233: { 0x02012002, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
234: { 0x02012003, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
235: { 0x02012004, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
236: { 0x02012005, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
237: { 0x02012006, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
238: { 0x02012007, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
239: { 0x02012008, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
240: { 0x02012009, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
241: { 0x0201200a, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
242: { 0x0201200b, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
243: { 0x0201200c, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
244: { 0x0201200d, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
245: { 0x0201200e, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
246: { 0x0201200f, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
247: { 0x02012010, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
248: { 0x02012011, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
249: { 0x02012012, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
250: { 0x02012013, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
251: { 0x02012014, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
252: { 0x02012015, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
253: { 0x02012016, SIZE_BYTE, MOdrive_Read, MOdrive_Write },
1.1.1.5 ! root 254: #else
! 255: { 0x02012000, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 256: { 0x02012001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 257: { 0x02012002, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 258: { 0x02012003, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 259: { 0x02012004, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 260: { 0x02012005, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 261: { 0x02012006, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 262: { 0x02012007, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 263: { 0x02012008, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 264: { 0x02012009, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 265: { 0x0201200a, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 266: { 0x0201200b, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 267: { 0x0201200c, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 268: { 0x0201200d, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 269: { 0x0201200e, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 270: { 0x0201200f, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 271: { 0x02012010, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 272: { 0x02012011, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 273: { 0x02012012, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 274: { 0x02012013, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 275: { 0x02012014, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 276: { 0x02012015, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 277: { 0x02012016, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception },
! 278: #endif
1.1.1.4 root 279:
280:
281: /*------------------ DMA ------------------*/
282:
283: /* DMA Control/Status Registers (writes MUST be 32-bit) */
284: { 0x02000010, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
285: { 0x02000040, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
286: { 0x02000050, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
1.1.1.5 ! root 287: { 0x02000080, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
! 288: { 0x02000090, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
1.1.1.4 root 289: { 0x020000c0, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
1.1.1.5 ! root 290: { 0x020000d0, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
1.1.1.4 root 291: { 0x02000110, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
292: { 0x02000150, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
293:
1.1.1.5 ! root 294: { 0x02000180, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
! 295: { 0x020001d0, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
! 296: { 0x020001c0, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write },
! 297:
! 298: /* Channel R2M */
! 299: { 0x020041c0, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write },
! 300: { 0x020041c4, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write },
! 301: { 0x020041c8, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write },
! 302: { 0x020041cc, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write },
! 303: { 0x020043c0, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, // check this!
! 304: { 0x020043c4, SIZE_LONG, DMA_Size_Read, DMA_Size_Write }, // check this!
! 305:
! 306: /* Channel M2R */
! 307: { 0x020041d0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
! 308: { 0x020041d4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
! 309: { 0x020041d8, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
! 310: { 0x020041dc, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
! 311: { 0x020043d0, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
! 312: { 0x020043d4, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
1.1.1.4 root 313:
314: /* Channel SCSI */
315: { 0x02004000, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write },
316: { 0x02004004, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write },
317: { 0x02004008, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write },
318: { 0x0200400c, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write },
319: { 0x02004010, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
320: { 0x02004014, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
321: { 0x02004018, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
322: { 0x0200401c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
323: { 0x02004210, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
324: { 0x02004214, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
325:
326: /* Channel Sound out */
327: { 0x02004040, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
328: { 0x02004044, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
329: { 0x02004048, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
330: { 0x0200404c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
331:
332: /* Channel MO Drive */
333: { 0x02004050, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
334: { 0x02004054, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
335: { 0x02004058, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
336: { 0x0200405c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
337: { 0x02004250, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
338: { 0x02004254, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
339:
340: /* Channel SCC */
341: { 0x020040c0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
342: { 0x020040c4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
343: // { 0x020040c8, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write },
344: // { 0x020040cc, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write },
345:
346: // { 0x020040d0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
347: // { 0x020040d4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
348: // { 0x020040d8, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
349: // { 0x020040dc, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
350: // { 0x020042d0, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
351: // { 0x020042d4, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
352:
353: /* Channel Ethernet Transmit */
354: { 0x02004100, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write },
355: { 0x02004104, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write },
356: { 0x02004108, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write },
357: { 0x0200410c, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write },
358: { 0x02004110, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
359: { 0x02004114, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
360: { 0x02004118, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
361: { 0x0200411c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
362: { 0x02004310, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
363: { 0x02004314, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
364:
365: /* Channel Ethernet Receive */
366: { 0x02004140, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write },
367: { 0x02004144, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write },
368: { 0x02004148, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write },
369: { 0x0200414c, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write },
370: { 0x02004150, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
371: { 0x02004154, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
372: { 0x02004158, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
373: { 0x0200415c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
374: { 0x02004350, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
375: { 0x02004354, SIZE_LONG, DMA_Size_Read, DMA_Size_Write },
376: /*-------------------- End of DMA -------------------*/
377:
378:
379: /* SCSI Command/Status Registers */
380: { 0x02014020, SIZE_BYTE, SCSI_CSR0_Read, SCSI_CSR0_Write },
381: { 0x02014021, SIZE_BYTE, SCSI_CSR1_Read, SCSI_CSR1_Write },
382:
383: /* SCSI Controller (NCR53C90) */
384: { 0x02014000, SIZE_BYTE, SCSI_TransCountL_Read, SCSI_TransCountL_Write },
385: { 0x02014001, SIZE_BYTE, SCSI_TransCountH_Read, SCSI_TransCountH_Write },
386: { 0x02014002, SIZE_BYTE, SCSI_FIFO_Read, SCSI_FIFO_Write },
387: { 0x02014003, SIZE_BYTE, SCSI_Command_Read, SCSI_Command_Write },
388: { 0x02014004, SIZE_BYTE, SCSI_Status_Read, SCSI_SelectBusID_Write },
389: { 0x02014005, SIZE_BYTE, SCSI_IntStatus_Read, SCSI_SelectTimeout_Write },
390: { 0x02014006, SIZE_BYTE, SCSI_SeqStep_Read, SCSI_SyncPeriod_Write },
391: { 0x02014007, SIZE_BYTE, SCSI_FIFOflags_Read, SCSI_SyncOffset_Write },
392: { 0x02014008, SIZE_BYTE, SCSI_Configuration_Read, SCSI_Configuration_Write },
393: { 0x02014009, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, SCSI_ClockConv_Write },
394: { 0x0201400a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, SCSI_Test_Write },
395: /* Additional Register for NCR53C90A (68040) */
396: { 0x0201400b, SIZE_BYTE, SCSI_Conf2_Read, IoMem_WriteWithoutInterceptionButTrace },
397: // { 0x0201400c, SIZE_BYTE, SCSI_CMD_Read, SCSI_CMD_Write },
398: // { 0x0201400d, SIZE_BYTE, SCSI_CMD_Read, SCSI_CMD_Write },
399: // { 0x0201400e, SIZE_BYTE, SCSI_CMD_Read, SCSI_CMD_Write },
400: // { 0x0201400f, SIZE_BYTE, SCSI_CMD_Read, SCSI_CMD_Write },
401:
402: /* Floppy Controller (82077AA) */
403: { 0x02014100, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
404: { 0x02014101, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
405: { 0x02014102, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
406: { 0x02014103, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
407: { 0x02014104, SIZE_BYTE, FDD_Main_Status_Read, IoMem_WriteWithoutInterceptionButTrace },
408: { 0x02014105, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
409: { 0x02014106, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
410: { 0x02014107, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
411:
412: /* Floppy External Control */
413: { 0x02014108, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
414:
415: /* Serial Communication Controller (Z8530) */
416: { 0x02018000, SIZE_BYTE, SCC_Read, SCC_Write },
417: { 0x02018001, SIZE_BYTE, SCC_Read, SCC_Write },
418: { 0x02018002, SIZE_BYTE, SCC_Read, SCC_Write },
419: { 0x02018003, SIZE_BYTE, SCC_Read, SCC_Write },
1.1 root 420: { 0x02018004, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
421: { 0, 0, NULL, NULL }
422: };
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.