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1.1 root 1: /* 1.1.1.6 ! root 2: Previous - ioMemTabNEXT.c ! 3: ! 4: This file is distributed under the GNU Public License, version 2 or at ! 5: your option any later version. Read the file gpl.txt for details. ! 6: ! 7: Table with hardware IO handlers for the NEXT. ! 8: */ 1.1 root 9: 10: 1.1.1.6 ! root 11: const char IoMemTabNEXT_fileid[] = "Previous ioMemTabNEXT.c : " __DATE__ " " __TIME__; 1.1 root 12: 13: #include "main.h" 14: #include "ioMem.h" 15: #include "ioMemTables.h" 16: #include "video.h" 17: #include "configuration.h" 18: #include "sysdeps.h" 19: #include "m68000.h" 1.1.1.4 root 20: #include "esp.h" 21: #include "ethernet.h" 22: #include "sysReg.h" 23: #include "dma.h" 24: #include "scc.h" 25: #include "mo.h" 1.1.1.6 ! root 26: #include "kms.h" ! 27: #include "printer.h" ! 28: #include "ramdac.h" ! 29: #include "floppy.h" ! 30: #include "dsp.h" 1.1 root 31: 32: 33: 34: /*-----------------------------------------------------------------------*/ 35: /* 1.1.1.6 ! root 36: List of functions to handle read/write hardware interceptions. ! 37: */ 1.1 root 38: const INTERCEPT_ACCESS_FUNC IoMemTable_NEXT[] = 39: { 1.1.1.6 ! root 40: /* DMA Controller (Fujitsu MB610313) (writes MUST be 32-bit) */ ! 41: { 0x02000010, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 42: { 0x02000040, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 43: { 0x02000050, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 44: { 0x02000080, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 45: { 0x02000090, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 46: { 0x020000c0, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 47: { 0x020000d0, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 48: { 0x02000110, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 49: { 0x02000150, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 50: { 0x02000180, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 51: { 0x020001d0, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 52: { 0x020001c0, SIZE_LONG, DMA_CSR_Read, DMA_CSR_Write }, ! 53: ! 54: /* Channel SCSI */ ! 55: { 0x02004010, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 56: { 0x02004014, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 57: { 0x02004018, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 58: { 0x0200401c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 59: { 0x02004210, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 60: ! 61: /* Channel Sound out */ ! 62: { 0x02004030, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write }, ! 63: { 0x02004034, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write }, ! 64: { 0x02004038, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write }, ! 65: { 0x0200403c, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write }, ! 66: { 0x02004040, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 67: { 0x02004044, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 68: { 0x02004048, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 69: { 0x0200404c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 70: { 0x02004240, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 71: ! 72: /* Channel MO Drive */ ! 73: { 0x02004050, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 74: { 0x02004054, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 75: { 0x02004058, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 76: { 0x0200405c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 77: { 0x02004250, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 78: ! 79: /* Channel Sound in */ ! 80: { 0x02004080, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 81: { 0x02004084, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 82: { 0x02004088, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 83: { 0x0200408c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 84: { 0x02004280, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 85: ! 86: /* Channel Printer */ ! 87: { 0x02004090, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 88: { 0x02004094, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 89: { 0x02004098, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 90: { 0x0200409c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 91: { 0x02004290, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 92: ! 93: /* Channel SCC */ ! 94: { 0x020040c0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 95: { 0x020040c4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 96: { 0x020040c8, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 97: { 0x020040cc, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 98: ! 99: /* Channel DSP */ ! 100: { 0x020040d0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 101: { 0x020040d4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 102: { 0x020040d8, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 103: { 0x020040dc, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 104: { 0x020042d0, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 105: ! 106: /* Channel Ethernet Transmit */ ! 107: { 0x02004100, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write }, ! 108: { 0x02004104, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write }, ! 109: { 0x02004108, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write }, ! 110: { 0x0200410c, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write }, ! 111: { 0x02004110, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 112: { 0x02004114, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 113: { 0x02004118, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 114: { 0x0200411c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 115: { 0x02004310, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 116: ! 117: /* Channel Ethernet Receive */ ! 118: { 0x02004140, SIZE_LONG, DMA_Saved_Next_Read, DMA_Saved_Next_Write }, ! 119: { 0x02004144, SIZE_LONG, DMA_Saved_Limit_Read, DMA_Saved_Limit_Write }, ! 120: { 0x02004148, SIZE_LONG, DMA_Saved_Start_Read, DMA_Saved_Start_Write }, ! 121: { 0x0200414c, SIZE_LONG, DMA_Saved_Stop_Read, DMA_Saved_Stop_Write }, ! 122: { 0x02004150, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 123: { 0x02004154, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 124: { 0x02004158, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 125: { 0x0200415c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 126: { 0x02004350, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 127: ! 128: /* Channel Video */ ! 129: { 0x02004180, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, /* Video scratch pad */ ! 130: { 0x02004184, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 131: { 0x02004188, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 132: { 0x0200418c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, /* Event scratch pad */ ! 133: ! 134: /* Channel R2M */ ! 135: { 0x020041c0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 136: { 0x020041c4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 137: { 0x020041c8, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 138: { 0x020041cc, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 139: { 0x020043c0, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 140: ! 141: /* Channel M2R */ ! 142: { 0x020041d0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write }, ! 143: { 0x020041d4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write }, ! 144: { 0x020041d8, SIZE_LONG, DMA_Start_Read, DMA_Start_Write }, ! 145: { 0x020041dc, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write }, ! 146: { 0x020043d0, SIZE_LONG, DMA_Init_Read, DMA_Init_Write }, ! 147: ! 148: /* Network Adapter (Fujitsu MB8795) */ ! 149: { 0x02006000, SIZE_BYTE, EN_TX_Status_Read, EN_TX_Status_Write }, ! 150: { 0x02006001, SIZE_BYTE, EN_TX_Mask_Read, EN_TX_Mask_Write }, ! 151: { 0x02006002, SIZE_BYTE, EN_RX_Status_Read, EN_RX_Status_Write }, ! 152: { 0x02006003, SIZE_BYTE, EN_RX_Mask_Read, EN_RX_Mask_Write }, ! 153: { 0x02006004, SIZE_BYTE, EN_TX_Mode_Read, EN_TX_Mode_Write }, ! 154: { 0x02006005, SIZE_BYTE, EN_RX_Mode_Read, EN_RX_Mode_Write }, ! 155: { 0x02006006, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, EN_Reset_Write }, ! 156: { 0x02006007, SIZE_BYTE, EN_CounterLo_Read, IoMem_WriteWithoutInterceptionButTrace }, ! 157: { 0x02006008, SIZE_BYTE, EN_NodeID0_Read, EN_NodeID0_Write }, ! 158: { 0x02006009, SIZE_BYTE, EN_NodeID1_Read, EN_NodeID1_Write }, ! 159: { 0x0200600a, SIZE_BYTE, EN_NodeID2_Read, EN_NodeID2_Write }, ! 160: { 0x0200600b, SIZE_BYTE, EN_NodeID3_Read, EN_NodeID3_Write }, ! 161: { 0x0200600c, SIZE_BYTE, EN_NodeID4_Read, EN_NodeID4_Write }, ! 162: { 0x0200600d, SIZE_BYTE, EN_NodeID5_Read, EN_NodeID5_Write }, 1.1.1.4 root 163: { 0x0200600e, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, 1.1.1.6 ! root 164: { 0x0200600f, SIZE_BYTE, EN_CounterHi_Read, IoMem_WriteWithoutInterceptionButTrace }, ! 165: ! 166: /* Memory Timing */ 1.1.1.4 root 167: { 0x02006010, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, 168: { 0x02006011, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, 169: { 0x02006012, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, 170: { 0x02006013, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, 171: { 0x02006014, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, 1.1.1.6 ! root 172: ! 173: /* Interrupt Status and Mask Registers */ 1.1 root 174: { 0x02007000, SIZE_LONG, IntRegStatRead, IntRegStatWrite }, 1.1.1.4 root 175: { 0x02007800, SIZE_LONG, IntRegMaskRead, IntRegMaskWrite }, 1.1.1.6 ! root 176: ! 177: /* DSP (Motorola XSP56001) */ ! 178: { 0x02008000, SIZE_BYTE, DSP_ICR_Read, DSP_ICR_Write }, ! 179: { 0x02008001, SIZE_BYTE, DSP_CVR_Read, DSP_CVR_Write }, ! 180: { 0x02008002, SIZE_BYTE, DSP_ISR_Read, DSP_ISR_Write }, ! 181: { 0x02008003, SIZE_BYTE, DSP_IVR_Read, DSP_IVR_Write }, ! 182: { 0x02008004, SIZE_BYTE, DSP_Data0_Read, DSP_Data0_Write }, ! 183: { 0x02008005, SIZE_BYTE, DSP_Data1_Read, DSP_Data1_Write }, ! 184: { 0x02008006, SIZE_BYTE, DSP_Data2_Read, DSP_Data2_Write }, ! 185: { 0x02008007, SIZE_BYTE, DSP_Data3_Read, DSP_Data3_Write }, ! 186: 1.1.1.4 root 187: /* System Control Register 1 */ 1.1 root 188: { 0x0200c000, SIZE_BYTE, SCR1_Read0, IoMem_WriteWithoutInterceptionButTrace }, 189: { 0x0200c001, SIZE_BYTE, SCR1_Read1, IoMem_WriteWithoutInterceptionButTrace }, 190: { 0x0200c002, SIZE_BYTE, SCR1_Read2, IoMem_WriteWithoutInterceptionButTrace }, 191: { 0x0200c003, SIZE_BYTE, SCR1_Read3, IoMem_WriteWithoutInterceptionButTrace }, 1.1.1.6 ! root 192: ! 193: /* Slot ID Register */ 1.1.1.4 root 194: { 0x0200c800, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace }, 195: { 0x0200c801, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace }, 196: { 0x0200c802, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace }, 197: { 0x0200c803, SIZE_BYTE, SID_Read, IoMem_WriteWithoutInterceptionButTrace }, 1.1.1.6 ! root 198: 1.1.1.4 root 199: /* System Control Register 2 */ 1.1 root 200: { 0x0200d000, SIZE_BYTE, SCR2_Read0, SCR2_Write0 }, 201: { 0x0200d001, SIZE_BYTE, SCR2_Read1, SCR2_Write1 }, 202: { 0x0200d002, SIZE_BYTE, SCR2_Read2, SCR2_Write2 }, 203: { 0x0200d003, SIZE_BYTE, SCR2_Read3, SCR2_Write3 }, 1.1.1.6 ! root 204: ! 205: /* Monitor/Soundbox (Keyboard, Mouse, Sound) */ ! 206: { 0x0200e000, SIZE_BYTE, KMS_Stat_Snd_Read, KMS_Ctrl_Snd_Write }, ! 207: { 0x0200e001, SIZE_BYTE, KMS_Stat_KM_Read, KMS_Ctrl_KM_Write }, ! 208: { 0x0200e002, SIZE_BYTE, KMS_Stat_TX_Read, KMS_Ctrl_TX_Write }, ! 209: { 0x0200e003, SIZE_BYTE, KMS_Stat_Cmd_Read, KMS_Ctrl_Cmd_Write }, ! 210: { 0x0200e004, SIZE_LONG, KMS_Data_Read, KMS_Data_Write }, ! 211: { 0x0200e008, SIZE_LONG, KMS_KM_Data_Read, IoMem_WriteWithoutInterceptionButTrace }, ! 212: { 0x0200e00c, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 213: ! 214: /* Printer */ ! 215: { 0x0200f000, SIZE_BYTE, LP_CSR0_Read, LP_CSR0_Write }, ! 216: { 0x0200f001, SIZE_BYTE, LP_CSR1_Read, LP_CSR1_Write }, ! 217: { 0x0200f002, SIZE_BYTE, LP_CSR2_Read, LP_CSR2_Write }, ! 218: { 0x0200f003, SIZE_BYTE, LP_CSR3_Read, LP_CSR3_Write }, ! 219: { 0x0200f004, SIZE_LONG, LP_Data_Read, LP_Data_Write }, ! 220: ! 221: /* Brightness */ ! 222: { 0x02010000, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 223: ! 224: /* Magneto-Optical Drive Controller (Fujitsu MB600310) */ ! 225: { 0x02012000, SIZE_BYTE, MO_TrackNumH_Read, MO_TrackNumH_Write }, ! 226: { 0x02012001, SIZE_BYTE, MO_TrackNumL_Read, MO_TrackNumL_Write }, ! 227: { 0x02012002, SIZE_BYTE, MO_SectorIncr_Read, MO_SectorIncr_Write }, ! 228: { 0x02012003, SIZE_BYTE, MO_SectorCnt_Read, MO_SectorCnt_Write }, ! 229: { 0x02012004, SIZE_BYTE, MO_IntStatus_Read, MO_IntStatus_Write }, ! 230: { 0x02012005, SIZE_BYTE, MO_IntMask_Read, MO_IntMask_Write }, ! 231: { 0x02012006, SIZE_BYTE, MOctrl_CSR2_Read, MOctrl_CSR2_Write }, ! 232: { 0x02012007, SIZE_BYTE, MOctrl_CSR1_Read, MOctrl_CSR1_Write }, ! 233: { 0x02012008, SIZE_BYTE, MO_CSR_H_Read, MO_CSR_H_Write }, ! 234: { 0x02012009, SIZE_BYTE, MO_CSR_L_Read, MO_CSR_L_Write }, ! 235: { 0x0201200a, SIZE_BYTE, MO_ErrStat_Read, IoMem_WriteWithoutInterceptionButTrace }, ! 236: { 0x0201200b, SIZE_BYTE, MO_EccCnt_Read, IoMem_WriteWithoutInterceptionButTrace }, ! 237: { 0x0201200c, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, MO_Init_Write }, ! 238: { 0x0201200d, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, MO_Format_Write }, ! 239: { 0x0201200e, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, MO_Mark_Write }, ! 240: { 0x0201200f, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 241: { 0x02012010, SIZE_BYTE, MO_Flag0_Read, MO_Flag0_Write }, ! 242: { 0x02012011, SIZE_BYTE, MO_Flag1_Read, MO_Flag1_Write }, ! 243: { 0x02012012, SIZE_BYTE, MO_Flag2_Read, MO_Flag2_Write }, ! 244: { 0x02012013, SIZE_BYTE, MO_Flag3_Read, MO_Flag3_Write }, ! 245: { 0x02012014, SIZE_BYTE, MO_Flag4_Read, MO_Flag4_Write }, ! 246: { 0x02012015, SIZE_BYTE, MO_Flag5_Read, MO_Flag5_Write }, ! 247: { 0x02012016, SIZE_BYTE, MO_Flag6_Read, MO_Flag6_Write }, ! 248: ! 249: /* SCSI Controller (NCR53C90) */ ! 250: { 0x02014000, SIZE_BYTE, ESP_TransCountL_Read, ESP_TransCountL_Write }, ! 251: { 0x02014001, SIZE_BYTE, ESP_TransCountH_Read, ESP_TransCountH_Write }, ! 252: { 0x02014002, SIZE_BYTE, ESP_FIFO_Read, ESP_FIFO_Write }, ! 253: { 0x02014003, SIZE_BYTE, ESP_Command_Read, ESP_Command_Write }, ! 254: { 0x02014004, SIZE_BYTE, ESP_Status_Read, ESP_SelectBusID_Write }, ! 255: { 0x02014005, SIZE_BYTE, ESP_IntStatus_Read, ESP_SelectTimeout_Write }, ! 256: { 0x02014006, SIZE_BYTE, ESP_SeqStep_Read, ESP_SyncPeriod_Write }, ! 257: { 0x02014007, SIZE_BYTE, ESP_FIFOflags_Read, ESP_SyncOffset_Write }, ! 258: { 0x02014008, SIZE_BYTE, ESP_Configuration_Read, ESP_Configuration_Write }, ! 259: { 0x02014009, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, ESP_ClockConv_Write }, ! 260: { 0x0201400a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, ESP_Test_Write }, ! 261: /* Additional Registers for NCR53C90A (68040) */ ! 262: { 0x0201400b, SIZE_BYTE, ESP_Conf2_Read, IoMem_WriteWithoutInterceptionButTrace }, ! 263: { 0x0201400c, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 264: { 0x0201400d, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 265: { 0x0201400e, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 266: { 0x0201400f, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 267: ! 268: /* SCSI DMA Control/Status */ ! 269: { 0x02014020, SIZE_BYTE, ESP_DMA_CTRL_Read, ESP_DMA_CTRL_Write }, ! 270: { 0x02014021, SIZE_BYTE, ESP_DMA_FIFO_STAT_Read, ESP_DMA_FIFO_STAT_Write }, ! 271: ! 272: /* Floppy Controller (Intel 82077AA) */ ! 273: { 0x02014100, SIZE_BYTE, FLP_StatA_Read, IoMem_WriteWithoutInterceptionButTrace }, ! 274: { 0x02014101, SIZE_BYTE, FLP_StatB_Read, IoMem_WriteWithoutInterceptionButTrace }, ! 275: { 0x02014102, SIZE_BYTE, FLP_DataOut_Read, FLP_DataOut_Write }, ! 276: { 0x02014103, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 277: { 0x02014104, SIZE_BYTE, FLP_Status_Read, FLP_DataRate_Write }, ! 278: { 0x02014105, SIZE_BYTE, FLP_FIFO_Read, FLP_FIFO_Write }, ! 279: { 0x02014106, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 280: { 0x02014107, SIZE_BYTE, FLP_DataIn_Read, FLP_Configuration_Write }, ! 281: ! 282: /* Floppy External Control */ ! 283: { 0x02014108, SIZE_BYTE, FLP_Control_Read, FLP_Select_Write }, ! 284: ! 285: /* Internal Hardclock */ ! 286: { 0x02016000, SIZE_BYTE, HardclockRead0, HardclockWrite0 }, ! 287: { 0x02016001, SIZE_BYTE, HardclockRead1, HardclockWrite1 }, ! 288: { 0x02016004, SIZE_BYTE, HardclockReadCSR, HardclockWriteCSR }, ! 289: ! 290: /* Serial Communication Controller (AMD Z8530H) */ ! 291: { 0x02018000, SIZE_BYTE, SCC_ControlB_Read, SCC_ControlB_Write }, ! 292: { 0x02018001, SIZE_BYTE, SCC_ControlA_Read, SCC_ControlA_Write }, ! 293: { 0x02018002, SIZE_BYTE, SCC_DataB_Read, SCC_DataB_Write }, ! 294: { 0x02018003, SIZE_BYTE, SCC_DataA_Read, SCC_DataA_Write }, ! 295: /* Serial Interface Clock */ ! 296: { 0x02018004, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 297: ! 298: /* RAMDAC (Brooktree Bt463) */ ! 299: { 0x02018100, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 300: { 0x02018101, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 301: { 0x02018102, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 302: { 0x02018103, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 303: ! 304: /* Color Video Control and Memory Timings */ ! 305: { 0x02018180, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, ColorVideo_CMD_Write }, ! 306: { 0x02018190, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 307: { 0x02018198, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace }, ! 308: ! 309: /* Event Counter */ ! 310: { 0x0201a000, SIZE_BYTE, System_Timer_Read, IoMem_WriteWithoutInterceptionButTrace }, ! 311: { 0x0201a001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace }, ! 312: { 0x0201a002, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace }, ! 313: { 0x0201a003, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace }, 1.1.1.4 root 314: 1.1 root 315: { 0, 0, NULL, NULL } 316: };
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