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1.1 root 1: /*
2: Previous - ioMemTabTurbo.c
3:
4: This file is distributed under the GNU Public License, version 2 or at
5: your option any later version. Read the file gpl.txt for details.
6:
7: Table with hardware IO handlers for the NEXT.
8: */
9:
10:
11: const char IoMemTabTurbo_fileid[] = "Previous ioMemTabTurbo.c : " __DATE__ " " __TIME__;
12:
13: #include "main.h"
14: #include "ioMem.h"
15: #include "ioMemTables.h"
16: #include "video.h"
17: #include "configuration.h"
18: #include "sysdeps.h"
19: #include "m68000.h"
20: #include "esp.h"
21: #include "ethernet.h"
22: #include "sysReg.h"
23: #include "dma.h"
24: #include "scc.h"
25: #include "mo.h"
26: #include "kms.h"
27: #include "printer.h"
28: #include "ramdac.h"
29: #include "floppy.h"
30: #include "dsp.h"
31:
32:
33:
34: /*-----------------------------------------------------------------------*/
35: /*
36: List of functions to handle read/write hardware interceptions.
37: */
38: const INTERCEPT_ACCESS_FUNC IoMemTable_Turbo[] =
39: {
40: /* DMA Controller (Motorola) (writes MUST be 32-bit) */
41: { 0x02000010, SIZE_LONG, TDMA_CSR_Read, TDMA_CSR_Write },
42: { 0x02000040, SIZE_LONG, TDMA_CSR_Read, TDMA_CSR_Write },
43: { 0x02000080, SIZE_LONG, TDMA_CSR_Read, TDMA_CSR_Write },
44: { 0x02000090, SIZE_LONG, TDMA_CSR_Read, TDMA_CSR_Write },
45: { 0x020000d0, SIZE_LONG, TDMA_CSR_Read, TDMA_CSR_Write },
46: { 0x02000110, SIZE_LONG, TDMA_CSR_Read, TDMA_CSR_Write },
47: { 0x02000150, SIZE_LONG, TDMA_CSR_Read, TDMA_CSR_Write },
48:
49: /* Channel SCSI */
50: { 0x02004010, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
51: { 0x02004014, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
52: { 0x02004018, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
53: { 0x0200401c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
54:
55: /* Channel Sound out */
56: { 0x02004040, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
57: { 0x02004044, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
58: { 0x02004048, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
59: { 0x0200404c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
60:
61: /* Ethernet Saved Next */
62: { 0x02004050, SIZE_LONG, TDMA_Saved_Next_Read, IoMem_WriteWithoutInterceptionButTrace },
63:
64: /* Channel Sound in */
65: { 0x02004080, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
66: { 0x02004084, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
67: { 0x02004088, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
68: { 0x0200408c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
69:
70: /* Channel Printer */
71: { 0x02004090, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
72: { 0x02004094, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
73: { 0x02004098, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
74: { 0x0200409c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
75:
76: /* Channel DSP */
77: { 0x020040d0, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
78: { 0x020040d4, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
79: { 0x020040d8, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
80: { 0x020040dc, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
81:
82: /* Channel Ethernet Transmit */
83: { 0x02004110, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
84: { 0x02004114, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
85: { 0x02004118, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
86: { 0x0200411c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
87:
88: /* Channel Ethernet Receive */
89: { 0x02004150, SIZE_LONG, DMA_Next_Read, DMA_Next_Write },
90: { 0x02004154, SIZE_LONG, DMA_Limit_Read, DMA_Limit_Write },
91: { 0x02004158, SIZE_LONG, DMA_Start_Read, DMA_Start_Write },
92: { 0x0200415c, SIZE_LONG, DMA_Stop_Read, DMA_Stop_Write },
93:
94: /* DMA Init */
95: { 0x02004210, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
96: { 0x02004240, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
97: { 0x02004280, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
98: { 0x02004290, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
99: { 0x020042d0, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
100: { 0x02004310, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
101: { 0x02004350, SIZE_LONG, DMA_Init_Read, DMA_Init_Write },
102:
103: /* Network Adapter (AT&T 7213) */
104: { 0x02006000, SIZE_BYTE, EN_TX_Status_Read, EN_TX_Status_Write },
105: { 0x02006001, SIZE_BYTE, EN_TX_Mask_Read, EN_TX_Mask_Write },
106: { 0x02006002, SIZE_BYTE, EN_RX_Status_Read, EN_RX_Status_Write },
107: { 0x02006003, SIZE_BYTE, EN_RX_Mask_Read, EN_RX_Mask_Write },
108: { 0x02006004, SIZE_BYTE, EN_TX_Mode_Read, EN_TX_Mode_Write },
109: { 0x02006005, SIZE_BYTE, EN_RX_Mode_Read, EN_RX_Mode_Write },
110: { 0x02006006, SIZE_BYTE, EN_Control_Read, EN_Control_Write },
111: { 0x02006007, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
112: { 0x02006008, SIZE_BYTE, EN_NodeID0_Read, EN_NodeID0_Write },
113: { 0x02006009, SIZE_BYTE, EN_NodeID1_Read, EN_NodeID1_Write },
114: { 0x0200600a, SIZE_BYTE, EN_NodeID2_Read, EN_NodeID2_Write },
115: { 0x0200600b, SIZE_BYTE, EN_NodeID3_Read, EN_NodeID3_Write },
116: { 0x0200600c, SIZE_BYTE, EN_NodeID4_Read, EN_NodeID4_Write },
117: { 0x0200600d, SIZE_BYTE, EN_NodeID5_Read, EN_NodeID5_Write },
118: { 0x0200600e, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
119: { 0x0200600f, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
120:
121: /* Interrupt Status and Mask Registers */
122: { 0x02007000, SIZE_LONG, IntRegStatRead, IntRegStatWrite },
123: { 0x02007800, SIZE_LONG, IntRegMaskRead, IntRegMaskWrite },
124:
125: /* DSP (Motorola XSP56001) */
126: { 0x02008000, SIZE_BYTE, DSP_ICR_Read, DSP_ICR_Write },
127: { 0x02008001, SIZE_BYTE, DSP_CVR_Read, DSP_CVR_Write },
128: { 0x02008002, SIZE_BYTE, DSP_ISR_Read, DSP_ISR_Write },
129: { 0x02008003, SIZE_BYTE, DSP_IVR_Read, DSP_IVR_Write },
130: { 0x02008004, SIZE_BYTE, DSP_Data0_Read, DSP_Data0_Write },
131: { 0x02008005, SIZE_BYTE, DSP_Data1_Read, DSP_Data1_Write },
132: { 0x02008006, SIZE_BYTE, DSP_Data2_Read, DSP_Data2_Write },
133: { 0x02008007, SIZE_BYTE, DSP_Data3_Read, DSP_Data3_Write },
134:
135: /* System Control Register 1 */
136: { 0x0200c000, SIZE_BYTE, SCR1_Read0, IoMem_WriteWithoutInterceptionButTrace },
137: { 0x0200c001, SIZE_BYTE, SCR1_Read1, IoMem_WriteWithoutInterceptionButTrace },
138: { 0x0200c002, SIZE_BYTE, SCR1_Read2, IoMem_WriteWithoutInterceptionButTrace },
139: { 0x0200c003, SIZE_BYTE, SCR1_Read3, IoMem_WriteWithoutInterceptionButTrace },
140:
141: /* System Control Register 2 */
142: { 0x0200d000, SIZE_BYTE, SCR2_Read0, SCR2_Write0 },
143: { 0x0200d001, SIZE_BYTE, SCR2_Read1, SCR2_Write1 },
144: { 0x0200d002, SIZE_BYTE, SCR2_Read2, SCR2_Write2 },
145: { 0x0200d003, SIZE_BYTE, SCR2_Read3, SCR2_Write3 },
146:
147: /* Monitor/Soundbox (Keyboard, Mouse, Sound) */
148: { 0x0200e000, SIZE_BYTE, KMS_Stat_Snd_Read, KMS_Ctrl_Snd_Write },
149: { 0x0200e001, SIZE_BYTE, KMS_Stat_KM_Read, KMS_Ctrl_KM_Write },
150: { 0x0200e002, SIZE_BYTE, KMS_Stat_TX_Read, KMS_Ctrl_TX_Write },
151: { 0x0200e003, SIZE_BYTE, KMS_Stat_Cmd_Read, KMS_Ctrl_Cmd_Write },
152: { 0x0200e004, SIZE_LONG, KMS_Data_Read, KMS_Data_Write },
153: { 0x0200e008, SIZE_LONG, KMS_KM_Data_Read, IoMem_WriteWithoutInterceptionButTrace },
154: { 0x0200e00c, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
155:
156: /* Printer */
157: { 0x0200f000, SIZE_BYTE, LP_CSR0_Read, LP_CSR0_Write },
158: { 0x0200f001, SIZE_BYTE, LP_CSR1_Read, LP_CSR1_Write },
159: { 0x0200f002, SIZE_BYTE, LP_CSR2_Read, LP_CSR2_Write },
160: { 0x0200f003, SIZE_BYTE, LP_CSR3_Read, LP_CSR3_Write },
161: { 0x0200f004, SIZE_LONG, LP_Data_Read, LP_Data_Write },
162:
163: /* Brightness */
164: { 0x02010000, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
165:
166: /* GPIO Register */
167: { 0x02012000, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
168: { 0x02012001, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
169: { 0x02012002, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
170: { 0x02012003, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
171:
172: /* SCSI Controller (NCR53C90A) */
173: { 0x02014000, SIZE_BYTE, ESP_TransCountL_Read, ESP_TransCountL_Write },
174: { 0x02014001, SIZE_BYTE, ESP_TransCountH_Read, ESP_TransCountH_Write },
175: { 0x02014002, SIZE_BYTE, ESP_FIFO_Read, ESP_FIFO_Write },
176: { 0x02014003, SIZE_BYTE, ESP_Command_Read, ESP_Command_Write },
177: { 0x02014004, SIZE_BYTE, ESP_Status_Read, ESP_SelectBusID_Write },
178: { 0x02014005, SIZE_BYTE, ESP_IntStatus_Read, ESP_SelectTimeout_Write },
179: { 0x02014006, SIZE_BYTE, ESP_SeqStep_Read, ESP_SyncPeriod_Write },
180: { 0x02014007, SIZE_BYTE, ESP_FIFOflags_Read, ESP_SyncOffset_Write },
181: { 0x02014008, SIZE_BYTE, ESP_Configuration_Read, ESP_Configuration_Write },
182: { 0x02014009, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, ESP_ClockConv_Write },
183: { 0x0201400a, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, ESP_Test_Write },
184: { 0x0201400b, SIZE_BYTE, ESP_Conf2_Read, IoMem_WriteWithoutInterceptionButTrace },
185: { 0x0201400c, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
186: { 0x0201400d, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
187: { 0x0201400e, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
188: { 0x0201400f, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
189:
190: /* SCSI DMA Control/Status Registers */
191: { 0x02014020, SIZE_BYTE, ESP_DMA_CTRL_Read, ESP_DMA_CTRL_Write },
192: { 0x02014021, SIZE_BYTE, ESP_DMA_FIFO_STAT_Read, ESP_DMA_FIFO_STAT_Write },
193:
194: /* Event Counter */
1.1.1.2 ! root 195: { 0x0201a000, SIZE_BYTE, System_Timer_Read, System_Timer_Write },
1.1 root 196: { 0x0201a001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
197: { 0x0201a002, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
198: { 0x0201a003, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterceptionButTrace },
199:
200: /* Floppy Controller (Intel 82077AA) */
201: { 0x02014100, SIZE_BYTE, FLP_StatA_Read, IoMem_WriteWithoutInterceptionButTrace },
202: { 0x02014101, SIZE_BYTE, FLP_StatB_Read, IoMem_WriteWithoutInterceptionButTrace },
203: { 0x02014102, SIZE_BYTE, FLP_DataOut_Read, FLP_DataOut_Write },
204: { 0x02014103, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
205: { 0x02014104, SIZE_BYTE, FLP_Status_Read, FLP_DataRate_Write },
206: { 0x02014105, SIZE_BYTE, FLP_FIFO_Read, FLP_FIFO_Write },
207: { 0x02014106, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
208: { 0x02014107, SIZE_BYTE, FLP_DataIn_Read, FLP_Configuration_Write },
209:
210: /* Floppy External Control */
211: { 0x02014108, SIZE_BYTE, FLP_Control_Read, FLP_Select_Write },
212:
213: /* Internal Hardclock */
214: { 0x02016000, SIZE_BYTE, HardclockRead0, HardclockWrite0 },
215: { 0x02016001, SIZE_BYTE, HardclockRead1, HardclockWrite1 },
216: { 0x02016004, SIZE_BYTE, HardclockReadCSR, HardclockWriteCSR },
217:
218: /* Serial Communication Controller (AMD Z8530H) */
219: { 0x02018000, SIZE_BYTE, SCC_ControlB_Read, SCC_ControlB_Write },
220: { 0x02018001, SIZE_BYTE, SCC_ControlA_Read, SCC_ControlA_Write },
221: { 0x02018002, SIZE_BYTE, SCC_DataB_Read, SCC_DataB_Write },
222: { 0x02018003, SIZE_BYTE, SCC_DataA_Read, SCC_DataA_Write },
223: /* Serial Interface Clock */
224: { 0x02018004, SIZE_LONG, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
225:
226: /* RAMDAC (Brooktree Bt463) */
227: { 0x0201c000, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
228: { 0x0201c001, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
229: { 0x0201c002, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
230: { 0x0201c003, SIZE_BYTE, IoMem_ReadWithoutInterceptionButTrace, IoMem_WriteWithoutInterceptionButTrace },
231:
232: { 0, 0, NULL, NULL }
233: };
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.