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1.1 root 1: #include "main.h"
2: #include "configuration.h"
3: #include "m68000.h"
4: #include "dimension.h"
5: #include "sysdeps.h"
6: #include "nbic.h"
7:
8: #define LOG_NEXTBUS_LEVEL LOG_NONE
9:
10: /* NeXTbus and NeXTbus Interface Chip emulation */
11:
12: #define NUM_SLOTS 15
13:
14:
15: /* NBIC Registers */
16:
17: struct {
18: Uint32 control;
19: Uint32 id;
20: Uint8 intstatus;
21: Uint8 intmask;
22: } nbic;
23:
24:
25: /* Control: 0x02020000 (rw), only non-Turbo */
26: #define NBIC_CTRL_IGNSID0 0x10000000 /* Ignore slot ID bit 0 */
27: #define NBIC_CTRL_STFWD 0x08000000 /* Store forward */
28: #define NBIC_CTRL_RMCOL 0x04000000 /* Read modify cycle collision */
29:
30: /* ID: 0x02020004 (w), 0xF0FFFFFx (r), only non-Turbo */
31: #define NBIC_ID_VALID 0x80000000
32: #define NBIC_ID_M_MASK 0x7FFF0000 /* Manufacturer ID */
33: #define NBIC_ID_B_MASK 0x0000FFFF /* Board ID */
34:
35: /* Interrupt: 0xF0FFFFE8 (r) */
36: #define NBIC_INT_STATUS 0x80
37:
38: /* Interrupt mask: 0xF0FFFFEC (rw) */
39: #define NBIC_INT_MASK 0x80
40:
41:
42: /* Register access functions */
1.1.1.2 ! root 43: static Uint8 nbic_control_read0(Uint32 addr) {
1.1 root 44: Log_Printf(LOG_WARN, "[NBIC] Control (byte 0) read at %08X",addr);
45: return (nbic.control>>24);
46: }
1.1.1.2 ! root 47: static Uint8 nbic_control_read1(Uint32 addr) {
1.1 root 48: Log_Printf(LOG_WARN, "[NBIC] Control (byte 1) read at %08X",addr);
49: return (nbic.control>>16);
50: }
1.1.1.2 ! root 51: static Uint8 nbic_control_read2(Uint32 addr) {
1.1 root 52: Log_Printf(LOG_WARN, "[NBIC] Control (byte 2) read at %08X",addr);
53: return (nbic.control>>8);
54: }
1.1.1.2 ! root 55: static Uint8 nbic_control_read3(Uint32 addr) {
1.1 root 56: Log_Printf(LOG_WARN, "[NBIC] Control (byte 3) read at %08X",addr);
57: return nbic.control;
58: }
59:
1.1.1.2 ! root 60: static void nbic_control_write0(Uint32 addr, Uint8 val) {
1.1 root 61: Log_Printf(LOG_WARN, "[NBIC] Control (byte 0) write %02X at %08X",val,addr);
62: nbic.control &= 0x00FFFFFF;
63: nbic.control |= (val&0xFF)<<24;
64: }
1.1.1.2 ! root 65: static void nbic_control_write1(Uint32 addr, Uint8 val) {
1.1 root 66: Log_Printf(LOG_WARN, "[NBIC] Control (byte 1) write %02X at %08X",val,addr);
67: nbic.control &= 0xFF00FFFF;
68: nbic.control |= (val&0xFF)<<16;
69: }
1.1.1.2 ! root 70: static void nbic_control_write2(Uint32 addr, Uint8 val) {
1.1 root 71: Log_Printf(LOG_WARN, "[NBIC] Control (byte 2) write %02X at %08X",val,addr);
72: nbic.control &= 0xFFFF00FF;
73: nbic.control |= (val&0xFF)<<8;
74: }
1.1.1.2 ! root 75: static void nbic_control_write3(Uint32 addr, Uint8 val) {
1.1 root 76: Log_Printf(LOG_WARN, "[NBIC] Control (byte 3) write %02X at %08X",val,addr);
77: nbic.control &= 0xFFFFFF00;
78: nbic.control |= val&0xFF;
79: }
80:
81:
1.1.1.2 ! root 82: static Uint8 nbic_id_read0(Uint32 addr) {
1.1 root 83: Log_Printf(LOG_WARN, "[NBIC] ID (byte 0) read at %08X",addr);
84: return (nbic.id>>24);
85: }
1.1.1.2 ! root 86: static Uint8 nbic_id_read1(Uint32 addr) {
1.1 root 87: Log_Printf(LOG_WARN, "[NBIC] ID (byte 1) read at %08X",addr);
88: return (nbic.id>>16);
89: }
1.1.1.2 ! root 90: static Uint8 nbic_id_read2(Uint32 addr) {
1.1 root 91: Log_Printf(LOG_WARN, "[NBIC] ID (byte 2) read at %08X",addr);
92: return (nbic.id>>8);
93: }
1.1.1.2 ! root 94: static Uint8 nbic_id_read3(Uint32 addr) {
1.1 root 95: Log_Printf(LOG_WARN, "[NBIC] ID (byte 3) read at %08X",addr);
96: return nbic.id;
97: }
98:
1.1.1.2 ! root 99: static void nbic_id_write0(Uint32 addr, Uint8 val) {
1.1 root 100: Log_Printf(LOG_WARN, "[NBIC] ID (byte 0) write %02X at %08X",val,addr);
101: nbic.id &= 0x00FFFFFF;
102: nbic.id |= (val&0xFF)<<24;
103: }
1.1.1.2 ! root 104: static void nbic_id_write1(Uint32 addr, Uint8 val) {
1.1 root 105: Log_Printf(LOG_WARN, "[NBIC] ID (byte 1) write %02X at %08X",val,addr);
106: nbic.id &= 0xFF00FFFF;
107: nbic.id |= (val&0xFF)<<16;
108: }
1.1.1.2 ! root 109: static void nbic_id_write2(Uint32 addr, Uint8 val) {
1.1 root 110: Log_Printf(LOG_WARN, "[NBIC] ID (byte 2) write %02X at %08X",val,addr);
111: nbic.id &= 0xFFFF00FF;
112: nbic.id |= (val&0xFF)<<8;
113: }
1.1.1.2 ! root 114: static void nbic_id_write3(Uint32 addr, Uint8 val) {
1.1 root 115: Log_Printf(LOG_WARN, "[NBIC] ID (byte 3) write %02X at %08X",val,addr);
116: nbic.id &= 0xFFFFFF00;
117: nbic.id |= val&0xFF;
118: }
119:
1.1.1.2 ! root 120: static Uint8 nbic_intstatus_read(Uint32 addr) {
1.1 root 121: Log_Printf(LOG_WARN, "[NBIC] Interrupt status read at %08X",addr);
122: return nbic.intstatus;
123: }
124:
1.1.1.2 ! root 125: static Uint8 nbic_intmask_read(Uint32 addr) {
1.1 root 126: Log_Printf(LOG_WARN, "[NBIC] Interrupt mask read at %08X",addr);
127: return nbic.intmask;
128: }
1.1.1.2 ! root 129: static void nbic_intmask_write(Uint32 addr, Uint8 val) {
1.1 root 130: Log_Printf(LOG_WARN, "[NBIC] Interrupt mask write %02X at %08X",val,addr);
131: nbic.intmask = val;
132: }
133:
1.1.1.2 ! root 134: static Uint8 nbic_zero_read(Uint32 addr) {
1.1 root 135: Log_Printf(LOG_WARN, "[NBIC] zero read at %08X",addr);
136: return 0;
137: }
1.1.1.2 ! root 138: static void nbic_zero_write(Uint32 addr, Uint8 val) {
1.1 root 139: Log_Printf(LOG_WARN, "[NBIC] zero write %02X at %08X",val,addr);
140: }
141:
1.1.1.2 ! root 142: static Uint8 nbic_bus_error_read(Uint32 addr) {
1.1 root 143: Log_Printf(LOG_WARN, "[NBIC] bus error read at %08X",addr);
144: M68000_BusError(addr, 1);
145: return 0;
146: }
1.1.1.2 ! root 147: static void nbic_bus_error_write(Uint32 addr, Uint8 val) {
1.1 root 148: Log_Printf(LOG_WARN, "[NBIC] bus error write at %08X",addr);
149: M68000_BusError(addr, 0);
150: }
151:
152:
153: /* Direct register access */
154: static Uint8 (*nbic_read_reg[8])(Uint32) = {
155: nbic_control_read0, nbic_control_read1, nbic_control_read2, nbic_control_read3,
156: nbic_bus_error_read, nbic_bus_error_read, nbic_bus_error_read, nbic_bus_error_read
157: };
158:
159: static void (*nbic_write_reg[8])(Uint32, Uint8) = {
160: nbic_control_write0, nbic_control_write1, nbic_control_write2, nbic_control_write3,
161: nbic_id_write0, nbic_id_write1, nbic_id_write2, nbic_id_write3
162: };
163:
164:
165: Uint32 nbic_reg_lget(Uint32 addr) {
166: Uint32 val = 0;
167:
168: if (addr&3) {
169: Log_Printf(LOG_WARN, "[NBIC] Unaligned access at %08X.",addr);
170: abort();
171: }
172:
173: if ((addr&0x0000FFFF)>7) {
174: nbic_bus_error_read(addr);
175: } else {
176: val = nbic_read_reg[addr&7](addr)<<24;
177: val |= nbic_read_reg[(addr&7)+1](addr+1)<<16;
178: val |= nbic_read_reg[(addr&7)+2](addr+2)<<8;
179: val |= nbic_read_reg[(addr&7)+3](addr+3);
180: }
181:
182: return val;
183: }
184:
185: Uint32 nbic_reg_wget(uaecptr addr) {
186: Uint32 val = 0;
187:
188: if (addr&1) {
189: Log_Printf(LOG_WARN, "[NBIC] Unaligned access at %08X.",addr);
190: abort();
191: }
192:
193: if ((addr&0x0000FFFF)>7) {
194: nbic_bus_error_read(addr);
195: } else {
196: val = nbic_read_reg[addr&7](addr)<<8;
197: val |= nbic_read_reg[(addr&7)+1](addr);
198: }
199:
200: return val;
201: }
202:
203: Uint32 nbic_reg_bget(uaecptr addr) {
204: if ((addr&0x0000FFFF)>7) {
205: return nbic_bus_error_read(addr);
206: } else {
207: return nbic_read_reg[addr&7](addr);
208: }
209: }
210:
211: void nbic_reg_lput(uaecptr addr, Uint32 l) {
212: if (addr&3) {
213: Log_Printf(LOG_WARN, "[NBIC] Unaligned access at %08X.",addr);
214: abort();
215: }
216:
217: if ((addr&0x0000FFFF)>7) {
218: nbic_bus_error_write(addr,0);
219: } else {
220: nbic_write_reg[addr&7](addr,l>>24);
221: nbic_write_reg[(addr&7)+1](addr,l>>16);
222: nbic_write_reg[(addr&7)+2](addr,l>>8);
223: nbic_write_reg[(addr&7)+3](addr,l);
224: }
225: }
226:
227: void nbic_reg_wput(uaecptr addr, Uint32 w) {
228: if (addr&1) {
229: Log_Printf(LOG_WARN, "[NBIC] Unaligned access at %08X.",addr);
230: abort();
231: }
232:
233: if ((addr&0x0000FFFF)>7) {
234: nbic_bus_error_write(addr,0);
235: } else {
236: nbic_write_reg[addr&7](addr,w>>8);
237: nbic_write_reg[(addr&7)+1](addr,w);
238: }
239: }
240:
241: void nbic_reg_bput(uaecptr addr, Uint32 b) {
242: if ((addr&0x0000FFFF)>7) {
243: nbic_bus_error_write(addr,0);
244: } else {
245: nbic_write_reg[addr&7](addr,b);
246: }
247: }
248:
249:
250: /* NeXTbus CPU board slot space access */
251: static Uint8 (*nbic_read_cpu_slot[32])(Uint32) = {
252: nbic_bus_error_read, nbic_bus_error_read, nbic_bus_error_read, nbic_bus_error_read,
253: nbic_bus_error_read, nbic_bus_error_read, nbic_bus_error_read, nbic_bus_error_read,
254: nbic_intstatus_read, nbic_zero_read, nbic_zero_read, nbic_zero_read,
255: nbic_intmask_read, nbic_zero_read, nbic_zero_read, nbic_zero_read,
256:
257: nbic_id_read0, nbic_zero_read, nbic_zero_read, nbic_zero_read,
258: nbic_id_read1, nbic_zero_read, nbic_zero_read, nbic_zero_read,
259: nbic_id_read2, nbic_zero_read, nbic_zero_read, nbic_zero_read,
260: nbic_id_read3, nbic_zero_read, nbic_zero_read, nbic_zero_read,
261: };
262:
263: static void (*nbic_write_cpu_slot[32])(Uint32, Uint8) = {
264: nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write,
265: nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write,
266: nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write,
267: nbic_intmask_write, nbic_zero_write, nbic_zero_write, nbic_zero_write,
268:
269: nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write,
270: nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write,
271: nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write,
272: nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write, nbic_bus_error_write
273: };
274:
1.1.1.2 ! root 275: static Uint32 nb_cpu_slot_lget(Uint32 addr) {
1.1 root 276: Uint32 val = 0;
277:
278: if (addr&3) {
279: Log_Printf(LOG_WARN, "[NBIC] Unaligned access at %08X.",addr);
280: abort();
281: }
282:
283: if ((addr&0x00FFFFFF)<0x00FFFFE8) {
284: nbic_bus_error_read(addr);
285: } else {
286: val = nbic_read_cpu_slot[addr&0x1F](addr)<<24;
287: val |= nbic_read_cpu_slot[(addr&0x1F)+1](addr+1)<<16;
288: val |= nbic_read_cpu_slot[(addr&0x1F)+2](addr+2)<<8;
289: val |= nbic_read_cpu_slot[(addr&0x1F)+3](addr+3);
290: }
291:
292: return val;
293: }
294:
1.1.1.2 ! root 295: static Uint16 nb_cpu_slot_wget(Uint32 addr) {
1.1 root 296: Uint32 val = 0;
297:
298: if (addr&1) {
299: Log_Printf(LOG_WARN, "[NBIC] Unaligned access at %08X.",addr);
300: abort();
301: }
302:
303: if ((addr&0x00FFFFFF)<0x00FFFFE8) {
304: nbic_bus_error_read(addr);
305: } else {
306: val = nbic_read_cpu_slot[addr&0x1F](addr)<<8;
307: val |= nbic_read_cpu_slot[(addr&0x1F)+1](addr+1)<<16;
308: }
309:
310: return val;
311: }
312:
1.1.1.2 ! root 313: static Uint8 nb_cpu_slot_bget(Uint32 addr) {
1.1 root 314: if ((addr&0x00FFFFFF)<0x00FFFFE8) {
315: return nbic_bus_error_read(addr);
316: } else {
317: return nbic_read_cpu_slot[addr&0x1F](addr);
318: }
319: }
320:
1.1.1.2 ! root 321: static void nb_cpu_slot_lput(Uint32 addr, Uint32 l) {
1.1 root 322: if (addr&3) {
323: Log_Printf(LOG_WARN, "[NBIC] Unaligned access at %08X.",addr);
324: abort();
325: }
326:
327: if ((addr&0x00FFFFFF)<0x00FFFFE8) {
328: nbic_bus_error_write(addr,0);
329: } else {
330: nbic_write_cpu_slot[addr&0x1F](addr,l>>24);
331: nbic_write_cpu_slot[(addr&0x1F)+1](addr,l>>16);
332: nbic_write_cpu_slot[(addr&0x1F)+2](addr,l>>8);
333: nbic_write_cpu_slot[(addr&0x1F)+3](addr,l);
334: }
335: }
336:
1.1.1.2 ! root 337: static void nb_cpu_slot_wput(Uint32 addr, Uint16 w) {
1.1 root 338: if (addr&1) {
339: Log_Printf(LOG_WARN, "[NBIC] Unaligned access at %08X.",addr);
340: abort();
341: }
342:
343: if ((addr&0x00FFFFFF)<0x00FFFFE8) {
344: nbic_bus_error_write(addr,0);
345: } else {
346: nbic_write_cpu_slot[addr&0x1F](addr,w>>8);
347: nbic_write_cpu_slot[(addr&0x1F)+1](addr,w);
348: }
349: }
350:
1.1.1.2 ! root 351: static void nb_cpu_slot_bput(Uint32 addr, Uint8 b) {
1.1 root 352: if ((addr&0x00FFFFFF)<0x00FFFFE8) {
353: nbic_bus_error_write(addr,0);
354: } else {
355: nbic_write_cpu_slot[addr&0x1F](addr,b);
356: }
357: }
358:
359:
360: /* NeXTbus timeout functions */
1.1.1.2 ! root 361: static Uint32 nb_timeout_lget(Uint32 addr) {
1.1 root 362: Log_Printf(LOG_WARN, "[NextBus] Bus error lget at %08X",addr);
363:
364: M68000_BusError(addr, 1);
365: return 0;
366: }
367:
1.1.1.2 ! root 368: static Uint16 nb_timeout_wget(Uint32 addr) {
1.1 root 369: Log_Printf(LOG_WARN, "[NextBus] Bus error wget at %08X",addr);
370:
371: M68000_BusError(addr, 1);
372: return 0;
373: }
374:
1.1.1.2 ! root 375: static Uint8 nb_timeout_bget(Uint32 addr) {
1.1 root 376: Log_Printf(LOG_WARN, "[NextBus] Bus error bget at %08X",addr);
377:
378: M68000_BusError(addr, 1);
379: return 0;
380: }
381:
1.1.1.2 ! root 382: static void nb_timeout_lput(Uint32 addr, Uint32 l) {
1.1 root 383: Log_Printf(LOG_WARN, "[NextBus] Bus error lput at %08X",addr);
384:
385: M68000_BusError(addr, 0);
386: }
387:
1.1.1.2 ! root 388: static void nb_timeout_wput(Uint32 addr, Uint16 w) {
1.1 root 389: Log_Printf(LOG_WARN, "[NextBus] Bus error lput at %08X",addr);
390:
391: M68000_BusError(addr, 0);
392: }
393:
1.1.1.2 ! root 394: static void nb_timeout_bput(Uint32 addr, Uint8 b) {
1.1 root 395: Log_Printf(LOG_WARN, "[NextBus] Bus error lput at %08X",addr);
396:
397: M68000_BusError(addr, 0);
398: }
399:
400:
401: /* Board access via NeXTbus */
402:
403: typedef struct {
404: Uint32 (*lget)(Uint32 addr);
405: Uint16 (*wget)(Uint32 addr);
406: Uint8 (*bget)(Uint32 addr);
407: void (*lput)(Uint32 addr, Uint32 val);
408: void (*wput)(Uint32 addr, Uint16 val);
409: void (*bput)(Uint32 addr, Uint8 val);
410: } nextbus_access_funcs;
411:
412: /* Board space access functions */
413: static nextbus_access_funcs nextbus_board[NUM_SLOTS] = {
414: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
415: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
416: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
417: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
418: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
419: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
420: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
421: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
422: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
423: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
424: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
425: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
426: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
427: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
428: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
429: };
430:
431: /* Slot space access functions */
432: static nextbus_access_funcs nextbus_slot[16] = {
433: { nb_cpu_slot_lget, nb_cpu_slot_wget, nb_cpu_slot_bget, nb_cpu_slot_lput, nb_cpu_slot_wput, nb_cpu_slot_bput },
434: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
435: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
436: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
437: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
438: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
439: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
440: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
441: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
442: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
443: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
444: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
445: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
446: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
447: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput },
448: { nb_timeout_lget, nb_timeout_wget, nb_timeout_bget, nb_timeout_lput, nb_timeout_wput, nb_timeout_bput }
449: };
450:
451:
452: /* Slot memory */
453: Uint32 nextbus_slot_lget(Uint32 addr) {
454: int slot;
455: slot = (addr & 0x0F000000)>>24;
456: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Slot %i: lget at %08X",slot,addr);
457:
458: return nextbus_slot[slot].lget(addr);
459: }
460:
461: Uint32 nextbus_slot_wget(Uint32 addr) {
462: int slot;
463: slot = (addr & 0x0F000000)>>24;
464: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Slot %i: wget at %08X",slot,addr);
465:
466: return nextbus_slot[slot].wget(addr);
467: }
468:
469: Uint32 nextbus_slot_bget(Uint32 addr) {
470: int slot;
471: slot = (addr & 0x0F000000)>>24;
472: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Slot %i: bget at %08X",slot,addr);
473:
474: return nextbus_slot[slot].bget(addr);
475: }
476:
477: void nextbus_slot_lput(Uint32 addr, Uint32 val) {
478: int slot;
479: slot = (addr & 0x0F000000)>>24;
480: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Slot %i: lput at %08X, val %08X",slot,addr,val);
481:
482: nextbus_slot[slot].lput(addr, val);
483: }
484:
485: void nextbus_slot_wput(Uint32 addr, Uint32 val) {
486: int slot;
487: slot = (addr & 0x0F000000)>>24;
488: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Slot %i: wput at %08X, val %04X",slot,addr,val);
489:
490: nextbus_slot[slot].wput(addr, val);
491: }
492:
493: void nextbus_slot_bput(Uint32 addr, Uint32 val) {
494: int slot;
495: slot = (addr & 0x0F000000)>>24;
496: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Slot %i: bput at %08X, val %02X",slot,addr,val);
497:
498: nextbus_slot[slot].bput(addr, val);
499: }
500:
501: /* Board memory */
502: Uint32 nextbus_board_lget(Uint32 addr) {
503: int slot;
504: slot = (addr & 0xF0000000)>>28;
505: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Board %i: lget at %08X",slot,addr);
506:
507: return nextbus_board[slot].lget(addr);
508: }
509:
510: Uint32 nextbus_board_wget(Uint32 addr) {
511: int slot;
512: slot = (addr & 0xF0000000)>>28;
513: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Board %i: wget at %08X",slot,addr);
514:
515: return nextbus_board[slot].wget(addr);
516: }
517:
518: Uint32 nextbus_board_bget(Uint32 addr) {
519: int slot;
520: slot = (addr & 0xF0000000)>>28;
521: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Board %i: bget at %08X",slot,addr);
522:
523: return nextbus_board[slot].bget(addr);
524: }
525:
526: void nextbus_board_lput(Uint32 addr, Uint32 val) {
527: int slot;
528: slot = (addr & 0xF0000000)>>28;
529: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Board %i: lput at %08X, val %08X",slot,addr,val);
530:
531: nextbus_board[slot].lput(addr, val);
532: }
533:
534: void nextbus_board_wput(Uint32 addr, Uint32 val) {
535: int slot;
536: slot = (addr & 0xF0000000)>>28;
537: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Board %i: wput at %08X, val %04X",slot,addr,val);
538:
539: nextbus_board[slot].wput(addr, val);
540: }
541:
542: void nextbus_board_bput(Uint32 addr, Uint32 val) {
543: int slot;
544: slot = (addr & 0xF0000000)>>28;
545: Log_Printf(LOG_NEXTBUS_LEVEL, "[NextBus] Board %i: bput at %08X, val %02X",slot,addr,val);
546:
547: nextbus_board[slot].bput(addr, val);
548: }
549:
550: /* Init function for NextBus */
551: void nextbus_init(void) {
1.1.1.2 ! root 552: if (ConfigureParams.Dimension.bEnabled && (ConfigureParams.System.nMachineType == NEXT_CUBE030 || ConfigureParams.System.nMachineType == NEXT_CUBE040)) {
1.1 root 553: Log_Printf(LOG_WARN, "[NextBus/ND] board at slot %i",ND_SLOT);
554:
555: nextbus_board[ND_SLOT].lget = nd_board_lget;
556: nextbus_board[ND_SLOT].wget = nd_board_wget;
557: nextbus_board[ND_SLOT].bget = nd_board_bget;
558: nextbus_board[ND_SLOT].lput = nd_board_lput;
559: nextbus_board[ND_SLOT].wput = nd_board_wput;
560: nextbus_board[ND_SLOT].bput = nd_board_bput;
561: nextbus_slot[ND_SLOT].lget = nd_slot_lget;
562: nextbus_slot[ND_SLOT].wget = nd_slot_wget;
563: nextbus_slot[ND_SLOT].bget = nd_slot_bget;
564: nextbus_slot[ND_SLOT].lput = nd_slot_lput;
565: nextbus_slot[ND_SLOT].wput = nd_slot_wput;
566: nextbus_slot[ND_SLOT].bput = nd_slot_bput;
567:
568: dimension_init();
569: } else {
570: nextbus_board[ND_SLOT].lget = nb_timeout_lget;
571: nextbus_board[ND_SLOT].wget = nb_timeout_wget;
572: nextbus_board[ND_SLOT].bget = nb_timeout_bget;
573: nextbus_board[ND_SLOT].lput = nb_timeout_lput;
574: nextbus_board[ND_SLOT].wput = nb_timeout_wput;
575: nextbus_board[ND_SLOT].bput = nb_timeout_bput;
576: nextbus_slot[ND_SLOT].lget = nb_timeout_lget;
577: nextbus_slot[ND_SLOT].wget = nb_timeout_wget;
578: nextbus_slot[ND_SLOT].bget = nb_timeout_bget;
579: nextbus_slot[ND_SLOT].lput = nb_timeout_lput;
580: nextbus_slot[ND_SLOT].wput = nb_timeout_wput;
581: nextbus_slot[ND_SLOT].bput = nb_timeout_bput;
582:
583: dimension_uninit();
584: }
585: }
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