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1.1 root 1: #include "sysdeps.h"
2: #include "hatari-glue.h"
3: #include "maccess.h"
4: #include "memory.h"
5: #include "newcpu.h"
6: #include "cputbl.h"
7: #define CPUFUNC(x) x##_ff
8: #ifdef NOFLAGS
9: #include "noflags.h"
10: #endif
11:
12: #if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
13: #define PART_1 1
14: #define PART_2 1
15: #define PART_3 1
16: #define PART_4 1
17: #define PART_5 1
18: #define PART_6 1
19: #define PART_7 1
20: #define PART_8 1
21: #endif
22:
23: #ifdef PART_1
24: unsigned long REGPARAM2 CPUFUNC(op_0_0)(uae_u32 opcode) /* OR */
25: {
26: uae_u32 dstreg = opcode & 7;
27: OpcodeFamily = 1; CurrentInstrCycles = 8;
28: {{ uae_s8 src = get_ibyte(2);
29: { uae_s8 dst = m68k_dreg(regs, dstreg);
30: src |= dst;
31: CLEAR_CZNV;
32: SET_ZFLG (((uae_s8)(src)) == 0);
33: SET_NFLG (((uae_s8)(src)) < 0);
34: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
35: }}}m68k_incpc(4);
36: return 8;
37: }
38: unsigned long REGPARAM2 CPUFUNC(op_10_0)(uae_u32 opcode) /* OR */
39: {
40: uae_u32 dstreg = opcode & 7;
41: OpcodeFamily = 1; CurrentInstrCycles = 16;
42: {{ uae_s8 src = get_ibyte(2);
43: { uaecptr dsta = m68k_areg(regs, dstreg);
44: { uae_s8 dst = get_byte(dsta);
45: src |= dst;
46: CLEAR_CZNV;
47: SET_ZFLG (((uae_s8)(src)) == 0);
48: SET_NFLG (((uae_s8)(src)) < 0);
49: put_byte(dsta,src);
50: }}}}m68k_incpc(4);
51: return 16;
52: }
53: unsigned long REGPARAM2 CPUFUNC(op_18_0)(uae_u32 opcode) /* OR */
54: {
55: uae_u32 dstreg = opcode & 7;
56: OpcodeFamily = 1; CurrentInstrCycles = 16;
57: {{ uae_s8 src = get_ibyte(2);
58: { uaecptr dsta = m68k_areg(regs, dstreg);
59: { uae_s8 dst = get_byte(dsta);
60: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
61: src |= dst;
62: CLEAR_CZNV;
63: SET_ZFLG (((uae_s8)(src)) == 0);
64: SET_NFLG (((uae_s8)(src)) < 0);
65: put_byte(dsta,src);
66: }}}}m68k_incpc(4);
67: return 16;
68: }
69: unsigned long REGPARAM2 CPUFUNC(op_20_0)(uae_u32 opcode) /* OR */
70: {
71: uae_u32 dstreg = opcode & 7;
72: OpcodeFamily = 1; CurrentInstrCycles = 18;
73: {{ uae_s8 src = get_ibyte(2);
74: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
75: { uae_s8 dst = get_byte(dsta);
76: m68k_areg (regs, dstreg) = dsta;
77: src |= dst;
78: CLEAR_CZNV;
79: SET_ZFLG (((uae_s8)(src)) == 0);
80: SET_NFLG (((uae_s8)(src)) < 0);
81: put_byte(dsta,src);
82: }}}}m68k_incpc(4);
83: return 18;
84: }
85: unsigned long REGPARAM2 CPUFUNC(op_28_0)(uae_u32 opcode) /* OR */
86: {
87: uae_u32 dstreg = opcode & 7;
88: OpcodeFamily = 1; CurrentInstrCycles = 20;
89: {{ uae_s8 src = get_ibyte(2);
90: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
91: { uae_s8 dst = get_byte(dsta);
92: src |= dst;
93: CLEAR_CZNV;
94: SET_ZFLG (((uae_s8)(src)) == 0);
95: SET_NFLG (((uae_s8)(src)) < 0);
96: put_byte(dsta,src);
97: }}}}m68k_incpc(6);
98: return 20;
99: }
100: unsigned long REGPARAM2 CPUFUNC(op_30_0)(uae_u32 opcode) /* OR */
101: {
102: uae_u32 dstreg = opcode & 7;
103: OpcodeFamily = 1; CurrentInstrCycles = 22;
104: {{ uae_s8 src = get_ibyte(2);
105: {m68k_incpc(4);
106: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
107: BusCyclePenalty += 2;
108: { uae_s8 dst = get_byte(dsta);
109: src |= dst;
110: CLEAR_CZNV;
111: SET_ZFLG (((uae_s8)(src)) == 0);
112: SET_NFLG (((uae_s8)(src)) < 0);
113: put_byte(dsta,src);
114: }}}}}return 22;
115: }
116: unsigned long REGPARAM2 CPUFUNC(op_38_0)(uae_u32 opcode) /* OR */
117: {
118: OpcodeFamily = 1; CurrentInstrCycles = 20;
119: {{ uae_s8 src = get_ibyte(2);
120: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
121: { uae_s8 dst = get_byte(dsta);
122: src |= dst;
123: CLEAR_CZNV;
124: SET_ZFLG (((uae_s8)(src)) == 0);
125: SET_NFLG (((uae_s8)(src)) < 0);
126: put_byte(dsta,src);
127: }}}}m68k_incpc(6);
128: return 20;
129: }
130: unsigned long REGPARAM2 CPUFUNC(op_39_0)(uae_u32 opcode) /* OR */
131: {
132: OpcodeFamily = 1; CurrentInstrCycles = 24;
133: {{ uae_s8 src = get_ibyte(2);
134: { uaecptr dsta = get_ilong(4);
135: { uae_s8 dst = get_byte(dsta);
136: src |= dst;
137: CLEAR_CZNV;
138: SET_ZFLG (((uae_s8)(src)) == 0);
139: SET_NFLG (((uae_s8)(src)) < 0);
140: put_byte(dsta,src);
141: }}}}m68k_incpc(8);
142: return 24;
143: }
144: unsigned long REGPARAM2 CPUFUNC(op_3c_0)(uae_u32 opcode) /* ORSR */
145: {
146: OpcodeFamily = 4; CurrentInstrCycles = 20;
147: { MakeSR();
148: { uae_s16 src = get_iword(2);
149: src &= 0xFF;
150: regs.sr |= src;
151: MakeFromSR();
152: }}m68k_incpc(4);
153: return 20;
154: }
155: unsigned long REGPARAM2 CPUFUNC(op_40_0)(uae_u32 opcode) /* OR */
156: {
157: uae_u32 dstreg = opcode & 7;
158: OpcodeFamily = 1; CurrentInstrCycles = 8;
159: {{ uae_s16 src = get_iword(2);
160: { uae_s16 dst = m68k_dreg(regs, dstreg);
161: src |= dst;
162: CLEAR_CZNV;
163: SET_ZFLG (((uae_s16)(src)) == 0);
164: SET_NFLG (((uae_s16)(src)) < 0);
165: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
166: }}}m68k_incpc(4);
167: return 8;
168: }
169: unsigned long REGPARAM2 CPUFUNC(op_50_0)(uae_u32 opcode) /* OR */
170: {
171: uae_u32 dstreg = opcode & 7;
172: OpcodeFamily = 1; CurrentInstrCycles = 16;
173: {{ uae_s16 src = get_iword(2);
174: { uaecptr dsta = m68k_areg(regs, dstreg);
175: { uae_s16 dst = get_word(dsta);
176: src |= dst;
177: CLEAR_CZNV;
178: SET_ZFLG (((uae_s16)(src)) == 0);
179: SET_NFLG (((uae_s16)(src)) < 0);
180: put_word(dsta,src);
181: }}}}m68k_incpc(4);
182: return 16;
183: }
184: unsigned long REGPARAM2 CPUFUNC(op_58_0)(uae_u32 opcode) /* OR */
185: {
186: uae_u32 dstreg = opcode & 7;
187: OpcodeFamily = 1; CurrentInstrCycles = 16;
188: {{ uae_s16 src = get_iword(2);
189: { uaecptr dsta = m68k_areg(regs, dstreg);
190: { uae_s16 dst = get_word(dsta);
191: m68k_areg(regs, dstreg) += 2;
192: src |= dst;
193: CLEAR_CZNV;
194: SET_ZFLG (((uae_s16)(src)) == 0);
195: SET_NFLG (((uae_s16)(src)) < 0);
196: put_word(dsta,src);
197: }}}}m68k_incpc(4);
198: return 16;
199: }
200: unsigned long REGPARAM2 CPUFUNC(op_60_0)(uae_u32 opcode) /* OR */
201: {
202: uae_u32 dstreg = opcode & 7;
203: OpcodeFamily = 1; CurrentInstrCycles = 18;
204: {{ uae_s16 src = get_iword(2);
205: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
206: { uae_s16 dst = get_word(dsta);
207: m68k_areg (regs, dstreg) = dsta;
208: src |= dst;
209: CLEAR_CZNV;
210: SET_ZFLG (((uae_s16)(src)) == 0);
211: SET_NFLG (((uae_s16)(src)) < 0);
212: put_word(dsta,src);
213: }}}}m68k_incpc(4);
214: return 18;
215: }
216: unsigned long REGPARAM2 CPUFUNC(op_68_0)(uae_u32 opcode) /* OR */
217: {
218: uae_u32 dstreg = opcode & 7;
219: OpcodeFamily = 1; CurrentInstrCycles = 20;
220: {{ uae_s16 src = get_iword(2);
221: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
222: { uae_s16 dst = get_word(dsta);
223: src |= dst;
224: CLEAR_CZNV;
225: SET_ZFLG (((uae_s16)(src)) == 0);
226: SET_NFLG (((uae_s16)(src)) < 0);
227: put_word(dsta,src);
228: }}}}m68k_incpc(6);
229: return 20;
230: }
231: unsigned long REGPARAM2 CPUFUNC(op_70_0)(uae_u32 opcode) /* OR */
232: {
233: uae_u32 dstreg = opcode & 7;
234: OpcodeFamily = 1; CurrentInstrCycles = 22;
235: {{ uae_s16 src = get_iword(2);
236: {m68k_incpc(4);
237: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
238: BusCyclePenalty += 2;
239: { uae_s16 dst = get_word(dsta);
240: src |= dst;
241: CLEAR_CZNV;
242: SET_ZFLG (((uae_s16)(src)) == 0);
243: SET_NFLG (((uae_s16)(src)) < 0);
244: put_word(dsta,src);
245: }}}}}return 22;
246: }
247: unsigned long REGPARAM2 CPUFUNC(op_78_0)(uae_u32 opcode) /* OR */
248: {
249: OpcodeFamily = 1; CurrentInstrCycles = 20;
250: {{ uae_s16 src = get_iword(2);
251: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
252: { uae_s16 dst = get_word(dsta);
253: src |= dst;
254: CLEAR_CZNV;
255: SET_ZFLG (((uae_s16)(src)) == 0);
256: SET_NFLG (((uae_s16)(src)) < 0);
257: put_word(dsta,src);
258: }}}}m68k_incpc(6);
259: return 20;
260: }
261: unsigned long REGPARAM2 CPUFUNC(op_79_0)(uae_u32 opcode) /* OR */
262: {
263: OpcodeFamily = 1; CurrentInstrCycles = 24;
264: {{ uae_s16 src = get_iword(2);
265: { uaecptr dsta = get_ilong(4);
266: { uae_s16 dst = get_word(dsta);
267: src |= dst;
268: CLEAR_CZNV;
269: SET_ZFLG (((uae_s16)(src)) == 0);
270: SET_NFLG (((uae_s16)(src)) < 0);
271: put_word(dsta,src);
272: }}}}m68k_incpc(8);
273: return 24;
274: }
275: unsigned long REGPARAM2 CPUFUNC(op_7c_0)(uae_u32 opcode) /* ORSR */
276: {
277: OpcodeFamily = 4; CurrentInstrCycles = 20;
278: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel18; }
279: { MakeSR();
280: { uae_s16 src = get_iword(2);
281: regs.sr |= src;
282: MakeFromSR();
283: }}}m68k_incpc(4);
284: endlabel18: ;
285: return 20;
286: }
287: unsigned long REGPARAM2 CPUFUNC(op_80_0)(uae_u32 opcode) /* OR */
288: {
289: uae_u32 dstreg = opcode & 7;
290: OpcodeFamily = 1; CurrentInstrCycles = 16;
291: {{ uae_s32 src = get_ilong(2);
292: { uae_s32 dst = m68k_dreg(regs, dstreg);
293: src |= dst;
294: CLEAR_CZNV;
295: SET_ZFLG (((uae_s32)(src)) == 0);
296: SET_NFLG (((uae_s32)(src)) < 0);
297: m68k_dreg(regs, dstreg) = (src);
298: }}}m68k_incpc(6);
299: return 16;
300: }
301: unsigned long REGPARAM2 CPUFUNC(op_90_0)(uae_u32 opcode) /* OR */
302: {
303: uae_u32 dstreg = opcode & 7;
304: OpcodeFamily = 1; CurrentInstrCycles = 28;
305: {{ uae_s32 src = get_ilong(2);
306: { uaecptr dsta = m68k_areg(regs, dstreg);
307: { uae_s32 dst = get_long(dsta);
308: src |= dst;
309: CLEAR_CZNV;
310: SET_ZFLG (((uae_s32)(src)) == 0);
311: SET_NFLG (((uae_s32)(src)) < 0);
312: put_long(dsta,src);
313: }}}}m68k_incpc(6);
314: return 28;
315: }
316: unsigned long REGPARAM2 CPUFUNC(op_98_0)(uae_u32 opcode) /* OR */
317: {
318: uae_u32 dstreg = opcode & 7;
319: OpcodeFamily = 1; CurrentInstrCycles = 28;
320: {{ uae_s32 src = get_ilong(2);
321: { uaecptr dsta = m68k_areg(regs, dstreg);
322: { uae_s32 dst = get_long(dsta);
323: m68k_areg(regs, dstreg) += 4;
324: src |= dst;
325: CLEAR_CZNV;
326: SET_ZFLG (((uae_s32)(src)) == 0);
327: SET_NFLG (((uae_s32)(src)) < 0);
328: put_long(dsta,src);
329: }}}}m68k_incpc(6);
330: return 28;
331: }
332: unsigned long REGPARAM2 CPUFUNC(op_a0_0)(uae_u32 opcode) /* OR */
333: {
334: uae_u32 dstreg = opcode & 7;
335: OpcodeFamily = 1; CurrentInstrCycles = 30;
336: {{ uae_s32 src = get_ilong(2);
337: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
338: { uae_s32 dst = get_long(dsta);
339: m68k_areg (regs, dstreg) = dsta;
340: src |= dst;
341: CLEAR_CZNV;
342: SET_ZFLG (((uae_s32)(src)) == 0);
343: SET_NFLG (((uae_s32)(src)) < 0);
344: put_long(dsta,src);
345: }}}}m68k_incpc(6);
346: return 30;
347: }
348: unsigned long REGPARAM2 CPUFUNC(op_a8_0)(uae_u32 opcode) /* OR */
349: {
350: uae_u32 dstreg = opcode & 7;
351: OpcodeFamily = 1; CurrentInstrCycles = 32;
352: {{ uae_s32 src = get_ilong(2);
353: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
354: { uae_s32 dst = get_long(dsta);
355: src |= dst;
356: CLEAR_CZNV;
357: SET_ZFLG (((uae_s32)(src)) == 0);
358: SET_NFLG (((uae_s32)(src)) < 0);
359: put_long(dsta,src);
360: }}}}m68k_incpc(8);
361: return 32;
362: }
363: unsigned long REGPARAM2 CPUFUNC(op_b0_0)(uae_u32 opcode) /* OR */
364: {
365: uae_u32 dstreg = opcode & 7;
366: OpcodeFamily = 1; CurrentInstrCycles = 34;
367: {{ uae_s32 src = get_ilong(2);
368: {m68k_incpc(6);
369: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
370: BusCyclePenalty += 2;
371: { uae_s32 dst = get_long(dsta);
372: src |= dst;
373: CLEAR_CZNV;
374: SET_ZFLG (((uae_s32)(src)) == 0);
375: SET_NFLG (((uae_s32)(src)) < 0);
376: put_long(dsta,src);
377: }}}}}return 34;
378: }
379: unsigned long REGPARAM2 CPUFUNC(op_b8_0)(uae_u32 opcode) /* OR */
380: {
381: OpcodeFamily = 1; CurrentInstrCycles = 32;
382: {{ uae_s32 src = get_ilong(2);
383: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
384: { uae_s32 dst = get_long(dsta);
385: src |= dst;
386: CLEAR_CZNV;
387: SET_ZFLG (((uae_s32)(src)) == 0);
388: SET_NFLG (((uae_s32)(src)) < 0);
389: put_long(dsta,src);
390: }}}}m68k_incpc(8);
391: return 32;
392: }
393: unsigned long REGPARAM2 CPUFUNC(op_b9_0)(uae_u32 opcode) /* OR */
394: {
395: OpcodeFamily = 1; CurrentInstrCycles = 36;
396: {{ uae_s32 src = get_ilong(2);
397: { uaecptr dsta = get_ilong(6);
398: { uae_s32 dst = get_long(dsta);
399: src |= dst;
400: CLEAR_CZNV;
401: SET_ZFLG (((uae_s32)(src)) == 0);
402: SET_NFLG (((uae_s32)(src)) < 0);
403: put_long(dsta,src);
404: }}}}m68k_incpc(10);
405: return 36;
406: }
407: unsigned long REGPARAM2 CPUFUNC(op_d0_0)(uae_u32 opcode) /* CHK2 */
408: {
409: uae_u32 dstreg = opcode & 7;
410: OpcodeFamily = 81; CurrentInstrCycles = 8;
411: { uaecptr oldpc = m68k_getpc();
412: { uae_s16 extra = get_iword(2);
413: { uaecptr dsta = m68k_areg(regs, dstreg);
414: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
415: lower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);
416: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
417: SET_ZFLG (upper == reg || lower == reg);
418: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
419: m68k_incpc(4);
420: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel27; }
421: }
422: }}}endlabel27: ;
423: return 8;
424: }
425: unsigned long REGPARAM2 CPUFUNC(op_e8_0)(uae_u32 opcode) /* CHK2 */
426: {
427: uae_u32 dstreg = opcode & 7;
428: OpcodeFamily = 81; CurrentInstrCycles = 12;
429: { uaecptr oldpc = m68k_getpc();
430: { uae_s16 extra = get_iword(2);
431: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
432: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
433: lower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);
434: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
435: SET_ZFLG (upper == reg || lower == reg);
436: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
437: m68k_incpc(6);
438: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel28; }
439: }
440: }}}endlabel28: ;
441: return 12;
442: }
443: unsigned long REGPARAM2 CPUFUNC(op_f0_0)(uae_u32 opcode) /* CHK2 */
444: {
445: uae_u32 dstreg = opcode & 7;
446: OpcodeFamily = 81; CurrentInstrCycles = 14;
447: { uaecptr oldpc = m68k_getpc();
448: { uae_s16 extra = get_iword(2);
449: {m68k_incpc(4);
450: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
451: BusCyclePenalty += 2;
452: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
453: lower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);
454: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
455: SET_ZFLG (upper == reg || lower == reg);
456: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
457: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel29; }
458: }
459: }}}}endlabel29: ;
460: return 14;
461: }
462: unsigned long REGPARAM2 CPUFUNC(op_f8_0)(uae_u32 opcode) /* CHK2 */
463: {
464: OpcodeFamily = 81; CurrentInstrCycles = 12;
465: { uaecptr oldpc = m68k_getpc();
466: { uae_s16 extra = get_iword(2);
467: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
468: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
469: lower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);
470: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
471: SET_ZFLG (upper == reg || lower == reg);
472: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
473: m68k_incpc(6);
474: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel30; }
475: }
476: }}}endlabel30: ;
477: return 12;
478: }
479: unsigned long REGPARAM2 CPUFUNC(op_f9_0)(uae_u32 opcode) /* CHK2 */
480: {
481: OpcodeFamily = 81; CurrentInstrCycles = 16;
482: { uaecptr oldpc = m68k_getpc();
483: { uae_s16 extra = get_iword(2);
484: { uaecptr dsta = get_ilong(4);
485: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
486: lower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);
487: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
488: SET_ZFLG (upper == reg || lower == reg);
489: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
490: m68k_incpc(8);
491: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel31; }
492: }
493: }}}endlabel31: ;
494: return 16;
495: }
496: unsigned long REGPARAM2 CPUFUNC(op_fa_0)(uae_u32 opcode) /* CHK2 */
497: {
498: uae_u32 dstreg = 2;
499: OpcodeFamily = 81; CurrentInstrCycles = 12;
500: { uaecptr oldpc = m68k_getpc();
501: { uae_s16 extra = get_iword(2);
502: { uaecptr dsta = m68k_getpc () + 4;
503: dsta += (uae_s32)(uae_s16)get_iword(4);
504: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
505: lower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);
506: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
507: SET_ZFLG (upper == reg || lower == reg);
508: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
509: m68k_incpc(6);
510: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel32; }
511: }
512: }}}endlabel32: ;
513: return 12;
514: }
515: unsigned long REGPARAM2 CPUFUNC(op_fb_0)(uae_u32 opcode) /* CHK2 */
516: {
517: uae_u32 dstreg = 3;
518: OpcodeFamily = 81; CurrentInstrCycles = 14;
519: { uaecptr oldpc = m68k_getpc();
520: { uae_s16 extra = get_iword(2);
521: {m68k_incpc(4);
522: { uaecptr tmppc = m68k_getpc();
523: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
524: BusCyclePenalty += 2;
525: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
526: lower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);
527: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
528: SET_ZFLG (upper == reg || lower == reg);
529: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
530: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel33; }
531: }
532: }}}}endlabel33: ;
533: return 14;
534: }
535: unsigned long REGPARAM2 CPUFUNC(op_100_0)(uae_u32 opcode) /* BTST */
536: {
537: uae_u32 srcreg = ((opcode >> 9) & 7);
538: uae_u32 dstreg = opcode & 7;
539: OpcodeFamily = 21; CurrentInstrCycles = 6;
540: {{ uae_s32 src = m68k_dreg(regs, srcreg);
541: { uae_s32 dst = m68k_dreg(regs, dstreg);
542: src &= 31;
543: SET_ZFLG (1 ^ ((dst >> src) & 1));
544: }}}m68k_incpc(2);
545: return 6;
546: }
547: unsigned long REGPARAM2 CPUFUNC(op_108_0)(uae_u32 opcode) /* MVPMR */
548: {
549: uae_u32 srcreg = (opcode & 7);
550: uae_u32 dstreg = (opcode >> 9) & 7;
551: OpcodeFamily = 29; CurrentInstrCycles = 16;
552: { uaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
553: { uae_u16 val = (get_byte(memp) << 8) + get_byte(memp + 2);
554: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
555: }}m68k_incpc(4);
556: return 16;
557: }
558: unsigned long REGPARAM2 CPUFUNC(op_110_0)(uae_u32 opcode) /* BTST */
559: {
560: uae_u32 srcreg = ((opcode >> 9) & 7);
561: uae_u32 dstreg = opcode & 7;
562: OpcodeFamily = 21; CurrentInstrCycles = 8;
563: {{ uae_s8 src = m68k_dreg(regs, srcreg);
564: { uaecptr dsta = m68k_areg(regs, dstreg);
565: { uae_s8 dst = get_byte(dsta);
566: src &= 7;
567: SET_ZFLG (1 ^ ((dst >> src) & 1));
568: }}}}m68k_incpc(2);
569: return 8;
570: }
571: unsigned long REGPARAM2 CPUFUNC(op_118_0)(uae_u32 opcode) /* BTST */
572: {
573: uae_u32 srcreg = ((opcode >> 9) & 7);
574: uae_u32 dstreg = opcode & 7;
575: OpcodeFamily = 21; CurrentInstrCycles = 8;
576: {{ uae_s8 src = m68k_dreg(regs, srcreg);
577: { uaecptr dsta = m68k_areg(regs, dstreg);
578: { uae_s8 dst = get_byte(dsta);
579: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
580: src &= 7;
581: SET_ZFLG (1 ^ ((dst >> src) & 1));
582: }}}}m68k_incpc(2);
583: return 8;
584: }
585: unsigned long REGPARAM2 CPUFUNC(op_120_0)(uae_u32 opcode) /* BTST */
586: {
587: uae_u32 srcreg = ((opcode >> 9) & 7);
588: uae_u32 dstreg = opcode & 7;
589: OpcodeFamily = 21; CurrentInstrCycles = 10;
590: {{ uae_s8 src = m68k_dreg(regs, srcreg);
591: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
592: { uae_s8 dst = get_byte(dsta);
593: m68k_areg (regs, dstreg) = dsta;
594: src &= 7;
595: SET_ZFLG (1 ^ ((dst >> src) & 1));
596: }}}}m68k_incpc(2);
597: return 10;
598: }
599: unsigned long REGPARAM2 CPUFUNC(op_128_0)(uae_u32 opcode) /* BTST */
600: {
601: uae_u32 srcreg = ((opcode >> 9) & 7);
602: uae_u32 dstreg = opcode & 7;
603: OpcodeFamily = 21; CurrentInstrCycles = 12;
604: {{ uae_s8 src = m68k_dreg(regs, srcreg);
605: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
606: { uae_s8 dst = get_byte(dsta);
607: src &= 7;
608: SET_ZFLG (1 ^ ((dst >> src) & 1));
609: }}}}m68k_incpc(4);
610: return 12;
611: }
612: unsigned long REGPARAM2 CPUFUNC(op_130_0)(uae_u32 opcode) /* BTST */
613: {
614: uae_u32 srcreg = ((opcode >> 9) & 7);
615: uae_u32 dstreg = opcode & 7;
616: OpcodeFamily = 21; CurrentInstrCycles = 14;
617: {{ uae_s8 src = m68k_dreg(regs, srcreg);
618: {m68k_incpc(2);
619: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
620: BusCyclePenalty += 2;
621: { uae_s8 dst = get_byte(dsta);
622: src &= 7;
623: SET_ZFLG (1 ^ ((dst >> src) & 1));
624: }}}}}return 14;
625: }
626: unsigned long REGPARAM2 CPUFUNC(op_138_0)(uae_u32 opcode) /* BTST */
627: {
628: uae_u32 srcreg = ((opcode >> 9) & 7);
629: OpcodeFamily = 21; CurrentInstrCycles = 12;
630: {{ uae_s8 src = m68k_dreg(regs, srcreg);
631: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
632: { uae_s8 dst = get_byte(dsta);
633: src &= 7;
634: SET_ZFLG (1 ^ ((dst >> src) & 1));
635: }}}}m68k_incpc(4);
636: return 12;
637: }
638: unsigned long REGPARAM2 CPUFUNC(op_139_0)(uae_u32 opcode) /* BTST */
639: {
640: uae_u32 srcreg = ((opcode >> 9) & 7);
641: OpcodeFamily = 21; CurrentInstrCycles = 16;
642: {{ uae_s8 src = m68k_dreg(regs, srcreg);
643: { uaecptr dsta = get_ilong(2);
644: { uae_s8 dst = get_byte(dsta);
645: src &= 7;
646: SET_ZFLG (1 ^ ((dst >> src) & 1));
647: }}}}m68k_incpc(6);
648: return 16;
649: }
650: unsigned long REGPARAM2 CPUFUNC(op_13a_0)(uae_u32 opcode) /* BTST */
651: {
652: uae_u32 srcreg = ((opcode >> 9) & 7);
653: uae_u32 dstreg = 2;
654: OpcodeFamily = 21; CurrentInstrCycles = 12;
655: {{ uae_s8 src = m68k_dreg(regs, srcreg);
656: { uaecptr dsta = m68k_getpc () + 2;
657: dsta += (uae_s32)(uae_s16)get_iword(2);
658: { uae_s8 dst = get_byte(dsta);
659: src &= 7;
660: SET_ZFLG (1 ^ ((dst >> src) & 1));
661: }}}}m68k_incpc(4);
662: return 12;
663: }
664: unsigned long REGPARAM2 CPUFUNC(op_13b_0)(uae_u32 opcode) /* BTST */
665: {
666: uae_u32 srcreg = ((opcode >> 9) & 7);
667: uae_u32 dstreg = 3;
668: OpcodeFamily = 21; CurrentInstrCycles = 14;
669: {{ uae_s8 src = m68k_dreg(regs, srcreg);
670: {m68k_incpc(2);
671: { uaecptr tmppc = m68k_getpc();
672: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
673: BusCyclePenalty += 2;
674: { uae_s8 dst = get_byte(dsta);
675: src &= 7;
676: SET_ZFLG (1 ^ ((dst >> src) & 1));
677: }}}}}return 14;
678: }
679: unsigned long REGPARAM2 CPUFUNC(op_13c_0)(uae_u32 opcode) /* BTST */
680: {
681: uae_u32 srcreg = ((opcode >> 9) & 7);
682: OpcodeFamily = 21; CurrentInstrCycles = 8;
683: {{ uae_s8 src = m68k_dreg(regs, srcreg);
684: { uae_s8 dst = get_ibyte(2);
685: src &= 7;
686: SET_ZFLG (1 ^ ((dst >> src) & 1));
687: }}}m68k_incpc(4);
688: return 8;
689: }
690: unsigned long REGPARAM2 CPUFUNC(op_140_0)(uae_u32 opcode) /* BCHG */
691: {
692: uae_u32 srcreg = ((opcode >> 9) & 7);
693: uae_u32 dstreg = opcode & 7;
694: OpcodeFamily = 22; CurrentInstrCycles = 8;
695: {{ uae_s32 src = m68k_dreg(regs, srcreg);
696: { uae_s32 dst = m68k_dreg(regs, dstreg);
697: src &= 31;
698: dst ^= (1 << src);
699: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
700: m68k_dreg(regs, dstreg) = (dst);
701: }}}m68k_incpc(2);
702: return 8;
703: }
704: unsigned long REGPARAM2 CPUFUNC(op_148_0)(uae_u32 opcode) /* MVPMR */
705: {
706: uae_u32 srcreg = (opcode & 7);
707: uae_u32 dstreg = (opcode >> 9) & 7;
708: OpcodeFamily = 29; CurrentInstrCycles = 24;
709: { uaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
710: { uae_u32 val = (get_byte(memp) << 24) + (get_byte(memp + 2) << 16)
711: + (get_byte(memp + 4) << 8) + get_byte(memp + 6);
712: m68k_dreg(regs, dstreg) = (val);
713: }}m68k_incpc(4);
714: return 24;
715: }
716: unsigned long REGPARAM2 CPUFUNC(op_150_0)(uae_u32 opcode) /* BCHG */
717: {
718: uae_u32 srcreg = ((opcode >> 9) & 7);
719: uae_u32 dstreg = opcode & 7;
720: OpcodeFamily = 22; CurrentInstrCycles = 12;
721: {{ uae_s8 src = m68k_dreg(regs, srcreg);
722: { uaecptr dsta = m68k_areg(regs, dstreg);
723: { uae_s8 dst = get_byte(dsta);
724: src &= 7;
725: dst ^= (1 << src);
726: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
727: put_byte(dsta,dst);
728: }}}}m68k_incpc(2);
729: return 12;
730: }
731: unsigned long REGPARAM2 CPUFUNC(op_158_0)(uae_u32 opcode) /* BCHG */
732: {
733: uae_u32 srcreg = ((opcode >> 9) & 7);
734: uae_u32 dstreg = opcode & 7;
735: OpcodeFamily = 22; CurrentInstrCycles = 12;
736: {{ uae_s8 src = m68k_dreg(regs, srcreg);
737: { uaecptr dsta = m68k_areg(regs, dstreg);
738: { uae_s8 dst = get_byte(dsta);
739: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
740: src &= 7;
741: dst ^= (1 << src);
742: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
743: put_byte(dsta,dst);
744: }}}}m68k_incpc(2);
745: return 12;
746: }
747: unsigned long REGPARAM2 CPUFUNC(op_160_0)(uae_u32 opcode) /* BCHG */
748: {
749: uae_u32 srcreg = ((opcode >> 9) & 7);
750: uae_u32 dstreg = opcode & 7;
751: OpcodeFamily = 22; CurrentInstrCycles = 14;
752: {{ uae_s8 src = m68k_dreg(regs, srcreg);
753: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
754: { uae_s8 dst = get_byte(dsta);
755: m68k_areg (regs, dstreg) = dsta;
756: src &= 7;
757: dst ^= (1 << src);
758: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
759: put_byte(dsta,dst);
760: }}}}m68k_incpc(2);
761: return 14;
762: }
763: unsigned long REGPARAM2 CPUFUNC(op_168_0)(uae_u32 opcode) /* BCHG */
764: {
765: uae_u32 srcreg = ((opcode >> 9) & 7);
766: uae_u32 dstreg = opcode & 7;
767: OpcodeFamily = 22; CurrentInstrCycles = 16;
768: {{ uae_s8 src = m68k_dreg(regs, srcreg);
769: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
770: { uae_s8 dst = get_byte(dsta);
771: src &= 7;
772: dst ^= (1 << src);
773: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
774: put_byte(dsta,dst);
775: }}}}m68k_incpc(4);
776: return 16;
777: }
778: unsigned long REGPARAM2 CPUFUNC(op_170_0)(uae_u32 opcode) /* BCHG */
779: {
780: uae_u32 srcreg = ((opcode >> 9) & 7);
781: uae_u32 dstreg = opcode & 7;
782: OpcodeFamily = 22; CurrentInstrCycles = 18;
783: {{ uae_s8 src = m68k_dreg(regs, srcreg);
784: {m68k_incpc(2);
785: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
786: BusCyclePenalty += 2;
787: { uae_s8 dst = get_byte(dsta);
788: src &= 7;
789: dst ^= (1 << src);
790: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
791: put_byte(dsta,dst);
792: }}}}}return 18;
793: }
794: unsigned long REGPARAM2 CPUFUNC(op_178_0)(uae_u32 opcode) /* BCHG */
795: {
796: uae_u32 srcreg = ((opcode >> 9) & 7);
797: OpcodeFamily = 22; CurrentInstrCycles = 16;
798: {{ uae_s8 src = m68k_dreg(regs, srcreg);
799: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
800: { uae_s8 dst = get_byte(dsta);
801: src &= 7;
802: dst ^= (1 << src);
803: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
804: put_byte(dsta,dst);
805: }}}}m68k_incpc(4);
806: return 16;
807: }
808: unsigned long REGPARAM2 CPUFUNC(op_179_0)(uae_u32 opcode) /* BCHG */
809: {
810: uae_u32 srcreg = ((opcode >> 9) & 7);
811: OpcodeFamily = 22; CurrentInstrCycles = 20;
812: {{ uae_s8 src = m68k_dreg(regs, srcreg);
813: { uaecptr dsta = get_ilong(2);
814: { uae_s8 dst = get_byte(dsta);
815: src &= 7;
816: dst ^= (1 << src);
817: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
818: put_byte(dsta,dst);
819: }}}}m68k_incpc(6);
820: return 20;
821: }
822: unsigned long REGPARAM2 CPUFUNC(op_17a_0)(uae_u32 opcode) /* BCHG */
823: {
824: uae_u32 srcreg = ((opcode >> 9) & 7);
825: uae_u32 dstreg = 2;
826: OpcodeFamily = 22; CurrentInstrCycles = 16;
827: {{ uae_s8 src = m68k_dreg(regs, srcreg);
828: { uaecptr dsta = m68k_getpc () + 2;
829: dsta += (uae_s32)(uae_s16)get_iword(2);
830: { uae_s8 dst = get_byte(dsta);
831: src &= 7;
832: dst ^= (1 << src);
833: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
834: put_byte(dsta,dst);
835: }}}}m68k_incpc(4);
836: return 16;
837: }
838: unsigned long REGPARAM2 CPUFUNC(op_17b_0)(uae_u32 opcode) /* BCHG */
839: {
840: uae_u32 srcreg = ((opcode >> 9) & 7);
841: uae_u32 dstreg = 3;
842: OpcodeFamily = 22; CurrentInstrCycles = 18;
843: {{ uae_s8 src = m68k_dreg(regs, srcreg);
844: {m68k_incpc(2);
845: { uaecptr tmppc = m68k_getpc();
846: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
847: BusCyclePenalty += 2;
848: { uae_s8 dst = get_byte(dsta);
849: src &= 7;
850: dst ^= (1 << src);
851: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
852: put_byte(dsta,dst);
853: }}}}}return 18;
854: }
855: unsigned long REGPARAM2 CPUFUNC(op_180_0)(uae_u32 opcode) /* BCLR */
856: {
857: uae_u32 srcreg = ((opcode >> 9) & 7);
858: uae_u32 dstreg = opcode & 7;
859: OpcodeFamily = 23; CurrentInstrCycles = 10;
860: {{ uae_s32 src = m68k_dreg(regs, srcreg);
861: { uae_s32 dst = m68k_dreg(regs, dstreg);
862: src &= 31;
863: SET_ZFLG (1 ^ ((dst >> src) & 1));
864: dst &= ~(1 << src);
865: m68k_dreg(regs, dstreg) = (dst);
866: if ( src < 16 ) { m68k_incpc(2); return 8; }
867: }}}m68k_incpc(2);
868: return 10;
869: }
870: unsigned long REGPARAM2 CPUFUNC(op_188_0)(uae_u32 opcode) /* MVPRM */
871: {
872: uae_u32 srcreg = ((opcode >> 9) & 7);
873: uae_u32 dstreg = opcode & 7;
874: OpcodeFamily = 28; CurrentInstrCycles = 16;
875: {{ uae_s16 src = m68k_dreg(regs, srcreg);
876: uaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
877: put_byte(memp, src >> 8); put_byte(memp + 2, src);
878: }}m68k_incpc(4);
879: return 16;
880: }
881: unsigned long REGPARAM2 CPUFUNC(op_190_0)(uae_u32 opcode) /* BCLR */
882: {
883: uae_u32 srcreg = ((opcode >> 9) & 7);
884: uae_u32 dstreg = opcode & 7;
885: OpcodeFamily = 23; CurrentInstrCycles = 12;
886: {{ uae_s8 src = m68k_dreg(regs, srcreg);
887: { uaecptr dsta = m68k_areg(regs, dstreg);
888: { uae_s8 dst = get_byte(dsta);
889: src &= 7;
890: SET_ZFLG (1 ^ ((dst >> src) & 1));
891: dst &= ~(1 << src);
892: put_byte(dsta,dst);
893: }}}}m68k_incpc(2);
894: return 12;
895: }
896: unsigned long REGPARAM2 CPUFUNC(op_198_0)(uae_u32 opcode) /* BCLR */
897: {
898: uae_u32 srcreg = ((opcode >> 9) & 7);
899: uae_u32 dstreg = opcode & 7;
900: OpcodeFamily = 23; CurrentInstrCycles = 12;
901: {{ uae_s8 src = m68k_dreg(regs, srcreg);
902: { uaecptr dsta = m68k_areg(regs, dstreg);
903: { uae_s8 dst = get_byte(dsta);
904: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
905: src &= 7;
906: SET_ZFLG (1 ^ ((dst >> src) & 1));
907: dst &= ~(1 << src);
908: put_byte(dsta,dst);
909: }}}}m68k_incpc(2);
910: return 12;
911: }
912: unsigned long REGPARAM2 CPUFUNC(op_1a0_0)(uae_u32 opcode) /* BCLR */
913: {
914: uae_u32 srcreg = ((opcode >> 9) & 7);
915: uae_u32 dstreg = opcode & 7;
916: OpcodeFamily = 23; CurrentInstrCycles = 14;
917: {{ uae_s8 src = m68k_dreg(regs, srcreg);
918: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
919: { uae_s8 dst = get_byte(dsta);
920: m68k_areg (regs, dstreg) = dsta;
921: src &= 7;
922: SET_ZFLG (1 ^ ((dst >> src) & 1));
923: dst &= ~(1 << src);
924: put_byte(dsta,dst);
925: }}}}m68k_incpc(2);
926: return 14;
927: }
928: unsigned long REGPARAM2 CPUFUNC(op_1a8_0)(uae_u32 opcode) /* BCLR */
929: {
930: uae_u32 srcreg = ((opcode >> 9) & 7);
931: uae_u32 dstreg = opcode & 7;
932: OpcodeFamily = 23; CurrentInstrCycles = 16;
933: {{ uae_s8 src = m68k_dreg(regs, srcreg);
934: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
935: { uae_s8 dst = get_byte(dsta);
936: src &= 7;
937: SET_ZFLG (1 ^ ((dst >> src) & 1));
938: dst &= ~(1 << src);
939: put_byte(dsta,dst);
940: }}}}m68k_incpc(4);
941: return 16;
942: }
943: unsigned long REGPARAM2 CPUFUNC(op_1b0_0)(uae_u32 opcode) /* BCLR */
944: {
945: uae_u32 srcreg = ((opcode >> 9) & 7);
946: uae_u32 dstreg = opcode & 7;
947: OpcodeFamily = 23; CurrentInstrCycles = 18;
948: {{ uae_s8 src = m68k_dreg(regs, srcreg);
949: {m68k_incpc(2);
950: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
951: BusCyclePenalty += 2;
952: { uae_s8 dst = get_byte(dsta);
953: src &= 7;
954: SET_ZFLG (1 ^ ((dst >> src) & 1));
955: dst &= ~(1 << src);
956: put_byte(dsta,dst);
957: }}}}}return 18;
958: }
959: unsigned long REGPARAM2 CPUFUNC(op_1b8_0)(uae_u32 opcode) /* BCLR */
960: {
961: uae_u32 srcreg = ((opcode >> 9) & 7);
962: OpcodeFamily = 23; CurrentInstrCycles = 16;
963: {{ uae_s8 src = m68k_dreg(regs, srcreg);
964: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
965: { uae_s8 dst = get_byte(dsta);
966: src &= 7;
967: SET_ZFLG (1 ^ ((dst >> src) & 1));
968: dst &= ~(1 << src);
969: put_byte(dsta,dst);
970: }}}}m68k_incpc(4);
971: return 16;
972: }
973: unsigned long REGPARAM2 CPUFUNC(op_1b9_0)(uae_u32 opcode) /* BCLR */
974: {
975: uae_u32 srcreg = ((opcode >> 9) & 7);
976: OpcodeFamily = 23; CurrentInstrCycles = 20;
977: {{ uae_s8 src = m68k_dreg(regs, srcreg);
978: { uaecptr dsta = get_ilong(2);
979: { uae_s8 dst = get_byte(dsta);
980: src &= 7;
981: SET_ZFLG (1 ^ ((dst >> src) & 1));
982: dst &= ~(1 << src);
983: put_byte(dsta,dst);
984: }}}}m68k_incpc(6);
985: return 20;
986: }
987: unsigned long REGPARAM2 CPUFUNC(op_1ba_0)(uae_u32 opcode) /* BCLR */
988: {
989: uae_u32 srcreg = ((opcode >> 9) & 7);
990: uae_u32 dstreg = 2;
991: OpcodeFamily = 23; CurrentInstrCycles = 16;
992: {{ uae_s8 src = m68k_dreg(regs, srcreg);
993: { uaecptr dsta = m68k_getpc () + 2;
994: dsta += (uae_s32)(uae_s16)get_iword(2);
995: { uae_s8 dst = get_byte(dsta);
996: src &= 7;
997: SET_ZFLG (1 ^ ((dst >> src) & 1));
998: dst &= ~(1 << src);
999: put_byte(dsta,dst);
1000: }}}}m68k_incpc(4);
1001: return 16;
1002: }
1003: unsigned long REGPARAM2 CPUFUNC(op_1bb_0)(uae_u32 opcode) /* BCLR */
1004: {
1005: uae_u32 srcreg = ((opcode >> 9) & 7);
1006: uae_u32 dstreg = 3;
1007: OpcodeFamily = 23; CurrentInstrCycles = 18;
1008: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1009: {m68k_incpc(2);
1010: { uaecptr tmppc = m68k_getpc();
1011: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
1012: BusCyclePenalty += 2;
1013: { uae_s8 dst = get_byte(dsta);
1014: src &= 7;
1015: SET_ZFLG (1 ^ ((dst >> src) & 1));
1016: dst &= ~(1 << src);
1017: put_byte(dsta,dst);
1018: }}}}}return 18;
1019: }
1020: unsigned long REGPARAM2 CPUFUNC(op_1c0_0)(uae_u32 opcode) /* BSET */
1021: {
1022: uae_u32 srcreg = ((opcode >> 9) & 7);
1023: uae_u32 dstreg = opcode & 7;
1024: OpcodeFamily = 24; CurrentInstrCycles = 8;
1025: {{ uae_s32 src = m68k_dreg(regs, srcreg);
1026: { uae_s32 dst = m68k_dreg(regs, dstreg);
1027: src &= 31;
1028: SET_ZFLG (1 ^ ((dst >> src) & 1));
1029: dst |= (1 << src);
1030: m68k_dreg(regs, dstreg) = (dst);
1031: }}}m68k_incpc(2);
1032: return 8;
1033: }
1034: unsigned long REGPARAM2 CPUFUNC(op_1c8_0)(uae_u32 opcode) /* MVPRM */
1035: {
1036: uae_u32 srcreg = ((opcode >> 9) & 7);
1037: uae_u32 dstreg = opcode & 7;
1038: OpcodeFamily = 28; CurrentInstrCycles = 24;
1039: {{ uae_s32 src = m68k_dreg(regs, srcreg);
1040: uaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
1041: put_byte(memp, src >> 24); put_byte(memp + 2, src >> 16);
1042: put_byte(memp + 4, src >> 8); put_byte(memp + 6, src);
1043: }}m68k_incpc(4);
1044: return 24;
1045: }
1046: unsigned long REGPARAM2 CPUFUNC(op_1d0_0)(uae_u32 opcode) /* BSET */
1047: {
1048: uae_u32 srcreg = ((opcode >> 9) & 7);
1049: uae_u32 dstreg = opcode & 7;
1050: OpcodeFamily = 24; CurrentInstrCycles = 12;
1051: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1052: { uaecptr dsta = m68k_areg(regs, dstreg);
1053: { uae_s8 dst = get_byte(dsta);
1054: src &= 7;
1055: SET_ZFLG (1 ^ ((dst >> src) & 1));
1056: dst |= (1 << src);
1057: put_byte(dsta,dst);
1058: }}}}m68k_incpc(2);
1059: return 12;
1060: }
1061: unsigned long REGPARAM2 CPUFUNC(op_1d8_0)(uae_u32 opcode) /* BSET */
1062: {
1063: uae_u32 srcreg = ((opcode >> 9) & 7);
1064: uae_u32 dstreg = opcode & 7;
1065: OpcodeFamily = 24; CurrentInstrCycles = 12;
1066: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1067: { uaecptr dsta = m68k_areg(regs, dstreg);
1068: { uae_s8 dst = get_byte(dsta);
1069: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
1070: src &= 7;
1071: SET_ZFLG (1 ^ ((dst >> src) & 1));
1072: dst |= (1 << src);
1073: put_byte(dsta,dst);
1074: }}}}m68k_incpc(2);
1075: return 12;
1076: }
1077: unsigned long REGPARAM2 CPUFUNC(op_1e0_0)(uae_u32 opcode) /* BSET */
1078: {
1079: uae_u32 srcreg = ((opcode >> 9) & 7);
1080: uae_u32 dstreg = opcode & 7;
1081: OpcodeFamily = 24; CurrentInstrCycles = 14;
1082: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1083: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
1084: { uae_s8 dst = get_byte(dsta);
1085: m68k_areg (regs, dstreg) = dsta;
1086: src &= 7;
1087: SET_ZFLG (1 ^ ((dst >> src) & 1));
1088: dst |= (1 << src);
1089: put_byte(dsta,dst);
1090: }}}}m68k_incpc(2);
1091: return 14;
1092: }
1093: unsigned long REGPARAM2 CPUFUNC(op_1e8_0)(uae_u32 opcode) /* BSET */
1094: {
1095: uae_u32 srcreg = ((opcode >> 9) & 7);
1096: uae_u32 dstreg = opcode & 7;
1097: OpcodeFamily = 24; CurrentInstrCycles = 16;
1098: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1099: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
1100: { uae_s8 dst = get_byte(dsta);
1101: src &= 7;
1102: SET_ZFLG (1 ^ ((dst >> src) & 1));
1103: dst |= (1 << src);
1104: put_byte(dsta,dst);
1105: }}}}m68k_incpc(4);
1106: return 16;
1107: }
1108: unsigned long REGPARAM2 CPUFUNC(op_1f0_0)(uae_u32 opcode) /* BSET */
1109: {
1110: uae_u32 srcreg = ((opcode >> 9) & 7);
1111: uae_u32 dstreg = opcode & 7;
1112: OpcodeFamily = 24; CurrentInstrCycles = 18;
1113: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1114: {m68k_incpc(2);
1115: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
1116: BusCyclePenalty += 2;
1117: { uae_s8 dst = get_byte(dsta);
1118: src &= 7;
1119: SET_ZFLG (1 ^ ((dst >> src) & 1));
1120: dst |= (1 << src);
1121: put_byte(dsta,dst);
1122: }}}}}return 18;
1123: }
1124: unsigned long REGPARAM2 CPUFUNC(op_1f8_0)(uae_u32 opcode) /* BSET */
1125: {
1126: uae_u32 srcreg = ((opcode >> 9) & 7);
1127: OpcodeFamily = 24; CurrentInstrCycles = 16;
1128: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1129: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
1130: { uae_s8 dst = get_byte(dsta);
1131: src &= 7;
1132: SET_ZFLG (1 ^ ((dst >> src) & 1));
1133: dst |= (1 << src);
1134: put_byte(dsta,dst);
1135: }}}}m68k_incpc(4);
1136: return 16;
1137: }
1138: unsigned long REGPARAM2 CPUFUNC(op_1f9_0)(uae_u32 opcode) /* BSET */
1139: {
1140: uae_u32 srcreg = ((opcode >> 9) & 7);
1141: OpcodeFamily = 24; CurrentInstrCycles = 20;
1142: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1143: { uaecptr dsta = get_ilong(2);
1144: { uae_s8 dst = get_byte(dsta);
1145: src &= 7;
1146: SET_ZFLG (1 ^ ((dst >> src) & 1));
1147: dst |= (1 << src);
1148: put_byte(dsta,dst);
1149: }}}}m68k_incpc(6);
1150: return 20;
1151: }
1152: unsigned long REGPARAM2 CPUFUNC(op_1fa_0)(uae_u32 opcode) /* BSET */
1153: {
1154: uae_u32 srcreg = ((opcode >> 9) & 7);
1155: uae_u32 dstreg = 2;
1156: OpcodeFamily = 24; CurrentInstrCycles = 16;
1157: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1158: { uaecptr dsta = m68k_getpc () + 2;
1159: dsta += (uae_s32)(uae_s16)get_iword(2);
1160: { uae_s8 dst = get_byte(dsta);
1161: src &= 7;
1162: SET_ZFLG (1 ^ ((dst >> src) & 1));
1163: dst |= (1 << src);
1164: put_byte(dsta,dst);
1165: }}}}m68k_incpc(4);
1166: return 16;
1167: }
1168: unsigned long REGPARAM2 CPUFUNC(op_1fb_0)(uae_u32 opcode) /* BSET */
1169: {
1170: uae_u32 srcreg = ((opcode >> 9) & 7);
1171: uae_u32 dstreg = 3;
1172: OpcodeFamily = 24; CurrentInstrCycles = 18;
1173: {{ uae_s8 src = m68k_dreg(regs, srcreg);
1174: {m68k_incpc(2);
1175: { uaecptr tmppc = m68k_getpc();
1176: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
1177: BusCyclePenalty += 2;
1178: { uae_s8 dst = get_byte(dsta);
1179: src &= 7;
1180: SET_ZFLG (1 ^ ((dst >> src) & 1));
1181: dst |= (1 << src);
1182: put_byte(dsta,dst);
1183: }}}}}return 18;
1184: }
1185: unsigned long REGPARAM2 CPUFUNC(op_200_0)(uae_u32 opcode) /* AND */
1186: {
1187: uae_u32 dstreg = opcode & 7;
1188: OpcodeFamily = 2; CurrentInstrCycles = 8;
1189: {{ uae_s8 src = get_ibyte(2);
1190: { uae_s8 dst = m68k_dreg(regs, dstreg);
1191: src &= dst;
1192: CLEAR_CZNV;
1193: SET_ZFLG (((uae_s8)(src)) == 0);
1194: SET_NFLG (((uae_s8)(src)) < 0);
1195: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
1196: }}}m68k_incpc(4);
1197: return 8;
1198: }
1199: unsigned long REGPARAM2 CPUFUNC(op_210_0)(uae_u32 opcode) /* AND */
1200: {
1201: uae_u32 dstreg = opcode & 7;
1202: OpcodeFamily = 2; CurrentInstrCycles = 16;
1203: {{ uae_s8 src = get_ibyte(2);
1204: { uaecptr dsta = m68k_areg(regs, dstreg);
1205: { uae_s8 dst = get_byte(dsta);
1206: src &= dst;
1207: CLEAR_CZNV;
1208: SET_ZFLG (((uae_s8)(src)) == 0);
1209: SET_NFLG (((uae_s8)(src)) < 0);
1210: put_byte(dsta,src);
1211: }}}}m68k_incpc(4);
1212: return 16;
1213: }
1214: unsigned long REGPARAM2 CPUFUNC(op_218_0)(uae_u32 opcode) /* AND */
1215: {
1216: uae_u32 dstreg = opcode & 7;
1217: OpcodeFamily = 2; CurrentInstrCycles = 16;
1218: {{ uae_s8 src = get_ibyte(2);
1219: { uaecptr dsta = m68k_areg(regs, dstreg);
1220: { uae_s8 dst = get_byte(dsta);
1221: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
1222: src &= dst;
1223: CLEAR_CZNV;
1224: SET_ZFLG (((uae_s8)(src)) == 0);
1225: SET_NFLG (((uae_s8)(src)) < 0);
1226: put_byte(dsta,src);
1227: }}}}m68k_incpc(4);
1228: return 16;
1229: }
1230: unsigned long REGPARAM2 CPUFUNC(op_220_0)(uae_u32 opcode) /* AND */
1231: {
1232: uae_u32 dstreg = opcode & 7;
1233: OpcodeFamily = 2; CurrentInstrCycles = 18;
1234: {{ uae_s8 src = get_ibyte(2);
1235: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
1236: { uae_s8 dst = get_byte(dsta);
1237: m68k_areg (regs, dstreg) = dsta;
1238: src &= dst;
1239: CLEAR_CZNV;
1240: SET_ZFLG (((uae_s8)(src)) == 0);
1241: SET_NFLG (((uae_s8)(src)) < 0);
1242: put_byte(dsta,src);
1243: }}}}m68k_incpc(4);
1244: return 18;
1245: }
1246: unsigned long REGPARAM2 CPUFUNC(op_228_0)(uae_u32 opcode) /* AND */
1247: {
1248: uae_u32 dstreg = opcode & 7;
1249: OpcodeFamily = 2; CurrentInstrCycles = 20;
1250: {{ uae_s8 src = get_ibyte(2);
1251: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
1252: { uae_s8 dst = get_byte(dsta);
1253: src &= dst;
1254: CLEAR_CZNV;
1255: SET_ZFLG (((uae_s8)(src)) == 0);
1256: SET_NFLG (((uae_s8)(src)) < 0);
1257: put_byte(dsta,src);
1258: }}}}m68k_incpc(6);
1259: return 20;
1260: }
1261: unsigned long REGPARAM2 CPUFUNC(op_230_0)(uae_u32 opcode) /* AND */
1262: {
1263: uae_u32 dstreg = opcode & 7;
1264: OpcodeFamily = 2; CurrentInstrCycles = 22;
1265: {{ uae_s8 src = get_ibyte(2);
1266: {m68k_incpc(4);
1267: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
1268: BusCyclePenalty += 2;
1269: { uae_s8 dst = get_byte(dsta);
1270: src &= dst;
1271: CLEAR_CZNV;
1272: SET_ZFLG (((uae_s8)(src)) == 0);
1273: SET_NFLG (((uae_s8)(src)) < 0);
1274: put_byte(dsta,src);
1275: }}}}}return 22;
1276: }
1277: unsigned long REGPARAM2 CPUFUNC(op_238_0)(uae_u32 opcode) /* AND */
1278: {
1279: OpcodeFamily = 2; CurrentInstrCycles = 20;
1280: {{ uae_s8 src = get_ibyte(2);
1281: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
1282: { uae_s8 dst = get_byte(dsta);
1283: src &= dst;
1284: CLEAR_CZNV;
1285: SET_ZFLG (((uae_s8)(src)) == 0);
1286: SET_NFLG (((uae_s8)(src)) < 0);
1287: put_byte(dsta,src);
1288: }}}}m68k_incpc(6);
1289: return 20;
1290: }
1291: unsigned long REGPARAM2 CPUFUNC(op_239_0)(uae_u32 opcode) /* AND */
1292: {
1293: OpcodeFamily = 2; CurrentInstrCycles = 24;
1294: {{ uae_s8 src = get_ibyte(2);
1295: { uaecptr dsta = get_ilong(4);
1296: { uae_s8 dst = get_byte(dsta);
1297: src &= dst;
1298: CLEAR_CZNV;
1299: SET_ZFLG (((uae_s8)(src)) == 0);
1300: SET_NFLG (((uae_s8)(src)) < 0);
1301: put_byte(dsta,src);
1302: }}}}m68k_incpc(8);
1303: return 24;
1304: }
1305: unsigned long REGPARAM2 CPUFUNC(op_23c_0)(uae_u32 opcode) /* ANDSR */
1306: {
1307: OpcodeFamily = 5; CurrentInstrCycles = 20;
1308: { MakeSR();
1309: { uae_s16 src = get_iword(2);
1310: src |= 0xFF00;
1311: regs.sr &= src;
1312: MakeFromSR();
1313: }}m68k_incpc(4);
1314: return 20;
1315: }
1316: unsigned long REGPARAM2 CPUFUNC(op_240_0)(uae_u32 opcode) /* AND */
1317: {
1318: uae_u32 dstreg = opcode & 7;
1319: OpcodeFamily = 2; CurrentInstrCycles = 8;
1320: {{ uae_s16 src = get_iword(2);
1321: { uae_s16 dst = m68k_dreg(regs, dstreg);
1322: src &= dst;
1323: CLEAR_CZNV;
1324: SET_ZFLG (((uae_s16)(src)) == 0);
1325: SET_NFLG (((uae_s16)(src)) < 0);
1326: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
1327: }}}m68k_incpc(4);
1328: return 8;
1329: }
1330: unsigned long REGPARAM2 CPUFUNC(op_250_0)(uae_u32 opcode) /* AND */
1331: {
1332: uae_u32 dstreg = opcode & 7;
1333: OpcodeFamily = 2; CurrentInstrCycles = 16;
1334: {{ uae_s16 src = get_iword(2);
1335: { uaecptr dsta = m68k_areg(regs, dstreg);
1336: { uae_s16 dst = get_word(dsta);
1337: src &= dst;
1338: CLEAR_CZNV;
1339: SET_ZFLG (((uae_s16)(src)) == 0);
1340: SET_NFLG (((uae_s16)(src)) < 0);
1341: put_word(dsta,src);
1342: }}}}m68k_incpc(4);
1343: return 16;
1344: }
1345: unsigned long REGPARAM2 CPUFUNC(op_258_0)(uae_u32 opcode) /* AND */
1346: {
1347: uae_u32 dstreg = opcode & 7;
1348: OpcodeFamily = 2; CurrentInstrCycles = 16;
1349: {{ uae_s16 src = get_iword(2);
1350: { uaecptr dsta = m68k_areg(regs, dstreg);
1351: { uae_s16 dst = get_word(dsta);
1352: m68k_areg(regs, dstreg) += 2;
1353: src &= dst;
1354: CLEAR_CZNV;
1355: SET_ZFLG (((uae_s16)(src)) == 0);
1356: SET_NFLG (((uae_s16)(src)) < 0);
1357: put_word(dsta,src);
1358: }}}}m68k_incpc(4);
1359: return 16;
1360: }
1361: unsigned long REGPARAM2 CPUFUNC(op_260_0)(uae_u32 opcode) /* AND */
1362: {
1363: uae_u32 dstreg = opcode & 7;
1364: OpcodeFamily = 2; CurrentInstrCycles = 18;
1365: {{ uae_s16 src = get_iword(2);
1366: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
1367: { uae_s16 dst = get_word(dsta);
1368: m68k_areg (regs, dstreg) = dsta;
1369: src &= dst;
1370: CLEAR_CZNV;
1371: SET_ZFLG (((uae_s16)(src)) == 0);
1372: SET_NFLG (((uae_s16)(src)) < 0);
1373: put_word(dsta,src);
1374: }}}}m68k_incpc(4);
1375: return 18;
1376: }
1377: unsigned long REGPARAM2 CPUFUNC(op_268_0)(uae_u32 opcode) /* AND */
1378: {
1379: uae_u32 dstreg = opcode & 7;
1380: OpcodeFamily = 2; CurrentInstrCycles = 20;
1381: {{ uae_s16 src = get_iword(2);
1382: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
1383: { uae_s16 dst = get_word(dsta);
1384: src &= dst;
1385: CLEAR_CZNV;
1386: SET_ZFLG (((uae_s16)(src)) == 0);
1387: SET_NFLG (((uae_s16)(src)) < 0);
1388: put_word(dsta,src);
1389: }}}}m68k_incpc(6);
1390: return 20;
1391: }
1392: unsigned long REGPARAM2 CPUFUNC(op_270_0)(uae_u32 opcode) /* AND */
1393: {
1394: uae_u32 dstreg = opcode & 7;
1395: OpcodeFamily = 2; CurrentInstrCycles = 22;
1396: {{ uae_s16 src = get_iword(2);
1397: {m68k_incpc(4);
1398: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
1399: BusCyclePenalty += 2;
1400: { uae_s16 dst = get_word(dsta);
1401: src &= dst;
1402: CLEAR_CZNV;
1403: SET_ZFLG (((uae_s16)(src)) == 0);
1404: SET_NFLG (((uae_s16)(src)) < 0);
1405: put_word(dsta,src);
1406: }}}}}return 22;
1407: }
1408: unsigned long REGPARAM2 CPUFUNC(op_278_0)(uae_u32 opcode) /* AND */
1409: {
1410: OpcodeFamily = 2; CurrentInstrCycles = 20;
1411: {{ uae_s16 src = get_iword(2);
1412: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
1413: { uae_s16 dst = get_word(dsta);
1414: src &= dst;
1415: CLEAR_CZNV;
1416: SET_ZFLG (((uae_s16)(src)) == 0);
1417: SET_NFLG (((uae_s16)(src)) < 0);
1418: put_word(dsta,src);
1419: }}}}m68k_incpc(6);
1420: return 20;
1421: }
1422: unsigned long REGPARAM2 CPUFUNC(op_279_0)(uae_u32 opcode) /* AND */
1423: {
1424: OpcodeFamily = 2; CurrentInstrCycles = 24;
1425: {{ uae_s16 src = get_iword(2);
1426: { uaecptr dsta = get_ilong(4);
1427: { uae_s16 dst = get_word(dsta);
1428: src &= dst;
1429: CLEAR_CZNV;
1430: SET_ZFLG (((uae_s16)(src)) == 0);
1431: SET_NFLG (((uae_s16)(src)) < 0);
1432: put_word(dsta,src);
1433: }}}}m68k_incpc(8);
1434: return 24;
1435: }
1436: unsigned long REGPARAM2 CPUFUNC(op_27c_0)(uae_u32 opcode) /* ANDSR */
1437: {
1438: OpcodeFamily = 5; CurrentInstrCycles = 20;
1439: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel96; }
1440: { MakeSR();
1441: { uae_s16 src = get_iword(2);
1442: regs.sr &= src;
1443: MakeFromSR();
1444: }}}m68k_incpc(4);
1445: endlabel96: ;
1446: return 20;
1447: }
1448: unsigned long REGPARAM2 CPUFUNC(op_280_0)(uae_u32 opcode) /* AND */
1449: {
1450: uae_u32 dstreg = opcode & 7;
1451: OpcodeFamily = 2; CurrentInstrCycles = 16;
1452: {{ uae_s32 src = get_ilong(2);
1453: { uae_s32 dst = m68k_dreg(regs, dstreg);
1454: src &= dst;
1455: CLEAR_CZNV;
1456: SET_ZFLG (((uae_s32)(src)) == 0);
1457: SET_NFLG (((uae_s32)(src)) < 0);
1458: m68k_dreg(regs, dstreg) = (src);
1459: }}}m68k_incpc(6);
1460: return 16;
1461: }
1462: unsigned long REGPARAM2 CPUFUNC(op_290_0)(uae_u32 opcode) /* AND */
1463: {
1464: uae_u32 dstreg = opcode & 7;
1465: OpcodeFamily = 2; CurrentInstrCycles = 28;
1466: {{ uae_s32 src = get_ilong(2);
1467: { uaecptr dsta = m68k_areg(regs, dstreg);
1468: { uae_s32 dst = get_long(dsta);
1469: src &= dst;
1470: CLEAR_CZNV;
1471: SET_ZFLG (((uae_s32)(src)) == 0);
1472: SET_NFLG (((uae_s32)(src)) < 0);
1473: put_long(dsta,src);
1474: }}}}m68k_incpc(6);
1475: return 28;
1476: }
1477: unsigned long REGPARAM2 CPUFUNC(op_298_0)(uae_u32 opcode) /* AND */
1478: {
1479: uae_u32 dstreg = opcode & 7;
1480: OpcodeFamily = 2; CurrentInstrCycles = 28;
1481: {{ uae_s32 src = get_ilong(2);
1482: { uaecptr dsta = m68k_areg(regs, dstreg);
1483: { uae_s32 dst = get_long(dsta);
1484: m68k_areg(regs, dstreg) += 4;
1485: src &= dst;
1486: CLEAR_CZNV;
1487: SET_ZFLG (((uae_s32)(src)) == 0);
1488: SET_NFLG (((uae_s32)(src)) < 0);
1489: put_long(dsta,src);
1490: }}}}m68k_incpc(6);
1491: return 28;
1492: }
1493: unsigned long REGPARAM2 CPUFUNC(op_2a0_0)(uae_u32 opcode) /* AND */
1494: {
1495: uae_u32 dstreg = opcode & 7;
1496: OpcodeFamily = 2; CurrentInstrCycles = 30;
1497: {{ uae_s32 src = get_ilong(2);
1498: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
1499: { uae_s32 dst = get_long(dsta);
1500: m68k_areg (regs, dstreg) = dsta;
1501: src &= dst;
1502: CLEAR_CZNV;
1503: SET_ZFLG (((uae_s32)(src)) == 0);
1504: SET_NFLG (((uae_s32)(src)) < 0);
1505: put_long(dsta,src);
1506: }}}}m68k_incpc(6);
1507: return 30;
1508: }
1509: unsigned long REGPARAM2 CPUFUNC(op_2a8_0)(uae_u32 opcode) /* AND */
1510: {
1511: uae_u32 dstreg = opcode & 7;
1512: OpcodeFamily = 2; CurrentInstrCycles = 32;
1513: {{ uae_s32 src = get_ilong(2);
1514: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
1515: { uae_s32 dst = get_long(dsta);
1516: src &= dst;
1517: CLEAR_CZNV;
1518: SET_ZFLG (((uae_s32)(src)) == 0);
1519: SET_NFLG (((uae_s32)(src)) < 0);
1520: put_long(dsta,src);
1521: }}}}m68k_incpc(8);
1522: return 32;
1523: }
1524: unsigned long REGPARAM2 CPUFUNC(op_2b0_0)(uae_u32 opcode) /* AND */
1525: {
1526: uae_u32 dstreg = opcode & 7;
1527: OpcodeFamily = 2; CurrentInstrCycles = 34;
1528: {{ uae_s32 src = get_ilong(2);
1529: {m68k_incpc(6);
1530: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
1531: BusCyclePenalty += 2;
1532: { uae_s32 dst = get_long(dsta);
1533: src &= dst;
1534: CLEAR_CZNV;
1535: SET_ZFLG (((uae_s32)(src)) == 0);
1536: SET_NFLG (((uae_s32)(src)) < 0);
1537: put_long(dsta,src);
1538: }}}}}return 34;
1539: }
1540: unsigned long REGPARAM2 CPUFUNC(op_2b8_0)(uae_u32 opcode) /* AND */
1541: {
1542: OpcodeFamily = 2; CurrentInstrCycles = 32;
1543: {{ uae_s32 src = get_ilong(2);
1544: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
1545: { uae_s32 dst = get_long(dsta);
1546: src &= dst;
1547: CLEAR_CZNV;
1548: SET_ZFLG (((uae_s32)(src)) == 0);
1549: SET_NFLG (((uae_s32)(src)) < 0);
1550: put_long(dsta,src);
1551: }}}}m68k_incpc(8);
1552: return 32;
1553: }
1554: unsigned long REGPARAM2 CPUFUNC(op_2b9_0)(uae_u32 opcode) /* AND */
1555: {
1556: OpcodeFamily = 2; CurrentInstrCycles = 36;
1557: {{ uae_s32 src = get_ilong(2);
1558: { uaecptr dsta = get_ilong(6);
1559: { uae_s32 dst = get_long(dsta);
1560: src &= dst;
1561: CLEAR_CZNV;
1562: SET_ZFLG (((uae_s32)(src)) == 0);
1563: SET_NFLG (((uae_s32)(src)) < 0);
1564: put_long(dsta,src);
1565: }}}}m68k_incpc(10);
1566: return 36;
1567: }
1568: unsigned long REGPARAM2 CPUFUNC(op_2d0_0)(uae_u32 opcode) /* CHK2 */
1569: {
1570: uae_u32 dstreg = opcode & 7;
1571: OpcodeFamily = 81; CurrentInstrCycles = 8;
1572: { uaecptr oldpc = m68k_getpc();
1573: { uae_s16 extra = get_iword(2);
1574: { uaecptr dsta = m68k_areg(regs, dstreg);
1575: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
1576: lower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);
1577: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
1578: SET_ZFLG (upper == reg || lower == reg);
1579: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
1580: m68k_incpc(4);
1581: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel105; }
1582: }
1583: }}}endlabel105: ;
1584: return 8;
1585: }
1586: unsigned long REGPARAM2 CPUFUNC(op_2e8_0)(uae_u32 opcode) /* CHK2 */
1587: {
1588: uae_u32 dstreg = opcode & 7;
1589: OpcodeFamily = 81; CurrentInstrCycles = 12;
1590: { uaecptr oldpc = m68k_getpc();
1591: { uae_s16 extra = get_iword(2);
1592: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
1593: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
1594: lower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);
1595: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
1596: SET_ZFLG (upper == reg || lower == reg);
1597: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
1598: m68k_incpc(6);
1599: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel106; }
1600: }
1601: }}}endlabel106: ;
1602: return 12;
1603: }
1604: unsigned long REGPARAM2 CPUFUNC(op_2f0_0)(uae_u32 opcode) /* CHK2 */
1605: {
1606: uae_u32 dstreg = opcode & 7;
1607: OpcodeFamily = 81; CurrentInstrCycles = 14;
1608: { uaecptr oldpc = m68k_getpc();
1609: { uae_s16 extra = get_iword(2);
1610: {m68k_incpc(4);
1611: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
1612: BusCyclePenalty += 2;
1613: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
1614: lower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);
1615: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
1616: SET_ZFLG (upper == reg || lower == reg);
1617: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
1618: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel107; }
1619: }
1620: }}}}endlabel107: ;
1621: return 14;
1622: }
1623: unsigned long REGPARAM2 CPUFUNC(op_2f8_0)(uae_u32 opcode) /* CHK2 */
1624: {
1625: OpcodeFamily = 81; CurrentInstrCycles = 12;
1626: { uaecptr oldpc = m68k_getpc();
1627: { uae_s16 extra = get_iword(2);
1628: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
1629: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
1630: lower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);
1631: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
1632: SET_ZFLG (upper == reg || lower == reg);
1633: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
1634: m68k_incpc(6);
1635: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel108; }
1636: }
1637: }}}endlabel108: ;
1638: return 12;
1639: }
1640: unsigned long REGPARAM2 CPUFUNC(op_2f9_0)(uae_u32 opcode) /* CHK2 */
1641: {
1642: OpcodeFamily = 81; CurrentInstrCycles = 16;
1643: { uaecptr oldpc = m68k_getpc();
1644: { uae_s16 extra = get_iword(2);
1645: { uaecptr dsta = get_ilong(4);
1646: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
1647: lower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);
1648: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
1649: SET_ZFLG (upper == reg || lower == reg);
1650: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
1651: m68k_incpc(8);
1652: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel109; }
1653: }
1654: }}}endlabel109: ;
1655: return 16;
1656: }
1657: unsigned long REGPARAM2 CPUFUNC(op_2fa_0)(uae_u32 opcode) /* CHK2 */
1658: {
1659: uae_u32 dstreg = 2;
1660: OpcodeFamily = 81; CurrentInstrCycles = 12;
1661: { uaecptr oldpc = m68k_getpc();
1662: { uae_s16 extra = get_iword(2);
1663: { uaecptr dsta = m68k_getpc () + 4;
1664: dsta += (uae_s32)(uae_s16)get_iword(4);
1665: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
1666: lower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);
1667: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
1668: SET_ZFLG (upper == reg || lower == reg);
1669: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
1670: m68k_incpc(6);
1671: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel110; }
1672: }
1673: }}}endlabel110: ;
1674: return 12;
1675: }
1676: unsigned long REGPARAM2 CPUFUNC(op_2fb_0)(uae_u32 opcode) /* CHK2 */
1677: {
1678: uae_u32 dstreg = 3;
1679: OpcodeFamily = 81; CurrentInstrCycles = 14;
1680: { uaecptr oldpc = m68k_getpc();
1681: { uae_s16 extra = get_iword(2);
1682: {m68k_incpc(4);
1683: { uaecptr tmppc = m68k_getpc();
1684: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
1685: BusCyclePenalty += 2;
1686: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
1687: lower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);
1688: if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
1689: SET_ZFLG (upper == reg || lower == reg);
1690: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
1691: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel111; }
1692: }
1693: }}}}endlabel111: ;
1694: return 14;
1695: }
1696: unsigned long REGPARAM2 CPUFUNC(op_400_0)(uae_u32 opcode) /* SUB */
1697: {
1698: uae_u32 dstreg = opcode & 7;
1699: OpcodeFamily = 7; CurrentInstrCycles = 8;
1700: {{ uae_s8 src = get_ibyte(2);
1701: { uae_s8 dst = m68k_dreg(regs, dstreg);
1702: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
1703: { int flgs = ((uae_s8)(src)) < 0;
1704: int flgo = ((uae_s8)(dst)) < 0;
1705: int flgn = ((uae_s8)(newv)) < 0;
1706: SET_ZFLG (((uae_s8)(newv)) == 0);
1707: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1708: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
1709: COPY_CARRY;
1710: SET_NFLG (flgn != 0);
1711: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
1712: }}}}}}m68k_incpc(4);
1713: return 8;
1714: }
1715: unsigned long REGPARAM2 CPUFUNC(op_410_0)(uae_u32 opcode) /* SUB */
1716: {
1717: uae_u32 dstreg = opcode & 7;
1718: OpcodeFamily = 7; CurrentInstrCycles = 16;
1719: {{ uae_s8 src = get_ibyte(2);
1720: { uaecptr dsta = m68k_areg(regs, dstreg);
1721: { uae_s8 dst = get_byte(dsta);
1722: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
1723: { int flgs = ((uae_s8)(src)) < 0;
1724: int flgo = ((uae_s8)(dst)) < 0;
1725: int flgn = ((uae_s8)(newv)) < 0;
1726: SET_ZFLG (((uae_s8)(newv)) == 0);
1727: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1728: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
1729: COPY_CARRY;
1730: SET_NFLG (flgn != 0);
1731: put_byte(dsta,newv);
1732: }}}}}}}m68k_incpc(4);
1733: return 16;
1734: }
1735: unsigned long REGPARAM2 CPUFUNC(op_418_0)(uae_u32 opcode) /* SUB */
1736: {
1737: uae_u32 dstreg = opcode & 7;
1738: OpcodeFamily = 7; CurrentInstrCycles = 16;
1739: {{ uae_s8 src = get_ibyte(2);
1740: { uaecptr dsta = m68k_areg(regs, dstreg);
1741: { uae_s8 dst = get_byte(dsta);
1742: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
1743: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
1744: { int flgs = ((uae_s8)(src)) < 0;
1745: int flgo = ((uae_s8)(dst)) < 0;
1746: int flgn = ((uae_s8)(newv)) < 0;
1747: SET_ZFLG (((uae_s8)(newv)) == 0);
1748: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1749: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
1750: COPY_CARRY;
1751: SET_NFLG (flgn != 0);
1752: put_byte(dsta,newv);
1753: }}}}}}}m68k_incpc(4);
1754: return 16;
1755: }
1756: unsigned long REGPARAM2 CPUFUNC(op_420_0)(uae_u32 opcode) /* SUB */
1757: {
1758: uae_u32 dstreg = opcode & 7;
1759: OpcodeFamily = 7; CurrentInstrCycles = 18;
1760: {{ uae_s8 src = get_ibyte(2);
1761: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
1762: { uae_s8 dst = get_byte(dsta);
1763: m68k_areg (regs, dstreg) = dsta;
1764: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
1765: { int flgs = ((uae_s8)(src)) < 0;
1766: int flgo = ((uae_s8)(dst)) < 0;
1767: int flgn = ((uae_s8)(newv)) < 0;
1768: SET_ZFLG (((uae_s8)(newv)) == 0);
1769: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1770: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
1771: COPY_CARRY;
1772: SET_NFLG (flgn != 0);
1773: put_byte(dsta,newv);
1774: }}}}}}}m68k_incpc(4);
1775: return 18;
1776: }
1777: unsigned long REGPARAM2 CPUFUNC(op_428_0)(uae_u32 opcode) /* SUB */
1778: {
1779: uae_u32 dstreg = opcode & 7;
1780: OpcodeFamily = 7; CurrentInstrCycles = 20;
1781: {{ uae_s8 src = get_ibyte(2);
1782: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
1783: { uae_s8 dst = get_byte(dsta);
1784: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
1785: { int flgs = ((uae_s8)(src)) < 0;
1786: int flgo = ((uae_s8)(dst)) < 0;
1787: int flgn = ((uae_s8)(newv)) < 0;
1788: SET_ZFLG (((uae_s8)(newv)) == 0);
1789: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1790: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
1791: COPY_CARRY;
1792: SET_NFLG (flgn != 0);
1793: put_byte(dsta,newv);
1794: }}}}}}}m68k_incpc(6);
1795: return 20;
1796: }
1797: unsigned long REGPARAM2 CPUFUNC(op_430_0)(uae_u32 opcode) /* SUB */
1798: {
1799: uae_u32 dstreg = opcode & 7;
1800: OpcodeFamily = 7; CurrentInstrCycles = 22;
1801: {{ uae_s8 src = get_ibyte(2);
1802: {m68k_incpc(4);
1803: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
1804: BusCyclePenalty += 2;
1805: { uae_s8 dst = get_byte(dsta);
1806: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
1807: { int flgs = ((uae_s8)(src)) < 0;
1808: int flgo = ((uae_s8)(dst)) < 0;
1809: int flgn = ((uae_s8)(newv)) < 0;
1810: SET_ZFLG (((uae_s8)(newv)) == 0);
1811: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1812: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
1813: COPY_CARRY;
1814: SET_NFLG (flgn != 0);
1815: put_byte(dsta,newv);
1816: }}}}}}}}return 22;
1817: }
1818: unsigned long REGPARAM2 CPUFUNC(op_438_0)(uae_u32 opcode) /* SUB */
1819: {
1820: OpcodeFamily = 7; CurrentInstrCycles = 20;
1821: {{ uae_s8 src = get_ibyte(2);
1822: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
1823: { uae_s8 dst = get_byte(dsta);
1824: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
1825: { int flgs = ((uae_s8)(src)) < 0;
1826: int flgo = ((uae_s8)(dst)) < 0;
1827: int flgn = ((uae_s8)(newv)) < 0;
1828: SET_ZFLG (((uae_s8)(newv)) == 0);
1829: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1830: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
1831: COPY_CARRY;
1832: SET_NFLG (flgn != 0);
1833: put_byte(dsta,newv);
1834: }}}}}}}m68k_incpc(6);
1835: return 20;
1836: }
1837: unsigned long REGPARAM2 CPUFUNC(op_439_0)(uae_u32 opcode) /* SUB */
1838: {
1839: OpcodeFamily = 7; CurrentInstrCycles = 24;
1840: {{ uae_s8 src = get_ibyte(2);
1841: { uaecptr dsta = get_ilong(4);
1842: { uae_s8 dst = get_byte(dsta);
1843: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
1844: { int flgs = ((uae_s8)(src)) < 0;
1845: int flgo = ((uae_s8)(dst)) < 0;
1846: int flgn = ((uae_s8)(newv)) < 0;
1847: SET_ZFLG (((uae_s8)(newv)) == 0);
1848: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1849: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
1850: COPY_CARRY;
1851: SET_NFLG (flgn != 0);
1852: put_byte(dsta,newv);
1853: }}}}}}}m68k_incpc(8);
1854: return 24;
1855: }
1856: unsigned long REGPARAM2 CPUFUNC(op_440_0)(uae_u32 opcode) /* SUB */
1857: {
1858: uae_u32 dstreg = opcode & 7;
1859: OpcodeFamily = 7; CurrentInstrCycles = 8;
1860: {{ uae_s16 src = get_iword(2);
1861: { uae_s16 dst = m68k_dreg(regs, dstreg);
1862: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
1863: { int flgs = ((uae_s16)(src)) < 0;
1864: int flgo = ((uae_s16)(dst)) < 0;
1865: int flgn = ((uae_s16)(newv)) < 0;
1866: SET_ZFLG (((uae_s16)(newv)) == 0);
1867: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1868: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
1869: COPY_CARRY;
1870: SET_NFLG (flgn != 0);
1871: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
1872: }}}}}}m68k_incpc(4);
1873: return 8;
1874: }
1875: unsigned long REGPARAM2 CPUFUNC(op_450_0)(uae_u32 opcode) /* SUB */
1876: {
1877: uae_u32 dstreg = opcode & 7;
1878: OpcodeFamily = 7; CurrentInstrCycles = 16;
1879: {{ uae_s16 src = get_iword(2);
1880: { uaecptr dsta = m68k_areg(regs, dstreg);
1881: { uae_s16 dst = get_word(dsta);
1882: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
1883: { int flgs = ((uae_s16)(src)) < 0;
1884: int flgo = ((uae_s16)(dst)) < 0;
1885: int flgn = ((uae_s16)(newv)) < 0;
1886: SET_ZFLG (((uae_s16)(newv)) == 0);
1887: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1888: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
1889: COPY_CARRY;
1890: SET_NFLG (flgn != 0);
1891: put_word(dsta,newv);
1892: }}}}}}}m68k_incpc(4);
1893: return 16;
1894: }
1895: unsigned long REGPARAM2 CPUFUNC(op_458_0)(uae_u32 opcode) /* SUB */
1896: {
1897: uae_u32 dstreg = opcode & 7;
1898: OpcodeFamily = 7; CurrentInstrCycles = 16;
1899: {{ uae_s16 src = get_iword(2);
1900: { uaecptr dsta = m68k_areg(regs, dstreg);
1901: { uae_s16 dst = get_word(dsta);
1902: m68k_areg(regs, dstreg) += 2;
1903: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
1904: { int flgs = ((uae_s16)(src)) < 0;
1905: int flgo = ((uae_s16)(dst)) < 0;
1906: int flgn = ((uae_s16)(newv)) < 0;
1907: SET_ZFLG (((uae_s16)(newv)) == 0);
1908: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1909: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
1910: COPY_CARRY;
1911: SET_NFLG (flgn != 0);
1912: put_word(dsta,newv);
1913: }}}}}}}m68k_incpc(4);
1914: return 16;
1915: }
1916: unsigned long REGPARAM2 CPUFUNC(op_460_0)(uae_u32 opcode) /* SUB */
1917: {
1918: uae_u32 dstreg = opcode & 7;
1919: OpcodeFamily = 7; CurrentInstrCycles = 18;
1920: {{ uae_s16 src = get_iword(2);
1921: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
1922: { uae_s16 dst = get_word(dsta);
1923: m68k_areg (regs, dstreg) = dsta;
1924: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
1925: { int flgs = ((uae_s16)(src)) < 0;
1926: int flgo = ((uae_s16)(dst)) < 0;
1927: int flgn = ((uae_s16)(newv)) < 0;
1928: SET_ZFLG (((uae_s16)(newv)) == 0);
1929: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1930: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
1931: COPY_CARRY;
1932: SET_NFLG (flgn != 0);
1933: put_word(dsta,newv);
1934: }}}}}}}m68k_incpc(4);
1935: return 18;
1936: }
1937: unsigned long REGPARAM2 CPUFUNC(op_468_0)(uae_u32 opcode) /* SUB */
1938: {
1939: uae_u32 dstreg = opcode & 7;
1940: OpcodeFamily = 7; CurrentInstrCycles = 20;
1941: {{ uae_s16 src = get_iword(2);
1942: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
1943: { uae_s16 dst = get_word(dsta);
1944: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
1945: { int flgs = ((uae_s16)(src)) < 0;
1946: int flgo = ((uae_s16)(dst)) < 0;
1947: int flgn = ((uae_s16)(newv)) < 0;
1948: SET_ZFLG (((uae_s16)(newv)) == 0);
1949: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1950: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
1951: COPY_CARRY;
1952: SET_NFLG (flgn != 0);
1953: put_word(dsta,newv);
1954: }}}}}}}m68k_incpc(6);
1955: return 20;
1956: }
1957: unsigned long REGPARAM2 CPUFUNC(op_470_0)(uae_u32 opcode) /* SUB */
1958: {
1959: uae_u32 dstreg = opcode & 7;
1960: OpcodeFamily = 7; CurrentInstrCycles = 22;
1961: {{ uae_s16 src = get_iword(2);
1962: {m68k_incpc(4);
1963: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
1964: BusCyclePenalty += 2;
1965: { uae_s16 dst = get_word(dsta);
1966: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
1967: { int flgs = ((uae_s16)(src)) < 0;
1968: int flgo = ((uae_s16)(dst)) < 0;
1969: int flgn = ((uae_s16)(newv)) < 0;
1970: SET_ZFLG (((uae_s16)(newv)) == 0);
1971: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1972: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
1973: COPY_CARRY;
1974: SET_NFLG (flgn != 0);
1975: put_word(dsta,newv);
1976: }}}}}}}}return 22;
1977: }
1978: unsigned long REGPARAM2 CPUFUNC(op_478_0)(uae_u32 opcode) /* SUB */
1979: {
1980: OpcodeFamily = 7; CurrentInstrCycles = 20;
1981: {{ uae_s16 src = get_iword(2);
1982: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
1983: { uae_s16 dst = get_word(dsta);
1984: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
1985: { int flgs = ((uae_s16)(src)) < 0;
1986: int flgo = ((uae_s16)(dst)) < 0;
1987: int flgn = ((uae_s16)(newv)) < 0;
1988: SET_ZFLG (((uae_s16)(newv)) == 0);
1989: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
1990: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
1991: COPY_CARRY;
1992: SET_NFLG (flgn != 0);
1993: put_word(dsta,newv);
1994: }}}}}}}m68k_incpc(6);
1995: return 20;
1996: }
1997: unsigned long REGPARAM2 CPUFUNC(op_479_0)(uae_u32 opcode) /* SUB */
1998: {
1999: OpcodeFamily = 7; CurrentInstrCycles = 24;
2000: {{ uae_s16 src = get_iword(2);
2001: { uaecptr dsta = get_ilong(4);
2002: { uae_s16 dst = get_word(dsta);
2003: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
2004: { int flgs = ((uae_s16)(src)) < 0;
2005: int flgo = ((uae_s16)(dst)) < 0;
2006: int flgn = ((uae_s16)(newv)) < 0;
2007: SET_ZFLG (((uae_s16)(newv)) == 0);
2008: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
2009: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
2010: COPY_CARRY;
2011: SET_NFLG (flgn != 0);
2012: put_word(dsta,newv);
2013: }}}}}}}m68k_incpc(8);
2014: return 24;
2015: }
2016: unsigned long REGPARAM2 CPUFUNC(op_480_0)(uae_u32 opcode) /* SUB */
2017: {
2018: uae_u32 dstreg = opcode & 7;
2019: OpcodeFamily = 7; CurrentInstrCycles = 16;
2020: {{ uae_s32 src = get_ilong(2);
2021: { uae_s32 dst = m68k_dreg(regs, dstreg);
2022: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
2023: { int flgs = ((uae_s32)(src)) < 0;
2024: int flgo = ((uae_s32)(dst)) < 0;
2025: int flgn = ((uae_s32)(newv)) < 0;
2026: SET_ZFLG (((uae_s32)(newv)) == 0);
2027: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
2028: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
2029: COPY_CARRY;
2030: SET_NFLG (flgn != 0);
2031: m68k_dreg(regs, dstreg) = (newv);
2032: }}}}}}m68k_incpc(6);
2033: return 16;
2034: }
2035: unsigned long REGPARAM2 CPUFUNC(op_490_0)(uae_u32 opcode) /* SUB */
2036: {
2037: uae_u32 dstreg = opcode & 7;
2038: OpcodeFamily = 7; CurrentInstrCycles = 28;
2039: {{ uae_s32 src = get_ilong(2);
2040: { uaecptr dsta = m68k_areg(regs, dstreg);
2041: { uae_s32 dst = get_long(dsta);
2042: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
2043: { int flgs = ((uae_s32)(src)) < 0;
2044: int flgo = ((uae_s32)(dst)) < 0;
2045: int flgn = ((uae_s32)(newv)) < 0;
2046: SET_ZFLG (((uae_s32)(newv)) == 0);
2047: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
2048: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
2049: COPY_CARRY;
2050: SET_NFLG (flgn != 0);
2051: put_long(dsta,newv);
2052: }}}}}}}m68k_incpc(6);
2053: return 28;
2054: }
2055: unsigned long REGPARAM2 CPUFUNC(op_498_0)(uae_u32 opcode) /* SUB */
2056: {
2057: uae_u32 dstreg = opcode & 7;
2058: OpcodeFamily = 7; CurrentInstrCycles = 28;
2059: {{ uae_s32 src = get_ilong(2);
2060: { uaecptr dsta = m68k_areg(regs, dstreg);
2061: { uae_s32 dst = get_long(dsta);
2062: m68k_areg(regs, dstreg) += 4;
2063: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
2064: { int flgs = ((uae_s32)(src)) < 0;
2065: int flgo = ((uae_s32)(dst)) < 0;
2066: int flgn = ((uae_s32)(newv)) < 0;
2067: SET_ZFLG (((uae_s32)(newv)) == 0);
2068: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
2069: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
2070: COPY_CARRY;
2071: SET_NFLG (flgn != 0);
2072: put_long(dsta,newv);
2073: }}}}}}}m68k_incpc(6);
2074: return 28;
2075: }
2076: unsigned long REGPARAM2 CPUFUNC(op_4a0_0)(uae_u32 opcode) /* SUB */
2077: {
2078: uae_u32 dstreg = opcode & 7;
2079: OpcodeFamily = 7; CurrentInstrCycles = 30;
2080: {{ uae_s32 src = get_ilong(2);
2081: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
2082: { uae_s32 dst = get_long(dsta);
2083: m68k_areg (regs, dstreg) = dsta;
2084: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
2085: { int flgs = ((uae_s32)(src)) < 0;
2086: int flgo = ((uae_s32)(dst)) < 0;
2087: int flgn = ((uae_s32)(newv)) < 0;
2088: SET_ZFLG (((uae_s32)(newv)) == 0);
2089: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
2090: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
2091: COPY_CARRY;
2092: SET_NFLG (flgn != 0);
2093: put_long(dsta,newv);
2094: }}}}}}}m68k_incpc(6);
2095: return 30;
2096: }
2097: unsigned long REGPARAM2 CPUFUNC(op_4a8_0)(uae_u32 opcode) /* SUB */
2098: {
2099: uae_u32 dstreg = opcode & 7;
2100: OpcodeFamily = 7; CurrentInstrCycles = 32;
2101: {{ uae_s32 src = get_ilong(2);
2102: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
2103: { uae_s32 dst = get_long(dsta);
2104: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
2105: { int flgs = ((uae_s32)(src)) < 0;
2106: int flgo = ((uae_s32)(dst)) < 0;
2107: int flgn = ((uae_s32)(newv)) < 0;
2108: SET_ZFLG (((uae_s32)(newv)) == 0);
2109: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
2110: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
2111: COPY_CARRY;
2112: SET_NFLG (flgn != 0);
2113: put_long(dsta,newv);
2114: }}}}}}}m68k_incpc(8);
2115: return 32;
2116: }
2117: unsigned long REGPARAM2 CPUFUNC(op_4b0_0)(uae_u32 opcode) /* SUB */
2118: {
2119: uae_u32 dstreg = opcode & 7;
2120: OpcodeFamily = 7; CurrentInstrCycles = 34;
2121: {{ uae_s32 src = get_ilong(2);
2122: {m68k_incpc(6);
2123: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
2124: BusCyclePenalty += 2;
2125: { uae_s32 dst = get_long(dsta);
2126: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
2127: { int flgs = ((uae_s32)(src)) < 0;
2128: int flgo = ((uae_s32)(dst)) < 0;
2129: int flgn = ((uae_s32)(newv)) < 0;
2130: SET_ZFLG (((uae_s32)(newv)) == 0);
2131: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
2132: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
2133: COPY_CARRY;
2134: SET_NFLG (flgn != 0);
2135: put_long(dsta,newv);
2136: }}}}}}}}return 34;
2137: }
2138: unsigned long REGPARAM2 CPUFUNC(op_4b8_0)(uae_u32 opcode) /* SUB */
2139: {
2140: OpcodeFamily = 7; CurrentInstrCycles = 32;
2141: {{ uae_s32 src = get_ilong(2);
2142: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
2143: { uae_s32 dst = get_long(dsta);
2144: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
2145: { int flgs = ((uae_s32)(src)) < 0;
2146: int flgo = ((uae_s32)(dst)) < 0;
2147: int flgn = ((uae_s32)(newv)) < 0;
2148: SET_ZFLG (((uae_s32)(newv)) == 0);
2149: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
2150: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
2151: COPY_CARRY;
2152: SET_NFLG (flgn != 0);
2153: put_long(dsta,newv);
2154: }}}}}}}m68k_incpc(8);
2155: return 32;
2156: }
2157: unsigned long REGPARAM2 CPUFUNC(op_4b9_0)(uae_u32 opcode) /* SUB */
2158: {
2159: OpcodeFamily = 7; CurrentInstrCycles = 36;
2160: {{ uae_s32 src = get_ilong(2);
2161: { uaecptr dsta = get_ilong(6);
2162: { uae_s32 dst = get_long(dsta);
2163: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
2164: { int flgs = ((uae_s32)(src)) < 0;
2165: int flgo = ((uae_s32)(dst)) < 0;
2166: int flgn = ((uae_s32)(newv)) < 0;
2167: SET_ZFLG (((uae_s32)(newv)) == 0);
2168: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
2169: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
2170: COPY_CARRY;
2171: SET_NFLG (flgn != 0);
2172: put_long(dsta,newv);
2173: }}}}}}}m68k_incpc(10);
2174: return 36;
2175: }
2176: unsigned long REGPARAM2 CPUFUNC(op_4d0_0)(uae_u32 opcode) /* CHK2 */
2177: {
2178: uae_u32 dstreg = opcode & 7;
2179: OpcodeFamily = 81; CurrentInstrCycles = 8;
2180: { uaecptr oldpc = m68k_getpc();
2181: { uae_s16 extra = get_iword(2);
2182: { uaecptr dsta = m68k_areg(regs, dstreg);
2183: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
2184: lower=get_long(dsta); upper = get_long(dsta+4);
2185: SET_ZFLG (upper == reg || lower == reg);
2186: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
2187: m68k_incpc(4);
2188: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel136; }
2189: }
2190: }}}endlabel136: ;
2191: return 8;
2192: }
2193: unsigned long REGPARAM2 CPUFUNC(op_4e8_0)(uae_u32 opcode) /* CHK2 */
2194: {
2195: uae_u32 dstreg = opcode & 7;
2196: OpcodeFamily = 81; CurrentInstrCycles = 12;
2197: { uaecptr oldpc = m68k_getpc();
2198: { uae_s16 extra = get_iword(2);
2199: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
2200: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
2201: lower=get_long(dsta); upper = get_long(dsta+4);
2202: SET_ZFLG (upper == reg || lower == reg);
2203: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
2204: m68k_incpc(6);
2205: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel137; }
2206: }
2207: }}}endlabel137: ;
2208: return 12;
2209: }
2210: unsigned long REGPARAM2 CPUFUNC(op_4f0_0)(uae_u32 opcode) /* CHK2 */
2211: {
2212: uae_u32 dstreg = opcode & 7;
2213: OpcodeFamily = 81; CurrentInstrCycles = 14;
2214: { uaecptr oldpc = m68k_getpc();
2215: { uae_s16 extra = get_iword(2);
2216: {m68k_incpc(4);
2217: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
2218: BusCyclePenalty += 2;
2219: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
2220: lower=get_long(dsta); upper = get_long(dsta+4);
2221: SET_ZFLG (upper == reg || lower == reg);
2222: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
2223: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel138; }
2224: }
2225: }}}}endlabel138: ;
2226: return 14;
2227: }
2228: unsigned long REGPARAM2 CPUFUNC(op_4f8_0)(uae_u32 opcode) /* CHK2 */
2229: {
2230: OpcodeFamily = 81; CurrentInstrCycles = 12;
2231: { uaecptr oldpc = m68k_getpc();
2232: { uae_s16 extra = get_iword(2);
2233: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
2234: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
2235: lower=get_long(dsta); upper = get_long(dsta+4);
2236: SET_ZFLG (upper == reg || lower == reg);
2237: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
2238: m68k_incpc(6);
2239: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel139; }
2240: }
2241: }}}endlabel139: ;
2242: return 12;
2243: }
2244: unsigned long REGPARAM2 CPUFUNC(op_4f9_0)(uae_u32 opcode) /* CHK2 */
2245: {
2246: OpcodeFamily = 81; CurrentInstrCycles = 16;
2247: { uaecptr oldpc = m68k_getpc();
2248: { uae_s16 extra = get_iword(2);
2249: { uaecptr dsta = get_ilong(4);
2250: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
2251: lower=get_long(dsta); upper = get_long(dsta+4);
2252: SET_ZFLG (upper == reg || lower == reg);
2253: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
2254: m68k_incpc(8);
2255: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel140; }
2256: }
2257: }}}endlabel140: ;
2258: return 16;
2259: }
2260: unsigned long REGPARAM2 CPUFUNC(op_4fa_0)(uae_u32 opcode) /* CHK2 */
2261: {
2262: uae_u32 dstreg = 2;
2263: OpcodeFamily = 81; CurrentInstrCycles = 12;
2264: { uaecptr oldpc = m68k_getpc();
2265: { uae_s16 extra = get_iword(2);
2266: { uaecptr dsta = m68k_getpc () + 4;
2267: dsta += (uae_s32)(uae_s16)get_iword(4);
2268: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
2269: lower=get_long(dsta); upper = get_long(dsta+4);
2270: SET_ZFLG (upper == reg || lower == reg);
2271: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
2272: m68k_incpc(6);
2273: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel141; }
2274: }
2275: }}}endlabel141: ;
2276: return 12;
2277: }
2278: unsigned long REGPARAM2 CPUFUNC(op_4fb_0)(uae_u32 opcode) /* CHK2 */
2279: {
2280: uae_u32 dstreg = 3;
2281: OpcodeFamily = 81; CurrentInstrCycles = 14;
2282: { uaecptr oldpc = m68k_getpc();
2283: { uae_s16 extra = get_iword(2);
2284: {m68k_incpc(4);
2285: { uaecptr tmppc = m68k_getpc();
2286: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
2287: BusCyclePenalty += 2;
2288: {uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
2289: lower=get_long(dsta); upper = get_long(dsta+4);
2290: SET_ZFLG (upper == reg || lower == reg);
2291: SET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
2292: if ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel142; }
2293: }
2294: }}}}endlabel142: ;
2295: return 14;
2296: }
2297: unsigned long REGPARAM2 CPUFUNC(op_600_0)(uae_u32 opcode) /* ADD */
2298: {
2299: uae_u32 dstreg = opcode & 7;
2300: OpcodeFamily = 11; CurrentInstrCycles = 8;
2301: {{ uae_s8 src = get_ibyte(2);
2302: { uae_s8 dst = m68k_dreg(regs, dstreg);
2303: { refill_prefetch (m68k_getpc(), 2);
2304: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
2305: { int flgs = ((uae_s8)(src)) < 0;
2306: int flgo = ((uae_s8)(dst)) < 0;
2307: int flgn = ((uae_s8)(newv)) < 0;
2308: SET_ZFLG (((uae_s8)(newv)) == 0);
2309: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2310: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
2311: COPY_CARRY;
2312: SET_NFLG (flgn != 0);
2313: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
2314: }}}}}}m68k_incpc(4);
2315: return 8;
2316: }
2317: unsigned long REGPARAM2 CPUFUNC(op_610_0)(uae_u32 opcode) /* ADD */
2318: {
2319: uae_u32 dstreg = opcode & 7;
2320: OpcodeFamily = 11; CurrentInstrCycles = 16;
2321: {{ uae_s8 src = get_ibyte(2);
2322: { uaecptr dsta = m68k_areg(regs, dstreg);
2323: { uae_s8 dst = get_byte(dsta);
2324: { refill_prefetch (m68k_getpc(), 2);
2325: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
2326: { int flgs = ((uae_s8)(src)) < 0;
2327: int flgo = ((uae_s8)(dst)) < 0;
2328: int flgn = ((uae_s8)(newv)) < 0;
2329: SET_ZFLG (((uae_s8)(newv)) == 0);
2330: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2331: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
2332: COPY_CARRY;
2333: SET_NFLG (flgn != 0);
2334: put_byte(dsta,newv);
2335: }}}}}}}m68k_incpc(4);
2336: return 16;
2337: }
2338: unsigned long REGPARAM2 CPUFUNC(op_618_0)(uae_u32 opcode) /* ADD */
2339: {
2340: uae_u32 dstreg = opcode & 7;
2341: OpcodeFamily = 11; CurrentInstrCycles = 16;
2342: {{ uae_s8 src = get_ibyte(2);
2343: { uaecptr dsta = m68k_areg(regs, dstreg);
2344: { uae_s8 dst = get_byte(dsta);
2345: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
2346: { refill_prefetch (m68k_getpc(), 2);
2347: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
2348: { int flgs = ((uae_s8)(src)) < 0;
2349: int flgo = ((uae_s8)(dst)) < 0;
2350: int flgn = ((uae_s8)(newv)) < 0;
2351: SET_ZFLG (((uae_s8)(newv)) == 0);
2352: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2353: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
2354: COPY_CARRY;
2355: SET_NFLG (flgn != 0);
2356: put_byte(dsta,newv);
2357: }}}}}}}m68k_incpc(4);
2358: return 16;
2359: }
2360: unsigned long REGPARAM2 CPUFUNC(op_620_0)(uae_u32 opcode) /* ADD */
2361: {
2362: uae_u32 dstreg = opcode & 7;
2363: OpcodeFamily = 11; CurrentInstrCycles = 18;
2364: {{ uae_s8 src = get_ibyte(2);
2365: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
2366: { uae_s8 dst = get_byte(dsta);
2367: m68k_areg (regs, dstreg) = dsta;
2368: { refill_prefetch (m68k_getpc(), 2);
2369: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
2370: { int flgs = ((uae_s8)(src)) < 0;
2371: int flgo = ((uae_s8)(dst)) < 0;
2372: int flgn = ((uae_s8)(newv)) < 0;
2373: SET_ZFLG (((uae_s8)(newv)) == 0);
2374: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2375: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
2376: COPY_CARRY;
2377: SET_NFLG (flgn != 0);
2378: put_byte(dsta,newv);
2379: }}}}}}}m68k_incpc(4);
2380: return 18;
2381: }
2382: unsigned long REGPARAM2 CPUFUNC(op_628_0)(uae_u32 opcode) /* ADD */
2383: {
2384: uae_u32 dstreg = opcode & 7;
2385: OpcodeFamily = 11; CurrentInstrCycles = 20;
2386: {{ uae_s8 src = get_ibyte(2);
2387: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
2388: { uae_s8 dst = get_byte(dsta);
2389: { refill_prefetch (m68k_getpc(), 2);
2390: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
2391: { int flgs = ((uae_s8)(src)) < 0;
2392: int flgo = ((uae_s8)(dst)) < 0;
2393: int flgn = ((uae_s8)(newv)) < 0;
2394: SET_ZFLG (((uae_s8)(newv)) == 0);
2395: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2396: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
2397: COPY_CARRY;
2398: SET_NFLG (flgn != 0);
2399: put_byte(dsta,newv);
2400: }}}}}}}m68k_incpc(6);
2401: return 20;
2402: }
2403: unsigned long REGPARAM2 CPUFUNC(op_630_0)(uae_u32 opcode) /* ADD */
2404: {
2405: uae_u32 dstreg = opcode & 7;
2406: OpcodeFamily = 11; CurrentInstrCycles = 22;
2407: {{ uae_s8 src = get_ibyte(2);
2408: {m68k_incpc(4);
2409: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
2410: BusCyclePenalty += 2;
2411: { uae_s8 dst = get_byte(dsta);
2412: { refill_prefetch (m68k_getpc(), 2);
2413: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
2414: { int flgs = ((uae_s8)(src)) < 0;
2415: int flgo = ((uae_s8)(dst)) < 0;
2416: int flgn = ((uae_s8)(newv)) < 0;
2417: SET_ZFLG (((uae_s8)(newv)) == 0);
2418: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2419: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
2420: COPY_CARRY;
2421: SET_NFLG (flgn != 0);
2422: put_byte(dsta,newv);
2423: }}}}}}}}return 22;
2424: }
2425: unsigned long REGPARAM2 CPUFUNC(op_638_0)(uae_u32 opcode) /* ADD */
2426: {
2427: OpcodeFamily = 11; CurrentInstrCycles = 20;
2428: {{ uae_s8 src = get_ibyte(2);
2429: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
2430: { uae_s8 dst = get_byte(dsta);
2431: { refill_prefetch (m68k_getpc(), 2);
2432: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
2433: { int flgs = ((uae_s8)(src)) < 0;
2434: int flgo = ((uae_s8)(dst)) < 0;
2435: int flgn = ((uae_s8)(newv)) < 0;
2436: SET_ZFLG (((uae_s8)(newv)) == 0);
2437: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2438: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
2439: COPY_CARRY;
2440: SET_NFLG (flgn != 0);
2441: put_byte(dsta,newv);
2442: }}}}}}}m68k_incpc(6);
2443: return 20;
2444: }
2445: unsigned long REGPARAM2 CPUFUNC(op_639_0)(uae_u32 opcode) /* ADD */
2446: {
2447: OpcodeFamily = 11; CurrentInstrCycles = 24;
2448: {{ uae_s8 src = get_ibyte(2);
2449: { uaecptr dsta = get_ilong(4);
2450: { uae_s8 dst = get_byte(dsta);
2451: { refill_prefetch (m68k_getpc(), 2);
2452: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
2453: { int flgs = ((uae_s8)(src)) < 0;
2454: int flgo = ((uae_s8)(dst)) < 0;
2455: int flgn = ((uae_s8)(newv)) < 0;
2456: SET_ZFLG (((uae_s8)(newv)) == 0);
2457: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2458: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
2459: COPY_CARRY;
2460: SET_NFLG (flgn != 0);
2461: put_byte(dsta,newv);
2462: }}}}}}}m68k_incpc(8);
2463: return 24;
2464: }
2465: unsigned long REGPARAM2 CPUFUNC(op_640_0)(uae_u32 opcode) /* ADD */
2466: {
2467: uae_u32 dstreg = opcode & 7;
2468: OpcodeFamily = 11; CurrentInstrCycles = 8;
2469: {{ uae_s16 src = get_iword(2);
2470: { uae_s16 dst = m68k_dreg(regs, dstreg);
2471: { refill_prefetch (m68k_getpc(), 2);
2472: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
2473: { int flgs = ((uae_s16)(src)) < 0;
2474: int flgo = ((uae_s16)(dst)) < 0;
2475: int flgn = ((uae_s16)(newv)) < 0;
2476: SET_ZFLG (((uae_s16)(newv)) == 0);
2477: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2478: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
2479: COPY_CARRY;
2480: SET_NFLG (flgn != 0);
2481: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
2482: }}}}}}m68k_incpc(4);
2483: return 8;
2484: }
2485: unsigned long REGPARAM2 CPUFUNC(op_650_0)(uae_u32 opcode) /* ADD */
2486: {
2487: uae_u32 dstreg = opcode & 7;
2488: OpcodeFamily = 11; CurrentInstrCycles = 16;
2489: {{ uae_s16 src = get_iword(2);
2490: { uaecptr dsta = m68k_areg(regs, dstreg);
2491: { uae_s16 dst = get_word(dsta);
2492: { refill_prefetch (m68k_getpc(), 2);
2493: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
2494: { int flgs = ((uae_s16)(src)) < 0;
2495: int flgo = ((uae_s16)(dst)) < 0;
2496: int flgn = ((uae_s16)(newv)) < 0;
2497: SET_ZFLG (((uae_s16)(newv)) == 0);
2498: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2499: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
2500: COPY_CARRY;
2501: SET_NFLG (flgn != 0);
2502: put_word(dsta,newv);
2503: }}}}}}}m68k_incpc(4);
2504: return 16;
2505: }
2506: unsigned long REGPARAM2 CPUFUNC(op_658_0)(uae_u32 opcode) /* ADD */
2507: {
2508: uae_u32 dstreg = opcode & 7;
2509: OpcodeFamily = 11; CurrentInstrCycles = 16;
2510: {{ uae_s16 src = get_iword(2);
2511: { uaecptr dsta = m68k_areg(regs, dstreg);
2512: { uae_s16 dst = get_word(dsta);
2513: m68k_areg(regs, dstreg) += 2;
2514: { refill_prefetch (m68k_getpc(), 2);
2515: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
2516: { int flgs = ((uae_s16)(src)) < 0;
2517: int flgo = ((uae_s16)(dst)) < 0;
2518: int flgn = ((uae_s16)(newv)) < 0;
2519: SET_ZFLG (((uae_s16)(newv)) == 0);
2520: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2521: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
2522: COPY_CARRY;
2523: SET_NFLG (flgn != 0);
2524: put_word(dsta,newv);
2525: }}}}}}}m68k_incpc(4);
2526: return 16;
2527: }
2528: unsigned long REGPARAM2 CPUFUNC(op_660_0)(uae_u32 opcode) /* ADD */
2529: {
2530: uae_u32 dstreg = opcode & 7;
2531: OpcodeFamily = 11; CurrentInstrCycles = 18;
2532: {{ uae_s16 src = get_iword(2);
2533: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
2534: { uae_s16 dst = get_word(dsta);
2535: m68k_areg (regs, dstreg) = dsta;
2536: { refill_prefetch (m68k_getpc(), 2);
2537: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
2538: { int flgs = ((uae_s16)(src)) < 0;
2539: int flgo = ((uae_s16)(dst)) < 0;
2540: int flgn = ((uae_s16)(newv)) < 0;
2541: SET_ZFLG (((uae_s16)(newv)) == 0);
2542: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2543: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
2544: COPY_CARRY;
2545: SET_NFLG (flgn != 0);
2546: put_word(dsta,newv);
2547: }}}}}}}m68k_incpc(4);
2548: return 18;
2549: }
2550: unsigned long REGPARAM2 CPUFUNC(op_668_0)(uae_u32 opcode) /* ADD */
2551: {
2552: uae_u32 dstreg = opcode & 7;
2553: OpcodeFamily = 11; CurrentInstrCycles = 20;
2554: {{ uae_s16 src = get_iword(2);
2555: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
2556: { uae_s16 dst = get_word(dsta);
2557: { refill_prefetch (m68k_getpc(), 2);
2558: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
2559: { int flgs = ((uae_s16)(src)) < 0;
2560: int flgo = ((uae_s16)(dst)) < 0;
2561: int flgn = ((uae_s16)(newv)) < 0;
2562: SET_ZFLG (((uae_s16)(newv)) == 0);
2563: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2564: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
2565: COPY_CARRY;
2566: SET_NFLG (flgn != 0);
2567: put_word(dsta,newv);
2568: }}}}}}}m68k_incpc(6);
2569: return 20;
2570: }
2571: unsigned long REGPARAM2 CPUFUNC(op_670_0)(uae_u32 opcode) /* ADD */
2572: {
2573: uae_u32 dstreg = opcode & 7;
2574: OpcodeFamily = 11; CurrentInstrCycles = 22;
2575: {{ uae_s16 src = get_iword(2);
2576: {m68k_incpc(4);
2577: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
2578: BusCyclePenalty += 2;
2579: { uae_s16 dst = get_word(dsta);
2580: { refill_prefetch (m68k_getpc(), 2);
2581: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
2582: { int flgs = ((uae_s16)(src)) < 0;
2583: int flgo = ((uae_s16)(dst)) < 0;
2584: int flgn = ((uae_s16)(newv)) < 0;
2585: SET_ZFLG (((uae_s16)(newv)) == 0);
2586: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2587: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
2588: COPY_CARRY;
2589: SET_NFLG (flgn != 0);
2590: put_word(dsta,newv);
2591: }}}}}}}}return 22;
2592: }
2593: unsigned long REGPARAM2 CPUFUNC(op_678_0)(uae_u32 opcode) /* ADD */
2594: {
2595: OpcodeFamily = 11; CurrentInstrCycles = 20;
2596: {{ uae_s16 src = get_iword(2);
2597: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
2598: { uae_s16 dst = get_word(dsta);
2599: { refill_prefetch (m68k_getpc(), 2);
2600: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
2601: { int flgs = ((uae_s16)(src)) < 0;
2602: int flgo = ((uae_s16)(dst)) < 0;
2603: int flgn = ((uae_s16)(newv)) < 0;
2604: SET_ZFLG (((uae_s16)(newv)) == 0);
2605: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2606: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
2607: COPY_CARRY;
2608: SET_NFLG (flgn != 0);
2609: put_word(dsta,newv);
2610: }}}}}}}m68k_incpc(6);
2611: return 20;
2612: }
2613: unsigned long REGPARAM2 CPUFUNC(op_679_0)(uae_u32 opcode) /* ADD */
2614: {
2615: OpcodeFamily = 11; CurrentInstrCycles = 24;
2616: {{ uae_s16 src = get_iword(2);
2617: { uaecptr dsta = get_ilong(4);
2618: { uae_s16 dst = get_word(dsta);
2619: { refill_prefetch (m68k_getpc(), 2);
2620: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
2621: { int flgs = ((uae_s16)(src)) < 0;
2622: int flgo = ((uae_s16)(dst)) < 0;
2623: int flgn = ((uae_s16)(newv)) < 0;
2624: SET_ZFLG (((uae_s16)(newv)) == 0);
2625: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2626: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
2627: COPY_CARRY;
2628: SET_NFLG (flgn != 0);
2629: put_word(dsta,newv);
2630: }}}}}}}m68k_incpc(8);
2631: return 24;
2632: }
2633: unsigned long REGPARAM2 CPUFUNC(op_680_0)(uae_u32 opcode) /* ADD */
2634: {
2635: uae_u32 dstreg = opcode & 7;
2636: OpcodeFamily = 11; CurrentInstrCycles = 16;
2637: {{ uae_s32 src = get_ilong(2);
2638: { uae_s32 dst = m68k_dreg(regs, dstreg);
2639: { refill_prefetch (m68k_getpc(), 2);
2640: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
2641: { int flgs = ((uae_s32)(src)) < 0;
2642: int flgo = ((uae_s32)(dst)) < 0;
2643: int flgn = ((uae_s32)(newv)) < 0;
2644: SET_ZFLG (((uae_s32)(newv)) == 0);
2645: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2646: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
2647: COPY_CARRY;
2648: SET_NFLG (flgn != 0);
2649: m68k_dreg(regs, dstreg) = (newv);
2650: }}}}}}m68k_incpc(6);
2651: return 16;
2652: }
2653: unsigned long REGPARAM2 CPUFUNC(op_690_0)(uae_u32 opcode) /* ADD */
2654: {
2655: uae_u32 dstreg = opcode & 7;
2656: OpcodeFamily = 11; CurrentInstrCycles = 28;
2657: {{ uae_s32 src = get_ilong(2);
2658: { uaecptr dsta = m68k_areg(regs, dstreg);
2659: { uae_s32 dst = get_long(dsta);
2660: { refill_prefetch (m68k_getpc(), 2);
2661: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
2662: { int flgs = ((uae_s32)(src)) < 0;
2663: int flgo = ((uae_s32)(dst)) < 0;
2664: int flgn = ((uae_s32)(newv)) < 0;
2665: SET_ZFLG (((uae_s32)(newv)) == 0);
2666: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2667: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
2668: COPY_CARRY;
2669: SET_NFLG (flgn != 0);
2670: put_long(dsta,newv);
2671: }}}}}}}m68k_incpc(6);
2672: return 28;
2673: }
2674: unsigned long REGPARAM2 CPUFUNC(op_698_0)(uae_u32 opcode) /* ADD */
2675: {
2676: uae_u32 dstreg = opcode & 7;
2677: OpcodeFamily = 11; CurrentInstrCycles = 28;
2678: {{ uae_s32 src = get_ilong(2);
2679: { uaecptr dsta = m68k_areg(regs, dstreg);
2680: { uae_s32 dst = get_long(dsta);
2681: m68k_areg(regs, dstreg) += 4;
2682: { refill_prefetch (m68k_getpc(), 2);
2683: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
2684: { int flgs = ((uae_s32)(src)) < 0;
2685: int flgo = ((uae_s32)(dst)) < 0;
2686: int flgn = ((uae_s32)(newv)) < 0;
2687: SET_ZFLG (((uae_s32)(newv)) == 0);
2688: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2689: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
2690: COPY_CARRY;
2691: SET_NFLG (flgn != 0);
2692: put_long(dsta,newv);
2693: }}}}}}}m68k_incpc(6);
2694: return 28;
2695: }
2696: unsigned long REGPARAM2 CPUFUNC(op_6a0_0)(uae_u32 opcode) /* ADD */
2697: {
2698: uae_u32 dstreg = opcode & 7;
2699: OpcodeFamily = 11; CurrentInstrCycles = 30;
2700: {{ uae_s32 src = get_ilong(2);
2701: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
2702: { uae_s32 dst = get_long(dsta);
2703: m68k_areg (regs, dstreg) = dsta;
2704: { refill_prefetch (m68k_getpc(), 2);
2705: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
2706: { int flgs = ((uae_s32)(src)) < 0;
2707: int flgo = ((uae_s32)(dst)) < 0;
2708: int flgn = ((uae_s32)(newv)) < 0;
2709: SET_ZFLG (((uae_s32)(newv)) == 0);
2710: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2711: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
2712: COPY_CARRY;
2713: SET_NFLG (flgn != 0);
2714: put_long(dsta,newv);
2715: }}}}}}}m68k_incpc(6);
2716: return 30;
2717: }
2718: unsigned long REGPARAM2 CPUFUNC(op_6a8_0)(uae_u32 opcode) /* ADD */
2719: {
2720: uae_u32 dstreg = opcode & 7;
2721: OpcodeFamily = 11; CurrentInstrCycles = 32;
2722: {{ uae_s32 src = get_ilong(2);
2723: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
2724: { uae_s32 dst = get_long(dsta);
2725: { refill_prefetch (m68k_getpc(), 2);
2726: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
2727: { int flgs = ((uae_s32)(src)) < 0;
2728: int flgo = ((uae_s32)(dst)) < 0;
2729: int flgn = ((uae_s32)(newv)) < 0;
2730: SET_ZFLG (((uae_s32)(newv)) == 0);
2731: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2732: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
2733: COPY_CARRY;
2734: SET_NFLG (flgn != 0);
2735: put_long(dsta,newv);
2736: }}}}}}}m68k_incpc(8);
2737: return 32;
2738: }
2739: unsigned long REGPARAM2 CPUFUNC(op_6b0_0)(uae_u32 opcode) /* ADD */
2740: {
2741: uae_u32 dstreg = opcode & 7;
2742: OpcodeFamily = 11; CurrentInstrCycles = 34;
2743: {{ uae_s32 src = get_ilong(2);
2744: {m68k_incpc(6);
2745: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
2746: BusCyclePenalty += 2;
2747: { uae_s32 dst = get_long(dsta);
2748: { refill_prefetch (m68k_getpc(), 2);
2749: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
2750: { int flgs = ((uae_s32)(src)) < 0;
2751: int flgo = ((uae_s32)(dst)) < 0;
2752: int flgn = ((uae_s32)(newv)) < 0;
2753: SET_ZFLG (((uae_s32)(newv)) == 0);
2754: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2755: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
2756: COPY_CARRY;
2757: SET_NFLG (flgn != 0);
2758: put_long(dsta,newv);
2759: }}}}}}}}return 34;
2760: }
2761: unsigned long REGPARAM2 CPUFUNC(op_6b8_0)(uae_u32 opcode) /* ADD */
2762: {
2763: OpcodeFamily = 11; CurrentInstrCycles = 32;
2764: {{ uae_s32 src = get_ilong(2);
2765: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
2766: { uae_s32 dst = get_long(dsta);
2767: { refill_prefetch (m68k_getpc(), 2);
2768: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
2769: { int flgs = ((uae_s32)(src)) < 0;
2770: int flgo = ((uae_s32)(dst)) < 0;
2771: int flgn = ((uae_s32)(newv)) < 0;
2772: SET_ZFLG (((uae_s32)(newv)) == 0);
2773: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2774: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
2775: COPY_CARRY;
2776: SET_NFLG (flgn != 0);
2777: put_long(dsta,newv);
2778: }}}}}}}m68k_incpc(8);
2779: return 32;
2780: }
2781: unsigned long REGPARAM2 CPUFUNC(op_6b9_0)(uae_u32 opcode) /* ADD */
2782: {
2783: OpcodeFamily = 11; CurrentInstrCycles = 36;
2784: {{ uae_s32 src = get_ilong(2);
2785: { uaecptr dsta = get_ilong(6);
2786: { uae_s32 dst = get_long(dsta);
2787: { refill_prefetch (m68k_getpc(), 2);
2788: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
2789: { int flgs = ((uae_s32)(src)) < 0;
2790: int flgo = ((uae_s32)(dst)) < 0;
2791: int flgn = ((uae_s32)(newv)) < 0;
2792: SET_ZFLG (((uae_s32)(newv)) == 0);
2793: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
2794: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
2795: COPY_CARRY;
2796: SET_NFLG (flgn != 0);
2797: put_long(dsta,newv);
2798: }}}}}}}m68k_incpc(10);
2799: return 36;
2800: }
2801: unsigned long REGPARAM2 CPUFUNC(op_6c0_0)(uae_u32 opcode) /* RTM */
2802: {
2803: uae_u32 srcreg = (opcode & 7);
2804: OpcodeFamily = 101; CurrentInstrCycles = 4;
2805: {m68k_incpc(2);
2806: op_illg(opcode);
2807: }return 4;
2808: }
2809: unsigned long REGPARAM2 CPUFUNC(op_6c8_0)(uae_u32 opcode) /* RTM */
2810: {
2811: uae_u32 srcreg = (opcode & 7);
2812: OpcodeFamily = 101; CurrentInstrCycles = 4;
2813: {m68k_incpc(2);
2814: op_illg(opcode);
2815: }return 4;
2816: }
2817: unsigned long REGPARAM2 CPUFUNC(op_6d0_0)(uae_u32 opcode) /* CALLM */
2818: {
2819: uae_u32 srcreg = (opcode & 7);
2820: OpcodeFamily = 100; CurrentInstrCycles = 4;
2821: {m68k_incpc(2);
2822: op_illg(opcode);
2823: }return 4;
2824: }
2825: unsigned long REGPARAM2 CPUFUNC(op_6e8_0)(uae_u32 opcode) /* CALLM */
2826: {
2827: uae_u32 srcreg = (opcode & 7);
2828: OpcodeFamily = 100; CurrentInstrCycles = 4;
2829: {m68k_incpc(2);
2830: op_illg(opcode);
2831: }return 4;
2832: }
2833: unsigned long REGPARAM2 CPUFUNC(op_6f0_0)(uae_u32 opcode) /* CALLM */
2834: {
2835: uae_u32 srcreg = (opcode & 7);
2836: OpcodeFamily = 100; CurrentInstrCycles = 4;
2837: {m68k_incpc(2);
2838: op_illg(opcode);
2839: }return 4;
2840: }
2841: unsigned long REGPARAM2 CPUFUNC(op_6f8_0)(uae_u32 opcode) /* CALLM */
2842: {
2843: OpcodeFamily = 100; CurrentInstrCycles = 4;
2844: {m68k_incpc(2);
2845: op_illg(opcode);
2846: }return 4;
2847: }
2848: unsigned long REGPARAM2 CPUFUNC(op_6f9_0)(uae_u32 opcode) /* CALLM */
2849: {
2850: OpcodeFamily = 100; CurrentInstrCycles = 4;
2851: {m68k_incpc(2);
2852: op_illg(opcode);
2853: }return 4;
2854: }
2855: unsigned long REGPARAM2 CPUFUNC(op_6fa_0)(uae_u32 opcode) /* CALLM */
2856: {
2857: OpcodeFamily = 100; CurrentInstrCycles = 4;
2858: {m68k_incpc(2);
2859: op_illg(opcode);
2860: }return 4;
2861: }
2862: unsigned long REGPARAM2 CPUFUNC(op_6fb_0)(uae_u32 opcode) /* CALLM */
2863: {
2864: OpcodeFamily = 100; CurrentInstrCycles = 4;
2865: {m68k_incpc(2);
2866: op_illg(opcode);
2867: }return 4;
2868: }
2869: unsigned long REGPARAM2 CPUFUNC(op_800_0)(uae_u32 opcode) /* BTST */
2870: {
2871: uae_u32 dstreg = opcode & 7;
2872: OpcodeFamily = 21; CurrentInstrCycles = 10;
2873: {{ uae_s16 src = get_iword(2);
2874: { uae_s32 dst = m68k_dreg(regs, dstreg);
2875: src &= 31;
2876: SET_ZFLG (1 ^ ((dst >> src) & 1));
2877: }}}m68k_incpc(4);
2878: return 10;
2879: }
2880: unsigned long REGPARAM2 CPUFUNC(op_810_0)(uae_u32 opcode) /* BTST */
2881: {
2882: uae_u32 dstreg = opcode & 7;
2883: OpcodeFamily = 21; CurrentInstrCycles = 12;
2884: {{ uae_s16 src = get_iword(2);
2885: { uaecptr dsta = m68k_areg(regs, dstreg);
2886: { uae_s8 dst = get_byte(dsta);
2887: src &= 7;
2888: SET_ZFLG (1 ^ ((dst >> src) & 1));
2889: }}}}m68k_incpc(4);
2890: return 12;
2891: }
2892: unsigned long REGPARAM2 CPUFUNC(op_818_0)(uae_u32 opcode) /* BTST */
2893: {
2894: uae_u32 dstreg = opcode & 7;
2895: OpcodeFamily = 21; CurrentInstrCycles = 12;
2896: {{ uae_s16 src = get_iword(2);
2897: { uaecptr dsta = m68k_areg(regs, dstreg);
2898: { uae_s8 dst = get_byte(dsta);
2899: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
2900: src &= 7;
2901: SET_ZFLG (1 ^ ((dst >> src) & 1));
2902: }}}}m68k_incpc(4);
2903: return 12;
2904: }
2905: unsigned long REGPARAM2 CPUFUNC(op_820_0)(uae_u32 opcode) /* BTST */
2906: {
2907: uae_u32 dstreg = opcode & 7;
2908: OpcodeFamily = 21; CurrentInstrCycles = 14;
2909: {{ uae_s16 src = get_iword(2);
2910: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
2911: { uae_s8 dst = get_byte(dsta);
2912: m68k_areg (regs, dstreg) = dsta;
2913: src &= 7;
2914: SET_ZFLG (1 ^ ((dst >> src) & 1));
2915: }}}}m68k_incpc(4);
2916: return 14;
2917: }
2918: unsigned long REGPARAM2 CPUFUNC(op_828_0)(uae_u32 opcode) /* BTST */
2919: {
2920: uae_u32 dstreg = opcode & 7;
2921: OpcodeFamily = 21; CurrentInstrCycles = 16;
2922: {{ uae_s16 src = get_iword(2);
2923: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
2924: { uae_s8 dst = get_byte(dsta);
2925: src &= 7;
2926: SET_ZFLG (1 ^ ((dst >> src) & 1));
2927: }}}}m68k_incpc(6);
2928: return 16;
2929: }
2930: unsigned long REGPARAM2 CPUFUNC(op_830_0)(uae_u32 opcode) /* BTST */
2931: {
2932: uae_u32 dstreg = opcode & 7;
2933: OpcodeFamily = 21; CurrentInstrCycles = 18;
2934: {{ uae_s16 src = get_iword(2);
2935: {m68k_incpc(4);
2936: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
2937: BusCyclePenalty += 2;
2938: { uae_s8 dst = get_byte(dsta);
2939: src &= 7;
2940: SET_ZFLG (1 ^ ((dst >> src) & 1));
2941: }}}}}return 18;
2942: }
2943: unsigned long REGPARAM2 CPUFUNC(op_838_0)(uae_u32 opcode) /* BTST */
2944: {
2945: OpcodeFamily = 21; CurrentInstrCycles = 16;
2946: {{ uae_s16 src = get_iword(2);
2947: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
2948: { uae_s8 dst = get_byte(dsta);
2949: src &= 7;
2950: SET_ZFLG (1 ^ ((dst >> src) & 1));
2951: }}}}m68k_incpc(6);
2952: return 16;
2953: }
2954: unsigned long REGPARAM2 CPUFUNC(op_839_0)(uae_u32 opcode) /* BTST */
2955: {
2956: OpcodeFamily = 21; CurrentInstrCycles = 20;
2957: {{ uae_s16 src = get_iword(2);
2958: { uaecptr dsta = get_ilong(4);
2959: { uae_s8 dst = get_byte(dsta);
2960: src &= 7;
2961: SET_ZFLG (1 ^ ((dst >> src) & 1));
2962: }}}}m68k_incpc(8);
2963: return 20;
2964: }
2965: unsigned long REGPARAM2 CPUFUNC(op_83a_0)(uae_u32 opcode) /* BTST */
2966: {
2967: uae_u32 dstreg = 2;
2968: OpcodeFamily = 21; CurrentInstrCycles = 16;
2969: {{ uae_s16 src = get_iword(2);
2970: { uaecptr dsta = m68k_getpc () + 4;
2971: dsta += (uae_s32)(uae_s16)get_iword(4);
2972: { uae_s8 dst = get_byte(dsta);
2973: src &= 7;
2974: SET_ZFLG (1 ^ ((dst >> src) & 1));
2975: }}}}m68k_incpc(6);
2976: return 16;
2977: }
2978: unsigned long REGPARAM2 CPUFUNC(op_83b_0)(uae_u32 opcode) /* BTST */
2979: {
2980: uae_u32 dstreg = 3;
2981: OpcodeFamily = 21; CurrentInstrCycles = 18;
2982: {{ uae_s16 src = get_iword(2);
2983: {m68k_incpc(4);
2984: { uaecptr tmppc = m68k_getpc();
2985: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
2986: BusCyclePenalty += 2;
2987: { uae_s8 dst = get_byte(dsta);
2988: src &= 7;
2989: SET_ZFLG (1 ^ ((dst >> src) & 1));
2990: }}}}}return 18;
2991: }
2992: unsigned long REGPARAM2 CPUFUNC(op_83c_0)(uae_u32 opcode) /* BTST */
2993: {
2994: OpcodeFamily = 21; CurrentInstrCycles = 12;
2995: {{ uae_s16 src = get_iword(2);
2996: { uae_s8 dst = get_ibyte(4);
2997: src &= 7;
2998: SET_ZFLG (1 ^ ((dst >> src) & 1));
2999: }}}m68k_incpc(6);
3000: return 12;
3001: }
3002: unsigned long REGPARAM2 CPUFUNC(op_840_0)(uae_u32 opcode) /* BCHG */
3003: {
3004: uae_u32 dstreg = opcode & 7;
3005: OpcodeFamily = 22; CurrentInstrCycles = 12;
3006: {{ uae_s16 src = get_iword(2);
3007: { uae_s32 dst = m68k_dreg(regs, dstreg);
3008: src &= 31;
3009: dst ^= (1 << src);
3010: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3011: m68k_dreg(regs, dstreg) = (dst);
3012: }}}m68k_incpc(4);
3013: return 12;
3014: }
3015: unsigned long REGPARAM2 CPUFUNC(op_850_0)(uae_u32 opcode) /* BCHG */
3016: {
3017: uae_u32 dstreg = opcode & 7;
3018: OpcodeFamily = 22; CurrentInstrCycles = 16;
3019: {{ uae_s16 src = get_iword(2);
3020: { uaecptr dsta = m68k_areg(regs, dstreg);
3021: { uae_s8 dst = get_byte(dsta);
3022: src &= 7;
3023: dst ^= (1 << src);
3024: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3025: put_byte(dsta,dst);
3026: }}}}m68k_incpc(4);
3027: return 16;
3028: }
3029: unsigned long REGPARAM2 CPUFUNC(op_858_0)(uae_u32 opcode) /* BCHG */
3030: {
3031: uae_u32 dstreg = opcode & 7;
3032: OpcodeFamily = 22; CurrentInstrCycles = 16;
3033: {{ uae_s16 src = get_iword(2);
3034: { uaecptr dsta = m68k_areg(regs, dstreg);
3035: { uae_s8 dst = get_byte(dsta);
3036: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
3037: src &= 7;
3038: dst ^= (1 << src);
3039: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3040: put_byte(dsta,dst);
3041: }}}}m68k_incpc(4);
3042: return 16;
3043: }
3044: unsigned long REGPARAM2 CPUFUNC(op_860_0)(uae_u32 opcode) /* BCHG */
3045: {
3046: uae_u32 dstreg = opcode & 7;
3047: OpcodeFamily = 22; CurrentInstrCycles = 18;
3048: {{ uae_s16 src = get_iword(2);
3049: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
3050: { uae_s8 dst = get_byte(dsta);
3051: m68k_areg (regs, dstreg) = dsta;
3052: src &= 7;
3053: dst ^= (1 << src);
3054: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3055: put_byte(dsta,dst);
3056: }}}}m68k_incpc(4);
3057: return 18;
3058: }
3059: unsigned long REGPARAM2 CPUFUNC(op_868_0)(uae_u32 opcode) /* BCHG */
3060: {
3061: uae_u32 dstreg = opcode & 7;
3062: OpcodeFamily = 22; CurrentInstrCycles = 20;
3063: {{ uae_s16 src = get_iword(2);
3064: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
3065: { uae_s8 dst = get_byte(dsta);
3066: src &= 7;
3067: dst ^= (1 << src);
3068: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3069: put_byte(dsta,dst);
3070: }}}}m68k_incpc(6);
3071: return 20;
3072: }
3073: unsigned long REGPARAM2 CPUFUNC(op_870_0)(uae_u32 opcode) /* BCHG */
3074: {
3075: uae_u32 dstreg = opcode & 7;
3076: OpcodeFamily = 22; CurrentInstrCycles = 22;
3077: {{ uae_s16 src = get_iword(2);
3078: {m68k_incpc(4);
3079: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
3080: BusCyclePenalty += 2;
3081: { uae_s8 dst = get_byte(dsta);
3082: src &= 7;
3083: dst ^= (1 << src);
3084: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3085: put_byte(dsta,dst);
3086: }}}}}return 22;
3087: }
3088: unsigned long REGPARAM2 CPUFUNC(op_878_0)(uae_u32 opcode) /* BCHG */
3089: {
3090: OpcodeFamily = 22; CurrentInstrCycles = 20;
3091: {{ uae_s16 src = get_iword(2);
3092: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
3093: { uae_s8 dst = get_byte(dsta);
3094: src &= 7;
3095: dst ^= (1 << src);
3096: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3097: put_byte(dsta,dst);
3098: }}}}m68k_incpc(6);
3099: return 20;
3100: }
3101: unsigned long REGPARAM2 CPUFUNC(op_879_0)(uae_u32 opcode) /* BCHG */
3102: {
3103: OpcodeFamily = 22; CurrentInstrCycles = 24;
3104: {{ uae_s16 src = get_iword(2);
3105: { uaecptr dsta = get_ilong(4);
3106: { uae_s8 dst = get_byte(dsta);
3107: src &= 7;
3108: dst ^= (1 << src);
3109: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3110: put_byte(dsta,dst);
3111: }}}}m68k_incpc(8);
3112: return 24;
3113: }
3114: unsigned long REGPARAM2 CPUFUNC(op_87a_0)(uae_u32 opcode) /* BCHG */
3115: {
3116: uae_u32 dstreg = 2;
3117: OpcodeFamily = 22; CurrentInstrCycles = 20;
3118: {{ uae_s16 src = get_iword(2);
3119: { uaecptr dsta = m68k_getpc () + 4;
3120: dsta += (uae_s32)(uae_s16)get_iword(4);
3121: { uae_s8 dst = get_byte(dsta);
3122: src &= 7;
3123: dst ^= (1 << src);
3124: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3125: put_byte(dsta,dst);
3126: }}}}m68k_incpc(6);
3127: return 20;
3128: }
3129: unsigned long REGPARAM2 CPUFUNC(op_87b_0)(uae_u32 opcode) /* BCHG */
3130: {
3131: uae_u32 dstreg = 3;
3132: OpcodeFamily = 22; CurrentInstrCycles = 22;
3133: {{ uae_s16 src = get_iword(2);
3134: {m68k_incpc(4);
3135: { uaecptr tmppc = m68k_getpc();
3136: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
3137: BusCyclePenalty += 2;
3138: { uae_s8 dst = get_byte(dsta);
3139: src &= 7;
3140: dst ^= (1 << src);
3141: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
3142: put_byte(dsta,dst);
3143: }}}}}return 22;
3144: }
3145: unsigned long REGPARAM2 CPUFUNC(op_880_0)(uae_u32 opcode) /* BCLR */
3146: {
3147: uae_u32 dstreg = opcode & 7;
3148: OpcodeFamily = 23; CurrentInstrCycles = 14;
3149: {{ uae_s16 src = get_iword(2);
3150: { uae_s32 dst = m68k_dreg(regs, dstreg);
3151: src &= 31;
3152: SET_ZFLG (1 ^ ((dst >> src) & 1));
3153: dst &= ~(1 << src);
3154: m68k_dreg(regs, dstreg) = (dst);
3155: if ( src < 16 ) { m68k_incpc(4); return 12; }
3156: }}}m68k_incpc(4);
3157: return 14;
3158: }
3159: unsigned long REGPARAM2 CPUFUNC(op_890_0)(uae_u32 opcode) /* BCLR */
3160: {
3161: uae_u32 dstreg = opcode & 7;
3162: OpcodeFamily = 23; CurrentInstrCycles = 16;
3163: {{ uae_s16 src = get_iword(2);
3164: { uaecptr dsta = m68k_areg(regs, dstreg);
3165: { uae_s8 dst = get_byte(dsta);
3166: src &= 7;
3167: SET_ZFLG (1 ^ ((dst >> src) & 1));
3168: dst &= ~(1 << src);
3169: put_byte(dsta,dst);
3170: }}}}m68k_incpc(4);
3171: return 16;
3172: }
3173: unsigned long REGPARAM2 CPUFUNC(op_898_0)(uae_u32 opcode) /* BCLR */
3174: {
3175: uae_u32 dstreg = opcode & 7;
3176: OpcodeFamily = 23; CurrentInstrCycles = 16;
3177: {{ uae_s16 src = get_iword(2);
3178: { uaecptr dsta = m68k_areg(regs, dstreg);
3179: { uae_s8 dst = get_byte(dsta);
3180: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
3181: src &= 7;
3182: SET_ZFLG (1 ^ ((dst >> src) & 1));
3183: dst &= ~(1 << src);
3184: put_byte(dsta,dst);
3185: }}}}m68k_incpc(4);
3186: return 16;
3187: }
3188: unsigned long REGPARAM2 CPUFUNC(op_8a0_0)(uae_u32 opcode) /* BCLR */
3189: {
3190: uae_u32 dstreg = opcode & 7;
3191: OpcodeFamily = 23; CurrentInstrCycles = 18;
3192: {{ uae_s16 src = get_iword(2);
3193: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
3194: { uae_s8 dst = get_byte(dsta);
3195: m68k_areg (regs, dstreg) = dsta;
3196: src &= 7;
3197: SET_ZFLG (1 ^ ((dst >> src) & 1));
3198: dst &= ~(1 << src);
3199: put_byte(dsta,dst);
3200: }}}}m68k_incpc(4);
3201: return 18;
3202: }
3203: unsigned long REGPARAM2 CPUFUNC(op_8a8_0)(uae_u32 opcode) /* BCLR */
3204: {
3205: uae_u32 dstreg = opcode & 7;
3206: OpcodeFamily = 23; CurrentInstrCycles = 20;
3207: {{ uae_s16 src = get_iword(2);
3208: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
3209: { uae_s8 dst = get_byte(dsta);
3210: src &= 7;
3211: SET_ZFLG (1 ^ ((dst >> src) & 1));
3212: dst &= ~(1 << src);
3213: put_byte(dsta,dst);
3214: }}}}m68k_incpc(6);
3215: return 20;
3216: }
3217: unsigned long REGPARAM2 CPUFUNC(op_8b0_0)(uae_u32 opcode) /* BCLR */
3218: {
3219: uae_u32 dstreg = opcode & 7;
3220: OpcodeFamily = 23; CurrentInstrCycles = 22;
3221: {{ uae_s16 src = get_iword(2);
3222: {m68k_incpc(4);
3223: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
3224: BusCyclePenalty += 2;
3225: { uae_s8 dst = get_byte(dsta);
3226: src &= 7;
3227: SET_ZFLG (1 ^ ((dst >> src) & 1));
3228: dst &= ~(1 << src);
3229: put_byte(dsta,dst);
3230: }}}}}return 22;
3231: }
3232: unsigned long REGPARAM2 CPUFUNC(op_8b8_0)(uae_u32 opcode) /* BCLR */
3233: {
3234: OpcodeFamily = 23; CurrentInstrCycles = 20;
3235: {{ uae_s16 src = get_iword(2);
3236: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
3237: { uae_s8 dst = get_byte(dsta);
3238: src &= 7;
3239: SET_ZFLG (1 ^ ((dst >> src) & 1));
3240: dst &= ~(1 << src);
3241: put_byte(dsta,dst);
3242: }}}}m68k_incpc(6);
3243: return 20;
3244: }
3245: unsigned long REGPARAM2 CPUFUNC(op_8b9_0)(uae_u32 opcode) /* BCLR */
3246: {
3247: OpcodeFamily = 23; CurrentInstrCycles = 24;
3248: {{ uae_s16 src = get_iword(2);
3249: { uaecptr dsta = get_ilong(4);
3250: { uae_s8 dst = get_byte(dsta);
3251: src &= 7;
3252: SET_ZFLG (1 ^ ((dst >> src) & 1));
3253: dst &= ~(1 << src);
3254: put_byte(dsta,dst);
3255: }}}}m68k_incpc(8);
3256: return 24;
3257: }
3258: unsigned long REGPARAM2 CPUFUNC(op_8ba_0)(uae_u32 opcode) /* BCLR */
3259: {
3260: uae_u32 dstreg = 2;
3261: OpcodeFamily = 23; CurrentInstrCycles = 20;
3262: {{ uae_s16 src = get_iword(2);
3263: { uaecptr dsta = m68k_getpc () + 4;
3264: dsta += (uae_s32)(uae_s16)get_iword(4);
3265: { uae_s8 dst = get_byte(dsta);
3266: src &= 7;
3267: SET_ZFLG (1 ^ ((dst >> src) & 1));
3268: dst &= ~(1 << src);
3269: put_byte(dsta,dst);
3270: }}}}m68k_incpc(6);
3271: return 20;
3272: }
3273: unsigned long REGPARAM2 CPUFUNC(op_8bb_0)(uae_u32 opcode) /* BCLR */
3274: {
3275: uae_u32 dstreg = 3;
3276: OpcodeFamily = 23; CurrentInstrCycles = 22;
3277: {{ uae_s16 src = get_iword(2);
3278: {m68k_incpc(4);
3279: { uaecptr tmppc = m68k_getpc();
3280: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
3281: BusCyclePenalty += 2;
3282: { uae_s8 dst = get_byte(dsta);
3283: src &= 7;
3284: SET_ZFLG (1 ^ ((dst >> src) & 1));
3285: dst &= ~(1 << src);
3286: put_byte(dsta,dst);
3287: }}}}}return 22;
3288: }
3289: unsigned long REGPARAM2 CPUFUNC(op_8c0_0)(uae_u32 opcode) /* BSET */
3290: {
3291: uae_u32 dstreg = opcode & 7;
3292: OpcodeFamily = 24; CurrentInstrCycles = 12;
3293: {{ uae_s16 src = get_iword(2);
3294: { uae_s32 dst = m68k_dreg(regs, dstreg);
3295: src &= 31;
3296: SET_ZFLG (1 ^ ((dst >> src) & 1));
3297: dst |= (1 << src);
3298: m68k_dreg(regs, dstreg) = (dst);
3299: }}}m68k_incpc(4);
3300: return 12;
3301: }
3302: unsigned long REGPARAM2 CPUFUNC(op_8d0_0)(uae_u32 opcode) /* BSET */
3303: {
3304: uae_u32 dstreg = opcode & 7;
3305: OpcodeFamily = 24; CurrentInstrCycles = 16;
3306: {{ uae_s16 src = get_iword(2);
3307: { uaecptr dsta = m68k_areg(regs, dstreg);
3308: { uae_s8 dst = get_byte(dsta);
3309: src &= 7;
3310: SET_ZFLG (1 ^ ((dst >> src) & 1));
3311: dst |= (1 << src);
3312: put_byte(dsta,dst);
3313: }}}}m68k_incpc(4);
3314: return 16;
3315: }
3316: unsigned long REGPARAM2 CPUFUNC(op_8d8_0)(uae_u32 opcode) /* BSET */
3317: {
3318: uae_u32 dstreg = opcode & 7;
3319: OpcodeFamily = 24; CurrentInstrCycles = 16;
3320: {{ uae_s16 src = get_iword(2);
3321: { uaecptr dsta = m68k_areg(regs, dstreg);
3322: { uae_s8 dst = get_byte(dsta);
3323: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
3324: src &= 7;
3325: SET_ZFLG (1 ^ ((dst >> src) & 1));
3326: dst |= (1 << src);
3327: put_byte(dsta,dst);
3328: }}}}m68k_incpc(4);
3329: return 16;
3330: }
3331: unsigned long REGPARAM2 CPUFUNC(op_8e0_0)(uae_u32 opcode) /* BSET */
3332: {
3333: uae_u32 dstreg = opcode & 7;
3334: OpcodeFamily = 24; CurrentInstrCycles = 18;
3335: {{ uae_s16 src = get_iword(2);
3336: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
3337: { uae_s8 dst = get_byte(dsta);
3338: m68k_areg (regs, dstreg) = dsta;
3339: src &= 7;
3340: SET_ZFLG (1 ^ ((dst >> src) & 1));
3341: dst |= (1 << src);
3342: put_byte(dsta,dst);
3343: }}}}m68k_incpc(4);
3344: return 18;
3345: }
3346: unsigned long REGPARAM2 CPUFUNC(op_8e8_0)(uae_u32 opcode) /* BSET */
3347: {
3348: uae_u32 dstreg = opcode & 7;
3349: OpcodeFamily = 24; CurrentInstrCycles = 20;
3350: {{ uae_s16 src = get_iword(2);
3351: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
3352: { uae_s8 dst = get_byte(dsta);
3353: src &= 7;
3354: SET_ZFLG (1 ^ ((dst >> src) & 1));
3355: dst |= (1 << src);
3356: put_byte(dsta,dst);
3357: }}}}m68k_incpc(6);
3358: return 20;
3359: }
3360: unsigned long REGPARAM2 CPUFUNC(op_8f0_0)(uae_u32 opcode) /* BSET */
3361: {
3362: uae_u32 dstreg = opcode & 7;
3363: OpcodeFamily = 24; CurrentInstrCycles = 22;
3364: {{ uae_s16 src = get_iword(2);
3365: {m68k_incpc(4);
3366: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
3367: BusCyclePenalty += 2;
3368: { uae_s8 dst = get_byte(dsta);
3369: src &= 7;
3370: SET_ZFLG (1 ^ ((dst >> src) & 1));
3371: dst |= (1 << src);
3372: put_byte(dsta,dst);
3373: }}}}}return 22;
3374: }
3375: unsigned long REGPARAM2 CPUFUNC(op_8f8_0)(uae_u32 opcode) /* BSET */
3376: {
3377: OpcodeFamily = 24; CurrentInstrCycles = 20;
3378: {{ uae_s16 src = get_iword(2);
3379: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
3380: { uae_s8 dst = get_byte(dsta);
3381: src &= 7;
3382: SET_ZFLG (1 ^ ((dst >> src) & 1));
3383: dst |= (1 << src);
3384: put_byte(dsta,dst);
3385: }}}}m68k_incpc(6);
3386: return 20;
3387: }
3388: unsigned long REGPARAM2 CPUFUNC(op_8f9_0)(uae_u32 opcode) /* BSET */
3389: {
3390: OpcodeFamily = 24; CurrentInstrCycles = 24;
3391: {{ uae_s16 src = get_iword(2);
3392: { uaecptr dsta = get_ilong(4);
3393: { uae_s8 dst = get_byte(dsta);
3394: src &= 7;
3395: SET_ZFLG (1 ^ ((dst >> src) & 1));
3396: dst |= (1 << src);
3397: put_byte(dsta,dst);
3398: }}}}m68k_incpc(8);
3399: return 24;
3400: }
3401: unsigned long REGPARAM2 CPUFUNC(op_8fa_0)(uae_u32 opcode) /* BSET */
3402: {
3403: uae_u32 dstreg = 2;
3404: OpcodeFamily = 24; CurrentInstrCycles = 20;
3405: {{ uae_s16 src = get_iword(2);
3406: { uaecptr dsta = m68k_getpc () + 4;
3407: dsta += (uae_s32)(uae_s16)get_iword(4);
3408: { uae_s8 dst = get_byte(dsta);
3409: src &= 7;
3410: SET_ZFLG (1 ^ ((dst >> src) & 1));
3411: dst |= (1 << src);
3412: put_byte(dsta,dst);
3413: }}}}m68k_incpc(6);
3414: return 20;
3415: }
3416: unsigned long REGPARAM2 CPUFUNC(op_8fb_0)(uae_u32 opcode) /* BSET */
3417: {
3418: uae_u32 dstreg = 3;
3419: OpcodeFamily = 24; CurrentInstrCycles = 22;
3420: {{ uae_s16 src = get_iword(2);
3421: {m68k_incpc(4);
3422: { uaecptr tmppc = m68k_getpc();
3423: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
3424: BusCyclePenalty += 2;
3425: { uae_s8 dst = get_byte(dsta);
3426: src &= 7;
3427: SET_ZFLG (1 ^ ((dst >> src) & 1));
3428: dst |= (1 << src);
3429: put_byte(dsta,dst);
3430: }}}}}return 22;
3431: }
3432: unsigned long REGPARAM2 CPUFUNC(op_a00_0)(uae_u32 opcode) /* EOR */
3433: {
3434: uae_u32 dstreg = opcode & 7;
3435: OpcodeFamily = 3; CurrentInstrCycles = 8;
3436: {{ uae_s8 src = get_ibyte(2);
3437: { uae_s8 dst = m68k_dreg(regs, dstreg);
3438: src ^= dst;
3439: CLEAR_CZNV;
3440: SET_ZFLG (((uae_s8)(src)) == 0);
3441: SET_NFLG (((uae_s8)(src)) < 0);
3442: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
3443: }}}m68k_incpc(4);
3444: return 8;
3445: }
3446: unsigned long REGPARAM2 CPUFUNC(op_a10_0)(uae_u32 opcode) /* EOR */
3447: {
3448: uae_u32 dstreg = opcode & 7;
3449: OpcodeFamily = 3; CurrentInstrCycles = 16;
3450: {{ uae_s8 src = get_ibyte(2);
3451: { uaecptr dsta = m68k_areg(regs, dstreg);
3452: { uae_s8 dst = get_byte(dsta);
3453: src ^= dst;
3454: CLEAR_CZNV;
3455: SET_ZFLG (((uae_s8)(src)) == 0);
3456: SET_NFLG (((uae_s8)(src)) < 0);
3457: put_byte(dsta,src);
3458: }}}}m68k_incpc(4);
3459: return 16;
3460: }
3461: unsigned long REGPARAM2 CPUFUNC(op_a18_0)(uae_u32 opcode) /* EOR */
3462: {
3463: uae_u32 dstreg = opcode & 7;
3464: OpcodeFamily = 3; CurrentInstrCycles = 16;
3465: {{ uae_s8 src = get_ibyte(2);
3466: { uaecptr dsta = m68k_areg(regs, dstreg);
3467: { uae_s8 dst = get_byte(dsta);
3468: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
3469: src ^= dst;
3470: CLEAR_CZNV;
3471: SET_ZFLG (((uae_s8)(src)) == 0);
3472: SET_NFLG (((uae_s8)(src)) < 0);
3473: put_byte(dsta,src);
3474: }}}}m68k_incpc(4);
3475: return 16;
3476: }
3477: unsigned long REGPARAM2 CPUFUNC(op_a20_0)(uae_u32 opcode) /* EOR */
3478: {
3479: uae_u32 dstreg = opcode & 7;
3480: OpcodeFamily = 3; CurrentInstrCycles = 18;
3481: {{ uae_s8 src = get_ibyte(2);
3482: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
3483: { uae_s8 dst = get_byte(dsta);
3484: m68k_areg (regs, dstreg) = dsta;
3485: src ^= dst;
3486: CLEAR_CZNV;
3487: SET_ZFLG (((uae_s8)(src)) == 0);
3488: SET_NFLG (((uae_s8)(src)) < 0);
3489: put_byte(dsta,src);
3490: }}}}m68k_incpc(4);
3491: return 18;
3492: }
3493: unsigned long REGPARAM2 CPUFUNC(op_a28_0)(uae_u32 opcode) /* EOR */
3494: {
3495: uae_u32 dstreg = opcode & 7;
3496: OpcodeFamily = 3; CurrentInstrCycles = 20;
3497: {{ uae_s8 src = get_ibyte(2);
3498: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
3499: { uae_s8 dst = get_byte(dsta);
3500: src ^= dst;
3501: CLEAR_CZNV;
3502: SET_ZFLG (((uae_s8)(src)) == 0);
3503: SET_NFLG (((uae_s8)(src)) < 0);
3504: put_byte(dsta,src);
3505: }}}}m68k_incpc(6);
3506: return 20;
3507: }
3508: unsigned long REGPARAM2 CPUFUNC(op_a30_0)(uae_u32 opcode) /* EOR */
3509: {
3510: uae_u32 dstreg = opcode & 7;
3511: OpcodeFamily = 3; CurrentInstrCycles = 22;
3512: {{ uae_s8 src = get_ibyte(2);
3513: {m68k_incpc(4);
3514: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
3515: BusCyclePenalty += 2;
3516: { uae_s8 dst = get_byte(dsta);
3517: src ^= dst;
3518: CLEAR_CZNV;
3519: SET_ZFLG (((uae_s8)(src)) == 0);
3520: SET_NFLG (((uae_s8)(src)) < 0);
3521: put_byte(dsta,src);
3522: }}}}}return 22;
3523: }
3524: unsigned long REGPARAM2 CPUFUNC(op_a38_0)(uae_u32 opcode) /* EOR */
3525: {
3526: OpcodeFamily = 3; CurrentInstrCycles = 20;
3527: {{ uae_s8 src = get_ibyte(2);
3528: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
3529: { uae_s8 dst = get_byte(dsta);
3530: src ^= dst;
3531: CLEAR_CZNV;
3532: SET_ZFLG (((uae_s8)(src)) == 0);
3533: SET_NFLG (((uae_s8)(src)) < 0);
3534: put_byte(dsta,src);
3535: }}}}m68k_incpc(6);
3536: return 20;
3537: }
3538: unsigned long REGPARAM2 CPUFUNC(op_a39_0)(uae_u32 opcode) /* EOR */
3539: {
3540: OpcodeFamily = 3; CurrentInstrCycles = 24;
3541: {{ uae_s8 src = get_ibyte(2);
3542: { uaecptr dsta = get_ilong(4);
3543: { uae_s8 dst = get_byte(dsta);
3544: src ^= dst;
3545: CLEAR_CZNV;
3546: SET_ZFLG (((uae_s8)(src)) == 0);
3547: SET_NFLG (((uae_s8)(src)) < 0);
3548: put_byte(dsta,src);
3549: }}}}m68k_incpc(8);
3550: return 24;
3551: }
3552: unsigned long REGPARAM2 CPUFUNC(op_a3c_0)(uae_u32 opcode) /* EORSR */
3553: {
3554: OpcodeFamily = 6; CurrentInstrCycles = 20;
3555: { MakeSR();
3556: { uae_s16 src = get_iword(2);
3557: src &= 0xFF;
3558: regs.sr ^= src;
3559: MakeFromSR();
3560: }}m68k_incpc(4);
3561: return 20;
3562: }
3563: unsigned long REGPARAM2 CPUFUNC(op_a40_0)(uae_u32 opcode) /* EOR */
3564: {
3565: uae_u32 dstreg = opcode & 7;
3566: OpcodeFamily = 3; CurrentInstrCycles = 8;
3567: {{ uae_s16 src = get_iword(2);
3568: { uae_s16 dst = m68k_dreg(regs, dstreg);
3569: src ^= dst;
3570: CLEAR_CZNV;
3571: SET_ZFLG (((uae_s16)(src)) == 0);
3572: SET_NFLG (((uae_s16)(src)) < 0);
3573: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
3574: }}}m68k_incpc(4);
3575: return 8;
3576: }
3577: unsigned long REGPARAM2 CPUFUNC(op_a50_0)(uae_u32 opcode) /* EOR */
3578: {
3579: uae_u32 dstreg = opcode & 7;
3580: OpcodeFamily = 3; CurrentInstrCycles = 16;
3581: {{ uae_s16 src = get_iword(2);
3582: { uaecptr dsta = m68k_areg(regs, dstreg);
3583: { uae_s16 dst = get_word(dsta);
3584: src ^= dst;
3585: CLEAR_CZNV;
3586: SET_ZFLG (((uae_s16)(src)) == 0);
3587: SET_NFLG (((uae_s16)(src)) < 0);
3588: put_word(dsta,src);
3589: }}}}m68k_incpc(4);
3590: return 16;
3591: }
3592: unsigned long REGPARAM2 CPUFUNC(op_a58_0)(uae_u32 opcode) /* EOR */
3593: {
3594: uae_u32 dstreg = opcode & 7;
3595: OpcodeFamily = 3; CurrentInstrCycles = 16;
3596: {{ uae_s16 src = get_iword(2);
3597: { uaecptr dsta = m68k_areg(regs, dstreg);
3598: { uae_s16 dst = get_word(dsta);
3599: m68k_areg(regs, dstreg) += 2;
3600: src ^= dst;
3601: CLEAR_CZNV;
3602: SET_ZFLG (((uae_s16)(src)) == 0);
3603: SET_NFLG (((uae_s16)(src)) < 0);
3604: put_word(dsta,src);
3605: }}}}m68k_incpc(4);
3606: return 16;
3607: }
3608: unsigned long REGPARAM2 CPUFUNC(op_a60_0)(uae_u32 opcode) /* EOR */
3609: {
3610: uae_u32 dstreg = opcode & 7;
3611: OpcodeFamily = 3; CurrentInstrCycles = 18;
3612: {{ uae_s16 src = get_iword(2);
3613: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
3614: { uae_s16 dst = get_word(dsta);
3615: m68k_areg (regs, dstreg) = dsta;
3616: src ^= dst;
3617: CLEAR_CZNV;
3618: SET_ZFLG (((uae_s16)(src)) == 0);
3619: SET_NFLG (((uae_s16)(src)) < 0);
3620: put_word(dsta,src);
3621: }}}}m68k_incpc(4);
3622: return 18;
3623: }
3624: unsigned long REGPARAM2 CPUFUNC(op_a68_0)(uae_u32 opcode) /* EOR */
3625: {
3626: uae_u32 dstreg = opcode & 7;
3627: OpcodeFamily = 3; CurrentInstrCycles = 20;
3628: {{ uae_s16 src = get_iword(2);
3629: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
3630: { uae_s16 dst = get_word(dsta);
3631: src ^= dst;
3632: CLEAR_CZNV;
3633: SET_ZFLG (((uae_s16)(src)) == 0);
3634: SET_NFLG (((uae_s16)(src)) < 0);
3635: put_word(dsta,src);
3636: }}}}m68k_incpc(6);
3637: return 20;
3638: }
3639: unsigned long REGPARAM2 CPUFUNC(op_a70_0)(uae_u32 opcode) /* EOR */
3640: {
3641: uae_u32 dstreg = opcode & 7;
3642: OpcodeFamily = 3; CurrentInstrCycles = 22;
3643: {{ uae_s16 src = get_iword(2);
3644: {m68k_incpc(4);
3645: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
3646: BusCyclePenalty += 2;
3647: { uae_s16 dst = get_word(dsta);
3648: src ^= dst;
3649: CLEAR_CZNV;
3650: SET_ZFLG (((uae_s16)(src)) == 0);
3651: SET_NFLG (((uae_s16)(src)) < 0);
3652: put_word(dsta,src);
3653: }}}}}return 22;
3654: }
3655: unsigned long REGPARAM2 CPUFUNC(op_a78_0)(uae_u32 opcode) /* EOR */
3656: {
3657: OpcodeFamily = 3; CurrentInstrCycles = 20;
3658: {{ uae_s16 src = get_iword(2);
3659: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
3660: { uae_s16 dst = get_word(dsta);
3661: src ^= dst;
3662: CLEAR_CZNV;
3663: SET_ZFLG (((uae_s16)(src)) == 0);
3664: SET_NFLG (((uae_s16)(src)) < 0);
3665: put_word(dsta,src);
3666: }}}}m68k_incpc(6);
3667: return 20;
3668: }
3669: unsigned long REGPARAM2 CPUFUNC(op_a79_0)(uae_u32 opcode) /* EOR */
3670: {
3671: OpcodeFamily = 3; CurrentInstrCycles = 24;
3672: {{ uae_s16 src = get_iword(2);
3673: { uaecptr dsta = get_ilong(4);
3674: { uae_s16 dst = get_word(dsta);
3675: src ^= dst;
3676: CLEAR_CZNV;
3677: SET_ZFLG (((uae_s16)(src)) == 0);
3678: SET_NFLG (((uae_s16)(src)) < 0);
3679: put_word(dsta,src);
3680: }}}}m68k_incpc(8);
3681: return 24;
3682: }
3683: unsigned long REGPARAM2 CPUFUNC(op_a7c_0)(uae_u32 opcode) /* EORSR */
3684: {
3685: OpcodeFamily = 6; CurrentInstrCycles = 20;
3686: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel234; }
3687: { MakeSR();
3688: { uae_s16 src = get_iword(2);
3689: regs.sr ^= src;
3690: MakeFromSR();
3691: }}}m68k_incpc(4);
3692: endlabel234: ;
3693: return 20;
3694: }
3695: #endif
3696:
3697: #ifdef PART_2
3698: unsigned long REGPARAM2 CPUFUNC(op_a80_0)(uae_u32 opcode) /* EOR */
3699: {
3700: uae_u32 dstreg = opcode & 7;
3701: OpcodeFamily = 3; CurrentInstrCycles = 16;
3702: {{ uae_s32 src = get_ilong(2);
3703: { uae_s32 dst = m68k_dreg(regs, dstreg);
3704: src ^= dst;
3705: CLEAR_CZNV;
3706: SET_ZFLG (((uae_s32)(src)) == 0);
3707: SET_NFLG (((uae_s32)(src)) < 0);
3708: m68k_dreg(regs, dstreg) = (src);
3709: }}}m68k_incpc(6);
3710: return 16;
3711: }
3712: unsigned long REGPARAM2 CPUFUNC(op_a90_0)(uae_u32 opcode) /* EOR */
3713: {
3714: uae_u32 dstreg = opcode & 7;
3715: OpcodeFamily = 3; CurrentInstrCycles = 28;
3716: {{ uae_s32 src = get_ilong(2);
3717: { uaecptr dsta = m68k_areg(regs, dstreg);
3718: { uae_s32 dst = get_long(dsta);
3719: src ^= dst;
3720: CLEAR_CZNV;
3721: SET_ZFLG (((uae_s32)(src)) == 0);
3722: SET_NFLG (((uae_s32)(src)) < 0);
3723: put_long(dsta,src);
3724: }}}}m68k_incpc(6);
3725: return 28;
3726: }
3727: unsigned long REGPARAM2 CPUFUNC(op_a98_0)(uae_u32 opcode) /* EOR */
3728: {
3729: uae_u32 dstreg = opcode & 7;
3730: OpcodeFamily = 3; CurrentInstrCycles = 28;
3731: {{ uae_s32 src = get_ilong(2);
3732: { uaecptr dsta = m68k_areg(regs, dstreg);
3733: { uae_s32 dst = get_long(dsta);
3734: m68k_areg(regs, dstreg) += 4;
3735: src ^= dst;
3736: CLEAR_CZNV;
3737: SET_ZFLG (((uae_s32)(src)) == 0);
3738: SET_NFLG (((uae_s32)(src)) < 0);
3739: put_long(dsta,src);
3740: }}}}m68k_incpc(6);
3741: return 28;
3742: }
3743: unsigned long REGPARAM2 CPUFUNC(op_aa0_0)(uae_u32 opcode) /* EOR */
3744: {
3745: uae_u32 dstreg = opcode & 7;
3746: OpcodeFamily = 3; CurrentInstrCycles = 30;
3747: {{ uae_s32 src = get_ilong(2);
3748: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
3749: { uae_s32 dst = get_long(dsta);
3750: m68k_areg (regs, dstreg) = dsta;
3751: src ^= dst;
3752: CLEAR_CZNV;
3753: SET_ZFLG (((uae_s32)(src)) == 0);
3754: SET_NFLG (((uae_s32)(src)) < 0);
3755: put_long(dsta,src);
3756: }}}}m68k_incpc(6);
3757: return 30;
3758: }
3759: unsigned long REGPARAM2 CPUFUNC(op_aa8_0)(uae_u32 opcode) /* EOR */
3760: {
3761: uae_u32 dstreg = opcode & 7;
3762: OpcodeFamily = 3; CurrentInstrCycles = 32;
3763: {{ uae_s32 src = get_ilong(2);
3764: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
3765: { uae_s32 dst = get_long(dsta);
3766: src ^= dst;
3767: CLEAR_CZNV;
3768: SET_ZFLG (((uae_s32)(src)) == 0);
3769: SET_NFLG (((uae_s32)(src)) < 0);
3770: put_long(dsta,src);
3771: }}}}m68k_incpc(8);
3772: return 32;
3773: }
3774: unsigned long REGPARAM2 CPUFUNC(op_ab0_0)(uae_u32 opcode) /* EOR */
3775: {
3776: uae_u32 dstreg = opcode & 7;
3777: OpcodeFamily = 3; CurrentInstrCycles = 34;
3778: {{ uae_s32 src = get_ilong(2);
3779: {m68k_incpc(6);
3780: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
3781: BusCyclePenalty += 2;
3782: { uae_s32 dst = get_long(dsta);
3783: src ^= dst;
3784: CLEAR_CZNV;
3785: SET_ZFLG (((uae_s32)(src)) == 0);
3786: SET_NFLG (((uae_s32)(src)) < 0);
3787: put_long(dsta,src);
3788: }}}}}return 34;
3789: }
3790: unsigned long REGPARAM2 CPUFUNC(op_ab8_0)(uae_u32 opcode) /* EOR */
3791: {
3792: OpcodeFamily = 3; CurrentInstrCycles = 32;
3793: {{ uae_s32 src = get_ilong(2);
3794: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
3795: { uae_s32 dst = get_long(dsta);
3796: src ^= dst;
3797: CLEAR_CZNV;
3798: SET_ZFLG (((uae_s32)(src)) == 0);
3799: SET_NFLG (((uae_s32)(src)) < 0);
3800: put_long(dsta,src);
3801: }}}}m68k_incpc(8);
3802: return 32;
3803: }
3804: unsigned long REGPARAM2 CPUFUNC(op_ab9_0)(uae_u32 opcode) /* EOR */
3805: {
3806: OpcodeFamily = 3; CurrentInstrCycles = 36;
3807: {{ uae_s32 src = get_ilong(2);
3808: { uaecptr dsta = get_ilong(6);
3809: { uae_s32 dst = get_long(dsta);
3810: src ^= dst;
3811: CLEAR_CZNV;
3812: SET_ZFLG (((uae_s32)(src)) == 0);
3813: SET_NFLG (((uae_s32)(src)) < 0);
3814: put_long(dsta,src);
3815: }}}}m68k_incpc(10);
3816: return 36;
3817: }
3818: unsigned long REGPARAM2 CPUFUNC(op_ad0_0)(uae_u32 opcode) /* CAS */
3819: {
3820: uae_u32 dstreg = opcode & 7;
3821: OpcodeFamily = 84; CurrentInstrCycles = 16;
3822: {{ uae_s16 src = get_iword(2);
3823: { uaecptr dsta = m68k_areg(regs, dstreg);
3824: { uae_s8 dst = get_byte(dsta);
3825: { int ru = (src >> 6) & 7;
3826: int rc = src & 7;
3827: {uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(m68k_dreg(regs, rc)));
3828: { int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
3829: int flgo = ((uae_s8)(dst)) < 0;
3830: int flgn = ((uae_s8)(newv)) < 0;
3831: SET_ZFLG (((uae_s8)(newv)) == 0);
3832: SET_VFLG ((flgs != flgo) && (flgn != flgo));
3833: SET_CFLG (((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
3834: SET_NFLG (flgn != 0);
3835: if (GET_ZFLG){ put_byte(dsta,(m68k_dreg(regs, ru)));
3836: }else{m68k_dreg(regs, rc) = dst;
3837: }}}}}}}}m68k_incpc(4);
3838: return 16;
3839: }
3840: unsigned long REGPARAM2 CPUFUNC(op_ad8_0)(uae_u32 opcode) /* CAS */
3841: {
3842: uae_u32 dstreg = opcode & 7;
3843: OpcodeFamily = 84; CurrentInstrCycles = 16;
3844: {{ uae_s16 src = get_iword(2);
3845: { uaecptr dsta = m68k_areg(regs, dstreg);
3846: { uae_s8 dst = get_byte(dsta);
3847: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
3848: { int ru = (src >> 6) & 7;
3849: int rc = src & 7;
3850: {uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(m68k_dreg(regs, rc)));
3851: { int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
3852: int flgo = ((uae_s8)(dst)) < 0;
3853: int flgn = ((uae_s8)(newv)) < 0;
3854: SET_ZFLG (((uae_s8)(newv)) == 0);
3855: SET_VFLG ((flgs != flgo) && (flgn != flgo));
3856: SET_CFLG (((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
3857: SET_NFLG (flgn != 0);
3858: if (GET_ZFLG){ put_byte(dsta,(m68k_dreg(regs, ru)));
3859: }else{m68k_dreg(regs, rc) = dst;
3860: }}}}}}}}m68k_incpc(4);
3861: return 16;
3862: }
3863: unsigned long REGPARAM2 CPUFUNC(op_ae0_0)(uae_u32 opcode) /* CAS */
3864: {
3865: uae_u32 dstreg = opcode & 7;
3866: OpcodeFamily = 84; CurrentInstrCycles = 18;
3867: {{ uae_s16 src = get_iword(2);
3868: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
3869: { uae_s8 dst = get_byte(dsta);
3870: m68k_areg (regs, dstreg) = dsta;
3871: { int ru = (src >> 6) & 7;
3872: int rc = src & 7;
3873: {uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(m68k_dreg(regs, rc)));
3874: { int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
3875: int flgo = ((uae_s8)(dst)) < 0;
3876: int flgn = ((uae_s8)(newv)) < 0;
3877: SET_ZFLG (((uae_s8)(newv)) == 0);
3878: SET_VFLG ((flgs != flgo) && (flgn != flgo));
3879: SET_CFLG (((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
3880: SET_NFLG (flgn != 0);
3881: if (GET_ZFLG){ put_byte(dsta,(m68k_dreg(regs, ru)));
3882: }else{m68k_dreg(regs, rc) = dst;
3883: }}}}}}}}m68k_incpc(4);
3884: return 18;
3885: }
3886: unsigned long REGPARAM2 CPUFUNC(op_ae8_0)(uae_u32 opcode) /* CAS */
3887: {
3888: uae_u32 dstreg = opcode & 7;
3889: OpcodeFamily = 84; CurrentInstrCycles = 20;
3890: {{ uae_s16 src = get_iword(2);
3891: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
3892: { uae_s8 dst = get_byte(dsta);
3893: { int ru = (src >> 6) & 7;
3894: int rc = src & 7;
3895: {uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(m68k_dreg(regs, rc)));
3896: { int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
3897: int flgo = ((uae_s8)(dst)) < 0;
3898: int flgn = ((uae_s8)(newv)) < 0;
3899: SET_ZFLG (((uae_s8)(newv)) == 0);
3900: SET_VFLG ((flgs != flgo) && (flgn != flgo));
3901: SET_CFLG (((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
3902: SET_NFLG (flgn != 0);
3903: if (GET_ZFLG){ put_byte(dsta,(m68k_dreg(regs, ru)));
3904: }else{m68k_dreg(regs, rc) = dst;
3905: }}}}}}}}m68k_incpc(6);
3906: return 20;
3907: }
3908: unsigned long REGPARAM2 CPUFUNC(op_af0_0)(uae_u32 opcode) /* CAS */
3909: {
3910: uae_u32 dstreg = opcode & 7;
3911: OpcodeFamily = 84; CurrentInstrCycles = 22;
3912: {{ uae_s16 src = get_iword(2);
3913: {m68k_incpc(4);
3914: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
3915: BusCyclePenalty += 2;
3916: { uae_s8 dst = get_byte(dsta);
3917: { int ru = (src >> 6) & 7;
3918: int rc = src & 7;
3919: {uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(m68k_dreg(regs, rc)));
3920: { int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
3921: int flgo = ((uae_s8)(dst)) < 0;
3922: int flgn = ((uae_s8)(newv)) < 0;
3923: SET_ZFLG (((uae_s8)(newv)) == 0);
3924: SET_VFLG ((flgs != flgo) && (flgn != flgo));
3925: SET_CFLG (((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
3926: SET_NFLG (flgn != 0);
3927: if (GET_ZFLG){ put_byte(dsta,(m68k_dreg(regs, ru)));
3928: }else{m68k_dreg(regs, rc) = dst;
3929: }}}}}}}}}return 22;
3930: }
3931: unsigned long REGPARAM2 CPUFUNC(op_af8_0)(uae_u32 opcode) /* CAS */
3932: {
3933: OpcodeFamily = 84; CurrentInstrCycles = 20;
3934: {{ uae_s16 src = get_iword(2);
3935: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
3936: { uae_s8 dst = get_byte(dsta);
3937: { int ru = (src >> 6) & 7;
3938: int rc = src & 7;
3939: {uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(m68k_dreg(regs, rc)));
3940: { int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
3941: int flgo = ((uae_s8)(dst)) < 0;
3942: int flgn = ((uae_s8)(newv)) < 0;
3943: SET_ZFLG (((uae_s8)(newv)) == 0);
3944: SET_VFLG ((flgs != flgo) && (flgn != flgo));
3945: SET_CFLG (((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
3946: SET_NFLG (flgn != 0);
3947: if (GET_ZFLG){ put_byte(dsta,(m68k_dreg(regs, ru)));
3948: }else{m68k_dreg(regs, rc) = dst;
3949: }}}}}}}}m68k_incpc(6);
3950: return 20;
3951: }
3952: unsigned long REGPARAM2 CPUFUNC(op_af9_0)(uae_u32 opcode) /* CAS */
3953: {
3954: OpcodeFamily = 84; CurrentInstrCycles = 24;
3955: {{ uae_s16 src = get_iword(2);
3956: { uaecptr dsta = get_ilong(4);
3957: { uae_s8 dst = get_byte(dsta);
3958: { int ru = (src >> 6) & 7;
3959: int rc = src & 7;
3960: {uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(m68k_dreg(regs, rc)));
3961: { int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
3962: int flgo = ((uae_s8)(dst)) < 0;
3963: int flgn = ((uae_s8)(newv)) < 0;
3964: SET_ZFLG (((uae_s8)(newv)) == 0);
3965: SET_VFLG ((flgs != flgo) && (flgn != flgo));
3966: SET_CFLG (((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
3967: SET_NFLG (flgn != 0);
3968: if (GET_ZFLG){ put_byte(dsta,(m68k_dreg(regs, ru)));
3969: }else{m68k_dreg(regs, rc) = dst;
3970: }}}}}}}}m68k_incpc(8);
3971: return 24;
3972: }
3973: unsigned long REGPARAM2 CPUFUNC(op_c00_0)(uae_u32 opcode) /* CMP */
3974: {
3975: uae_u32 dstreg = opcode & 7;
3976: OpcodeFamily = 25; CurrentInstrCycles = 8;
3977: {{ uae_s8 src = get_ibyte(2);
3978: { uae_s8 dst = m68k_dreg(regs, dstreg);
3979: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
3980: { int flgs = ((uae_s8)(src)) < 0;
3981: int flgo = ((uae_s8)(dst)) < 0;
3982: int flgn = ((uae_s8)(newv)) < 0;
3983: SET_ZFLG (((uae_s8)(newv)) == 0);
3984: SET_VFLG ((flgs != flgo) && (flgn != flgo));
3985: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
3986: SET_NFLG (flgn != 0);
3987: }}}}}}m68k_incpc(4);
3988: return 8;
3989: }
3990: unsigned long REGPARAM2 CPUFUNC(op_c10_0)(uae_u32 opcode) /* CMP */
3991: {
3992: uae_u32 dstreg = opcode & 7;
3993: OpcodeFamily = 25; CurrentInstrCycles = 12;
3994: {{ uae_s8 src = get_ibyte(2);
3995: { uaecptr dsta = m68k_areg(regs, dstreg);
3996: { uae_s8 dst = get_byte(dsta);
3997: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
3998: { int flgs = ((uae_s8)(src)) < 0;
3999: int flgo = ((uae_s8)(dst)) < 0;
4000: int flgn = ((uae_s8)(newv)) < 0;
4001: SET_ZFLG (((uae_s8)(newv)) == 0);
4002: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4003: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
4004: SET_NFLG (flgn != 0);
4005: }}}}}}}m68k_incpc(4);
4006: return 12;
4007: }
4008: unsigned long REGPARAM2 CPUFUNC(op_c18_0)(uae_u32 opcode) /* CMP */
4009: {
4010: uae_u32 dstreg = opcode & 7;
4011: OpcodeFamily = 25; CurrentInstrCycles = 12;
4012: {{ uae_s8 src = get_ibyte(2);
4013: { uaecptr dsta = m68k_areg(regs, dstreg);
4014: { uae_s8 dst = get_byte(dsta);
4015: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
4016: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
4017: { int flgs = ((uae_s8)(src)) < 0;
4018: int flgo = ((uae_s8)(dst)) < 0;
4019: int flgn = ((uae_s8)(newv)) < 0;
4020: SET_ZFLG (((uae_s8)(newv)) == 0);
4021: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4022: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
4023: SET_NFLG (flgn != 0);
4024: }}}}}}}m68k_incpc(4);
4025: return 12;
4026: }
4027: unsigned long REGPARAM2 CPUFUNC(op_c20_0)(uae_u32 opcode) /* CMP */
4028: {
4029: uae_u32 dstreg = opcode & 7;
4030: OpcodeFamily = 25; CurrentInstrCycles = 14;
4031: {{ uae_s8 src = get_ibyte(2);
4032: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
4033: { uae_s8 dst = get_byte(dsta);
4034: m68k_areg (regs, dstreg) = dsta;
4035: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
4036: { int flgs = ((uae_s8)(src)) < 0;
4037: int flgo = ((uae_s8)(dst)) < 0;
4038: int flgn = ((uae_s8)(newv)) < 0;
4039: SET_ZFLG (((uae_s8)(newv)) == 0);
4040: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4041: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
4042: SET_NFLG (flgn != 0);
4043: }}}}}}}m68k_incpc(4);
4044: return 14;
4045: }
4046: unsigned long REGPARAM2 CPUFUNC(op_c28_0)(uae_u32 opcode) /* CMP */
4047: {
4048: uae_u32 dstreg = opcode & 7;
4049: OpcodeFamily = 25; CurrentInstrCycles = 16;
4050: {{ uae_s8 src = get_ibyte(2);
4051: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
4052: { uae_s8 dst = get_byte(dsta);
4053: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
4054: { int flgs = ((uae_s8)(src)) < 0;
4055: int flgo = ((uae_s8)(dst)) < 0;
4056: int flgn = ((uae_s8)(newv)) < 0;
4057: SET_ZFLG (((uae_s8)(newv)) == 0);
4058: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4059: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
4060: SET_NFLG (flgn != 0);
4061: }}}}}}}m68k_incpc(6);
4062: return 16;
4063: }
4064: unsigned long REGPARAM2 CPUFUNC(op_c30_0)(uae_u32 opcode) /* CMP */
4065: {
4066: uae_u32 dstreg = opcode & 7;
4067: OpcodeFamily = 25; CurrentInstrCycles = 18;
4068: {{ uae_s8 src = get_ibyte(2);
4069: {m68k_incpc(4);
4070: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
4071: BusCyclePenalty += 2;
4072: { uae_s8 dst = get_byte(dsta);
4073: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
4074: { int flgs = ((uae_s8)(src)) < 0;
4075: int flgo = ((uae_s8)(dst)) < 0;
4076: int flgn = ((uae_s8)(newv)) < 0;
4077: SET_ZFLG (((uae_s8)(newv)) == 0);
4078: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4079: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
4080: SET_NFLG (flgn != 0);
4081: }}}}}}}}return 18;
4082: }
4083: unsigned long REGPARAM2 CPUFUNC(op_c38_0)(uae_u32 opcode) /* CMP */
4084: {
4085: OpcodeFamily = 25; CurrentInstrCycles = 16;
4086: {{ uae_s8 src = get_ibyte(2);
4087: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
4088: { uae_s8 dst = get_byte(dsta);
4089: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
4090: { int flgs = ((uae_s8)(src)) < 0;
4091: int flgo = ((uae_s8)(dst)) < 0;
4092: int flgn = ((uae_s8)(newv)) < 0;
4093: SET_ZFLG (((uae_s8)(newv)) == 0);
4094: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4095: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
4096: SET_NFLG (flgn != 0);
4097: }}}}}}}m68k_incpc(6);
4098: return 16;
4099: }
4100: unsigned long REGPARAM2 CPUFUNC(op_c39_0)(uae_u32 opcode) /* CMP */
4101: {
4102: OpcodeFamily = 25; CurrentInstrCycles = 20;
4103: {{ uae_s8 src = get_ibyte(2);
4104: { uaecptr dsta = get_ilong(4);
4105: { uae_s8 dst = get_byte(dsta);
4106: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
4107: { int flgs = ((uae_s8)(src)) < 0;
4108: int flgo = ((uae_s8)(dst)) < 0;
4109: int flgn = ((uae_s8)(newv)) < 0;
4110: SET_ZFLG (((uae_s8)(newv)) == 0);
4111: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4112: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
4113: SET_NFLG (flgn != 0);
4114: }}}}}}}m68k_incpc(8);
4115: return 20;
4116: }
4117: unsigned long REGPARAM2 CPUFUNC(op_c3a_0)(uae_u32 opcode) /* CMP */
4118: {
4119: uae_u32 dstreg = 2;
4120: OpcodeFamily = 25; CurrentInstrCycles = 16;
4121: {{ uae_s8 src = get_ibyte(2);
4122: { uaecptr dsta = m68k_getpc () + 4;
4123: dsta += (uae_s32)(uae_s16)get_iword(4);
4124: { uae_s8 dst = get_byte(dsta);
4125: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
4126: { int flgs = ((uae_s8)(src)) < 0;
4127: int flgo = ((uae_s8)(dst)) < 0;
4128: int flgn = ((uae_s8)(newv)) < 0;
4129: SET_ZFLG (((uae_s8)(newv)) == 0);
4130: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4131: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
4132: SET_NFLG (flgn != 0);
4133: }}}}}}}m68k_incpc(6);
4134: return 16;
4135: }
4136: unsigned long REGPARAM2 CPUFUNC(op_c3b_0)(uae_u32 opcode) /* CMP */
4137: {
4138: uae_u32 dstreg = 3;
4139: OpcodeFamily = 25; CurrentInstrCycles = 18;
4140: {{ uae_s8 src = get_ibyte(2);
4141: {m68k_incpc(4);
4142: { uaecptr tmppc = m68k_getpc();
4143: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
4144: BusCyclePenalty += 2;
4145: { uae_s8 dst = get_byte(dsta);
4146: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
4147: { int flgs = ((uae_s8)(src)) < 0;
4148: int flgo = ((uae_s8)(dst)) < 0;
4149: int flgn = ((uae_s8)(newv)) < 0;
4150: SET_ZFLG (((uae_s8)(newv)) == 0);
4151: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4152: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
4153: SET_NFLG (flgn != 0);
4154: }}}}}}}}return 18;
4155: }
4156: unsigned long REGPARAM2 CPUFUNC(op_c40_0)(uae_u32 opcode) /* CMP */
4157: {
4158: uae_u32 dstreg = opcode & 7;
4159: OpcodeFamily = 25; CurrentInstrCycles = 8;
4160: {{ uae_s16 src = get_iword(2);
4161: { uae_s16 dst = m68k_dreg(regs, dstreg);
4162: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4163: { int flgs = ((uae_s16)(src)) < 0;
4164: int flgo = ((uae_s16)(dst)) < 0;
4165: int flgn = ((uae_s16)(newv)) < 0;
4166: SET_ZFLG (((uae_s16)(newv)) == 0);
4167: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4168: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4169: SET_NFLG (flgn != 0);
4170: }}}}}}m68k_incpc(4);
4171: return 8;
4172: }
4173: unsigned long REGPARAM2 CPUFUNC(op_c50_0)(uae_u32 opcode) /* CMP */
4174: {
4175: uae_u32 dstreg = opcode & 7;
4176: OpcodeFamily = 25; CurrentInstrCycles = 12;
4177: {{ uae_s16 src = get_iword(2);
4178: { uaecptr dsta = m68k_areg(regs, dstreg);
4179: { uae_s16 dst = get_word(dsta);
4180: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4181: { int flgs = ((uae_s16)(src)) < 0;
4182: int flgo = ((uae_s16)(dst)) < 0;
4183: int flgn = ((uae_s16)(newv)) < 0;
4184: SET_ZFLG (((uae_s16)(newv)) == 0);
4185: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4186: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4187: SET_NFLG (flgn != 0);
4188: }}}}}}}m68k_incpc(4);
4189: return 12;
4190: }
4191: unsigned long REGPARAM2 CPUFUNC(op_c58_0)(uae_u32 opcode) /* CMP */
4192: {
4193: uae_u32 dstreg = opcode & 7;
4194: OpcodeFamily = 25; CurrentInstrCycles = 12;
4195: {{ uae_s16 src = get_iword(2);
4196: { uaecptr dsta = m68k_areg(regs, dstreg);
4197: { uae_s16 dst = get_word(dsta);
4198: m68k_areg(regs, dstreg) += 2;
4199: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4200: { int flgs = ((uae_s16)(src)) < 0;
4201: int flgo = ((uae_s16)(dst)) < 0;
4202: int flgn = ((uae_s16)(newv)) < 0;
4203: SET_ZFLG (((uae_s16)(newv)) == 0);
4204: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4205: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4206: SET_NFLG (flgn != 0);
4207: }}}}}}}m68k_incpc(4);
4208: return 12;
4209: }
4210: unsigned long REGPARAM2 CPUFUNC(op_c60_0)(uae_u32 opcode) /* CMP */
4211: {
4212: uae_u32 dstreg = opcode & 7;
4213: OpcodeFamily = 25; CurrentInstrCycles = 14;
4214: {{ uae_s16 src = get_iword(2);
4215: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
4216: { uae_s16 dst = get_word(dsta);
4217: m68k_areg (regs, dstreg) = dsta;
4218: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4219: { int flgs = ((uae_s16)(src)) < 0;
4220: int flgo = ((uae_s16)(dst)) < 0;
4221: int flgn = ((uae_s16)(newv)) < 0;
4222: SET_ZFLG (((uae_s16)(newv)) == 0);
4223: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4224: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4225: SET_NFLG (flgn != 0);
4226: }}}}}}}m68k_incpc(4);
4227: return 14;
4228: }
4229: unsigned long REGPARAM2 CPUFUNC(op_c68_0)(uae_u32 opcode) /* CMP */
4230: {
4231: uae_u32 dstreg = opcode & 7;
4232: OpcodeFamily = 25; CurrentInstrCycles = 16;
4233: {{ uae_s16 src = get_iword(2);
4234: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
4235: { uae_s16 dst = get_word(dsta);
4236: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4237: { int flgs = ((uae_s16)(src)) < 0;
4238: int flgo = ((uae_s16)(dst)) < 0;
4239: int flgn = ((uae_s16)(newv)) < 0;
4240: SET_ZFLG (((uae_s16)(newv)) == 0);
4241: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4242: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4243: SET_NFLG (flgn != 0);
4244: }}}}}}}m68k_incpc(6);
4245: return 16;
4246: }
4247: unsigned long REGPARAM2 CPUFUNC(op_c70_0)(uae_u32 opcode) /* CMP */
4248: {
4249: uae_u32 dstreg = opcode & 7;
4250: OpcodeFamily = 25; CurrentInstrCycles = 18;
4251: {{ uae_s16 src = get_iword(2);
4252: {m68k_incpc(4);
4253: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
4254: BusCyclePenalty += 2;
4255: { uae_s16 dst = get_word(dsta);
4256: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4257: { int flgs = ((uae_s16)(src)) < 0;
4258: int flgo = ((uae_s16)(dst)) < 0;
4259: int flgn = ((uae_s16)(newv)) < 0;
4260: SET_ZFLG (((uae_s16)(newv)) == 0);
4261: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4262: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4263: SET_NFLG (flgn != 0);
4264: }}}}}}}}return 18;
4265: }
4266: unsigned long REGPARAM2 CPUFUNC(op_c78_0)(uae_u32 opcode) /* CMP */
4267: {
4268: OpcodeFamily = 25; CurrentInstrCycles = 16;
4269: {{ uae_s16 src = get_iword(2);
4270: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
4271: { uae_s16 dst = get_word(dsta);
4272: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4273: { int flgs = ((uae_s16)(src)) < 0;
4274: int flgo = ((uae_s16)(dst)) < 0;
4275: int flgn = ((uae_s16)(newv)) < 0;
4276: SET_ZFLG (((uae_s16)(newv)) == 0);
4277: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4278: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4279: SET_NFLG (flgn != 0);
4280: }}}}}}}m68k_incpc(6);
4281: return 16;
4282: }
4283: unsigned long REGPARAM2 CPUFUNC(op_c79_0)(uae_u32 opcode) /* CMP */
4284: {
4285: OpcodeFamily = 25; CurrentInstrCycles = 20;
4286: {{ uae_s16 src = get_iword(2);
4287: { uaecptr dsta = get_ilong(4);
4288: { uae_s16 dst = get_word(dsta);
4289: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4290: { int flgs = ((uae_s16)(src)) < 0;
4291: int flgo = ((uae_s16)(dst)) < 0;
4292: int flgn = ((uae_s16)(newv)) < 0;
4293: SET_ZFLG (((uae_s16)(newv)) == 0);
4294: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4295: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4296: SET_NFLG (flgn != 0);
4297: }}}}}}}m68k_incpc(8);
4298: return 20;
4299: }
4300: unsigned long REGPARAM2 CPUFUNC(op_c7a_0)(uae_u32 opcode) /* CMP */
4301: {
4302: uae_u32 dstreg = 2;
4303: OpcodeFamily = 25; CurrentInstrCycles = 16;
4304: {{ uae_s16 src = get_iword(2);
4305: { uaecptr dsta = m68k_getpc () + 4;
4306: dsta += (uae_s32)(uae_s16)get_iword(4);
4307: { uae_s16 dst = get_word(dsta);
4308: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4309: { int flgs = ((uae_s16)(src)) < 0;
4310: int flgo = ((uae_s16)(dst)) < 0;
4311: int flgn = ((uae_s16)(newv)) < 0;
4312: SET_ZFLG (((uae_s16)(newv)) == 0);
4313: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4314: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4315: SET_NFLG (flgn != 0);
4316: }}}}}}}m68k_incpc(6);
4317: return 16;
4318: }
4319: unsigned long REGPARAM2 CPUFUNC(op_c7b_0)(uae_u32 opcode) /* CMP */
4320: {
4321: uae_u32 dstreg = 3;
4322: OpcodeFamily = 25; CurrentInstrCycles = 18;
4323: {{ uae_s16 src = get_iword(2);
4324: {m68k_incpc(4);
4325: { uaecptr tmppc = m68k_getpc();
4326: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
4327: BusCyclePenalty += 2;
4328: { uae_s16 dst = get_word(dsta);
4329: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
4330: { int flgs = ((uae_s16)(src)) < 0;
4331: int flgo = ((uae_s16)(dst)) < 0;
4332: int flgn = ((uae_s16)(newv)) < 0;
4333: SET_ZFLG (((uae_s16)(newv)) == 0);
4334: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4335: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
4336: SET_NFLG (flgn != 0);
4337: }}}}}}}}return 18;
4338: }
4339: unsigned long REGPARAM2 CPUFUNC(op_c80_0)(uae_u32 opcode) /* CMP */
4340: {
4341: uae_u32 dstreg = opcode & 7;
4342: OpcodeFamily = 25; CurrentInstrCycles = 14;
4343: {{ uae_s32 src = get_ilong(2);
4344: { uae_s32 dst = m68k_dreg(regs, dstreg);
4345: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4346: { int flgs = ((uae_s32)(src)) < 0;
4347: int flgo = ((uae_s32)(dst)) < 0;
4348: int flgn = ((uae_s32)(newv)) < 0;
4349: SET_ZFLG (((uae_s32)(newv)) == 0);
4350: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4351: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4352: SET_NFLG (flgn != 0);
4353: }}}}}}m68k_incpc(6);
4354: return 14;
4355: }
4356: unsigned long REGPARAM2 CPUFUNC(op_c90_0)(uae_u32 opcode) /* CMP */
4357: {
4358: uae_u32 dstreg = opcode & 7;
4359: OpcodeFamily = 25; CurrentInstrCycles = 20;
4360: {{ uae_s32 src = get_ilong(2);
4361: { uaecptr dsta = m68k_areg(regs, dstreg);
4362: { uae_s32 dst = get_long(dsta);
4363: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4364: { int flgs = ((uae_s32)(src)) < 0;
4365: int flgo = ((uae_s32)(dst)) < 0;
4366: int flgn = ((uae_s32)(newv)) < 0;
4367: SET_ZFLG (((uae_s32)(newv)) == 0);
4368: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4369: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4370: SET_NFLG (flgn != 0);
4371: }}}}}}}m68k_incpc(6);
4372: return 20;
4373: }
4374: unsigned long REGPARAM2 CPUFUNC(op_c98_0)(uae_u32 opcode) /* CMP */
4375: {
4376: uae_u32 dstreg = opcode & 7;
4377: OpcodeFamily = 25; CurrentInstrCycles = 20;
4378: {{ uae_s32 src = get_ilong(2);
4379: { uaecptr dsta = m68k_areg(regs, dstreg);
4380: { uae_s32 dst = get_long(dsta);
4381: m68k_areg(regs, dstreg) += 4;
4382: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4383: { int flgs = ((uae_s32)(src)) < 0;
4384: int flgo = ((uae_s32)(dst)) < 0;
4385: int flgn = ((uae_s32)(newv)) < 0;
4386: SET_ZFLG (((uae_s32)(newv)) == 0);
4387: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4388: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4389: SET_NFLG (flgn != 0);
4390: }}}}}}}m68k_incpc(6);
4391: return 20;
4392: }
4393: unsigned long REGPARAM2 CPUFUNC(op_ca0_0)(uae_u32 opcode) /* CMP */
4394: {
4395: uae_u32 dstreg = opcode & 7;
4396: OpcodeFamily = 25; CurrentInstrCycles = 22;
4397: {{ uae_s32 src = get_ilong(2);
4398: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
4399: { uae_s32 dst = get_long(dsta);
4400: m68k_areg (regs, dstreg) = dsta;
4401: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4402: { int flgs = ((uae_s32)(src)) < 0;
4403: int flgo = ((uae_s32)(dst)) < 0;
4404: int flgn = ((uae_s32)(newv)) < 0;
4405: SET_ZFLG (((uae_s32)(newv)) == 0);
4406: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4407: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4408: SET_NFLG (flgn != 0);
4409: }}}}}}}m68k_incpc(6);
4410: return 22;
4411: }
4412: unsigned long REGPARAM2 CPUFUNC(op_ca8_0)(uae_u32 opcode) /* CMP */
4413: {
4414: uae_u32 dstreg = opcode & 7;
4415: OpcodeFamily = 25; CurrentInstrCycles = 24;
4416: {{ uae_s32 src = get_ilong(2);
4417: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
4418: { uae_s32 dst = get_long(dsta);
4419: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4420: { int flgs = ((uae_s32)(src)) < 0;
4421: int flgo = ((uae_s32)(dst)) < 0;
4422: int flgn = ((uae_s32)(newv)) < 0;
4423: SET_ZFLG (((uae_s32)(newv)) == 0);
4424: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4425: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4426: SET_NFLG (flgn != 0);
4427: }}}}}}}m68k_incpc(8);
4428: return 24;
4429: }
4430: unsigned long REGPARAM2 CPUFUNC(op_cb0_0)(uae_u32 opcode) /* CMP */
4431: {
4432: uae_u32 dstreg = opcode & 7;
4433: OpcodeFamily = 25; CurrentInstrCycles = 26;
4434: {{ uae_s32 src = get_ilong(2);
4435: {m68k_incpc(6);
4436: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
4437: BusCyclePenalty += 2;
4438: { uae_s32 dst = get_long(dsta);
4439: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4440: { int flgs = ((uae_s32)(src)) < 0;
4441: int flgo = ((uae_s32)(dst)) < 0;
4442: int flgn = ((uae_s32)(newv)) < 0;
4443: SET_ZFLG (((uae_s32)(newv)) == 0);
4444: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4445: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4446: SET_NFLG (flgn != 0);
4447: }}}}}}}}return 26;
4448: }
4449: unsigned long REGPARAM2 CPUFUNC(op_cb8_0)(uae_u32 opcode) /* CMP */
4450: {
4451: OpcodeFamily = 25; CurrentInstrCycles = 24;
4452: {{ uae_s32 src = get_ilong(2);
4453: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
4454: { uae_s32 dst = get_long(dsta);
4455: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4456: { int flgs = ((uae_s32)(src)) < 0;
4457: int flgo = ((uae_s32)(dst)) < 0;
4458: int flgn = ((uae_s32)(newv)) < 0;
4459: SET_ZFLG (((uae_s32)(newv)) == 0);
4460: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4461: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4462: SET_NFLG (flgn != 0);
4463: }}}}}}}m68k_incpc(8);
4464: return 24;
4465: }
4466: unsigned long REGPARAM2 CPUFUNC(op_cb9_0)(uae_u32 opcode) /* CMP */
4467: {
4468: OpcodeFamily = 25; CurrentInstrCycles = 28;
4469: {{ uae_s32 src = get_ilong(2);
4470: { uaecptr dsta = get_ilong(6);
4471: { uae_s32 dst = get_long(dsta);
4472: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4473: { int flgs = ((uae_s32)(src)) < 0;
4474: int flgo = ((uae_s32)(dst)) < 0;
4475: int flgn = ((uae_s32)(newv)) < 0;
4476: SET_ZFLG (((uae_s32)(newv)) == 0);
4477: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4478: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4479: SET_NFLG (flgn != 0);
4480: }}}}}}}m68k_incpc(10);
4481: return 28;
4482: }
4483: unsigned long REGPARAM2 CPUFUNC(op_cba_0)(uae_u32 opcode) /* CMP */
4484: {
4485: uae_u32 dstreg = 2;
4486: OpcodeFamily = 25; CurrentInstrCycles = 24;
4487: {{ uae_s32 src = get_ilong(2);
4488: { uaecptr dsta = m68k_getpc () + 6;
4489: dsta += (uae_s32)(uae_s16)get_iword(6);
4490: { uae_s32 dst = get_long(dsta);
4491: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4492: { int flgs = ((uae_s32)(src)) < 0;
4493: int flgo = ((uae_s32)(dst)) < 0;
4494: int flgn = ((uae_s32)(newv)) < 0;
4495: SET_ZFLG (((uae_s32)(newv)) == 0);
4496: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4497: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4498: SET_NFLG (flgn != 0);
4499: }}}}}}}m68k_incpc(8);
4500: return 24;
4501: }
4502: unsigned long REGPARAM2 CPUFUNC(op_cbb_0)(uae_u32 opcode) /* CMP */
4503: {
4504: uae_u32 dstreg = 3;
4505: OpcodeFamily = 25; CurrentInstrCycles = 26;
4506: {{ uae_s32 src = get_ilong(2);
4507: {m68k_incpc(6);
4508: { uaecptr tmppc = m68k_getpc();
4509: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
4510: BusCyclePenalty += 2;
4511: { uae_s32 dst = get_long(dsta);
4512: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
4513: { int flgs = ((uae_s32)(src)) < 0;
4514: int flgo = ((uae_s32)(dst)) < 0;
4515: int flgn = ((uae_s32)(newv)) < 0;
4516: SET_ZFLG (((uae_s32)(newv)) == 0);
4517: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4518: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
4519: SET_NFLG (flgn != 0);
4520: }}}}}}}}return 26;
4521: }
4522: unsigned long REGPARAM2 CPUFUNC(op_cd0_0)(uae_u32 opcode) /* CAS */
4523: {
4524: uae_u32 dstreg = opcode & 7;
4525: OpcodeFamily = 84; CurrentInstrCycles = 16;
4526: {{ uae_s16 src = get_iword(2);
4527: { uaecptr dsta = m68k_areg(regs, dstreg);
4528: { uae_s16 dst = get_word(dsta);
4529: { int ru = (src >> 6) & 7;
4530: int rc = src & 7;
4531: {uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(m68k_dreg(regs, rc)));
4532: { int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
4533: int flgo = ((uae_s16)(dst)) < 0;
4534: int flgn = ((uae_s16)(newv)) < 0;
4535: SET_ZFLG (((uae_s16)(newv)) == 0);
4536: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4537: SET_CFLG (((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
4538: SET_NFLG (flgn != 0);
4539: if (GET_ZFLG){ put_word(dsta,(m68k_dreg(regs, ru)));
4540: }else{m68k_dreg(regs, rc) = dst;
4541: }}}}}}}}m68k_incpc(4);
4542: return 16;
4543: }
4544: unsigned long REGPARAM2 CPUFUNC(op_cd8_0)(uae_u32 opcode) /* CAS */
4545: {
4546: uae_u32 dstreg = opcode & 7;
4547: OpcodeFamily = 84; CurrentInstrCycles = 16;
4548: {{ uae_s16 src = get_iword(2);
4549: { uaecptr dsta = m68k_areg(regs, dstreg);
4550: { uae_s16 dst = get_word(dsta);
4551: m68k_areg(regs, dstreg) += 2;
4552: { int ru = (src >> 6) & 7;
4553: int rc = src & 7;
4554: {uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(m68k_dreg(regs, rc)));
4555: { int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
4556: int flgo = ((uae_s16)(dst)) < 0;
4557: int flgn = ((uae_s16)(newv)) < 0;
4558: SET_ZFLG (((uae_s16)(newv)) == 0);
4559: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4560: SET_CFLG (((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
4561: SET_NFLG (flgn != 0);
4562: if (GET_ZFLG){ put_word(dsta,(m68k_dreg(regs, ru)));
4563: }else{m68k_dreg(regs, rc) = dst;
4564: }}}}}}}}m68k_incpc(4);
4565: return 16;
4566: }
4567: unsigned long REGPARAM2 CPUFUNC(op_ce0_0)(uae_u32 opcode) /* CAS */
4568: {
4569: uae_u32 dstreg = opcode & 7;
4570: OpcodeFamily = 84; CurrentInstrCycles = 18;
4571: {{ uae_s16 src = get_iword(2);
4572: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
4573: { uae_s16 dst = get_word(dsta);
4574: m68k_areg (regs, dstreg) = dsta;
4575: { int ru = (src >> 6) & 7;
4576: int rc = src & 7;
4577: {uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(m68k_dreg(regs, rc)));
4578: { int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
4579: int flgo = ((uae_s16)(dst)) < 0;
4580: int flgn = ((uae_s16)(newv)) < 0;
4581: SET_ZFLG (((uae_s16)(newv)) == 0);
4582: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4583: SET_CFLG (((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
4584: SET_NFLG (flgn != 0);
4585: if (GET_ZFLG){ put_word(dsta,(m68k_dreg(regs, ru)));
4586: }else{m68k_dreg(regs, rc) = dst;
4587: }}}}}}}}m68k_incpc(4);
4588: return 18;
4589: }
4590: unsigned long REGPARAM2 CPUFUNC(op_ce8_0)(uae_u32 opcode) /* CAS */
4591: {
4592: uae_u32 dstreg = opcode & 7;
4593: OpcodeFamily = 84; CurrentInstrCycles = 20;
4594: {{ uae_s16 src = get_iword(2);
4595: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
4596: { uae_s16 dst = get_word(dsta);
4597: { int ru = (src >> 6) & 7;
4598: int rc = src & 7;
4599: {uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(m68k_dreg(regs, rc)));
4600: { int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
4601: int flgo = ((uae_s16)(dst)) < 0;
4602: int flgn = ((uae_s16)(newv)) < 0;
4603: SET_ZFLG (((uae_s16)(newv)) == 0);
4604: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4605: SET_CFLG (((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
4606: SET_NFLG (flgn != 0);
4607: if (GET_ZFLG){ put_word(dsta,(m68k_dreg(regs, ru)));
4608: }else{m68k_dreg(regs, rc) = dst;
4609: }}}}}}}}m68k_incpc(6);
4610: return 20;
4611: }
4612: unsigned long REGPARAM2 CPUFUNC(op_cf0_0)(uae_u32 opcode) /* CAS */
4613: {
4614: uae_u32 dstreg = opcode & 7;
4615: OpcodeFamily = 84; CurrentInstrCycles = 22;
4616: {{ uae_s16 src = get_iword(2);
4617: {m68k_incpc(4);
4618: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
4619: BusCyclePenalty += 2;
4620: { uae_s16 dst = get_word(dsta);
4621: { int ru = (src >> 6) & 7;
4622: int rc = src & 7;
4623: {uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(m68k_dreg(regs, rc)));
4624: { int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
4625: int flgo = ((uae_s16)(dst)) < 0;
4626: int flgn = ((uae_s16)(newv)) < 0;
4627: SET_ZFLG (((uae_s16)(newv)) == 0);
4628: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4629: SET_CFLG (((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
4630: SET_NFLG (flgn != 0);
4631: if (GET_ZFLG){ put_word(dsta,(m68k_dreg(regs, ru)));
4632: }else{m68k_dreg(regs, rc) = dst;
4633: }}}}}}}}}return 22;
4634: }
4635: unsigned long REGPARAM2 CPUFUNC(op_cf8_0)(uae_u32 opcode) /* CAS */
4636: {
4637: OpcodeFamily = 84; CurrentInstrCycles = 20;
4638: {{ uae_s16 src = get_iword(2);
4639: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
4640: { uae_s16 dst = get_word(dsta);
4641: { int ru = (src >> 6) & 7;
4642: int rc = src & 7;
4643: {uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(m68k_dreg(regs, rc)));
4644: { int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
4645: int flgo = ((uae_s16)(dst)) < 0;
4646: int flgn = ((uae_s16)(newv)) < 0;
4647: SET_ZFLG (((uae_s16)(newv)) == 0);
4648: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4649: SET_CFLG (((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
4650: SET_NFLG (flgn != 0);
4651: if (GET_ZFLG){ put_word(dsta,(m68k_dreg(regs, ru)));
4652: }else{m68k_dreg(regs, rc) = dst;
4653: }}}}}}}}m68k_incpc(6);
4654: return 20;
4655: }
4656: unsigned long REGPARAM2 CPUFUNC(op_cf9_0)(uae_u32 opcode) /* CAS */
4657: {
4658: OpcodeFamily = 84; CurrentInstrCycles = 24;
4659: {{ uae_s16 src = get_iword(2);
4660: { uaecptr dsta = get_ilong(4);
4661: { uae_s16 dst = get_word(dsta);
4662: { int ru = (src >> 6) & 7;
4663: int rc = src & 7;
4664: {uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(m68k_dreg(regs, rc)));
4665: { int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
4666: int flgo = ((uae_s16)(dst)) < 0;
4667: int flgn = ((uae_s16)(newv)) < 0;
4668: SET_ZFLG (((uae_s16)(newv)) == 0);
4669: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4670: SET_CFLG (((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
4671: SET_NFLG (flgn != 0);
4672: if (GET_ZFLG){ put_word(dsta,(m68k_dreg(regs, ru)));
4673: }else{m68k_dreg(regs, rc) = dst;
4674: }}}}}}}}m68k_incpc(8);
4675: return 24;
4676: }
4677: unsigned long REGPARAM2 CPUFUNC(op_cfc_0)(uae_u32 opcode) /* CAS2 */
4678: {
4679: OpcodeFamily = 85; CurrentInstrCycles = 12;
4680: {{ uae_s32 extra = get_ilong(2);
4681: uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
4682: uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
4683: uae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);
4684: {uae_u32 newv = ((uae_s16)(dst1)) - ((uae_s16)(m68k_dreg(regs, (extra >> 16) & 7)));
4685: { int flgs = ((uae_s16)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
4686: int flgo = ((uae_s16)(dst1)) < 0;
4687: int flgn = ((uae_s16)(newv)) < 0;
4688: SET_ZFLG (((uae_s16)(newv)) == 0);
4689: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4690: SET_CFLG (((uae_u16)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
4691: SET_NFLG (flgn != 0);
4692: if (GET_ZFLG) {
4693: {uae_u32 newv = ((uae_s16)(dst2)) - ((uae_s16)(m68k_dreg(regs, extra & 7)));
4694: { int flgs = ((uae_s16)(m68k_dreg(regs, extra & 7))) < 0;
4695: int flgo = ((uae_s16)(dst2)) < 0;
4696: int flgn = ((uae_s16)(newv)) < 0;
4697: SET_ZFLG (((uae_s16)(newv)) == 0);
4698: SET_VFLG ((flgs != flgo) && (flgn != flgo));
4699: SET_CFLG (((uae_u16)(m68k_dreg(regs, extra & 7))) > ((uae_u16)(dst2)));
4700: SET_NFLG (flgn != 0);
4701: if (GET_ZFLG) {
4702: put_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));
4703: put_word(rn1, m68k_dreg(regs, (extra >> 6) & 7));
4704: }}
4705: }}}} if (! GET_ZFLG) {
4706: m68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
4707: m68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
4708: }
4709: }}m68k_incpc(6);
4710: return 12;
4711: }
4712: unsigned long REGPARAM2 CPUFUNC(op_e10_0)(uae_u32 opcode) /* MOVES */
4713: {
4714: uae_u32 dstreg = opcode & 7;
4715: OpcodeFamily = 103; CurrentInstrCycles = 16;
4716: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel288; }
4717: {{ uae_s16 extra = get_iword(2);
4718: if (extra & 0x800)
4719: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4720: { uaecptr dsta = m68k_areg(regs, dstreg);
4721: put_byte(dsta,src);
4722: }}else{{ uaecptr srca = m68k_areg(regs, dstreg);
4723: { uae_s8 src = get_byte(srca);
4724: if (extra & 0x8000) {
4725: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
4726: } else {
4727: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
4728: }
4729: }}}}}}m68k_incpc(4);
4730: endlabel288: ;
4731: return 16;
4732: }
4733: unsigned long REGPARAM2 CPUFUNC(op_e18_0)(uae_u32 opcode) /* MOVES */
4734: {
4735: uae_u32 dstreg = opcode & 7;
4736: OpcodeFamily = 103; CurrentInstrCycles = 16;
4737: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel289; }
4738: {{ uae_s16 extra = get_iword(2);
4739: if (extra & 0x800)
4740: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4741: { uaecptr dsta = m68k_areg(regs, dstreg);
4742: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
4743: put_byte(dsta,src);
4744: }}else{{ uaecptr srca = m68k_areg(regs, dstreg);
4745: { uae_s8 src = get_byte(srca);
4746: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
4747: if (extra & 0x8000) {
4748: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
4749: } else {
4750: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
4751: }
4752: }}}}}}m68k_incpc(4);
4753: endlabel289: ;
4754: return 16;
4755: }
4756: unsigned long REGPARAM2 CPUFUNC(op_e20_0)(uae_u32 opcode) /* MOVES */
4757: {
4758: uae_u32 dstreg = opcode & 7;
4759: OpcodeFamily = 103; CurrentInstrCycles = 20;
4760: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel290; }
4761: {{ uae_s16 extra = get_iword(2);
4762: if (extra & 0x800)
4763: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4764: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
4765: m68k_areg (regs, dstreg) = dsta;
4766: put_byte(dsta,src);
4767: }}else{{ uaecptr srca = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
4768: { uae_s8 src = get_byte(srca);
4769: m68k_areg (regs, dstreg) = srca;
4770: if (extra & 0x8000) {
4771: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
4772: } else {
4773: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
4774: }
4775: }}}}}}m68k_incpc(4);
4776: endlabel290: ;
4777: return 20;
4778: }
4779: unsigned long REGPARAM2 CPUFUNC(op_e28_0)(uae_u32 opcode) /* MOVES */
4780: {
4781: uae_u32 dstreg = opcode & 7;
4782: OpcodeFamily = 103; CurrentInstrCycles = 24;
4783: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel291; }
4784: {{ uae_s16 extra = get_iword(2);
4785: if (extra & 0x800)
4786: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4787: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
4788: put_byte(dsta,src);
4789: }}else{{ uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
4790: { uae_s8 src = get_byte(srca);
4791: if (extra & 0x8000) {
4792: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
4793: } else {
4794: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
4795: }
4796: }}}}}}m68k_incpc(8);
4797: endlabel291: ;
4798: return 24;
4799: }
4800: unsigned long REGPARAM2 CPUFUNC(op_e30_0)(uae_u32 opcode) /* MOVES */
4801: {
4802: uae_u32 dstreg = opcode & 7;
4803: OpcodeFamily = 103; CurrentInstrCycles = 28;
4804: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel292; }
4805: {{ uae_s16 extra = get_iword(2);
4806: if (extra & 0x800)
4807: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4808: {m68k_incpc(4);
4809: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
4810: BusCyclePenalty += 2;
4811: put_byte(dsta,src);
4812: }}}else{{{ uaecptr srca = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
4813: BusCyclePenalty += 2;
4814: { uae_s8 src = get_byte(srca);
4815: if (extra & 0x8000) {
4816: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
4817: } else {
4818: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
4819: }
4820: }}}}}}}endlabel292: ;
4821: return 28;
4822: }
4823: unsigned long REGPARAM2 CPUFUNC(op_e38_0)(uae_u32 opcode) /* MOVES */
4824: {
4825: OpcodeFamily = 103; CurrentInstrCycles = 24;
4826: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel293; }
4827: {{ uae_s16 extra = get_iword(2);
4828: if (extra & 0x800)
4829: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4830: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
4831: put_byte(dsta,src);
4832: }}else{{ uaecptr srca = (uae_s32)(uae_s16)get_iword(6);
4833: { uae_s8 src = get_byte(srca);
4834: if (extra & 0x8000) {
4835: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
4836: } else {
4837: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
4838: }
4839: }}}}}}m68k_incpc(8);
4840: endlabel293: ;
4841: return 24;
4842: }
4843: unsigned long REGPARAM2 CPUFUNC(op_e39_0)(uae_u32 opcode) /* MOVES */
4844: {
4845: OpcodeFamily = 103; CurrentInstrCycles = 32;
4846: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel294; }
4847: {{ uae_s16 extra = get_iword(2);
4848: if (extra & 0x800)
4849: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4850: { uaecptr dsta = get_ilong(4);
4851: put_byte(dsta,src);
4852: }}else{{ uaecptr srca = get_ilong(8);
4853: { uae_s8 src = get_byte(srca);
4854: if (extra & 0x8000) {
4855: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
4856: } else {
4857: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
4858: }
4859: }}}}}}m68k_incpc(12);
4860: endlabel294: ;
4861: return 32;
4862: }
4863: unsigned long REGPARAM2 CPUFUNC(op_e50_0)(uae_u32 opcode) /* MOVES */
4864: {
4865: uae_u32 dstreg = opcode & 7;
4866: OpcodeFamily = 103; CurrentInstrCycles = 16;
4867: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel295; }
4868: {{ uae_s16 extra = get_iword(2);
4869: if (extra & 0x800)
4870: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4871: { uaecptr dsta = m68k_areg(regs, dstreg);
4872: put_word(dsta,src);
4873: }}else{{ uaecptr srca = m68k_areg(regs, dstreg);
4874: { uae_s16 src = get_word(srca);
4875: if (extra & 0x8000) {
4876: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
4877: } else {
4878: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
4879: }
4880: }}}}}}m68k_incpc(4);
4881: endlabel295: ;
4882: return 16;
4883: }
4884: unsigned long REGPARAM2 CPUFUNC(op_e58_0)(uae_u32 opcode) /* MOVES */
4885: {
4886: uae_u32 dstreg = opcode & 7;
4887: OpcodeFamily = 103; CurrentInstrCycles = 16;
4888: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel296; }
4889: {{ uae_s16 extra = get_iword(2);
4890: if (extra & 0x800)
4891: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4892: { uaecptr dsta = m68k_areg(regs, dstreg);
4893: m68k_areg(regs, dstreg) += 2;
4894: put_word(dsta,src);
4895: }}else{{ uaecptr srca = m68k_areg(regs, dstreg);
4896: { uae_s16 src = get_word(srca);
4897: m68k_areg(regs, dstreg) += 2;
4898: if (extra & 0x8000) {
4899: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
4900: } else {
4901: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
4902: }
4903: }}}}}}m68k_incpc(4);
4904: endlabel296: ;
4905: return 16;
4906: }
4907: unsigned long REGPARAM2 CPUFUNC(op_e60_0)(uae_u32 opcode) /* MOVES */
4908: {
4909: uae_u32 dstreg = opcode & 7;
4910: OpcodeFamily = 103; CurrentInstrCycles = 20;
4911: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel297; }
4912: {{ uae_s16 extra = get_iword(2);
4913: if (extra & 0x800)
4914: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4915: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
4916: m68k_areg (regs, dstreg) = dsta;
4917: put_word(dsta,src);
4918: }}else{{ uaecptr srca = m68k_areg(regs, dstreg) - 2;
4919: { uae_s16 src = get_word(srca);
4920: m68k_areg (regs, dstreg) = srca;
4921: if (extra & 0x8000) {
4922: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
4923: } else {
4924: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
4925: }
4926: }}}}}}m68k_incpc(4);
4927: endlabel297: ;
4928: return 20;
4929: }
4930: unsigned long REGPARAM2 CPUFUNC(op_e68_0)(uae_u32 opcode) /* MOVES */
4931: {
4932: uae_u32 dstreg = opcode & 7;
4933: OpcodeFamily = 103; CurrentInstrCycles = 24;
4934: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel298; }
4935: {{ uae_s16 extra = get_iword(2);
4936: if (extra & 0x800)
4937: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4938: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
4939: put_word(dsta,src);
4940: }}else{{ uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
4941: { uae_s16 src = get_word(srca);
4942: if (extra & 0x8000) {
4943: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
4944: } else {
4945: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
4946: }
4947: }}}}}}m68k_incpc(8);
4948: endlabel298: ;
4949: return 24;
4950: }
4951: unsigned long REGPARAM2 CPUFUNC(op_e70_0)(uae_u32 opcode) /* MOVES */
4952: {
4953: uae_u32 dstreg = opcode & 7;
4954: OpcodeFamily = 103; CurrentInstrCycles = 28;
4955: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel299; }
4956: {{ uae_s16 extra = get_iword(2);
4957: if (extra & 0x800)
4958: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4959: {m68k_incpc(4);
4960: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
4961: BusCyclePenalty += 2;
4962: put_word(dsta,src);
4963: }}}else{{{ uaecptr srca = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
4964: BusCyclePenalty += 2;
4965: { uae_s16 src = get_word(srca);
4966: if (extra & 0x8000) {
4967: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
4968: } else {
4969: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
4970: }
4971: }}}}}}}endlabel299: ;
4972: return 28;
4973: }
4974: unsigned long REGPARAM2 CPUFUNC(op_e78_0)(uae_u32 opcode) /* MOVES */
4975: {
4976: OpcodeFamily = 103; CurrentInstrCycles = 24;
4977: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel300; }
4978: {{ uae_s16 extra = get_iword(2);
4979: if (extra & 0x800)
4980: { uae_u32 src = regs.regs[(extra >> 12) & 15];
4981: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
4982: put_word(dsta,src);
4983: }}else{{ uaecptr srca = (uae_s32)(uae_s16)get_iword(6);
4984: { uae_s16 src = get_word(srca);
4985: if (extra & 0x8000) {
4986: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
4987: } else {
4988: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
4989: }
4990: }}}}}}m68k_incpc(8);
4991: endlabel300: ;
4992: return 24;
4993: }
4994: unsigned long REGPARAM2 CPUFUNC(op_e79_0)(uae_u32 opcode) /* MOVES */
4995: {
4996: OpcodeFamily = 103; CurrentInstrCycles = 32;
4997: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel301; }
4998: {{ uae_s16 extra = get_iword(2);
4999: if (extra & 0x800)
5000: { uae_u32 src = regs.regs[(extra >> 12) & 15];
5001: { uaecptr dsta = get_ilong(4);
5002: put_word(dsta,src);
5003: }}else{{ uaecptr srca = get_ilong(8);
5004: { uae_s16 src = get_word(srca);
5005: if (extra & 0x8000) {
5006: m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
5007: } else {
5008: m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
5009: }
5010: }}}}}}m68k_incpc(12);
5011: endlabel301: ;
5012: return 32;
5013: }
5014: unsigned long REGPARAM2 CPUFUNC(op_e90_0)(uae_u32 opcode) /* MOVES */
5015: {
5016: uae_u32 dstreg = opcode & 7;
5017: OpcodeFamily = 103; CurrentInstrCycles = 24;
5018: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel302; }
5019: {{ uae_s16 extra = get_iword(2);
5020: if (extra & 0x800)
5021: { uae_u32 src = regs.regs[(extra >> 12) & 15];
5022: { uaecptr dsta = m68k_areg(regs, dstreg);
5023: put_long(dsta,src);
5024: }}else{{ uaecptr srca = m68k_areg(regs, dstreg);
5025: { uae_s32 src = get_long(srca);
5026: if (extra & 0x8000) {
5027: m68k_areg(regs, (extra >> 12) & 7) = src;
5028: } else {
5029: m68k_dreg(regs, (extra >> 12) & 7) = (src);
5030: }
5031: }}}}}}m68k_incpc(4);
5032: endlabel302: ;
5033: return 24;
5034: }
5035: unsigned long REGPARAM2 CPUFUNC(op_e98_0)(uae_u32 opcode) /* MOVES */
5036: {
5037: uae_u32 dstreg = opcode & 7;
5038: OpcodeFamily = 103; CurrentInstrCycles = 24;
5039: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel303; }
5040: {{ uae_s16 extra = get_iword(2);
5041: if (extra & 0x800)
5042: { uae_u32 src = regs.regs[(extra >> 12) & 15];
5043: { uaecptr dsta = m68k_areg(regs, dstreg);
5044: m68k_areg(regs, dstreg) += 4;
5045: put_long(dsta,src);
5046: }}else{{ uaecptr srca = m68k_areg(regs, dstreg);
5047: { uae_s32 src = get_long(srca);
5048: m68k_areg(regs, dstreg) += 4;
5049: if (extra & 0x8000) {
5050: m68k_areg(regs, (extra >> 12) & 7) = src;
5051: } else {
5052: m68k_dreg(regs, (extra >> 12) & 7) = (src);
5053: }
5054: }}}}}}m68k_incpc(4);
5055: endlabel303: ;
5056: return 24;
5057: }
5058: unsigned long REGPARAM2 CPUFUNC(op_ea0_0)(uae_u32 opcode) /* MOVES */
5059: {
5060: uae_u32 dstreg = opcode & 7;
5061: OpcodeFamily = 103; CurrentInstrCycles = 28;
5062: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel304; }
5063: {{ uae_s16 extra = get_iword(2);
5064: if (extra & 0x800)
5065: { uae_u32 src = regs.regs[(extra >> 12) & 15];
5066: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
5067: m68k_areg (regs, dstreg) = dsta;
5068: put_long(dsta,src);
5069: }}else{{ uaecptr srca = m68k_areg(regs, dstreg) - 4;
5070: { uae_s32 src = get_long(srca);
5071: m68k_areg (regs, dstreg) = srca;
5072: if (extra & 0x8000) {
5073: m68k_areg(regs, (extra >> 12) & 7) = src;
5074: } else {
5075: m68k_dreg(regs, (extra >> 12) & 7) = (src);
5076: }
5077: }}}}}}m68k_incpc(4);
5078: endlabel304: ;
5079: return 28;
5080: }
5081: unsigned long REGPARAM2 CPUFUNC(op_ea8_0)(uae_u32 opcode) /* MOVES */
5082: {
5083: uae_u32 dstreg = opcode & 7;
5084: OpcodeFamily = 103; CurrentInstrCycles = 32;
5085: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel305; }
5086: {{ uae_s16 extra = get_iword(2);
5087: if (extra & 0x800)
5088: { uae_u32 src = regs.regs[(extra >> 12) & 15];
5089: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
5090: put_long(dsta,src);
5091: }}else{{ uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
5092: { uae_s32 src = get_long(srca);
5093: if (extra & 0x8000) {
5094: m68k_areg(regs, (extra >> 12) & 7) = src;
5095: } else {
5096: m68k_dreg(regs, (extra >> 12) & 7) = (src);
5097: }
5098: }}}}}}m68k_incpc(8);
5099: endlabel305: ;
5100: return 32;
5101: }
5102: unsigned long REGPARAM2 CPUFUNC(op_eb0_0)(uae_u32 opcode) /* MOVES */
5103: {
5104: uae_u32 dstreg = opcode & 7;
5105: OpcodeFamily = 103; CurrentInstrCycles = 36;
5106: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel306; }
5107: {{ uae_s16 extra = get_iword(2);
5108: if (extra & 0x800)
5109: { uae_u32 src = regs.regs[(extra >> 12) & 15];
5110: {m68k_incpc(4);
5111: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
5112: BusCyclePenalty += 2;
5113: put_long(dsta,src);
5114: }}}else{{{ uaecptr srca = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
5115: BusCyclePenalty += 2;
5116: { uae_s32 src = get_long(srca);
5117: if (extra & 0x8000) {
5118: m68k_areg(regs, (extra >> 12) & 7) = src;
5119: } else {
5120: m68k_dreg(regs, (extra >> 12) & 7) = (src);
5121: }
5122: }}}}}}}endlabel306: ;
5123: return 36;
5124: }
5125: unsigned long REGPARAM2 CPUFUNC(op_eb8_0)(uae_u32 opcode) /* MOVES */
5126: {
5127: OpcodeFamily = 103; CurrentInstrCycles = 32;
5128: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel307; }
5129: {{ uae_s16 extra = get_iword(2);
5130: if (extra & 0x800)
5131: { uae_u32 src = regs.regs[(extra >> 12) & 15];
5132: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
5133: put_long(dsta,src);
5134: }}else{{ uaecptr srca = (uae_s32)(uae_s16)get_iword(6);
5135: { uae_s32 src = get_long(srca);
5136: if (extra & 0x8000) {
5137: m68k_areg(regs, (extra >> 12) & 7) = src;
5138: } else {
5139: m68k_dreg(regs, (extra >> 12) & 7) = (src);
5140: }
5141: }}}}}}m68k_incpc(8);
5142: endlabel307: ;
5143: return 32;
5144: }
5145: unsigned long REGPARAM2 CPUFUNC(op_eb9_0)(uae_u32 opcode) /* MOVES */
5146: {
5147: OpcodeFamily = 103; CurrentInstrCycles = 40;
5148: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel308; }
5149: {{ uae_s16 extra = get_iword(2);
5150: if (extra & 0x800)
5151: { uae_u32 src = regs.regs[(extra >> 12) & 15];
5152: { uaecptr dsta = get_ilong(4);
5153: put_long(dsta,src);
5154: }}else{{ uaecptr srca = get_ilong(8);
5155: { uae_s32 src = get_long(srca);
5156: if (extra & 0x8000) {
5157: m68k_areg(regs, (extra >> 12) & 7) = src;
5158: } else {
5159: m68k_dreg(regs, (extra >> 12) & 7) = (src);
5160: }
5161: }}}}}}m68k_incpc(12);
5162: endlabel308: ;
5163: return 40;
5164: }
5165: unsigned long REGPARAM2 CPUFUNC(op_ed0_0)(uae_u32 opcode) /* CAS */
5166: {
5167: uae_u32 dstreg = opcode & 7;
5168: OpcodeFamily = 84; CurrentInstrCycles = 24;
5169: {{ uae_s16 src = get_iword(2);
5170: { uaecptr dsta = m68k_areg(regs, dstreg);
5171: { uae_s32 dst = get_long(dsta);
5172: { int ru = (src >> 6) & 7;
5173: int rc = src & 7;
5174: {uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(m68k_dreg(regs, rc)));
5175: { int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
5176: int flgo = ((uae_s32)(dst)) < 0;
5177: int flgn = ((uae_s32)(newv)) < 0;
5178: SET_ZFLG (((uae_s32)(newv)) == 0);
5179: SET_VFLG ((flgs != flgo) && (flgn != flgo));
5180: SET_CFLG (((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
5181: SET_NFLG (flgn != 0);
5182: if (GET_ZFLG){ put_long(dsta,(m68k_dreg(regs, ru)));
5183: }else{m68k_dreg(regs, rc) = dst;
5184: }}}}}}}}m68k_incpc(4);
5185: return 24;
5186: }
5187: unsigned long REGPARAM2 CPUFUNC(op_ed8_0)(uae_u32 opcode) /* CAS */
5188: {
5189: uae_u32 dstreg = opcode & 7;
5190: OpcodeFamily = 84; CurrentInstrCycles = 24;
5191: {{ uae_s16 src = get_iword(2);
5192: { uaecptr dsta = m68k_areg(regs, dstreg);
5193: { uae_s32 dst = get_long(dsta);
5194: m68k_areg(regs, dstreg) += 4;
5195: { int ru = (src >> 6) & 7;
5196: int rc = src & 7;
5197: {uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(m68k_dreg(regs, rc)));
5198: { int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
5199: int flgo = ((uae_s32)(dst)) < 0;
5200: int flgn = ((uae_s32)(newv)) < 0;
5201: SET_ZFLG (((uae_s32)(newv)) == 0);
5202: SET_VFLG ((flgs != flgo) && (flgn != flgo));
5203: SET_CFLG (((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
5204: SET_NFLG (flgn != 0);
5205: if (GET_ZFLG){ put_long(dsta,(m68k_dreg(regs, ru)));
5206: }else{m68k_dreg(regs, rc) = dst;
5207: }}}}}}}}m68k_incpc(4);
5208: return 24;
5209: }
5210: unsigned long REGPARAM2 CPUFUNC(op_ee0_0)(uae_u32 opcode) /* CAS */
5211: {
5212: uae_u32 dstreg = opcode & 7;
5213: OpcodeFamily = 84; CurrentInstrCycles = 26;
5214: {{ uae_s16 src = get_iword(2);
5215: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
5216: { uae_s32 dst = get_long(dsta);
5217: m68k_areg (regs, dstreg) = dsta;
5218: { int ru = (src >> 6) & 7;
5219: int rc = src & 7;
5220: {uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(m68k_dreg(regs, rc)));
5221: { int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
5222: int flgo = ((uae_s32)(dst)) < 0;
5223: int flgn = ((uae_s32)(newv)) < 0;
5224: SET_ZFLG (((uae_s32)(newv)) == 0);
5225: SET_VFLG ((flgs != flgo) && (flgn != flgo));
5226: SET_CFLG (((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
5227: SET_NFLG (flgn != 0);
5228: if (GET_ZFLG){ put_long(dsta,(m68k_dreg(regs, ru)));
5229: }else{m68k_dreg(regs, rc) = dst;
5230: }}}}}}}}m68k_incpc(4);
5231: return 26;
5232: }
5233: unsigned long REGPARAM2 CPUFUNC(op_ee8_0)(uae_u32 opcode) /* CAS */
5234: {
5235: uae_u32 dstreg = opcode & 7;
5236: OpcodeFamily = 84; CurrentInstrCycles = 28;
5237: {{ uae_s16 src = get_iword(2);
5238: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
5239: { uae_s32 dst = get_long(dsta);
5240: { int ru = (src >> 6) & 7;
5241: int rc = src & 7;
5242: {uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(m68k_dreg(regs, rc)));
5243: { int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
5244: int flgo = ((uae_s32)(dst)) < 0;
5245: int flgn = ((uae_s32)(newv)) < 0;
5246: SET_ZFLG (((uae_s32)(newv)) == 0);
5247: SET_VFLG ((flgs != flgo) && (flgn != flgo));
5248: SET_CFLG (((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
5249: SET_NFLG (flgn != 0);
5250: if (GET_ZFLG){ put_long(dsta,(m68k_dreg(regs, ru)));
5251: }else{m68k_dreg(regs, rc) = dst;
5252: }}}}}}}}m68k_incpc(6);
5253: return 28;
5254: }
5255: unsigned long REGPARAM2 CPUFUNC(op_ef0_0)(uae_u32 opcode) /* CAS */
5256: {
5257: uae_u32 dstreg = opcode & 7;
5258: OpcodeFamily = 84; CurrentInstrCycles = 30;
5259: {{ uae_s16 src = get_iword(2);
5260: {m68k_incpc(4);
5261: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
5262: BusCyclePenalty += 2;
5263: { uae_s32 dst = get_long(dsta);
5264: { int ru = (src >> 6) & 7;
5265: int rc = src & 7;
5266: {uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(m68k_dreg(regs, rc)));
5267: { int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
5268: int flgo = ((uae_s32)(dst)) < 0;
5269: int flgn = ((uae_s32)(newv)) < 0;
5270: SET_ZFLG (((uae_s32)(newv)) == 0);
5271: SET_VFLG ((flgs != flgo) && (flgn != flgo));
5272: SET_CFLG (((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
5273: SET_NFLG (flgn != 0);
5274: if (GET_ZFLG){ put_long(dsta,(m68k_dreg(regs, ru)));
5275: }else{m68k_dreg(regs, rc) = dst;
5276: }}}}}}}}}return 30;
5277: }
5278: unsigned long REGPARAM2 CPUFUNC(op_ef8_0)(uae_u32 opcode) /* CAS */
5279: {
5280: OpcodeFamily = 84; CurrentInstrCycles = 28;
5281: {{ uae_s16 src = get_iword(2);
5282: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
5283: { uae_s32 dst = get_long(dsta);
5284: { int ru = (src >> 6) & 7;
5285: int rc = src & 7;
5286: {uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(m68k_dreg(regs, rc)));
5287: { int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
5288: int flgo = ((uae_s32)(dst)) < 0;
5289: int flgn = ((uae_s32)(newv)) < 0;
5290: SET_ZFLG (((uae_s32)(newv)) == 0);
5291: SET_VFLG ((flgs != flgo) && (flgn != flgo));
5292: SET_CFLG (((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
5293: SET_NFLG (flgn != 0);
5294: if (GET_ZFLG){ put_long(dsta,(m68k_dreg(regs, ru)));
5295: }else{m68k_dreg(regs, rc) = dst;
5296: }}}}}}}}m68k_incpc(6);
5297: return 28;
5298: }
5299: unsigned long REGPARAM2 CPUFUNC(op_ef9_0)(uae_u32 opcode) /* CAS */
5300: {
5301: OpcodeFamily = 84; CurrentInstrCycles = 32;
5302: {{ uae_s16 src = get_iword(2);
5303: { uaecptr dsta = get_ilong(4);
5304: { uae_s32 dst = get_long(dsta);
5305: { int ru = (src >> 6) & 7;
5306: int rc = src & 7;
5307: {uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(m68k_dreg(regs, rc)));
5308: { int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
5309: int flgo = ((uae_s32)(dst)) < 0;
5310: int flgn = ((uae_s32)(newv)) < 0;
5311: SET_ZFLG (((uae_s32)(newv)) == 0);
5312: SET_VFLG ((flgs != flgo) && (flgn != flgo));
5313: SET_CFLG (((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
5314: SET_NFLG (flgn != 0);
5315: if (GET_ZFLG){ put_long(dsta,(m68k_dreg(regs, ru)));
5316: }else{m68k_dreg(regs, rc) = dst;
5317: }}}}}}}}m68k_incpc(8);
5318: return 32;
5319: }
5320: unsigned long REGPARAM2 CPUFUNC(op_efc_0)(uae_u32 opcode) /* CAS2 */
5321: {
5322: OpcodeFamily = 85; CurrentInstrCycles = 12;
5323: {{ uae_s32 extra = get_ilong(2);
5324: uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
5325: uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
5326: uae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);
5327: {uae_u32 newv = ((uae_s32)(dst1)) - ((uae_s32)(m68k_dreg(regs, (extra >> 16) & 7)));
5328: { int flgs = ((uae_s32)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
5329: int flgo = ((uae_s32)(dst1)) < 0;
5330: int flgn = ((uae_s32)(newv)) < 0;
5331: SET_ZFLG (((uae_s32)(newv)) == 0);
5332: SET_VFLG ((flgs != flgo) && (flgn != flgo));
5333: SET_CFLG (((uae_u32)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
5334: SET_NFLG (flgn != 0);
5335: if (GET_ZFLG) {
5336: {uae_u32 newv = ((uae_s32)(dst2)) - ((uae_s32)(m68k_dreg(regs, extra & 7)));
5337: { int flgs = ((uae_s32)(m68k_dreg(regs, extra & 7))) < 0;
5338: int flgo = ((uae_s32)(dst2)) < 0;
5339: int flgn = ((uae_s32)(newv)) < 0;
5340: SET_ZFLG (((uae_s32)(newv)) == 0);
5341: SET_VFLG ((flgs != flgo) && (flgn != flgo));
5342: SET_CFLG (((uae_u32)(m68k_dreg(regs, extra & 7))) > ((uae_u32)(dst2)));
5343: SET_NFLG (flgn != 0);
5344: if (GET_ZFLG) {
5345: put_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));
5346: put_long(rn1, m68k_dreg(regs, (extra >> 6) & 7));
5347: }}
5348: }}}} if (! GET_ZFLG) {
5349: m68k_dreg(regs, (extra >> 22) & 7) = dst1;
5350: m68k_dreg(regs, (extra >> 6) & 7) = dst2;
5351: }
5352: }}m68k_incpc(6);
5353: return 12;
5354: }
5355: unsigned long REGPARAM2 CPUFUNC(op_1000_0)(uae_u32 opcode) /* MOVE */
5356: {
5357: uae_u32 srcreg = (opcode & 7);
5358: uae_u32 dstreg = (opcode >> 9) & 7;
5359: OpcodeFamily = 30; CurrentInstrCycles = 4;
5360: {{ uae_s8 src = m68k_dreg(regs, srcreg);
5361: { CLEAR_CZNV;
5362: SET_ZFLG (((uae_s8)(src)) == 0);
5363: SET_NFLG (((uae_s8)(src)) < 0);
5364: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5365: }}}m68k_incpc(2);
5366: return 4;
5367: }
5368: unsigned long REGPARAM2 CPUFUNC(op_1008_0)(uae_u32 opcode) /* MOVE */
5369: {
5370: uae_u32 srcreg = (opcode & 7);
5371: uae_u32 dstreg = (opcode >> 9) & 7;
5372: OpcodeFamily = 30; CurrentInstrCycles = 4;
5373: {{ uae_s8 src = m68k_areg(regs, srcreg);
5374: { CLEAR_CZNV;
5375: SET_ZFLG (((uae_s8)(src)) == 0);
5376: SET_NFLG (((uae_s8)(src)) < 0);
5377: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5378: }}}m68k_incpc(2);
5379: return 4;
5380: }
5381: unsigned long REGPARAM2 CPUFUNC(op_1010_0)(uae_u32 opcode) /* MOVE */
5382: {
5383: uae_u32 srcreg = (opcode & 7);
5384: uae_u32 dstreg = (opcode >> 9) & 7;
5385: OpcodeFamily = 30; CurrentInstrCycles = 8;
5386: {{ uaecptr srca = m68k_areg(regs, srcreg);
5387: { uae_s8 src = get_byte(srca);
5388: { CLEAR_CZNV;
5389: SET_ZFLG (((uae_s8)(src)) == 0);
5390: SET_NFLG (((uae_s8)(src)) < 0);
5391: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5392: }}}}m68k_incpc(2);
5393: return 8;
5394: }
5395: unsigned long REGPARAM2 CPUFUNC(op_1018_0)(uae_u32 opcode) /* MOVE */
5396: {
5397: uae_u32 srcreg = (opcode & 7);
5398: uae_u32 dstreg = (opcode >> 9) & 7;
5399: OpcodeFamily = 30; CurrentInstrCycles = 8;
5400: {{ uaecptr srca = m68k_areg(regs, srcreg);
5401: { uae_s8 src = get_byte(srca);
5402: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
5403: { CLEAR_CZNV;
5404: SET_ZFLG (((uae_s8)(src)) == 0);
5405: SET_NFLG (((uae_s8)(src)) < 0);
5406: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5407: }}}}m68k_incpc(2);
5408: return 8;
5409: }
5410: unsigned long REGPARAM2 CPUFUNC(op_1020_0)(uae_u32 opcode) /* MOVE */
5411: {
5412: uae_u32 srcreg = (opcode & 7);
5413: uae_u32 dstreg = (opcode >> 9) & 7;
5414: OpcodeFamily = 30; CurrentInstrCycles = 10;
5415: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
5416: { uae_s8 src = get_byte(srca);
5417: m68k_areg (regs, srcreg) = srca;
5418: { CLEAR_CZNV;
5419: SET_ZFLG (((uae_s8)(src)) == 0);
5420: SET_NFLG (((uae_s8)(src)) < 0);
5421: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5422: }}}}m68k_incpc(2);
5423: return 10;
5424: }
5425: unsigned long REGPARAM2 CPUFUNC(op_1028_0)(uae_u32 opcode) /* MOVE */
5426: {
5427: uae_u32 srcreg = (opcode & 7);
5428: uae_u32 dstreg = (opcode >> 9) & 7;
5429: OpcodeFamily = 30; CurrentInstrCycles = 12;
5430: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
5431: { uae_s8 src = get_byte(srca);
5432: { CLEAR_CZNV;
5433: SET_ZFLG (((uae_s8)(src)) == 0);
5434: SET_NFLG (((uae_s8)(src)) < 0);
5435: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5436: }}}}m68k_incpc(4);
5437: return 12;
5438: }
5439: unsigned long REGPARAM2 CPUFUNC(op_1030_0)(uae_u32 opcode) /* MOVE */
5440: {
5441: uae_u32 srcreg = (opcode & 7);
5442: uae_u32 dstreg = (opcode >> 9) & 7;
5443: OpcodeFamily = 30; CurrentInstrCycles = 14;
5444: {{m68k_incpc(2);
5445: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
5446: BusCyclePenalty += 2;
5447: { uae_s8 src = get_byte(srca);
5448: { CLEAR_CZNV;
5449: SET_ZFLG (((uae_s8)(src)) == 0);
5450: SET_NFLG (((uae_s8)(src)) < 0);
5451: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5452: }}}}}return 14;
5453: }
5454: unsigned long REGPARAM2 CPUFUNC(op_1038_0)(uae_u32 opcode) /* MOVE */
5455: {
5456: uae_u32 dstreg = (opcode >> 9) & 7;
5457: OpcodeFamily = 30; CurrentInstrCycles = 12;
5458: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
5459: { uae_s8 src = get_byte(srca);
5460: { CLEAR_CZNV;
5461: SET_ZFLG (((uae_s8)(src)) == 0);
5462: SET_NFLG (((uae_s8)(src)) < 0);
5463: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5464: }}}}m68k_incpc(4);
5465: return 12;
5466: }
5467: unsigned long REGPARAM2 CPUFUNC(op_1039_0)(uae_u32 opcode) /* MOVE */
5468: {
5469: uae_u32 dstreg = (opcode >> 9) & 7;
5470: OpcodeFamily = 30; CurrentInstrCycles = 16;
5471: {{ uaecptr srca = get_ilong(2);
5472: { uae_s8 src = get_byte(srca);
5473: { CLEAR_CZNV;
5474: SET_ZFLG (((uae_s8)(src)) == 0);
5475: SET_NFLG (((uae_s8)(src)) < 0);
5476: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5477: }}}}m68k_incpc(6);
5478: return 16;
5479: }
5480: unsigned long REGPARAM2 CPUFUNC(op_103a_0)(uae_u32 opcode) /* MOVE */
5481: {
5482: uae_u32 dstreg = (opcode >> 9) & 7;
5483: OpcodeFamily = 30; CurrentInstrCycles = 12;
5484: {{ uaecptr srca = m68k_getpc () + 2;
5485: srca += (uae_s32)(uae_s16)get_iword(2);
5486: { uae_s8 src = get_byte(srca);
5487: { CLEAR_CZNV;
5488: SET_ZFLG (((uae_s8)(src)) == 0);
5489: SET_NFLG (((uae_s8)(src)) < 0);
5490: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5491: }}}}m68k_incpc(4);
5492: return 12;
5493: }
5494: unsigned long REGPARAM2 CPUFUNC(op_103b_0)(uae_u32 opcode) /* MOVE */
5495: {
5496: uae_u32 dstreg = (opcode >> 9) & 7;
5497: OpcodeFamily = 30; CurrentInstrCycles = 14;
5498: {{m68k_incpc(2);
5499: { uaecptr tmppc = m68k_getpc();
5500: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
5501: BusCyclePenalty += 2;
5502: { uae_s8 src = get_byte(srca);
5503: { CLEAR_CZNV;
5504: SET_ZFLG (((uae_s8)(src)) == 0);
5505: SET_NFLG (((uae_s8)(src)) < 0);
5506: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5507: }}}}}return 14;
5508: }
5509: unsigned long REGPARAM2 CPUFUNC(op_103c_0)(uae_u32 opcode) /* MOVE */
5510: {
5511: uae_u32 dstreg = (opcode >> 9) & 7;
5512: OpcodeFamily = 30; CurrentInstrCycles = 8;
5513: {{ uae_s8 src = get_ibyte(2);
5514: { CLEAR_CZNV;
5515: SET_ZFLG (((uae_s8)(src)) == 0);
5516: SET_NFLG (((uae_s8)(src)) < 0);
5517: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
5518: }}}m68k_incpc(4);
5519: return 8;
5520: }
5521: unsigned long REGPARAM2 CPUFUNC(op_1080_0)(uae_u32 opcode) /* MOVE */
5522: {
5523: uae_u32 srcreg = (opcode & 7);
5524: uae_u32 dstreg = (opcode >> 9) & 7;
5525: OpcodeFamily = 30; CurrentInstrCycles = 8;
5526: {{ uae_s8 src = m68k_dreg(regs, srcreg);
5527: { uaecptr dsta = m68k_areg(regs, dstreg);
5528: CLEAR_CZNV;
5529: SET_ZFLG (((uae_s8)(src)) == 0);
5530: SET_NFLG (((uae_s8)(src)) < 0);
5531: put_byte(dsta,src);
5532: }}}m68k_incpc(2);
5533: return 8;
5534: }
5535: unsigned long REGPARAM2 CPUFUNC(op_1088_0)(uae_u32 opcode) /* MOVE */
5536: {
5537: uae_u32 srcreg = (opcode & 7);
5538: uae_u32 dstreg = (opcode >> 9) & 7;
5539: OpcodeFamily = 30; CurrentInstrCycles = 8;
5540: {{ uae_s8 src = m68k_areg(regs, srcreg);
5541: { uaecptr dsta = m68k_areg(regs, dstreg);
5542: CLEAR_CZNV;
5543: SET_ZFLG (((uae_s8)(src)) == 0);
5544: SET_NFLG (((uae_s8)(src)) < 0);
5545: put_byte(dsta,src);
5546: }}}m68k_incpc(2);
5547: return 8;
5548: }
5549: unsigned long REGPARAM2 CPUFUNC(op_1090_0)(uae_u32 opcode) /* MOVE */
5550: {
5551: uae_u32 srcreg = (opcode & 7);
5552: uae_u32 dstreg = (opcode >> 9) & 7;
5553: OpcodeFamily = 30; CurrentInstrCycles = 12;
5554: {{ uaecptr srca = m68k_areg(regs, srcreg);
5555: { uae_s8 src = get_byte(srca);
5556: { uaecptr dsta = m68k_areg(regs, dstreg);
5557: CLEAR_CZNV;
5558: SET_ZFLG (((uae_s8)(src)) == 0);
5559: SET_NFLG (((uae_s8)(src)) < 0);
5560: put_byte(dsta,src);
5561: }}}}m68k_incpc(2);
5562: return 12;
5563: }
5564: unsigned long REGPARAM2 CPUFUNC(op_1098_0)(uae_u32 opcode) /* MOVE */
5565: {
5566: uae_u32 srcreg = (opcode & 7);
5567: uae_u32 dstreg = (opcode >> 9) & 7;
5568: OpcodeFamily = 30; CurrentInstrCycles = 12;
5569: {{ uaecptr srca = m68k_areg(regs, srcreg);
5570: { uae_s8 src = get_byte(srca);
5571: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
5572: { uaecptr dsta = m68k_areg(regs, dstreg);
5573: CLEAR_CZNV;
5574: SET_ZFLG (((uae_s8)(src)) == 0);
5575: SET_NFLG (((uae_s8)(src)) < 0);
5576: put_byte(dsta,src);
5577: }}}}m68k_incpc(2);
5578: return 12;
5579: }
5580: unsigned long REGPARAM2 CPUFUNC(op_10a0_0)(uae_u32 opcode) /* MOVE */
5581: {
5582: uae_u32 srcreg = (opcode & 7);
5583: uae_u32 dstreg = (opcode >> 9) & 7;
5584: OpcodeFamily = 30; CurrentInstrCycles = 14;
5585: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
5586: { uae_s8 src = get_byte(srca);
5587: m68k_areg (regs, srcreg) = srca;
5588: { uaecptr dsta = m68k_areg(regs, dstreg);
5589: CLEAR_CZNV;
5590: SET_ZFLG (((uae_s8)(src)) == 0);
5591: SET_NFLG (((uae_s8)(src)) < 0);
5592: put_byte(dsta,src);
5593: }}}}m68k_incpc(2);
5594: return 14;
5595: }
5596: unsigned long REGPARAM2 CPUFUNC(op_10a8_0)(uae_u32 opcode) /* MOVE */
5597: {
5598: uae_u32 srcreg = (opcode & 7);
5599: uae_u32 dstreg = (opcode >> 9) & 7;
5600: OpcodeFamily = 30; CurrentInstrCycles = 16;
5601: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
5602: { uae_s8 src = get_byte(srca);
5603: { uaecptr dsta = m68k_areg(regs, dstreg);
5604: CLEAR_CZNV;
5605: SET_ZFLG (((uae_s8)(src)) == 0);
5606: SET_NFLG (((uae_s8)(src)) < 0);
5607: put_byte(dsta,src);
5608: }}}}m68k_incpc(4);
5609: return 16;
5610: }
5611: unsigned long REGPARAM2 CPUFUNC(op_10b0_0)(uae_u32 opcode) /* MOVE */
5612: {
5613: uae_u32 srcreg = (opcode & 7);
5614: uae_u32 dstreg = (opcode >> 9) & 7;
5615: OpcodeFamily = 30; CurrentInstrCycles = 18;
5616: {{m68k_incpc(2);
5617: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
5618: BusCyclePenalty += 2;
5619: { uae_s8 src = get_byte(srca);
5620: { uaecptr dsta = m68k_areg(regs, dstreg);
5621: CLEAR_CZNV;
5622: SET_ZFLG (((uae_s8)(src)) == 0);
5623: SET_NFLG (((uae_s8)(src)) < 0);
5624: put_byte(dsta,src);
5625: }}}}}return 18;
5626: }
5627: unsigned long REGPARAM2 CPUFUNC(op_10b8_0)(uae_u32 opcode) /* MOVE */
5628: {
5629: uae_u32 dstreg = (opcode >> 9) & 7;
5630: OpcodeFamily = 30; CurrentInstrCycles = 16;
5631: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
5632: { uae_s8 src = get_byte(srca);
5633: { uaecptr dsta = m68k_areg(regs, dstreg);
5634: CLEAR_CZNV;
5635: SET_ZFLG (((uae_s8)(src)) == 0);
5636: SET_NFLG (((uae_s8)(src)) < 0);
5637: put_byte(dsta,src);
5638: }}}}m68k_incpc(4);
5639: return 16;
5640: }
5641: unsigned long REGPARAM2 CPUFUNC(op_10b9_0)(uae_u32 opcode) /* MOVE */
5642: {
5643: uae_u32 dstreg = (opcode >> 9) & 7;
5644: OpcodeFamily = 30; CurrentInstrCycles = 20;
5645: {{ uaecptr srca = get_ilong(2);
5646: { uae_s8 src = get_byte(srca);
5647: { uaecptr dsta = m68k_areg(regs, dstreg);
5648: CLEAR_CZNV;
5649: SET_ZFLG (((uae_s8)(src)) == 0);
5650: SET_NFLG (((uae_s8)(src)) < 0);
5651: put_byte(dsta,src);
5652: }}}}m68k_incpc(6);
5653: return 20;
5654: }
5655: unsigned long REGPARAM2 CPUFUNC(op_10ba_0)(uae_u32 opcode) /* MOVE */
5656: {
5657: uae_u32 dstreg = (opcode >> 9) & 7;
5658: OpcodeFamily = 30; CurrentInstrCycles = 16;
5659: {{ uaecptr srca = m68k_getpc () + 2;
5660: srca += (uae_s32)(uae_s16)get_iword(2);
5661: { uae_s8 src = get_byte(srca);
5662: { uaecptr dsta = m68k_areg(regs, dstreg);
5663: CLEAR_CZNV;
5664: SET_ZFLG (((uae_s8)(src)) == 0);
5665: SET_NFLG (((uae_s8)(src)) < 0);
5666: put_byte(dsta,src);
5667: }}}}m68k_incpc(4);
5668: return 16;
5669: }
5670: unsigned long REGPARAM2 CPUFUNC(op_10bb_0)(uae_u32 opcode) /* MOVE */
5671: {
5672: uae_u32 dstreg = (opcode >> 9) & 7;
5673: OpcodeFamily = 30; CurrentInstrCycles = 18;
5674: {{m68k_incpc(2);
5675: { uaecptr tmppc = m68k_getpc();
5676: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
5677: BusCyclePenalty += 2;
5678: { uae_s8 src = get_byte(srca);
5679: { uaecptr dsta = m68k_areg(regs, dstreg);
5680: CLEAR_CZNV;
5681: SET_ZFLG (((uae_s8)(src)) == 0);
5682: SET_NFLG (((uae_s8)(src)) < 0);
5683: put_byte(dsta,src);
5684: }}}}}return 18;
5685: }
5686: unsigned long REGPARAM2 CPUFUNC(op_10bc_0)(uae_u32 opcode) /* MOVE */
5687: {
5688: uae_u32 dstreg = (opcode >> 9) & 7;
5689: OpcodeFamily = 30; CurrentInstrCycles = 12;
5690: {{ uae_s8 src = get_ibyte(2);
5691: { uaecptr dsta = m68k_areg(regs, dstreg);
5692: CLEAR_CZNV;
5693: SET_ZFLG (((uae_s8)(src)) == 0);
5694: SET_NFLG (((uae_s8)(src)) < 0);
5695: put_byte(dsta,src);
5696: }}}m68k_incpc(4);
5697: return 12;
5698: }
5699: unsigned long REGPARAM2 CPUFUNC(op_10c0_0)(uae_u32 opcode) /* MOVE */
5700: {
5701: uae_u32 srcreg = (opcode & 7);
5702: uae_u32 dstreg = (opcode >> 9) & 7;
5703: OpcodeFamily = 30; CurrentInstrCycles = 8;
5704: {{ uae_s8 src = m68k_dreg(regs, srcreg);
5705: { uaecptr dsta = m68k_areg(regs, dstreg);
5706: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5707: CLEAR_CZNV;
5708: SET_ZFLG (((uae_s8)(src)) == 0);
5709: SET_NFLG (((uae_s8)(src)) < 0);
5710: put_byte(dsta,src);
5711: }}}m68k_incpc(2);
5712: return 8;
5713: }
5714: unsigned long REGPARAM2 CPUFUNC(op_10c8_0)(uae_u32 opcode) /* MOVE */
5715: {
5716: uae_u32 srcreg = (opcode & 7);
5717: uae_u32 dstreg = (opcode >> 9) & 7;
5718: OpcodeFamily = 30; CurrentInstrCycles = 8;
5719: {{ uae_s8 src = m68k_areg(regs, srcreg);
5720: { uaecptr dsta = m68k_areg(regs, dstreg);
5721: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5722: CLEAR_CZNV;
5723: SET_ZFLG (((uae_s8)(src)) == 0);
5724: SET_NFLG (((uae_s8)(src)) < 0);
5725: put_byte(dsta,src);
5726: }}}m68k_incpc(2);
5727: return 8;
5728: }
5729: unsigned long REGPARAM2 CPUFUNC(op_10d0_0)(uae_u32 opcode) /* MOVE */
5730: {
5731: uae_u32 srcreg = (opcode & 7);
5732: uae_u32 dstreg = (opcode >> 9) & 7;
5733: OpcodeFamily = 30; CurrentInstrCycles = 12;
5734: {{ uaecptr srca = m68k_areg(regs, srcreg);
5735: { uae_s8 src = get_byte(srca);
5736: { uaecptr dsta = m68k_areg(regs, dstreg);
5737: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5738: CLEAR_CZNV;
5739: SET_ZFLG (((uae_s8)(src)) == 0);
5740: SET_NFLG (((uae_s8)(src)) < 0);
5741: put_byte(dsta,src);
5742: }}}}m68k_incpc(2);
5743: return 12;
5744: }
5745: unsigned long REGPARAM2 CPUFUNC(op_10d8_0)(uae_u32 opcode) /* MOVE */
5746: {
5747: uae_u32 srcreg = (opcode & 7);
5748: uae_u32 dstreg = (opcode >> 9) & 7;
5749: OpcodeFamily = 30; CurrentInstrCycles = 12;
5750: {{ uaecptr srca = m68k_areg(regs, srcreg);
5751: { uae_s8 src = get_byte(srca);
5752: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
5753: { uaecptr dsta = m68k_areg(regs, dstreg);
5754: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5755: CLEAR_CZNV;
5756: SET_ZFLG (((uae_s8)(src)) == 0);
5757: SET_NFLG (((uae_s8)(src)) < 0);
5758: put_byte(dsta,src);
5759: }}}}m68k_incpc(2);
5760: return 12;
5761: }
5762: unsigned long REGPARAM2 CPUFUNC(op_10e0_0)(uae_u32 opcode) /* MOVE */
5763: {
5764: uae_u32 srcreg = (opcode & 7);
5765: uae_u32 dstreg = (opcode >> 9) & 7;
5766: OpcodeFamily = 30; CurrentInstrCycles = 14;
5767: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
5768: { uae_s8 src = get_byte(srca);
5769: m68k_areg (regs, srcreg) = srca;
5770: { uaecptr dsta = m68k_areg(regs, dstreg);
5771: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5772: CLEAR_CZNV;
5773: SET_ZFLG (((uae_s8)(src)) == 0);
5774: SET_NFLG (((uae_s8)(src)) < 0);
5775: put_byte(dsta,src);
5776: }}}}m68k_incpc(2);
5777: return 14;
5778: }
5779: unsigned long REGPARAM2 CPUFUNC(op_10e8_0)(uae_u32 opcode) /* MOVE */
5780: {
5781: uae_u32 srcreg = (opcode & 7);
5782: uae_u32 dstreg = (opcode >> 9) & 7;
5783: OpcodeFamily = 30; CurrentInstrCycles = 16;
5784: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
5785: { uae_s8 src = get_byte(srca);
5786: { uaecptr dsta = m68k_areg(regs, dstreg);
5787: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5788: CLEAR_CZNV;
5789: SET_ZFLG (((uae_s8)(src)) == 0);
5790: SET_NFLG (((uae_s8)(src)) < 0);
5791: put_byte(dsta,src);
5792: }}}}m68k_incpc(4);
5793: return 16;
5794: }
5795: unsigned long REGPARAM2 CPUFUNC(op_10f0_0)(uae_u32 opcode) /* MOVE */
5796: {
5797: uae_u32 srcreg = (opcode & 7);
5798: uae_u32 dstreg = (opcode >> 9) & 7;
5799: OpcodeFamily = 30; CurrentInstrCycles = 18;
5800: {{m68k_incpc(2);
5801: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
5802: BusCyclePenalty += 2;
5803: { uae_s8 src = get_byte(srca);
5804: { uaecptr dsta = m68k_areg(regs, dstreg);
5805: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5806: CLEAR_CZNV;
5807: SET_ZFLG (((uae_s8)(src)) == 0);
5808: SET_NFLG (((uae_s8)(src)) < 0);
5809: put_byte(dsta,src);
5810: }}}}}return 18;
5811: }
5812: unsigned long REGPARAM2 CPUFUNC(op_10f8_0)(uae_u32 opcode) /* MOVE */
5813: {
5814: uae_u32 dstreg = (opcode >> 9) & 7;
5815: OpcodeFamily = 30; CurrentInstrCycles = 16;
5816: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
5817: { uae_s8 src = get_byte(srca);
5818: { uaecptr dsta = m68k_areg(regs, dstreg);
5819: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5820: CLEAR_CZNV;
5821: SET_ZFLG (((uae_s8)(src)) == 0);
5822: SET_NFLG (((uae_s8)(src)) < 0);
5823: put_byte(dsta,src);
5824: }}}}m68k_incpc(4);
5825: return 16;
5826: }
5827: unsigned long REGPARAM2 CPUFUNC(op_10f9_0)(uae_u32 opcode) /* MOVE */
5828: {
5829: uae_u32 dstreg = (opcode >> 9) & 7;
5830: OpcodeFamily = 30; CurrentInstrCycles = 20;
5831: {{ uaecptr srca = get_ilong(2);
5832: { uae_s8 src = get_byte(srca);
5833: { uaecptr dsta = m68k_areg(regs, dstreg);
5834: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5835: CLEAR_CZNV;
5836: SET_ZFLG (((uae_s8)(src)) == 0);
5837: SET_NFLG (((uae_s8)(src)) < 0);
5838: put_byte(dsta,src);
5839: }}}}m68k_incpc(6);
5840: return 20;
5841: }
5842: unsigned long REGPARAM2 CPUFUNC(op_10fa_0)(uae_u32 opcode) /* MOVE */
5843: {
5844: uae_u32 dstreg = (opcode >> 9) & 7;
5845: OpcodeFamily = 30; CurrentInstrCycles = 16;
5846: {{ uaecptr srca = m68k_getpc () + 2;
5847: srca += (uae_s32)(uae_s16)get_iword(2);
5848: { uae_s8 src = get_byte(srca);
5849: { uaecptr dsta = m68k_areg(regs, dstreg);
5850: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5851: CLEAR_CZNV;
5852: SET_ZFLG (((uae_s8)(src)) == 0);
5853: SET_NFLG (((uae_s8)(src)) < 0);
5854: put_byte(dsta,src);
5855: }}}}m68k_incpc(4);
5856: return 16;
5857: }
5858: unsigned long REGPARAM2 CPUFUNC(op_10fb_0)(uae_u32 opcode) /* MOVE */
5859: {
5860: uae_u32 dstreg = (opcode >> 9) & 7;
5861: OpcodeFamily = 30; CurrentInstrCycles = 18;
5862: {{m68k_incpc(2);
5863: { uaecptr tmppc = m68k_getpc();
5864: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
5865: BusCyclePenalty += 2;
5866: { uae_s8 src = get_byte(srca);
5867: { uaecptr dsta = m68k_areg(regs, dstreg);
5868: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5869: CLEAR_CZNV;
5870: SET_ZFLG (((uae_s8)(src)) == 0);
5871: SET_NFLG (((uae_s8)(src)) < 0);
5872: put_byte(dsta,src);
5873: }}}}}return 18;
5874: }
5875: unsigned long REGPARAM2 CPUFUNC(op_10fc_0)(uae_u32 opcode) /* MOVE */
5876: {
5877: uae_u32 dstreg = (opcode >> 9) & 7;
5878: OpcodeFamily = 30; CurrentInstrCycles = 12;
5879: {{ uae_s8 src = get_ibyte(2);
5880: { uaecptr dsta = m68k_areg(regs, dstreg);
5881: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
5882: CLEAR_CZNV;
5883: SET_ZFLG (((uae_s8)(src)) == 0);
5884: SET_NFLG (((uae_s8)(src)) < 0);
5885: put_byte(dsta,src);
5886: }}}m68k_incpc(4);
5887: return 12;
5888: }
5889: unsigned long REGPARAM2 CPUFUNC(op_1100_0)(uae_u32 opcode) /* MOVE */
5890: {
5891: uae_u32 srcreg = (opcode & 7);
5892: uae_u32 dstreg = (opcode >> 9) & 7;
5893: OpcodeFamily = 30; CurrentInstrCycles = 8;
5894: {{ uae_s8 src = m68k_dreg(regs, srcreg);
5895: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
5896: m68k_areg (regs, dstreg) = dsta;
5897: CLEAR_CZNV;
5898: SET_ZFLG (((uae_s8)(src)) == 0);
5899: SET_NFLG (((uae_s8)(src)) < 0);
5900: put_byte(dsta,src);
5901: }}}m68k_incpc(2);
5902: return 8;
5903: }
5904: unsigned long REGPARAM2 CPUFUNC(op_1108_0)(uae_u32 opcode) /* MOVE */
5905: {
5906: uae_u32 srcreg = (opcode & 7);
5907: uae_u32 dstreg = (opcode >> 9) & 7;
5908: OpcodeFamily = 30; CurrentInstrCycles = 8;
5909: {{ uae_s8 src = m68k_areg(regs, srcreg);
5910: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
5911: m68k_areg (regs, dstreg) = dsta;
5912: CLEAR_CZNV;
5913: SET_ZFLG (((uae_s8)(src)) == 0);
5914: SET_NFLG (((uae_s8)(src)) < 0);
5915: put_byte(dsta,src);
5916: }}}m68k_incpc(2);
5917: return 8;
5918: }
5919: unsigned long REGPARAM2 CPUFUNC(op_1110_0)(uae_u32 opcode) /* MOVE */
5920: {
5921: uae_u32 srcreg = (opcode & 7);
5922: uae_u32 dstreg = (opcode >> 9) & 7;
5923: OpcodeFamily = 30; CurrentInstrCycles = 12;
5924: {{ uaecptr srca = m68k_areg(regs, srcreg);
5925: { uae_s8 src = get_byte(srca);
5926: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
5927: m68k_areg (regs, dstreg) = dsta;
5928: CLEAR_CZNV;
5929: SET_ZFLG (((uae_s8)(src)) == 0);
5930: SET_NFLG (((uae_s8)(src)) < 0);
5931: put_byte(dsta,src);
5932: }}}}m68k_incpc(2);
5933: return 12;
5934: }
5935: unsigned long REGPARAM2 CPUFUNC(op_1118_0)(uae_u32 opcode) /* MOVE */
5936: {
5937: uae_u32 srcreg = (opcode & 7);
5938: uae_u32 dstreg = (opcode >> 9) & 7;
5939: OpcodeFamily = 30; CurrentInstrCycles = 12;
5940: {{ uaecptr srca = m68k_areg(regs, srcreg);
5941: { uae_s8 src = get_byte(srca);
5942: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
5943: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
5944: m68k_areg (regs, dstreg) = dsta;
5945: CLEAR_CZNV;
5946: SET_ZFLG (((uae_s8)(src)) == 0);
5947: SET_NFLG (((uae_s8)(src)) < 0);
5948: put_byte(dsta,src);
5949: }}}}m68k_incpc(2);
5950: return 12;
5951: }
5952: unsigned long REGPARAM2 CPUFUNC(op_1120_0)(uae_u32 opcode) /* MOVE */
5953: {
5954: uae_u32 srcreg = (opcode & 7);
5955: uae_u32 dstreg = (opcode >> 9) & 7;
5956: OpcodeFamily = 30; CurrentInstrCycles = 14;
5957: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
5958: { uae_s8 src = get_byte(srca);
5959: m68k_areg (regs, srcreg) = srca;
5960: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
5961: m68k_areg (regs, dstreg) = dsta;
5962: CLEAR_CZNV;
5963: SET_ZFLG (((uae_s8)(src)) == 0);
5964: SET_NFLG (((uae_s8)(src)) < 0);
5965: put_byte(dsta,src);
5966: }}}}m68k_incpc(2);
5967: return 14;
5968: }
5969: unsigned long REGPARAM2 CPUFUNC(op_1128_0)(uae_u32 opcode) /* MOVE */
5970: {
5971: uae_u32 srcreg = (opcode & 7);
5972: uae_u32 dstreg = (opcode >> 9) & 7;
5973: OpcodeFamily = 30; CurrentInstrCycles = 16;
5974: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
5975: { uae_s8 src = get_byte(srca);
5976: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
5977: m68k_areg (regs, dstreg) = dsta;
5978: CLEAR_CZNV;
5979: SET_ZFLG (((uae_s8)(src)) == 0);
5980: SET_NFLG (((uae_s8)(src)) < 0);
5981: put_byte(dsta,src);
5982: }}}}m68k_incpc(4);
5983: return 16;
5984: }
5985: unsigned long REGPARAM2 CPUFUNC(op_1130_0)(uae_u32 opcode) /* MOVE */
5986: {
5987: uae_u32 srcreg = (opcode & 7);
5988: uae_u32 dstreg = (opcode >> 9) & 7;
5989: OpcodeFamily = 30; CurrentInstrCycles = 18;
5990: {{m68k_incpc(2);
5991: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
5992: BusCyclePenalty += 2;
5993: { uae_s8 src = get_byte(srca);
5994: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
5995: m68k_areg (regs, dstreg) = dsta;
5996: CLEAR_CZNV;
5997: SET_ZFLG (((uae_s8)(src)) == 0);
5998: SET_NFLG (((uae_s8)(src)) < 0);
5999: put_byte(dsta,src);
6000: }}}}}return 18;
6001: }
6002: unsigned long REGPARAM2 CPUFUNC(op_1138_0)(uae_u32 opcode) /* MOVE */
6003: {
6004: uae_u32 dstreg = (opcode >> 9) & 7;
6005: OpcodeFamily = 30; CurrentInstrCycles = 16;
6006: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
6007: { uae_s8 src = get_byte(srca);
6008: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
6009: m68k_areg (regs, dstreg) = dsta;
6010: CLEAR_CZNV;
6011: SET_ZFLG (((uae_s8)(src)) == 0);
6012: SET_NFLG (((uae_s8)(src)) < 0);
6013: put_byte(dsta,src);
6014: }}}}m68k_incpc(4);
6015: return 16;
6016: }
6017: unsigned long REGPARAM2 CPUFUNC(op_1139_0)(uae_u32 opcode) /* MOVE */
6018: {
6019: uae_u32 dstreg = (opcode >> 9) & 7;
6020: OpcodeFamily = 30; CurrentInstrCycles = 20;
6021: {{ uaecptr srca = get_ilong(2);
6022: { uae_s8 src = get_byte(srca);
6023: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
6024: m68k_areg (regs, dstreg) = dsta;
6025: CLEAR_CZNV;
6026: SET_ZFLG (((uae_s8)(src)) == 0);
6027: SET_NFLG (((uae_s8)(src)) < 0);
6028: put_byte(dsta,src);
6029: }}}}m68k_incpc(6);
6030: return 20;
6031: }
6032: unsigned long REGPARAM2 CPUFUNC(op_113a_0)(uae_u32 opcode) /* MOVE */
6033: {
6034: uae_u32 dstreg = (opcode >> 9) & 7;
6035: OpcodeFamily = 30; CurrentInstrCycles = 16;
6036: {{ uaecptr srca = m68k_getpc () + 2;
6037: srca += (uae_s32)(uae_s16)get_iword(2);
6038: { uae_s8 src = get_byte(srca);
6039: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
6040: m68k_areg (regs, dstreg) = dsta;
6041: CLEAR_CZNV;
6042: SET_ZFLG (((uae_s8)(src)) == 0);
6043: SET_NFLG (((uae_s8)(src)) < 0);
6044: put_byte(dsta,src);
6045: }}}}m68k_incpc(4);
6046: return 16;
6047: }
6048: unsigned long REGPARAM2 CPUFUNC(op_113b_0)(uae_u32 opcode) /* MOVE */
6049: {
6050: uae_u32 dstreg = (opcode >> 9) & 7;
6051: OpcodeFamily = 30; CurrentInstrCycles = 18;
6052: {{m68k_incpc(2);
6053: { uaecptr tmppc = m68k_getpc();
6054: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
6055: BusCyclePenalty += 2;
6056: { uae_s8 src = get_byte(srca);
6057: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
6058: m68k_areg (regs, dstreg) = dsta;
6059: CLEAR_CZNV;
6060: SET_ZFLG (((uae_s8)(src)) == 0);
6061: SET_NFLG (((uae_s8)(src)) < 0);
6062: put_byte(dsta,src);
6063: }}}}}return 18;
6064: }
6065: unsigned long REGPARAM2 CPUFUNC(op_113c_0)(uae_u32 opcode) /* MOVE */
6066: {
6067: uae_u32 dstreg = (opcode >> 9) & 7;
6068: OpcodeFamily = 30; CurrentInstrCycles = 12;
6069: {{ uae_s8 src = get_ibyte(2);
6070: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
6071: m68k_areg (regs, dstreg) = dsta;
6072: CLEAR_CZNV;
6073: SET_ZFLG (((uae_s8)(src)) == 0);
6074: SET_NFLG (((uae_s8)(src)) < 0);
6075: put_byte(dsta,src);
6076: }}}m68k_incpc(4);
6077: return 12;
6078: }
6079: unsigned long REGPARAM2 CPUFUNC(op_1140_0)(uae_u32 opcode) /* MOVE */
6080: {
6081: uae_u32 srcreg = (opcode & 7);
6082: uae_u32 dstreg = (opcode >> 9) & 7;
6083: OpcodeFamily = 30; CurrentInstrCycles = 12;
6084: {{ uae_s8 src = m68k_dreg(regs, srcreg);
6085: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
6086: CLEAR_CZNV;
6087: SET_ZFLG (((uae_s8)(src)) == 0);
6088: SET_NFLG (((uae_s8)(src)) < 0);
6089: put_byte(dsta,src);
6090: }}}m68k_incpc(4);
6091: return 12;
6092: }
6093: unsigned long REGPARAM2 CPUFUNC(op_1148_0)(uae_u32 opcode) /* MOVE */
6094: {
6095: uae_u32 srcreg = (opcode & 7);
6096: uae_u32 dstreg = (opcode >> 9) & 7;
6097: OpcodeFamily = 30; CurrentInstrCycles = 12;
6098: {{ uae_s8 src = m68k_areg(regs, srcreg);
6099: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
6100: CLEAR_CZNV;
6101: SET_ZFLG (((uae_s8)(src)) == 0);
6102: SET_NFLG (((uae_s8)(src)) < 0);
6103: put_byte(dsta,src);
6104: }}}m68k_incpc(4);
6105: return 12;
6106: }
6107: unsigned long REGPARAM2 CPUFUNC(op_1150_0)(uae_u32 opcode) /* MOVE */
6108: {
6109: uae_u32 srcreg = (opcode & 7);
6110: uae_u32 dstreg = (opcode >> 9) & 7;
6111: OpcodeFamily = 30; CurrentInstrCycles = 16;
6112: {{ uaecptr srca = m68k_areg(regs, srcreg);
6113: { uae_s8 src = get_byte(srca);
6114: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
6115: CLEAR_CZNV;
6116: SET_ZFLG (((uae_s8)(src)) == 0);
6117: SET_NFLG (((uae_s8)(src)) < 0);
6118: put_byte(dsta,src);
6119: }}}}m68k_incpc(4);
6120: return 16;
6121: }
6122: unsigned long REGPARAM2 CPUFUNC(op_1158_0)(uae_u32 opcode) /* MOVE */
6123: {
6124: uae_u32 srcreg = (opcode & 7);
6125: uae_u32 dstreg = (opcode >> 9) & 7;
6126: OpcodeFamily = 30; CurrentInstrCycles = 16;
6127: {{ uaecptr srca = m68k_areg(regs, srcreg);
6128: { uae_s8 src = get_byte(srca);
6129: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
6130: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
6131: CLEAR_CZNV;
6132: SET_ZFLG (((uae_s8)(src)) == 0);
6133: SET_NFLG (((uae_s8)(src)) < 0);
6134: put_byte(dsta,src);
6135: }}}}m68k_incpc(4);
6136: return 16;
6137: }
6138: unsigned long REGPARAM2 CPUFUNC(op_1160_0)(uae_u32 opcode) /* MOVE */
6139: {
6140: uae_u32 srcreg = (opcode & 7);
6141: uae_u32 dstreg = (opcode >> 9) & 7;
6142: OpcodeFamily = 30; CurrentInstrCycles = 18;
6143: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
6144: { uae_s8 src = get_byte(srca);
6145: m68k_areg (regs, srcreg) = srca;
6146: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
6147: CLEAR_CZNV;
6148: SET_ZFLG (((uae_s8)(src)) == 0);
6149: SET_NFLG (((uae_s8)(src)) < 0);
6150: put_byte(dsta,src);
6151: }}}}m68k_incpc(4);
6152: return 18;
6153: }
6154: unsigned long REGPARAM2 CPUFUNC(op_1168_0)(uae_u32 opcode) /* MOVE */
6155: {
6156: uae_u32 srcreg = (opcode & 7);
6157: uae_u32 dstreg = (opcode >> 9) & 7;
6158: OpcodeFamily = 30; CurrentInstrCycles = 20;
6159: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
6160: { uae_s8 src = get_byte(srca);
6161: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
6162: CLEAR_CZNV;
6163: SET_ZFLG (((uae_s8)(src)) == 0);
6164: SET_NFLG (((uae_s8)(src)) < 0);
6165: put_byte(dsta,src);
6166: }}}}m68k_incpc(6);
6167: return 20;
6168: }
6169: unsigned long REGPARAM2 CPUFUNC(op_1170_0)(uae_u32 opcode) /* MOVE */
6170: {
6171: uae_u32 srcreg = (opcode & 7);
6172: uae_u32 dstreg = (opcode >> 9) & 7;
6173: OpcodeFamily = 30; CurrentInstrCycles = 22;
6174: {{m68k_incpc(2);
6175: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
6176: BusCyclePenalty += 2;
6177: { uae_s8 src = get_byte(srca);
6178: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(0);
6179: CLEAR_CZNV;
6180: SET_ZFLG (((uae_s8)(src)) == 0);
6181: SET_NFLG (((uae_s8)(src)) < 0);
6182: put_byte(dsta,src);
6183: }}}}}m68k_incpc(2);
6184: return 22;
6185: }
6186: unsigned long REGPARAM2 CPUFUNC(op_1178_0)(uae_u32 opcode) /* MOVE */
6187: {
6188: uae_u32 dstreg = (opcode >> 9) & 7;
6189: OpcodeFamily = 30; CurrentInstrCycles = 20;
6190: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
6191: { uae_s8 src = get_byte(srca);
6192: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
6193: CLEAR_CZNV;
6194: SET_ZFLG (((uae_s8)(src)) == 0);
6195: SET_NFLG (((uae_s8)(src)) < 0);
6196: put_byte(dsta,src);
6197: }}}}m68k_incpc(6);
6198: return 20;
6199: }
6200: unsigned long REGPARAM2 CPUFUNC(op_1179_0)(uae_u32 opcode) /* MOVE */
6201: {
6202: uae_u32 dstreg = (opcode >> 9) & 7;
6203: OpcodeFamily = 30; CurrentInstrCycles = 24;
6204: {{ uaecptr srca = get_ilong(2);
6205: { uae_s8 src = get_byte(srca);
6206: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
6207: CLEAR_CZNV;
6208: SET_ZFLG (((uae_s8)(src)) == 0);
6209: SET_NFLG (((uae_s8)(src)) < 0);
6210: put_byte(dsta,src);
6211: }}}}m68k_incpc(8);
6212: return 24;
6213: }
6214: unsigned long REGPARAM2 CPUFUNC(op_117a_0)(uae_u32 opcode) /* MOVE */
6215: {
6216: uae_u32 dstreg = (opcode >> 9) & 7;
6217: OpcodeFamily = 30; CurrentInstrCycles = 20;
6218: {{ uaecptr srca = m68k_getpc () + 2;
6219: srca += (uae_s32)(uae_s16)get_iword(2);
6220: { uae_s8 src = get_byte(srca);
6221: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
6222: CLEAR_CZNV;
6223: SET_ZFLG (((uae_s8)(src)) == 0);
6224: SET_NFLG (((uae_s8)(src)) < 0);
6225: put_byte(dsta,src);
6226: }}}}m68k_incpc(6);
6227: return 20;
6228: }
6229: unsigned long REGPARAM2 CPUFUNC(op_117b_0)(uae_u32 opcode) /* MOVE */
6230: {
6231: uae_u32 dstreg = (opcode >> 9) & 7;
6232: OpcodeFamily = 30; CurrentInstrCycles = 22;
6233: {{m68k_incpc(2);
6234: { uaecptr tmppc = m68k_getpc();
6235: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
6236: BusCyclePenalty += 2;
6237: { uae_s8 src = get_byte(srca);
6238: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(0);
6239: CLEAR_CZNV;
6240: SET_ZFLG (((uae_s8)(src)) == 0);
6241: SET_NFLG (((uae_s8)(src)) < 0);
6242: put_byte(dsta,src);
6243: }}}}}m68k_incpc(2);
6244: return 22;
6245: }
6246: unsigned long REGPARAM2 CPUFUNC(op_117c_0)(uae_u32 opcode) /* MOVE */
6247: {
6248: uae_u32 dstreg = (opcode >> 9) & 7;
6249: OpcodeFamily = 30; CurrentInstrCycles = 16;
6250: {{ uae_s8 src = get_ibyte(2);
6251: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
6252: CLEAR_CZNV;
6253: SET_ZFLG (((uae_s8)(src)) == 0);
6254: SET_NFLG (((uae_s8)(src)) < 0);
6255: put_byte(dsta,src);
6256: }}}m68k_incpc(6);
6257: return 16;
6258: }
6259: unsigned long REGPARAM2 CPUFUNC(op_1180_0)(uae_u32 opcode) /* MOVE */
6260: {
6261: uae_u32 srcreg = (opcode & 7);
6262: uae_u32 dstreg = (opcode >> 9) & 7;
6263: OpcodeFamily = 30; CurrentInstrCycles = 14;
6264: {{ uae_s8 src = m68k_dreg(regs, srcreg);
6265: {m68k_incpc(2);
6266: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6267: BusCyclePenalty += 2;
6268: CLEAR_CZNV;
6269: SET_ZFLG (((uae_s8)(src)) == 0);
6270: SET_NFLG (((uae_s8)(src)) < 0);
6271: put_byte(dsta,src);
6272: }}}}return 14;
6273: }
6274: unsigned long REGPARAM2 CPUFUNC(op_1188_0)(uae_u32 opcode) /* MOVE */
6275: {
6276: uae_u32 srcreg = (opcode & 7);
6277: uae_u32 dstreg = (opcode >> 9) & 7;
6278: OpcodeFamily = 30; CurrentInstrCycles = 14;
6279: {{ uae_s8 src = m68k_areg(regs, srcreg);
6280: {m68k_incpc(2);
6281: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6282: BusCyclePenalty += 2;
6283: CLEAR_CZNV;
6284: SET_ZFLG (((uae_s8)(src)) == 0);
6285: SET_NFLG (((uae_s8)(src)) < 0);
6286: put_byte(dsta,src);
6287: }}}}return 14;
6288: }
6289: unsigned long REGPARAM2 CPUFUNC(op_1190_0)(uae_u32 opcode) /* MOVE */
6290: {
6291: uae_u32 srcreg = (opcode & 7);
6292: uae_u32 dstreg = (opcode >> 9) & 7;
6293: OpcodeFamily = 30; CurrentInstrCycles = 18;
6294: {{ uaecptr srca = m68k_areg(regs, srcreg);
6295: { uae_s8 src = get_byte(srca);
6296: {m68k_incpc(2);
6297: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6298: BusCyclePenalty += 2;
6299: CLEAR_CZNV;
6300: SET_ZFLG (((uae_s8)(src)) == 0);
6301: SET_NFLG (((uae_s8)(src)) < 0);
6302: put_byte(dsta,src);
6303: }}}}}return 18;
6304: }
6305: unsigned long REGPARAM2 CPUFUNC(op_1198_0)(uae_u32 opcode) /* MOVE */
6306: {
6307: uae_u32 srcreg = (opcode & 7);
6308: uae_u32 dstreg = (opcode >> 9) & 7;
6309: OpcodeFamily = 30; CurrentInstrCycles = 18;
6310: {{ uaecptr srca = m68k_areg(regs, srcreg);
6311: { uae_s8 src = get_byte(srca);
6312: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
6313: {m68k_incpc(2);
6314: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6315: BusCyclePenalty += 2;
6316: CLEAR_CZNV;
6317: SET_ZFLG (((uae_s8)(src)) == 0);
6318: SET_NFLG (((uae_s8)(src)) < 0);
6319: put_byte(dsta,src);
6320: }}}}}return 18;
6321: }
6322: unsigned long REGPARAM2 CPUFUNC(op_11a0_0)(uae_u32 opcode) /* MOVE */
6323: {
6324: uae_u32 srcreg = (opcode & 7);
6325: uae_u32 dstreg = (opcode >> 9) & 7;
6326: OpcodeFamily = 30; CurrentInstrCycles = 20;
6327: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
6328: { uae_s8 src = get_byte(srca);
6329: m68k_areg (regs, srcreg) = srca;
6330: {m68k_incpc(2);
6331: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6332: BusCyclePenalty += 2;
6333: CLEAR_CZNV;
6334: SET_ZFLG (((uae_s8)(src)) == 0);
6335: SET_NFLG (((uae_s8)(src)) < 0);
6336: put_byte(dsta,src);
6337: }}}}}return 20;
6338: }
6339: unsigned long REGPARAM2 CPUFUNC(op_11a8_0)(uae_u32 opcode) /* MOVE */
6340: {
6341: uae_u32 srcreg = (opcode & 7);
6342: uae_u32 dstreg = (opcode >> 9) & 7;
6343: OpcodeFamily = 30; CurrentInstrCycles = 22;
6344: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
6345: { uae_s8 src = get_byte(srca);
6346: {m68k_incpc(4);
6347: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6348: BusCyclePenalty += 2;
6349: CLEAR_CZNV;
6350: SET_ZFLG (((uae_s8)(src)) == 0);
6351: SET_NFLG (((uae_s8)(src)) < 0);
6352: put_byte(dsta,src);
6353: }}}}}return 22;
6354: }
6355: unsigned long REGPARAM2 CPUFUNC(op_11b0_0)(uae_u32 opcode) /* MOVE */
6356: {
6357: uae_u32 srcreg = (opcode & 7);
6358: uae_u32 dstreg = (opcode >> 9) & 7;
6359: OpcodeFamily = 30; CurrentInstrCycles = 24;
6360: {{m68k_incpc(2);
6361: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
6362: BusCyclePenalty += 2;
6363: { uae_s8 src = get_byte(srca);
6364: {{ uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6365: BusCyclePenalty += 2;
6366: CLEAR_CZNV;
6367: SET_ZFLG (((uae_s8)(src)) == 0);
6368: SET_NFLG (((uae_s8)(src)) < 0);
6369: put_byte(dsta,src);
6370: }}}}}}return 24;
6371: }
6372: unsigned long REGPARAM2 CPUFUNC(op_11b8_0)(uae_u32 opcode) /* MOVE */
6373: {
6374: uae_u32 dstreg = (opcode >> 9) & 7;
6375: OpcodeFamily = 30; CurrentInstrCycles = 22;
6376: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
6377: { uae_s8 src = get_byte(srca);
6378: {m68k_incpc(4);
6379: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6380: BusCyclePenalty += 2;
6381: CLEAR_CZNV;
6382: SET_ZFLG (((uae_s8)(src)) == 0);
6383: SET_NFLG (((uae_s8)(src)) < 0);
6384: put_byte(dsta,src);
6385: }}}}}return 22;
6386: }
6387: unsigned long REGPARAM2 CPUFUNC(op_11b9_0)(uae_u32 opcode) /* MOVE */
6388: {
6389: uae_u32 dstreg = (opcode >> 9) & 7;
6390: OpcodeFamily = 30; CurrentInstrCycles = 26;
6391: {{ uaecptr srca = get_ilong(2);
6392: { uae_s8 src = get_byte(srca);
6393: {m68k_incpc(6);
6394: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6395: BusCyclePenalty += 2;
6396: CLEAR_CZNV;
6397: SET_ZFLG (((uae_s8)(src)) == 0);
6398: SET_NFLG (((uae_s8)(src)) < 0);
6399: put_byte(dsta,src);
6400: }}}}}return 26;
6401: }
6402: unsigned long REGPARAM2 CPUFUNC(op_11ba_0)(uae_u32 opcode) /* MOVE */
6403: {
6404: uae_u32 dstreg = (opcode >> 9) & 7;
6405: OpcodeFamily = 30; CurrentInstrCycles = 22;
6406: {{ uaecptr srca = m68k_getpc () + 2;
6407: srca += (uae_s32)(uae_s16)get_iword(2);
6408: { uae_s8 src = get_byte(srca);
6409: {m68k_incpc(4);
6410: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6411: BusCyclePenalty += 2;
6412: CLEAR_CZNV;
6413: SET_ZFLG (((uae_s8)(src)) == 0);
6414: SET_NFLG (((uae_s8)(src)) < 0);
6415: put_byte(dsta,src);
6416: }}}}}return 22;
6417: }
6418: unsigned long REGPARAM2 CPUFUNC(op_11bb_0)(uae_u32 opcode) /* MOVE */
6419: {
6420: uae_u32 dstreg = (opcode >> 9) & 7;
6421: OpcodeFamily = 30; CurrentInstrCycles = 24;
6422: {{m68k_incpc(2);
6423: { uaecptr tmppc = m68k_getpc();
6424: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
6425: BusCyclePenalty += 2;
6426: { uae_s8 src = get_byte(srca);
6427: {{ uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6428: BusCyclePenalty += 2;
6429: CLEAR_CZNV;
6430: SET_ZFLG (((uae_s8)(src)) == 0);
6431: SET_NFLG (((uae_s8)(src)) < 0);
6432: put_byte(dsta,src);
6433: }}}}}}return 24;
6434: }
6435: unsigned long REGPARAM2 CPUFUNC(op_11bc_0)(uae_u32 opcode) /* MOVE */
6436: {
6437: uae_u32 dstreg = (opcode >> 9) & 7;
6438: OpcodeFamily = 30; CurrentInstrCycles = 18;
6439: {{ uae_s8 src = get_ibyte(2);
6440: {m68k_incpc(4);
6441: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
6442: BusCyclePenalty += 2;
6443: CLEAR_CZNV;
6444: SET_ZFLG (((uae_s8)(src)) == 0);
6445: SET_NFLG (((uae_s8)(src)) < 0);
6446: put_byte(dsta,src);
6447: }}}}return 18;
6448: }
6449: unsigned long REGPARAM2 CPUFUNC(op_11c0_0)(uae_u32 opcode) /* MOVE */
6450: {
6451: uae_u32 srcreg = (opcode & 7);
6452: OpcodeFamily = 30; CurrentInstrCycles = 12;
6453: {{ uae_s8 src = m68k_dreg(regs, srcreg);
6454: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
6455: CLEAR_CZNV;
6456: SET_ZFLG (((uae_s8)(src)) == 0);
6457: SET_NFLG (((uae_s8)(src)) < 0);
6458: put_byte(dsta,src);
6459: }}}m68k_incpc(4);
6460: return 12;
6461: }
6462: unsigned long REGPARAM2 CPUFUNC(op_11c8_0)(uae_u32 opcode) /* MOVE */
6463: {
6464: uae_u32 srcreg = (opcode & 7);
6465: OpcodeFamily = 30; CurrentInstrCycles = 12;
6466: {{ uae_s8 src = m68k_areg(regs, srcreg);
6467: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
6468: CLEAR_CZNV;
6469: SET_ZFLG (((uae_s8)(src)) == 0);
6470: SET_NFLG (((uae_s8)(src)) < 0);
6471: put_byte(dsta,src);
6472: }}}m68k_incpc(4);
6473: return 12;
6474: }
6475: unsigned long REGPARAM2 CPUFUNC(op_11d0_0)(uae_u32 opcode) /* MOVE */
6476: {
6477: uae_u32 srcreg = (opcode & 7);
6478: OpcodeFamily = 30; CurrentInstrCycles = 16;
6479: {{ uaecptr srca = m68k_areg(regs, srcreg);
6480: { uae_s8 src = get_byte(srca);
6481: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
6482: CLEAR_CZNV;
6483: SET_ZFLG (((uae_s8)(src)) == 0);
6484: SET_NFLG (((uae_s8)(src)) < 0);
6485: put_byte(dsta,src);
6486: }}}}m68k_incpc(4);
6487: return 16;
6488: }
6489: unsigned long REGPARAM2 CPUFUNC(op_11d8_0)(uae_u32 opcode) /* MOVE */
6490: {
6491: uae_u32 srcreg = (opcode & 7);
6492: OpcodeFamily = 30; CurrentInstrCycles = 16;
6493: {{ uaecptr srca = m68k_areg(regs, srcreg);
6494: { uae_s8 src = get_byte(srca);
6495: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
6496: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
6497: CLEAR_CZNV;
6498: SET_ZFLG (((uae_s8)(src)) == 0);
6499: SET_NFLG (((uae_s8)(src)) < 0);
6500: put_byte(dsta,src);
6501: }}}}m68k_incpc(4);
6502: return 16;
6503: }
6504: unsigned long REGPARAM2 CPUFUNC(op_11e0_0)(uae_u32 opcode) /* MOVE */
6505: {
6506: uae_u32 srcreg = (opcode & 7);
6507: OpcodeFamily = 30; CurrentInstrCycles = 18;
6508: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
6509: { uae_s8 src = get_byte(srca);
6510: m68k_areg (regs, srcreg) = srca;
6511: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
6512: CLEAR_CZNV;
6513: SET_ZFLG (((uae_s8)(src)) == 0);
6514: SET_NFLG (((uae_s8)(src)) < 0);
6515: put_byte(dsta,src);
6516: }}}}m68k_incpc(4);
6517: return 18;
6518: }
6519: unsigned long REGPARAM2 CPUFUNC(op_11e8_0)(uae_u32 opcode) /* MOVE */
6520: {
6521: uae_u32 srcreg = (opcode & 7);
6522: OpcodeFamily = 30; CurrentInstrCycles = 20;
6523: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
6524: { uae_s8 src = get_byte(srca);
6525: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
6526: CLEAR_CZNV;
6527: SET_ZFLG (((uae_s8)(src)) == 0);
6528: SET_NFLG (((uae_s8)(src)) < 0);
6529: put_byte(dsta,src);
6530: }}}}m68k_incpc(6);
6531: return 20;
6532: }
6533: unsigned long REGPARAM2 CPUFUNC(op_11f0_0)(uae_u32 opcode) /* MOVE */
6534: {
6535: uae_u32 srcreg = (opcode & 7);
6536: OpcodeFamily = 30; CurrentInstrCycles = 22;
6537: {{m68k_incpc(2);
6538: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
6539: BusCyclePenalty += 2;
6540: { uae_s8 src = get_byte(srca);
6541: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(0);
6542: CLEAR_CZNV;
6543: SET_ZFLG (((uae_s8)(src)) == 0);
6544: SET_NFLG (((uae_s8)(src)) < 0);
6545: put_byte(dsta,src);
6546: }}}}}m68k_incpc(2);
6547: return 22;
6548: }
6549: unsigned long REGPARAM2 CPUFUNC(op_11f8_0)(uae_u32 opcode) /* MOVE */
6550: {
6551: OpcodeFamily = 30; CurrentInstrCycles = 20;
6552: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
6553: { uae_s8 src = get_byte(srca);
6554: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
6555: CLEAR_CZNV;
6556: SET_ZFLG (((uae_s8)(src)) == 0);
6557: SET_NFLG (((uae_s8)(src)) < 0);
6558: put_byte(dsta,src);
6559: }}}}m68k_incpc(6);
6560: return 20;
6561: }
6562: unsigned long REGPARAM2 CPUFUNC(op_11f9_0)(uae_u32 opcode) /* MOVE */
6563: {
6564: OpcodeFamily = 30; CurrentInstrCycles = 24;
6565: {{ uaecptr srca = get_ilong(2);
6566: { uae_s8 src = get_byte(srca);
6567: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
6568: CLEAR_CZNV;
6569: SET_ZFLG (((uae_s8)(src)) == 0);
6570: SET_NFLG (((uae_s8)(src)) < 0);
6571: put_byte(dsta,src);
6572: }}}}m68k_incpc(8);
6573: return 24;
6574: }
6575: unsigned long REGPARAM2 CPUFUNC(op_11fa_0)(uae_u32 opcode) /* MOVE */
6576: {
6577: OpcodeFamily = 30; CurrentInstrCycles = 20;
6578: {{ uaecptr srca = m68k_getpc () + 2;
6579: srca += (uae_s32)(uae_s16)get_iword(2);
6580: { uae_s8 src = get_byte(srca);
6581: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
6582: CLEAR_CZNV;
6583: SET_ZFLG (((uae_s8)(src)) == 0);
6584: SET_NFLG (((uae_s8)(src)) < 0);
6585: put_byte(dsta,src);
6586: }}}}m68k_incpc(6);
6587: return 20;
6588: }
6589: unsigned long REGPARAM2 CPUFUNC(op_11fb_0)(uae_u32 opcode) /* MOVE */
6590: {
6591: OpcodeFamily = 30; CurrentInstrCycles = 22;
6592: {{m68k_incpc(2);
6593: { uaecptr tmppc = m68k_getpc();
6594: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
6595: BusCyclePenalty += 2;
6596: { uae_s8 src = get_byte(srca);
6597: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(0);
6598: CLEAR_CZNV;
6599: SET_ZFLG (((uae_s8)(src)) == 0);
6600: SET_NFLG (((uae_s8)(src)) < 0);
6601: put_byte(dsta,src);
6602: }}}}}m68k_incpc(2);
6603: return 22;
6604: }
6605: unsigned long REGPARAM2 CPUFUNC(op_11fc_0)(uae_u32 opcode) /* MOVE */
6606: {
6607: OpcodeFamily = 30; CurrentInstrCycles = 16;
6608: {{ uae_s8 src = get_ibyte(2);
6609: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
6610: CLEAR_CZNV;
6611: SET_ZFLG (((uae_s8)(src)) == 0);
6612: SET_NFLG (((uae_s8)(src)) < 0);
6613: put_byte(dsta,src);
6614: }}}m68k_incpc(6);
6615: return 16;
6616: }
6617: unsigned long REGPARAM2 CPUFUNC(op_13c0_0)(uae_u32 opcode) /* MOVE */
6618: {
6619: uae_u32 srcreg = (opcode & 7);
6620: OpcodeFamily = 30; CurrentInstrCycles = 16;
6621: {{ uae_s8 src = m68k_dreg(regs, srcreg);
6622: { uaecptr dsta = get_ilong(2);
6623: CLEAR_CZNV;
6624: SET_ZFLG (((uae_s8)(src)) == 0);
6625: SET_NFLG (((uae_s8)(src)) < 0);
6626: put_byte(dsta,src);
6627: }}}m68k_incpc(6);
6628: return 16;
6629: }
6630: unsigned long REGPARAM2 CPUFUNC(op_13c8_0)(uae_u32 opcode) /* MOVE */
6631: {
6632: uae_u32 srcreg = (opcode & 7);
6633: OpcodeFamily = 30; CurrentInstrCycles = 16;
6634: {{ uae_s8 src = m68k_areg(regs, srcreg);
6635: { uaecptr dsta = get_ilong(2);
6636: CLEAR_CZNV;
6637: SET_ZFLG (((uae_s8)(src)) == 0);
6638: SET_NFLG (((uae_s8)(src)) < 0);
6639: put_byte(dsta,src);
6640: }}}m68k_incpc(6);
6641: return 16;
6642: }
6643: unsigned long REGPARAM2 CPUFUNC(op_13d0_0)(uae_u32 opcode) /* MOVE */
6644: {
6645: uae_u32 srcreg = (opcode & 7);
6646: OpcodeFamily = 30; CurrentInstrCycles = 20;
6647: {{ uaecptr srca = m68k_areg(regs, srcreg);
6648: { uae_s8 src = get_byte(srca);
6649: { uaecptr dsta = get_ilong(2);
6650: CLEAR_CZNV;
6651: SET_ZFLG (((uae_s8)(src)) == 0);
6652: SET_NFLG (((uae_s8)(src)) < 0);
6653: put_byte(dsta,src);
6654: }}}}m68k_incpc(6);
6655: return 20;
6656: }
6657: unsigned long REGPARAM2 CPUFUNC(op_13d8_0)(uae_u32 opcode) /* MOVE */
6658: {
6659: uae_u32 srcreg = (opcode & 7);
6660: OpcodeFamily = 30; CurrentInstrCycles = 20;
6661: {{ uaecptr srca = m68k_areg(regs, srcreg);
6662: { uae_s8 src = get_byte(srca);
6663: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
6664: { uaecptr dsta = get_ilong(2);
6665: CLEAR_CZNV;
6666: SET_ZFLG (((uae_s8)(src)) == 0);
6667: SET_NFLG (((uae_s8)(src)) < 0);
6668: put_byte(dsta,src);
6669: }}}}m68k_incpc(6);
6670: return 20;
6671: }
6672: unsigned long REGPARAM2 CPUFUNC(op_13e0_0)(uae_u32 opcode) /* MOVE */
6673: {
6674: uae_u32 srcreg = (opcode & 7);
6675: OpcodeFamily = 30; CurrentInstrCycles = 22;
6676: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
6677: { uae_s8 src = get_byte(srca);
6678: m68k_areg (regs, srcreg) = srca;
6679: { uaecptr dsta = get_ilong(2);
6680: CLEAR_CZNV;
6681: SET_ZFLG (((uae_s8)(src)) == 0);
6682: SET_NFLG (((uae_s8)(src)) < 0);
6683: put_byte(dsta,src);
6684: }}}}m68k_incpc(6);
6685: return 22;
6686: }
6687: unsigned long REGPARAM2 CPUFUNC(op_13e8_0)(uae_u32 opcode) /* MOVE */
6688: {
6689: uae_u32 srcreg = (opcode & 7);
6690: OpcodeFamily = 30; CurrentInstrCycles = 24;
6691: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
6692: { uae_s8 src = get_byte(srca);
6693: { uaecptr dsta = get_ilong(4);
6694: CLEAR_CZNV;
6695: SET_ZFLG (((uae_s8)(src)) == 0);
6696: SET_NFLG (((uae_s8)(src)) < 0);
6697: put_byte(dsta,src);
6698: }}}}m68k_incpc(8);
6699: return 24;
6700: }
6701: unsigned long REGPARAM2 CPUFUNC(op_13f0_0)(uae_u32 opcode) /* MOVE */
6702: {
6703: uae_u32 srcreg = (opcode & 7);
6704: OpcodeFamily = 30; CurrentInstrCycles = 26;
6705: {{m68k_incpc(2);
6706: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
6707: BusCyclePenalty += 2;
6708: { uae_s8 src = get_byte(srca);
6709: { uaecptr dsta = get_ilong(0);
6710: CLEAR_CZNV;
6711: SET_ZFLG (((uae_s8)(src)) == 0);
6712: SET_NFLG (((uae_s8)(src)) < 0);
6713: put_byte(dsta,src);
6714: }}}}}m68k_incpc(4);
6715: return 26;
6716: }
6717: unsigned long REGPARAM2 CPUFUNC(op_13f8_0)(uae_u32 opcode) /* MOVE */
6718: {
6719: OpcodeFamily = 30; CurrentInstrCycles = 24;
6720: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
6721: { uae_s8 src = get_byte(srca);
6722: { uaecptr dsta = get_ilong(4);
6723: CLEAR_CZNV;
6724: SET_ZFLG (((uae_s8)(src)) == 0);
6725: SET_NFLG (((uae_s8)(src)) < 0);
6726: put_byte(dsta,src);
6727: }}}}m68k_incpc(8);
6728: return 24;
6729: }
6730: unsigned long REGPARAM2 CPUFUNC(op_13f9_0)(uae_u32 opcode) /* MOVE */
6731: {
6732: OpcodeFamily = 30; CurrentInstrCycles = 28;
6733: {{ uaecptr srca = get_ilong(2);
6734: { uae_s8 src = get_byte(srca);
6735: { uaecptr dsta = get_ilong(6);
6736: CLEAR_CZNV;
6737: SET_ZFLG (((uae_s8)(src)) == 0);
6738: SET_NFLG (((uae_s8)(src)) < 0);
6739: put_byte(dsta,src);
6740: }}}}m68k_incpc(10);
6741: return 28;
6742: }
6743: unsigned long REGPARAM2 CPUFUNC(op_13fa_0)(uae_u32 opcode) /* MOVE */
6744: {
6745: OpcodeFamily = 30; CurrentInstrCycles = 24;
6746: {{ uaecptr srca = m68k_getpc () + 2;
6747: srca += (uae_s32)(uae_s16)get_iword(2);
6748: { uae_s8 src = get_byte(srca);
6749: { uaecptr dsta = get_ilong(4);
6750: CLEAR_CZNV;
6751: SET_ZFLG (((uae_s8)(src)) == 0);
6752: SET_NFLG (((uae_s8)(src)) < 0);
6753: put_byte(dsta,src);
6754: }}}}m68k_incpc(8);
6755: return 24;
6756: }
6757: unsigned long REGPARAM2 CPUFUNC(op_13fb_0)(uae_u32 opcode) /* MOVE */
6758: {
6759: OpcodeFamily = 30; CurrentInstrCycles = 26;
6760: {{m68k_incpc(2);
6761: { uaecptr tmppc = m68k_getpc();
6762: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
6763: BusCyclePenalty += 2;
6764: { uae_s8 src = get_byte(srca);
6765: { uaecptr dsta = get_ilong(0);
6766: CLEAR_CZNV;
6767: SET_ZFLG (((uae_s8)(src)) == 0);
6768: SET_NFLG (((uae_s8)(src)) < 0);
6769: put_byte(dsta,src);
6770: }}}}}m68k_incpc(4);
6771: return 26;
6772: }
6773: unsigned long REGPARAM2 CPUFUNC(op_13fc_0)(uae_u32 opcode) /* MOVE */
6774: {
6775: OpcodeFamily = 30; CurrentInstrCycles = 20;
6776: {{ uae_s8 src = get_ibyte(2);
6777: { uaecptr dsta = get_ilong(4);
6778: CLEAR_CZNV;
6779: SET_ZFLG (((uae_s8)(src)) == 0);
6780: SET_NFLG (((uae_s8)(src)) < 0);
6781: put_byte(dsta,src);
6782: }}}m68k_incpc(8);
6783: return 20;
6784: }
6785: unsigned long REGPARAM2 CPUFUNC(op_2000_0)(uae_u32 opcode) /* MOVE */
6786: {
6787: uae_u32 srcreg = (opcode & 7);
6788: uae_u32 dstreg = (opcode >> 9) & 7;
6789: OpcodeFamily = 30; CurrentInstrCycles = 4;
6790: {{ uae_s32 src = m68k_dreg(regs, srcreg);
6791: { CLEAR_CZNV;
6792: SET_ZFLG (((uae_s32)(src)) == 0);
6793: SET_NFLG (((uae_s32)(src)) < 0);
6794: m68k_dreg(regs, dstreg) = (src);
6795: }}}m68k_incpc(2);
6796: return 4;
6797: }
6798: unsigned long REGPARAM2 CPUFUNC(op_2008_0)(uae_u32 opcode) /* MOVE */
6799: {
6800: uae_u32 srcreg = (opcode & 7);
6801: uae_u32 dstreg = (opcode >> 9) & 7;
6802: OpcodeFamily = 30; CurrentInstrCycles = 4;
6803: {{ uae_s32 src = m68k_areg(regs, srcreg);
6804: { CLEAR_CZNV;
6805: SET_ZFLG (((uae_s32)(src)) == 0);
6806: SET_NFLG (((uae_s32)(src)) < 0);
6807: m68k_dreg(regs, dstreg) = (src);
6808: }}}m68k_incpc(2);
6809: return 4;
6810: }
6811: unsigned long REGPARAM2 CPUFUNC(op_2010_0)(uae_u32 opcode) /* MOVE */
6812: {
6813: uae_u32 srcreg = (opcode & 7);
6814: uae_u32 dstreg = (opcode >> 9) & 7;
6815: OpcodeFamily = 30; CurrentInstrCycles = 12;
6816: {{ uaecptr srca = m68k_areg(regs, srcreg);
6817: { uae_s32 src = get_long(srca);
6818: { CLEAR_CZNV;
6819: SET_ZFLG (((uae_s32)(src)) == 0);
6820: SET_NFLG (((uae_s32)(src)) < 0);
6821: m68k_dreg(regs, dstreg) = (src);
6822: }}}}m68k_incpc(2);
6823: return 12;
6824: }
6825: unsigned long REGPARAM2 CPUFUNC(op_2018_0)(uae_u32 opcode) /* MOVE */
6826: {
6827: uae_u32 srcreg = (opcode & 7);
6828: uae_u32 dstreg = (opcode >> 9) & 7;
6829: OpcodeFamily = 30; CurrentInstrCycles = 12;
6830: {{ uaecptr srca = m68k_areg(regs, srcreg);
6831: { uae_s32 src = get_long(srca);
6832: m68k_areg(regs, srcreg) += 4;
6833: { CLEAR_CZNV;
6834: SET_ZFLG (((uae_s32)(src)) == 0);
6835: SET_NFLG (((uae_s32)(src)) < 0);
6836: m68k_dreg(regs, dstreg) = (src);
6837: }}}}m68k_incpc(2);
6838: return 12;
6839: }
6840: unsigned long REGPARAM2 CPUFUNC(op_2020_0)(uae_u32 opcode) /* MOVE */
6841: {
6842: uae_u32 srcreg = (opcode & 7);
6843: uae_u32 dstreg = (opcode >> 9) & 7;
6844: OpcodeFamily = 30; CurrentInstrCycles = 14;
6845: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
6846: { uae_s32 src = get_long(srca);
6847: m68k_areg (regs, srcreg) = srca;
6848: { CLEAR_CZNV;
6849: SET_ZFLG (((uae_s32)(src)) == 0);
6850: SET_NFLG (((uae_s32)(src)) < 0);
6851: m68k_dreg(regs, dstreg) = (src);
6852: }}}}m68k_incpc(2);
6853: return 14;
6854: }
6855: unsigned long REGPARAM2 CPUFUNC(op_2028_0)(uae_u32 opcode) /* MOVE */
6856: {
6857: uae_u32 srcreg = (opcode & 7);
6858: uae_u32 dstreg = (opcode >> 9) & 7;
6859: OpcodeFamily = 30; CurrentInstrCycles = 16;
6860: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
6861: { uae_s32 src = get_long(srca);
6862: { CLEAR_CZNV;
6863: SET_ZFLG (((uae_s32)(src)) == 0);
6864: SET_NFLG (((uae_s32)(src)) < 0);
6865: m68k_dreg(regs, dstreg) = (src);
6866: }}}}m68k_incpc(4);
6867: return 16;
6868: }
6869: unsigned long REGPARAM2 CPUFUNC(op_2030_0)(uae_u32 opcode) /* MOVE */
6870: {
6871: uae_u32 srcreg = (opcode & 7);
6872: uae_u32 dstreg = (opcode >> 9) & 7;
6873: OpcodeFamily = 30; CurrentInstrCycles = 18;
6874: {{m68k_incpc(2);
6875: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
6876: BusCyclePenalty += 2;
6877: { uae_s32 src = get_long(srca);
6878: { CLEAR_CZNV;
6879: SET_ZFLG (((uae_s32)(src)) == 0);
6880: SET_NFLG (((uae_s32)(src)) < 0);
6881: m68k_dreg(regs, dstreg) = (src);
6882: }}}}}return 18;
6883: }
6884: unsigned long REGPARAM2 CPUFUNC(op_2038_0)(uae_u32 opcode) /* MOVE */
6885: {
6886: uae_u32 dstreg = (opcode >> 9) & 7;
6887: OpcodeFamily = 30; CurrentInstrCycles = 16;
6888: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
6889: { uae_s32 src = get_long(srca);
6890: { CLEAR_CZNV;
6891: SET_ZFLG (((uae_s32)(src)) == 0);
6892: SET_NFLG (((uae_s32)(src)) < 0);
6893: m68k_dreg(regs, dstreg) = (src);
6894: }}}}m68k_incpc(4);
6895: return 16;
6896: }
6897: unsigned long REGPARAM2 CPUFUNC(op_2039_0)(uae_u32 opcode) /* MOVE */
6898: {
6899: uae_u32 dstreg = (opcode >> 9) & 7;
6900: OpcodeFamily = 30; CurrentInstrCycles = 20;
6901: {{ uaecptr srca = get_ilong(2);
6902: { uae_s32 src = get_long(srca);
6903: { CLEAR_CZNV;
6904: SET_ZFLG (((uae_s32)(src)) == 0);
6905: SET_NFLG (((uae_s32)(src)) < 0);
6906: m68k_dreg(regs, dstreg) = (src);
6907: }}}}m68k_incpc(6);
6908: return 20;
6909: }
6910: unsigned long REGPARAM2 CPUFUNC(op_203a_0)(uae_u32 opcode) /* MOVE */
6911: {
6912: uae_u32 dstreg = (opcode >> 9) & 7;
6913: OpcodeFamily = 30; CurrentInstrCycles = 16;
6914: {{ uaecptr srca = m68k_getpc () + 2;
6915: srca += (uae_s32)(uae_s16)get_iword(2);
6916: { uae_s32 src = get_long(srca);
6917: { CLEAR_CZNV;
6918: SET_ZFLG (((uae_s32)(src)) == 0);
6919: SET_NFLG (((uae_s32)(src)) < 0);
6920: m68k_dreg(regs, dstreg) = (src);
6921: }}}}m68k_incpc(4);
6922: return 16;
6923: }
6924: unsigned long REGPARAM2 CPUFUNC(op_203b_0)(uae_u32 opcode) /* MOVE */
6925: {
6926: uae_u32 dstreg = (opcode >> 9) & 7;
6927: OpcodeFamily = 30; CurrentInstrCycles = 18;
6928: {{m68k_incpc(2);
6929: { uaecptr tmppc = m68k_getpc();
6930: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
6931: BusCyclePenalty += 2;
6932: { uae_s32 src = get_long(srca);
6933: { CLEAR_CZNV;
6934: SET_ZFLG (((uae_s32)(src)) == 0);
6935: SET_NFLG (((uae_s32)(src)) < 0);
6936: m68k_dreg(regs, dstreg) = (src);
6937: }}}}}return 18;
6938: }
6939: unsigned long REGPARAM2 CPUFUNC(op_203c_0)(uae_u32 opcode) /* MOVE */
6940: {
6941: uae_u32 dstreg = (opcode >> 9) & 7;
6942: OpcodeFamily = 30; CurrentInstrCycles = 12;
6943: {{ uae_s32 src = get_ilong(2);
6944: { CLEAR_CZNV;
6945: SET_ZFLG (((uae_s32)(src)) == 0);
6946: SET_NFLG (((uae_s32)(src)) < 0);
6947: m68k_dreg(regs, dstreg) = (src);
6948: }}}m68k_incpc(6);
6949: return 12;
6950: }
6951: unsigned long REGPARAM2 CPUFUNC(op_2040_0)(uae_u32 opcode) /* MOVEA */
6952: {
6953: uae_u32 srcreg = (opcode & 7);
6954: uae_u32 dstreg = (opcode >> 9) & 7;
6955: OpcodeFamily = 31; CurrentInstrCycles = 4;
6956: {{ uae_s32 src = m68k_dreg(regs, srcreg);
6957: { uae_u32 val = src;
6958: m68k_areg(regs, dstreg) = (val);
6959: }}}m68k_incpc(2);
6960: return 4;
6961: }
6962: unsigned long REGPARAM2 CPUFUNC(op_2048_0)(uae_u32 opcode) /* MOVEA */
6963: {
6964: uae_u32 srcreg = (opcode & 7);
6965: uae_u32 dstreg = (opcode >> 9) & 7;
6966: OpcodeFamily = 31; CurrentInstrCycles = 4;
6967: {{ uae_s32 src = m68k_areg(regs, srcreg);
6968: { uae_u32 val = src;
6969: m68k_areg(regs, dstreg) = (val);
6970: }}}m68k_incpc(2);
6971: return 4;
6972: }
6973: unsigned long REGPARAM2 CPUFUNC(op_2050_0)(uae_u32 opcode) /* MOVEA */
6974: {
6975: uae_u32 srcreg = (opcode & 7);
6976: uae_u32 dstreg = (opcode >> 9) & 7;
6977: OpcodeFamily = 31; CurrentInstrCycles = 12;
6978: {{ uaecptr srca = m68k_areg(regs, srcreg);
6979: { uae_s32 src = get_long(srca);
6980: { uae_u32 val = src;
6981: m68k_areg(regs, dstreg) = (val);
6982: }}}}m68k_incpc(2);
6983: return 12;
6984: }
6985: unsigned long REGPARAM2 CPUFUNC(op_2058_0)(uae_u32 opcode) /* MOVEA */
6986: {
6987: uae_u32 srcreg = (opcode & 7);
6988: uae_u32 dstreg = (opcode >> 9) & 7;
6989: OpcodeFamily = 31; CurrentInstrCycles = 12;
6990: {{ uaecptr srca = m68k_areg(regs, srcreg);
6991: { uae_s32 src = get_long(srca);
6992: m68k_areg(regs, srcreg) += 4;
6993: { uae_u32 val = src;
6994: m68k_areg(regs, dstreg) = (val);
6995: }}}}m68k_incpc(2);
6996: return 12;
6997: }
6998: unsigned long REGPARAM2 CPUFUNC(op_2060_0)(uae_u32 opcode) /* MOVEA */
6999: {
7000: uae_u32 srcreg = (opcode & 7);
7001: uae_u32 dstreg = (opcode >> 9) & 7;
7002: OpcodeFamily = 31; CurrentInstrCycles = 14;
7003: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
7004: { uae_s32 src = get_long(srca);
7005: m68k_areg (regs, srcreg) = srca;
7006: { uae_u32 val = src;
7007: m68k_areg(regs, dstreg) = (val);
7008: }}}}m68k_incpc(2);
7009: return 14;
7010: }
7011: unsigned long REGPARAM2 CPUFUNC(op_2068_0)(uae_u32 opcode) /* MOVEA */
7012: {
7013: uae_u32 srcreg = (opcode & 7);
7014: uae_u32 dstreg = (opcode >> 9) & 7;
7015: OpcodeFamily = 31; CurrentInstrCycles = 16;
7016: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
7017: { uae_s32 src = get_long(srca);
7018: { uae_u32 val = src;
7019: m68k_areg(regs, dstreg) = (val);
7020: }}}}m68k_incpc(4);
7021: return 16;
7022: }
7023: unsigned long REGPARAM2 CPUFUNC(op_2070_0)(uae_u32 opcode) /* MOVEA */
7024: {
7025: uae_u32 srcreg = (opcode & 7);
7026: uae_u32 dstreg = (opcode >> 9) & 7;
7027: OpcodeFamily = 31; CurrentInstrCycles = 18;
7028: {{m68k_incpc(2);
7029: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
7030: BusCyclePenalty += 2;
7031: { uae_s32 src = get_long(srca);
7032: { uae_u32 val = src;
7033: m68k_areg(regs, dstreg) = (val);
7034: }}}}}return 18;
7035: }
7036: unsigned long REGPARAM2 CPUFUNC(op_2078_0)(uae_u32 opcode) /* MOVEA */
7037: {
7038: uae_u32 dstreg = (opcode >> 9) & 7;
7039: OpcodeFamily = 31; CurrentInstrCycles = 16;
7040: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
7041: { uae_s32 src = get_long(srca);
7042: { uae_u32 val = src;
7043: m68k_areg(regs, dstreg) = (val);
7044: }}}}m68k_incpc(4);
7045: return 16;
7046: }
7047: unsigned long REGPARAM2 CPUFUNC(op_2079_0)(uae_u32 opcode) /* MOVEA */
7048: {
7049: uae_u32 dstreg = (opcode >> 9) & 7;
7050: OpcodeFamily = 31; CurrentInstrCycles = 20;
7051: {{ uaecptr srca = get_ilong(2);
7052: { uae_s32 src = get_long(srca);
7053: { uae_u32 val = src;
7054: m68k_areg(regs, dstreg) = (val);
7055: }}}}m68k_incpc(6);
7056: return 20;
7057: }
7058: unsigned long REGPARAM2 CPUFUNC(op_207a_0)(uae_u32 opcode) /* MOVEA */
7059: {
7060: uae_u32 dstreg = (opcode >> 9) & 7;
7061: OpcodeFamily = 31; CurrentInstrCycles = 16;
7062: {{ uaecptr srca = m68k_getpc () + 2;
7063: srca += (uae_s32)(uae_s16)get_iword(2);
7064: { uae_s32 src = get_long(srca);
7065: { uae_u32 val = src;
7066: m68k_areg(regs, dstreg) = (val);
7067: }}}}m68k_incpc(4);
7068: return 16;
7069: }
7070: unsigned long REGPARAM2 CPUFUNC(op_207b_0)(uae_u32 opcode) /* MOVEA */
7071: {
7072: uae_u32 dstreg = (opcode >> 9) & 7;
7073: OpcodeFamily = 31; CurrentInstrCycles = 18;
7074: {{m68k_incpc(2);
7075: { uaecptr tmppc = m68k_getpc();
7076: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
7077: BusCyclePenalty += 2;
7078: { uae_s32 src = get_long(srca);
7079: { uae_u32 val = src;
7080: m68k_areg(regs, dstreg) = (val);
7081: }}}}}return 18;
7082: }
7083: unsigned long REGPARAM2 CPUFUNC(op_207c_0)(uae_u32 opcode) /* MOVEA */
7084: {
7085: uae_u32 dstreg = (opcode >> 9) & 7;
7086: OpcodeFamily = 31; CurrentInstrCycles = 12;
7087: {{ uae_s32 src = get_ilong(2);
7088: { uae_u32 val = src;
7089: m68k_areg(regs, dstreg) = (val);
7090: }}}m68k_incpc(6);
7091: return 12;
7092: }
7093: unsigned long REGPARAM2 CPUFUNC(op_2080_0)(uae_u32 opcode) /* MOVE */
7094: {
7095: uae_u32 srcreg = (opcode & 7);
7096: uae_u32 dstreg = (opcode >> 9) & 7;
7097: OpcodeFamily = 30; CurrentInstrCycles = 12;
7098: {{ uae_s32 src = m68k_dreg(regs, srcreg);
7099: { uaecptr dsta = m68k_areg(regs, dstreg);
7100: CLEAR_CZNV;
7101: SET_ZFLG (((uae_s32)(src)) == 0);
7102: SET_NFLG (((uae_s32)(src)) < 0);
7103: put_long(dsta,src);
7104: }}}m68k_incpc(2);
7105: return 12;
7106: }
7107: unsigned long REGPARAM2 CPUFUNC(op_2088_0)(uae_u32 opcode) /* MOVE */
7108: {
7109: uae_u32 srcreg = (opcode & 7);
7110: uae_u32 dstreg = (opcode >> 9) & 7;
7111: OpcodeFamily = 30; CurrentInstrCycles = 12;
7112: {{ uae_s32 src = m68k_areg(regs, srcreg);
7113: { uaecptr dsta = m68k_areg(regs, dstreg);
7114: CLEAR_CZNV;
7115: SET_ZFLG (((uae_s32)(src)) == 0);
7116: SET_NFLG (((uae_s32)(src)) < 0);
7117: put_long(dsta,src);
7118: }}}m68k_incpc(2);
7119: return 12;
7120: }
7121: unsigned long REGPARAM2 CPUFUNC(op_2090_0)(uae_u32 opcode) /* MOVE */
7122: {
7123: uae_u32 srcreg = (opcode & 7);
7124: uae_u32 dstreg = (opcode >> 9) & 7;
7125: OpcodeFamily = 30; CurrentInstrCycles = 20;
7126: {{ uaecptr srca = m68k_areg(regs, srcreg);
7127: { uae_s32 src = get_long(srca);
7128: { uaecptr dsta = m68k_areg(regs, dstreg);
7129: CLEAR_CZNV;
7130: SET_ZFLG (((uae_s32)(src)) == 0);
7131: SET_NFLG (((uae_s32)(src)) < 0);
7132: put_long(dsta,src);
7133: }}}}m68k_incpc(2);
7134: return 20;
7135: }
7136: unsigned long REGPARAM2 CPUFUNC(op_2098_0)(uae_u32 opcode) /* MOVE */
7137: {
7138: uae_u32 srcreg = (opcode & 7);
7139: uae_u32 dstreg = (opcode >> 9) & 7;
7140: OpcodeFamily = 30; CurrentInstrCycles = 20;
7141: {{ uaecptr srca = m68k_areg(regs, srcreg);
7142: { uae_s32 src = get_long(srca);
7143: m68k_areg(regs, srcreg) += 4;
7144: { uaecptr dsta = m68k_areg(regs, dstreg);
7145: CLEAR_CZNV;
7146: SET_ZFLG (((uae_s32)(src)) == 0);
7147: SET_NFLG (((uae_s32)(src)) < 0);
7148: put_long(dsta,src);
7149: }}}}m68k_incpc(2);
7150: return 20;
7151: }
7152: unsigned long REGPARAM2 CPUFUNC(op_20a0_0)(uae_u32 opcode) /* MOVE */
7153: {
7154: uae_u32 srcreg = (opcode & 7);
7155: uae_u32 dstreg = (opcode >> 9) & 7;
7156: OpcodeFamily = 30; CurrentInstrCycles = 22;
7157: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
7158: { uae_s32 src = get_long(srca);
7159: m68k_areg (regs, srcreg) = srca;
7160: { uaecptr dsta = m68k_areg(regs, dstreg);
7161: CLEAR_CZNV;
7162: SET_ZFLG (((uae_s32)(src)) == 0);
7163: SET_NFLG (((uae_s32)(src)) < 0);
7164: put_long(dsta,src);
7165: }}}}m68k_incpc(2);
7166: return 22;
7167: }
7168: unsigned long REGPARAM2 CPUFUNC(op_20a8_0)(uae_u32 opcode) /* MOVE */
7169: {
7170: uae_u32 srcreg = (opcode & 7);
7171: uae_u32 dstreg = (opcode >> 9) & 7;
7172: OpcodeFamily = 30; CurrentInstrCycles = 24;
7173: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
7174: { uae_s32 src = get_long(srca);
7175: { uaecptr dsta = m68k_areg(regs, dstreg);
7176: CLEAR_CZNV;
7177: SET_ZFLG (((uae_s32)(src)) == 0);
7178: SET_NFLG (((uae_s32)(src)) < 0);
7179: put_long(dsta,src);
7180: }}}}m68k_incpc(4);
7181: return 24;
7182: }
7183: unsigned long REGPARAM2 CPUFUNC(op_20b0_0)(uae_u32 opcode) /* MOVE */
7184: {
7185: uae_u32 srcreg = (opcode & 7);
7186: uae_u32 dstreg = (opcode >> 9) & 7;
7187: OpcodeFamily = 30; CurrentInstrCycles = 26;
7188: {{m68k_incpc(2);
7189: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
7190: BusCyclePenalty += 2;
7191: { uae_s32 src = get_long(srca);
7192: { uaecptr dsta = m68k_areg(regs, dstreg);
7193: CLEAR_CZNV;
7194: SET_ZFLG (((uae_s32)(src)) == 0);
7195: SET_NFLG (((uae_s32)(src)) < 0);
7196: put_long(dsta,src);
7197: }}}}}return 26;
7198: }
7199: unsigned long REGPARAM2 CPUFUNC(op_20b8_0)(uae_u32 opcode) /* MOVE */
7200: {
7201: uae_u32 dstreg = (opcode >> 9) & 7;
7202: OpcodeFamily = 30; CurrentInstrCycles = 24;
7203: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
7204: { uae_s32 src = get_long(srca);
7205: { uaecptr dsta = m68k_areg(regs, dstreg);
7206: CLEAR_CZNV;
7207: SET_ZFLG (((uae_s32)(src)) == 0);
7208: SET_NFLG (((uae_s32)(src)) < 0);
7209: put_long(dsta,src);
7210: }}}}m68k_incpc(4);
7211: return 24;
7212: }
7213: unsigned long REGPARAM2 CPUFUNC(op_20b9_0)(uae_u32 opcode) /* MOVE */
7214: {
7215: uae_u32 dstreg = (opcode >> 9) & 7;
7216: OpcodeFamily = 30; CurrentInstrCycles = 28;
7217: {{ uaecptr srca = get_ilong(2);
7218: { uae_s32 src = get_long(srca);
7219: { uaecptr dsta = m68k_areg(regs, dstreg);
7220: CLEAR_CZNV;
7221: SET_ZFLG (((uae_s32)(src)) == 0);
7222: SET_NFLG (((uae_s32)(src)) < 0);
7223: put_long(dsta,src);
7224: }}}}m68k_incpc(6);
7225: return 28;
7226: }
7227: unsigned long REGPARAM2 CPUFUNC(op_20ba_0)(uae_u32 opcode) /* MOVE */
7228: {
7229: uae_u32 dstreg = (opcode >> 9) & 7;
7230: OpcodeFamily = 30; CurrentInstrCycles = 24;
7231: {{ uaecptr srca = m68k_getpc () + 2;
7232: srca += (uae_s32)(uae_s16)get_iword(2);
7233: { uae_s32 src = get_long(srca);
7234: { uaecptr dsta = m68k_areg(regs, dstreg);
7235: CLEAR_CZNV;
7236: SET_ZFLG (((uae_s32)(src)) == 0);
7237: SET_NFLG (((uae_s32)(src)) < 0);
7238: put_long(dsta,src);
7239: }}}}m68k_incpc(4);
7240: return 24;
7241: }
7242: unsigned long REGPARAM2 CPUFUNC(op_20bb_0)(uae_u32 opcode) /* MOVE */
7243: {
7244: uae_u32 dstreg = (opcode >> 9) & 7;
7245: OpcodeFamily = 30; CurrentInstrCycles = 26;
7246: {{m68k_incpc(2);
7247: { uaecptr tmppc = m68k_getpc();
7248: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
7249: BusCyclePenalty += 2;
7250: { uae_s32 src = get_long(srca);
7251: { uaecptr dsta = m68k_areg(regs, dstreg);
7252: CLEAR_CZNV;
7253: SET_ZFLG (((uae_s32)(src)) == 0);
7254: SET_NFLG (((uae_s32)(src)) < 0);
7255: put_long(dsta,src);
7256: }}}}}return 26;
7257: }
7258: unsigned long REGPARAM2 CPUFUNC(op_20bc_0)(uae_u32 opcode) /* MOVE */
7259: {
7260: uae_u32 dstreg = (opcode >> 9) & 7;
7261: OpcodeFamily = 30; CurrentInstrCycles = 20;
7262: {{ uae_s32 src = get_ilong(2);
7263: { uaecptr dsta = m68k_areg(regs, dstreg);
7264: CLEAR_CZNV;
7265: SET_ZFLG (((uae_s32)(src)) == 0);
7266: SET_NFLG (((uae_s32)(src)) < 0);
7267: put_long(dsta,src);
7268: }}}m68k_incpc(6);
7269: return 20;
7270: }
7271: unsigned long REGPARAM2 CPUFUNC(op_20c0_0)(uae_u32 opcode) /* MOVE */
7272: {
7273: uae_u32 srcreg = (opcode & 7);
7274: uae_u32 dstreg = (opcode >> 9) & 7;
7275: OpcodeFamily = 30; CurrentInstrCycles = 12;
7276: {{ uae_s32 src = m68k_dreg(regs, srcreg);
7277: { uaecptr dsta = m68k_areg(regs, dstreg);
7278: m68k_areg(regs, dstreg) += 4;
7279: CLEAR_CZNV;
7280: SET_ZFLG (((uae_s32)(src)) == 0);
7281: SET_NFLG (((uae_s32)(src)) < 0);
7282: put_long(dsta,src);
7283: }}}m68k_incpc(2);
7284: return 12;
7285: }
7286: unsigned long REGPARAM2 CPUFUNC(op_20c8_0)(uae_u32 opcode) /* MOVE */
7287: {
7288: uae_u32 srcreg = (opcode & 7);
7289: uae_u32 dstreg = (opcode >> 9) & 7;
7290: OpcodeFamily = 30; CurrentInstrCycles = 12;
7291: {{ uae_s32 src = m68k_areg(regs, srcreg);
7292: { uaecptr dsta = m68k_areg(regs, dstreg);
7293: m68k_areg(regs, dstreg) += 4;
7294: CLEAR_CZNV;
7295: SET_ZFLG (((uae_s32)(src)) == 0);
7296: SET_NFLG (((uae_s32)(src)) < 0);
7297: put_long(dsta,src);
7298: }}}m68k_incpc(2);
7299: return 12;
7300: }
7301: unsigned long REGPARAM2 CPUFUNC(op_20d0_0)(uae_u32 opcode) /* MOVE */
7302: {
7303: uae_u32 srcreg = (opcode & 7);
7304: uae_u32 dstreg = (opcode >> 9) & 7;
7305: OpcodeFamily = 30; CurrentInstrCycles = 20;
7306: {{ uaecptr srca = m68k_areg(regs, srcreg);
7307: { uae_s32 src = get_long(srca);
7308: { uaecptr dsta = m68k_areg(regs, dstreg);
7309: m68k_areg(regs, dstreg) += 4;
7310: CLEAR_CZNV;
7311: SET_ZFLG (((uae_s32)(src)) == 0);
7312: SET_NFLG (((uae_s32)(src)) < 0);
7313: put_long(dsta,src);
7314: }}}}m68k_incpc(2);
7315: return 20;
7316: }
7317: unsigned long REGPARAM2 CPUFUNC(op_20d8_0)(uae_u32 opcode) /* MOVE */
7318: {
7319: uae_u32 srcreg = (opcode & 7);
7320: uae_u32 dstreg = (opcode >> 9) & 7;
7321: OpcodeFamily = 30; CurrentInstrCycles = 20;
7322: {{ uaecptr srca = m68k_areg(regs, srcreg);
7323: { uae_s32 src = get_long(srca);
7324: m68k_areg(regs, srcreg) += 4;
7325: { uaecptr dsta = m68k_areg(regs, dstreg);
7326: m68k_areg(regs, dstreg) += 4;
7327: CLEAR_CZNV;
7328: SET_ZFLG (((uae_s32)(src)) == 0);
7329: SET_NFLG (((uae_s32)(src)) < 0);
7330: put_long(dsta,src);
7331: }}}}m68k_incpc(2);
7332: return 20;
7333: }
7334: unsigned long REGPARAM2 CPUFUNC(op_20e0_0)(uae_u32 opcode) /* MOVE */
7335: {
7336: uae_u32 srcreg = (opcode & 7);
7337: uae_u32 dstreg = (opcode >> 9) & 7;
7338: OpcodeFamily = 30; CurrentInstrCycles = 22;
7339: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
7340: { uae_s32 src = get_long(srca);
7341: m68k_areg (regs, srcreg) = srca;
7342: { uaecptr dsta = m68k_areg(regs, dstreg);
7343: m68k_areg(regs, dstreg) += 4;
7344: CLEAR_CZNV;
7345: SET_ZFLG (((uae_s32)(src)) == 0);
7346: SET_NFLG (((uae_s32)(src)) < 0);
7347: put_long(dsta,src);
7348: }}}}m68k_incpc(2);
7349: return 22;
7350: }
7351: unsigned long REGPARAM2 CPUFUNC(op_20e8_0)(uae_u32 opcode) /* MOVE */
7352: {
7353: uae_u32 srcreg = (opcode & 7);
7354: uae_u32 dstreg = (opcode >> 9) & 7;
7355: OpcodeFamily = 30; CurrentInstrCycles = 24;
7356: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
7357: { uae_s32 src = get_long(srca);
7358: { uaecptr dsta = m68k_areg(regs, dstreg);
7359: m68k_areg(regs, dstreg) += 4;
7360: CLEAR_CZNV;
7361: SET_ZFLG (((uae_s32)(src)) == 0);
7362: SET_NFLG (((uae_s32)(src)) < 0);
7363: put_long(dsta,src);
7364: }}}}m68k_incpc(4);
7365: return 24;
7366: }
7367: unsigned long REGPARAM2 CPUFUNC(op_20f0_0)(uae_u32 opcode) /* MOVE */
7368: {
7369: uae_u32 srcreg = (opcode & 7);
7370: uae_u32 dstreg = (opcode >> 9) & 7;
7371: OpcodeFamily = 30; CurrentInstrCycles = 26;
7372: {{m68k_incpc(2);
7373: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
7374: BusCyclePenalty += 2;
7375: { uae_s32 src = get_long(srca);
7376: { uaecptr dsta = m68k_areg(regs, dstreg);
7377: m68k_areg(regs, dstreg) += 4;
7378: CLEAR_CZNV;
7379: SET_ZFLG (((uae_s32)(src)) == 0);
7380: SET_NFLG (((uae_s32)(src)) < 0);
7381: put_long(dsta,src);
7382: }}}}}return 26;
7383: }
7384: unsigned long REGPARAM2 CPUFUNC(op_20f8_0)(uae_u32 opcode) /* MOVE */
7385: {
7386: uae_u32 dstreg = (opcode >> 9) & 7;
7387: OpcodeFamily = 30; CurrentInstrCycles = 24;
7388: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
7389: { uae_s32 src = get_long(srca);
7390: { uaecptr dsta = m68k_areg(regs, dstreg);
7391: m68k_areg(regs, dstreg) += 4;
7392: CLEAR_CZNV;
7393: SET_ZFLG (((uae_s32)(src)) == 0);
7394: SET_NFLG (((uae_s32)(src)) < 0);
7395: put_long(dsta,src);
7396: }}}}m68k_incpc(4);
7397: return 24;
7398: }
7399: unsigned long REGPARAM2 CPUFUNC(op_20f9_0)(uae_u32 opcode) /* MOVE */
7400: {
7401: uae_u32 dstreg = (opcode >> 9) & 7;
7402: OpcodeFamily = 30; CurrentInstrCycles = 28;
7403: {{ uaecptr srca = get_ilong(2);
7404: { uae_s32 src = get_long(srca);
7405: { uaecptr dsta = m68k_areg(regs, dstreg);
7406: m68k_areg(regs, dstreg) += 4;
7407: CLEAR_CZNV;
7408: SET_ZFLG (((uae_s32)(src)) == 0);
7409: SET_NFLG (((uae_s32)(src)) < 0);
7410: put_long(dsta,src);
7411: }}}}m68k_incpc(6);
7412: return 28;
7413: }
7414: unsigned long REGPARAM2 CPUFUNC(op_20fa_0)(uae_u32 opcode) /* MOVE */
7415: {
7416: uae_u32 dstreg = (opcode >> 9) & 7;
7417: OpcodeFamily = 30; CurrentInstrCycles = 24;
7418: {{ uaecptr srca = m68k_getpc () + 2;
7419: srca += (uae_s32)(uae_s16)get_iword(2);
7420: { uae_s32 src = get_long(srca);
7421: { uaecptr dsta = m68k_areg(regs, dstreg);
7422: m68k_areg(regs, dstreg) += 4;
7423: CLEAR_CZNV;
7424: SET_ZFLG (((uae_s32)(src)) == 0);
7425: SET_NFLG (((uae_s32)(src)) < 0);
7426: put_long(dsta,src);
7427: }}}}m68k_incpc(4);
7428: return 24;
7429: }
7430: unsigned long REGPARAM2 CPUFUNC(op_20fb_0)(uae_u32 opcode) /* MOVE */
7431: {
7432: uae_u32 dstreg = (opcode >> 9) & 7;
7433: OpcodeFamily = 30; CurrentInstrCycles = 26;
7434: {{m68k_incpc(2);
7435: { uaecptr tmppc = m68k_getpc();
7436: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
7437: BusCyclePenalty += 2;
7438: { uae_s32 src = get_long(srca);
7439: { uaecptr dsta = m68k_areg(regs, dstreg);
7440: m68k_areg(regs, dstreg) += 4;
7441: CLEAR_CZNV;
7442: SET_ZFLG (((uae_s32)(src)) == 0);
7443: SET_NFLG (((uae_s32)(src)) < 0);
7444: put_long(dsta,src);
7445: }}}}}return 26;
7446: }
7447: unsigned long REGPARAM2 CPUFUNC(op_20fc_0)(uae_u32 opcode) /* MOVE */
7448: {
7449: uae_u32 dstreg = (opcode >> 9) & 7;
7450: OpcodeFamily = 30; CurrentInstrCycles = 20;
7451: {{ uae_s32 src = get_ilong(2);
7452: { uaecptr dsta = m68k_areg(regs, dstreg);
7453: m68k_areg(regs, dstreg) += 4;
7454: CLEAR_CZNV;
7455: SET_ZFLG (((uae_s32)(src)) == 0);
7456: SET_NFLG (((uae_s32)(src)) < 0);
7457: put_long(dsta,src);
7458: }}}m68k_incpc(6);
7459: return 20;
7460: }
7461: unsigned long REGPARAM2 CPUFUNC(op_2100_0)(uae_u32 opcode) /* MOVE */
7462: {
7463: uae_u32 srcreg = (opcode & 7);
7464: uae_u32 dstreg = (opcode >> 9) & 7;
7465: OpcodeFamily = 30; CurrentInstrCycles = 12;
7466: {{ uae_s32 src = m68k_dreg(regs, srcreg);
7467: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7468: m68k_areg (regs, dstreg) = dsta;
7469: CLEAR_CZNV;
7470: SET_ZFLG (((uae_s32)(src)) == 0);
7471: SET_NFLG (((uae_s32)(src)) < 0);
7472: put_long(dsta,src);
7473: }}}m68k_incpc(2);
7474: return 12;
7475: }
7476: unsigned long REGPARAM2 CPUFUNC(op_2108_0)(uae_u32 opcode) /* MOVE */
7477: {
7478: uae_u32 srcreg = (opcode & 7);
7479: uae_u32 dstreg = (opcode >> 9) & 7;
7480: OpcodeFamily = 30; CurrentInstrCycles = 12;
7481: {{ uae_s32 src = m68k_areg(regs, srcreg);
7482: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7483: m68k_areg (regs, dstreg) = dsta;
7484: CLEAR_CZNV;
7485: SET_ZFLG (((uae_s32)(src)) == 0);
7486: SET_NFLG (((uae_s32)(src)) < 0);
7487: put_long(dsta,src);
7488: }}}m68k_incpc(2);
7489: return 12;
7490: }
7491: unsigned long REGPARAM2 CPUFUNC(op_2110_0)(uae_u32 opcode) /* MOVE */
7492: {
7493: uae_u32 srcreg = (opcode & 7);
7494: uae_u32 dstreg = (opcode >> 9) & 7;
7495: OpcodeFamily = 30; CurrentInstrCycles = 20;
7496: {{ uaecptr srca = m68k_areg(regs, srcreg);
7497: { uae_s32 src = get_long(srca);
7498: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7499: m68k_areg (regs, dstreg) = dsta;
7500: CLEAR_CZNV;
7501: SET_ZFLG (((uae_s32)(src)) == 0);
7502: SET_NFLG (((uae_s32)(src)) < 0);
7503: put_long(dsta,src);
7504: }}}}m68k_incpc(2);
7505: return 20;
7506: }
7507: unsigned long REGPARAM2 CPUFUNC(op_2118_0)(uae_u32 opcode) /* MOVE */
7508: {
7509: uae_u32 srcreg = (opcode & 7);
7510: uae_u32 dstreg = (opcode >> 9) & 7;
7511: OpcodeFamily = 30; CurrentInstrCycles = 20;
7512: {{ uaecptr srca = m68k_areg(regs, srcreg);
7513: { uae_s32 src = get_long(srca);
7514: m68k_areg(regs, srcreg) += 4;
7515: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7516: m68k_areg (regs, dstreg) = dsta;
7517: CLEAR_CZNV;
7518: SET_ZFLG (((uae_s32)(src)) == 0);
7519: SET_NFLG (((uae_s32)(src)) < 0);
7520: put_long(dsta,src);
7521: }}}}m68k_incpc(2);
7522: return 20;
7523: }
7524: unsigned long REGPARAM2 CPUFUNC(op_2120_0)(uae_u32 opcode) /* MOVE */
7525: {
7526: uae_u32 srcreg = (opcode & 7);
7527: uae_u32 dstreg = (opcode >> 9) & 7;
7528: OpcodeFamily = 30; CurrentInstrCycles = 22;
7529: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
7530: { uae_s32 src = get_long(srca);
7531: m68k_areg (regs, srcreg) = srca;
7532: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7533: m68k_areg (regs, dstreg) = dsta;
7534: CLEAR_CZNV;
7535: SET_ZFLG (((uae_s32)(src)) == 0);
7536: SET_NFLG (((uae_s32)(src)) < 0);
7537: put_long(dsta,src);
7538: }}}}m68k_incpc(2);
7539: return 22;
7540: }
7541: unsigned long REGPARAM2 CPUFUNC(op_2128_0)(uae_u32 opcode) /* MOVE */
7542: {
7543: uae_u32 srcreg = (opcode & 7);
7544: uae_u32 dstreg = (opcode >> 9) & 7;
7545: OpcodeFamily = 30; CurrentInstrCycles = 24;
7546: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
7547: { uae_s32 src = get_long(srca);
7548: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7549: m68k_areg (regs, dstreg) = dsta;
7550: CLEAR_CZNV;
7551: SET_ZFLG (((uae_s32)(src)) == 0);
7552: SET_NFLG (((uae_s32)(src)) < 0);
7553: put_long(dsta,src);
7554: }}}}m68k_incpc(4);
7555: return 24;
7556: }
7557: unsigned long REGPARAM2 CPUFUNC(op_2130_0)(uae_u32 opcode) /* MOVE */
7558: {
7559: uae_u32 srcreg = (opcode & 7);
7560: uae_u32 dstreg = (opcode >> 9) & 7;
7561: OpcodeFamily = 30; CurrentInstrCycles = 26;
7562: {{m68k_incpc(2);
7563: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
7564: BusCyclePenalty += 2;
7565: { uae_s32 src = get_long(srca);
7566: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7567: m68k_areg (regs, dstreg) = dsta;
7568: CLEAR_CZNV;
7569: SET_ZFLG (((uae_s32)(src)) == 0);
7570: SET_NFLG (((uae_s32)(src)) < 0);
7571: put_long(dsta,src);
7572: }}}}}return 26;
7573: }
7574: unsigned long REGPARAM2 CPUFUNC(op_2138_0)(uae_u32 opcode) /* MOVE */
7575: {
7576: uae_u32 dstreg = (opcode >> 9) & 7;
7577: OpcodeFamily = 30; CurrentInstrCycles = 24;
7578: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
7579: { uae_s32 src = get_long(srca);
7580: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7581: m68k_areg (regs, dstreg) = dsta;
7582: CLEAR_CZNV;
7583: SET_ZFLG (((uae_s32)(src)) == 0);
7584: SET_NFLG (((uae_s32)(src)) < 0);
7585: put_long(dsta,src);
7586: }}}}m68k_incpc(4);
7587: return 24;
7588: }
7589: #endif
7590:
7591: #ifdef PART_3
7592: unsigned long REGPARAM2 CPUFUNC(op_2139_0)(uae_u32 opcode) /* MOVE */
7593: {
7594: uae_u32 dstreg = (opcode >> 9) & 7;
7595: OpcodeFamily = 30; CurrentInstrCycles = 28;
7596: {{ uaecptr srca = get_ilong(2);
7597: { uae_s32 src = get_long(srca);
7598: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7599: m68k_areg (regs, dstreg) = dsta;
7600: CLEAR_CZNV;
7601: SET_ZFLG (((uae_s32)(src)) == 0);
7602: SET_NFLG (((uae_s32)(src)) < 0);
7603: put_long(dsta,src);
7604: }}}}m68k_incpc(6);
7605: return 28;
7606: }
7607: unsigned long REGPARAM2 CPUFUNC(op_213a_0)(uae_u32 opcode) /* MOVE */
7608: {
7609: uae_u32 dstreg = (opcode >> 9) & 7;
7610: OpcodeFamily = 30; CurrentInstrCycles = 24;
7611: {{ uaecptr srca = m68k_getpc () + 2;
7612: srca += (uae_s32)(uae_s16)get_iword(2);
7613: { uae_s32 src = get_long(srca);
7614: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7615: m68k_areg (regs, dstreg) = dsta;
7616: CLEAR_CZNV;
7617: SET_ZFLG (((uae_s32)(src)) == 0);
7618: SET_NFLG (((uae_s32)(src)) < 0);
7619: put_long(dsta,src);
7620: }}}}m68k_incpc(4);
7621: return 24;
7622: }
7623: unsigned long REGPARAM2 CPUFUNC(op_213b_0)(uae_u32 opcode) /* MOVE */
7624: {
7625: uae_u32 dstreg = (opcode >> 9) & 7;
7626: OpcodeFamily = 30; CurrentInstrCycles = 26;
7627: {{m68k_incpc(2);
7628: { uaecptr tmppc = m68k_getpc();
7629: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
7630: BusCyclePenalty += 2;
7631: { uae_s32 src = get_long(srca);
7632: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7633: m68k_areg (regs, dstreg) = dsta;
7634: CLEAR_CZNV;
7635: SET_ZFLG (((uae_s32)(src)) == 0);
7636: SET_NFLG (((uae_s32)(src)) < 0);
7637: put_long(dsta,src);
7638: }}}}}return 26;
7639: }
7640: unsigned long REGPARAM2 CPUFUNC(op_213c_0)(uae_u32 opcode) /* MOVE */
7641: {
7642: uae_u32 dstreg = (opcode >> 9) & 7;
7643: OpcodeFamily = 30; CurrentInstrCycles = 20;
7644: {{ uae_s32 src = get_ilong(2);
7645: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
7646: m68k_areg (regs, dstreg) = dsta;
7647: CLEAR_CZNV;
7648: SET_ZFLG (((uae_s32)(src)) == 0);
7649: SET_NFLG (((uae_s32)(src)) < 0);
7650: put_long(dsta,src);
7651: }}}m68k_incpc(6);
7652: return 20;
7653: }
7654: unsigned long REGPARAM2 CPUFUNC(op_2140_0)(uae_u32 opcode) /* MOVE */
7655: {
7656: uae_u32 srcreg = (opcode & 7);
7657: uae_u32 dstreg = (opcode >> 9) & 7;
7658: OpcodeFamily = 30; CurrentInstrCycles = 16;
7659: {{ uae_s32 src = m68k_dreg(regs, srcreg);
7660: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
7661: CLEAR_CZNV;
7662: SET_ZFLG (((uae_s32)(src)) == 0);
7663: SET_NFLG (((uae_s32)(src)) < 0);
7664: put_long(dsta,src);
7665: }}}m68k_incpc(4);
7666: return 16;
7667: }
7668: unsigned long REGPARAM2 CPUFUNC(op_2148_0)(uae_u32 opcode) /* MOVE */
7669: {
7670: uae_u32 srcreg = (opcode & 7);
7671: uae_u32 dstreg = (opcode >> 9) & 7;
7672: OpcodeFamily = 30; CurrentInstrCycles = 16;
7673: {{ uae_s32 src = m68k_areg(regs, srcreg);
7674: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
7675: CLEAR_CZNV;
7676: SET_ZFLG (((uae_s32)(src)) == 0);
7677: SET_NFLG (((uae_s32)(src)) < 0);
7678: put_long(dsta,src);
7679: }}}m68k_incpc(4);
7680: return 16;
7681: }
7682: unsigned long REGPARAM2 CPUFUNC(op_2150_0)(uae_u32 opcode) /* MOVE */
7683: {
7684: uae_u32 srcreg = (opcode & 7);
7685: uae_u32 dstreg = (opcode >> 9) & 7;
7686: OpcodeFamily = 30; CurrentInstrCycles = 24;
7687: {{ uaecptr srca = m68k_areg(regs, srcreg);
7688: { uae_s32 src = get_long(srca);
7689: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
7690: CLEAR_CZNV;
7691: SET_ZFLG (((uae_s32)(src)) == 0);
7692: SET_NFLG (((uae_s32)(src)) < 0);
7693: put_long(dsta,src);
7694: }}}}m68k_incpc(4);
7695: return 24;
7696: }
7697: unsigned long REGPARAM2 CPUFUNC(op_2158_0)(uae_u32 opcode) /* MOVE */
7698: {
7699: uae_u32 srcreg = (opcode & 7);
7700: uae_u32 dstreg = (opcode >> 9) & 7;
7701: OpcodeFamily = 30; CurrentInstrCycles = 24;
7702: {{ uaecptr srca = m68k_areg(regs, srcreg);
7703: { uae_s32 src = get_long(srca);
7704: m68k_areg(regs, srcreg) += 4;
7705: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
7706: CLEAR_CZNV;
7707: SET_ZFLG (((uae_s32)(src)) == 0);
7708: SET_NFLG (((uae_s32)(src)) < 0);
7709: put_long(dsta,src);
7710: }}}}m68k_incpc(4);
7711: return 24;
7712: }
7713: unsigned long REGPARAM2 CPUFUNC(op_2160_0)(uae_u32 opcode) /* MOVE */
7714: {
7715: uae_u32 srcreg = (opcode & 7);
7716: uae_u32 dstreg = (opcode >> 9) & 7;
7717: OpcodeFamily = 30; CurrentInstrCycles = 26;
7718: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
7719: { uae_s32 src = get_long(srca);
7720: m68k_areg (regs, srcreg) = srca;
7721: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
7722: CLEAR_CZNV;
7723: SET_ZFLG (((uae_s32)(src)) == 0);
7724: SET_NFLG (((uae_s32)(src)) < 0);
7725: put_long(dsta,src);
7726: }}}}m68k_incpc(4);
7727: return 26;
7728: }
7729: unsigned long REGPARAM2 CPUFUNC(op_2168_0)(uae_u32 opcode) /* MOVE */
7730: {
7731: uae_u32 srcreg = (opcode & 7);
7732: uae_u32 dstreg = (opcode >> 9) & 7;
7733: OpcodeFamily = 30; CurrentInstrCycles = 28;
7734: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
7735: { uae_s32 src = get_long(srca);
7736: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
7737: CLEAR_CZNV;
7738: SET_ZFLG (((uae_s32)(src)) == 0);
7739: SET_NFLG (((uae_s32)(src)) < 0);
7740: put_long(dsta,src);
7741: }}}}m68k_incpc(6);
7742: return 28;
7743: }
7744: unsigned long REGPARAM2 CPUFUNC(op_2170_0)(uae_u32 opcode) /* MOVE */
7745: {
7746: uae_u32 srcreg = (opcode & 7);
7747: uae_u32 dstreg = (opcode >> 9) & 7;
7748: OpcodeFamily = 30; CurrentInstrCycles = 30;
7749: {{m68k_incpc(2);
7750: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
7751: BusCyclePenalty += 2;
7752: { uae_s32 src = get_long(srca);
7753: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(0);
7754: CLEAR_CZNV;
7755: SET_ZFLG (((uae_s32)(src)) == 0);
7756: SET_NFLG (((uae_s32)(src)) < 0);
7757: put_long(dsta,src);
7758: }}}}}m68k_incpc(2);
7759: return 30;
7760: }
7761: unsigned long REGPARAM2 CPUFUNC(op_2178_0)(uae_u32 opcode) /* MOVE */
7762: {
7763: uae_u32 dstreg = (opcode >> 9) & 7;
7764: OpcodeFamily = 30; CurrentInstrCycles = 28;
7765: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
7766: { uae_s32 src = get_long(srca);
7767: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
7768: CLEAR_CZNV;
7769: SET_ZFLG (((uae_s32)(src)) == 0);
7770: SET_NFLG (((uae_s32)(src)) < 0);
7771: put_long(dsta,src);
7772: }}}}m68k_incpc(6);
7773: return 28;
7774: }
7775: unsigned long REGPARAM2 CPUFUNC(op_2179_0)(uae_u32 opcode) /* MOVE */
7776: {
7777: uae_u32 dstreg = (opcode >> 9) & 7;
7778: OpcodeFamily = 30; CurrentInstrCycles = 32;
7779: {{ uaecptr srca = get_ilong(2);
7780: { uae_s32 src = get_long(srca);
7781: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
7782: CLEAR_CZNV;
7783: SET_ZFLG (((uae_s32)(src)) == 0);
7784: SET_NFLG (((uae_s32)(src)) < 0);
7785: put_long(dsta,src);
7786: }}}}m68k_incpc(8);
7787: return 32;
7788: }
7789: unsigned long REGPARAM2 CPUFUNC(op_217a_0)(uae_u32 opcode) /* MOVE */
7790: {
7791: uae_u32 dstreg = (opcode >> 9) & 7;
7792: OpcodeFamily = 30; CurrentInstrCycles = 28;
7793: {{ uaecptr srca = m68k_getpc () + 2;
7794: srca += (uae_s32)(uae_s16)get_iword(2);
7795: { uae_s32 src = get_long(srca);
7796: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
7797: CLEAR_CZNV;
7798: SET_ZFLG (((uae_s32)(src)) == 0);
7799: SET_NFLG (((uae_s32)(src)) < 0);
7800: put_long(dsta,src);
7801: }}}}m68k_incpc(6);
7802: return 28;
7803: }
7804: unsigned long REGPARAM2 CPUFUNC(op_217b_0)(uae_u32 opcode) /* MOVE */
7805: {
7806: uae_u32 dstreg = (opcode >> 9) & 7;
7807: OpcodeFamily = 30; CurrentInstrCycles = 30;
7808: {{m68k_incpc(2);
7809: { uaecptr tmppc = m68k_getpc();
7810: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
7811: BusCyclePenalty += 2;
7812: { uae_s32 src = get_long(srca);
7813: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(0);
7814: CLEAR_CZNV;
7815: SET_ZFLG (((uae_s32)(src)) == 0);
7816: SET_NFLG (((uae_s32)(src)) < 0);
7817: put_long(dsta,src);
7818: }}}}}m68k_incpc(2);
7819: return 30;
7820: }
7821: unsigned long REGPARAM2 CPUFUNC(op_217c_0)(uae_u32 opcode) /* MOVE */
7822: {
7823: uae_u32 dstreg = (opcode >> 9) & 7;
7824: OpcodeFamily = 30; CurrentInstrCycles = 24;
7825: {{ uae_s32 src = get_ilong(2);
7826: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
7827: CLEAR_CZNV;
7828: SET_ZFLG (((uae_s32)(src)) == 0);
7829: SET_NFLG (((uae_s32)(src)) < 0);
7830: put_long(dsta,src);
7831: }}}m68k_incpc(8);
7832: return 24;
7833: }
7834: unsigned long REGPARAM2 CPUFUNC(op_2180_0)(uae_u32 opcode) /* MOVE */
7835: {
7836: uae_u32 srcreg = (opcode & 7);
7837: uae_u32 dstreg = (opcode >> 9) & 7;
7838: OpcodeFamily = 30; CurrentInstrCycles = 18;
7839: {{ uae_s32 src = m68k_dreg(regs, srcreg);
7840: {m68k_incpc(2);
7841: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7842: BusCyclePenalty += 2;
7843: CLEAR_CZNV;
7844: SET_ZFLG (((uae_s32)(src)) == 0);
7845: SET_NFLG (((uae_s32)(src)) < 0);
7846: put_long(dsta,src);
7847: }}}}return 18;
7848: }
7849: unsigned long REGPARAM2 CPUFUNC(op_2188_0)(uae_u32 opcode) /* MOVE */
7850: {
7851: uae_u32 srcreg = (opcode & 7);
7852: uae_u32 dstreg = (opcode >> 9) & 7;
7853: OpcodeFamily = 30; CurrentInstrCycles = 18;
7854: {{ uae_s32 src = m68k_areg(regs, srcreg);
7855: {m68k_incpc(2);
7856: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7857: BusCyclePenalty += 2;
7858: CLEAR_CZNV;
7859: SET_ZFLG (((uae_s32)(src)) == 0);
7860: SET_NFLG (((uae_s32)(src)) < 0);
7861: put_long(dsta,src);
7862: }}}}return 18;
7863: }
7864: unsigned long REGPARAM2 CPUFUNC(op_2190_0)(uae_u32 opcode) /* MOVE */
7865: {
7866: uae_u32 srcreg = (opcode & 7);
7867: uae_u32 dstreg = (opcode >> 9) & 7;
7868: OpcodeFamily = 30; CurrentInstrCycles = 26;
7869: {{ uaecptr srca = m68k_areg(regs, srcreg);
7870: { uae_s32 src = get_long(srca);
7871: {m68k_incpc(2);
7872: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7873: BusCyclePenalty += 2;
7874: CLEAR_CZNV;
7875: SET_ZFLG (((uae_s32)(src)) == 0);
7876: SET_NFLG (((uae_s32)(src)) < 0);
7877: put_long(dsta,src);
7878: }}}}}return 26;
7879: }
7880: unsigned long REGPARAM2 CPUFUNC(op_2198_0)(uae_u32 opcode) /* MOVE */
7881: {
7882: uae_u32 srcreg = (opcode & 7);
7883: uae_u32 dstreg = (opcode >> 9) & 7;
7884: OpcodeFamily = 30; CurrentInstrCycles = 26;
7885: {{ uaecptr srca = m68k_areg(regs, srcreg);
7886: { uae_s32 src = get_long(srca);
7887: m68k_areg(regs, srcreg) += 4;
7888: {m68k_incpc(2);
7889: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7890: BusCyclePenalty += 2;
7891: CLEAR_CZNV;
7892: SET_ZFLG (((uae_s32)(src)) == 0);
7893: SET_NFLG (((uae_s32)(src)) < 0);
7894: put_long(dsta,src);
7895: }}}}}return 26;
7896: }
7897: unsigned long REGPARAM2 CPUFUNC(op_21a0_0)(uae_u32 opcode) /* MOVE */
7898: {
7899: uae_u32 srcreg = (opcode & 7);
7900: uae_u32 dstreg = (opcode >> 9) & 7;
7901: OpcodeFamily = 30; CurrentInstrCycles = 28;
7902: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
7903: { uae_s32 src = get_long(srca);
7904: m68k_areg (regs, srcreg) = srca;
7905: {m68k_incpc(2);
7906: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7907: BusCyclePenalty += 2;
7908: CLEAR_CZNV;
7909: SET_ZFLG (((uae_s32)(src)) == 0);
7910: SET_NFLG (((uae_s32)(src)) < 0);
7911: put_long(dsta,src);
7912: }}}}}return 28;
7913: }
7914: unsigned long REGPARAM2 CPUFUNC(op_21a8_0)(uae_u32 opcode) /* MOVE */
7915: {
7916: uae_u32 srcreg = (opcode & 7);
7917: uae_u32 dstreg = (opcode >> 9) & 7;
7918: OpcodeFamily = 30; CurrentInstrCycles = 30;
7919: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
7920: { uae_s32 src = get_long(srca);
7921: {m68k_incpc(4);
7922: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7923: BusCyclePenalty += 2;
7924: CLEAR_CZNV;
7925: SET_ZFLG (((uae_s32)(src)) == 0);
7926: SET_NFLG (((uae_s32)(src)) < 0);
7927: put_long(dsta,src);
7928: }}}}}return 30;
7929: }
7930: unsigned long REGPARAM2 CPUFUNC(op_21b0_0)(uae_u32 opcode) /* MOVE */
7931: {
7932: uae_u32 srcreg = (opcode & 7);
7933: uae_u32 dstreg = (opcode >> 9) & 7;
7934: OpcodeFamily = 30; CurrentInstrCycles = 32;
7935: {{m68k_incpc(2);
7936: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
7937: BusCyclePenalty += 2;
7938: { uae_s32 src = get_long(srca);
7939: {{ uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7940: BusCyclePenalty += 2;
7941: CLEAR_CZNV;
7942: SET_ZFLG (((uae_s32)(src)) == 0);
7943: SET_NFLG (((uae_s32)(src)) < 0);
7944: put_long(dsta,src);
7945: }}}}}}return 32;
7946: }
7947: unsigned long REGPARAM2 CPUFUNC(op_21b8_0)(uae_u32 opcode) /* MOVE */
7948: {
7949: uae_u32 dstreg = (opcode >> 9) & 7;
7950: OpcodeFamily = 30; CurrentInstrCycles = 30;
7951: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
7952: { uae_s32 src = get_long(srca);
7953: {m68k_incpc(4);
7954: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7955: BusCyclePenalty += 2;
7956: CLEAR_CZNV;
7957: SET_ZFLG (((uae_s32)(src)) == 0);
7958: SET_NFLG (((uae_s32)(src)) < 0);
7959: put_long(dsta,src);
7960: }}}}}return 30;
7961: }
7962: unsigned long REGPARAM2 CPUFUNC(op_21b9_0)(uae_u32 opcode) /* MOVE */
7963: {
7964: uae_u32 dstreg = (opcode >> 9) & 7;
7965: OpcodeFamily = 30; CurrentInstrCycles = 34;
7966: {{ uaecptr srca = get_ilong(2);
7967: { uae_s32 src = get_long(srca);
7968: {m68k_incpc(6);
7969: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7970: BusCyclePenalty += 2;
7971: CLEAR_CZNV;
7972: SET_ZFLG (((uae_s32)(src)) == 0);
7973: SET_NFLG (((uae_s32)(src)) < 0);
7974: put_long(dsta,src);
7975: }}}}}return 34;
7976: }
7977: unsigned long REGPARAM2 CPUFUNC(op_21ba_0)(uae_u32 opcode) /* MOVE */
7978: {
7979: uae_u32 dstreg = (opcode >> 9) & 7;
7980: OpcodeFamily = 30; CurrentInstrCycles = 30;
7981: {{ uaecptr srca = m68k_getpc () + 2;
7982: srca += (uae_s32)(uae_s16)get_iword(2);
7983: { uae_s32 src = get_long(srca);
7984: {m68k_incpc(4);
7985: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
7986: BusCyclePenalty += 2;
7987: CLEAR_CZNV;
7988: SET_ZFLG (((uae_s32)(src)) == 0);
7989: SET_NFLG (((uae_s32)(src)) < 0);
7990: put_long(dsta,src);
7991: }}}}}return 30;
7992: }
7993: unsigned long REGPARAM2 CPUFUNC(op_21bb_0)(uae_u32 opcode) /* MOVE */
7994: {
7995: uae_u32 dstreg = (opcode >> 9) & 7;
7996: OpcodeFamily = 30; CurrentInstrCycles = 32;
7997: {{m68k_incpc(2);
7998: { uaecptr tmppc = m68k_getpc();
7999: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
8000: BusCyclePenalty += 2;
8001: { uae_s32 src = get_long(srca);
8002: {{ uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
8003: BusCyclePenalty += 2;
8004: CLEAR_CZNV;
8005: SET_ZFLG (((uae_s32)(src)) == 0);
8006: SET_NFLG (((uae_s32)(src)) < 0);
8007: put_long(dsta,src);
8008: }}}}}}return 32;
8009: }
8010: unsigned long REGPARAM2 CPUFUNC(op_21bc_0)(uae_u32 opcode) /* MOVE */
8011: {
8012: uae_u32 dstreg = (opcode >> 9) & 7;
8013: OpcodeFamily = 30; CurrentInstrCycles = 26;
8014: {{ uae_s32 src = get_ilong(2);
8015: {m68k_incpc(6);
8016: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
8017: BusCyclePenalty += 2;
8018: CLEAR_CZNV;
8019: SET_ZFLG (((uae_s32)(src)) == 0);
8020: SET_NFLG (((uae_s32)(src)) < 0);
8021: put_long(dsta,src);
8022: }}}}return 26;
8023: }
8024: unsigned long REGPARAM2 CPUFUNC(op_21c0_0)(uae_u32 opcode) /* MOVE */
8025: {
8026: uae_u32 srcreg = (opcode & 7);
8027: OpcodeFamily = 30; CurrentInstrCycles = 16;
8028: {{ uae_s32 src = m68k_dreg(regs, srcreg);
8029: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
8030: CLEAR_CZNV;
8031: SET_ZFLG (((uae_s32)(src)) == 0);
8032: SET_NFLG (((uae_s32)(src)) < 0);
8033: put_long(dsta,src);
8034: }}}m68k_incpc(4);
8035: return 16;
8036: }
8037: unsigned long REGPARAM2 CPUFUNC(op_21c8_0)(uae_u32 opcode) /* MOVE */
8038: {
8039: uae_u32 srcreg = (opcode & 7);
8040: OpcodeFamily = 30; CurrentInstrCycles = 16;
8041: {{ uae_s32 src = m68k_areg(regs, srcreg);
8042: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
8043: CLEAR_CZNV;
8044: SET_ZFLG (((uae_s32)(src)) == 0);
8045: SET_NFLG (((uae_s32)(src)) < 0);
8046: put_long(dsta,src);
8047: }}}m68k_incpc(4);
8048: return 16;
8049: }
8050: unsigned long REGPARAM2 CPUFUNC(op_21d0_0)(uae_u32 opcode) /* MOVE */
8051: {
8052: uae_u32 srcreg = (opcode & 7);
8053: OpcodeFamily = 30; CurrentInstrCycles = 24;
8054: {{ uaecptr srca = m68k_areg(regs, srcreg);
8055: { uae_s32 src = get_long(srca);
8056: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
8057: CLEAR_CZNV;
8058: SET_ZFLG (((uae_s32)(src)) == 0);
8059: SET_NFLG (((uae_s32)(src)) < 0);
8060: put_long(dsta,src);
8061: }}}}m68k_incpc(4);
8062: return 24;
8063: }
8064: unsigned long REGPARAM2 CPUFUNC(op_21d8_0)(uae_u32 opcode) /* MOVE */
8065: {
8066: uae_u32 srcreg = (opcode & 7);
8067: OpcodeFamily = 30; CurrentInstrCycles = 24;
8068: {{ uaecptr srca = m68k_areg(regs, srcreg);
8069: { uae_s32 src = get_long(srca);
8070: m68k_areg(regs, srcreg) += 4;
8071: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
8072: CLEAR_CZNV;
8073: SET_ZFLG (((uae_s32)(src)) == 0);
8074: SET_NFLG (((uae_s32)(src)) < 0);
8075: put_long(dsta,src);
8076: }}}}m68k_incpc(4);
8077: return 24;
8078: }
8079: unsigned long REGPARAM2 CPUFUNC(op_21e0_0)(uae_u32 opcode) /* MOVE */
8080: {
8081: uae_u32 srcreg = (opcode & 7);
8082: OpcodeFamily = 30; CurrentInstrCycles = 26;
8083: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
8084: { uae_s32 src = get_long(srca);
8085: m68k_areg (regs, srcreg) = srca;
8086: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
8087: CLEAR_CZNV;
8088: SET_ZFLG (((uae_s32)(src)) == 0);
8089: SET_NFLG (((uae_s32)(src)) < 0);
8090: put_long(dsta,src);
8091: }}}}m68k_incpc(4);
8092: return 26;
8093: }
8094: unsigned long REGPARAM2 CPUFUNC(op_21e8_0)(uae_u32 opcode) /* MOVE */
8095: {
8096: uae_u32 srcreg = (opcode & 7);
8097: OpcodeFamily = 30; CurrentInstrCycles = 28;
8098: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
8099: { uae_s32 src = get_long(srca);
8100: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
8101: CLEAR_CZNV;
8102: SET_ZFLG (((uae_s32)(src)) == 0);
8103: SET_NFLG (((uae_s32)(src)) < 0);
8104: put_long(dsta,src);
8105: }}}}m68k_incpc(6);
8106: return 28;
8107: }
8108: unsigned long REGPARAM2 CPUFUNC(op_21f0_0)(uae_u32 opcode) /* MOVE */
8109: {
8110: uae_u32 srcreg = (opcode & 7);
8111: OpcodeFamily = 30; CurrentInstrCycles = 30;
8112: {{m68k_incpc(2);
8113: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
8114: BusCyclePenalty += 2;
8115: { uae_s32 src = get_long(srca);
8116: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(0);
8117: CLEAR_CZNV;
8118: SET_ZFLG (((uae_s32)(src)) == 0);
8119: SET_NFLG (((uae_s32)(src)) < 0);
8120: put_long(dsta,src);
8121: }}}}}m68k_incpc(2);
8122: return 30;
8123: }
8124: unsigned long REGPARAM2 CPUFUNC(op_21f8_0)(uae_u32 opcode) /* MOVE */
8125: {
8126: OpcodeFamily = 30; CurrentInstrCycles = 28;
8127: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
8128: { uae_s32 src = get_long(srca);
8129: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
8130: CLEAR_CZNV;
8131: SET_ZFLG (((uae_s32)(src)) == 0);
8132: SET_NFLG (((uae_s32)(src)) < 0);
8133: put_long(dsta,src);
8134: }}}}m68k_incpc(6);
8135: return 28;
8136: }
8137: unsigned long REGPARAM2 CPUFUNC(op_21f9_0)(uae_u32 opcode) /* MOVE */
8138: {
8139: OpcodeFamily = 30; CurrentInstrCycles = 32;
8140: {{ uaecptr srca = get_ilong(2);
8141: { uae_s32 src = get_long(srca);
8142: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
8143: CLEAR_CZNV;
8144: SET_ZFLG (((uae_s32)(src)) == 0);
8145: SET_NFLG (((uae_s32)(src)) < 0);
8146: put_long(dsta,src);
8147: }}}}m68k_incpc(8);
8148: return 32;
8149: }
8150: unsigned long REGPARAM2 CPUFUNC(op_21fa_0)(uae_u32 opcode) /* MOVE */
8151: {
8152: OpcodeFamily = 30; CurrentInstrCycles = 28;
8153: {{ uaecptr srca = m68k_getpc () + 2;
8154: srca += (uae_s32)(uae_s16)get_iword(2);
8155: { uae_s32 src = get_long(srca);
8156: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
8157: CLEAR_CZNV;
8158: SET_ZFLG (((uae_s32)(src)) == 0);
8159: SET_NFLG (((uae_s32)(src)) < 0);
8160: put_long(dsta,src);
8161: }}}}m68k_incpc(6);
8162: return 28;
8163: }
8164: unsigned long REGPARAM2 CPUFUNC(op_21fb_0)(uae_u32 opcode) /* MOVE */
8165: {
8166: OpcodeFamily = 30; CurrentInstrCycles = 30;
8167: {{m68k_incpc(2);
8168: { uaecptr tmppc = m68k_getpc();
8169: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
8170: BusCyclePenalty += 2;
8171: { uae_s32 src = get_long(srca);
8172: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(0);
8173: CLEAR_CZNV;
8174: SET_ZFLG (((uae_s32)(src)) == 0);
8175: SET_NFLG (((uae_s32)(src)) < 0);
8176: put_long(dsta,src);
8177: }}}}}m68k_incpc(2);
8178: return 30;
8179: }
8180: unsigned long REGPARAM2 CPUFUNC(op_21fc_0)(uae_u32 opcode) /* MOVE */
8181: {
8182: OpcodeFamily = 30; CurrentInstrCycles = 24;
8183: {{ uae_s32 src = get_ilong(2);
8184: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
8185: CLEAR_CZNV;
8186: SET_ZFLG (((uae_s32)(src)) == 0);
8187: SET_NFLG (((uae_s32)(src)) < 0);
8188: put_long(dsta,src);
8189: }}}m68k_incpc(8);
8190: return 24;
8191: }
8192: unsigned long REGPARAM2 CPUFUNC(op_23c0_0)(uae_u32 opcode) /* MOVE */
8193: {
8194: uae_u32 srcreg = (opcode & 7);
8195: OpcodeFamily = 30; CurrentInstrCycles = 20;
8196: {{ uae_s32 src = m68k_dreg(regs, srcreg);
8197: { uaecptr dsta = get_ilong(2);
8198: CLEAR_CZNV;
8199: SET_ZFLG (((uae_s32)(src)) == 0);
8200: SET_NFLG (((uae_s32)(src)) < 0);
8201: put_long(dsta,src);
8202: }}}m68k_incpc(6);
8203: return 20;
8204: }
8205: unsigned long REGPARAM2 CPUFUNC(op_23c8_0)(uae_u32 opcode) /* MOVE */
8206: {
8207: uae_u32 srcreg = (opcode & 7);
8208: OpcodeFamily = 30; CurrentInstrCycles = 20;
8209: {{ uae_s32 src = m68k_areg(regs, srcreg);
8210: { uaecptr dsta = get_ilong(2);
8211: CLEAR_CZNV;
8212: SET_ZFLG (((uae_s32)(src)) == 0);
8213: SET_NFLG (((uae_s32)(src)) < 0);
8214: put_long(dsta,src);
8215: }}}m68k_incpc(6);
8216: return 20;
8217: }
8218: unsigned long REGPARAM2 CPUFUNC(op_23d0_0)(uae_u32 opcode) /* MOVE */
8219: {
8220: uae_u32 srcreg = (opcode & 7);
8221: OpcodeFamily = 30; CurrentInstrCycles = 28;
8222: {{ uaecptr srca = m68k_areg(regs, srcreg);
8223: { uae_s32 src = get_long(srca);
8224: { uaecptr dsta = get_ilong(2);
8225: CLEAR_CZNV;
8226: SET_ZFLG (((uae_s32)(src)) == 0);
8227: SET_NFLG (((uae_s32)(src)) < 0);
8228: put_long(dsta,src);
8229: }}}}m68k_incpc(6);
8230: return 28;
8231: }
8232: unsigned long REGPARAM2 CPUFUNC(op_23d8_0)(uae_u32 opcode) /* MOVE */
8233: {
8234: uae_u32 srcreg = (opcode & 7);
8235: OpcodeFamily = 30; CurrentInstrCycles = 28;
8236: {{ uaecptr srca = m68k_areg(regs, srcreg);
8237: { uae_s32 src = get_long(srca);
8238: m68k_areg(regs, srcreg) += 4;
8239: { uaecptr dsta = get_ilong(2);
8240: CLEAR_CZNV;
8241: SET_ZFLG (((uae_s32)(src)) == 0);
8242: SET_NFLG (((uae_s32)(src)) < 0);
8243: put_long(dsta,src);
8244: }}}}m68k_incpc(6);
8245: return 28;
8246: }
8247: unsigned long REGPARAM2 CPUFUNC(op_23e0_0)(uae_u32 opcode) /* MOVE */
8248: {
8249: uae_u32 srcreg = (opcode & 7);
8250: OpcodeFamily = 30; CurrentInstrCycles = 30;
8251: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
8252: { uae_s32 src = get_long(srca);
8253: m68k_areg (regs, srcreg) = srca;
8254: { uaecptr dsta = get_ilong(2);
8255: CLEAR_CZNV;
8256: SET_ZFLG (((uae_s32)(src)) == 0);
8257: SET_NFLG (((uae_s32)(src)) < 0);
8258: put_long(dsta,src);
8259: }}}}m68k_incpc(6);
8260: return 30;
8261: }
8262: unsigned long REGPARAM2 CPUFUNC(op_23e8_0)(uae_u32 opcode) /* MOVE */
8263: {
8264: uae_u32 srcreg = (opcode & 7);
8265: OpcodeFamily = 30; CurrentInstrCycles = 32;
8266: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
8267: { uae_s32 src = get_long(srca);
8268: { uaecptr dsta = get_ilong(4);
8269: CLEAR_CZNV;
8270: SET_ZFLG (((uae_s32)(src)) == 0);
8271: SET_NFLG (((uae_s32)(src)) < 0);
8272: put_long(dsta,src);
8273: }}}}m68k_incpc(8);
8274: return 32;
8275: }
8276: unsigned long REGPARAM2 CPUFUNC(op_23f0_0)(uae_u32 opcode) /* MOVE */
8277: {
8278: uae_u32 srcreg = (opcode & 7);
8279: OpcodeFamily = 30; CurrentInstrCycles = 34;
8280: {{m68k_incpc(2);
8281: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
8282: BusCyclePenalty += 2;
8283: { uae_s32 src = get_long(srca);
8284: { uaecptr dsta = get_ilong(0);
8285: CLEAR_CZNV;
8286: SET_ZFLG (((uae_s32)(src)) == 0);
8287: SET_NFLG (((uae_s32)(src)) < 0);
8288: put_long(dsta,src);
8289: }}}}}m68k_incpc(4);
8290: return 34;
8291: }
8292: unsigned long REGPARAM2 CPUFUNC(op_23f8_0)(uae_u32 opcode) /* MOVE */
8293: {
8294: OpcodeFamily = 30; CurrentInstrCycles = 32;
8295: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
8296: { uae_s32 src = get_long(srca);
8297: { uaecptr dsta = get_ilong(4);
8298: CLEAR_CZNV;
8299: SET_ZFLG (((uae_s32)(src)) == 0);
8300: SET_NFLG (((uae_s32)(src)) < 0);
8301: put_long(dsta,src);
8302: }}}}m68k_incpc(8);
8303: return 32;
8304: }
8305: unsigned long REGPARAM2 CPUFUNC(op_23f9_0)(uae_u32 opcode) /* MOVE */
8306: {
8307: OpcodeFamily = 30; CurrentInstrCycles = 36;
8308: {{ uaecptr srca = get_ilong(2);
8309: { uae_s32 src = get_long(srca);
8310: { uaecptr dsta = get_ilong(6);
8311: CLEAR_CZNV;
8312: SET_ZFLG (((uae_s32)(src)) == 0);
8313: SET_NFLG (((uae_s32)(src)) < 0);
8314: put_long(dsta,src);
8315: }}}}m68k_incpc(10);
8316: return 36;
8317: }
8318: unsigned long REGPARAM2 CPUFUNC(op_23fa_0)(uae_u32 opcode) /* MOVE */
8319: {
8320: OpcodeFamily = 30; CurrentInstrCycles = 32;
8321: {{ uaecptr srca = m68k_getpc () + 2;
8322: srca += (uae_s32)(uae_s16)get_iword(2);
8323: { uae_s32 src = get_long(srca);
8324: { uaecptr dsta = get_ilong(4);
8325: CLEAR_CZNV;
8326: SET_ZFLG (((uae_s32)(src)) == 0);
8327: SET_NFLG (((uae_s32)(src)) < 0);
8328: put_long(dsta,src);
8329: }}}}m68k_incpc(8);
8330: return 32;
8331: }
8332: unsigned long REGPARAM2 CPUFUNC(op_23fb_0)(uae_u32 opcode) /* MOVE */
8333: {
8334: OpcodeFamily = 30; CurrentInstrCycles = 34;
8335: {{m68k_incpc(2);
8336: { uaecptr tmppc = m68k_getpc();
8337: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
8338: BusCyclePenalty += 2;
8339: { uae_s32 src = get_long(srca);
8340: { uaecptr dsta = get_ilong(0);
8341: CLEAR_CZNV;
8342: SET_ZFLG (((uae_s32)(src)) == 0);
8343: SET_NFLG (((uae_s32)(src)) < 0);
8344: put_long(dsta,src);
8345: }}}}}m68k_incpc(4);
8346: return 34;
8347: }
8348: unsigned long REGPARAM2 CPUFUNC(op_23fc_0)(uae_u32 opcode) /* MOVE */
8349: {
8350: OpcodeFamily = 30; CurrentInstrCycles = 28;
8351: {{ uae_s32 src = get_ilong(2);
8352: { uaecptr dsta = get_ilong(6);
8353: CLEAR_CZNV;
8354: SET_ZFLG (((uae_s32)(src)) == 0);
8355: SET_NFLG (((uae_s32)(src)) < 0);
8356: put_long(dsta,src);
8357: }}}m68k_incpc(10);
8358: return 28;
8359: }
8360: unsigned long REGPARAM2 CPUFUNC(op_3000_0)(uae_u32 opcode) /* MOVE */
8361: {
8362: uae_u32 srcreg = (opcode & 7);
8363: uae_u32 dstreg = (opcode >> 9) & 7;
8364: OpcodeFamily = 30; CurrentInstrCycles = 4;
8365: {{ uae_s16 src = m68k_dreg(regs, srcreg);
8366: { CLEAR_CZNV;
8367: SET_ZFLG (((uae_s16)(src)) == 0);
8368: SET_NFLG (((uae_s16)(src)) < 0);
8369: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8370: }}}m68k_incpc(2);
8371: return 4;
8372: }
8373: unsigned long REGPARAM2 CPUFUNC(op_3008_0)(uae_u32 opcode) /* MOVE */
8374: {
8375: uae_u32 srcreg = (opcode & 7);
8376: uae_u32 dstreg = (opcode >> 9) & 7;
8377: OpcodeFamily = 30; CurrentInstrCycles = 4;
8378: {{ uae_s16 src = m68k_areg(regs, srcreg);
8379: { CLEAR_CZNV;
8380: SET_ZFLG (((uae_s16)(src)) == 0);
8381: SET_NFLG (((uae_s16)(src)) < 0);
8382: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8383: }}}m68k_incpc(2);
8384: return 4;
8385: }
8386: unsigned long REGPARAM2 CPUFUNC(op_3010_0)(uae_u32 opcode) /* MOVE */
8387: {
8388: uae_u32 srcreg = (opcode & 7);
8389: uae_u32 dstreg = (opcode >> 9) & 7;
8390: OpcodeFamily = 30; CurrentInstrCycles = 8;
8391: {{ uaecptr srca = m68k_areg(regs, srcreg);
8392: { uae_s16 src = get_word(srca);
8393: { CLEAR_CZNV;
8394: SET_ZFLG (((uae_s16)(src)) == 0);
8395: SET_NFLG (((uae_s16)(src)) < 0);
8396: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8397: }}}}m68k_incpc(2);
8398: return 8;
8399: }
8400: unsigned long REGPARAM2 CPUFUNC(op_3018_0)(uae_u32 opcode) /* MOVE */
8401: {
8402: uae_u32 srcreg = (opcode & 7);
8403: uae_u32 dstreg = (opcode >> 9) & 7;
8404: OpcodeFamily = 30; CurrentInstrCycles = 8;
8405: {{ uaecptr srca = m68k_areg(regs, srcreg);
8406: { uae_s16 src = get_word(srca);
8407: m68k_areg(regs, srcreg) += 2;
8408: { CLEAR_CZNV;
8409: SET_ZFLG (((uae_s16)(src)) == 0);
8410: SET_NFLG (((uae_s16)(src)) < 0);
8411: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8412: }}}}m68k_incpc(2);
8413: return 8;
8414: }
8415: unsigned long REGPARAM2 CPUFUNC(op_3020_0)(uae_u32 opcode) /* MOVE */
8416: {
8417: uae_u32 srcreg = (opcode & 7);
8418: uae_u32 dstreg = (opcode >> 9) & 7;
8419: OpcodeFamily = 30; CurrentInstrCycles = 10;
8420: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
8421: { uae_s16 src = get_word(srca);
8422: m68k_areg (regs, srcreg) = srca;
8423: { CLEAR_CZNV;
8424: SET_ZFLG (((uae_s16)(src)) == 0);
8425: SET_NFLG (((uae_s16)(src)) < 0);
8426: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8427: }}}}m68k_incpc(2);
8428: return 10;
8429: }
8430: unsigned long REGPARAM2 CPUFUNC(op_3028_0)(uae_u32 opcode) /* MOVE */
8431: {
8432: uae_u32 srcreg = (opcode & 7);
8433: uae_u32 dstreg = (opcode >> 9) & 7;
8434: OpcodeFamily = 30; CurrentInstrCycles = 12;
8435: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
8436: { uae_s16 src = get_word(srca);
8437: { CLEAR_CZNV;
8438: SET_ZFLG (((uae_s16)(src)) == 0);
8439: SET_NFLG (((uae_s16)(src)) < 0);
8440: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8441: }}}}m68k_incpc(4);
8442: return 12;
8443: }
8444: unsigned long REGPARAM2 CPUFUNC(op_3030_0)(uae_u32 opcode) /* MOVE */
8445: {
8446: uae_u32 srcreg = (opcode & 7);
8447: uae_u32 dstreg = (opcode >> 9) & 7;
8448: OpcodeFamily = 30; CurrentInstrCycles = 14;
8449: {{m68k_incpc(2);
8450: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
8451: BusCyclePenalty += 2;
8452: { uae_s16 src = get_word(srca);
8453: { CLEAR_CZNV;
8454: SET_ZFLG (((uae_s16)(src)) == 0);
8455: SET_NFLG (((uae_s16)(src)) < 0);
8456: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8457: }}}}}return 14;
8458: }
8459: unsigned long REGPARAM2 CPUFUNC(op_3038_0)(uae_u32 opcode) /* MOVE */
8460: {
8461: uae_u32 dstreg = (opcode >> 9) & 7;
8462: OpcodeFamily = 30; CurrentInstrCycles = 12;
8463: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
8464: { uae_s16 src = get_word(srca);
8465: { CLEAR_CZNV;
8466: SET_ZFLG (((uae_s16)(src)) == 0);
8467: SET_NFLG (((uae_s16)(src)) < 0);
8468: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8469: }}}}m68k_incpc(4);
8470: return 12;
8471: }
8472: unsigned long REGPARAM2 CPUFUNC(op_3039_0)(uae_u32 opcode) /* MOVE */
8473: {
8474: uae_u32 dstreg = (opcode >> 9) & 7;
8475: OpcodeFamily = 30; CurrentInstrCycles = 16;
8476: {{ uaecptr srca = get_ilong(2);
8477: { uae_s16 src = get_word(srca);
8478: { CLEAR_CZNV;
8479: SET_ZFLG (((uae_s16)(src)) == 0);
8480: SET_NFLG (((uae_s16)(src)) < 0);
8481: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8482: }}}}m68k_incpc(6);
8483: return 16;
8484: }
8485: unsigned long REGPARAM2 CPUFUNC(op_303a_0)(uae_u32 opcode) /* MOVE */
8486: {
8487: uae_u32 dstreg = (opcode >> 9) & 7;
8488: OpcodeFamily = 30; CurrentInstrCycles = 12;
8489: {{ uaecptr srca = m68k_getpc () + 2;
8490: srca += (uae_s32)(uae_s16)get_iword(2);
8491: { uae_s16 src = get_word(srca);
8492: { CLEAR_CZNV;
8493: SET_ZFLG (((uae_s16)(src)) == 0);
8494: SET_NFLG (((uae_s16)(src)) < 0);
8495: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8496: }}}}m68k_incpc(4);
8497: return 12;
8498: }
8499: unsigned long REGPARAM2 CPUFUNC(op_303b_0)(uae_u32 opcode) /* MOVE */
8500: {
8501: uae_u32 dstreg = (opcode >> 9) & 7;
8502: OpcodeFamily = 30; CurrentInstrCycles = 14;
8503: {{m68k_incpc(2);
8504: { uaecptr tmppc = m68k_getpc();
8505: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
8506: BusCyclePenalty += 2;
8507: { uae_s16 src = get_word(srca);
8508: { CLEAR_CZNV;
8509: SET_ZFLG (((uae_s16)(src)) == 0);
8510: SET_NFLG (((uae_s16)(src)) < 0);
8511: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8512: }}}}}return 14;
8513: }
8514: unsigned long REGPARAM2 CPUFUNC(op_303c_0)(uae_u32 opcode) /* MOVE */
8515: {
8516: uae_u32 dstreg = (opcode >> 9) & 7;
8517: OpcodeFamily = 30; CurrentInstrCycles = 8;
8518: {{ uae_s16 src = get_iword(2);
8519: { CLEAR_CZNV;
8520: SET_ZFLG (((uae_s16)(src)) == 0);
8521: SET_NFLG (((uae_s16)(src)) < 0);
8522: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
8523: }}}m68k_incpc(4);
8524: return 8;
8525: }
8526: unsigned long REGPARAM2 CPUFUNC(op_3040_0)(uae_u32 opcode) /* MOVEA */
8527: {
8528: uae_u32 srcreg = (opcode & 7);
8529: uae_u32 dstreg = (opcode >> 9) & 7;
8530: OpcodeFamily = 31; CurrentInstrCycles = 4;
8531: {{ uae_s16 src = m68k_dreg(regs, srcreg);
8532: { uae_u32 val = (uae_s32)(uae_s16)src;
8533: m68k_areg(regs, dstreg) = (val);
8534: }}}m68k_incpc(2);
8535: return 4;
8536: }
8537: unsigned long REGPARAM2 CPUFUNC(op_3048_0)(uae_u32 opcode) /* MOVEA */
8538: {
8539: uae_u32 srcreg = (opcode & 7);
8540: uae_u32 dstreg = (opcode >> 9) & 7;
8541: OpcodeFamily = 31; CurrentInstrCycles = 4;
8542: {{ uae_s16 src = m68k_areg(regs, srcreg);
8543: { uae_u32 val = (uae_s32)(uae_s16)src;
8544: m68k_areg(regs, dstreg) = (val);
8545: }}}m68k_incpc(2);
8546: return 4;
8547: }
8548: unsigned long REGPARAM2 CPUFUNC(op_3050_0)(uae_u32 opcode) /* MOVEA */
8549: {
8550: uae_u32 srcreg = (opcode & 7);
8551: uae_u32 dstreg = (opcode >> 9) & 7;
8552: OpcodeFamily = 31; CurrentInstrCycles = 8;
8553: {{ uaecptr srca = m68k_areg(regs, srcreg);
8554: { uae_s16 src = get_word(srca);
8555: { uae_u32 val = (uae_s32)(uae_s16)src;
8556: m68k_areg(regs, dstreg) = (val);
8557: }}}}m68k_incpc(2);
8558: return 8;
8559: }
8560: unsigned long REGPARAM2 CPUFUNC(op_3058_0)(uae_u32 opcode) /* MOVEA */
8561: {
8562: uae_u32 srcreg = (opcode & 7);
8563: uae_u32 dstreg = (opcode >> 9) & 7;
8564: OpcodeFamily = 31; CurrentInstrCycles = 8;
8565: {{ uaecptr srca = m68k_areg(regs, srcreg);
8566: { uae_s16 src = get_word(srca);
8567: m68k_areg(regs, srcreg) += 2;
8568: { uae_u32 val = (uae_s32)(uae_s16)src;
8569: m68k_areg(regs, dstreg) = (val);
8570: }}}}m68k_incpc(2);
8571: return 8;
8572: }
8573: unsigned long REGPARAM2 CPUFUNC(op_3060_0)(uae_u32 opcode) /* MOVEA */
8574: {
8575: uae_u32 srcreg = (opcode & 7);
8576: uae_u32 dstreg = (opcode >> 9) & 7;
8577: OpcodeFamily = 31; CurrentInstrCycles = 10;
8578: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
8579: { uae_s16 src = get_word(srca);
8580: m68k_areg (regs, srcreg) = srca;
8581: { uae_u32 val = (uae_s32)(uae_s16)src;
8582: m68k_areg(regs, dstreg) = (val);
8583: }}}}m68k_incpc(2);
8584: return 10;
8585: }
8586: unsigned long REGPARAM2 CPUFUNC(op_3068_0)(uae_u32 opcode) /* MOVEA */
8587: {
8588: uae_u32 srcreg = (opcode & 7);
8589: uae_u32 dstreg = (opcode >> 9) & 7;
8590: OpcodeFamily = 31; CurrentInstrCycles = 12;
8591: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
8592: { uae_s16 src = get_word(srca);
8593: { uae_u32 val = (uae_s32)(uae_s16)src;
8594: m68k_areg(regs, dstreg) = (val);
8595: }}}}m68k_incpc(4);
8596: return 12;
8597: }
8598: unsigned long REGPARAM2 CPUFUNC(op_3070_0)(uae_u32 opcode) /* MOVEA */
8599: {
8600: uae_u32 srcreg = (opcode & 7);
8601: uae_u32 dstreg = (opcode >> 9) & 7;
8602: OpcodeFamily = 31; CurrentInstrCycles = 14;
8603: {{m68k_incpc(2);
8604: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
8605: BusCyclePenalty += 2;
8606: { uae_s16 src = get_word(srca);
8607: { uae_u32 val = (uae_s32)(uae_s16)src;
8608: m68k_areg(regs, dstreg) = (val);
8609: }}}}}return 14;
8610: }
8611: unsigned long REGPARAM2 CPUFUNC(op_3078_0)(uae_u32 opcode) /* MOVEA */
8612: {
8613: uae_u32 dstreg = (opcode >> 9) & 7;
8614: OpcodeFamily = 31; CurrentInstrCycles = 12;
8615: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
8616: { uae_s16 src = get_word(srca);
8617: { uae_u32 val = (uae_s32)(uae_s16)src;
8618: m68k_areg(regs, dstreg) = (val);
8619: }}}}m68k_incpc(4);
8620: return 12;
8621: }
8622: unsigned long REGPARAM2 CPUFUNC(op_3079_0)(uae_u32 opcode) /* MOVEA */
8623: {
8624: uae_u32 dstreg = (opcode >> 9) & 7;
8625: OpcodeFamily = 31; CurrentInstrCycles = 16;
8626: {{ uaecptr srca = get_ilong(2);
8627: { uae_s16 src = get_word(srca);
8628: { uae_u32 val = (uae_s32)(uae_s16)src;
8629: m68k_areg(regs, dstreg) = (val);
8630: }}}}m68k_incpc(6);
8631: return 16;
8632: }
8633: unsigned long REGPARAM2 CPUFUNC(op_307a_0)(uae_u32 opcode) /* MOVEA */
8634: {
8635: uae_u32 dstreg = (opcode >> 9) & 7;
8636: OpcodeFamily = 31; CurrentInstrCycles = 12;
8637: {{ uaecptr srca = m68k_getpc () + 2;
8638: srca += (uae_s32)(uae_s16)get_iword(2);
8639: { uae_s16 src = get_word(srca);
8640: { uae_u32 val = (uae_s32)(uae_s16)src;
8641: m68k_areg(regs, dstreg) = (val);
8642: }}}}m68k_incpc(4);
8643: return 12;
8644: }
8645: unsigned long REGPARAM2 CPUFUNC(op_307b_0)(uae_u32 opcode) /* MOVEA */
8646: {
8647: uae_u32 dstreg = (opcode >> 9) & 7;
8648: OpcodeFamily = 31; CurrentInstrCycles = 14;
8649: {{m68k_incpc(2);
8650: { uaecptr tmppc = m68k_getpc();
8651: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
8652: BusCyclePenalty += 2;
8653: { uae_s16 src = get_word(srca);
8654: { uae_u32 val = (uae_s32)(uae_s16)src;
8655: m68k_areg(regs, dstreg) = (val);
8656: }}}}}return 14;
8657: }
8658: unsigned long REGPARAM2 CPUFUNC(op_307c_0)(uae_u32 opcode) /* MOVEA */
8659: {
8660: uae_u32 dstreg = (opcode >> 9) & 7;
8661: OpcodeFamily = 31; CurrentInstrCycles = 8;
8662: {{ uae_s16 src = get_iword(2);
8663: { uae_u32 val = (uae_s32)(uae_s16)src;
8664: m68k_areg(regs, dstreg) = (val);
8665: }}}m68k_incpc(4);
8666: return 8;
8667: }
8668: unsigned long REGPARAM2 CPUFUNC(op_3080_0)(uae_u32 opcode) /* MOVE */
8669: {
8670: uae_u32 srcreg = (opcode & 7);
8671: uae_u32 dstreg = (opcode >> 9) & 7;
8672: OpcodeFamily = 30; CurrentInstrCycles = 8;
8673: {{ uae_s16 src = m68k_dreg(regs, srcreg);
8674: { uaecptr dsta = m68k_areg(regs, dstreg);
8675: CLEAR_CZNV;
8676: SET_ZFLG (((uae_s16)(src)) == 0);
8677: SET_NFLG (((uae_s16)(src)) < 0);
8678: put_word(dsta,src);
8679: }}}m68k_incpc(2);
8680: return 8;
8681: }
8682: unsigned long REGPARAM2 CPUFUNC(op_3088_0)(uae_u32 opcode) /* MOVE */
8683: {
8684: uae_u32 srcreg = (opcode & 7);
8685: uae_u32 dstreg = (opcode >> 9) & 7;
8686: OpcodeFamily = 30; CurrentInstrCycles = 8;
8687: {{ uae_s16 src = m68k_areg(regs, srcreg);
8688: { uaecptr dsta = m68k_areg(regs, dstreg);
8689: CLEAR_CZNV;
8690: SET_ZFLG (((uae_s16)(src)) == 0);
8691: SET_NFLG (((uae_s16)(src)) < 0);
8692: put_word(dsta,src);
8693: }}}m68k_incpc(2);
8694: return 8;
8695: }
8696: unsigned long REGPARAM2 CPUFUNC(op_3090_0)(uae_u32 opcode) /* MOVE */
8697: {
8698: uae_u32 srcreg = (opcode & 7);
8699: uae_u32 dstreg = (opcode >> 9) & 7;
8700: OpcodeFamily = 30; CurrentInstrCycles = 12;
8701: {{ uaecptr srca = m68k_areg(regs, srcreg);
8702: { uae_s16 src = get_word(srca);
8703: { uaecptr dsta = m68k_areg(regs, dstreg);
8704: CLEAR_CZNV;
8705: SET_ZFLG (((uae_s16)(src)) == 0);
8706: SET_NFLG (((uae_s16)(src)) < 0);
8707: put_word(dsta,src);
8708: }}}}m68k_incpc(2);
8709: return 12;
8710: }
8711: unsigned long REGPARAM2 CPUFUNC(op_3098_0)(uae_u32 opcode) /* MOVE */
8712: {
8713: uae_u32 srcreg = (opcode & 7);
8714: uae_u32 dstreg = (opcode >> 9) & 7;
8715: OpcodeFamily = 30; CurrentInstrCycles = 12;
8716: {{ uaecptr srca = m68k_areg(regs, srcreg);
8717: { uae_s16 src = get_word(srca);
8718: m68k_areg(regs, srcreg) += 2;
8719: { uaecptr dsta = m68k_areg(regs, dstreg);
8720: CLEAR_CZNV;
8721: SET_ZFLG (((uae_s16)(src)) == 0);
8722: SET_NFLG (((uae_s16)(src)) < 0);
8723: put_word(dsta,src);
8724: }}}}m68k_incpc(2);
8725: return 12;
8726: }
8727: unsigned long REGPARAM2 CPUFUNC(op_30a0_0)(uae_u32 opcode) /* MOVE */
8728: {
8729: uae_u32 srcreg = (opcode & 7);
8730: uae_u32 dstreg = (opcode >> 9) & 7;
8731: OpcodeFamily = 30; CurrentInstrCycles = 14;
8732: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
8733: { uae_s16 src = get_word(srca);
8734: m68k_areg (regs, srcreg) = srca;
8735: { uaecptr dsta = m68k_areg(regs, dstreg);
8736: CLEAR_CZNV;
8737: SET_ZFLG (((uae_s16)(src)) == 0);
8738: SET_NFLG (((uae_s16)(src)) < 0);
8739: put_word(dsta,src);
8740: }}}}m68k_incpc(2);
8741: return 14;
8742: }
8743: unsigned long REGPARAM2 CPUFUNC(op_30a8_0)(uae_u32 opcode) /* MOVE */
8744: {
8745: uae_u32 srcreg = (opcode & 7);
8746: uae_u32 dstreg = (opcode >> 9) & 7;
8747: OpcodeFamily = 30; CurrentInstrCycles = 16;
8748: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
8749: { uae_s16 src = get_word(srca);
8750: { uaecptr dsta = m68k_areg(regs, dstreg);
8751: CLEAR_CZNV;
8752: SET_ZFLG (((uae_s16)(src)) == 0);
8753: SET_NFLG (((uae_s16)(src)) < 0);
8754: put_word(dsta,src);
8755: }}}}m68k_incpc(4);
8756: return 16;
8757: }
8758: unsigned long REGPARAM2 CPUFUNC(op_30b0_0)(uae_u32 opcode) /* MOVE */
8759: {
8760: uae_u32 srcreg = (opcode & 7);
8761: uae_u32 dstreg = (opcode >> 9) & 7;
8762: OpcodeFamily = 30; CurrentInstrCycles = 18;
8763: {{m68k_incpc(2);
8764: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
8765: BusCyclePenalty += 2;
8766: { uae_s16 src = get_word(srca);
8767: { uaecptr dsta = m68k_areg(regs, dstreg);
8768: CLEAR_CZNV;
8769: SET_ZFLG (((uae_s16)(src)) == 0);
8770: SET_NFLG (((uae_s16)(src)) < 0);
8771: put_word(dsta,src);
8772: }}}}}return 18;
8773: }
8774: unsigned long REGPARAM2 CPUFUNC(op_30b8_0)(uae_u32 opcode) /* MOVE */
8775: {
8776: uae_u32 dstreg = (opcode >> 9) & 7;
8777: OpcodeFamily = 30; CurrentInstrCycles = 16;
8778: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
8779: { uae_s16 src = get_word(srca);
8780: { uaecptr dsta = m68k_areg(regs, dstreg);
8781: CLEAR_CZNV;
8782: SET_ZFLG (((uae_s16)(src)) == 0);
8783: SET_NFLG (((uae_s16)(src)) < 0);
8784: put_word(dsta,src);
8785: }}}}m68k_incpc(4);
8786: return 16;
8787: }
8788: unsigned long REGPARAM2 CPUFUNC(op_30b9_0)(uae_u32 opcode) /* MOVE */
8789: {
8790: uae_u32 dstreg = (opcode >> 9) & 7;
8791: OpcodeFamily = 30; CurrentInstrCycles = 20;
8792: {{ uaecptr srca = get_ilong(2);
8793: { uae_s16 src = get_word(srca);
8794: { uaecptr dsta = m68k_areg(regs, dstreg);
8795: CLEAR_CZNV;
8796: SET_ZFLG (((uae_s16)(src)) == 0);
8797: SET_NFLG (((uae_s16)(src)) < 0);
8798: put_word(dsta,src);
8799: }}}}m68k_incpc(6);
8800: return 20;
8801: }
8802: unsigned long REGPARAM2 CPUFUNC(op_30ba_0)(uae_u32 opcode) /* MOVE */
8803: {
8804: uae_u32 dstreg = (opcode >> 9) & 7;
8805: OpcodeFamily = 30; CurrentInstrCycles = 16;
8806: {{ uaecptr srca = m68k_getpc () + 2;
8807: srca += (uae_s32)(uae_s16)get_iword(2);
8808: { uae_s16 src = get_word(srca);
8809: { uaecptr dsta = m68k_areg(regs, dstreg);
8810: CLEAR_CZNV;
8811: SET_ZFLG (((uae_s16)(src)) == 0);
8812: SET_NFLG (((uae_s16)(src)) < 0);
8813: put_word(dsta,src);
8814: }}}}m68k_incpc(4);
8815: return 16;
8816: }
8817: unsigned long REGPARAM2 CPUFUNC(op_30bb_0)(uae_u32 opcode) /* MOVE */
8818: {
8819: uae_u32 dstreg = (opcode >> 9) & 7;
8820: OpcodeFamily = 30; CurrentInstrCycles = 18;
8821: {{m68k_incpc(2);
8822: { uaecptr tmppc = m68k_getpc();
8823: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
8824: BusCyclePenalty += 2;
8825: { uae_s16 src = get_word(srca);
8826: { uaecptr dsta = m68k_areg(regs, dstreg);
8827: CLEAR_CZNV;
8828: SET_ZFLG (((uae_s16)(src)) == 0);
8829: SET_NFLG (((uae_s16)(src)) < 0);
8830: put_word(dsta,src);
8831: }}}}}return 18;
8832: }
8833: unsigned long REGPARAM2 CPUFUNC(op_30bc_0)(uae_u32 opcode) /* MOVE */
8834: {
8835: uae_u32 dstreg = (opcode >> 9) & 7;
8836: OpcodeFamily = 30; CurrentInstrCycles = 12;
8837: {{ uae_s16 src = get_iword(2);
8838: { uaecptr dsta = m68k_areg(regs, dstreg);
8839: CLEAR_CZNV;
8840: SET_ZFLG (((uae_s16)(src)) == 0);
8841: SET_NFLG (((uae_s16)(src)) < 0);
8842: put_word(dsta,src);
8843: }}}m68k_incpc(4);
8844: return 12;
8845: }
8846: unsigned long REGPARAM2 CPUFUNC(op_30c0_0)(uae_u32 opcode) /* MOVE */
8847: {
8848: uae_u32 srcreg = (opcode & 7);
8849: uae_u32 dstreg = (opcode >> 9) & 7;
8850: OpcodeFamily = 30; CurrentInstrCycles = 8;
8851: {{ uae_s16 src = m68k_dreg(regs, srcreg);
8852: { uaecptr dsta = m68k_areg(regs, dstreg);
8853: m68k_areg(regs, dstreg) += 2;
8854: CLEAR_CZNV;
8855: SET_ZFLG (((uae_s16)(src)) == 0);
8856: SET_NFLG (((uae_s16)(src)) < 0);
8857: put_word(dsta,src);
8858: }}}m68k_incpc(2);
8859: return 8;
8860: }
8861: unsigned long REGPARAM2 CPUFUNC(op_30c8_0)(uae_u32 opcode) /* MOVE */
8862: {
8863: uae_u32 srcreg = (opcode & 7);
8864: uae_u32 dstreg = (opcode >> 9) & 7;
8865: OpcodeFamily = 30; CurrentInstrCycles = 8;
8866: {{ uae_s16 src = m68k_areg(regs, srcreg);
8867: { uaecptr dsta = m68k_areg(regs, dstreg);
8868: m68k_areg(regs, dstreg) += 2;
8869: CLEAR_CZNV;
8870: SET_ZFLG (((uae_s16)(src)) == 0);
8871: SET_NFLG (((uae_s16)(src)) < 0);
8872: put_word(dsta,src);
8873: }}}m68k_incpc(2);
8874: return 8;
8875: }
8876: unsigned long REGPARAM2 CPUFUNC(op_30d0_0)(uae_u32 opcode) /* MOVE */
8877: {
8878: uae_u32 srcreg = (opcode & 7);
8879: uae_u32 dstreg = (opcode >> 9) & 7;
8880: OpcodeFamily = 30; CurrentInstrCycles = 12;
8881: {{ uaecptr srca = m68k_areg(regs, srcreg);
8882: { uae_s16 src = get_word(srca);
8883: { uaecptr dsta = m68k_areg(regs, dstreg);
8884: m68k_areg(regs, dstreg) += 2;
8885: CLEAR_CZNV;
8886: SET_ZFLG (((uae_s16)(src)) == 0);
8887: SET_NFLG (((uae_s16)(src)) < 0);
8888: put_word(dsta,src);
8889: }}}}m68k_incpc(2);
8890: return 12;
8891: }
8892: unsigned long REGPARAM2 CPUFUNC(op_30d8_0)(uae_u32 opcode) /* MOVE */
8893: {
8894: uae_u32 srcreg = (opcode & 7);
8895: uae_u32 dstreg = (opcode >> 9) & 7;
8896: OpcodeFamily = 30; CurrentInstrCycles = 12;
8897: {{ uaecptr srca = m68k_areg(regs, srcreg);
8898: { uae_s16 src = get_word(srca);
8899: m68k_areg(regs, srcreg) += 2;
8900: { uaecptr dsta = m68k_areg(regs, dstreg);
8901: m68k_areg(regs, dstreg) += 2;
8902: CLEAR_CZNV;
8903: SET_ZFLG (((uae_s16)(src)) == 0);
8904: SET_NFLG (((uae_s16)(src)) < 0);
8905: put_word(dsta,src);
8906: }}}}m68k_incpc(2);
8907: return 12;
8908: }
8909: unsigned long REGPARAM2 CPUFUNC(op_30e0_0)(uae_u32 opcode) /* MOVE */
8910: {
8911: uae_u32 srcreg = (opcode & 7);
8912: uae_u32 dstreg = (opcode >> 9) & 7;
8913: OpcodeFamily = 30; CurrentInstrCycles = 14;
8914: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
8915: { uae_s16 src = get_word(srca);
8916: m68k_areg (regs, srcreg) = srca;
8917: { uaecptr dsta = m68k_areg(regs, dstreg);
8918: m68k_areg(regs, dstreg) += 2;
8919: CLEAR_CZNV;
8920: SET_ZFLG (((uae_s16)(src)) == 0);
8921: SET_NFLG (((uae_s16)(src)) < 0);
8922: put_word(dsta,src);
8923: }}}}m68k_incpc(2);
8924: return 14;
8925: }
8926: unsigned long REGPARAM2 CPUFUNC(op_30e8_0)(uae_u32 opcode) /* MOVE */
8927: {
8928: uae_u32 srcreg = (opcode & 7);
8929: uae_u32 dstreg = (opcode >> 9) & 7;
8930: OpcodeFamily = 30; CurrentInstrCycles = 16;
8931: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
8932: { uae_s16 src = get_word(srca);
8933: { uaecptr dsta = m68k_areg(regs, dstreg);
8934: m68k_areg(regs, dstreg) += 2;
8935: CLEAR_CZNV;
8936: SET_ZFLG (((uae_s16)(src)) == 0);
8937: SET_NFLG (((uae_s16)(src)) < 0);
8938: put_word(dsta,src);
8939: }}}}m68k_incpc(4);
8940: return 16;
8941: }
8942: unsigned long REGPARAM2 CPUFUNC(op_30f0_0)(uae_u32 opcode) /* MOVE */
8943: {
8944: uae_u32 srcreg = (opcode & 7);
8945: uae_u32 dstreg = (opcode >> 9) & 7;
8946: OpcodeFamily = 30; CurrentInstrCycles = 18;
8947: {{m68k_incpc(2);
8948: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
8949: BusCyclePenalty += 2;
8950: { uae_s16 src = get_word(srca);
8951: { uaecptr dsta = m68k_areg(regs, dstreg);
8952: m68k_areg(regs, dstreg) += 2;
8953: CLEAR_CZNV;
8954: SET_ZFLG (((uae_s16)(src)) == 0);
8955: SET_NFLG (((uae_s16)(src)) < 0);
8956: put_word(dsta,src);
8957: }}}}}return 18;
8958: }
8959: unsigned long REGPARAM2 CPUFUNC(op_30f8_0)(uae_u32 opcode) /* MOVE */
8960: {
8961: uae_u32 dstreg = (opcode >> 9) & 7;
8962: OpcodeFamily = 30; CurrentInstrCycles = 16;
8963: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
8964: { uae_s16 src = get_word(srca);
8965: { uaecptr dsta = m68k_areg(regs, dstreg);
8966: m68k_areg(regs, dstreg) += 2;
8967: CLEAR_CZNV;
8968: SET_ZFLG (((uae_s16)(src)) == 0);
8969: SET_NFLG (((uae_s16)(src)) < 0);
8970: put_word(dsta,src);
8971: }}}}m68k_incpc(4);
8972: return 16;
8973: }
8974: unsigned long REGPARAM2 CPUFUNC(op_30f9_0)(uae_u32 opcode) /* MOVE */
8975: {
8976: uae_u32 dstreg = (opcode >> 9) & 7;
8977: OpcodeFamily = 30; CurrentInstrCycles = 20;
8978: {{ uaecptr srca = get_ilong(2);
8979: { uae_s16 src = get_word(srca);
8980: { uaecptr dsta = m68k_areg(regs, dstreg);
8981: m68k_areg(regs, dstreg) += 2;
8982: CLEAR_CZNV;
8983: SET_ZFLG (((uae_s16)(src)) == 0);
8984: SET_NFLG (((uae_s16)(src)) < 0);
8985: put_word(dsta,src);
8986: }}}}m68k_incpc(6);
8987: return 20;
8988: }
8989: unsigned long REGPARAM2 CPUFUNC(op_30fa_0)(uae_u32 opcode) /* MOVE */
8990: {
8991: uae_u32 dstreg = (opcode >> 9) & 7;
8992: OpcodeFamily = 30; CurrentInstrCycles = 16;
8993: {{ uaecptr srca = m68k_getpc () + 2;
8994: srca += (uae_s32)(uae_s16)get_iword(2);
8995: { uae_s16 src = get_word(srca);
8996: { uaecptr dsta = m68k_areg(regs, dstreg);
8997: m68k_areg(regs, dstreg) += 2;
8998: CLEAR_CZNV;
8999: SET_ZFLG (((uae_s16)(src)) == 0);
9000: SET_NFLG (((uae_s16)(src)) < 0);
9001: put_word(dsta,src);
9002: }}}}m68k_incpc(4);
9003: return 16;
9004: }
9005: unsigned long REGPARAM2 CPUFUNC(op_30fb_0)(uae_u32 opcode) /* MOVE */
9006: {
9007: uae_u32 dstreg = (opcode >> 9) & 7;
9008: OpcodeFamily = 30; CurrentInstrCycles = 18;
9009: {{m68k_incpc(2);
9010: { uaecptr tmppc = m68k_getpc();
9011: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
9012: BusCyclePenalty += 2;
9013: { uae_s16 src = get_word(srca);
9014: { uaecptr dsta = m68k_areg(regs, dstreg);
9015: m68k_areg(regs, dstreg) += 2;
9016: CLEAR_CZNV;
9017: SET_ZFLG (((uae_s16)(src)) == 0);
9018: SET_NFLG (((uae_s16)(src)) < 0);
9019: put_word(dsta,src);
9020: }}}}}return 18;
9021: }
9022: unsigned long REGPARAM2 CPUFUNC(op_30fc_0)(uae_u32 opcode) /* MOVE */
9023: {
9024: uae_u32 dstreg = (opcode >> 9) & 7;
9025: OpcodeFamily = 30; CurrentInstrCycles = 12;
9026: {{ uae_s16 src = get_iword(2);
9027: { uaecptr dsta = m68k_areg(regs, dstreg);
9028: m68k_areg(regs, dstreg) += 2;
9029: CLEAR_CZNV;
9030: SET_ZFLG (((uae_s16)(src)) == 0);
9031: SET_NFLG (((uae_s16)(src)) < 0);
9032: put_word(dsta,src);
9033: }}}m68k_incpc(4);
9034: return 12;
9035: }
9036: unsigned long REGPARAM2 CPUFUNC(op_3100_0)(uae_u32 opcode) /* MOVE */
9037: {
9038: uae_u32 srcreg = (opcode & 7);
9039: uae_u32 dstreg = (opcode >> 9) & 7;
9040: OpcodeFamily = 30; CurrentInstrCycles = 8;
9041: {{ uae_s16 src = m68k_dreg(regs, srcreg);
9042: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9043: m68k_areg (regs, dstreg) = dsta;
9044: CLEAR_CZNV;
9045: SET_ZFLG (((uae_s16)(src)) == 0);
9046: SET_NFLG (((uae_s16)(src)) < 0);
9047: put_word(dsta,src);
9048: }}}m68k_incpc(2);
9049: return 8;
9050: }
9051: unsigned long REGPARAM2 CPUFUNC(op_3108_0)(uae_u32 opcode) /* MOVE */
9052: {
9053: uae_u32 srcreg = (opcode & 7);
9054: uae_u32 dstreg = (opcode >> 9) & 7;
9055: OpcodeFamily = 30; CurrentInstrCycles = 8;
9056: {{ uae_s16 src = m68k_areg(regs, srcreg);
9057: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9058: m68k_areg (regs, dstreg) = dsta;
9059: CLEAR_CZNV;
9060: SET_ZFLG (((uae_s16)(src)) == 0);
9061: SET_NFLG (((uae_s16)(src)) < 0);
9062: put_word(dsta,src);
9063: }}}m68k_incpc(2);
9064: return 8;
9065: }
9066: unsigned long REGPARAM2 CPUFUNC(op_3110_0)(uae_u32 opcode) /* MOVE */
9067: {
9068: uae_u32 srcreg = (opcode & 7);
9069: uae_u32 dstreg = (opcode >> 9) & 7;
9070: OpcodeFamily = 30; CurrentInstrCycles = 12;
9071: {{ uaecptr srca = m68k_areg(regs, srcreg);
9072: { uae_s16 src = get_word(srca);
9073: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9074: m68k_areg (regs, dstreg) = dsta;
9075: CLEAR_CZNV;
9076: SET_ZFLG (((uae_s16)(src)) == 0);
9077: SET_NFLG (((uae_s16)(src)) < 0);
9078: put_word(dsta,src);
9079: }}}}m68k_incpc(2);
9080: return 12;
9081: }
9082: unsigned long REGPARAM2 CPUFUNC(op_3118_0)(uae_u32 opcode) /* MOVE */
9083: {
9084: uae_u32 srcreg = (opcode & 7);
9085: uae_u32 dstreg = (opcode >> 9) & 7;
9086: OpcodeFamily = 30; CurrentInstrCycles = 12;
9087: {{ uaecptr srca = m68k_areg(regs, srcreg);
9088: { uae_s16 src = get_word(srca);
9089: m68k_areg(regs, srcreg) += 2;
9090: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9091: m68k_areg (regs, dstreg) = dsta;
9092: CLEAR_CZNV;
9093: SET_ZFLG (((uae_s16)(src)) == 0);
9094: SET_NFLG (((uae_s16)(src)) < 0);
9095: put_word(dsta,src);
9096: }}}}m68k_incpc(2);
9097: return 12;
9098: }
9099: unsigned long REGPARAM2 CPUFUNC(op_3120_0)(uae_u32 opcode) /* MOVE */
9100: {
9101: uae_u32 srcreg = (opcode & 7);
9102: uae_u32 dstreg = (opcode >> 9) & 7;
9103: OpcodeFamily = 30; CurrentInstrCycles = 14;
9104: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
9105: { uae_s16 src = get_word(srca);
9106: m68k_areg (regs, srcreg) = srca;
9107: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9108: m68k_areg (regs, dstreg) = dsta;
9109: CLEAR_CZNV;
9110: SET_ZFLG (((uae_s16)(src)) == 0);
9111: SET_NFLG (((uae_s16)(src)) < 0);
9112: put_word(dsta,src);
9113: }}}}m68k_incpc(2);
9114: return 14;
9115: }
9116: unsigned long REGPARAM2 CPUFUNC(op_3128_0)(uae_u32 opcode) /* MOVE */
9117: {
9118: uae_u32 srcreg = (opcode & 7);
9119: uae_u32 dstreg = (opcode >> 9) & 7;
9120: OpcodeFamily = 30; CurrentInstrCycles = 16;
9121: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
9122: { uae_s16 src = get_word(srca);
9123: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9124: m68k_areg (regs, dstreg) = dsta;
9125: CLEAR_CZNV;
9126: SET_ZFLG (((uae_s16)(src)) == 0);
9127: SET_NFLG (((uae_s16)(src)) < 0);
9128: put_word(dsta,src);
9129: }}}}m68k_incpc(4);
9130: return 16;
9131: }
9132: unsigned long REGPARAM2 CPUFUNC(op_3130_0)(uae_u32 opcode) /* MOVE */
9133: {
9134: uae_u32 srcreg = (opcode & 7);
9135: uae_u32 dstreg = (opcode >> 9) & 7;
9136: OpcodeFamily = 30; CurrentInstrCycles = 18;
9137: {{m68k_incpc(2);
9138: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
9139: BusCyclePenalty += 2;
9140: { uae_s16 src = get_word(srca);
9141: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9142: m68k_areg (regs, dstreg) = dsta;
9143: CLEAR_CZNV;
9144: SET_ZFLG (((uae_s16)(src)) == 0);
9145: SET_NFLG (((uae_s16)(src)) < 0);
9146: put_word(dsta,src);
9147: }}}}}return 18;
9148: }
9149: unsigned long REGPARAM2 CPUFUNC(op_3138_0)(uae_u32 opcode) /* MOVE */
9150: {
9151: uae_u32 dstreg = (opcode >> 9) & 7;
9152: OpcodeFamily = 30; CurrentInstrCycles = 16;
9153: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
9154: { uae_s16 src = get_word(srca);
9155: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9156: m68k_areg (regs, dstreg) = dsta;
9157: CLEAR_CZNV;
9158: SET_ZFLG (((uae_s16)(src)) == 0);
9159: SET_NFLG (((uae_s16)(src)) < 0);
9160: put_word(dsta,src);
9161: }}}}m68k_incpc(4);
9162: return 16;
9163: }
9164: unsigned long REGPARAM2 CPUFUNC(op_3139_0)(uae_u32 opcode) /* MOVE */
9165: {
9166: uae_u32 dstreg = (opcode >> 9) & 7;
9167: OpcodeFamily = 30; CurrentInstrCycles = 20;
9168: {{ uaecptr srca = get_ilong(2);
9169: { uae_s16 src = get_word(srca);
9170: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9171: m68k_areg (regs, dstreg) = dsta;
9172: CLEAR_CZNV;
9173: SET_ZFLG (((uae_s16)(src)) == 0);
9174: SET_NFLG (((uae_s16)(src)) < 0);
9175: put_word(dsta,src);
9176: }}}}m68k_incpc(6);
9177: return 20;
9178: }
9179: unsigned long REGPARAM2 CPUFUNC(op_313a_0)(uae_u32 opcode) /* MOVE */
9180: {
9181: uae_u32 dstreg = (opcode >> 9) & 7;
9182: OpcodeFamily = 30; CurrentInstrCycles = 16;
9183: {{ uaecptr srca = m68k_getpc () + 2;
9184: srca += (uae_s32)(uae_s16)get_iword(2);
9185: { uae_s16 src = get_word(srca);
9186: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9187: m68k_areg (regs, dstreg) = dsta;
9188: CLEAR_CZNV;
9189: SET_ZFLG (((uae_s16)(src)) == 0);
9190: SET_NFLG (((uae_s16)(src)) < 0);
9191: put_word(dsta,src);
9192: }}}}m68k_incpc(4);
9193: return 16;
9194: }
9195: unsigned long REGPARAM2 CPUFUNC(op_313b_0)(uae_u32 opcode) /* MOVE */
9196: {
9197: uae_u32 dstreg = (opcode >> 9) & 7;
9198: OpcodeFamily = 30; CurrentInstrCycles = 18;
9199: {{m68k_incpc(2);
9200: { uaecptr tmppc = m68k_getpc();
9201: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
9202: BusCyclePenalty += 2;
9203: { uae_s16 src = get_word(srca);
9204: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9205: m68k_areg (regs, dstreg) = dsta;
9206: CLEAR_CZNV;
9207: SET_ZFLG (((uae_s16)(src)) == 0);
9208: SET_NFLG (((uae_s16)(src)) < 0);
9209: put_word(dsta,src);
9210: }}}}}return 18;
9211: }
9212: unsigned long REGPARAM2 CPUFUNC(op_313c_0)(uae_u32 opcode) /* MOVE */
9213: {
9214: uae_u32 dstreg = (opcode >> 9) & 7;
9215: OpcodeFamily = 30; CurrentInstrCycles = 12;
9216: {{ uae_s16 src = get_iword(2);
9217: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
9218: m68k_areg (regs, dstreg) = dsta;
9219: CLEAR_CZNV;
9220: SET_ZFLG (((uae_s16)(src)) == 0);
9221: SET_NFLG (((uae_s16)(src)) < 0);
9222: put_word(dsta,src);
9223: }}}m68k_incpc(4);
9224: return 12;
9225: }
9226: unsigned long REGPARAM2 CPUFUNC(op_3140_0)(uae_u32 opcode) /* MOVE */
9227: {
9228: uae_u32 srcreg = (opcode & 7);
9229: uae_u32 dstreg = (opcode >> 9) & 7;
9230: OpcodeFamily = 30; CurrentInstrCycles = 12;
9231: {{ uae_s16 src = m68k_dreg(regs, srcreg);
9232: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
9233: CLEAR_CZNV;
9234: SET_ZFLG (((uae_s16)(src)) == 0);
9235: SET_NFLG (((uae_s16)(src)) < 0);
9236: put_word(dsta,src);
9237: }}}m68k_incpc(4);
9238: return 12;
9239: }
9240: unsigned long REGPARAM2 CPUFUNC(op_3148_0)(uae_u32 opcode) /* MOVE */
9241: {
9242: uae_u32 srcreg = (opcode & 7);
9243: uae_u32 dstreg = (opcode >> 9) & 7;
9244: OpcodeFamily = 30; CurrentInstrCycles = 12;
9245: {{ uae_s16 src = m68k_areg(regs, srcreg);
9246: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
9247: CLEAR_CZNV;
9248: SET_ZFLG (((uae_s16)(src)) == 0);
9249: SET_NFLG (((uae_s16)(src)) < 0);
9250: put_word(dsta,src);
9251: }}}m68k_incpc(4);
9252: return 12;
9253: }
9254: unsigned long REGPARAM2 CPUFUNC(op_3150_0)(uae_u32 opcode) /* MOVE */
9255: {
9256: uae_u32 srcreg = (opcode & 7);
9257: uae_u32 dstreg = (opcode >> 9) & 7;
9258: OpcodeFamily = 30; CurrentInstrCycles = 16;
9259: {{ uaecptr srca = m68k_areg(regs, srcreg);
9260: { uae_s16 src = get_word(srca);
9261: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
9262: CLEAR_CZNV;
9263: SET_ZFLG (((uae_s16)(src)) == 0);
9264: SET_NFLG (((uae_s16)(src)) < 0);
9265: put_word(dsta,src);
9266: }}}}m68k_incpc(4);
9267: return 16;
9268: }
9269: unsigned long REGPARAM2 CPUFUNC(op_3158_0)(uae_u32 opcode) /* MOVE */
9270: {
9271: uae_u32 srcreg = (opcode & 7);
9272: uae_u32 dstreg = (opcode >> 9) & 7;
9273: OpcodeFamily = 30; CurrentInstrCycles = 16;
9274: {{ uaecptr srca = m68k_areg(regs, srcreg);
9275: { uae_s16 src = get_word(srca);
9276: m68k_areg(regs, srcreg) += 2;
9277: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
9278: CLEAR_CZNV;
9279: SET_ZFLG (((uae_s16)(src)) == 0);
9280: SET_NFLG (((uae_s16)(src)) < 0);
9281: put_word(dsta,src);
9282: }}}}m68k_incpc(4);
9283: return 16;
9284: }
9285: unsigned long REGPARAM2 CPUFUNC(op_3160_0)(uae_u32 opcode) /* MOVE */
9286: {
9287: uae_u32 srcreg = (opcode & 7);
9288: uae_u32 dstreg = (opcode >> 9) & 7;
9289: OpcodeFamily = 30; CurrentInstrCycles = 18;
9290: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
9291: { uae_s16 src = get_word(srca);
9292: m68k_areg (regs, srcreg) = srca;
9293: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
9294: CLEAR_CZNV;
9295: SET_ZFLG (((uae_s16)(src)) == 0);
9296: SET_NFLG (((uae_s16)(src)) < 0);
9297: put_word(dsta,src);
9298: }}}}m68k_incpc(4);
9299: return 18;
9300: }
9301: unsigned long REGPARAM2 CPUFUNC(op_3168_0)(uae_u32 opcode) /* MOVE */
9302: {
9303: uae_u32 srcreg = (opcode & 7);
9304: uae_u32 dstreg = (opcode >> 9) & 7;
9305: OpcodeFamily = 30; CurrentInstrCycles = 20;
9306: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
9307: { uae_s16 src = get_word(srca);
9308: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
9309: CLEAR_CZNV;
9310: SET_ZFLG (((uae_s16)(src)) == 0);
9311: SET_NFLG (((uae_s16)(src)) < 0);
9312: put_word(dsta,src);
9313: }}}}m68k_incpc(6);
9314: return 20;
9315: }
9316: unsigned long REGPARAM2 CPUFUNC(op_3170_0)(uae_u32 opcode) /* MOVE */
9317: {
9318: uae_u32 srcreg = (opcode & 7);
9319: uae_u32 dstreg = (opcode >> 9) & 7;
9320: OpcodeFamily = 30; CurrentInstrCycles = 22;
9321: {{m68k_incpc(2);
9322: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
9323: BusCyclePenalty += 2;
9324: { uae_s16 src = get_word(srca);
9325: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(0);
9326: CLEAR_CZNV;
9327: SET_ZFLG (((uae_s16)(src)) == 0);
9328: SET_NFLG (((uae_s16)(src)) < 0);
9329: put_word(dsta,src);
9330: }}}}}m68k_incpc(2);
9331: return 22;
9332: }
9333: unsigned long REGPARAM2 CPUFUNC(op_3178_0)(uae_u32 opcode) /* MOVE */
9334: {
9335: uae_u32 dstreg = (opcode >> 9) & 7;
9336: OpcodeFamily = 30; CurrentInstrCycles = 20;
9337: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
9338: { uae_s16 src = get_word(srca);
9339: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
9340: CLEAR_CZNV;
9341: SET_ZFLG (((uae_s16)(src)) == 0);
9342: SET_NFLG (((uae_s16)(src)) < 0);
9343: put_word(dsta,src);
9344: }}}}m68k_incpc(6);
9345: return 20;
9346: }
9347: unsigned long REGPARAM2 CPUFUNC(op_3179_0)(uae_u32 opcode) /* MOVE */
9348: {
9349: uae_u32 dstreg = (opcode >> 9) & 7;
9350: OpcodeFamily = 30; CurrentInstrCycles = 24;
9351: {{ uaecptr srca = get_ilong(2);
9352: { uae_s16 src = get_word(srca);
9353: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(6);
9354: CLEAR_CZNV;
9355: SET_ZFLG (((uae_s16)(src)) == 0);
9356: SET_NFLG (((uae_s16)(src)) < 0);
9357: put_word(dsta,src);
9358: }}}}m68k_incpc(8);
9359: return 24;
9360: }
9361: unsigned long REGPARAM2 CPUFUNC(op_317a_0)(uae_u32 opcode) /* MOVE */
9362: {
9363: uae_u32 dstreg = (opcode >> 9) & 7;
9364: OpcodeFamily = 30; CurrentInstrCycles = 20;
9365: {{ uaecptr srca = m68k_getpc () + 2;
9366: srca += (uae_s32)(uae_s16)get_iword(2);
9367: { uae_s16 src = get_word(srca);
9368: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
9369: CLEAR_CZNV;
9370: SET_ZFLG (((uae_s16)(src)) == 0);
9371: SET_NFLG (((uae_s16)(src)) < 0);
9372: put_word(dsta,src);
9373: }}}}m68k_incpc(6);
9374: return 20;
9375: }
9376: unsigned long REGPARAM2 CPUFUNC(op_317b_0)(uae_u32 opcode) /* MOVE */
9377: {
9378: uae_u32 dstreg = (opcode >> 9) & 7;
9379: OpcodeFamily = 30; CurrentInstrCycles = 22;
9380: {{m68k_incpc(2);
9381: { uaecptr tmppc = m68k_getpc();
9382: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
9383: BusCyclePenalty += 2;
9384: { uae_s16 src = get_word(srca);
9385: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(0);
9386: CLEAR_CZNV;
9387: SET_ZFLG (((uae_s16)(src)) == 0);
9388: SET_NFLG (((uae_s16)(src)) < 0);
9389: put_word(dsta,src);
9390: }}}}}m68k_incpc(2);
9391: return 22;
9392: }
9393: unsigned long REGPARAM2 CPUFUNC(op_317c_0)(uae_u32 opcode) /* MOVE */
9394: {
9395: uae_u32 dstreg = (opcode >> 9) & 7;
9396: OpcodeFamily = 30; CurrentInstrCycles = 16;
9397: {{ uae_s16 src = get_iword(2);
9398: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
9399: CLEAR_CZNV;
9400: SET_ZFLG (((uae_s16)(src)) == 0);
9401: SET_NFLG (((uae_s16)(src)) < 0);
9402: put_word(dsta,src);
9403: }}}m68k_incpc(6);
9404: return 16;
9405: }
9406: unsigned long REGPARAM2 CPUFUNC(op_3180_0)(uae_u32 opcode) /* MOVE */
9407: {
9408: uae_u32 srcreg = (opcode & 7);
9409: uae_u32 dstreg = (opcode >> 9) & 7;
9410: OpcodeFamily = 30; CurrentInstrCycles = 14;
9411: {{ uae_s16 src = m68k_dreg(regs, srcreg);
9412: {m68k_incpc(2);
9413: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9414: BusCyclePenalty += 2;
9415: CLEAR_CZNV;
9416: SET_ZFLG (((uae_s16)(src)) == 0);
9417: SET_NFLG (((uae_s16)(src)) < 0);
9418: put_word(dsta,src);
9419: }}}}return 14;
9420: }
9421: unsigned long REGPARAM2 CPUFUNC(op_3188_0)(uae_u32 opcode) /* MOVE */
9422: {
9423: uae_u32 srcreg = (opcode & 7);
9424: uae_u32 dstreg = (opcode >> 9) & 7;
9425: OpcodeFamily = 30; CurrentInstrCycles = 14;
9426: {{ uae_s16 src = m68k_areg(regs, srcreg);
9427: {m68k_incpc(2);
9428: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9429: BusCyclePenalty += 2;
9430: CLEAR_CZNV;
9431: SET_ZFLG (((uae_s16)(src)) == 0);
9432: SET_NFLG (((uae_s16)(src)) < 0);
9433: put_word(dsta,src);
9434: }}}}return 14;
9435: }
9436: unsigned long REGPARAM2 CPUFUNC(op_3190_0)(uae_u32 opcode) /* MOVE */
9437: {
9438: uae_u32 srcreg = (opcode & 7);
9439: uae_u32 dstreg = (opcode >> 9) & 7;
9440: OpcodeFamily = 30; CurrentInstrCycles = 18;
9441: {{ uaecptr srca = m68k_areg(regs, srcreg);
9442: { uae_s16 src = get_word(srca);
9443: {m68k_incpc(2);
9444: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9445: BusCyclePenalty += 2;
9446: CLEAR_CZNV;
9447: SET_ZFLG (((uae_s16)(src)) == 0);
9448: SET_NFLG (((uae_s16)(src)) < 0);
9449: put_word(dsta,src);
9450: }}}}}return 18;
9451: }
9452: unsigned long REGPARAM2 CPUFUNC(op_3198_0)(uae_u32 opcode) /* MOVE */
9453: {
9454: uae_u32 srcreg = (opcode & 7);
9455: uae_u32 dstreg = (opcode >> 9) & 7;
9456: OpcodeFamily = 30; CurrentInstrCycles = 18;
9457: {{ uaecptr srca = m68k_areg(regs, srcreg);
9458: { uae_s16 src = get_word(srca);
9459: m68k_areg(regs, srcreg) += 2;
9460: {m68k_incpc(2);
9461: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9462: BusCyclePenalty += 2;
9463: CLEAR_CZNV;
9464: SET_ZFLG (((uae_s16)(src)) == 0);
9465: SET_NFLG (((uae_s16)(src)) < 0);
9466: put_word(dsta,src);
9467: }}}}}return 18;
9468: }
9469: unsigned long REGPARAM2 CPUFUNC(op_31a0_0)(uae_u32 opcode) /* MOVE */
9470: {
9471: uae_u32 srcreg = (opcode & 7);
9472: uae_u32 dstreg = (opcode >> 9) & 7;
9473: OpcodeFamily = 30; CurrentInstrCycles = 20;
9474: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
9475: { uae_s16 src = get_word(srca);
9476: m68k_areg (regs, srcreg) = srca;
9477: {m68k_incpc(2);
9478: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9479: BusCyclePenalty += 2;
9480: CLEAR_CZNV;
9481: SET_ZFLG (((uae_s16)(src)) == 0);
9482: SET_NFLG (((uae_s16)(src)) < 0);
9483: put_word(dsta,src);
9484: }}}}}return 20;
9485: }
9486: unsigned long REGPARAM2 CPUFUNC(op_31a8_0)(uae_u32 opcode) /* MOVE */
9487: {
9488: uae_u32 srcreg = (opcode & 7);
9489: uae_u32 dstreg = (opcode >> 9) & 7;
9490: OpcodeFamily = 30; CurrentInstrCycles = 22;
9491: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
9492: { uae_s16 src = get_word(srca);
9493: {m68k_incpc(4);
9494: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9495: BusCyclePenalty += 2;
9496: CLEAR_CZNV;
9497: SET_ZFLG (((uae_s16)(src)) == 0);
9498: SET_NFLG (((uae_s16)(src)) < 0);
9499: put_word(dsta,src);
9500: }}}}}return 22;
9501: }
9502: unsigned long REGPARAM2 CPUFUNC(op_31b0_0)(uae_u32 opcode) /* MOVE */
9503: {
9504: uae_u32 srcreg = (opcode & 7);
9505: uae_u32 dstreg = (opcode >> 9) & 7;
9506: OpcodeFamily = 30; CurrentInstrCycles = 24;
9507: {{m68k_incpc(2);
9508: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
9509: BusCyclePenalty += 2;
9510: { uae_s16 src = get_word(srca);
9511: {{ uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9512: BusCyclePenalty += 2;
9513: CLEAR_CZNV;
9514: SET_ZFLG (((uae_s16)(src)) == 0);
9515: SET_NFLG (((uae_s16)(src)) < 0);
9516: put_word(dsta,src);
9517: }}}}}}return 24;
9518: }
9519: unsigned long REGPARAM2 CPUFUNC(op_31b8_0)(uae_u32 opcode) /* MOVE */
9520: {
9521: uae_u32 dstreg = (opcode >> 9) & 7;
9522: OpcodeFamily = 30; CurrentInstrCycles = 22;
9523: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
9524: { uae_s16 src = get_word(srca);
9525: {m68k_incpc(4);
9526: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9527: BusCyclePenalty += 2;
9528: CLEAR_CZNV;
9529: SET_ZFLG (((uae_s16)(src)) == 0);
9530: SET_NFLG (((uae_s16)(src)) < 0);
9531: put_word(dsta,src);
9532: }}}}}return 22;
9533: }
9534: unsigned long REGPARAM2 CPUFUNC(op_31b9_0)(uae_u32 opcode) /* MOVE */
9535: {
9536: uae_u32 dstreg = (opcode >> 9) & 7;
9537: OpcodeFamily = 30; CurrentInstrCycles = 26;
9538: {{ uaecptr srca = get_ilong(2);
9539: { uae_s16 src = get_word(srca);
9540: {m68k_incpc(6);
9541: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9542: BusCyclePenalty += 2;
9543: CLEAR_CZNV;
9544: SET_ZFLG (((uae_s16)(src)) == 0);
9545: SET_NFLG (((uae_s16)(src)) < 0);
9546: put_word(dsta,src);
9547: }}}}}return 26;
9548: }
9549: unsigned long REGPARAM2 CPUFUNC(op_31ba_0)(uae_u32 opcode) /* MOVE */
9550: {
9551: uae_u32 dstreg = (opcode >> 9) & 7;
9552: OpcodeFamily = 30; CurrentInstrCycles = 22;
9553: {{ uaecptr srca = m68k_getpc () + 2;
9554: srca += (uae_s32)(uae_s16)get_iword(2);
9555: { uae_s16 src = get_word(srca);
9556: {m68k_incpc(4);
9557: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9558: BusCyclePenalty += 2;
9559: CLEAR_CZNV;
9560: SET_ZFLG (((uae_s16)(src)) == 0);
9561: SET_NFLG (((uae_s16)(src)) < 0);
9562: put_word(dsta,src);
9563: }}}}}return 22;
9564: }
9565: unsigned long REGPARAM2 CPUFUNC(op_31bb_0)(uae_u32 opcode) /* MOVE */
9566: {
9567: uae_u32 dstreg = (opcode >> 9) & 7;
9568: OpcodeFamily = 30; CurrentInstrCycles = 24;
9569: {{m68k_incpc(2);
9570: { uaecptr tmppc = m68k_getpc();
9571: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
9572: BusCyclePenalty += 2;
9573: { uae_s16 src = get_word(srca);
9574: {{ uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9575: BusCyclePenalty += 2;
9576: CLEAR_CZNV;
9577: SET_ZFLG (((uae_s16)(src)) == 0);
9578: SET_NFLG (((uae_s16)(src)) < 0);
9579: put_word(dsta,src);
9580: }}}}}}return 24;
9581: }
9582: unsigned long REGPARAM2 CPUFUNC(op_31bc_0)(uae_u32 opcode) /* MOVE */
9583: {
9584: uae_u32 dstreg = (opcode >> 9) & 7;
9585: OpcodeFamily = 30; CurrentInstrCycles = 18;
9586: {{ uae_s16 src = get_iword(2);
9587: {m68k_incpc(4);
9588: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
9589: BusCyclePenalty += 2;
9590: CLEAR_CZNV;
9591: SET_ZFLG (((uae_s16)(src)) == 0);
9592: SET_NFLG (((uae_s16)(src)) < 0);
9593: put_word(dsta,src);
9594: }}}}return 18;
9595: }
9596: unsigned long REGPARAM2 CPUFUNC(op_31c0_0)(uae_u32 opcode) /* MOVE */
9597: {
9598: uae_u32 srcreg = (opcode & 7);
9599: OpcodeFamily = 30; CurrentInstrCycles = 12;
9600: {{ uae_s16 src = m68k_dreg(regs, srcreg);
9601: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
9602: CLEAR_CZNV;
9603: SET_ZFLG (((uae_s16)(src)) == 0);
9604: SET_NFLG (((uae_s16)(src)) < 0);
9605: put_word(dsta,src);
9606: }}}m68k_incpc(4);
9607: return 12;
9608: }
9609: unsigned long REGPARAM2 CPUFUNC(op_31c8_0)(uae_u32 opcode) /* MOVE */
9610: {
9611: uae_u32 srcreg = (opcode & 7);
9612: OpcodeFamily = 30; CurrentInstrCycles = 12;
9613: {{ uae_s16 src = m68k_areg(regs, srcreg);
9614: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
9615: CLEAR_CZNV;
9616: SET_ZFLG (((uae_s16)(src)) == 0);
9617: SET_NFLG (((uae_s16)(src)) < 0);
9618: put_word(dsta,src);
9619: }}}m68k_incpc(4);
9620: return 12;
9621: }
9622: unsigned long REGPARAM2 CPUFUNC(op_31d0_0)(uae_u32 opcode) /* MOVE */
9623: {
9624: uae_u32 srcreg = (opcode & 7);
9625: OpcodeFamily = 30; CurrentInstrCycles = 16;
9626: {{ uaecptr srca = m68k_areg(regs, srcreg);
9627: { uae_s16 src = get_word(srca);
9628: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
9629: CLEAR_CZNV;
9630: SET_ZFLG (((uae_s16)(src)) == 0);
9631: SET_NFLG (((uae_s16)(src)) < 0);
9632: put_word(dsta,src);
9633: }}}}m68k_incpc(4);
9634: return 16;
9635: }
9636: unsigned long REGPARAM2 CPUFUNC(op_31d8_0)(uae_u32 opcode) /* MOVE */
9637: {
9638: uae_u32 srcreg = (opcode & 7);
9639: OpcodeFamily = 30; CurrentInstrCycles = 16;
9640: {{ uaecptr srca = m68k_areg(regs, srcreg);
9641: { uae_s16 src = get_word(srca);
9642: m68k_areg(regs, srcreg) += 2;
9643: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
9644: CLEAR_CZNV;
9645: SET_ZFLG (((uae_s16)(src)) == 0);
9646: SET_NFLG (((uae_s16)(src)) < 0);
9647: put_word(dsta,src);
9648: }}}}m68k_incpc(4);
9649: return 16;
9650: }
9651: unsigned long REGPARAM2 CPUFUNC(op_31e0_0)(uae_u32 opcode) /* MOVE */
9652: {
9653: uae_u32 srcreg = (opcode & 7);
9654: OpcodeFamily = 30; CurrentInstrCycles = 18;
9655: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
9656: { uae_s16 src = get_word(srca);
9657: m68k_areg (regs, srcreg) = srca;
9658: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
9659: CLEAR_CZNV;
9660: SET_ZFLG (((uae_s16)(src)) == 0);
9661: SET_NFLG (((uae_s16)(src)) < 0);
9662: put_word(dsta,src);
9663: }}}}m68k_incpc(4);
9664: return 18;
9665: }
9666: unsigned long REGPARAM2 CPUFUNC(op_31e8_0)(uae_u32 opcode) /* MOVE */
9667: {
9668: uae_u32 srcreg = (opcode & 7);
9669: OpcodeFamily = 30; CurrentInstrCycles = 20;
9670: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
9671: { uae_s16 src = get_word(srca);
9672: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
9673: CLEAR_CZNV;
9674: SET_ZFLG (((uae_s16)(src)) == 0);
9675: SET_NFLG (((uae_s16)(src)) < 0);
9676: put_word(dsta,src);
9677: }}}}m68k_incpc(6);
9678: return 20;
9679: }
9680: unsigned long REGPARAM2 CPUFUNC(op_31f0_0)(uae_u32 opcode) /* MOVE */
9681: {
9682: uae_u32 srcreg = (opcode & 7);
9683: OpcodeFamily = 30; CurrentInstrCycles = 22;
9684: {{m68k_incpc(2);
9685: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
9686: BusCyclePenalty += 2;
9687: { uae_s16 src = get_word(srca);
9688: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(0);
9689: CLEAR_CZNV;
9690: SET_ZFLG (((uae_s16)(src)) == 0);
9691: SET_NFLG (((uae_s16)(src)) < 0);
9692: put_word(dsta,src);
9693: }}}}}m68k_incpc(2);
9694: return 22;
9695: }
9696: unsigned long REGPARAM2 CPUFUNC(op_31f8_0)(uae_u32 opcode) /* MOVE */
9697: {
9698: OpcodeFamily = 30; CurrentInstrCycles = 20;
9699: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
9700: { uae_s16 src = get_word(srca);
9701: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
9702: CLEAR_CZNV;
9703: SET_ZFLG (((uae_s16)(src)) == 0);
9704: SET_NFLG (((uae_s16)(src)) < 0);
9705: put_word(dsta,src);
9706: }}}}m68k_incpc(6);
9707: return 20;
9708: }
9709: unsigned long REGPARAM2 CPUFUNC(op_31f9_0)(uae_u32 opcode) /* MOVE */
9710: {
9711: OpcodeFamily = 30; CurrentInstrCycles = 24;
9712: {{ uaecptr srca = get_ilong(2);
9713: { uae_s16 src = get_word(srca);
9714: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(6);
9715: CLEAR_CZNV;
9716: SET_ZFLG (((uae_s16)(src)) == 0);
9717: SET_NFLG (((uae_s16)(src)) < 0);
9718: put_word(dsta,src);
9719: }}}}m68k_incpc(8);
9720: return 24;
9721: }
9722: unsigned long REGPARAM2 CPUFUNC(op_31fa_0)(uae_u32 opcode) /* MOVE */
9723: {
9724: OpcodeFamily = 30; CurrentInstrCycles = 20;
9725: {{ uaecptr srca = m68k_getpc () + 2;
9726: srca += (uae_s32)(uae_s16)get_iword(2);
9727: { uae_s16 src = get_word(srca);
9728: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
9729: CLEAR_CZNV;
9730: SET_ZFLG (((uae_s16)(src)) == 0);
9731: SET_NFLG (((uae_s16)(src)) < 0);
9732: put_word(dsta,src);
9733: }}}}m68k_incpc(6);
9734: return 20;
9735: }
9736: unsigned long REGPARAM2 CPUFUNC(op_31fb_0)(uae_u32 opcode) /* MOVE */
9737: {
9738: OpcodeFamily = 30; CurrentInstrCycles = 22;
9739: {{m68k_incpc(2);
9740: { uaecptr tmppc = m68k_getpc();
9741: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
9742: BusCyclePenalty += 2;
9743: { uae_s16 src = get_word(srca);
9744: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(0);
9745: CLEAR_CZNV;
9746: SET_ZFLG (((uae_s16)(src)) == 0);
9747: SET_NFLG (((uae_s16)(src)) < 0);
9748: put_word(dsta,src);
9749: }}}}}m68k_incpc(2);
9750: return 22;
9751: }
9752: unsigned long REGPARAM2 CPUFUNC(op_31fc_0)(uae_u32 opcode) /* MOVE */
9753: {
9754: OpcodeFamily = 30; CurrentInstrCycles = 16;
9755: {{ uae_s16 src = get_iword(2);
9756: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
9757: CLEAR_CZNV;
9758: SET_ZFLG (((uae_s16)(src)) == 0);
9759: SET_NFLG (((uae_s16)(src)) < 0);
9760: put_word(dsta,src);
9761: }}}m68k_incpc(6);
9762: return 16;
9763: }
9764: unsigned long REGPARAM2 CPUFUNC(op_33c0_0)(uae_u32 opcode) /* MOVE */
9765: {
9766: uae_u32 srcreg = (opcode & 7);
9767: OpcodeFamily = 30; CurrentInstrCycles = 16;
9768: {{ uae_s16 src = m68k_dreg(regs, srcreg);
9769: { uaecptr dsta = get_ilong(2);
9770: CLEAR_CZNV;
9771: SET_ZFLG (((uae_s16)(src)) == 0);
9772: SET_NFLG (((uae_s16)(src)) < 0);
9773: put_word(dsta,src);
9774: }}}m68k_incpc(6);
9775: return 16;
9776: }
9777: unsigned long REGPARAM2 CPUFUNC(op_33c8_0)(uae_u32 opcode) /* MOVE */
9778: {
9779: uae_u32 srcreg = (opcode & 7);
9780: OpcodeFamily = 30; CurrentInstrCycles = 16;
9781: {{ uae_s16 src = m68k_areg(regs, srcreg);
9782: { uaecptr dsta = get_ilong(2);
9783: CLEAR_CZNV;
9784: SET_ZFLG (((uae_s16)(src)) == 0);
9785: SET_NFLG (((uae_s16)(src)) < 0);
9786: put_word(dsta,src);
9787: }}}m68k_incpc(6);
9788: return 16;
9789: }
9790: unsigned long REGPARAM2 CPUFUNC(op_33d0_0)(uae_u32 opcode) /* MOVE */
9791: {
9792: uae_u32 srcreg = (opcode & 7);
9793: OpcodeFamily = 30; CurrentInstrCycles = 20;
9794: {{ uaecptr srca = m68k_areg(regs, srcreg);
9795: { uae_s16 src = get_word(srca);
9796: { uaecptr dsta = get_ilong(2);
9797: CLEAR_CZNV;
9798: SET_ZFLG (((uae_s16)(src)) == 0);
9799: SET_NFLG (((uae_s16)(src)) < 0);
9800: put_word(dsta,src);
9801: }}}}m68k_incpc(6);
9802: return 20;
9803: }
9804: unsigned long REGPARAM2 CPUFUNC(op_33d8_0)(uae_u32 opcode) /* MOVE */
9805: {
9806: uae_u32 srcreg = (opcode & 7);
9807: OpcodeFamily = 30; CurrentInstrCycles = 20;
9808: {{ uaecptr srca = m68k_areg(regs, srcreg);
9809: { uae_s16 src = get_word(srca);
9810: m68k_areg(regs, srcreg) += 2;
9811: { uaecptr dsta = get_ilong(2);
9812: CLEAR_CZNV;
9813: SET_ZFLG (((uae_s16)(src)) == 0);
9814: SET_NFLG (((uae_s16)(src)) < 0);
9815: put_word(dsta,src);
9816: }}}}m68k_incpc(6);
9817: return 20;
9818: }
9819: unsigned long REGPARAM2 CPUFUNC(op_33e0_0)(uae_u32 opcode) /* MOVE */
9820: {
9821: uae_u32 srcreg = (opcode & 7);
9822: OpcodeFamily = 30; CurrentInstrCycles = 22;
9823: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
9824: { uae_s16 src = get_word(srca);
9825: m68k_areg (regs, srcreg) = srca;
9826: { uaecptr dsta = get_ilong(2);
9827: CLEAR_CZNV;
9828: SET_ZFLG (((uae_s16)(src)) == 0);
9829: SET_NFLG (((uae_s16)(src)) < 0);
9830: put_word(dsta,src);
9831: }}}}m68k_incpc(6);
9832: return 22;
9833: }
9834: unsigned long REGPARAM2 CPUFUNC(op_33e8_0)(uae_u32 opcode) /* MOVE */
9835: {
9836: uae_u32 srcreg = (opcode & 7);
9837: OpcodeFamily = 30; CurrentInstrCycles = 24;
9838: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
9839: { uae_s16 src = get_word(srca);
9840: { uaecptr dsta = get_ilong(4);
9841: CLEAR_CZNV;
9842: SET_ZFLG (((uae_s16)(src)) == 0);
9843: SET_NFLG (((uae_s16)(src)) < 0);
9844: put_word(dsta,src);
9845: }}}}m68k_incpc(8);
9846: return 24;
9847: }
9848: unsigned long REGPARAM2 CPUFUNC(op_33f0_0)(uae_u32 opcode) /* MOVE */
9849: {
9850: uae_u32 srcreg = (opcode & 7);
9851: OpcodeFamily = 30; CurrentInstrCycles = 26;
9852: {{m68k_incpc(2);
9853: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
9854: BusCyclePenalty += 2;
9855: { uae_s16 src = get_word(srca);
9856: { uaecptr dsta = get_ilong(0);
9857: CLEAR_CZNV;
9858: SET_ZFLG (((uae_s16)(src)) == 0);
9859: SET_NFLG (((uae_s16)(src)) < 0);
9860: put_word(dsta,src);
9861: }}}}}m68k_incpc(4);
9862: return 26;
9863: }
9864: unsigned long REGPARAM2 CPUFUNC(op_33f8_0)(uae_u32 opcode) /* MOVE */
9865: {
9866: OpcodeFamily = 30; CurrentInstrCycles = 24;
9867: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
9868: { uae_s16 src = get_word(srca);
9869: { uaecptr dsta = get_ilong(4);
9870: CLEAR_CZNV;
9871: SET_ZFLG (((uae_s16)(src)) == 0);
9872: SET_NFLG (((uae_s16)(src)) < 0);
9873: put_word(dsta,src);
9874: }}}}m68k_incpc(8);
9875: return 24;
9876: }
9877: unsigned long REGPARAM2 CPUFUNC(op_33f9_0)(uae_u32 opcode) /* MOVE */
9878: {
9879: OpcodeFamily = 30; CurrentInstrCycles = 28;
9880: {{ uaecptr srca = get_ilong(2);
9881: { uae_s16 src = get_word(srca);
9882: { uaecptr dsta = get_ilong(6);
9883: CLEAR_CZNV;
9884: SET_ZFLG (((uae_s16)(src)) == 0);
9885: SET_NFLG (((uae_s16)(src)) < 0);
9886: put_word(dsta,src);
9887: }}}}m68k_incpc(10);
9888: return 28;
9889: }
9890: unsigned long REGPARAM2 CPUFUNC(op_33fa_0)(uae_u32 opcode) /* MOVE */
9891: {
9892: OpcodeFamily = 30; CurrentInstrCycles = 24;
9893: {{ uaecptr srca = m68k_getpc () + 2;
9894: srca += (uae_s32)(uae_s16)get_iword(2);
9895: { uae_s16 src = get_word(srca);
9896: { uaecptr dsta = get_ilong(4);
9897: CLEAR_CZNV;
9898: SET_ZFLG (((uae_s16)(src)) == 0);
9899: SET_NFLG (((uae_s16)(src)) < 0);
9900: put_word(dsta,src);
9901: }}}}m68k_incpc(8);
9902: return 24;
9903: }
9904: unsigned long REGPARAM2 CPUFUNC(op_33fb_0)(uae_u32 opcode) /* MOVE */
9905: {
9906: OpcodeFamily = 30; CurrentInstrCycles = 26;
9907: {{m68k_incpc(2);
9908: { uaecptr tmppc = m68k_getpc();
9909: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
9910: BusCyclePenalty += 2;
9911: { uae_s16 src = get_word(srca);
9912: { uaecptr dsta = get_ilong(0);
9913: CLEAR_CZNV;
9914: SET_ZFLG (((uae_s16)(src)) == 0);
9915: SET_NFLG (((uae_s16)(src)) < 0);
9916: put_word(dsta,src);
9917: }}}}}m68k_incpc(4);
9918: return 26;
9919: }
9920: unsigned long REGPARAM2 CPUFUNC(op_33fc_0)(uae_u32 opcode) /* MOVE */
9921: {
9922: OpcodeFamily = 30; CurrentInstrCycles = 20;
9923: {{ uae_s16 src = get_iword(2);
9924: { uaecptr dsta = get_ilong(4);
9925: CLEAR_CZNV;
9926: SET_ZFLG (((uae_s16)(src)) == 0);
9927: SET_NFLG (((uae_s16)(src)) < 0);
9928: put_word(dsta,src);
9929: }}}m68k_incpc(8);
9930: return 20;
9931: }
9932: unsigned long REGPARAM2 CPUFUNC(op_4000_0)(uae_u32 opcode) /* NEGX */
9933: {
9934: uae_u32 srcreg = (opcode & 7);
9935: OpcodeFamily = 16; CurrentInstrCycles = 4;
9936: {{ uae_s8 src = m68k_dreg(regs, srcreg);
9937: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
9938: { int flgs = ((uae_s8)(src)) < 0;
9939: int flgo = ((uae_s8)(0)) < 0;
9940: int flgn = ((uae_s8)(newv)) < 0;
9941: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
9942: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
9943: COPY_CARRY;
9944: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
9945: SET_NFLG (((uae_s8)(newv)) < 0);
9946: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
9947: }}}}m68k_incpc(2);
9948: return 4;
9949: }
9950: unsigned long REGPARAM2 CPUFUNC(op_4010_0)(uae_u32 opcode) /* NEGX */
9951: {
9952: uae_u32 srcreg = (opcode & 7);
9953: OpcodeFamily = 16; CurrentInstrCycles = 12;
9954: {{ uaecptr srca = m68k_areg(regs, srcreg);
9955: { uae_s8 src = get_byte(srca);
9956: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
9957: { int flgs = ((uae_s8)(src)) < 0;
9958: int flgo = ((uae_s8)(0)) < 0;
9959: int flgn = ((uae_s8)(newv)) < 0;
9960: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
9961: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
9962: COPY_CARRY;
9963: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
9964: SET_NFLG (((uae_s8)(newv)) < 0);
9965: put_byte(srca,newv);
9966: }}}}}m68k_incpc(2);
9967: return 12;
9968: }
9969: unsigned long REGPARAM2 CPUFUNC(op_4018_0)(uae_u32 opcode) /* NEGX */
9970: {
9971: uae_u32 srcreg = (opcode & 7);
9972: OpcodeFamily = 16; CurrentInstrCycles = 12;
9973: {{ uaecptr srca = m68k_areg(regs, srcreg);
9974: { uae_s8 src = get_byte(srca);
9975: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
9976: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
9977: { int flgs = ((uae_s8)(src)) < 0;
9978: int flgo = ((uae_s8)(0)) < 0;
9979: int flgn = ((uae_s8)(newv)) < 0;
9980: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
9981: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
9982: COPY_CARRY;
9983: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
9984: SET_NFLG (((uae_s8)(newv)) < 0);
9985: put_byte(srca,newv);
9986: }}}}}m68k_incpc(2);
9987: return 12;
9988: }
9989: unsigned long REGPARAM2 CPUFUNC(op_4020_0)(uae_u32 opcode) /* NEGX */
9990: {
9991: uae_u32 srcreg = (opcode & 7);
9992: OpcodeFamily = 16; CurrentInstrCycles = 14;
9993: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
9994: { uae_s8 src = get_byte(srca);
9995: m68k_areg (regs, srcreg) = srca;
9996: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
9997: { int flgs = ((uae_s8)(src)) < 0;
9998: int flgo = ((uae_s8)(0)) < 0;
9999: int flgn = ((uae_s8)(newv)) < 0;
10000: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10001: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10002: COPY_CARRY;
10003: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
10004: SET_NFLG (((uae_s8)(newv)) < 0);
10005: put_byte(srca,newv);
10006: }}}}}m68k_incpc(2);
10007: return 14;
10008: }
10009: unsigned long REGPARAM2 CPUFUNC(op_4028_0)(uae_u32 opcode) /* NEGX */
10010: {
10011: uae_u32 srcreg = (opcode & 7);
10012: OpcodeFamily = 16; CurrentInstrCycles = 16;
10013: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
10014: { uae_s8 src = get_byte(srca);
10015: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10016: { int flgs = ((uae_s8)(src)) < 0;
10017: int flgo = ((uae_s8)(0)) < 0;
10018: int flgn = ((uae_s8)(newv)) < 0;
10019: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10020: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10021: COPY_CARRY;
10022: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
10023: SET_NFLG (((uae_s8)(newv)) < 0);
10024: put_byte(srca,newv);
10025: }}}}}m68k_incpc(4);
10026: return 16;
10027: }
10028: unsigned long REGPARAM2 CPUFUNC(op_4030_0)(uae_u32 opcode) /* NEGX */
10029: {
10030: uae_u32 srcreg = (opcode & 7);
10031: OpcodeFamily = 16; CurrentInstrCycles = 18;
10032: {{m68k_incpc(2);
10033: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
10034: BusCyclePenalty += 2;
10035: { uae_s8 src = get_byte(srca);
10036: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10037: { int flgs = ((uae_s8)(src)) < 0;
10038: int flgo = ((uae_s8)(0)) < 0;
10039: int flgn = ((uae_s8)(newv)) < 0;
10040: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10041: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10042: COPY_CARRY;
10043: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
10044: SET_NFLG (((uae_s8)(newv)) < 0);
10045: put_byte(srca,newv);
10046: }}}}}}return 18;
10047: }
10048: unsigned long REGPARAM2 CPUFUNC(op_4038_0)(uae_u32 opcode) /* NEGX */
10049: {
10050: OpcodeFamily = 16; CurrentInstrCycles = 16;
10051: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
10052: { uae_s8 src = get_byte(srca);
10053: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10054: { int flgs = ((uae_s8)(src)) < 0;
10055: int flgo = ((uae_s8)(0)) < 0;
10056: int flgn = ((uae_s8)(newv)) < 0;
10057: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10058: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10059: COPY_CARRY;
10060: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
10061: SET_NFLG (((uae_s8)(newv)) < 0);
10062: put_byte(srca,newv);
10063: }}}}}m68k_incpc(4);
10064: return 16;
10065: }
10066: unsigned long REGPARAM2 CPUFUNC(op_4039_0)(uae_u32 opcode) /* NEGX */
10067: {
10068: OpcodeFamily = 16; CurrentInstrCycles = 20;
10069: {{ uaecptr srca = get_ilong(2);
10070: { uae_s8 src = get_byte(srca);
10071: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10072: { int flgs = ((uae_s8)(src)) < 0;
10073: int flgo = ((uae_s8)(0)) < 0;
10074: int flgn = ((uae_s8)(newv)) < 0;
10075: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10076: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10077: COPY_CARRY;
10078: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
10079: SET_NFLG (((uae_s8)(newv)) < 0);
10080: put_byte(srca,newv);
10081: }}}}}m68k_incpc(6);
10082: return 20;
10083: }
10084: unsigned long REGPARAM2 CPUFUNC(op_4040_0)(uae_u32 opcode) /* NEGX */
10085: {
10086: uae_u32 srcreg = (opcode & 7);
10087: OpcodeFamily = 16; CurrentInstrCycles = 4;
10088: {{ uae_s16 src = m68k_dreg(regs, srcreg);
10089: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10090: { int flgs = ((uae_s16)(src)) < 0;
10091: int flgo = ((uae_s16)(0)) < 0;
10092: int flgn = ((uae_s16)(newv)) < 0;
10093: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10094: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10095: COPY_CARRY;
10096: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
10097: SET_NFLG (((uae_s16)(newv)) < 0);
10098: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
10099: }}}}m68k_incpc(2);
10100: return 4;
10101: }
10102: unsigned long REGPARAM2 CPUFUNC(op_4050_0)(uae_u32 opcode) /* NEGX */
10103: {
10104: uae_u32 srcreg = (opcode & 7);
10105: OpcodeFamily = 16; CurrentInstrCycles = 12;
10106: {{ uaecptr srca = m68k_areg(regs, srcreg);
10107: { uae_s16 src = get_word(srca);
10108: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10109: { int flgs = ((uae_s16)(src)) < 0;
10110: int flgo = ((uae_s16)(0)) < 0;
10111: int flgn = ((uae_s16)(newv)) < 0;
10112: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10113: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10114: COPY_CARRY;
10115: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
10116: SET_NFLG (((uae_s16)(newv)) < 0);
10117: put_word(srca,newv);
10118: }}}}}m68k_incpc(2);
10119: return 12;
10120: }
10121: unsigned long REGPARAM2 CPUFUNC(op_4058_0)(uae_u32 opcode) /* NEGX */
10122: {
10123: uae_u32 srcreg = (opcode & 7);
10124: OpcodeFamily = 16; CurrentInstrCycles = 12;
10125: {{ uaecptr srca = m68k_areg(regs, srcreg);
10126: { uae_s16 src = get_word(srca);
10127: m68k_areg(regs, srcreg) += 2;
10128: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10129: { int flgs = ((uae_s16)(src)) < 0;
10130: int flgo = ((uae_s16)(0)) < 0;
10131: int flgn = ((uae_s16)(newv)) < 0;
10132: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10133: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10134: COPY_CARRY;
10135: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
10136: SET_NFLG (((uae_s16)(newv)) < 0);
10137: put_word(srca,newv);
10138: }}}}}m68k_incpc(2);
10139: return 12;
10140: }
10141: unsigned long REGPARAM2 CPUFUNC(op_4060_0)(uae_u32 opcode) /* NEGX */
10142: {
10143: uae_u32 srcreg = (opcode & 7);
10144: OpcodeFamily = 16; CurrentInstrCycles = 14;
10145: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
10146: { uae_s16 src = get_word(srca);
10147: m68k_areg (regs, srcreg) = srca;
10148: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10149: { int flgs = ((uae_s16)(src)) < 0;
10150: int flgo = ((uae_s16)(0)) < 0;
10151: int flgn = ((uae_s16)(newv)) < 0;
10152: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10153: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10154: COPY_CARRY;
10155: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
10156: SET_NFLG (((uae_s16)(newv)) < 0);
10157: put_word(srca,newv);
10158: }}}}}m68k_incpc(2);
10159: return 14;
10160: }
10161: unsigned long REGPARAM2 CPUFUNC(op_4068_0)(uae_u32 opcode) /* NEGX */
10162: {
10163: uae_u32 srcreg = (opcode & 7);
10164: OpcodeFamily = 16; CurrentInstrCycles = 16;
10165: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
10166: { uae_s16 src = get_word(srca);
10167: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10168: { int flgs = ((uae_s16)(src)) < 0;
10169: int flgo = ((uae_s16)(0)) < 0;
10170: int flgn = ((uae_s16)(newv)) < 0;
10171: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10172: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10173: COPY_CARRY;
10174: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
10175: SET_NFLG (((uae_s16)(newv)) < 0);
10176: put_word(srca,newv);
10177: }}}}}m68k_incpc(4);
10178: return 16;
10179: }
10180: unsigned long REGPARAM2 CPUFUNC(op_4070_0)(uae_u32 opcode) /* NEGX */
10181: {
10182: uae_u32 srcreg = (opcode & 7);
10183: OpcodeFamily = 16; CurrentInstrCycles = 18;
10184: {{m68k_incpc(2);
10185: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
10186: BusCyclePenalty += 2;
10187: { uae_s16 src = get_word(srca);
10188: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10189: { int flgs = ((uae_s16)(src)) < 0;
10190: int flgo = ((uae_s16)(0)) < 0;
10191: int flgn = ((uae_s16)(newv)) < 0;
10192: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10193: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10194: COPY_CARRY;
10195: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
10196: SET_NFLG (((uae_s16)(newv)) < 0);
10197: put_word(srca,newv);
10198: }}}}}}return 18;
10199: }
10200: unsigned long REGPARAM2 CPUFUNC(op_4078_0)(uae_u32 opcode) /* NEGX */
10201: {
10202: OpcodeFamily = 16; CurrentInstrCycles = 16;
10203: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
10204: { uae_s16 src = get_word(srca);
10205: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10206: { int flgs = ((uae_s16)(src)) < 0;
10207: int flgo = ((uae_s16)(0)) < 0;
10208: int flgn = ((uae_s16)(newv)) < 0;
10209: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10210: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10211: COPY_CARRY;
10212: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
10213: SET_NFLG (((uae_s16)(newv)) < 0);
10214: put_word(srca,newv);
10215: }}}}}m68k_incpc(4);
10216: return 16;
10217: }
10218: unsigned long REGPARAM2 CPUFUNC(op_4079_0)(uae_u32 opcode) /* NEGX */
10219: {
10220: OpcodeFamily = 16; CurrentInstrCycles = 20;
10221: {{ uaecptr srca = get_ilong(2);
10222: { uae_s16 src = get_word(srca);
10223: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10224: { int flgs = ((uae_s16)(src)) < 0;
10225: int flgo = ((uae_s16)(0)) < 0;
10226: int flgn = ((uae_s16)(newv)) < 0;
10227: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10228: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10229: COPY_CARRY;
10230: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
10231: SET_NFLG (((uae_s16)(newv)) < 0);
10232: put_word(srca,newv);
10233: }}}}}m68k_incpc(6);
10234: return 20;
10235: }
10236: unsigned long REGPARAM2 CPUFUNC(op_4080_0)(uae_u32 opcode) /* NEGX */
10237: {
10238: uae_u32 srcreg = (opcode & 7);
10239: OpcodeFamily = 16; CurrentInstrCycles = 6;
10240: {{ uae_s32 src = m68k_dreg(regs, srcreg);
10241: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10242: { int flgs = ((uae_s32)(src)) < 0;
10243: int flgo = ((uae_s32)(0)) < 0;
10244: int flgn = ((uae_s32)(newv)) < 0;
10245: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10246: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10247: COPY_CARRY;
10248: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
10249: SET_NFLG (((uae_s32)(newv)) < 0);
10250: m68k_dreg(regs, srcreg) = (newv);
10251: }}}}m68k_incpc(2);
10252: return 6;
10253: }
10254: unsigned long REGPARAM2 CPUFUNC(op_4090_0)(uae_u32 opcode) /* NEGX */
10255: {
10256: uae_u32 srcreg = (opcode & 7);
10257: OpcodeFamily = 16; CurrentInstrCycles = 20;
10258: {{ uaecptr srca = m68k_areg(regs, srcreg);
10259: { uae_s32 src = get_long(srca);
10260: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10261: { int flgs = ((uae_s32)(src)) < 0;
10262: int flgo = ((uae_s32)(0)) < 0;
10263: int flgn = ((uae_s32)(newv)) < 0;
10264: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10265: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10266: COPY_CARRY;
10267: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
10268: SET_NFLG (((uae_s32)(newv)) < 0);
10269: put_long(srca,newv);
10270: }}}}}m68k_incpc(2);
10271: return 20;
10272: }
10273: unsigned long REGPARAM2 CPUFUNC(op_4098_0)(uae_u32 opcode) /* NEGX */
10274: {
10275: uae_u32 srcreg = (opcode & 7);
10276: OpcodeFamily = 16; CurrentInstrCycles = 20;
10277: {{ uaecptr srca = m68k_areg(regs, srcreg);
10278: { uae_s32 src = get_long(srca);
10279: m68k_areg(regs, srcreg) += 4;
10280: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10281: { int flgs = ((uae_s32)(src)) < 0;
10282: int flgo = ((uae_s32)(0)) < 0;
10283: int flgn = ((uae_s32)(newv)) < 0;
10284: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10285: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10286: COPY_CARRY;
10287: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
10288: SET_NFLG (((uae_s32)(newv)) < 0);
10289: put_long(srca,newv);
10290: }}}}}m68k_incpc(2);
10291: return 20;
10292: }
10293: unsigned long REGPARAM2 CPUFUNC(op_40a0_0)(uae_u32 opcode) /* NEGX */
10294: {
10295: uae_u32 srcreg = (opcode & 7);
10296: OpcodeFamily = 16; CurrentInstrCycles = 22;
10297: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
10298: { uae_s32 src = get_long(srca);
10299: m68k_areg (regs, srcreg) = srca;
10300: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10301: { int flgs = ((uae_s32)(src)) < 0;
10302: int flgo = ((uae_s32)(0)) < 0;
10303: int flgn = ((uae_s32)(newv)) < 0;
10304: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10305: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10306: COPY_CARRY;
10307: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
10308: SET_NFLG (((uae_s32)(newv)) < 0);
10309: put_long(srca,newv);
10310: }}}}}m68k_incpc(2);
10311: return 22;
10312: }
10313: unsigned long REGPARAM2 CPUFUNC(op_40a8_0)(uae_u32 opcode) /* NEGX */
10314: {
10315: uae_u32 srcreg = (opcode & 7);
10316: OpcodeFamily = 16; CurrentInstrCycles = 24;
10317: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
10318: { uae_s32 src = get_long(srca);
10319: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10320: { int flgs = ((uae_s32)(src)) < 0;
10321: int flgo = ((uae_s32)(0)) < 0;
10322: int flgn = ((uae_s32)(newv)) < 0;
10323: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10324: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10325: COPY_CARRY;
10326: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
10327: SET_NFLG (((uae_s32)(newv)) < 0);
10328: put_long(srca,newv);
10329: }}}}}m68k_incpc(4);
10330: return 24;
10331: }
10332: unsigned long REGPARAM2 CPUFUNC(op_40b0_0)(uae_u32 opcode) /* NEGX */
10333: {
10334: uae_u32 srcreg = (opcode & 7);
10335: OpcodeFamily = 16; CurrentInstrCycles = 26;
10336: {{m68k_incpc(2);
10337: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
10338: BusCyclePenalty += 2;
10339: { uae_s32 src = get_long(srca);
10340: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10341: { int flgs = ((uae_s32)(src)) < 0;
10342: int flgo = ((uae_s32)(0)) < 0;
10343: int flgn = ((uae_s32)(newv)) < 0;
10344: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10345: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10346: COPY_CARRY;
10347: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
10348: SET_NFLG (((uae_s32)(newv)) < 0);
10349: put_long(srca,newv);
10350: }}}}}}return 26;
10351: }
10352: unsigned long REGPARAM2 CPUFUNC(op_40b8_0)(uae_u32 opcode) /* NEGX */
10353: {
10354: OpcodeFamily = 16; CurrentInstrCycles = 24;
10355: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
10356: { uae_s32 src = get_long(srca);
10357: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10358: { int flgs = ((uae_s32)(src)) < 0;
10359: int flgo = ((uae_s32)(0)) < 0;
10360: int flgn = ((uae_s32)(newv)) < 0;
10361: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10362: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10363: COPY_CARRY;
10364: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
10365: SET_NFLG (((uae_s32)(newv)) < 0);
10366: put_long(srca,newv);
10367: }}}}}m68k_incpc(4);
10368: return 24;
10369: }
10370: unsigned long REGPARAM2 CPUFUNC(op_40b9_0)(uae_u32 opcode) /* NEGX */
10371: {
10372: OpcodeFamily = 16; CurrentInstrCycles = 28;
10373: {{ uaecptr srca = get_ilong(2);
10374: { uae_s32 src = get_long(srca);
10375: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
10376: { int flgs = ((uae_s32)(src)) < 0;
10377: int flgo = ((uae_s32)(0)) < 0;
10378: int flgn = ((uae_s32)(newv)) < 0;
10379: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
10380: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
10381: COPY_CARRY;
10382: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
10383: SET_NFLG (((uae_s32)(newv)) < 0);
10384: put_long(srca,newv);
10385: }}}}}m68k_incpc(6);
10386: return 28;
10387: }
10388: unsigned long REGPARAM2 CPUFUNC(op_40c0_0)(uae_u32 opcode) /* MVSR2 */
10389: {
10390: uae_u32 srcreg = (opcode & 7);
10391: OpcodeFamily = 32; CurrentInstrCycles = 6;
10392: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel653; }
10393: {{ MakeSR();
10394: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
10395: }}}m68k_incpc(2);
10396: endlabel653: ;
10397: return 6;
10398: }
10399: unsigned long REGPARAM2 CPUFUNC(op_40d0_0)(uae_u32 opcode) /* MVSR2 */
10400: {
10401: uae_u32 srcreg = (opcode & 7);
10402: OpcodeFamily = 32; CurrentInstrCycles = 12;
10403: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel654; }
10404: {{ uaecptr srca = m68k_areg(regs, srcreg);
10405: MakeSR();
10406: put_word(srca,regs.sr);
10407: }}}m68k_incpc(2);
10408: endlabel654: ;
10409: return 12;
10410: }
10411: unsigned long REGPARAM2 CPUFUNC(op_40d8_0)(uae_u32 opcode) /* MVSR2 */
10412: {
10413: uae_u32 srcreg = (opcode & 7);
10414: OpcodeFamily = 32; CurrentInstrCycles = 12;
10415: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel655; }
10416: {{ uaecptr srca = m68k_areg(regs, srcreg);
10417: m68k_areg(regs, srcreg) += 2;
10418: MakeSR();
10419: put_word(srca,regs.sr);
10420: }}}m68k_incpc(2);
10421: endlabel655: ;
10422: return 12;
10423: }
10424: unsigned long REGPARAM2 CPUFUNC(op_40e0_0)(uae_u32 opcode) /* MVSR2 */
10425: {
10426: uae_u32 srcreg = (opcode & 7);
10427: OpcodeFamily = 32; CurrentInstrCycles = 14;
10428: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel656; }
10429: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
10430: m68k_areg (regs, srcreg) = srca;
10431: MakeSR();
10432: put_word(srca,regs.sr);
10433: }}}m68k_incpc(2);
10434: endlabel656: ;
10435: return 14;
10436: }
10437: unsigned long REGPARAM2 CPUFUNC(op_40e8_0)(uae_u32 opcode) /* MVSR2 */
10438: {
10439: uae_u32 srcreg = (opcode & 7);
10440: OpcodeFamily = 32; CurrentInstrCycles = 16;
10441: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel657; }
10442: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
10443: MakeSR();
10444: put_word(srca,regs.sr);
10445: }}}m68k_incpc(4);
10446: endlabel657: ;
10447: return 16;
10448: }
10449: unsigned long REGPARAM2 CPUFUNC(op_40f0_0)(uae_u32 opcode) /* MVSR2 */
10450: {
10451: uae_u32 srcreg = (opcode & 7);
10452: OpcodeFamily = 32; CurrentInstrCycles = 18;
10453: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel658; }
10454: {{m68k_incpc(2);
10455: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
10456: BusCyclePenalty += 2;
10457: MakeSR();
10458: put_word(srca,regs.sr);
10459: }}}}endlabel658: ;
10460: return 18;
10461: }
10462: unsigned long REGPARAM2 CPUFUNC(op_40f8_0)(uae_u32 opcode) /* MVSR2 */
10463: {
10464: OpcodeFamily = 32; CurrentInstrCycles = 16;
10465: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel659; }
10466: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
10467: MakeSR();
10468: put_word(srca,regs.sr);
10469: }}}m68k_incpc(4);
10470: endlabel659: ;
10471: return 16;
10472: }
10473: unsigned long REGPARAM2 CPUFUNC(op_40f9_0)(uae_u32 opcode) /* MVSR2 */
10474: {
10475: OpcodeFamily = 32; CurrentInstrCycles = 20;
10476: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel660; }
10477: {{ uaecptr srca = get_ilong(2);
10478: MakeSR();
10479: put_word(srca,regs.sr);
10480: }}}m68k_incpc(6);
10481: endlabel660: ;
10482: return 20;
10483: }
10484: unsigned long REGPARAM2 CPUFUNC(op_4100_0)(uae_u32 opcode) /* CHK */
10485: {
10486: uae_u32 srcreg = (opcode & 7);
10487: uae_u32 dstreg = (opcode >> 9) & 7;
10488: OpcodeFamily = 80; CurrentInstrCycles = 10;
10489: { uaecptr oldpc = m68k_getpc();
10490: { uae_s32 src = m68k_dreg(regs, srcreg);
10491: { uae_s32 dst = m68k_dreg(regs, dstreg);
10492: m68k_incpc(2);
10493: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel661; }
10494: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel661; }
10495: }}}endlabel661: ;
10496: return 10;
10497: }
10498: unsigned long REGPARAM2 CPUFUNC(op_4110_0)(uae_u32 opcode) /* CHK */
10499: {
10500: uae_u32 srcreg = (opcode & 7);
10501: uae_u32 dstreg = (opcode >> 9) & 7;
10502: OpcodeFamily = 80; CurrentInstrCycles = 18;
10503: { uaecptr oldpc = m68k_getpc();
10504: { uaecptr srca = m68k_areg(regs, srcreg);
10505: { uae_s32 src = get_long(srca);
10506: { uae_s32 dst = m68k_dreg(regs, dstreg);
10507: m68k_incpc(2);
10508: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel662; }
10509: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel662; }
10510: }}}}endlabel662: ;
10511: return 18;
10512: }
10513: unsigned long REGPARAM2 CPUFUNC(op_4118_0)(uae_u32 opcode) /* CHK */
10514: {
10515: uae_u32 srcreg = (opcode & 7);
10516: uae_u32 dstreg = (opcode >> 9) & 7;
10517: OpcodeFamily = 80; CurrentInstrCycles = 18;
10518: { uaecptr oldpc = m68k_getpc();
10519: { uaecptr srca = m68k_areg(regs, srcreg);
10520: { uae_s32 src = get_long(srca);
10521: m68k_areg(regs, srcreg) += 4;
10522: { uae_s32 dst = m68k_dreg(regs, dstreg);
10523: m68k_incpc(2);
10524: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel663; }
10525: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel663; }
10526: }}}}endlabel663: ;
10527: return 18;
10528: }
10529: unsigned long REGPARAM2 CPUFUNC(op_4120_0)(uae_u32 opcode) /* CHK */
10530: {
10531: uae_u32 srcreg = (opcode & 7);
10532: uae_u32 dstreg = (opcode >> 9) & 7;
10533: OpcodeFamily = 80; CurrentInstrCycles = 20;
10534: { uaecptr oldpc = m68k_getpc();
10535: { uaecptr srca = m68k_areg(regs, srcreg) - 4;
10536: { uae_s32 src = get_long(srca);
10537: m68k_areg (regs, srcreg) = srca;
10538: { uae_s32 dst = m68k_dreg(regs, dstreg);
10539: m68k_incpc(2);
10540: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel664; }
10541: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel664; }
10542: }}}}endlabel664: ;
10543: return 20;
10544: }
10545: unsigned long REGPARAM2 CPUFUNC(op_4128_0)(uae_u32 opcode) /* CHK */
10546: {
10547: uae_u32 srcreg = (opcode & 7);
10548: uae_u32 dstreg = (opcode >> 9) & 7;
10549: OpcodeFamily = 80; CurrentInstrCycles = 22;
10550: { uaecptr oldpc = m68k_getpc();
10551: { uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
10552: { uae_s32 src = get_long(srca);
10553: { uae_s32 dst = m68k_dreg(regs, dstreg);
10554: m68k_incpc(4);
10555: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel665; }
10556: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel665; }
10557: }}}}endlabel665: ;
10558: return 22;
10559: }
10560: unsigned long REGPARAM2 CPUFUNC(op_4130_0)(uae_u32 opcode) /* CHK */
10561: {
10562: uae_u32 srcreg = (opcode & 7);
10563: uae_u32 dstreg = (opcode >> 9) & 7;
10564: OpcodeFamily = 80; CurrentInstrCycles = 24;
10565: { uaecptr oldpc = m68k_getpc();
10566: {m68k_incpc(2);
10567: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
10568: BusCyclePenalty += 2;
10569: { uae_s32 src = get_long(srca);
10570: { uae_s32 dst = m68k_dreg(regs, dstreg);
10571: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel666; }
10572: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel666; }
10573: }}}}}endlabel666: ;
10574: return 24;
10575: }
10576: unsigned long REGPARAM2 CPUFUNC(op_4138_0)(uae_u32 opcode) /* CHK */
10577: {
10578: uae_u32 dstreg = (opcode >> 9) & 7;
10579: OpcodeFamily = 80; CurrentInstrCycles = 22;
10580: { uaecptr oldpc = m68k_getpc();
10581: { uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
10582: { uae_s32 src = get_long(srca);
10583: { uae_s32 dst = m68k_dreg(regs, dstreg);
10584: m68k_incpc(4);
10585: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel667; }
10586: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel667; }
10587: }}}}endlabel667: ;
10588: return 22;
10589: }
10590: unsigned long REGPARAM2 CPUFUNC(op_4139_0)(uae_u32 opcode) /* CHK */
10591: {
10592: uae_u32 dstreg = (opcode >> 9) & 7;
10593: OpcodeFamily = 80; CurrentInstrCycles = 26;
10594: { uaecptr oldpc = m68k_getpc();
10595: { uaecptr srca = get_ilong(2);
10596: { uae_s32 src = get_long(srca);
10597: { uae_s32 dst = m68k_dreg(regs, dstreg);
10598: m68k_incpc(6);
10599: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel668; }
10600: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel668; }
10601: }}}}endlabel668: ;
10602: return 26;
10603: }
10604: unsigned long REGPARAM2 CPUFUNC(op_413a_0)(uae_u32 opcode) /* CHK */
10605: {
10606: uae_u32 dstreg = (opcode >> 9) & 7;
10607: OpcodeFamily = 80; CurrentInstrCycles = 22;
10608: { uaecptr oldpc = m68k_getpc();
10609: { uaecptr srca = m68k_getpc () + 2;
10610: srca += (uae_s32)(uae_s16)get_iword(2);
10611: { uae_s32 src = get_long(srca);
10612: { uae_s32 dst = m68k_dreg(regs, dstreg);
10613: m68k_incpc(4);
10614: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel669; }
10615: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel669; }
10616: }}}}endlabel669: ;
10617: return 22;
10618: }
10619: unsigned long REGPARAM2 CPUFUNC(op_413b_0)(uae_u32 opcode) /* CHK */
10620: {
10621: uae_u32 dstreg = (opcode >> 9) & 7;
10622: OpcodeFamily = 80; CurrentInstrCycles = 24;
10623: { uaecptr oldpc = m68k_getpc();
10624: {m68k_incpc(2);
10625: { uaecptr tmppc = m68k_getpc();
10626: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
10627: BusCyclePenalty += 2;
10628: { uae_s32 src = get_long(srca);
10629: { uae_s32 dst = m68k_dreg(regs, dstreg);
10630: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel670; }
10631: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel670; }
10632: }}}}}endlabel670: ;
10633: return 24;
10634: }
10635: unsigned long REGPARAM2 CPUFUNC(op_413c_0)(uae_u32 opcode) /* CHK */
10636: {
10637: uae_u32 dstreg = (opcode >> 9) & 7;
10638: OpcodeFamily = 80; CurrentInstrCycles = 18;
10639: { uaecptr oldpc = m68k_getpc();
10640: { uae_s32 src = get_ilong(2);
10641: { uae_s32 dst = m68k_dreg(regs, dstreg);
10642: m68k_incpc(6);
10643: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel671; }
10644: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel671; }
10645: }}}endlabel671: ;
10646: return 18;
10647: }
10648: unsigned long REGPARAM2 CPUFUNC(op_4180_0)(uae_u32 opcode) /* CHK */
10649: {
10650: uae_u32 srcreg = (opcode & 7);
10651: uae_u32 dstreg = (opcode >> 9) & 7;
10652: OpcodeFamily = 80; CurrentInstrCycles = 10;
10653: { uaecptr oldpc = m68k_getpc();
10654: { uae_s16 src = m68k_dreg(regs, srcreg);
10655: { uae_s16 dst = m68k_dreg(regs, dstreg);
10656: m68k_incpc(2);
10657: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel672; }
10658: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel672; }
10659: }}}endlabel672: ;
10660: return 10;
10661: }
10662: unsigned long REGPARAM2 CPUFUNC(op_4190_0)(uae_u32 opcode) /* CHK */
10663: {
10664: uae_u32 srcreg = (opcode & 7);
10665: uae_u32 dstreg = (opcode >> 9) & 7;
10666: OpcodeFamily = 80; CurrentInstrCycles = 14;
10667: { uaecptr oldpc = m68k_getpc();
10668: { uaecptr srca = m68k_areg(regs, srcreg);
10669: { uae_s16 src = get_word(srca);
10670: { uae_s16 dst = m68k_dreg(regs, dstreg);
10671: m68k_incpc(2);
10672: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel673; }
10673: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel673; }
10674: }}}}endlabel673: ;
10675: return 14;
10676: }
10677: unsigned long REGPARAM2 CPUFUNC(op_4198_0)(uae_u32 opcode) /* CHK */
10678: {
10679: uae_u32 srcreg = (opcode & 7);
10680: uae_u32 dstreg = (opcode >> 9) & 7;
10681: OpcodeFamily = 80; CurrentInstrCycles = 14;
10682: { uaecptr oldpc = m68k_getpc();
10683: { uaecptr srca = m68k_areg(regs, srcreg);
10684: { uae_s16 src = get_word(srca);
10685: m68k_areg(regs, srcreg) += 2;
10686: { uae_s16 dst = m68k_dreg(regs, dstreg);
10687: m68k_incpc(2);
10688: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel674; }
10689: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel674; }
10690: }}}}endlabel674: ;
10691: return 14;
10692: }
10693: unsigned long REGPARAM2 CPUFUNC(op_41a0_0)(uae_u32 opcode) /* CHK */
10694: {
10695: uae_u32 srcreg = (opcode & 7);
10696: uae_u32 dstreg = (opcode >> 9) & 7;
10697: OpcodeFamily = 80; CurrentInstrCycles = 16;
10698: { uaecptr oldpc = m68k_getpc();
10699: { uaecptr srca = m68k_areg(regs, srcreg) - 2;
10700: { uae_s16 src = get_word(srca);
10701: m68k_areg (regs, srcreg) = srca;
10702: { uae_s16 dst = m68k_dreg(regs, dstreg);
10703: m68k_incpc(2);
10704: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel675; }
10705: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel675; }
10706: }}}}endlabel675: ;
10707: return 16;
10708: }
10709: unsigned long REGPARAM2 CPUFUNC(op_41a8_0)(uae_u32 opcode) /* CHK */
10710: {
10711: uae_u32 srcreg = (opcode & 7);
10712: uae_u32 dstreg = (opcode >> 9) & 7;
10713: OpcodeFamily = 80; CurrentInstrCycles = 18;
10714: { uaecptr oldpc = m68k_getpc();
10715: { uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
10716: { uae_s16 src = get_word(srca);
10717: { uae_s16 dst = m68k_dreg(regs, dstreg);
10718: m68k_incpc(4);
10719: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel676; }
10720: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel676; }
10721: }}}}endlabel676: ;
10722: return 18;
10723: }
10724: unsigned long REGPARAM2 CPUFUNC(op_41b0_0)(uae_u32 opcode) /* CHK */
10725: {
10726: uae_u32 srcreg = (opcode & 7);
10727: uae_u32 dstreg = (opcode >> 9) & 7;
10728: OpcodeFamily = 80; CurrentInstrCycles = 20;
10729: { uaecptr oldpc = m68k_getpc();
10730: {m68k_incpc(2);
10731: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
10732: BusCyclePenalty += 2;
10733: { uae_s16 src = get_word(srca);
10734: { uae_s16 dst = m68k_dreg(regs, dstreg);
10735: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel677; }
10736: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel677; }
10737: }}}}}endlabel677: ;
10738: return 20;
10739: }
10740: unsigned long REGPARAM2 CPUFUNC(op_41b8_0)(uae_u32 opcode) /* CHK */
10741: {
10742: uae_u32 dstreg = (opcode >> 9) & 7;
10743: OpcodeFamily = 80; CurrentInstrCycles = 18;
10744: { uaecptr oldpc = m68k_getpc();
10745: { uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
10746: { uae_s16 src = get_word(srca);
10747: { uae_s16 dst = m68k_dreg(regs, dstreg);
10748: m68k_incpc(4);
10749: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel678; }
10750: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel678; }
10751: }}}}endlabel678: ;
10752: return 18;
10753: }
10754: unsigned long REGPARAM2 CPUFUNC(op_41b9_0)(uae_u32 opcode) /* CHK */
10755: {
10756: uae_u32 dstreg = (opcode >> 9) & 7;
10757: OpcodeFamily = 80; CurrentInstrCycles = 22;
10758: { uaecptr oldpc = m68k_getpc();
10759: { uaecptr srca = get_ilong(2);
10760: { uae_s16 src = get_word(srca);
10761: { uae_s16 dst = m68k_dreg(regs, dstreg);
10762: m68k_incpc(6);
10763: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel679; }
10764: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel679; }
10765: }}}}endlabel679: ;
10766: return 22;
10767: }
10768: unsigned long REGPARAM2 CPUFUNC(op_41ba_0)(uae_u32 opcode) /* CHK */
10769: {
10770: uae_u32 dstreg = (opcode >> 9) & 7;
10771: OpcodeFamily = 80; CurrentInstrCycles = 18;
10772: { uaecptr oldpc = m68k_getpc();
10773: { uaecptr srca = m68k_getpc () + 2;
10774: srca += (uae_s32)(uae_s16)get_iword(2);
10775: { uae_s16 src = get_word(srca);
10776: { uae_s16 dst = m68k_dreg(regs, dstreg);
10777: m68k_incpc(4);
10778: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel680; }
10779: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel680; }
10780: }}}}endlabel680: ;
10781: return 18;
10782: }
10783: unsigned long REGPARAM2 CPUFUNC(op_41bb_0)(uae_u32 opcode) /* CHK */
10784: {
10785: uae_u32 dstreg = (opcode >> 9) & 7;
10786: OpcodeFamily = 80; CurrentInstrCycles = 20;
10787: { uaecptr oldpc = m68k_getpc();
10788: {m68k_incpc(2);
10789: { uaecptr tmppc = m68k_getpc();
10790: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
10791: BusCyclePenalty += 2;
10792: { uae_s16 src = get_word(srca);
10793: { uae_s16 dst = m68k_dreg(regs, dstreg);
10794: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel681; }
10795: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel681; }
10796: }}}}}endlabel681: ;
10797: return 20;
10798: }
10799: unsigned long REGPARAM2 CPUFUNC(op_41bc_0)(uae_u32 opcode) /* CHK */
10800: {
10801: uae_u32 dstreg = (opcode >> 9) & 7;
10802: OpcodeFamily = 80; CurrentInstrCycles = 14;
10803: { uaecptr oldpc = m68k_getpc();
10804: { uae_s16 src = get_iword(2);
10805: { uae_s16 dst = m68k_dreg(regs, dstreg);
10806: m68k_incpc(4);
10807: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel682; }
10808: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel682; }
10809: }}}endlabel682: ;
10810: return 14;
10811: }
10812: unsigned long REGPARAM2 CPUFUNC(op_41d0_0)(uae_u32 opcode) /* LEA */
10813: {
10814: uae_u32 srcreg = (opcode & 7);
10815: uae_u32 dstreg = (opcode >> 9) & 7;
10816: OpcodeFamily = 56; CurrentInstrCycles = 4;
10817: {{ uaecptr srca = m68k_areg(regs, srcreg);
10818: { m68k_areg(regs, dstreg) = (srca);
10819: }}}m68k_incpc(2);
10820: return 4;
10821: }
10822: unsigned long REGPARAM2 CPUFUNC(op_41e8_0)(uae_u32 opcode) /* LEA */
10823: {
10824: uae_u32 srcreg = (opcode & 7);
10825: uae_u32 dstreg = (opcode >> 9) & 7;
10826: OpcodeFamily = 56; CurrentInstrCycles = 8;
10827: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
10828: { m68k_areg(regs, dstreg) = (srca);
10829: }}}m68k_incpc(4);
10830: return 8;
10831: }
10832: unsigned long REGPARAM2 CPUFUNC(op_41f0_0)(uae_u32 opcode) /* LEA */
10833: {
10834: uae_u32 srcreg = (opcode & 7);
10835: uae_u32 dstreg = (opcode >> 9) & 7;
10836: OpcodeFamily = 56; CurrentInstrCycles = 14;
10837: {{m68k_incpc(2);
10838: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
10839: BusCyclePenalty += 2;
10840: { m68k_areg(regs, dstreg) = (srca);
10841: }}}}return 14;
10842: }
10843: unsigned long REGPARAM2 CPUFUNC(op_41f8_0)(uae_u32 opcode) /* LEA */
10844: {
10845: uae_u32 dstreg = (opcode >> 9) & 7;
10846: OpcodeFamily = 56; CurrentInstrCycles = 8;
10847: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
10848: { m68k_areg(regs, dstreg) = (srca);
10849: }}}m68k_incpc(4);
10850: return 8;
10851: }
10852: unsigned long REGPARAM2 CPUFUNC(op_41f9_0)(uae_u32 opcode) /* LEA */
10853: {
10854: uae_u32 dstreg = (opcode >> 9) & 7;
10855: OpcodeFamily = 56; CurrentInstrCycles = 12;
10856: {{ uaecptr srca = get_ilong(2);
10857: { m68k_areg(regs, dstreg) = (srca);
10858: }}}m68k_incpc(6);
10859: return 12;
10860: }
10861: unsigned long REGPARAM2 CPUFUNC(op_41fa_0)(uae_u32 opcode) /* LEA */
10862: {
10863: uae_u32 dstreg = (opcode >> 9) & 7;
10864: OpcodeFamily = 56; CurrentInstrCycles = 8;
10865: {{ uaecptr srca = m68k_getpc () + 2;
10866: srca += (uae_s32)(uae_s16)get_iword(2);
10867: { m68k_areg(regs, dstreg) = (srca);
10868: }}}m68k_incpc(4);
10869: return 8;
10870: }
10871: unsigned long REGPARAM2 CPUFUNC(op_41fb_0)(uae_u32 opcode) /* LEA */
10872: {
10873: uae_u32 dstreg = (opcode >> 9) & 7;
10874: OpcodeFamily = 56; CurrentInstrCycles = 14;
10875: {{m68k_incpc(2);
10876: { uaecptr tmppc = m68k_getpc();
10877: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
10878: BusCyclePenalty += 2;
10879: { m68k_areg(regs, dstreg) = (srca);
10880: }}}}return 14;
10881: }
10882: unsigned long REGPARAM2 CPUFUNC(op_4200_0)(uae_u32 opcode) /* CLR */
10883: {
10884: uae_u32 srcreg = (opcode & 7);
10885: OpcodeFamily = 18; CurrentInstrCycles = 4;
10886: {{ CLEAR_CZNV;
10887: SET_ZFLG (((uae_s8)(0)) == 0);
10888: SET_NFLG (((uae_s8)(0)) < 0);
10889: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
10890: }}m68k_incpc(2);
10891: return 4;
10892: }
10893: unsigned long REGPARAM2 CPUFUNC(op_4210_0)(uae_u32 opcode) /* CLR */
10894: {
10895: uae_u32 srcreg = (opcode & 7);
10896: OpcodeFamily = 18; CurrentInstrCycles = 12;
10897: {{ uaecptr srca = m68k_areg(regs, srcreg);
10898: uae_s8 src = get_byte(srca);
10899: CLEAR_CZNV;
10900: SET_ZFLG (((uae_s8)(0)) == 0);
10901: SET_NFLG (((uae_s8)(0)) < 0);
10902: put_byte(srca,0);
10903: }}m68k_incpc(2);
10904: return 12;
10905: }
10906: unsigned long REGPARAM2 CPUFUNC(op_4218_0)(uae_u32 opcode) /* CLR */
10907: {
10908: uae_u32 srcreg = (opcode & 7);
10909: OpcodeFamily = 18; CurrentInstrCycles = 12;
10910: {{ uaecptr srca = m68k_areg(regs, srcreg);
10911: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
10912: uae_s8 src = get_byte(srca);
10913: CLEAR_CZNV;
10914: SET_ZFLG (((uae_s8)(0)) == 0);
10915: SET_NFLG (((uae_s8)(0)) < 0);
10916: put_byte(srca,0);
10917: }}m68k_incpc(2);
10918: return 12;
10919: }
10920: unsigned long REGPARAM2 CPUFUNC(op_4220_0)(uae_u32 opcode) /* CLR */
10921: {
10922: uae_u32 srcreg = (opcode & 7);
10923: OpcodeFamily = 18; CurrentInstrCycles = 14;
10924: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
10925: m68k_areg (regs, srcreg) = srca;
10926: uae_s8 src = get_byte(srca);
10927: CLEAR_CZNV;
10928: SET_ZFLG (((uae_s8)(0)) == 0);
10929: SET_NFLG (((uae_s8)(0)) < 0);
10930: put_byte(srca,0);
10931: }}m68k_incpc(2);
10932: return 14;
10933: }
10934: unsigned long REGPARAM2 CPUFUNC(op_4228_0)(uae_u32 opcode) /* CLR */
10935: {
10936: uae_u32 srcreg = (opcode & 7);
10937: OpcodeFamily = 18; CurrentInstrCycles = 16;
10938: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
10939: uae_s8 src = get_byte(srca);
10940: CLEAR_CZNV;
10941: SET_ZFLG (((uae_s8)(0)) == 0);
10942: SET_NFLG (((uae_s8)(0)) < 0);
10943: put_byte(srca,0);
10944: }}m68k_incpc(4);
10945: return 16;
10946: }
10947: unsigned long REGPARAM2 CPUFUNC(op_4230_0)(uae_u32 opcode) /* CLR */
10948: {
10949: uae_u32 srcreg = (opcode & 7);
10950: OpcodeFamily = 18; CurrentInstrCycles = 18;
10951: {{m68k_incpc(2);
10952: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
10953: BusCyclePenalty += 2;
10954: uae_s8 src = get_byte(srca);
10955: CLEAR_CZNV;
10956: SET_ZFLG (((uae_s8)(0)) == 0);
10957: SET_NFLG (((uae_s8)(0)) < 0);
10958: put_byte(srca,0);
10959: }}}return 18;
10960: }
10961: unsigned long REGPARAM2 CPUFUNC(op_4238_0)(uae_u32 opcode) /* CLR */
10962: {
10963: OpcodeFamily = 18; CurrentInstrCycles = 16;
10964: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
10965: uae_s8 src = get_byte(srca);
10966: CLEAR_CZNV;
10967: SET_ZFLG (((uae_s8)(0)) == 0);
10968: SET_NFLG (((uae_s8)(0)) < 0);
10969: put_byte(srca,0);
10970: }}m68k_incpc(4);
10971: return 16;
10972: }
10973: unsigned long REGPARAM2 CPUFUNC(op_4239_0)(uae_u32 opcode) /* CLR */
10974: {
10975: OpcodeFamily = 18; CurrentInstrCycles = 20;
10976: {{ uaecptr srca = get_ilong(2);
10977: uae_s8 src = get_byte(srca);
10978: CLEAR_CZNV;
10979: SET_ZFLG (((uae_s8)(0)) == 0);
10980: SET_NFLG (((uae_s8)(0)) < 0);
10981: put_byte(srca,0);
10982: }}m68k_incpc(6);
10983: return 20;
10984: }
10985: unsigned long REGPARAM2 CPUFUNC(op_4240_0)(uae_u32 opcode) /* CLR */
10986: {
10987: uae_u32 srcreg = (opcode & 7);
10988: OpcodeFamily = 18; CurrentInstrCycles = 4;
10989: {{ CLEAR_CZNV;
10990: SET_ZFLG (((uae_s16)(0)) == 0);
10991: SET_NFLG (((uae_s16)(0)) < 0);
10992: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
10993: }}m68k_incpc(2);
10994: return 4;
10995: }
10996: unsigned long REGPARAM2 CPUFUNC(op_4250_0)(uae_u32 opcode) /* CLR */
10997: {
10998: uae_u32 srcreg = (opcode & 7);
10999: OpcodeFamily = 18; CurrentInstrCycles = 12;
11000: {{ uaecptr srca = m68k_areg(regs, srcreg);
11001: uae_s16 src = get_word(srca);
11002: CLEAR_CZNV;
11003: SET_ZFLG (((uae_s16)(0)) == 0);
11004: SET_NFLG (((uae_s16)(0)) < 0);
11005: put_word(srca,0);
11006: }}m68k_incpc(2);
11007: return 12;
11008: }
11009: unsigned long REGPARAM2 CPUFUNC(op_4258_0)(uae_u32 opcode) /* CLR */
11010: {
11011: uae_u32 srcreg = (opcode & 7);
11012: OpcodeFamily = 18; CurrentInstrCycles = 12;
11013: {{ uaecptr srca = m68k_areg(regs, srcreg);
11014: m68k_areg(regs, srcreg) += 2;
11015: uae_s16 src = get_word(srca);
11016: CLEAR_CZNV;
11017: SET_ZFLG (((uae_s16)(0)) == 0);
11018: SET_NFLG (((uae_s16)(0)) < 0);
11019: put_word(srca,0);
11020: }}m68k_incpc(2);
11021: return 12;
11022: }
11023: unsigned long REGPARAM2 CPUFUNC(op_4260_0)(uae_u32 opcode) /* CLR */
11024: {
11025: uae_u32 srcreg = (opcode & 7);
11026: OpcodeFamily = 18; CurrentInstrCycles = 14;
11027: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
11028: m68k_areg (regs, srcreg) = srca;
11029: uae_s16 src = get_word(srca);
11030: CLEAR_CZNV;
11031: SET_ZFLG (((uae_s16)(0)) == 0);
11032: SET_NFLG (((uae_s16)(0)) < 0);
11033: put_word(srca,0);
11034: }}m68k_incpc(2);
11035: return 14;
11036: }
11037: unsigned long REGPARAM2 CPUFUNC(op_4268_0)(uae_u32 opcode) /* CLR */
11038: {
11039: uae_u32 srcreg = (opcode & 7);
11040: OpcodeFamily = 18; CurrentInstrCycles = 16;
11041: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
11042: uae_s16 src = get_word(srca);
11043: CLEAR_CZNV;
11044: SET_ZFLG (((uae_s16)(0)) == 0);
11045: SET_NFLG (((uae_s16)(0)) < 0);
11046: put_word(srca,0);
11047: }}m68k_incpc(4);
11048: return 16;
11049: }
11050: #endif
11051:
11052: #ifdef PART_4
11053: unsigned long REGPARAM2 CPUFUNC(op_4270_0)(uae_u32 opcode) /* CLR */
11054: {
11055: uae_u32 srcreg = (opcode & 7);
11056: OpcodeFamily = 18; CurrentInstrCycles = 18;
11057: {{m68k_incpc(2);
11058: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
11059: BusCyclePenalty += 2;
11060: uae_s16 src = get_word(srca);
11061: CLEAR_CZNV;
11062: SET_ZFLG (((uae_s16)(0)) == 0);
11063: SET_NFLG (((uae_s16)(0)) < 0);
11064: put_word(srca,0);
11065: }}}return 18;
11066: }
11067: unsigned long REGPARAM2 CPUFUNC(op_4278_0)(uae_u32 opcode) /* CLR */
11068: {
11069: OpcodeFamily = 18; CurrentInstrCycles = 16;
11070: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
11071: uae_s16 src = get_word(srca);
11072: CLEAR_CZNV;
11073: SET_ZFLG (((uae_s16)(0)) == 0);
11074: SET_NFLG (((uae_s16)(0)) < 0);
11075: put_word(srca,0);
11076: }}m68k_incpc(4);
11077: return 16;
11078: }
11079: unsigned long REGPARAM2 CPUFUNC(op_4279_0)(uae_u32 opcode) /* CLR */
11080: {
11081: OpcodeFamily = 18; CurrentInstrCycles = 20;
11082: {{ uaecptr srca = get_ilong(2);
11083: uae_s16 src = get_word(srca);
11084: CLEAR_CZNV;
11085: SET_ZFLG (((uae_s16)(0)) == 0);
11086: SET_NFLG (((uae_s16)(0)) < 0);
11087: put_word(srca,0);
11088: }}m68k_incpc(6);
11089: return 20;
11090: }
11091: unsigned long REGPARAM2 CPUFUNC(op_4280_0)(uae_u32 opcode) /* CLR */
11092: {
11093: uae_u32 srcreg = (opcode & 7);
11094: OpcodeFamily = 18; CurrentInstrCycles = 6;
11095: {{ CLEAR_CZNV;
11096: SET_ZFLG (((uae_s32)(0)) == 0);
11097: SET_NFLG (((uae_s32)(0)) < 0);
11098: m68k_dreg(regs, srcreg) = (0);
11099: }}m68k_incpc(2);
11100: return 6;
11101: }
11102: unsigned long REGPARAM2 CPUFUNC(op_4290_0)(uae_u32 opcode) /* CLR */
11103: {
11104: uae_u32 srcreg = (opcode & 7);
11105: OpcodeFamily = 18; CurrentInstrCycles = 20;
11106: {{ uaecptr srca = m68k_areg(regs, srcreg);
11107: uae_s32 src = get_long(srca);
11108: CLEAR_CZNV;
11109: SET_ZFLG (((uae_s32)(0)) == 0);
11110: SET_NFLG (((uae_s32)(0)) < 0);
11111: put_long(srca,0);
11112: }}m68k_incpc(2);
11113: return 20;
11114: }
11115: unsigned long REGPARAM2 CPUFUNC(op_4298_0)(uae_u32 opcode) /* CLR */
11116: {
11117: uae_u32 srcreg = (opcode & 7);
11118: OpcodeFamily = 18; CurrentInstrCycles = 20;
11119: {{ uaecptr srca = m68k_areg(regs, srcreg);
11120: m68k_areg(regs, srcreg) += 4;
11121: uae_s32 src = get_long(srca);
11122: CLEAR_CZNV;
11123: SET_ZFLG (((uae_s32)(0)) == 0);
11124: SET_NFLG (((uae_s32)(0)) < 0);
11125: put_long(srca,0);
11126: }}m68k_incpc(2);
11127: return 20;
11128: }
11129: unsigned long REGPARAM2 CPUFUNC(op_42a0_0)(uae_u32 opcode) /* CLR */
11130: {
11131: uae_u32 srcreg = (opcode & 7);
11132: OpcodeFamily = 18; CurrentInstrCycles = 22;
11133: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
11134: m68k_areg (regs, srcreg) = srca;
11135: uae_s32 src = get_long(srca);
11136: CLEAR_CZNV;
11137: SET_ZFLG (((uae_s32)(0)) == 0);
11138: SET_NFLG (((uae_s32)(0)) < 0);
11139: put_long(srca,0);
11140: }}m68k_incpc(2);
11141: return 22;
11142: }
11143: unsigned long REGPARAM2 CPUFUNC(op_42a8_0)(uae_u32 opcode) /* CLR */
11144: {
11145: uae_u32 srcreg = (opcode & 7);
11146: OpcodeFamily = 18; CurrentInstrCycles = 24;
11147: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
11148: uae_s32 src = get_long(srca);
11149: CLEAR_CZNV;
11150: SET_ZFLG (((uae_s32)(0)) == 0);
11151: SET_NFLG (((uae_s32)(0)) < 0);
11152: put_long(srca,0);
11153: }}m68k_incpc(4);
11154: return 24;
11155: }
11156: unsigned long REGPARAM2 CPUFUNC(op_42b0_0)(uae_u32 opcode) /* CLR */
11157: {
11158: uae_u32 srcreg = (opcode & 7);
11159: OpcodeFamily = 18; CurrentInstrCycles = 26;
11160: {{m68k_incpc(2);
11161: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
11162: BusCyclePenalty += 2;
11163: uae_s32 src = get_long(srca);
11164: CLEAR_CZNV;
11165: SET_ZFLG (((uae_s32)(0)) == 0);
11166: SET_NFLG (((uae_s32)(0)) < 0);
11167: put_long(srca,0);
11168: }}}return 26;
11169: }
11170: unsigned long REGPARAM2 CPUFUNC(op_42b8_0)(uae_u32 opcode) /* CLR */
11171: {
11172: OpcodeFamily = 18; CurrentInstrCycles = 24;
11173: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
11174: uae_s32 src = get_long(srca);
11175: CLEAR_CZNV;
11176: SET_ZFLG (((uae_s32)(0)) == 0);
11177: SET_NFLG (((uae_s32)(0)) < 0);
11178: put_long(srca,0);
11179: }}m68k_incpc(4);
11180: return 24;
11181: }
11182: unsigned long REGPARAM2 CPUFUNC(op_42b9_0)(uae_u32 opcode) /* CLR */
11183: {
11184: OpcodeFamily = 18; CurrentInstrCycles = 28;
11185: {{ uaecptr srca = get_ilong(2);
11186: uae_s32 src = get_long(srca);
11187: CLEAR_CZNV;
11188: SET_ZFLG (((uae_s32)(0)) == 0);
11189: SET_NFLG (((uae_s32)(0)) < 0);
11190: put_long(srca,0);
11191: }}m68k_incpc(6);
11192: return 28;
11193: }
11194: unsigned long REGPARAM2 CPUFUNC(op_42c0_0)(uae_u32 opcode) /* MVSR2 */
11195: {
11196: uae_u32 srcreg = (opcode & 7);
11197: OpcodeFamily = 32; CurrentInstrCycles = 6;
11198: {{ MakeSR();
11199: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
11200: }}m68k_incpc(2);
11201: return 6;
11202: }
11203: unsigned long REGPARAM2 CPUFUNC(op_42d0_0)(uae_u32 opcode) /* MVSR2 */
11204: {
11205: uae_u32 srcreg = (opcode & 7);
11206: OpcodeFamily = 32; CurrentInstrCycles = 12;
11207: {{ uaecptr srca = m68k_areg(regs, srcreg);
11208: MakeSR();
11209: put_word(srca,regs.sr & 0xff);
11210: }}m68k_incpc(2);
11211: return 12;
11212: }
11213: unsigned long REGPARAM2 CPUFUNC(op_42d8_0)(uae_u32 opcode) /* MVSR2 */
11214: {
11215: uae_u32 srcreg = (opcode & 7);
11216: OpcodeFamily = 32; CurrentInstrCycles = 12;
11217: {{ uaecptr srca = m68k_areg(regs, srcreg);
11218: m68k_areg(regs, srcreg) += 2;
11219: MakeSR();
11220: put_word(srca,regs.sr & 0xff);
11221: }}m68k_incpc(2);
11222: return 12;
11223: }
11224: unsigned long REGPARAM2 CPUFUNC(op_42e0_0)(uae_u32 opcode) /* MVSR2 */
11225: {
11226: uae_u32 srcreg = (opcode & 7);
11227: OpcodeFamily = 32; CurrentInstrCycles = 14;
11228: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
11229: m68k_areg (regs, srcreg) = srca;
11230: MakeSR();
11231: put_word(srca,regs.sr & 0xff);
11232: }}m68k_incpc(2);
11233: return 14;
11234: }
11235: unsigned long REGPARAM2 CPUFUNC(op_42e8_0)(uae_u32 opcode) /* MVSR2 */
11236: {
11237: uae_u32 srcreg = (opcode & 7);
11238: OpcodeFamily = 32; CurrentInstrCycles = 16;
11239: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
11240: MakeSR();
11241: put_word(srca,regs.sr & 0xff);
11242: }}m68k_incpc(4);
11243: return 16;
11244: }
11245: unsigned long REGPARAM2 CPUFUNC(op_42f0_0)(uae_u32 opcode) /* MVSR2 */
11246: {
11247: uae_u32 srcreg = (opcode & 7);
11248: OpcodeFamily = 32; CurrentInstrCycles = 18;
11249: {{m68k_incpc(2);
11250: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
11251: BusCyclePenalty += 2;
11252: MakeSR();
11253: put_word(srca,regs.sr & 0xff);
11254: }}}return 18;
11255: }
11256: unsigned long REGPARAM2 CPUFUNC(op_42f8_0)(uae_u32 opcode) /* MVSR2 */
11257: {
11258: OpcodeFamily = 32; CurrentInstrCycles = 16;
11259: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
11260: MakeSR();
11261: put_word(srca,regs.sr & 0xff);
11262: }}m68k_incpc(4);
11263: return 16;
11264: }
11265: unsigned long REGPARAM2 CPUFUNC(op_42f9_0)(uae_u32 opcode) /* MVSR2 */
11266: {
11267: OpcodeFamily = 32; CurrentInstrCycles = 20;
11268: {{ uaecptr srca = get_ilong(2);
11269: MakeSR();
11270: put_word(srca,regs.sr & 0xff);
11271: }}m68k_incpc(6);
11272: return 20;
11273: }
11274: unsigned long REGPARAM2 CPUFUNC(op_4400_0)(uae_u32 opcode) /* NEG */
11275: {
11276: uae_u32 srcreg = (opcode & 7);
11277: OpcodeFamily = 15; CurrentInstrCycles = 4;
11278: {{ uae_s8 src = m68k_dreg(regs, srcreg);
11279: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
11280: { int flgs = ((uae_s8)(src)) < 0;
11281: int flgo = ((uae_s8)(0)) < 0;
11282: int flgn = ((uae_s8)(dst)) < 0;
11283: SET_ZFLG (((uae_s8)(dst)) == 0);
11284: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11285: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
11286: COPY_CARRY;
11287: SET_NFLG (flgn != 0);
11288: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
11289: }}}}}m68k_incpc(2);
11290: return 4;
11291: }
11292: unsigned long REGPARAM2 CPUFUNC(op_4410_0)(uae_u32 opcode) /* NEG */
11293: {
11294: uae_u32 srcreg = (opcode & 7);
11295: OpcodeFamily = 15; CurrentInstrCycles = 12;
11296: {{ uaecptr srca = m68k_areg(regs, srcreg);
11297: { uae_s8 src = get_byte(srca);
11298: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
11299: { int flgs = ((uae_s8)(src)) < 0;
11300: int flgo = ((uae_s8)(0)) < 0;
11301: int flgn = ((uae_s8)(dst)) < 0;
11302: SET_ZFLG (((uae_s8)(dst)) == 0);
11303: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11304: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
11305: COPY_CARRY;
11306: SET_NFLG (flgn != 0);
11307: put_byte(srca,dst);
11308: }}}}}}m68k_incpc(2);
11309: return 12;
11310: }
11311: unsigned long REGPARAM2 CPUFUNC(op_4418_0)(uae_u32 opcode) /* NEG */
11312: {
11313: uae_u32 srcreg = (opcode & 7);
11314: OpcodeFamily = 15; CurrentInstrCycles = 12;
11315: {{ uaecptr srca = m68k_areg(regs, srcreg);
11316: { uae_s8 src = get_byte(srca);
11317: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
11318: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
11319: { int flgs = ((uae_s8)(src)) < 0;
11320: int flgo = ((uae_s8)(0)) < 0;
11321: int flgn = ((uae_s8)(dst)) < 0;
11322: SET_ZFLG (((uae_s8)(dst)) == 0);
11323: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11324: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
11325: COPY_CARRY;
11326: SET_NFLG (flgn != 0);
11327: put_byte(srca,dst);
11328: }}}}}}m68k_incpc(2);
11329: return 12;
11330: }
11331: unsigned long REGPARAM2 CPUFUNC(op_4420_0)(uae_u32 opcode) /* NEG */
11332: {
11333: uae_u32 srcreg = (opcode & 7);
11334: OpcodeFamily = 15; CurrentInstrCycles = 14;
11335: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
11336: { uae_s8 src = get_byte(srca);
11337: m68k_areg (regs, srcreg) = srca;
11338: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
11339: { int flgs = ((uae_s8)(src)) < 0;
11340: int flgo = ((uae_s8)(0)) < 0;
11341: int flgn = ((uae_s8)(dst)) < 0;
11342: SET_ZFLG (((uae_s8)(dst)) == 0);
11343: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11344: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
11345: COPY_CARRY;
11346: SET_NFLG (flgn != 0);
11347: put_byte(srca,dst);
11348: }}}}}}m68k_incpc(2);
11349: return 14;
11350: }
11351: unsigned long REGPARAM2 CPUFUNC(op_4428_0)(uae_u32 opcode) /* NEG */
11352: {
11353: uae_u32 srcreg = (opcode & 7);
11354: OpcodeFamily = 15; CurrentInstrCycles = 16;
11355: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
11356: { uae_s8 src = get_byte(srca);
11357: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
11358: { int flgs = ((uae_s8)(src)) < 0;
11359: int flgo = ((uae_s8)(0)) < 0;
11360: int flgn = ((uae_s8)(dst)) < 0;
11361: SET_ZFLG (((uae_s8)(dst)) == 0);
11362: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11363: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
11364: COPY_CARRY;
11365: SET_NFLG (flgn != 0);
11366: put_byte(srca,dst);
11367: }}}}}}m68k_incpc(4);
11368: return 16;
11369: }
11370: unsigned long REGPARAM2 CPUFUNC(op_4430_0)(uae_u32 opcode) /* NEG */
11371: {
11372: uae_u32 srcreg = (opcode & 7);
11373: OpcodeFamily = 15; CurrentInstrCycles = 18;
11374: {{m68k_incpc(2);
11375: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
11376: BusCyclePenalty += 2;
11377: { uae_s8 src = get_byte(srca);
11378: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
11379: { int flgs = ((uae_s8)(src)) < 0;
11380: int flgo = ((uae_s8)(0)) < 0;
11381: int flgn = ((uae_s8)(dst)) < 0;
11382: SET_ZFLG (((uae_s8)(dst)) == 0);
11383: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11384: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
11385: COPY_CARRY;
11386: SET_NFLG (flgn != 0);
11387: put_byte(srca,dst);
11388: }}}}}}}return 18;
11389: }
11390: unsigned long REGPARAM2 CPUFUNC(op_4438_0)(uae_u32 opcode) /* NEG */
11391: {
11392: OpcodeFamily = 15; CurrentInstrCycles = 16;
11393: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
11394: { uae_s8 src = get_byte(srca);
11395: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
11396: { int flgs = ((uae_s8)(src)) < 0;
11397: int flgo = ((uae_s8)(0)) < 0;
11398: int flgn = ((uae_s8)(dst)) < 0;
11399: SET_ZFLG (((uae_s8)(dst)) == 0);
11400: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11401: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
11402: COPY_CARRY;
11403: SET_NFLG (flgn != 0);
11404: put_byte(srca,dst);
11405: }}}}}}m68k_incpc(4);
11406: return 16;
11407: }
11408: unsigned long REGPARAM2 CPUFUNC(op_4439_0)(uae_u32 opcode) /* NEG */
11409: {
11410: OpcodeFamily = 15; CurrentInstrCycles = 20;
11411: {{ uaecptr srca = get_ilong(2);
11412: { uae_s8 src = get_byte(srca);
11413: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
11414: { int flgs = ((uae_s8)(src)) < 0;
11415: int flgo = ((uae_s8)(0)) < 0;
11416: int flgn = ((uae_s8)(dst)) < 0;
11417: SET_ZFLG (((uae_s8)(dst)) == 0);
11418: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11419: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
11420: COPY_CARRY;
11421: SET_NFLG (flgn != 0);
11422: put_byte(srca,dst);
11423: }}}}}}m68k_incpc(6);
11424: return 20;
11425: }
11426: unsigned long REGPARAM2 CPUFUNC(op_4440_0)(uae_u32 opcode) /* NEG */
11427: {
11428: uae_u32 srcreg = (opcode & 7);
11429: OpcodeFamily = 15; CurrentInstrCycles = 4;
11430: {{ uae_s16 src = m68k_dreg(regs, srcreg);
11431: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
11432: { int flgs = ((uae_s16)(src)) < 0;
11433: int flgo = ((uae_s16)(0)) < 0;
11434: int flgn = ((uae_s16)(dst)) < 0;
11435: SET_ZFLG (((uae_s16)(dst)) == 0);
11436: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11437: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
11438: COPY_CARRY;
11439: SET_NFLG (flgn != 0);
11440: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
11441: }}}}}m68k_incpc(2);
11442: return 4;
11443: }
11444: unsigned long REGPARAM2 CPUFUNC(op_4450_0)(uae_u32 opcode) /* NEG */
11445: {
11446: uae_u32 srcreg = (opcode & 7);
11447: OpcodeFamily = 15; CurrentInstrCycles = 12;
11448: {{ uaecptr srca = m68k_areg(regs, srcreg);
11449: { uae_s16 src = get_word(srca);
11450: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
11451: { int flgs = ((uae_s16)(src)) < 0;
11452: int flgo = ((uae_s16)(0)) < 0;
11453: int flgn = ((uae_s16)(dst)) < 0;
11454: SET_ZFLG (((uae_s16)(dst)) == 0);
11455: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11456: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
11457: COPY_CARRY;
11458: SET_NFLG (flgn != 0);
11459: put_word(srca,dst);
11460: }}}}}}m68k_incpc(2);
11461: return 12;
11462: }
11463: unsigned long REGPARAM2 CPUFUNC(op_4458_0)(uae_u32 opcode) /* NEG */
11464: {
11465: uae_u32 srcreg = (opcode & 7);
11466: OpcodeFamily = 15; CurrentInstrCycles = 12;
11467: {{ uaecptr srca = m68k_areg(regs, srcreg);
11468: { uae_s16 src = get_word(srca);
11469: m68k_areg(regs, srcreg) += 2;
11470: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
11471: { int flgs = ((uae_s16)(src)) < 0;
11472: int flgo = ((uae_s16)(0)) < 0;
11473: int flgn = ((uae_s16)(dst)) < 0;
11474: SET_ZFLG (((uae_s16)(dst)) == 0);
11475: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11476: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
11477: COPY_CARRY;
11478: SET_NFLG (flgn != 0);
11479: put_word(srca,dst);
11480: }}}}}}m68k_incpc(2);
11481: return 12;
11482: }
11483: unsigned long REGPARAM2 CPUFUNC(op_4460_0)(uae_u32 opcode) /* NEG */
11484: {
11485: uae_u32 srcreg = (opcode & 7);
11486: OpcodeFamily = 15; CurrentInstrCycles = 14;
11487: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
11488: { uae_s16 src = get_word(srca);
11489: m68k_areg (regs, srcreg) = srca;
11490: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
11491: { int flgs = ((uae_s16)(src)) < 0;
11492: int flgo = ((uae_s16)(0)) < 0;
11493: int flgn = ((uae_s16)(dst)) < 0;
11494: SET_ZFLG (((uae_s16)(dst)) == 0);
11495: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11496: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
11497: COPY_CARRY;
11498: SET_NFLG (flgn != 0);
11499: put_word(srca,dst);
11500: }}}}}}m68k_incpc(2);
11501: return 14;
11502: }
11503: unsigned long REGPARAM2 CPUFUNC(op_4468_0)(uae_u32 opcode) /* NEG */
11504: {
11505: uae_u32 srcreg = (opcode & 7);
11506: OpcodeFamily = 15; CurrentInstrCycles = 16;
11507: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
11508: { uae_s16 src = get_word(srca);
11509: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
11510: { int flgs = ((uae_s16)(src)) < 0;
11511: int flgo = ((uae_s16)(0)) < 0;
11512: int flgn = ((uae_s16)(dst)) < 0;
11513: SET_ZFLG (((uae_s16)(dst)) == 0);
11514: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11515: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
11516: COPY_CARRY;
11517: SET_NFLG (flgn != 0);
11518: put_word(srca,dst);
11519: }}}}}}m68k_incpc(4);
11520: return 16;
11521: }
11522: unsigned long REGPARAM2 CPUFUNC(op_4470_0)(uae_u32 opcode) /* NEG */
11523: {
11524: uae_u32 srcreg = (opcode & 7);
11525: OpcodeFamily = 15; CurrentInstrCycles = 18;
11526: {{m68k_incpc(2);
11527: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
11528: BusCyclePenalty += 2;
11529: { uae_s16 src = get_word(srca);
11530: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
11531: { int flgs = ((uae_s16)(src)) < 0;
11532: int flgo = ((uae_s16)(0)) < 0;
11533: int flgn = ((uae_s16)(dst)) < 0;
11534: SET_ZFLG (((uae_s16)(dst)) == 0);
11535: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11536: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
11537: COPY_CARRY;
11538: SET_NFLG (flgn != 0);
11539: put_word(srca,dst);
11540: }}}}}}}return 18;
11541: }
11542: unsigned long REGPARAM2 CPUFUNC(op_4478_0)(uae_u32 opcode) /* NEG */
11543: {
11544: OpcodeFamily = 15; CurrentInstrCycles = 16;
11545: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
11546: { uae_s16 src = get_word(srca);
11547: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
11548: { int flgs = ((uae_s16)(src)) < 0;
11549: int flgo = ((uae_s16)(0)) < 0;
11550: int flgn = ((uae_s16)(dst)) < 0;
11551: SET_ZFLG (((uae_s16)(dst)) == 0);
11552: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11553: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
11554: COPY_CARRY;
11555: SET_NFLG (flgn != 0);
11556: put_word(srca,dst);
11557: }}}}}}m68k_incpc(4);
11558: return 16;
11559: }
11560: unsigned long REGPARAM2 CPUFUNC(op_4479_0)(uae_u32 opcode) /* NEG */
11561: {
11562: OpcodeFamily = 15; CurrentInstrCycles = 20;
11563: {{ uaecptr srca = get_ilong(2);
11564: { uae_s16 src = get_word(srca);
11565: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
11566: { int flgs = ((uae_s16)(src)) < 0;
11567: int flgo = ((uae_s16)(0)) < 0;
11568: int flgn = ((uae_s16)(dst)) < 0;
11569: SET_ZFLG (((uae_s16)(dst)) == 0);
11570: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11571: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
11572: COPY_CARRY;
11573: SET_NFLG (flgn != 0);
11574: put_word(srca,dst);
11575: }}}}}}m68k_incpc(6);
11576: return 20;
11577: }
11578: unsigned long REGPARAM2 CPUFUNC(op_4480_0)(uae_u32 opcode) /* NEG */
11579: {
11580: uae_u32 srcreg = (opcode & 7);
11581: OpcodeFamily = 15; CurrentInstrCycles = 6;
11582: {{ uae_s32 src = m68k_dreg(regs, srcreg);
11583: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
11584: { int flgs = ((uae_s32)(src)) < 0;
11585: int flgo = ((uae_s32)(0)) < 0;
11586: int flgn = ((uae_s32)(dst)) < 0;
11587: SET_ZFLG (((uae_s32)(dst)) == 0);
11588: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11589: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
11590: COPY_CARRY;
11591: SET_NFLG (flgn != 0);
11592: m68k_dreg(regs, srcreg) = (dst);
11593: }}}}}m68k_incpc(2);
11594: return 6;
11595: }
11596: unsigned long REGPARAM2 CPUFUNC(op_4490_0)(uae_u32 opcode) /* NEG */
11597: {
11598: uae_u32 srcreg = (opcode & 7);
11599: OpcodeFamily = 15; CurrentInstrCycles = 20;
11600: {{ uaecptr srca = m68k_areg(regs, srcreg);
11601: { uae_s32 src = get_long(srca);
11602: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
11603: { int flgs = ((uae_s32)(src)) < 0;
11604: int flgo = ((uae_s32)(0)) < 0;
11605: int flgn = ((uae_s32)(dst)) < 0;
11606: SET_ZFLG (((uae_s32)(dst)) == 0);
11607: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11608: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
11609: COPY_CARRY;
11610: SET_NFLG (flgn != 0);
11611: put_long(srca,dst);
11612: }}}}}}m68k_incpc(2);
11613: return 20;
11614: }
11615: unsigned long REGPARAM2 CPUFUNC(op_4498_0)(uae_u32 opcode) /* NEG */
11616: {
11617: uae_u32 srcreg = (opcode & 7);
11618: OpcodeFamily = 15; CurrentInstrCycles = 20;
11619: {{ uaecptr srca = m68k_areg(regs, srcreg);
11620: { uae_s32 src = get_long(srca);
11621: m68k_areg(regs, srcreg) += 4;
11622: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
11623: { int flgs = ((uae_s32)(src)) < 0;
11624: int flgo = ((uae_s32)(0)) < 0;
11625: int flgn = ((uae_s32)(dst)) < 0;
11626: SET_ZFLG (((uae_s32)(dst)) == 0);
11627: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11628: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
11629: COPY_CARRY;
11630: SET_NFLG (flgn != 0);
11631: put_long(srca,dst);
11632: }}}}}}m68k_incpc(2);
11633: return 20;
11634: }
11635: unsigned long REGPARAM2 CPUFUNC(op_44a0_0)(uae_u32 opcode) /* NEG */
11636: {
11637: uae_u32 srcreg = (opcode & 7);
11638: OpcodeFamily = 15; CurrentInstrCycles = 22;
11639: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
11640: { uae_s32 src = get_long(srca);
11641: m68k_areg (regs, srcreg) = srca;
11642: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
11643: { int flgs = ((uae_s32)(src)) < 0;
11644: int flgo = ((uae_s32)(0)) < 0;
11645: int flgn = ((uae_s32)(dst)) < 0;
11646: SET_ZFLG (((uae_s32)(dst)) == 0);
11647: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11648: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
11649: COPY_CARRY;
11650: SET_NFLG (flgn != 0);
11651: put_long(srca,dst);
11652: }}}}}}m68k_incpc(2);
11653: return 22;
11654: }
11655: unsigned long REGPARAM2 CPUFUNC(op_44a8_0)(uae_u32 opcode) /* NEG */
11656: {
11657: uae_u32 srcreg = (opcode & 7);
11658: OpcodeFamily = 15; CurrentInstrCycles = 24;
11659: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
11660: { uae_s32 src = get_long(srca);
11661: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
11662: { int flgs = ((uae_s32)(src)) < 0;
11663: int flgo = ((uae_s32)(0)) < 0;
11664: int flgn = ((uae_s32)(dst)) < 0;
11665: SET_ZFLG (((uae_s32)(dst)) == 0);
11666: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11667: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
11668: COPY_CARRY;
11669: SET_NFLG (flgn != 0);
11670: put_long(srca,dst);
11671: }}}}}}m68k_incpc(4);
11672: return 24;
11673: }
11674: unsigned long REGPARAM2 CPUFUNC(op_44b0_0)(uae_u32 opcode) /* NEG */
11675: {
11676: uae_u32 srcreg = (opcode & 7);
11677: OpcodeFamily = 15; CurrentInstrCycles = 26;
11678: {{m68k_incpc(2);
11679: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
11680: BusCyclePenalty += 2;
11681: { uae_s32 src = get_long(srca);
11682: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
11683: { int flgs = ((uae_s32)(src)) < 0;
11684: int flgo = ((uae_s32)(0)) < 0;
11685: int flgn = ((uae_s32)(dst)) < 0;
11686: SET_ZFLG (((uae_s32)(dst)) == 0);
11687: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11688: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
11689: COPY_CARRY;
11690: SET_NFLG (flgn != 0);
11691: put_long(srca,dst);
11692: }}}}}}}return 26;
11693: }
11694: unsigned long REGPARAM2 CPUFUNC(op_44b8_0)(uae_u32 opcode) /* NEG */
11695: {
11696: OpcodeFamily = 15; CurrentInstrCycles = 24;
11697: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
11698: { uae_s32 src = get_long(srca);
11699: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
11700: { int flgs = ((uae_s32)(src)) < 0;
11701: int flgo = ((uae_s32)(0)) < 0;
11702: int flgn = ((uae_s32)(dst)) < 0;
11703: SET_ZFLG (((uae_s32)(dst)) == 0);
11704: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11705: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
11706: COPY_CARRY;
11707: SET_NFLG (flgn != 0);
11708: put_long(srca,dst);
11709: }}}}}}m68k_incpc(4);
11710: return 24;
11711: }
11712: unsigned long REGPARAM2 CPUFUNC(op_44b9_0)(uae_u32 opcode) /* NEG */
11713: {
11714: OpcodeFamily = 15; CurrentInstrCycles = 28;
11715: {{ uaecptr srca = get_ilong(2);
11716: { uae_s32 src = get_long(srca);
11717: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
11718: { int flgs = ((uae_s32)(src)) < 0;
11719: int flgo = ((uae_s32)(0)) < 0;
11720: int flgn = ((uae_s32)(dst)) < 0;
11721: SET_ZFLG (((uae_s32)(dst)) == 0);
11722: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
11723: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
11724: COPY_CARRY;
11725: SET_NFLG (flgn != 0);
11726: put_long(srca,dst);
11727: }}}}}}m68k_incpc(6);
11728: return 28;
11729: }
11730: unsigned long REGPARAM2 CPUFUNC(op_44c0_0)(uae_u32 opcode) /* MV2SR */
11731: {
11732: uae_u32 srcreg = (opcode & 7);
11733: OpcodeFamily = 33; CurrentInstrCycles = 12;
11734: {{ uae_s16 src = m68k_dreg(regs, srcreg);
11735: MakeSR();
11736: regs.sr &= 0xFF00;
11737: regs.sr |= src & 0xFF;
11738: MakeFromSR();
11739: }}m68k_incpc(2);
11740: return 12;
11741: }
11742: unsigned long REGPARAM2 CPUFUNC(op_44d0_0)(uae_u32 opcode) /* MV2SR */
11743: {
11744: uae_u32 srcreg = (opcode & 7);
11745: OpcodeFamily = 33; CurrentInstrCycles = 16;
11746: {{ uaecptr srca = m68k_areg(regs, srcreg);
11747: { uae_s16 src = get_word(srca);
11748: MakeSR();
11749: regs.sr &= 0xFF00;
11750: regs.sr |= src & 0xFF;
11751: MakeFromSR();
11752: }}}m68k_incpc(2);
11753: return 16;
11754: }
11755: unsigned long REGPARAM2 CPUFUNC(op_44d8_0)(uae_u32 opcode) /* MV2SR */
11756: {
11757: uae_u32 srcreg = (opcode & 7);
11758: OpcodeFamily = 33; CurrentInstrCycles = 16;
11759: {{ uaecptr srca = m68k_areg(regs, srcreg);
11760: { uae_s16 src = get_word(srca);
11761: m68k_areg(regs, srcreg) += 2;
11762: MakeSR();
11763: regs.sr &= 0xFF00;
11764: regs.sr |= src & 0xFF;
11765: MakeFromSR();
11766: }}}m68k_incpc(2);
11767: return 16;
11768: }
11769: unsigned long REGPARAM2 CPUFUNC(op_44e0_0)(uae_u32 opcode) /* MV2SR */
11770: {
11771: uae_u32 srcreg = (opcode & 7);
11772: OpcodeFamily = 33; CurrentInstrCycles = 18;
11773: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
11774: { uae_s16 src = get_word(srca);
11775: m68k_areg (regs, srcreg) = srca;
11776: MakeSR();
11777: regs.sr &= 0xFF00;
11778: regs.sr |= src & 0xFF;
11779: MakeFromSR();
11780: }}}m68k_incpc(2);
11781: return 18;
11782: }
11783: unsigned long REGPARAM2 CPUFUNC(op_44e8_0)(uae_u32 opcode) /* MV2SR */
11784: {
11785: uae_u32 srcreg = (opcode & 7);
11786: OpcodeFamily = 33; CurrentInstrCycles = 20;
11787: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
11788: { uae_s16 src = get_word(srca);
11789: MakeSR();
11790: regs.sr &= 0xFF00;
11791: regs.sr |= src & 0xFF;
11792: MakeFromSR();
11793: }}}m68k_incpc(4);
11794: return 20;
11795: }
11796: unsigned long REGPARAM2 CPUFUNC(op_44f0_0)(uae_u32 opcode) /* MV2SR */
11797: {
11798: uae_u32 srcreg = (opcode & 7);
11799: OpcodeFamily = 33; CurrentInstrCycles = 22;
11800: {{m68k_incpc(2);
11801: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
11802: BusCyclePenalty += 2;
11803: { uae_s16 src = get_word(srca);
11804: MakeSR();
11805: regs.sr &= 0xFF00;
11806: regs.sr |= src & 0xFF;
11807: MakeFromSR();
11808: }}}}return 22;
11809: }
11810: unsigned long REGPARAM2 CPUFUNC(op_44f8_0)(uae_u32 opcode) /* MV2SR */
11811: {
11812: OpcodeFamily = 33; CurrentInstrCycles = 20;
11813: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
11814: { uae_s16 src = get_word(srca);
11815: MakeSR();
11816: regs.sr &= 0xFF00;
11817: regs.sr |= src & 0xFF;
11818: MakeFromSR();
11819: }}}m68k_incpc(4);
11820: return 20;
11821: }
11822: unsigned long REGPARAM2 CPUFUNC(op_44f9_0)(uae_u32 opcode) /* MV2SR */
11823: {
11824: OpcodeFamily = 33; CurrentInstrCycles = 24;
11825: {{ uaecptr srca = get_ilong(2);
11826: { uae_s16 src = get_word(srca);
11827: MakeSR();
11828: regs.sr &= 0xFF00;
11829: regs.sr |= src & 0xFF;
11830: MakeFromSR();
11831: }}}m68k_incpc(6);
11832: return 24;
11833: }
11834: unsigned long REGPARAM2 CPUFUNC(op_44fa_0)(uae_u32 opcode) /* MV2SR */
11835: {
11836: OpcodeFamily = 33; CurrentInstrCycles = 20;
11837: {{ uaecptr srca = m68k_getpc () + 2;
11838: srca += (uae_s32)(uae_s16)get_iword(2);
11839: { uae_s16 src = get_word(srca);
11840: MakeSR();
11841: regs.sr &= 0xFF00;
11842: regs.sr |= src & 0xFF;
11843: MakeFromSR();
11844: }}}m68k_incpc(4);
11845: return 20;
11846: }
11847: unsigned long REGPARAM2 CPUFUNC(op_44fb_0)(uae_u32 opcode) /* MV2SR */
11848: {
11849: OpcodeFamily = 33; CurrentInstrCycles = 22;
11850: {{m68k_incpc(2);
11851: { uaecptr tmppc = m68k_getpc();
11852: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
11853: BusCyclePenalty += 2;
11854: { uae_s16 src = get_word(srca);
11855: MakeSR();
11856: regs.sr &= 0xFF00;
11857: regs.sr |= src & 0xFF;
11858: MakeFromSR();
11859: }}}}return 22;
11860: }
11861: unsigned long REGPARAM2 CPUFUNC(op_44fc_0)(uae_u32 opcode) /* MV2SR */
11862: {
11863: OpcodeFamily = 33; CurrentInstrCycles = 16;
11864: {{ uae_s16 src = get_iword(2);
11865: MakeSR();
11866: regs.sr &= 0xFF00;
11867: regs.sr |= src & 0xFF;
11868: MakeFromSR();
11869: }}m68k_incpc(4);
11870: return 16;
11871: }
11872: unsigned long REGPARAM2 CPUFUNC(op_4600_0)(uae_u32 opcode) /* NOT */
11873: {
11874: uae_u32 srcreg = (opcode & 7);
11875: OpcodeFamily = 19; CurrentInstrCycles = 4;
11876: {{ uae_s8 src = m68k_dreg(regs, srcreg);
11877: { uae_u32 dst = ~src;
11878: CLEAR_CZNV;
11879: SET_ZFLG (((uae_s8)(dst)) == 0);
11880: SET_NFLG (((uae_s8)(dst)) < 0);
11881: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
11882: }}}m68k_incpc(2);
11883: return 4;
11884: }
11885: unsigned long REGPARAM2 CPUFUNC(op_4610_0)(uae_u32 opcode) /* NOT */
11886: {
11887: uae_u32 srcreg = (opcode & 7);
11888: OpcodeFamily = 19; CurrentInstrCycles = 12;
11889: {{ uaecptr srca = m68k_areg(regs, srcreg);
11890: { uae_s8 src = get_byte(srca);
11891: { uae_u32 dst = ~src;
11892: CLEAR_CZNV;
11893: SET_ZFLG (((uae_s8)(dst)) == 0);
11894: SET_NFLG (((uae_s8)(dst)) < 0);
11895: put_byte(srca,dst);
11896: }}}}m68k_incpc(2);
11897: return 12;
11898: }
11899: unsigned long REGPARAM2 CPUFUNC(op_4618_0)(uae_u32 opcode) /* NOT */
11900: {
11901: uae_u32 srcreg = (opcode & 7);
11902: OpcodeFamily = 19; CurrentInstrCycles = 12;
11903: {{ uaecptr srca = m68k_areg(regs, srcreg);
11904: { uae_s8 src = get_byte(srca);
11905: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
11906: { uae_u32 dst = ~src;
11907: CLEAR_CZNV;
11908: SET_ZFLG (((uae_s8)(dst)) == 0);
11909: SET_NFLG (((uae_s8)(dst)) < 0);
11910: put_byte(srca,dst);
11911: }}}}m68k_incpc(2);
11912: return 12;
11913: }
11914: unsigned long REGPARAM2 CPUFUNC(op_4620_0)(uae_u32 opcode) /* NOT */
11915: {
11916: uae_u32 srcreg = (opcode & 7);
11917: OpcodeFamily = 19; CurrentInstrCycles = 14;
11918: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
11919: { uae_s8 src = get_byte(srca);
11920: m68k_areg (regs, srcreg) = srca;
11921: { uae_u32 dst = ~src;
11922: CLEAR_CZNV;
11923: SET_ZFLG (((uae_s8)(dst)) == 0);
11924: SET_NFLG (((uae_s8)(dst)) < 0);
11925: put_byte(srca,dst);
11926: }}}}m68k_incpc(2);
11927: return 14;
11928: }
11929: unsigned long REGPARAM2 CPUFUNC(op_4628_0)(uae_u32 opcode) /* NOT */
11930: {
11931: uae_u32 srcreg = (opcode & 7);
11932: OpcodeFamily = 19; CurrentInstrCycles = 16;
11933: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
11934: { uae_s8 src = get_byte(srca);
11935: { uae_u32 dst = ~src;
11936: CLEAR_CZNV;
11937: SET_ZFLG (((uae_s8)(dst)) == 0);
11938: SET_NFLG (((uae_s8)(dst)) < 0);
11939: put_byte(srca,dst);
11940: }}}}m68k_incpc(4);
11941: return 16;
11942: }
11943: unsigned long REGPARAM2 CPUFUNC(op_4630_0)(uae_u32 opcode) /* NOT */
11944: {
11945: uae_u32 srcreg = (opcode & 7);
11946: OpcodeFamily = 19; CurrentInstrCycles = 18;
11947: {{m68k_incpc(2);
11948: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
11949: BusCyclePenalty += 2;
11950: { uae_s8 src = get_byte(srca);
11951: { uae_u32 dst = ~src;
11952: CLEAR_CZNV;
11953: SET_ZFLG (((uae_s8)(dst)) == 0);
11954: SET_NFLG (((uae_s8)(dst)) < 0);
11955: put_byte(srca,dst);
11956: }}}}}return 18;
11957: }
11958: unsigned long REGPARAM2 CPUFUNC(op_4638_0)(uae_u32 opcode) /* NOT */
11959: {
11960: OpcodeFamily = 19; CurrentInstrCycles = 16;
11961: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
11962: { uae_s8 src = get_byte(srca);
11963: { uae_u32 dst = ~src;
11964: CLEAR_CZNV;
11965: SET_ZFLG (((uae_s8)(dst)) == 0);
11966: SET_NFLG (((uae_s8)(dst)) < 0);
11967: put_byte(srca,dst);
11968: }}}}m68k_incpc(4);
11969: return 16;
11970: }
11971: unsigned long REGPARAM2 CPUFUNC(op_4639_0)(uae_u32 opcode) /* NOT */
11972: {
11973: OpcodeFamily = 19; CurrentInstrCycles = 20;
11974: {{ uaecptr srca = get_ilong(2);
11975: { uae_s8 src = get_byte(srca);
11976: { uae_u32 dst = ~src;
11977: CLEAR_CZNV;
11978: SET_ZFLG (((uae_s8)(dst)) == 0);
11979: SET_NFLG (((uae_s8)(dst)) < 0);
11980: put_byte(srca,dst);
11981: }}}}m68k_incpc(6);
11982: return 20;
11983: }
11984: unsigned long REGPARAM2 CPUFUNC(op_4640_0)(uae_u32 opcode) /* NOT */
11985: {
11986: uae_u32 srcreg = (opcode & 7);
11987: OpcodeFamily = 19; CurrentInstrCycles = 4;
11988: {{ uae_s16 src = m68k_dreg(regs, srcreg);
11989: { uae_u32 dst = ~src;
11990: CLEAR_CZNV;
11991: SET_ZFLG (((uae_s16)(dst)) == 0);
11992: SET_NFLG (((uae_s16)(dst)) < 0);
11993: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
11994: }}}m68k_incpc(2);
11995: return 4;
11996: }
11997: unsigned long REGPARAM2 CPUFUNC(op_4650_0)(uae_u32 opcode) /* NOT */
11998: {
11999: uae_u32 srcreg = (opcode & 7);
12000: OpcodeFamily = 19; CurrentInstrCycles = 12;
12001: {{ uaecptr srca = m68k_areg(regs, srcreg);
12002: { uae_s16 src = get_word(srca);
12003: { uae_u32 dst = ~src;
12004: CLEAR_CZNV;
12005: SET_ZFLG (((uae_s16)(dst)) == 0);
12006: SET_NFLG (((uae_s16)(dst)) < 0);
12007: put_word(srca,dst);
12008: }}}}m68k_incpc(2);
12009: return 12;
12010: }
12011: unsigned long REGPARAM2 CPUFUNC(op_4658_0)(uae_u32 opcode) /* NOT */
12012: {
12013: uae_u32 srcreg = (opcode & 7);
12014: OpcodeFamily = 19; CurrentInstrCycles = 12;
12015: {{ uaecptr srca = m68k_areg(regs, srcreg);
12016: { uae_s16 src = get_word(srca);
12017: m68k_areg(regs, srcreg) += 2;
12018: { uae_u32 dst = ~src;
12019: CLEAR_CZNV;
12020: SET_ZFLG (((uae_s16)(dst)) == 0);
12021: SET_NFLG (((uae_s16)(dst)) < 0);
12022: put_word(srca,dst);
12023: }}}}m68k_incpc(2);
12024: return 12;
12025: }
12026: unsigned long REGPARAM2 CPUFUNC(op_4660_0)(uae_u32 opcode) /* NOT */
12027: {
12028: uae_u32 srcreg = (opcode & 7);
12029: OpcodeFamily = 19; CurrentInstrCycles = 14;
12030: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
12031: { uae_s16 src = get_word(srca);
12032: m68k_areg (regs, srcreg) = srca;
12033: { uae_u32 dst = ~src;
12034: CLEAR_CZNV;
12035: SET_ZFLG (((uae_s16)(dst)) == 0);
12036: SET_NFLG (((uae_s16)(dst)) < 0);
12037: put_word(srca,dst);
12038: }}}}m68k_incpc(2);
12039: return 14;
12040: }
12041: unsigned long REGPARAM2 CPUFUNC(op_4668_0)(uae_u32 opcode) /* NOT */
12042: {
12043: uae_u32 srcreg = (opcode & 7);
12044: OpcodeFamily = 19; CurrentInstrCycles = 16;
12045: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
12046: { uae_s16 src = get_word(srca);
12047: { uae_u32 dst = ~src;
12048: CLEAR_CZNV;
12049: SET_ZFLG (((uae_s16)(dst)) == 0);
12050: SET_NFLG (((uae_s16)(dst)) < 0);
12051: put_word(srca,dst);
12052: }}}}m68k_incpc(4);
12053: return 16;
12054: }
12055: unsigned long REGPARAM2 CPUFUNC(op_4670_0)(uae_u32 opcode) /* NOT */
12056: {
12057: uae_u32 srcreg = (opcode & 7);
12058: OpcodeFamily = 19; CurrentInstrCycles = 18;
12059: {{m68k_incpc(2);
12060: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
12061: BusCyclePenalty += 2;
12062: { uae_s16 src = get_word(srca);
12063: { uae_u32 dst = ~src;
12064: CLEAR_CZNV;
12065: SET_ZFLG (((uae_s16)(dst)) == 0);
12066: SET_NFLG (((uae_s16)(dst)) < 0);
12067: put_word(srca,dst);
12068: }}}}}return 18;
12069: }
12070: unsigned long REGPARAM2 CPUFUNC(op_4678_0)(uae_u32 opcode) /* NOT */
12071: {
12072: OpcodeFamily = 19; CurrentInstrCycles = 16;
12073: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
12074: { uae_s16 src = get_word(srca);
12075: { uae_u32 dst = ~src;
12076: CLEAR_CZNV;
12077: SET_ZFLG (((uae_s16)(dst)) == 0);
12078: SET_NFLG (((uae_s16)(dst)) < 0);
12079: put_word(srca,dst);
12080: }}}}m68k_incpc(4);
12081: return 16;
12082: }
12083: unsigned long REGPARAM2 CPUFUNC(op_4679_0)(uae_u32 opcode) /* NOT */
12084: {
12085: OpcodeFamily = 19; CurrentInstrCycles = 20;
12086: {{ uaecptr srca = get_ilong(2);
12087: { uae_s16 src = get_word(srca);
12088: { uae_u32 dst = ~src;
12089: CLEAR_CZNV;
12090: SET_ZFLG (((uae_s16)(dst)) == 0);
12091: SET_NFLG (((uae_s16)(dst)) < 0);
12092: put_word(srca,dst);
12093: }}}}m68k_incpc(6);
12094: return 20;
12095: }
12096: unsigned long REGPARAM2 CPUFUNC(op_4680_0)(uae_u32 opcode) /* NOT */
12097: {
12098: uae_u32 srcreg = (opcode & 7);
12099: OpcodeFamily = 19; CurrentInstrCycles = 6;
12100: {{ uae_s32 src = m68k_dreg(regs, srcreg);
12101: { uae_u32 dst = ~src;
12102: CLEAR_CZNV;
12103: SET_ZFLG (((uae_s32)(dst)) == 0);
12104: SET_NFLG (((uae_s32)(dst)) < 0);
12105: m68k_dreg(regs, srcreg) = (dst);
12106: }}}m68k_incpc(2);
12107: return 6;
12108: }
12109: unsigned long REGPARAM2 CPUFUNC(op_4690_0)(uae_u32 opcode) /* NOT */
12110: {
12111: uae_u32 srcreg = (opcode & 7);
12112: OpcodeFamily = 19; CurrentInstrCycles = 20;
12113: {{ uaecptr srca = m68k_areg(regs, srcreg);
12114: { uae_s32 src = get_long(srca);
12115: { uae_u32 dst = ~src;
12116: CLEAR_CZNV;
12117: SET_ZFLG (((uae_s32)(dst)) == 0);
12118: SET_NFLG (((uae_s32)(dst)) < 0);
12119: put_long(srca,dst);
12120: }}}}m68k_incpc(2);
12121: return 20;
12122: }
12123: unsigned long REGPARAM2 CPUFUNC(op_4698_0)(uae_u32 opcode) /* NOT */
12124: {
12125: uae_u32 srcreg = (opcode & 7);
12126: OpcodeFamily = 19; CurrentInstrCycles = 20;
12127: {{ uaecptr srca = m68k_areg(regs, srcreg);
12128: { uae_s32 src = get_long(srca);
12129: m68k_areg(regs, srcreg) += 4;
12130: { uae_u32 dst = ~src;
12131: CLEAR_CZNV;
12132: SET_ZFLG (((uae_s32)(dst)) == 0);
12133: SET_NFLG (((uae_s32)(dst)) < 0);
12134: put_long(srca,dst);
12135: }}}}m68k_incpc(2);
12136: return 20;
12137: }
12138: unsigned long REGPARAM2 CPUFUNC(op_46a0_0)(uae_u32 opcode) /* NOT */
12139: {
12140: uae_u32 srcreg = (opcode & 7);
12141: OpcodeFamily = 19; CurrentInstrCycles = 22;
12142: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
12143: { uae_s32 src = get_long(srca);
12144: m68k_areg (regs, srcreg) = srca;
12145: { uae_u32 dst = ~src;
12146: CLEAR_CZNV;
12147: SET_ZFLG (((uae_s32)(dst)) == 0);
12148: SET_NFLG (((uae_s32)(dst)) < 0);
12149: put_long(srca,dst);
12150: }}}}m68k_incpc(2);
12151: return 22;
12152: }
12153: unsigned long REGPARAM2 CPUFUNC(op_46a8_0)(uae_u32 opcode) /* NOT */
12154: {
12155: uae_u32 srcreg = (opcode & 7);
12156: OpcodeFamily = 19; CurrentInstrCycles = 24;
12157: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
12158: { uae_s32 src = get_long(srca);
12159: { uae_u32 dst = ~src;
12160: CLEAR_CZNV;
12161: SET_ZFLG (((uae_s32)(dst)) == 0);
12162: SET_NFLG (((uae_s32)(dst)) < 0);
12163: put_long(srca,dst);
12164: }}}}m68k_incpc(4);
12165: return 24;
12166: }
12167: unsigned long REGPARAM2 CPUFUNC(op_46b0_0)(uae_u32 opcode) /* NOT */
12168: {
12169: uae_u32 srcreg = (opcode & 7);
12170: OpcodeFamily = 19; CurrentInstrCycles = 26;
12171: {{m68k_incpc(2);
12172: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
12173: BusCyclePenalty += 2;
12174: { uae_s32 src = get_long(srca);
12175: { uae_u32 dst = ~src;
12176: CLEAR_CZNV;
12177: SET_ZFLG (((uae_s32)(dst)) == 0);
12178: SET_NFLG (((uae_s32)(dst)) < 0);
12179: put_long(srca,dst);
12180: }}}}}return 26;
12181: }
12182: unsigned long REGPARAM2 CPUFUNC(op_46b8_0)(uae_u32 opcode) /* NOT */
12183: {
12184: OpcodeFamily = 19; CurrentInstrCycles = 24;
12185: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
12186: { uae_s32 src = get_long(srca);
12187: { uae_u32 dst = ~src;
12188: CLEAR_CZNV;
12189: SET_ZFLG (((uae_s32)(dst)) == 0);
12190: SET_NFLG (((uae_s32)(dst)) < 0);
12191: put_long(srca,dst);
12192: }}}}m68k_incpc(4);
12193: return 24;
12194: }
12195: unsigned long REGPARAM2 CPUFUNC(op_46b9_0)(uae_u32 opcode) /* NOT */
12196: {
12197: OpcodeFamily = 19; CurrentInstrCycles = 28;
12198: {{ uaecptr srca = get_ilong(2);
12199: { uae_s32 src = get_long(srca);
12200: { uae_u32 dst = ~src;
12201: CLEAR_CZNV;
12202: SET_ZFLG (((uae_s32)(dst)) == 0);
12203: SET_NFLG (((uae_s32)(dst)) < 0);
12204: put_long(srca,dst);
12205: }}}}m68k_incpc(6);
12206: return 28;
12207: }
12208: unsigned long REGPARAM2 CPUFUNC(op_46c0_0)(uae_u32 opcode) /* MV2SR */
12209: {
12210: uae_u32 srcreg = (opcode & 7);
12211: OpcodeFamily = 33; CurrentInstrCycles = 12;
12212: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel781; }
12213: {{ uae_s16 src = m68k_dreg(regs, srcreg);
12214: regs.sr = src;
12215: MakeFromSR();
12216: }}}m68k_incpc(2);
12217: endlabel781: ;
12218: return 12;
12219: }
12220: unsigned long REGPARAM2 CPUFUNC(op_46d0_0)(uae_u32 opcode) /* MV2SR */
12221: {
12222: uae_u32 srcreg = (opcode & 7);
12223: OpcodeFamily = 33; CurrentInstrCycles = 16;
12224: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel782; }
12225: {{ uaecptr srca = m68k_areg(regs, srcreg);
12226: { uae_s16 src = get_word(srca);
12227: regs.sr = src;
12228: MakeFromSR();
12229: }}}}m68k_incpc(2);
12230: endlabel782: ;
12231: return 16;
12232: }
12233: unsigned long REGPARAM2 CPUFUNC(op_46d8_0)(uae_u32 opcode) /* MV2SR */
12234: {
12235: uae_u32 srcreg = (opcode & 7);
12236: OpcodeFamily = 33; CurrentInstrCycles = 16;
12237: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel783; }
12238: {{ uaecptr srca = m68k_areg(regs, srcreg);
12239: { uae_s16 src = get_word(srca);
12240: m68k_areg(regs, srcreg) += 2;
12241: regs.sr = src;
12242: MakeFromSR();
12243: }}}}m68k_incpc(2);
12244: endlabel783: ;
12245: return 16;
12246: }
12247: unsigned long REGPARAM2 CPUFUNC(op_46e0_0)(uae_u32 opcode) /* MV2SR */
12248: {
12249: uae_u32 srcreg = (opcode & 7);
12250: OpcodeFamily = 33; CurrentInstrCycles = 18;
12251: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel784; }
12252: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
12253: { uae_s16 src = get_word(srca);
12254: m68k_areg (regs, srcreg) = srca;
12255: regs.sr = src;
12256: MakeFromSR();
12257: }}}}m68k_incpc(2);
12258: endlabel784: ;
12259: return 18;
12260: }
12261: unsigned long REGPARAM2 CPUFUNC(op_46e8_0)(uae_u32 opcode) /* MV2SR */
12262: {
12263: uae_u32 srcreg = (opcode & 7);
12264: OpcodeFamily = 33; CurrentInstrCycles = 20;
12265: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel785; }
12266: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
12267: { uae_s16 src = get_word(srca);
12268: regs.sr = src;
12269: MakeFromSR();
12270: }}}}m68k_incpc(4);
12271: endlabel785: ;
12272: return 20;
12273: }
12274: unsigned long REGPARAM2 CPUFUNC(op_46f0_0)(uae_u32 opcode) /* MV2SR */
12275: {
12276: uae_u32 srcreg = (opcode & 7);
12277: OpcodeFamily = 33; CurrentInstrCycles = 22;
12278: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel786; }
12279: {{m68k_incpc(2);
12280: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
12281: BusCyclePenalty += 2;
12282: { uae_s16 src = get_word(srca);
12283: regs.sr = src;
12284: MakeFromSR();
12285: }}}}}endlabel786: ;
12286: return 22;
12287: }
12288: unsigned long REGPARAM2 CPUFUNC(op_46f8_0)(uae_u32 opcode) /* MV2SR */
12289: {
12290: OpcodeFamily = 33; CurrentInstrCycles = 20;
12291: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel787; }
12292: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
12293: { uae_s16 src = get_word(srca);
12294: regs.sr = src;
12295: MakeFromSR();
12296: }}}}m68k_incpc(4);
12297: endlabel787: ;
12298: return 20;
12299: }
12300: unsigned long REGPARAM2 CPUFUNC(op_46f9_0)(uae_u32 opcode) /* MV2SR */
12301: {
12302: OpcodeFamily = 33; CurrentInstrCycles = 24;
12303: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel788; }
12304: {{ uaecptr srca = get_ilong(2);
12305: { uae_s16 src = get_word(srca);
12306: regs.sr = src;
12307: MakeFromSR();
12308: }}}}m68k_incpc(6);
12309: endlabel788: ;
12310: return 24;
12311: }
12312: unsigned long REGPARAM2 CPUFUNC(op_46fa_0)(uae_u32 opcode) /* MV2SR */
12313: {
12314: OpcodeFamily = 33; CurrentInstrCycles = 20;
12315: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel789; }
12316: {{ uaecptr srca = m68k_getpc () + 2;
12317: srca += (uae_s32)(uae_s16)get_iword(2);
12318: { uae_s16 src = get_word(srca);
12319: regs.sr = src;
12320: MakeFromSR();
12321: }}}}m68k_incpc(4);
12322: endlabel789: ;
12323: return 20;
12324: }
12325: unsigned long REGPARAM2 CPUFUNC(op_46fb_0)(uae_u32 opcode) /* MV2SR */
12326: {
12327: OpcodeFamily = 33; CurrentInstrCycles = 22;
12328: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel790; }
12329: {{m68k_incpc(2);
12330: { uaecptr tmppc = m68k_getpc();
12331: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
12332: BusCyclePenalty += 2;
12333: { uae_s16 src = get_word(srca);
12334: regs.sr = src;
12335: MakeFromSR();
12336: }}}}}endlabel790: ;
12337: return 22;
12338: }
12339: unsigned long REGPARAM2 CPUFUNC(op_46fc_0)(uae_u32 opcode) /* MV2SR */
12340: {
12341: OpcodeFamily = 33; CurrentInstrCycles = 16;
12342: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel791; }
12343: {{ uae_s16 src = get_iword(2);
12344: regs.sr = src;
12345: MakeFromSR();
12346: }}}m68k_incpc(4);
12347: endlabel791: ;
12348: return 16;
12349: }
12350: unsigned long REGPARAM2 CPUFUNC(op_4800_0)(uae_u32 opcode) /* NBCD */
12351: {
12352: uae_u32 srcreg = (opcode & 7);
12353: OpcodeFamily = 17; CurrentInstrCycles = 6;
12354: {{ uae_s8 src = m68k_dreg(regs, srcreg);
12355: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
12356: uae_u16 newv_hi = - (src & 0xF0);
12357: uae_u16 newv;
12358: int cflg;
12359: if (newv_lo > 9) { newv_lo -= 6; }
12360: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
12361: if (cflg) newv -= 0x60;
12362: SET_CFLG (cflg);
12363: COPY_CARRY;
12364: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
12365: SET_NFLG (((uae_s8)(newv)) < 0);
12366: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
12367: }}}m68k_incpc(2);
12368: return 6;
12369: }
12370: unsigned long REGPARAM2 CPUFUNC(op_4808_0)(uae_u32 opcode) /* LINK */
12371: {
12372: uae_u32 srcreg = (opcode & 7);
12373: OpcodeFamily = 47; CurrentInstrCycles = 22;
12374: {{ uaecptr olda = m68k_areg(regs, 7) - 4;
12375: m68k_areg (regs, 7) = olda;
12376: { uae_s32 src = m68k_areg(regs, srcreg);
12377: put_long(olda,src);
12378: m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
12379: { uae_s32 offs = get_ilong(2);
12380: m68k_areg(regs, 7) += offs;
12381: }}}}m68k_incpc(6);
12382: return 22;
12383: }
12384: unsigned long REGPARAM2 CPUFUNC(op_4810_0)(uae_u32 opcode) /* NBCD */
12385: {
12386: uae_u32 srcreg = (opcode & 7);
12387: OpcodeFamily = 17; CurrentInstrCycles = 12;
12388: {{ uaecptr srca = m68k_areg(regs, srcreg);
12389: { uae_s8 src = get_byte(srca);
12390: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
12391: uae_u16 newv_hi = - (src & 0xF0);
12392: uae_u16 newv;
12393: int cflg;
12394: if (newv_lo > 9) { newv_lo -= 6; }
12395: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
12396: if (cflg) newv -= 0x60;
12397: SET_CFLG (cflg);
12398: COPY_CARRY;
12399: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
12400: SET_NFLG (((uae_s8)(newv)) < 0);
12401: put_byte(srca,newv);
12402: }}}}m68k_incpc(2);
12403: return 12;
12404: }
12405: unsigned long REGPARAM2 CPUFUNC(op_4818_0)(uae_u32 opcode) /* NBCD */
12406: {
12407: uae_u32 srcreg = (opcode & 7);
12408: OpcodeFamily = 17; CurrentInstrCycles = 12;
12409: {{ uaecptr srca = m68k_areg(regs, srcreg);
12410: { uae_s8 src = get_byte(srca);
12411: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
12412: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
12413: uae_u16 newv_hi = - (src & 0xF0);
12414: uae_u16 newv;
12415: int cflg;
12416: if (newv_lo > 9) { newv_lo -= 6; }
12417: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
12418: if (cflg) newv -= 0x60;
12419: SET_CFLG (cflg);
12420: COPY_CARRY;
12421: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
12422: SET_NFLG (((uae_s8)(newv)) < 0);
12423: put_byte(srca,newv);
12424: }}}}m68k_incpc(2);
12425: return 12;
12426: }
12427: unsigned long REGPARAM2 CPUFUNC(op_4820_0)(uae_u32 opcode) /* NBCD */
12428: {
12429: uae_u32 srcreg = (opcode & 7);
12430: OpcodeFamily = 17; CurrentInstrCycles = 14;
12431: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
12432: { uae_s8 src = get_byte(srca);
12433: m68k_areg (regs, srcreg) = srca;
12434: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
12435: uae_u16 newv_hi = - (src & 0xF0);
12436: uae_u16 newv;
12437: int cflg;
12438: if (newv_lo > 9) { newv_lo -= 6; }
12439: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
12440: if (cflg) newv -= 0x60;
12441: SET_CFLG (cflg);
12442: COPY_CARRY;
12443: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
12444: SET_NFLG (((uae_s8)(newv)) < 0);
12445: put_byte(srca,newv);
12446: }}}}m68k_incpc(2);
12447: return 14;
12448: }
12449: unsigned long REGPARAM2 CPUFUNC(op_4828_0)(uae_u32 opcode) /* NBCD */
12450: {
12451: uae_u32 srcreg = (opcode & 7);
12452: OpcodeFamily = 17; CurrentInstrCycles = 16;
12453: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
12454: { uae_s8 src = get_byte(srca);
12455: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
12456: uae_u16 newv_hi = - (src & 0xF0);
12457: uae_u16 newv;
12458: int cflg;
12459: if (newv_lo > 9) { newv_lo -= 6; }
12460: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
12461: if (cflg) newv -= 0x60;
12462: SET_CFLG (cflg);
12463: COPY_CARRY;
12464: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
12465: SET_NFLG (((uae_s8)(newv)) < 0);
12466: put_byte(srca,newv);
12467: }}}}m68k_incpc(4);
12468: return 16;
12469: }
12470: unsigned long REGPARAM2 CPUFUNC(op_4830_0)(uae_u32 opcode) /* NBCD */
12471: {
12472: uae_u32 srcreg = (opcode & 7);
12473: OpcodeFamily = 17; CurrentInstrCycles = 18;
12474: {{m68k_incpc(2);
12475: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
12476: BusCyclePenalty += 2;
12477: { uae_s8 src = get_byte(srca);
12478: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
12479: uae_u16 newv_hi = - (src & 0xF0);
12480: uae_u16 newv;
12481: int cflg;
12482: if (newv_lo > 9) { newv_lo -= 6; }
12483: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
12484: if (cflg) newv -= 0x60;
12485: SET_CFLG (cflg);
12486: COPY_CARRY;
12487: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
12488: SET_NFLG (((uae_s8)(newv)) < 0);
12489: put_byte(srca,newv);
12490: }}}}}return 18;
12491: }
12492: unsigned long REGPARAM2 CPUFUNC(op_4838_0)(uae_u32 opcode) /* NBCD */
12493: {
12494: OpcodeFamily = 17; CurrentInstrCycles = 16;
12495: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
12496: { uae_s8 src = get_byte(srca);
12497: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
12498: uae_u16 newv_hi = - (src & 0xF0);
12499: uae_u16 newv;
12500: int cflg;
12501: if (newv_lo > 9) { newv_lo -= 6; }
12502: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
12503: if (cflg) newv -= 0x60;
12504: SET_CFLG (cflg);
12505: COPY_CARRY;
12506: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
12507: SET_NFLG (((uae_s8)(newv)) < 0);
12508: put_byte(srca,newv);
12509: }}}}m68k_incpc(4);
12510: return 16;
12511: }
12512: unsigned long REGPARAM2 CPUFUNC(op_4839_0)(uae_u32 opcode) /* NBCD */
12513: {
12514: OpcodeFamily = 17; CurrentInstrCycles = 20;
12515: {{ uaecptr srca = get_ilong(2);
12516: { uae_s8 src = get_byte(srca);
12517: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
12518: uae_u16 newv_hi = - (src & 0xF0);
12519: uae_u16 newv;
12520: int cflg;
12521: if (newv_lo > 9) { newv_lo -= 6; }
12522: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
12523: if (cflg) newv -= 0x60;
12524: SET_CFLG (cflg);
12525: COPY_CARRY;
12526: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
12527: SET_NFLG (((uae_s8)(newv)) < 0);
12528: put_byte(srca,newv);
12529: }}}}m68k_incpc(6);
12530: return 20;
12531: }
12532: unsigned long REGPARAM2 CPUFUNC(op_4840_0)(uae_u32 opcode) /* SWAP */
12533: {
12534: uae_u32 srcreg = (opcode & 7);
12535: OpcodeFamily = 34; CurrentInstrCycles = 4;
12536: {{ uae_s32 src = m68k_dreg(regs, srcreg);
12537: { uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
12538: CLEAR_CZNV;
12539: SET_ZFLG (((uae_s32)(dst)) == 0);
12540: SET_NFLG (((uae_s32)(dst)) < 0);
12541: m68k_dreg(regs, srcreg) = (dst);
12542: }}}m68k_incpc(2);
12543: return 4;
12544: }
12545: unsigned long REGPARAM2 CPUFUNC(op_4848_0)(uae_u32 opcode) /* BKPT */
12546: {
12547: uae_u32 srcreg = (opcode & 7);
12548: OpcodeFamily = 99; CurrentInstrCycles = 4;
12549: {m68k_incpc(2);
12550: op_illg(opcode);
12551: }return 4;
12552: }
12553: unsigned long REGPARAM2 CPUFUNC(op_4850_0)(uae_u32 opcode) /* PEA */
12554: {
12555: uae_u32 srcreg = (opcode & 7);
12556: OpcodeFamily = 57; CurrentInstrCycles = 12;
12557: {{ uaecptr srca = m68k_areg(regs, srcreg);
12558: { uaecptr dsta = m68k_areg(regs, 7) - 4;
12559: m68k_areg (regs, 7) = dsta;
12560: put_long(dsta,srca);
12561: }}}m68k_incpc(2);
12562: return 12;
12563: }
12564: unsigned long REGPARAM2 CPUFUNC(op_4868_0)(uae_u32 opcode) /* PEA */
12565: {
12566: uae_u32 srcreg = (opcode & 7);
12567: OpcodeFamily = 57; CurrentInstrCycles = 16;
12568: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
12569: { uaecptr dsta = m68k_areg(regs, 7) - 4;
12570: m68k_areg (regs, 7) = dsta;
12571: put_long(dsta,srca);
12572: }}}m68k_incpc(4);
12573: return 16;
12574: }
12575: unsigned long REGPARAM2 CPUFUNC(op_4870_0)(uae_u32 opcode) /* PEA */
12576: {
12577: uae_u32 srcreg = (opcode & 7);
12578: OpcodeFamily = 57; CurrentInstrCycles = 22;
12579: {{m68k_incpc(2);
12580: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
12581: BusCyclePenalty += 2;
12582: { uaecptr dsta = m68k_areg(regs, 7) - 4;
12583: m68k_areg (regs, 7) = dsta;
12584: put_long(dsta,srca);
12585: }}}}return 22;
12586: }
12587: unsigned long REGPARAM2 CPUFUNC(op_4878_0)(uae_u32 opcode) /* PEA */
12588: {
12589: OpcodeFamily = 57; CurrentInstrCycles = 16;
12590: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
12591: { uaecptr dsta = m68k_areg(regs, 7) - 4;
12592: m68k_areg (regs, 7) = dsta;
12593: put_long(dsta,srca);
12594: }}}m68k_incpc(4);
12595: return 16;
12596: }
12597: unsigned long REGPARAM2 CPUFUNC(op_4879_0)(uae_u32 opcode) /* PEA */
12598: {
12599: OpcodeFamily = 57; CurrentInstrCycles = 20;
12600: {{ uaecptr srca = get_ilong(2);
12601: { uaecptr dsta = m68k_areg(regs, 7) - 4;
12602: m68k_areg (regs, 7) = dsta;
12603: put_long(dsta,srca);
12604: }}}m68k_incpc(6);
12605: return 20;
12606: }
12607: unsigned long REGPARAM2 CPUFUNC(op_487a_0)(uae_u32 opcode) /* PEA */
12608: {
12609: OpcodeFamily = 57; CurrentInstrCycles = 16;
12610: {{ uaecptr srca = m68k_getpc () + 2;
12611: srca += (uae_s32)(uae_s16)get_iword(2);
12612: { uaecptr dsta = m68k_areg(regs, 7) - 4;
12613: m68k_areg (regs, 7) = dsta;
12614: put_long(dsta,srca);
12615: }}}m68k_incpc(4);
12616: return 16;
12617: }
12618: unsigned long REGPARAM2 CPUFUNC(op_487b_0)(uae_u32 opcode) /* PEA */
12619: {
12620: OpcodeFamily = 57; CurrentInstrCycles = 22;
12621: {{m68k_incpc(2);
12622: { uaecptr tmppc = m68k_getpc();
12623: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
12624: BusCyclePenalty += 2;
12625: { uaecptr dsta = m68k_areg(regs, 7) - 4;
12626: m68k_areg (regs, 7) = dsta;
12627: put_long(dsta,srca);
12628: }}}}return 22;
12629: }
12630: unsigned long REGPARAM2 CPUFUNC(op_4880_0)(uae_u32 opcode) /* EXT */
12631: {
12632: uae_u32 srcreg = (opcode & 7);
12633: OpcodeFamily = 36; CurrentInstrCycles = 4;
12634: {{ uae_s32 src = m68k_dreg(regs, srcreg);
12635: { uae_u16 dst = (uae_s16)(uae_s8)src;
12636: CLEAR_CZNV;
12637: SET_ZFLG (((uae_s16)(dst)) == 0);
12638: SET_NFLG (((uae_s16)(dst)) < 0);
12639: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
12640: }}}m68k_incpc(2);
12641: return 4;
12642: }
12643: unsigned long REGPARAM2 CPUFUNC(op_4890_0)(uae_u32 opcode) /* MVMLE */
12644: {
12645: uae_u32 dstreg = opcode & 7;
12646: unsigned int retcycles = 0;
12647: OpcodeFamily = 38; CurrentInstrCycles = 8;
12648: { uae_u16 mask = get_iword(2);
12649: retcycles = 0;
12650: { uaecptr srca = m68k_areg(regs, dstreg);
12651: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12652: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
12653: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
12654: }}}m68k_incpc(4);
12655: return (8+retcycles);
12656: }
12657: unsigned long REGPARAM2 CPUFUNC(op_48a0_0)(uae_u32 opcode) /* MVMLE */
12658: {
12659: uae_u32 dstreg = opcode & 7;
12660: unsigned int retcycles = 0;
12661: OpcodeFamily = 38; CurrentInstrCycles = 8;
12662: { uae_u16 mask = get_iword(2);
12663: retcycles = 0;
12664: { uaecptr srca = m68k_areg(regs, dstreg) - 0;
12665: { uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
12666: while (amask) { srca -= 2; put_word(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=4; }
12667: while (dmask) { srca -= 2; put_word(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=4; }
12668: m68k_areg(regs, dstreg) = srca;
12669: }}}m68k_incpc(4);
12670: return (8+retcycles);
12671: }
12672: unsigned long REGPARAM2 CPUFUNC(op_48a8_0)(uae_u32 opcode) /* MVMLE */
12673: {
12674: uae_u32 dstreg = opcode & 7;
12675: unsigned int retcycles = 0;
12676: OpcodeFamily = 38; CurrentInstrCycles = 12;
12677: { uae_u16 mask = get_iword(2);
12678: retcycles = 0;
12679: { uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
12680: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12681: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
12682: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
12683: }}}m68k_incpc(6);
12684: return (12+retcycles);
12685: }
12686: unsigned long REGPARAM2 CPUFUNC(op_48b0_0)(uae_u32 opcode) /* MVMLE */
12687: {
12688: uae_u32 dstreg = opcode & 7;
12689: unsigned int retcycles = 0;
12690: OpcodeFamily = 38; CurrentInstrCycles = 14;
12691: { uae_u16 mask = get_iword(2);
12692: retcycles = 0;
12693: {m68k_incpc(4);
12694: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
12695: BusCyclePenalty += 2;
12696: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12697: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
12698: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
12699: }}}} return (14+retcycles);
12700: }
12701: unsigned long REGPARAM2 CPUFUNC(op_48b8_0)(uae_u32 opcode) /* MVMLE */
12702: {
12703: unsigned int retcycles = 0;
12704: OpcodeFamily = 38; CurrentInstrCycles = 12;
12705: { uae_u16 mask = get_iword(2);
12706: retcycles = 0;
12707: { uaecptr srca = (uae_s32)(uae_s16)get_iword(4);
12708: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12709: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
12710: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
12711: }}}m68k_incpc(6);
12712: return (12+retcycles);
12713: }
12714: unsigned long REGPARAM2 CPUFUNC(op_48b9_0)(uae_u32 opcode) /* MVMLE */
12715: {
12716: unsigned int retcycles = 0;
12717: OpcodeFamily = 38; CurrentInstrCycles = 16;
12718: { uae_u16 mask = get_iword(2);
12719: retcycles = 0;
12720: { uaecptr srca = get_ilong(4);
12721: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12722: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
12723: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
12724: }}}m68k_incpc(8);
12725: return (16+retcycles);
12726: }
12727: unsigned long REGPARAM2 CPUFUNC(op_48c0_0)(uae_u32 opcode) /* EXT */
12728: {
12729: uae_u32 srcreg = (opcode & 7);
12730: OpcodeFamily = 36; CurrentInstrCycles = 4;
12731: {{ uae_s32 src = m68k_dreg(regs, srcreg);
12732: { uae_u32 dst = (uae_s32)(uae_s16)src;
12733: CLEAR_CZNV;
12734: SET_ZFLG (((uae_s32)(dst)) == 0);
12735: SET_NFLG (((uae_s32)(dst)) < 0);
12736: m68k_dreg(regs, srcreg) = (dst);
12737: }}}m68k_incpc(2);
12738: return 4;
12739: }
12740: unsigned long REGPARAM2 CPUFUNC(op_48d0_0)(uae_u32 opcode) /* MVMLE */
12741: {
12742: uae_u32 dstreg = opcode & 7;
12743: unsigned int retcycles = 0;
12744: OpcodeFamily = 38; CurrentInstrCycles = 8;
12745: { uae_u16 mask = get_iword(2);
12746: retcycles = 0;
12747: { uaecptr srca = m68k_areg(regs, dstreg);
12748: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12749: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
12750: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
12751: }}}m68k_incpc(4);
12752: return (8+retcycles);
12753: }
12754: unsigned long REGPARAM2 CPUFUNC(op_48e0_0)(uae_u32 opcode) /* MVMLE */
12755: {
12756: uae_u32 dstreg = opcode & 7;
12757: unsigned int retcycles = 0;
12758: OpcodeFamily = 38; CurrentInstrCycles = 8;
12759: { uae_u16 mask = get_iword(2);
12760: retcycles = 0;
12761: { uaecptr srca = m68k_areg(regs, dstreg) - 0;
12762: { uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
12763: while (amask) { srca -= 4; put_long(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=8; }
12764: while (dmask) { srca -= 4; put_long(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=8; }
12765: m68k_areg(regs, dstreg) = srca;
12766: }}}m68k_incpc(4);
12767: return (8+retcycles);
12768: }
12769: unsigned long REGPARAM2 CPUFUNC(op_48e8_0)(uae_u32 opcode) /* MVMLE */
12770: {
12771: uae_u32 dstreg = opcode & 7;
12772: unsigned int retcycles = 0;
12773: OpcodeFamily = 38; CurrentInstrCycles = 12;
12774: { uae_u16 mask = get_iword(2);
12775: retcycles = 0;
12776: { uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
12777: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12778: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
12779: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
12780: }}}m68k_incpc(6);
12781: return (12+retcycles);
12782: }
12783: unsigned long REGPARAM2 CPUFUNC(op_48f0_0)(uae_u32 opcode) /* MVMLE */
12784: {
12785: uae_u32 dstreg = opcode & 7;
12786: unsigned int retcycles = 0;
12787: OpcodeFamily = 38; CurrentInstrCycles = 14;
12788: { uae_u16 mask = get_iword(2);
12789: retcycles = 0;
12790: {m68k_incpc(4);
12791: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
12792: BusCyclePenalty += 2;
12793: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12794: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
12795: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
12796: }}}} return (14+retcycles);
12797: }
12798: unsigned long REGPARAM2 CPUFUNC(op_48f8_0)(uae_u32 opcode) /* MVMLE */
12799: {
12800: unsigned int retcycles = 0;
12801: OpcodeFamily = 38; CurrentInstrCycles = 12;
12802: { uae_u16 mask = get_iword(2);
12803: retcycles = 0;
12804: { uaecptr srca = (uae_s32)(uae_s16)get_iword(4);
12805: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12806: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
12807: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
12808: }}}m68k_incpc(6);
12809: return (12+retcycles);
12810: }
12811: unsigned long REGPARAM2 CPUFUNC(op_48f9_0)(uae_u32 opcode) /* MVMLE */
12812: {
12813: unsigned int retcycles = 0;
12814: OpcodeFamily = 38; CurrentInstrCycles = 16;
12815: { uae_u16 mask = get_iword(2);
12816: retcycles = 0;
12817: { uaecptr srca = get_ilong(4);
12818: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
12819: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
12820: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
12821: }}}m68k_incpc(8);
12822: return (16+retcycles);
12823: }
12824: unsigned long REGPARAM2 CPUFUNC(op_49c0_0)(uae_u32 opcode) /* EXT */
12825: {
12826: uae_u32 srcreg = (opcode & 7);
12827: OpcodeFamily = 36; CurrentInstrCycles = 4;
12828: {{ uae_s32 src = m68k_dreg(regs, srcreg);
12829: { uae_u32 dst = (uae_s32)(uae_s8)src;
12830: CLEAR_CZNV;
12831: SET_ZFLG (((uae_s32)(dst)) == 0);
12832: SET_NFLG (((uae_s32)(dst)) < 0);
12833: m68k_dreg(regs, srcreg) = (dst);
12834: }}}m68k_incpc(2);
12835: return 4;
12836: }
12837: unsigned long REGPARAM2 CPUFUNC(op_4a00_0)(uae_u32 opcode) /* TST */
12838: {
12839: uae_u32 srcreg = (opcode & 7);
12840: OpcodeFamily = 20; CurrentInstrCycles = 4;
12841: {{ uae_s8 src = m68k_dreg(regs, srcreg);
12842: CLEAR_CZNV;
12843: SET_ZFLG (((uae_s8)(src)) == 0);
12844: SET_NFLG (((uae_s8)(src)) < 0);
12845: }}m68k_incpc(2);
12846: return 4;
12847: }
12848: unsigned long REGPARAM2 CPUFUNC(op_4a10_0)(uae_u32 opcode) /* TST */
12849: {
12850: uae_u32 srcreg = (opcode & 7);
12851: OpcodeFamily = 20; CurrentInstrCycles = 8;
12852: {{ uaecptr srca = m68k_areg(regs, srcreg);
12853: { uae_s8 src = get_byte(srca);
12854: CLEAR_CZNV;
12855: SET_ZFLG (((uae_s8)(src)) == 0);
12856: SET_NFLG (((uae_s8)(src)) < 0);
12857: }}}m68k_incpc(2);
12858: return 8;
12859: }
12860: unsigned long REGPARAM2 CPUFUNC(op_4a18_0)(uae_u32 opcode) /* TST */
12861: {
12862: uae_u32 srcreg = (opcode & 7);
12863: OpcodeFamily = 20; CurrentInstrCycles = 8;
12864: {{ uaecptr srca = m68k_areg(regs, srcreg);
12865: { uae_s8 src = get_byte(srca);
12866: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
12867: CLEAR_CZNV;
12868: SET_ZFLG (((uae_s8)(src)) == 0);
12869: SET_NFLG (((uae_s8)(src)) < 0);
12870: }}}m68k_incpc(2);
12871: return 8;
12872: }
12873: unsigned long REGPARAM2 CPUFUNC(op_4a20_0)(uae_u32 opcode) /* TST */
12874: {
12875: uae_u32 srcreg = (opcode & 7);
12876: OpcodeFamily = 20; CurrentInstrCycles = 10;
12877: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
12878: { uae_s8 src = get_byte(srca);
12879: m68k_areg (regs, srcreg) = srca;
12880: CLEAR_CZNV;
12881: SET_ZFLG (((uae_s8)(src)) == 0);
12882: SET_NFLG (((uae_s8)(src)) < 0);
12883: }}}m68k_incpc(2);
12884: return 10;
12885: }
12886: unsigned long REGPARAM2 CPUFUNC(op_4a28_0)(uae_u32 opcode) /* TST */
12887: {
12888: uae_u32 srcreg = (opcode & 7);
12889: OpcodeFamily = 20; CurrentInstrCycles = 12;
12890: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
12891: { uae_s8 src = get_byte(srca);
12892: CLEAR_CZNV;
12893: SET_ZFLG (((uae_s8)(src)) == 0);
12894: SET_NFLG (((uae_s8)(src)) < 0);
12895: }}}m68k_incpc(4);
12896: return 12;
12897: }
12898: unsigned long REGPARAM2 CPUFUNC(op_4a30_0)(uae_u32 opcode) /* TST */
12899: {
12900: uae_u32 srcreg = (opcode & 7);
12901: OpcodeFamily = 20; CurrentInstrCycles = 14;
12902: {{m68k_incpc(2);
12903: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
12904: BusCyclePenalty += 2;
12905: { uae_s8 src = get_byte(srca);
12906: CLEAR_CZNV;
12907: SET_ZFLG (((uae_s8)(src)) == 0);
12908: SET_NFLG (((uae_s8)(src)) < 0);
12909: }}}}return 14;
12910: }
12911: unsigned long REGPARAM2 CPUFUNC(op_4a38_0)(uae_u32 opcode) /* TST */
12912: {
12913: OpcodeFamily = 20; CurrentInstrCycles = 12;
12914: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
12915: { uae_s8 src = get_byte(srca);
12916: CLEAR_CZNV;
12917: SET_ZFLG (((uae_s8)(src)) == 0);
12918: SET_NFLG (((uae_s8)(src)) < 0);
12919: }}}m68k_incpc(4);
12920: return 12;
12921: }
12922: unsigned long REGPARAM2 CPUFUNC(op_4a39_0)(uae_u32 opcode) /* TST */
12923: {
12924: OpcodeFamily = 20; CurrentInstrCycles = 16;
12925: {{ uaecptr srca = get_ilong(2);
12926: { uae_s8 src = get_byte(srca);
12927: CLEAR_CZNV;
12928: SET_ZFLG (((uae_s8)(src)) == 0);
12929: SET_NFLG (((uae_s8)(src)) < 0);
12930: }}}m68k_incpc(6);
12931: return 16;
12932: }
12933: unsigned long REGPARAM2 CPUFUNC(op_4a3a_0)(uae_u32 opcode) /* TST */
12934: {
12935: OpcodeFamily = 20; CurrentInstrCycles = 12;
12936: {{ uaecptr srca = m68k_getpc () + 2;
12937: srca += (uae_s32)(uae_s16)get_iword(2);
12938: { uae_s8 src = get_byte(srca);
12939: CLEAR_CZNV;
12940: SET_ZFLG (((uae_s8)(src)) == 0);
12941: SET_NFLG (((uae_s8)(src)) < 0);
12942: }}}m68k_incpc(4);
12943: return 12;
12944: }
12945: unsigned long REGPARAM2 CPUFUNC(op_4a3b_0)(uae_u32 opcode) /* TST */
12946: {
12947: OpcodeFamily = 20; CurrentInstrCycles = 14;
12948: {{m68k_incpc(2);
12949: { uaecptr tmppc = m68k_getpc();
12950: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
12951: BusCyclePenalty += 2;
12952: { uae_s8 src = get_byte(srca);
12953: CLEAR_CZNV;
12954: SET_ZFLG (((uae_s8)(src)) == 0);
12955: SET_NFLG (((uae_s8)(src)) < 0);
12956: }}}}return 14;
12957: }
12958: unsigned long REGPARAM2 CPUFUNC(op_4a3c_0)(uae_u32 opcode) /* TST */
12959: {
12960: OpcodeFamily = 20; CurrentInstrCycles = 8;
12961: {{ uae_s8 src = get_ibyte(2);
12962: CLEAR_CZNV;
12963: SET_ZFLG (((uae_s8)(src)) == 0);
12964: SET_NFLG (((uae_s8)(src)) < 0);
12965: }}m68k_incpc(4);
12966: return 8;
12967: }
12968: unsigned long REGPARAM2 CPUFUNC(op_4a40_0)(uae_u32 opcode) /* TST */
12969: {
12970: uae_u32 srcreg = (opcode & 7);
12971: OpcodeFamily = 20; CurrentInstrCycles = 4;
12972: {{ uae_s16 src = m68k_dreg(regs, srcreg);
12973: CLEAR_CZNV;
12974: SET_ZFLG (((uae_s16)(src)) == 0);
12975: SET_NFLG (((uae_s16)(src)) < 0);
12976: }}m68k_incpc(2);
12977: return 4;
12978: }
12979: unsigned long REGPARAM2 CPUFUNC(op_4a48_0)(uae_u32 opcode) /* TST */
12980: {
12981: uae_u32 srcreg = (opcode & 7);
12982: OpcodeFamily = 20; CurrentInstrCycles = 4;
12983: {{ uae_s16 src = m68k_areg(regs, srcreg);
12984: CLEAR_CZNV;
12985: SET_ZFLG (((uae_s16)(src)) == 0);
12986: SET_NFLG (((uae_s16)(src)) < 0);
12987: }}m68k_incpc(2);
12988: return 4;
12989: }
12990: unsigned long REGPARAM2 CPUFUNC(op_4a50_0)(uae_u32 opcode) /* TST */
12991: {
12992: uae_u32 srcreg = (opcode & 7);
12993: OpcodeFamily = 20; CurrentInstrCycles = 8;
12994: {{ uaecptr srca = m68k_areg(regs, srcreg);
12995: { uae_s16 src = get_word(srca);
12996: CLEAR_CZNV;
12997: SET_ZFLG (((uae_s16)(src)) == 0);
12998: SET_NFLG (((uae_s16)(src)) < 0);
12999: }}}m68k_incpc(2);
13000: return 8;
13001: }
13002: unsigned long REGPARAM2 CPUFUNC(op_4a58_0)(uae_u32 opcode) /* TST */
13003: {
13004: uae_u32 srcreg = (opcode & 7);
13005: OpcodeFamily = 20; CurrentInstrCycles = 8;
13006: {{ uaecptr srca = m68k_areg(regs, srcreg);
13007: { uae_s16 src = get_word(srca);
13008: m68k_areg(regs, srcreg) += 2;
13009: CLEAR_CZNV;
13010: SET_ZFLG (((uae_s16)(src)) == 0);
13011: SET_NFLG (((uae_s16)(src)) < 0);
13012: }}}m68k_incpc(2);
13013: return 8;
13014: }
13015: unsigned long REGPARAM2 CPUFUNC(op_4a60_0)(uae_u32 opcode) /* TST */
13016: {
13017: uae_u32 srcreg = (opcode & 7);
13018: OpcodeFamily = 20; CurrentInstrCycles = 10;
13019: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
13020: { uae_s16 src = get_word(srca);
13021: m68k_areg (regs, srcreg) = srca;
13022: CLEAR_CZNV;
13023: SET_ZFLG (((uae_s16)(src)) == 0);
13024: SET_NFLG (((uae_s16)(src)) < 0);
13025: }}}m68k_incpc(2);
13026: return 10;
13027: }
13028: unsigned long REGPARAM2 CPUFUNC(op_4a68_0)(uae_u32 opcode) /* TST */
13029: {
13030: uae_u32 srcreg = (opcode & 7);
13031: OpcodeFamily = 20; CurrentInstrCycles = 12;
13032: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
13033: { uae_s16 src = get_word(srca);
13034: CLEAR_CZNV;
13035: SET_ZFLG (((uae_s16)(src)) == 0);
13036: SET_NFLG (((uae_s16)(src)) < 0);
13037: }}}m68k_incpc(4);
13038: return 12;
13039: }
13040: unsigned long REGPARAM2 CPUFUNC(op_4a70_0)(uae_u32 opcode) /* TST */
13041: {
13042: uae_u32 srcreg = (opcode & 7);
13043: OpcodeFamily = 20; CurrentInstrCycles = 14;
13044: {{m68k_incpc(2);
13045: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
13046: BusCyclePenalty += 2;
13047: { uae_s16 src = get_word(srca);
13048: CLEAR_CZNV;
13049: SET_ZFLG (((uae_s16)(src)) == 0);
13050: SET_NFLG (((uae_s16)(src)) < 0);
13051: }}}}return 14;
13052: }
13053: unsigned long REGPARAM2 CPUFUNC(op_4a78_0)(uae_u32 opcode) /* TST */
13054: {
13055: OpcodeFamily = 20; CurrentInstrCycles = 12;
13056: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
13057: { uae_s16 src = get_word(srca);
13058: CLEAR_CZNV;
13059: SET_ZFLG (((uae_s16)(src)) == 0);
13060: SET_NFLG (((uae_s16)(src)) < 0);
13061: }}}m68k_incpc(4);
13062: return 12;
13063: }
13064: unsigned long REGPARAM2 CPUFUNC(op_4a79_0)(uae_u32 opcode) /* TST */
13065: {
13066: OpcodeFamily = 20; CurrentInstrCycles = 16;
13067: {{ uaecptr srca = get_ilong(2);
13068: { uae_s16 src = get_word(srca);
13069: CLEAR_CZNV;
13070: SET_ZFLG (((uae_s16)(src)) == 0);
13071: SET_NFLG (((uae_s16)(src)) < 0);
13072: }}}m68k_incpc(6);
13073: return 16;
13074: }
13075: unsigned long REGPARAM2 CPUFUNC(op_4a7a_0)(uae_u32 opcode) /* TST */
13076: {
13077: OpcodeFamily = 20; CurrentInstrCycles = 12;
13078: {{ uaecptr srca = m68k_getpc () + 2;
13079: srca += (uae_s32)(uae_s16)get_iword(2);
13080: { uae_s16 src = get_word(srca);
13081: CLEAR_CZNV;
13082: SET_ZFLG (((uae_s16)(src)) == 0);
13083: SET_NFLG (((uae_s16)(src)) < 0);
13084: }}}m68k_incpc(4);
13085: return 12;
13086: }
13087: unsigned long REGPARAM2 CPUFUNC(op_4a7b_0)(uae_u32 opcode) /* TST */
13088: {
13089: OpcodeFamily = 20; CurrentInstrCycles = 14;
13090: {{m68k_incpc(2);
13091: { uaecptr tmppc = m68k_getpc();
13092: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
13093: BusCyclePenalty += 2;
13094: { uae_s16 src = get_word(srca);
13095: CLEAR_CZNV;
13096: SET_ZFLG (((uae_s16)(src)) == 0);
13097: SET_NFLG (((uae_s16)(src)) < 0);
13098: }}}}return 14;
13099: }
13100: unsigned long REGPARAM2 CPUFUNC(op_4a7c_0)(uae_u32 opcode) /* TST */
13101: {
13102: OpcodeFamily = 20; CurrentInstrCycles = 8;
13103: {{ uae_s16 src = get_iword(2);
13104: CLEAR_CZNV;
13105: SET_ZFLG (((uae_s16)(src)) == 0);
13106: SET_NFLG (((uae_s16)(src)) < 0);
13107: }}m68k_incpc(4);
13108: return 8;
13109: }
13110: unsigned long REGPARAM2 CPUFUNC(op_4a80_0)(uae_u32 opcode) /* TST */
13111: {
13112: uae_u32 srcreg = (opcode & 7);
13113: OpcodeFamily = 20; CurrentInstrCycles = 4;
13114: {{ uae_s32 src = m68k_dreg(regs, srcreg);
13115: CLEAR_CZNV;
13116: SET_ZFLG (((uae_s32)(src)) == 0);
13117: SET_NFLG (((uae_s32)(src)) < 0);
13118: }}m68k_incpc(2);
13119: return 4;
13120: }
13121: unsigned long REGPARAM2 CPUFUNC(op_4a88_0)(uae_u32 opcode) /* TST */
13122: {
13123: uae_u32 srcreg = (opcode & 7);
13124: OpcodeFamily = 20; CurrentInstrCycles = 4;
13125: {{ uae_s32 src = m68k_areg(regs, srcreg);
13126: CLEAR_CZNV;
13127: SET_ZFLG (((uae_s32)(src)) == 0);
13128: SET_NFLG (((uae_s32)(src)) < 0);
13129: }}m68k_incpc(2);
13130: return 4;
13131: }
13132: unsigned long REGPARAM2 CPUFUNC(op_4a90_0)(uae_u32 opcode) /* TST */
13133: {
13134: uae_u32 srcreg = (opcode & 7);
13135: OpcodeFamily = 20; CurrentInstrCycles = 12;
13136: {{ uaecptr srca = m68k_areg(regs, srcreg);
13137: { uae_s32 src = get_long(srca);
13138: CLEAR_CZNV;
13139: SET_ZFLG (((uae_s32)(src)) == 0);
13140: SET_NFLG (((uae_s32)(src)) < 0);
13141: }}}m68k_incpc(2);
13142: return 12;
13143: }
13144: unsigned long REGPARAM2 CPUFUNC(op_4a98_0)(uae_u32 opcode) /* TST */
13145: {
13146: uae_u32 srcreg = (opcode & 7);
13147: OpcodeFamily = 20; CurrentInstrCycles = 12;
13148: {{ uaecptr srca = m68k_areg(regs, srcreg);
13149: { uae_s32 src = get_long(srca);
13150: m68k_areg(regs, srcreg) += 4;
13151: CLEAR_CZNV;
13152: SET_ZFLG (((uae_s32)(src)) == 0);
13153: SET_NFLG (((uae_s32)(src)) < 0);
13154: }}}m68k_incpc(2);
13155: return 12;
13156: }
13157: unsigned long REGPARAM2 CPUFUNC(op_4aa0_0)(uae_u32 opcode) /* TST */
13158: {
13159: uae_u32 srcreg = (opcode & 7);
13160: OpcodeFamily = 20; CurrentInstrCycles = 14;
13161: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
13162: { uae_s32 src = get_long(srca);
13163: m68k_areg (regs, srcreg) = srca;
13164: CLEAR_CZNV;
13165: SET_ZFLG (((uae_s32)(src)) == 0);
13166: SET_NFLG (((uae_s32)(src)) < 0);
13167: }}}m68k_incpc(2);
13168: return 14;
13169: }
13170: unsigned long REGPARAM2 CPUFUNC(op_4aa8_0)(uae_u32 opcode) /* TST */
13171: {
13172: uae_u32 srcreg = (opcode & 7);
13173: OpcodeFamily = 20; CurrentInstrCycles = 16;
13174: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
13175: { uae_s32 src = get_long(srca);
13176: CLEAR_CZNV;
13177: SET_ZFLG (((uae_s32)(src)) == 0);
13178: SET_NFLG (((uae_s32)(src)) < 0);
13179: }}}m68k_incpc(4);
13180: return 16;
13181: }
13182: unsigned long REGPARAM2 CPUFUNC(op_4ab0_0)(uae_u32 opcode) /* TST */
13183: {
13184: uae_u32 srcreg = (opcode & 7);
13185: OpcodeFamily = 20; CurrentInstrCycles = 18;
13186: {{m68k_incpc(2);
13187: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
13188: BusCyclePenalty += 2;
13189: { uae_s32 src = get_long(srca);
13190: CLEAR_CZNV;
13191: SET_ZFLG (((uae_s32)(src)) == 0);
13192: SET_NFLG (((uae_s32)(src)) < 0);
13193: }}}}return 18;
13194: }
13195: unsigned long REGPARAM2 CPUFUNC(op_4ab8_0)(uae_u32 opcode) /* TST */
13196: {
13197: OpcodeFamily = 20; CurrentInstrCycles = 16;
13198: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
13199: { uae_s32 src = get_long(srca);
13200: CLEAR_CZNV;
13201: SET_ZFLG (((uae_s32)(src)) == 0);
13202: SET_NFLG (((uae_s32)(src)) < 0);
13203: }}}m68k_incpc(4);
13204: return 16;
13205: }
13206: unsigned long REGPARAM2 CPUFUNC(op_4ab9_0)(uae_u32 opcode) /* TST */
13207: {
13208: OpcodeFamily = 20; CurrentInstrCycles = 20;
13209: {{ uaecptr srca = get_ilong(2);
13210: { uae_s32 src = get_long(srca);
13211: CLEAR_CZNV;
13212: SET_ZFLG (((uae_s32)(src)) == 0);
13213: SET_NFLG (((uae_s32)(src)) < 0);
13214: }}}m68k_incpc(6);
13215: return 20;
13216: }
13217: unsigned long REGPARAM2 CPUFUNC(op_4aba_0)(uae_u32 opcode) /* TST */
13218: {
13219: OpcodeFamily = 20; CurrentInstrCycles = 16;
13220: {{ uaecptr srca = m68k_getpc () + 2;
13221: srca += (uae_s32)(uae_s16)get_iword(2);
13222: { uae_s32 src = get_long(srca);
13223: CLEAR_CZNV;
13224: SET_ZFLG (((uae_s32)(src)) == 0);
13225: SET_NFLG (((uae_s32)(src)) < 0);
13226: }}}m68k_incpc(4);
13227: return 16;
13228: }
13229: unsigned long REGPARAM2 CPUFUNC(op_4abb_0)(uae_u32 opcode) /* TST */
13230: {
13231: OpcodeFamily = 20; CurrentInstrCycles = 18;
13232: {{m68k_incpc(2);
13233: { uaecptr tmppc = m68k_getpc();
13234: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
13235: BusCyclePenalty += 2;
13236: { uae_s32 src = get_long(srca);
13237: CLEAR_CZNV;
13238: SET_ZFLG (((uae_s32)(src)) == 0);
13239: SET_NFLG (((uae_s32)(src)) < 0);
13240: }}}}return 18;
13241: }
13242: unsigned long REGPARAM2 CPUFUNC(op_4abc_0)(uae_u32 opcode) /* TST */
13243: {
13244: OpcodeFamily = 20; CurrentInstrCycles = 12;
13245: {{ uae_s32 src = get_ilong(2);
13246: CLEAR_CZNV;
13247: SET_ZFLG (((uae_s32)(src)) == 0);
13248: SET_NFLG (((uae_s32)(src)) < 0);
13249: }}m68k_incpc(6);
13250: return 12;
13251: }
13252: unsigned long REGPARAM2 CPUFUNC(op_4ac0_0)(uae_u32 opcode) /* TAS */
13253: {
13254: uae_u32 srcreg = (opcode & 7);
13255: OpcodeFamily = 98; CurrentInstrCycles = 4;
13256: {{ uae_s8 src = m68k_dreg(regs, srcreg);
13257: CLEAR_CZNV;
13258: SET_ZFLG (((uae_s8)(src)) == 0);
13259: SET_NFLG (((uae_s8)(src)) < 0);
13260: src |= 0x80;
13261: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
13262: }}m68k_incpc(2);
13263: return 4;
13264: }
13265: unsigned long REGPARAM2 CPUFUNC(op_4ad0_0)(uae_u32 opcode) /* TAS */
13266: {
13267: uae_u32 srcreg = (opcode & 7);
13268: OpcodeFamily = 98; CurrentInstrCycles = 14;
13269: {{ uaecptr srca = m68k_areg(regs, srcreg);
13270: { uae_s8 src = get_byte(srca);
13271: CLEAR_CZNV;
13272: SET_ZFLG (((uae_s8)(src)) == 0);
13273: SET_NFLG (((uae_s8)(src)) < 0);
13274: src |= 0x80;
13275: put_byte(srca,src);
13276: }}}m68k_incpc(2);
13277: return 14;
13278: }
13279: unsigned long REGPARAM2 CPUFUNC(op_4ad8_0)(uae_u32 opcode) /* TAS */
13280: {
13281: uae_u32 srcreg = (opcode & 7);
13282: OpcodeFamily = 98; CurrentInstrCycles = 14;
13283: {{ uaecptr srca = m68k_areg(regs, srcreg);
13284: { uae_s8 src = get_byte(srca);
13285: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
13286: CLEAR_CZNV;
13287: SET_ZFLG (((uae_s8)(src)) == 0);
13288: SET_NFLG (((uae_s8)(src)) < 0);
13289: src |= 0x80;
13290: put_byte(srca,src);
13291: }}}m68k_incpc(2);
13292: return 14;
13293: }
13294: unsigned long REGPARAM2 CPUFUNC(op_4ae0_0)(uae_u32 opcode) /* TAS */
13295: {
13296: uae_u32 srcreg = (opcode & 7);
13297: OpcodeFamily = 98; CurrentInstrCycles = 16;
13298: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
13299: { uae_s8 src = get_byte(srca);
13300: m68k_areg (regs, srcreg) = srca;
13301: CLEAR_CZNV;
13302: SET_ZFLG (((uae_s8)(src)) == 0);
13303: SET_NFLG (((uae_s8)(src)) < 0);
13304: src |= 0x80;
13305: put_byte(srca,src);
13306: }}}m68k_incpc(2);
13307: return 16;
13308: }
13309: unsigned long REGPARAM2 CPUFUNC(op_4ae8_0)(uae_u32 opcode) /* TAS */
13310: {
13311: uae_u32 srcreg = (opcode & 7);
13312: OpcodeFamily = 98; CurrentInstrCycles = 18;
13313: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
13314: { uae_s8 src = get_byte(srca);
13315: CLEAR_CZNV;
13316: SET_ZFLG (((uae_s8)(src)) == 0);
13317: SET_NFLG (((uae_s8)(src)) < 0);
13318: src |= 0x80;
13319: put_byte(srca,src);
13320: }}}m68k_incpc(4);
13321: return 18;
13322: }
13323: unsigned long REGPARAM2 CPUFUNC(op_4af0_0)(uae_u32 opcode) /* TAS */
13324: {
13325: uae_u32 srcreg = (opcode & 7);
13326: OpcodeFamily = 98; CurrentInstrCycles = 20;
13327: {{m68k_incpc(2);
13328: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
13329: BusCyclePenalty += 2;
13330: { uae_s8 src = get_byte(srca);
13331: CLEAR_CZNV;
13332: SET_ZFLG (((uae_s8)(src)) == 0);
13333: SET_NFLG (((uae_s8)(src)) < 0);
13334: src |= 0x80;
13335: put_byte(srca,src);
13336: }}}}return 20;
13337: }
13338: unsigned long REGPARAM2 CPUFUNC(op_4af8_0)(uae_u32 opcode) /* TAS */
13339: {
13340: OpcodeFamily = 98; CurrentInstrCycles = 18;
13341: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
13342: { uae_s8 src = get_byte(srca);
13343: CLEAR_CZNV;
13344: SET_ZFLG (((uae_s8)(src)) == 0);
13345: SET_NFLG (((uae_s8)(src)) < 0);
13346: src |= 0x80;
13347: put_byte(srca,src);
13348: }}}m68k_incpc(4);
13349: return 18;
13350: }
13351: unsigned long REGPARAM2 CPUFUNC(op_4af9_0)(uae_u32 opcode) /* TAS */
13352: {
13353: OpcodeFamily = 98; CurrentInstrCycles = 22;
13354: {{ uaecptr srca = get_ilong(2);
13355: { uae_s8 src = get_byte(srca);
13356: CLEAR_CZNV;
13357: SET_ZFLG (((uae_s8)(src)) == 0);
13358: SET_NFLG (((uae_s8)(src)) < 0);
13359: src |= 0x80;
13360: put_byte(srca,src);
13361: }}}m68k_incpc(6);
13362: return 22;
13363: }
13364: unsigned long REGPARAM2 CPUFUNC(op_4c00_0)(uae_u32 opcode) /* MULL */
13365: {
13366: uae_u32 dstreg = opcode & 7;
13367: OpcodeFamily = 87; CurrentInstrCycles = 8;
13368: {{ uae_s16 extra = get_iword(2);
13369: { uae_s32 dst = m68k_dreg(regs, dstreg);
13370: m68k_incpc(4);
13371: m68k_mull(opcode, dst, extra);
13372: }}}return 8;
13373: }
13374: unsigned long REGPARAM2 CPUFUNC(op_4c10_0)(uae_u32 opcode) /* MULL */
13375: {
13376: uae_u32 dstreg = opcode & 7;
13377: OpcodeFamily = 87; CurrentInstrCycles = 16;
13378: {{ uae_s16 extra = get_iword(2);
13379: { uaecptr dsta = m68k_areg(regs, dstreg);
13380: { uae_s32 dst = get_long(dsta);
13381: m68k_incpc(4);
13382: m68k_mull(opcode, dst, extra);
13383: }}}}return 16;
13384: }
13385: unsigned long REGPARAM2 CPUFUNC(op_4c18_0)(uae_u32 opcode) /* MULL */
13386: {
13387: uae_u32 dstreg = opcode & 7;
13388: OpcodeFamily = 87; CurrentInstrCycles = 16;
13389: {{ uae_s16 extra = get_iword(2);
13390: { uaecptr dsta = m68k_areg(regs, dstreg);
13391: { uae_s32 dst = get_long(dsta);
13392: m68k_areg(regs, dstreg) += 4;
13393: m68k_incpc(4);
13394: m68k_mull(opcode, dst, extra);
13395: }}}}return 16;
13396: }
13397: unsigned long REGPARAM2 CPUFUNC(op_4c20_0)(uae_u32 opcode) /* MULL */
13398: {
13399: uae_u32 dstreg = opcode & 7;
13400: OpcodeFamily = 87; CurrentInstrCycles = 18;
13401: {{ uae_s16 extra = get_iword(2);
13402: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
13403: { uae_s32 dst = get_long(dsta);
13404: m68k_areg (regs, dstreg) = dsta;
13405: m68k_incpc(4);
13406: m68k_mull(opcode, dst, extra);
13407: }}}}return 18;
13408: }
13409: unsigned long REGPARAM2 CPUFUNC(op_4c28_0)(uae_u32 opcode) /* MULL */
13410: {
13411: uae_u32 dstreg = opcode & 7;
13412: OpcodeFamily = 87; CurrentInstrCycles = 20;
13413: {{ uae_s16 extra = get_iword(2);
13414: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
13415: { uae_s32 dst = get_long(dsta);
13416: m68k_incpc(6);
13417: m68k_mull(opcode, dst, extra);
13418: }}}}return 20;
13419: }
13420: unsigned long REGPARAM2 CPUFUNC(op_4c30_0)(uae_u32 opcode) /* MULL */
13421: {
13422: uae_u32 dstreg = opcode & 7;
13423: OpcodeFamily = 87; CurrentInstrCycles = 22;
13424: {{ uae_s16 extra = get_iword(2);
13425: {m68k_incpc(4);
13426: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
13427: BusCyclePenalty += 2;
13428: { uae_s32 dst = get_long(dsta);
13429: m68k_mull(opcode, dst, extra);
13430: }}}}}return 22;
13431: }
13432: unsigned long REGPARAM2 CPUFUNC(op_4c38_0)(uae_u32 opcode) /* MULL */
13433: {
13434: OpcodeFamily = 87; CurrentInstrCycles = 20;
13435: {{ uae_s16 extra = get_iword(2);
13436: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
13437: { uae_s32 dst = get_long(dsta);
13438: m68k_incpc(6);
13439: m68k_mull(opcode, dst, extra);
13440: }}}}return 20;
13441: }
13442: unsigned long REGPARAM2 CPUFUNC(op_4c39_0)(uae_u32 opcode) /* MULL */
13443: {
13444: OpcodeFamily = 87; CurrentInstrCycles = 24;
13445: {{ uae_s16 extra = get_iword(2);
13446: { uaecptr dsta = get_ilong(4);
13447: { uae_s32 dst = get_long(dsta);
13448: m68k_incpc(8);
13449: m68k_mull(opcode, dst, extra);
13450: }}}}return 24;
13451: }
13452: unsigned long REGPARAM2 CPUFUNC(op_4c3a_0)(uae_u32 opcode) /* MULL */
13453: {
13454: uae_u32 dstreg = 2;
13455: OpcodeFamily = 87; CurrentInstrCycles = 20;
13456: {{ uae_s16 extra = get_iword(2);
13457: { uaecptr dsta = m68k_getpc () + 4;
13458: dsta += (uae_s32)(uae_s16)get_iword(4);
13459: { uae_s32 dst = get_long(dsta);
13460: m68k_incpc(6);
13461: m68k_mull(opcode, dst, extra);
13462: }}}}return 20;
13463: }
13464: unsigned long REGPARAM2 CPUFUNC(op_4c3b_0)(uae_u32 opcode) /* MULL */
13465: {
13466: uae_u32 dstreg = 3;
13467: OpcodeFamily = 87; CurrentInstrCycles = 22;
13468: {{ uae_s16 extra = get_iword(2);
13469: {m68k_incpc(4);
13470: { uaecptr tmppc = m68k_getpc();
13471: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
13472: BusCyclePenalty += 2;
13473: { uae_s32 dst = get_long(dsta);
13474: m68k_mull(opcode, dst, extra);
13475: }}}}}return 22;
13476: }
13477: unsigned long REGPARAM2 CPUFUNC(op_4c3c_0)(uae_u32 opcode) /* MULL */
13478: {
13479: OpcodeFamily = 87; CurrentInstrCycles = 16;
13480: {{ uae_s16 extra = get_iword(2);
13481: { uae_s32 dst = get_ilong(4);
13482: m68k_incpc(8);
13483: m68k_mull(opcode, dst, extra);
13484: }}}return 16;
13485: }
13486: unsigned long REGPARAM2 CPUFUNC(op_4c40_0)(uae_u32 opcode) /* DIVL */
13487: {
13488: uae_u32 dstreg = opcode & 7;
13489: OpcodeFamily = 86; CurrentInstrCycles = 8;
13490: {m68k_incpc(2);
13491: { uaecptr oldpc = m68k_getpc();
13492: { uae_s16 extra = get_iword(0);
13493: { uae_s32 dst = m68k_dreg(regs, dstreg);
13494: m68k_incpc(2);
13495: m68k_divl(opcode, dst, extra, oldpc);
13496: }}}}return 8;
13497: }
13498: unsigned long REGPARAM2 CPUFUNC(op_4c50_0)(uae_u32 opcode) /* DIVL */
13499: {
13500: uae_u32 dstreg = opcode & 7;
13501: OpcodeFamily = 86; CurrentInstrCycles = 16;
13502: {m68k_incpc(2);
13503: { uaecptr oldpc = m68k_getpc();
13504: { uae_s16 extra = get_iword(0);
13505: { uaecptr dsta = m68k_areg(regs, dstreg);
13506: { uae_s32 dst = get_long(dsta);
13507: m68k_incpc(2);
13508: m68k_divl(opcode, dst, extra, oldpc);
13509: }}}}}return 16;
13510: }
13511: unsigned long REGPARAM2 CPUFUNC(op_4c58_0)(uae_u32 opcode) /* DIVL */
13512: {
13513: uae_u32 dstreg = opcode & 7;
13514: OpcodeFamily = 86; CurrentInstrCycles = 16;
13515: {m68k_incpc(2);
13516: { uaecptr oldpc = m68k_getpc();
13517: { uae_s16 extra = get_iword(0);
13518: { uaecptr dsta = m68k_areg(regs, dstreg);
13519: { uae_s32 dst = get_long(dsta);
13520: m68k_areg(regs, dstreg) += 4;
13521: m68k_incpc(2);
13522: m68k_divl(opcode, dst, extra, oldpc);
13523: }}}}}return 16;
13524: }
13525: unsigned long REGPARAM2 CPUFUNC(op_4c60_0)(uae_u32 opcode) /* DIVL */
13526: {
13527: uae_u32 dstreg = opcode & 7;
13528: OpcodeFamily = 86; CurrentInstrCycles = 18;
13529: {m68k_incpc(2);
13530: { uaecptr oldpc = m68k_getpc();
13531: { uae_s16 extra = get_iword(0);
13532: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
13533: { uae_s32 dst = get_long(dsta);
13534: m68k_areg (regs, dstreg) = dsta;
13535: m68k_incpc(2);
13536: m68k_divl(opcode, dst, extra, oldpc);
13537: }}}}}return 18;
13538: }
13539: unsigned long REGPARAM2 CPUFUNC(op_4c68_0)(uae_u32 opcode) /* DIVL */
13540: {
13541: uae_u32 dstreg = opcode & 7;
13542: OpcodeFamily = 86; CurrentInstrCycles = 20;
13543: {m68k_incpc(2);
13544: { uaecptr oldpc = m68k_getpc();
13545: { uae_s16 extra = get_iword(0);
13546: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
13547: { uae_s32 dst = get_long(dsta);
13548: m68k_incpc(4);
13549: m68k_divl(opcode, dst, extra, oldpc);
13550: }}}}}return 20;
13551: }
13552: unsigned long REGPARAM2 CPUFUNC(op_4c70_0)(uae_u32 opcode) /* DIVL */
13553: {
13554: uae_u32 dstreg = opcode & 7;
13555: OpcodeFamily = 86; CurrentInstrCycles = 22;
13556: {m68k_incpc(2);
13557: { uaecptr oldpc = m68k_getpc();
13558: { uae_s16 extra = get_iword(0);
13559: {m68k_incpc(2);
13560: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
13561: BusCyclePenalty += 2;
13562: { uae_s32 dst = get_long(dsta);
13563: m68k_divl(opcode, dst, extra, oldpc);
13564: }}}}}}return 22;
13565: }
13566: unsigned long REGPARAM2 CPUFUNC(op_4c78_0)(uae_u32 opcode) /* DIVL */
13567: {
13568: OpcodeFamily = 86; CurrentInstrCycles = 20;
13569: {m68k_incpc(2);
13570: { uaecptr oldpc = m68k_getpc();
13571: { uae_s16 extra = get_iword(0);
13572: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
13573: { uae_s32 dst = get_long(dsta);
13574: m68k_incpc(4);
13575: m68k_divl(opcode, dst, extra, oldpc);
13576: }}}}}return 20;
13577: }
13578: unsigned long REGPARAM2 CPUFUNC(op_4c79_0)(uae_u32 opcode) /* DIVL */
13579: {
13580: OpcodeFamily = 86; CurrentInstrCycles = 24;
13581: {m68k_incpc(2);
13582: { uaecptr oldpc = m68k_getpc();
13583: { uae_s16 extra = get_iword(0);
13584: { uaecptr dsta = get_ilong(2);
13585: { uae_s32 dst = get_long(dsta);
13586: m68k_incpc(6);
13587: m68k_divl(opcode, dst, extra, oldpc);
13588: }}}}}return 24;
13589: }
13590: unsigned long REGPARAM2 CPUFUNC(op_4c7a_0)(uae_u32 opcode) /* DIVL */
13591: {
13592: uae_u32 dstreg = 2;
13593: OpcodeFamily = 86; CurrentInstrCycles = 20;
13594: {m68k_incpc(2);
13595: { uaecptr oldpc = m68k_getpc();
13596: { uae_s16 extra = get_iword(0);
13597: { uaecptr dsta = m68k_getpc () + 2;
13598: dsta += (uae_s32)(uae_s16)get_iword(2);
13599: { uae_s32 dst = get_long(dsta);
13600: m68k_incpc(4);
13601: m68k_divl(opcode, dst, extra, oldpc);
13602: }}}}}return 20;
13603: }
13604: unsigned long REGPARAM2 CPUFUNC(op_4c7b_0)(uae_u32 opcode) /* DIVL */
13605: {
13606: uae_u32 dstreg = 3;
13607: OpcodeFamily = 86; CurrentInstrCycles = 22;
13608: {m68k_incpc(2);
13609: { uaecptr oldpc = m68k_getpc();
13610: { uae_s16 extra = get_iword(0);
13611: {m68k_incpc(2);
13612: { uaecptr tmppc = m68k_getpc();
13613: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
13614: BusCyclePenalty += 2;
13615: { uae_s32 dst = get_long(dsta);
13616: m68k_divl(opcode, dst, extra, oldpc);
13617: }}}}}}return 22;
13618: }
13619: unsigned long REGPARAM2 CPUFUNC(op_4c7c_0)(uae_u32 opcode) /* DIVL */
13620: {
13621: OpcodeFamily = 86; CurrentInstrCycles = 16;
13622: {m68k_incpc(2);
13623: { uaecptr oldpc = m68k_getpc();
13624: { uae_s16 extra = get_iword(0);
13625: { uae_s32 dst = get_ilong(2);
13626: m68k_incpc(6);
13627: m68k_divl(opcode, dst, extra, oldpc);
13628: }}}}return 16;
13629: }
13630: unsigned long REGPARAM2 CPUFUNC(op_4c90_0)(uae_u32 opcode) /* MVMEL */
13631: {
13632: uae_u32 dstreg = opcode & 7;
13633: unsigned int retcycles = 0;
13634: OpcodeFamily = 37; CurrentInstrCycles = 12;
13635: { uae_u16 mask = get_iword(2);
13636: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13637: retcycles = 0;
13638: { uaecptr srca = m68k_areg(regs, dstreg);
13639: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
13640: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
13641: }}}m68k_incpc(4);
13642: return (12+retcycles);
13643: }
13644: unsigned long REGPARAM2 CPUFUNC(op_4c98_0)(uae_u32 opcode) /* MVMEL */
13645: {
13646: uae_u32 dstreg = opcode & 7;
13647: unsigned int retcycles = 0;
13648: OpcodeFamily = 37; CurrentInstrCycles = 12;
13649: { uae_u16 mask = get_iword(2);
13650: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13651: retcycles = 0;
13652: { uaecptr srca = m68k_areg(regs, dstreg);
13653: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
13654: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
13655: m68k_areg(regs, dstreg) = srca;
13656: }}}m68k_incpc(4);
13657: return (12+retcycles);
13658: }
13659: unsigned long REGPARAM2 CPUFUNC(op_4ca8_0)(uae_u32 opcode) /* MVMEL */
13660: {
13661: uae_u32 dstreg = opcode & 7;
13662: unsigned int retcycles = 0;
13663: OpcodeFamily = 37; CurrentInstrCycles = 16;
13664: { uae_u16 mask = get_iword(2);
13665: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13666: retcycles = 0;
13667: { uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
13668: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
13669: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
13670: }}}m68k_incpc(6);
13671: return (16+retcycles);
13672: }
13673: unsigned long REGPARAM2 CPUFUNC(op_4cb0_0)(uae_u32 opcode) /* MVMEL */
13674: {
13675: uae_u32 dstreg = opcode & 7;
13676: unsigned int retcycles = 0;
13677: OpcodeFamily = 37; CurrentInstrCycles = 18;
13678: { uae_u16 mask = get_iword(2);
13679: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13680: retcycles = 0;
13681: {m68k_incpc(4);
13682: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
13683: BusCyclePenalty += 2;
13684: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
13685: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
13686: }}}} return (18+retcycles);
13687: }
13688: unsigned long REGPARAM2 CPUFUNC(op_4cb8_0)(uae_u32 opcode) /* MVMEL */
13689: {
13690: unsigned int retcycles = 0;
13691: OpcodeFamily = 37; CurrentInstrCycles = 16;
13692: { uae_u16 mask = get_iword(2);
13693: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13694: retcycles = 0;
13695: { uaecptr srca = (uae_s32)(uae_s16)get_iword(4);
13696: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
13697: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
13698: }}}m68k_incpc(6);
13699: return (16+retcycles);
13700: }
13701: unsigned long REGPARAM2 CPUFUNC(op_4cb9_0)(uae_u32 opcode) /* MVMEL */
13702: {
13703: unsigned int retcycles = 0;
13704: OpcodeFamily = 37; CurrentInstrCycles = 20;
13705: { uae_u16 mask = get_iword(2);
13706: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13707: retcycles = 0;
13708: { uaecptr srca = get_ilong(4);
13709: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
13710: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
13711: }}}m68k_incpc(8);
13712: return (20+retcycles);
13713: }
13714: unsigned long REGPARAM2 CPUFUNC(op_4cba_0)(uae_u32 opcode) /* MVMEL */
13715: {
13716: uae_u32 dstreg = 2;
13717: unsigned int retcycles = 0;
13718: OpcodeFamily = 37; CurrentInstrCycles = 16;
13719: { uae_u16 mask = get_iword(2);
13720: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13721: retcycles = 0;
13722: { uaecptr srca = m68k_getpc () + 4;
13723: srca += (uae_s32)(uae_s16)get_iword(4);
13724: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
13725: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
13726: }}}m68k_incpc(6);
13727: return (16+retcycles);
13728: }
13729: unsigned long REGPARAM2 CPUFUNC(op_4cbb_0)(uae_u32 opcode) /* MVMEL */
13730: {
13731: uae_u32 dstreg = 3;
13732: unsigned int retcycles = 0;
13733: OpcodeFamily = 37; CurrentInstrCycles = 18;
13734: { uae_u16 mask = get_iword(2);
13735: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13736: retcycles = 0;
13737: {m68k_incpc(4);
13738: { uaecptr tmppc = m68k_getpc();
13739: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
13740: BusCyclePenalty += 2;
13741: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
13742: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
13743: }}}} return (18+retcycles);
13744: }
13745: unsigned long REGPARAM2 CPUFUNC(op_4cd0_0)(uae_u32 opcode) /* MVMEL */
13746: {
13747: uae_u32 dstreg = opcode & 7;
13748: unsigned int retcycles = 0;
13749: OpcodeFamily = 37; CurrentInstrCycles = 12;
13750: { uae_u16 mask = get_iword(2);
13751: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13752: retcycles = 0;
13753: { uaecptr srca = m68k_areg(regs, dstreg);
13754: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
13755: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
13756: }}}m68k_incpc(4);
13757: return (12+retcycles);
13758: }
13759: unsigned long REGPARAM2 CPUFUNC(op_4cd8_0)(uae_u32 opcode) /* MVMEL */
13760: {
13761: uae_u32 dstreg = opcode & 7;
13762: unsigned int retcycles = 0;
13763: OpcodeFamily = 37; CurrentInstrCycles = 12;
13764: { uae_u16 mask = get_iword(2);
13765: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13766: retcycles = 0;
13767: { uaecptr srca = m68k_areg(regs, dstreg);
13768: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
13769: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
13770: m68k_areg(regs, dstreg) = srca;
13771: }}}m68k_incpc(4);
13772: return (12+retcycles);
13773: }
13774: unsigned long REGPARAM2 CPUFUNC(op_4ce8_0)(uae_u32 opcode) /* MVMEL */
13775: {
13776: uae_u32 dstreg = opcode & 7;
13777: unsigned int retcycles = 0;
13778: OpcodeFamily = 37; CurrentInstrCycles = 16;
13779: { uae_u16 mask = get_iword(2);
13780: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13781: retcycles = 0;
13782: { uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
13783: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
13784: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
13785: }}}m68k_incpc(6);
13786: return (16+retcycles);
13787: }
13788: unsigned long REGPARAM2 CPUFUNC(op_4cf0_0)(uae_u32 opcode) /* MVMEL */
13789: {
13790: uae_u32 dstreg = opcode & 7;
13791: unsigned int retcycles = 0;
13792: OpcodeFamily = 37; CurrentInstrCycles = 18;
13793: { uae_u16 mask = get_iword(2);
13794: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13795: retcycles = 0;
13796: {m68k_incpc(4);
13797: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
13798: BusCyclePenalty += 2;
13799: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
13800: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
13801: }}}} return (18+retcycles);
13802: }
13803: unsigned long REGPARAM2 CPUFUNC(op_4cf8_0)(uae_u32 opcode) /* MVMEL */
13804: {
13805: unsigned int retcycles = 0;
13806: OpcodeFamily = 37; CurrentInstrCycles = 16;
13807: { uae_u16 mask = get_iword(2);
13808: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13809: retcycles = 0;
13810: { uaecptr srca = (uae_s32)(uae_s16)get_iword(4);
13811: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
13812: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
13813: }}}m68k_incpc(6);
13814: return (16+retcycles);
13815: }
13816: unsigned long REGPARAM2 CPUFUNC(op_4cf9_0)(uae_u32 opcode) /* MVMEL */
13817: {
13818: unsigned int retcycles = 0;
13819: OpcodeFamily = 37; CurrentInstrCycles = 20;
13820: { uae_u16 mask = get_iword(2);
13821: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13822: retcycles = 0;
13823: { uaecptr srca = get_ilong(4);
13824: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
13825: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
13826: }}}m68k_incpc(8);
13827: return (20+retcycles);
13828: }
13829: unsigned long REGPARAM2 CPUFUNC(op_4cfa_0)(uae_u32 opcode) /* MVMEL */
13830: {
13831: uae_u32 dstreg = 2;
13832: unsigned int retcycles = 0;
13833: OpcodeFamily = 37; CurrentInstrCycles = 16;
13834: { uae_u16 mask = get_iword(2);
13835: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13836: retcycles = 0;
13837: { uaecptr srca = m68k_getpc () + 4;
13838: srca += (uae_s32)(uae_s16)get_iword(4);
13839: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
13840: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
13841: }}}m68k_incpc(6);
13842: return (16+retcycles);
13843: }
13844: unsigned long REGPARAM2 CPUFUNC(op_4cfb_0)(uae_u32 opcode) /* MVMEL */
13845: {
13846: uae_u32 dstreg = 3;
13847: unsigned int retcycles = 0;
13848: OpcodeFamily = 37; CurrentInstrCycles = 18;
13849: { uae_u16 mask = get_iword(2);
13850: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
13851: retcycles = 0;
13852: {m68k_incpc(4);
13853: { uaecptr tmppc = m68k_getpc();
13854: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
13855: BusCyclePenalty += 2;
13856: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
13857: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
13858: }}}} return (18+retcycles);
13859: }
13860: unsigned long REGPARAM2 CPUFUNC(op_4e40_0)(uae_u32 opcode) /* TRAP */
13861: {
13862: uae_u32 srcreg = (opcode & 15);
13863: OpcodeFamily = 39; CurrentInstrCycles = 4;
13864: {{ uae_u32 src = srcreg;
13865: m68k_incpc(2);
13866: Exception(src+32,0,M68000_EXC_SRC_CPU);
13867: }}return 4;
13868: }
13869: unsigned long REGPARAM2 CPUFUNC(op_4e50_0)(uae_u32 opcode) /* LINK */
13870: {
13871: uae_u32 srcreg = (opcode & 7);
13872: OpcodeFamily = 47; CurrentInstrCycles = 18;
13873: {{ uaecptr olda = m68k_areg(regs, 7) - 4;
13874: m68k_areg (regs, 7) = olda;
13875: { uae_s32 src = m68k_areg(regs, srcreg);
13876: put_long(olda,src);
13877: m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
13878: { uae_s16 offs = get_iword(2);
13879: m68k_areg(regs, 7) += offs;
13880: }}}}m68k_incpc(4);
13881: return 18;
13882: }
13883: unsigned long REGPARAM2 CPUFUNC(op_4e58_0)(uae_u32 opcode) /* UNLK */
13884: {
13885: uae_u32 srcreg = (opcode & 7);
13886: OpcodeFamily = 48; CurrentInstrCycles = 12;
13887: {{ uae_s32 src = m68k_areg(regs, srcreg);
13888: m68k_areg(regs, 7) = src;
13889: { uaecptr olda = m68k_areg(regs, 7);
13890: { uae_s32 old = get_long(olda);
13891: m68k_areg(regs, 7) += 4;
13892: m68k_areg(regs, srcreg) = (old);
13893: }}}}m68k_incpc(2);
13894: return 12;
13895: }
13896: unsigned long REGPARAM2 CPUFUNC(op_4e60_0)(uae_u32 opcode) /* MVR2USP */
13897: {
13898: uae_u32 srcreg = (opcode & 7);
13899: OpcodeFamily = 40; CurrentInstrCycles = 4;
13900: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel909; }
13901: {{ uae_s32 src = m68k_areg(regs, srcreg);
13902: regs.usp = src;
13903: }}}m68k_incpc(2);
13904: endlabel909: ;
13905: return 4;
13906: }
13907: unsigned long REGPARAM2 CPUFUNC(op_4e68_0)(uae_u32 opcode) /* MVUSP2R */
13908: {
13909: uae_u32 srcreg = (opcode & 7);
13910: OpcodeFamily = 41; CurrentInstrCycles = 4;
13911: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel910; }
13912: {{ m68k_areg(regs, srcreg) = (regs.usp);
13913: }}}m68k_incpc(2);
13914: endlabel910: ;
13915: return 4;
13916: }
13917: unsigned long REGPARAM2 CPUFUNC(op_4e70_0)(uae_u32 opcode) /* RESET */
13918: {
13919: OpcodeFamily = 42; CurrentInstrCycles = 132;
13920: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel911; }
13921: { customreset();
13922: }}m68k_incpc(2);
13923: endlabel911: ;
13924: return 132;
13925: }
13926: unsigned long REGPARAM2 CPUFUNC(op_4e71_0)(uae_u32 opcode) /* NOP */
13927: {
13928: OpcodeFamily = 43; CurrentInstrCycles = 4;
13929: {}m68k_incpc(2);
13930: return 4;
13931: }
13932: unsigned long REGPARAM2 CPUFUNC(op_4e72_0)(uae_u32 opcode) /* STOP */
13933: {
13934: OpcodeFamily = 44; CurrentInstrCycles = 4;
13935: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel913; }
13936: {{ uae_s16 src = get_iword(2);
13937: regs.sr = src;
13938: MakeFromSR();
13939: m68k_setstopped(1);
13940: }}}m68k_incpc(4);
13941: endlabel913: ;
13942: return 4;
13943: }
13944: unsigned long REGPARAM2 CPUFUNC(op_4e73_0)(uae_u32 opcode) /* RTE */
13945: {
13946: OpcodeFamily = 45; CurrentInstrCycles = 20;
13947: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel914; }
13948: { uae_u16 newsr; uae_u32 newpc; for (;;) {
13949: { uaecptr sra = m68k_areg(regs, 7);
13950: { uae_s16 sr = get_word(sra);
13951: m68k_areg(regs, 7) += 2;
13952: { uaecptr pca = m68k_areg(regs, 7);
13953: { uae_s32 pc = get_long(pca);
13954: m68k_areg(regs, 7) += 4;
13955: { uaecptr formata = m68k_areg(regs, 7);
13956: { uae_s16 format = get_word(formata);
13957: m68k_areg(regs, 7) += 2;
13958: newsr = sr; newpc = pc;
13959: if ((format & 0xF000) == 0x0000) { break; }
13960: else if ((format & 0xF000) == 0x1000) { ; }
13961: else if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }
13962: else if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }
13963: else if ((format & 0xF000) == 0x9000) { m68k_areg(regs, 7) += 12; break; }
13964: else if ((format & 0xF000) == 0xa000) { m68k_areg(regs, 7) += 24; break; }
13965: else if ((format & 0xF000) == 0xb000) { m68k_areg(regs, 7) += 84; break; }
13966: else { Exception(14,0,M68000_EXC_SRC_CPU); goto endlabel914; }
13967: regs.sr = newsr; MakeFromSR();
13968: }
13969: }}}}}} regs.sr = newsr; MakeFromSR();
13970: m68k_setpc_rte(newpc);
13971: }}endlabel914: ;
13972: return 20;
13973: }
13974: unsigned long REGPARAM2 CPUFUNC(op_4e74_0)(uae_u32 opcode) /* RTD */
13975: {
13976: OpcodeFamily = 46; CurrentInstrCycles = 16;
13977: {{ uaecptr pca = m68k_areg(regs, 7);
13978: { uae_s32 pc = get_long(pca);
13979: m68k_areg(regs, 7) += 4;
13980: { uae_s16 offs = get_iword(2);
13981: m68k_areg(regs, 7) += offs;
13982: m68k_setpc_rte(pc);
13983: }}}}return 16;
13984: }
13985: unsigned long REGPARAM2 CPUFUNC(op_4e75_0)(uae_u32 opcode) /* RTS */
13986: {
13987: OpcodeFamily = 49; CurrentInstrCycles = 16;
13988: { m68k_do_rts();
13989: }return 16;
13990: }
13991: unsigned long REGPARAM2 CPUFUNC(op_4e76_0)(uae_u32 opcode) /* TRAPV */
13992: {
13993: OpcodeFamily = 50; CurrentInstrCycles = 4;
13994: {m68k_incpc(2);
13995: if (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel917; }
13996: }endlabel917: ;
13997: return 4;
13998: }
13999: unsigned long REGPARAM2 CPUFUNC(op_4e77_0)(uae_u32 opcode) /* RTR */
14000: {
14001: OpcodeFamily = 51; CurrentInstrCycles = 20;
14002: { MakeSR();
14003: { uaecptr sra = m68k_areg(regs, 7);
14004: { uae_s16 sr = get_word(sra);
14005: m68k_areg(regs, 7) += 2;
14006: { uaecptr pca = m68k_areg(regs, 7);
14007: { uae_s32 pc = get_long(pca);
14008: m68k_areg(regs, 7) += 4;
14009: regs.sr &= 0xFF00; sr &= 0xFF;
14010: regs.sr |= sr; m68k_setpc(pc);
14011: MakeFromSR();
14012: }}}}}return 20;
14013: }
14014: unsigned long REGPARAM2 CPUFUNC(op_4e7a_0)(uae_u32 opcode) /* MOVEC2 */
14015: {
14016: OpcodeFamily = 82; CurrentInstrCycles = 8;
14017: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel919; }
14018: {{ uae_s16 src = get_iword(2);
14019: { int regno = (src >> 12) & 15;
14020: uae_u32 *regp = regs.regs + regno;
14021: if (! m68k_movec2(src & 0xFFF, regp)) goto endlabel919;
14022: }}}}m68k_incpc(4);
14023: endlabel919: ;
14024: return 8;
14025: }
14026: unsigned long REGPARAM2 CPUFUNC(op_4e7b_0)(uae_u32 opcode) /* MOVE2C */
14027: {
14028: OpcodeFamily = 83; CurrentInstrCycles = 8;
14029: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel920; }
14030: {{ uae_s16 src = get_iword(2);
14031: { int regno = (src >> 12) & 15;
14032: uae_u32 *regp = regs.regs + regno;
14033: if (! m68k_move2c(src & 0xFFF, regp)) goto endlabel920;
14034: }}}}m68k_incpc(4);
14035: endlabel920: ;
14036: return 8;
14037: }
14038: unsigned long REGPARAM2 CPUFUNC(op_4e90_0)(uae_u32 opcode) /* JSR */
14039: {
14040: uae_u32 srcreg = (opcode & 7);
14041: OpcodeFamily = 52; CurrentInstrCycles = 16;
14042: {{ uaecptr srca = m68k_areg(regs, srcreg);
14043: m68k_do_jsr(m68k_getpc() + 2, srca);
14044: }}return 16;
14045: }
14046: unsigned long REGPARAM2 CPUFUNC(op_4ea8_0)(uae_u32 opcode) /* JSR */
14047: {
14048: uae_u32 srcreg = (opcode & 7);
14049: OpcodeFamily = 52; CurrentInstrCycles = 18;
14050: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
14051: m68k_do_jsr(m68k_getpc() + 4, srca);
14052: }}return 18;
14053: }
14054: unsigned long REGPARAM2 CPUFUNC(op_4eb0_0)(uae_u32 opcode) /* JSR */
14055: {
14056: uae_u32 srcreg = (opcode & 7);
14057: OpcodeFamily = 52; CurrentInstrCycles = 22;
14058: {{m68k_incpc(2);
14059: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
14060: BusCyclePenalty += 2;
14061: m68k_do_jsr(m68k_getpc() + 0, srca);
14062: }}}return 22;
14063: }
14064: unsigned long REGPARAM2 CPUFUNC(op_4eb8_0)(uae_u32 opcode) /* JSR */
14065: {
14066: OpcodeFamily = 52; CurrentInstrCycles = 18;
14067: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
14068: m68k_do_jsr(m68k_getpc() + 4, srca);
14069: }}return 18;
14070: }
14071: unsigned long REGPARAM2 CPUFUNC(op_4eb9_0)(uae_u32 opcode) /* JSR */
14072: {
14073: OpcodeFamily = 52; CurrentInstrCycles = 20;
14074: {{ uaecptr srca = get_ilong(2);
14075: m68k_do_jsr(m68k_getpc() + 6, srca);
14076: }}return 20;
14077: }
14078: unsigned long REGPARAM2 CPUFUNC(op_4eba_0)(uae_u32 opcode) /* JSR */
14079: {
14080: OpcodeFamily = 52; CurrentInstrCycles = 18;
14081: {{ uaecptr srca = m68k_getpc () + 2;
14082: srca += (uae_s32)(uae_s16)get_iword(2);
14083: m68k_do_jsr(m68k_getpc() + 4, srca);
14084: }}return 18;
14085: }
14086: unsigned long REGPARAM2 CPUFUNC(op_4ebb_0)(uae_u32 opcode) /* JSR */
14087: {
14088: OpcodeFamily = 52; CurrentInstrCycles = 22;
14089: {{m68k_incpc(2);
14090: { uaecptr tmppc = m68k_getpc();
14091: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
14092: BusCyclePenalty += 2;
14093: m68k_do_jsr(m68k_getpc() + 0, srca);
14094: }}}return 22;
14095: }
14096: unsigned long REGPARAM2 CPUFUNC(op_4ed0_0)(uae_u32 opcode) /* JMP */
14097: {
14098: uae_u32 srcreg = (opcode & 7);
14099: OpcodeFamily = 53; CurrentInstrCycles = 8;
14100: {{ uaecptr srca = m68k_areg(regs, srcreg);
14101: m68k_setpc(srca);
14102: }}return 8;
14103: }
14104: unsigned long REGPARAM2 CPUFUNC(op_4ee8_0)(uae_u32 opcode) /* JMP */
14105: {
14106: uae_u32 srcreg = (opcode & 7);
14107: OpcodeFamily = 53; CurrentInstrCycles = 10;
14108: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
14109: m68k_setpc(srca);
14110: }}return 10;
14111: }
14112: unsigned long REGPARAM2 CPUFUNC(op_4ef0_0)(uae_u32 opcode) /* JMP */
14113: {
14114: uae_u32 srcreg = (opcode & 7);
14115: OpcodeFamily = 53; CurrentInstrCycles = 14;
14116: {{m68k_incpc(2);
14117: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
14118: BusCyclePenalty += 2;
14119: m68k_setpc(srca);
14120: }}}return 14;
14121: }
14122: unsigned long REGPARAM2 CPUFUNC(op_4ef8_0)(uae_u32 opcode) /* JMP */
14123: {
14124: OpcodeFamily = 53; CurrentInstrCycles = 10;
14125: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
14126: m68k_setpc(srca);
14127: }}return 10;
14128: }
14129: unsigned long REGPARAM2 CPUFUNC(op_4ef9_0)(uae_u32 opcode) /* JMP */
14130: {
14131: OpcodeFamily = 53; CurrentInstrCycles = 12;
14132: {{ uaecptr srca = get_ilong(2);
14133: m68k_setpc(srca);
14134: }}return 12;
14135: }
14136: unsigned long REGPARAM2 CPUFUNC(op_4efa_0)(uae_u32 opcode) /* JMP */
14137: {
14138: OpcodeFamily = 53; CurrentInstrCycles = 10;
14139: {{ uaecptr srca = m68k_getpc () + 2;
14140: srca += (uae_s32)(uae_s16)get_iword(2);
14141: m68k_setpc(srca);
14142: }}return 10;
14143: }
14144: unsigned long REGPARAM2 CPUFUNC(op_4efb_0)(uae_u32 opcode) /* JMP */
14145: {
14146: OpcodeFamily = 53; CurrentInstrCycles = 14;
14147: {{m68k_incpc(2);
14148: { uaecptr tmppc = m68k_getpc();
14149: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
14150: BusCyclePenalty += 2;
14151: m68k_setpc(srca);
14152: }}}return 14;
14153: }
14154: unsigned long REGPARAM2 CPUFUNC(op_5000_0)(uae_u32 opcode) /* ADD */
14155: {
14156: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14157: uae_u32 dstreg = opcode & 7;
14158: OpcodeFamily = 11; CurrentInstrCycles = 4;
14159: {{ uae_u32 src = srcreg;
14160: { uae_s8 dst = m68k_dreg(regs, dstreg);
14161: { refill_prefetch (m68k_getpc(), 2);
14162: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
14163: { int flgs = ((uae_s8)(src)) < 0;
14164: int flgo = ((uae_s8)(dst)) < 0;
14165: int flgn = ((uae_s8)(newv)) < 0;
14166: SET_ZFLG (((uae_s8)(newv)) == 0);
14167: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14168: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
14169: COPY_CARRY;
14170: SET_NFLG (flgn != 0);
14171: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
14172: }}}}}}m68k_incpc(2);
14173: return 4;
14174: }
14175: unsigned long REGPARAM2 CPUFUNC(op_5010_0)(uae_u32 opcode) /* ADD */
14176: {
14177: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14178: uae_u32 dstreg = opcode & 7;
14179: OpcodeFamily = 11; CurrentInstrCycles = 12;
14180: {{ uae_u32 src = srcreg;
14181: { uaecptr dsta = m68k_areg(regs, dstreg);
14182: { uae_s8 dst = get_byte(dsta);
14183: { refill_prefetch (m68k_getpc(), 2);
14184: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
14185: { int flgs = ((uae_s8)(src)) < 0;
14186: int flgo = ((uae_s8)(dst)) < 0;
14187: int flgn = ((uae_s8)(newv)) < 0;
14188: SET_ZFLG (((uae_s8)(newv)) == 0);
14189: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14190: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
14191: COPY_CARRY;
14192: SET_NFLG (flgn != 0);
14193: put_byte(dsta,newv);
14194: }}}}}}}m68k_incpc(2);
14195: return 12;
14196: }
14197: unsigned long REGPARAM2 CPUFUNC(op_5018_0)(uae_u32 opcode) /* ADD */
14198: {
14199: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14200: uae_u32 dstreg = opcode & 7;
14201: OpcodeFamily = 11; CurrentInstrCycles = 12;
14202: {{ uae_u32 src = srcreg;
14203: { uaecptr dsta = m68k_areg(regs, dstreg);
14204: { uae_s8 dst = get_byte(dsta);
14205: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
14206: { refill_prefetch (m68k_getpc(), 2);
14207: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
14208: { int flgs = ((uae_s8)(src)) < 0;
14209: int flgo = ((uae_s8)(dst)) < 0;
14210: int flgn = ((uae_s8)(newv)) < 0;
14211: SET_ZFLG (((uae_s8)(newv)) == 0);
14212: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14213: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
14214: COPY_CARRY;
14215: SET_NFLG (flgn != 0);
14216: put_byte(dsta,newv);
14217: }}}}}}}m68k_incpc(2);
14218: return 12;
14219: }
14220: #endif
14221:
14222: #ifdef PART_5
14223: unsigned long REGPARAM2 CPUFUNC(op_5020_0)(uae_u32 opcode) /* ADD */
14224: {
14225: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14226: uae_u32 dstreg = opcode & 7;
14227: OpcodeFamily = 11; CurrentInstrCycles = 14;
14228: {{ uae_u32 src = srcreg;
14229: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
14230: { uae_s8 dst = get_byte(dsta);
14231: m68k_areg (regs, dstreg) = dsta;
14232: { refill_prefetch (m68k_getpc(), 2);
14233: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
14234: { int flgs = ((uae_s8)(src)) < 0;
14235: int flgo = ((uae_s8)(dst)) < 0;
14236: int flgn = ((uae_s8)(newv)) < 0;
14237: SET_ZFLG (((uae_s8)(newv)) == 0);
14238: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14239: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
14240: COPY_CARRY;
14241: SET_NFLG (flgn != 0);
14242: put_byte(dsta,newv);
14243: }}}}}}}m68k_incpc(2);
14244: return 14;
14245: }
14246: unsigned long REGPARAM2 CPUFUNC(op_5028_0)(uae_u32 opcode) /* ADD */
14247: {
14248: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14249: uae_u32 dstreg = opcode & 7;
14250: OpcodeFamily = 11; CurrentInstrCycles = 16;
14251: {{ uae_u32 src = srcreg;
14252: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
14253: { uae_s8 dst = get_byte(dsta);
14254: { refill_prefetch (m68k_getpc(), 2);
14255: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
14256: { int flgs = ((uae_s8)(src)) < 0;
14257: int flgo = ((uae_s8)(dst)) < 0;
14258: int flgn = ((uae_s8)(newv)) < 0;
14259: SET_ZFLG (((uae_s8)(newv)) == 0);
14260: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14261: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
14262: COPY_CARRY;
14263: SET_NFLG (flgn != 0);
14264: put_byte(dsta,newv);
14265: }}}}}}}m68k_incpc(4);
14266: return 16;
14267: }
14268: unsigned long REGPARAM2 CPUFUNC(op_5030_0)(uae_u32 opcode) /* ADD */
14269: {
14270: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14271: uae_u32 dstreg = opcode & 7;
14272: OpcodeFamily = 11; CurrentInstrCycles = 18;
14273: {{ uae_u32 src = srcreg;
14274: {m68k_incpc(2);
14275: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
14276: BusCyclePenalty += 2;
14277: { uae_s8 dst = get_byte(dsta);
14278: { refill_prefetch (m68k_getpc(), 2);
14279: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
14280: { int flgs = ((uae_s8)(src)) < 0;
14281: int flgo = ((uae_s8)(dst)) < 0;
14282: int flgn = ((uae_s8)(newv)) < 0;
14283: SET_ZFLG (((uae_s8)(newv)) == 0);
14284: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14285: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
14286: COPY_CARRY;
14287: SET_NFLG (flgn != 0);
14288: put_byte(dsta,newv);
14289: }}}}}}}}return 18;
14290: }
14291: unsigned long REGPARAM2 CPUFUNC(op_5038_0)(uae_u32 opcode) /* ADD */
14292: {
14293: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14294: OpcodeFamily = 11; CurrentInstrCycles = 16;
14295: {{ uae_u32 src = srcreg;
14296: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
14297: { uae_s8 dst = get_byte(dsta);
14298: { refill_prefetch (m68k_getpc(), 2);
14299: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
14300: { int flgs = ((uae_s8)(src)) < 0;
14301: int flgo = ((uae_s8)(dst)) < 0;
14302: int flgn = ((uae_s8)(newv)) < 0;
14303: SET_ZFLG (((uae_s8)(newv)) == 0);
14304: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14305: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
14306: COPY_CARRY;
14307: SET_NFLG (flgn != 0);
14308: put_byte(dsta,newv);
14309: }}}}}}}m68k_incpc(4);
14310: return 16;
14311: }
14312: unsigned long REGPARAM2 CPUFUNC(op_5039_0)(uae_u32 opcode) /* ADD */
14313: {
14314: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14315: OpcodeFamily = 11; CurrentInstrCycles = 20;
14316: {{ uae_u32 src = srcreg;
14317: { uaecptr dsta = get_ilong(2);
14318: { uae_s8 dst = get_byte(dsta);
14319: { refill_prefetch (m68k_getpc(), 2);
14320: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
14321: { int flgs = ((uae_s8)(src)) < 0;
14322: int flgo = ((uae_s8)(dst)) < 0;
14323: int flgn = ((uae_s8)(newv)) < 0;
14324: SET_ZFLG (((uae_s8)(newv)) == 0);
14325: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14326: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
14327: COPY_CARRY;
14328: SET_NFLG (flgn != 0);
14329: put_byte(dsta,newv);
14330: }}}}}}}m68k_incpc(6);
14331: return 20;
14332: }
14333: unsigned long REGPARAM2 CPUFUNC(op_5040_0)(uae_u32 opcode) /* ADD */
14334: {
14335: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14336: uae_u32 dstreg = opcode & 7;
14337: OpcodeFamily = 11; CurrentInstrCycles = 4;
14338: {{ uae_u32 src = srcreg;
14339: { uae_s16 dst = m68k_dreg(regs, dstreg);
14340: { refill_prefetch (m68k_getpc(), 2);
14341: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
14342: { int flgs = ((uae_s16)(src)) < 0;
14343: int flgo = ((uae_s16)(dst)) < 0;
14344: int flgn = ((uae_s16)(newv)) < 0;
14345: SET_ZFLG (((uae_s16)(newv)) == 0);
14346: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14347: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
14348: COPY_CARRY;
14349: SET_NFLG (flgn != 0);
14350: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
14351: }}}}}}m68k_incpc(2);
14352: return 4;
14353: }
14354: unsigned long REGPARAM2 CPUFUNC(op_5048_0)(uae_u32 opcode) /* ADDA */
14355: {
14356: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14357: uae_u32 dstreg = opcode & 7;
14358: OpcodeFamily = 12; CurrentInstrCycles = 8;
14359: {{ uae_u32 src = srcreg;
14360: { uae_s32 dst = m68k_areg(regs, dstreg);
14361: { uae_u32 newv = dst + src;
14362: m68k_areg(regs, dstreg) = (newv);
14363: }}}}m68k_incpc(2);
14364: return 8;
14365: }
14366: unsigned long REGPARAM2 CPUFUNC(op_5050_0)(uae_u32 opcode) /* ADD */
14367: {
14368: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14369: uae_u32 dstreg = opcode & 7;
14370: OpcodeFamily = 11; CurrentInstrCycles = 12;
14371: {{ uae_u32 src = srcreg;
14372: { uaecptr dsta = m68k_areg(regs, dstreg);
14373: { uae_s16 dst = get_word(dsta);
14374: { refill_prefetch (m68k_getpc(), 2);
14375: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
14376: { int flgs = ((uae_s16)(src)) < 0;
14377: int flgo = ((uae_s16)(dst)) < 0;
14378: int flgn = ((uae_s16)(newv)) < 0;
14379: SET_ZFLG (((uae_s16)(newv)) == 0);
14380: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14381: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
14382: COPY_CARRY;
14383: SET_NFLG (flgn != 0);
14384: put_word(dsta,newv);
14385: }}}}}}}m68k_incpc(2);
14386: return 12;
14387: }
14388: unsigned long REGPARAM2 CPUFUNC(op_5058_0)(uae_u32 opcode) /* ADD */
14389: {
14390: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14391: uae_u32 dstreg = opcode & 7;
14392: OpcodeFamily = 11; CurrentInstrCycles = 12;
14393: {{ uae_u32 src = srcreg;
14394: { uaecptr dsta = m68k_areg(regs, dstreg);
14395: { uae_s16 dst = get_word(dsta);
14396: m68k_areg(regs, dstreg) += 2;
14397: { refill_prefetch (m68k_getpc(), 2);
14398: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
14399: { int flgs = ((uae_s16)(src)) < 0;
14400: int flgo = ((uae_s16)(dst)) < 0;
14401: int flgn = ((uae_s16)(newv)) < 0;
14402: SET_ZFLG (((uae_s16)(newv)) == 0);
14403: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14404: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
14405: COPY_CARRY;
14406: SET_NFLG (flgn != 0);
14407: put_word(dsta,newv);
14408: }}}}}}}m68k_incpc(2);
14409: return 12;
14410: }
14411: unsigned long REGPARAM2 CPUFUNC(op_5060_0)(uae_u32 opcode) /* ADD */
14412: {
14413: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14414: uae_u32 dstreg = opcode & 7;
14415: OpcodeFamily = 11; CurrentInstrCycles = 14;
14416: {{ uae_u32 src = srcreg;
14417: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
14418: { uae_s16 dst = get_word(dsta);
14419: m68k_areg (regs, dstreg) = dsta;
14420: { refill_prefetch (m68k_getpc(), 2);
14421: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
14422: { int flgs = ((uae_s16)(src)) < 0;
14423: int flgo = ((uae_s16)(dst)) < 0;
14424: int flgn = ((uae_s16)(newv)) < 0;
14425: SET_ZFLG (((uae_s16)(newv)) == 0);
14426: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14427: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
14428: COPY_CARRY;
14429: SET_NFLG (flgn != 0);
14430: put_word(dsta,newv);
14431: }}}}}}}m68k_incpc(2);
14432: return 14;
14433: }
14434: unsigned long REGPARAM2 CPUFUNC(op_5068_0)(uae_u32 opcode) /* ADD */
14435: {
14436: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14437: uae_u32 dstreg = opcode & 7;
14438: OpcodeFamily = 11; CurrentInstrCycles = 16;
14439: {{ uae_u32 src = srcreg;
14440: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
14441: { uae_s16 dst = get_word(dsta);
14442: { refill_prefetch (m68k_getpc(), 2);
14443: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
14444: { int flgs = ((uae_s16)(src)) < 0;
14445: int flgo = ((uae_s16)(dst)) < 0;
14446: int flgn = ((uae_s16)(newv)) < 0;
14447: SET_ZFLG (((uae_s16)(newv)) == 0);
14448: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14449: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
14450: COPY_CARRY;
14451: SET_NFLG (flgn != 0);
14452: put_word(dsta,newv);
14453: }}}}}}}m68k_incpc(4);
14454: return 16;
14455: }
14456: unsigned long REGPARAM2 CPUFUNC(op_5070_0)(uae_u32 opcode) /* ADD */
14457: {
14458: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14459: uae_u32 dstreg = opcode & 7;
14460: OpcodeFamily = 11; CurrentInstrCycles = 18;
14461: {{ uae_u32 src = srcreg;
14462: {m68k_incpc(2);
14463: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
14464: BusCyclePenalty += 2;
14465: { uae_s16 dst = get_word(dsta);
14466: { refill_prefetch (m68k_getpc(), 2);
14467: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
14468: { int flgs = ((uae_s16)(src)) < 0;
14469: int flgo = ((uae_s16)(dst)) < 0;
14470: int flgn = ((uae_s16)(newv)) < 0;
14471: SET_ZFLG (((uae_s16)(newv)) == 0);
14472: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14473: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
14474: COPY_CARRY;
14475: SET_NFLG (flgn != 0);
14476: put_word(dsta,newv);
14477: }}}}}}}}return 18;
14478: }
14479: unsigned long REGPARAM2 CPUFUNC(op_5078_0)(uae_u32 opcode) /* ADD */
14480: {
14481: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14482: OpcodeFamily = 11; CurrentInstrCycles = 16;
14483: {{ uae_u32 src = srcreg;
14484: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
14485: { uae_s16 dst = get_word(dsta);
14486: { refill_prefetch (m68k_getpc(), 2);
14487: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
14488: { int flgs = ((uae_s16)(src)) < 0;
14489: int flgo = ((uae_s16)(dst)) < 0;
14490: int flgn = ((uae_s16)(newv)) < 0;
14491: SET_ZFLG (((uae_s16)(newv)) == 0);
14492: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14493: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
14494: COPY_CARRY;
14495: SET_NFLG (flgn != 0);
14496: put_word(dsta,newv);
14497: }}}}}}}m68k_incpc(4);
14498: return 16;
14499: }
14500: unsigned long REGPARAM2 CPUFUNC(op_5079_0)(uae_u32 opcode) /* ADD */
14501: {
14502: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14503: OpcodeFamily = 11; CurrentInstrCycles = 20;
14504: {{ uae_u32 src = srcreg;
14505: { uaecptr dsta = get_ilong(2);
14506: { uae_s16 dst = get_word(dsta);
14507: { refill_prefetch (m68k_getpc(), 2);
14508: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
14509: { int flgs = ((uae_s16)(src)) < 0;
14510: int flgo = ((uae_s16)(dst)) < 0;
14511: int flgn = ((uae_s16)(newv)) < 0;
14512: SET_ZFLG (((uae_s16)(newv)) == 0);
14513: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14514: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
14515: COPY_CARRY;
14516: SET_NFLG (flgn != 0);
14517: put_word(dsta,newv);
14518: }}}}}}}m68k_incpc(6);
14519: return 20;
14520: }
14521: unsigned long REGPARAM2 CPUFUNC(op_5080_0)(uae_u32 opcode) /* ADD */
14522: {
14523: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14524: uae_u32 dstreg = opcode & 7;
14525: OpcodeFamily = 11; CurrentInstrCycles = 8;
14526: {{ uae_u32 src = srcreg;
14527: { uae_s32 dst = m68k_dreg(regs, dstreg);
14528: { refill_prefetch (m68k_getpc(), 2);
14529: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
14530: { int flgs = ((uae_s32)(src)) < 0;
14531: int flgo = ((uae_s32)(dst)) < 0;
14532: int flgn = ((uae_s32)(newv)) < 0;
14533: SET_ZFLG (((uae_s32)(newv)) == 0);
14534: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14535: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
14536: COPY_CARRY;
14537: SET_NFLG (flgn != 0);
14538: m68k_dreg(regs, dstreg) = (newv);
14539: }}}}}}m68k_incpc(2);
14540: return 8;
14541: }
14542: unsigned long REGPARAM2 CPUFUNC(op_5088_0)(uae_u32 opcode) /* ADDA */
14543: {
14544: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14545: uae_u32 dstreg = opcode & 7;
14546: OpcodeFamily = 12; CurrentInstrCycles = 8;
14547: {{ uae_u32 src = srcreg;
14548: { uae_s32 dst = m68k_areg(regs, dstreg);
14549: { uae_u32 newv = dst + src;
14550: m68k_areg(regs, dstreg) = (newv);
14551: }}}}m68k_incpc(2);
14552: return 8;
14553: }
14554: unsigned long REGPARAM2 CPUFUNC(op_5090_0)(uae_u32 opcode) /* ADD */
14555: {
14556: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14557: uae_u32 dstreg = opcode & 7;
14558: OpcodeFamily = 11; CurrentInstrCycles = 20;
14559: {{ uae_u32 src = srcreg;
14560: { uaecptr dsta = m68k_areg(regs, dstreg);
14561: { uae_s32 dst = get_long(dsta);
14562: { refill_prefetch (m68k_getpc(), 2);
14563: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
14564: { int flgs = ((uae_s32)(src)) < 0;
14565: int flgo = ((uae_s32)(dst)) < 0;
14566: int flgn = ((uae_s32)(newv)) < 0;
14567: SET_ZFLG (((uae_s32)(newv)) == 0);
14568: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14569: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
14570: COPY_CARRY;
14571: SET_NFLG (flgn != 0);
14572: put_long(dsta,newv);
14573: }}}}}}}m68k_incpc(2);
14574: return 20;
14575: }
14576: unsigned long REGPARAM2 CPUFUNC(op_5098_0)(uae_u32 opcode) /* ADD */
14577: {
14578: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14579: uae_u32 dstreg = opcode & 7;
14580: OpcodeFamily = 11; CurrentInstrCycles = 20;
14581: {{ uae_u32 src = srcreg;
14582: { uaecptr dsta = m68k_areg(regs, dstreg);
14583: { uae_s32 dst = get_long(dsta);
14584: m68k_areg(regs, dstreg) += 4;
14585: { refill_prefetch (m68k_getpc(), 2);
14586: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
14587: { int flgs = ((uae_s32)(src)) < 0;
14588: int flgo = ((uae_s32)(dst)) < 0;
14589: int flgn = ((uae_s32)(newv)) < 0;
14590: SET_ZFLG (((uae_s32)(newv)) == 0);
14591: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14592: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
14593: COPY_CARRY;
14594: SET_NFLG (flgn != 0);
14595: put_long(dsta,newv);
14596: }}}}}}}m68k_incpc(2);
14597: return 20;
14598: }
14599: unsigned long REGPARAM2 CPUFUNC(op_50a0_0)(uae_u32 opcode) /* ADD */
14600: {
14601: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14602: uae_u32 dstreg = opcode & 7;
14603: OpcodeFamily = 11; CurrentInstrCycles = 22;
14604: {{ uae_u32 src = srcreg;
14605: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
14606: { uae_s32 dst = get_long(dsta);
14607: m68k_areg (regs, dstreg) = dsta;
14608: { refill_prefetch (m68k_getpc(), 2);
14609: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
14610: { int flgs = ((uae_s32)(src)) < 0;
14611: int flgo = ((uae_s32)(dst)) < 0;
14612: int flgn = ((uae_s32)(newv)) < 0;
14613: SET_ZFLG (((uae_s32)(newv)) == 0);
14614: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14615: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
14616: COPY_CARRY;
14617: SET_NFLG (flgn != 0);
14618: put_long(dsta,newv);
14619: }}}}}}}m68k_incpc(2);
14620: return 22;
14621: }
14622: unsigned long REGPARAM2 CPUFUNC(op_50a8_0)(uae_u32 opcode) /* ADD */
14623: {
14624: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14625: uae_u32 dstreg = opcode & 7;
14626: OpcodeFamily = 11; CurrentInstrCycles = 24;
14627: {{ uae_u32 src = srcreg;
14628: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
14629: { uae_s32 dst = get_long(dsta);
14630: { refill_prefetch (m68k_getpc(), 2);
14631: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
14632: { int flgs = ((uae_s32)(src)) < 0;
14633: int flgo = ((uae_s32)(dst)) < 0;
14634: int flgn = ((uae_s32)(newv)) < 0;
14635: SET_ZFLG (((uae_s32)(newv)) == 0);
14636: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14637: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
14638: COPY_CARRY;
14639: SET_NFLG (flgn != 0);
14640: put_long(dsta,newv);
14641: }}}}}}}m68k_incpc(4);
14642: return 24;
14643: }
14644: unsigned long REGPARAM2 CPUFUNC(op_50b0_0)(uae_u32 opcode) /* ADD */
14645: {
14646: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14647: uae_u32 dstreg = opcode & 7;
14648: OpcodeFamily = 11; CurrentInstrCycles = 26;
14649: {{ uae_u32 src = srcreg;
14650: {m68k_incpc(2);
14651: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
14652: BusCyclePenalty += 2;
14653: { uae_s32 dst = get_long(dsta);
14654: { refill_prefetch (m68k_getpc(), 2);
14655: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
14656: { int flgs = ((uae_s32)(src)) < 0;
14657: int flgo = ((uae_s32)(dst)) < 0;
14658: int flgn = ((uae_s32)(newv)) < 0;
14659: SET_ZFLG (((uae_s32)(newv)) == 0);
14660: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14661: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
14662: COPY_CARRY;
14663: SET_NFLG (flgn != 0);
14664: put_long(dsta,newv);
14665: }}}}}}}}return 26;
14666: }
14667: unsigned long REGPARAM2 CPUFUNC(op_50b8_0)(uae_u32 opcode) /* ADD */
14668: {
14669: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14670: OpcodeFamily = 11; CurrentInstrCycles = 24;
14671: {{ uae_u32 src = srcreg;
14672: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
14673: { uae_s32 dst = get_long(dsta);
14674: { refill_prefetch (m68k_getpc(), 2);
14675: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
14676: { int flgs = ((uae_s32)(src)) < 0;
14677: int flgo = ((uae_s32)(dst)) < 0;
14678: int flgn = ((uae_s32)(newv)) < 0;
14679: SET_ZFLG (((uae_s32)(newv)) == 0);
14680: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14681: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
14682: COPY_CARRY;
14683: SET_NFLG (flgn != 0);
14684: put_long(dsta,newv);
14685: }}}}}}}m68k_incpc(4);
14686: return 24;
14687: }
14688: unsigned long REGPARAM2 CPUFUNC(op_50b9_0)(uae_u32 opcode) /* ADD */
14689: {
14690: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14691: OpcodeFamily = 11; CurrentInstrCycles = 28;
14692: {{ uae_u32 src = srcreg;
14693: { uaecptr dsta = get_ilong(2);
14694: { uae_s32 dst = get_long(dsta);
14695: { refill_prefetch (m68k_getpc(), 2);
14696: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
14697: { int flgs = ((uae_s32)(src)) < 0;
14698: int flgo = ((uae_s32)(dst)) < 0;
14699: int flgn = ((uae_s32)(newv)) < 0;
14700: SET_ZFLG (((uae_s32)(newv)) == 0);
14701: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
14702: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
14703: COPY_CARRY;
14704: SET_NFLG (flgn != 0);
14705: put_long(dsta,newv);
14706: }}}}}}}m68k_incpc(6);
14707: return 28;
14708: }
14709: unsigned long REGPARAM2 CPUFUNC(op_50c0_0)(uae_u32 opcode) /* Scc */
14710: {
14711: uae_u32 srcreg = (opcode & 7);
14712: OpcodeFamily = 59; CurrentInstrCycles = 4;
14713: {{{ int val = cctrue(0) ? 0xff : 0;
14714: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
14715: if (val) { m68k_incpc(2) ; return 4+2; }
14716: }}}m68k_incpc(2);
14717: return 4;
14718: }
14719: unsigned long REGPARAM2 CPUFUNC(op_50c8_0)(uae_u32 opcode) /* DBcc */
14720: {
14721: uae_u32 srcreg = (opcode & 7);
14722: OpcodeFamily = 58; CurrentInstrCycles = 12;
14723: {{ uae_s16 src = m68k_dreg(regs, srcreg);
14724: { uae_s16 offs = get_iword(2);
14725: if (!cctrue(0)) {
14726: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
14727: if (src) {
14728: m68k_incpc((uae_s32)offs + 2);
14729: return 10;
14730: } else {
14731: m68k_incpc(4);
14732: return 14;
14733: }
14734: }
14735: }}}m68k_incpc(4);
14736: endlabel962: ;
14737: return 12;
14738: }
14739: unsigned long REGPARAM2 CPUFUNC(op_50d0_0)(uae_u32 opcode) /* Scc */
14740: {
14741: uae_u32 srcreg = (opcode & 7);
14742: OpcodeFamily = 59; CurrentInstrCycles = 12;
14743: {{ uaecptr srca = m68k_areg(regs, srcreg);
14744: { int val = cctrue(0) ? 0xff : 0;
14745: put_byte(srca,val);
14746: }}}m68k_incpc(2);
14747: return 12;
14748: }
14749: unsigned long REGPARAM2 CPUFUNC(op_50d8_0)(uae_u32 opcode) /* Scc */
14750: {
14751: uae_u32 srcreg = (opcode & 7);
14752: OpcodeFamily = 59; CurrentInstrCycles = 12;
14753: {{ uaecptr srca = m68k_areg(regs, srcreg);
14754: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
14755: { int val = cctrue(0) ? 0xff : 0;
14756: put_byte(srca,val);
14757: }}}m68k_incpc(2);
14758: return 12;
14759: }
14760: unsigned long REGPARAM2 CPUFUNC(op_50e0_0)(uae_u32 opcode) /* Scc */
14761: {
14762: uae_u32 srcreg = (opcode & 7);
14763: OpcodeFamily = 59; CurrentInstrCycles = 14;
14764: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
14765: m68k_areg (regs, srcreg) = srca;
14766: { int val = cctrue(0) ? 0xff : 0;
14767: put_byte(srca,val);
14768: }}}m68k_incpc(2);
14769: return 14;
14770: }
14771: unsigned long REGPARAM2 CPUFUNC(op_50e8_0)(uae_u32 opcode) /* Scc */
14772: {
14773: uae_u32 srcreg = (opcode & 7);
14774: OpcodeFamily = 59; CurrentInstrCycles = 16;
14775: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
14776: { int val = cctrue(0) ? 0xff : 0;
14777: put_byte(srca,val);
14778: }}}m68k_incpc(4);
14779: return 16;
14780: }
14781: unsigned long REGPARAM2 CPUFUNC(op_50f0_0)(uae_u32 opcode) /* Scc */
14782: {
14783: uae_u32 srcreg = (opcode & 7);
14784: OpcodeFamily = 59; CurrentInstrCycles = 18;
14785: {{m68k_incpc(2);
14786: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
14787: BusCyclePenalty += 2;
14788: { int val = cctrue(0) ? 0xff : 0;
14789: put_byte(srca,val);
14790: }}}}return 18;
14791: }
14792: unsigned long REGPARAM2 CPUFUNC(op_50f8_0)(uae_u32 opcode) /* Scc */
14793: {
14794: OpcodeFamily = 59; CurrentInstrCycles = 16;
14795: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
14796: { int val = cctrue(0) ? 0xff : 0;
14797: put_byte(srca,val);
14798: }}}m68k_incpc(4);
14799: return 16;
14800: }
14801: unsigned long REGPARAM2 CPUFUNC(op_50f9_0)(uae_u32 opcode) /* Scc */
14802: {
14803: OpcodeFamily = 59; CurrentInstrCycles = 20;
14804: {{ uaecptr srca = get_ilong(2);
14805: { int val = cctrue(0) ? 0xff : 0;
14806: put_byte(srca,val);
14807: }}}m68k_incpc(6);
14808: return 20;
14809: }
14810: unsigned long REGPARAM2 CPUFUNC(op_50fa_0)(uae_u32 opcode) /* TRAPcc */
14811: {
14812: OpcodeFamily = 102; CurrentInstrCycles = 8;
14813: {{ uae_s16 dummy = get_iword(2);
14814: if (cctrue(0)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel970; }
14815: }}m68k_incpc(4);
14816: endlabel970: ;
14817: return 8;
14818: }
14819: unsigned long REGPARAM2 CPUFUNC(op_50fb_0)(uae_u32 opcode) /* TRAPcc */
14820: {
14821: OpcodeFamily = 102; CurrentInstrCycles = 12;
14822: {{ uae_s32 dummy = get_ilong(2);
14823: if (cctrue(0)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel971; }
14824: }}m68k_incpc(6);
14825: endlabel971: ;
14826: return 12;
14827: }
14828: unsigned long REGPARAM2 CPUFUNC(op_50fc_0)(uae_u32 opcode) /* TRAPcc */
14829: {
14830: OpcodeFamily = 102; CurrentInstrCycles = 4;
14831: { if (cctrue(0)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel972; }
14832: }m68k_incpc(2);
14833: endlabel972: ;
14834: return 4;
14835: }
14836: unsigned long REGPARAM2 CPUFUNC(op_5100_0)(uae_u32 opcode) /* SUB */
14837: {
14838: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14839: uae_u32 dstreg = opcode & 7;
14840: OpcodeFamily = 7; CurrentInstrCycles = 4;
14841: {{ uae_u32 src = srcreg;
14842: { uae_s8 dst = m68k_dreg(regs, dstreg);
14843: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
14844: { int flgs = ((uae_s8)(src)) < 0;
14845: int flgo = ((uae_s8)(dst)) < 0;
14846: int flgn = ((uae_s8)(newv)) < 0;
14847: SET_ZFLG (((uae_s8)(newv)) == 0);
14848: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
14849: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
14850: COPY_CARRY;
14851: SET_NFLG (flgn != 0);
14852: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
14853: }}}}}}m68k_incpc(2);
14854: return 4;
14855: }
14856: unsigned long REGPARAM2 CPUFUNC(op_5110_0)(uae_u32 opcode) /* SUB */
14857: {
14858: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14859: uae_u32 dstreg = opcode & 7;
14860: OpcodeFamily = 7; CurrentInstrCycles = 12;
14861: {{ uae_u32 src = srcreg;
14862: { uaecptr dsta = m68k_areg(regs, dstreg);
14863: { uae_s8 dst = get_byte(dsta);
14864: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
14865: { int flgs = ((uae_s8)(src)) < 0;
14866: int flgo = ((uae_s8)(dst)) < 0;
14867: int flgn = ((uae_s8)(newv)) < 0;
14868: SET_ZFLG (((uae_s8)(newv)) == 0);
14869: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
14870: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
14871: COPY_CARRY;
14872: SET_NFLG (flgn != 0);
14873: put_byte(dsta,newv);
14874: }}}}}}}m68k_incpc(2);
14875: return 12;
14876: }
14877: unsigned long REGPARAM2 CPUFUNC(op_5118_0)(uae_u32 opcode) /* SUB */
14878: {
14879: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14880: uae_u32 dstreg = opcode & 7;
14881: OpcodeFamily = 7; CurrentInstrCycles = 12;
14882: {{ uae_u32 src = srcreg;
14883: { uaecptr dsta = m68k_areg(regs, dstreg);
14884: { uae_s8 dst = get_byte(dsta);
14885: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
14886: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
14887: { int flgs = ((uae_s8)(src)) < 0;
14888: int flgo = ((uae_s8)(dst)) < 0;
14889: int flgn = ((uae_s8)(newv)) < 0;
14890: SET_ZFLG (((uae_s8)(newv)) == 0);
14891: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
14892: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
14893: COPY_CARRY;
14894: SET_NFLG (flgn != 0);
14895: put_byte(dsta,newv);
14896: }}}}}}}m68k_incpc(2);
14897: return 12;
14898: }
14899: unsigned long REGPARAM2 CPUFUNC(op_5120_0)(uae_u32 opcode) /* SUB */
14900: {
14901: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14902: uae_u32 dstreg = opcode & 7;
14903: OpcodeFamily = 7; CurrentInstrCycles = 14;
14904: {{ uae_u32 src = srcreg;
14905: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
14906: { uae_s8 dst = get_byte(dsta);
14907: m68k_areg (regs, dstreg) = dsta;
14908: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
14909: { int flgs = ((uae_s8)(src)) < 0;
14910: int flgo = ((uae_s8)(dst)) < 0;
14911: int flgn = ((uae_s8)(newv)) < 0;
14912: SET_ZFLG (((uae_s8)(newv)) == 0);
14913: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
14914: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
14915: COPY_CARRY;
14916: SET_NFLG (flgn != 0);
14917: put_byte(dsta,newv);
14918: }}}}}}}m68k_incpc(2);
14919: return 14;
14920: }
14921: unsigned long REGPARAM2 CPUFUNC(op_5128_0)(uae_u32 opcode) /* SUB */
14922: {
14923: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14924: uae_u32 dstreg = opcode & 7;
14925: OpcodeFamily = 7; CurrentInstrCycles = 16;
14926: {{ uae_u32 src = srcreg;
14927: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
14928: { uae_s8 dst = get_byte(dsta);
14929: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
14930: { int flgs = ((uae_s8)(src)) < 0;
14931: int flgo = ((uae_s8)(dst)) < 0;
14932: int flgn = ((uae_s8)(newv)) < 0;
14933: SET_ZFLG (((uae_s8)(newv)) == 0);
14934: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
14935: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
14936: COPY_CARRY;
14937: SET_NFLG (flgn != 0);
14938: put_byte(dsta,newv);
14939: }}}}}}}m68k_incpc(4);
14940: return 16;
14941: }
14942: unsigned long REGPARAM2 CPUFUNC(op_5130_0)(uae_u32 opcode) /* SUB */
14943: {
14944: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14945: uae_u32 dstreg = opcode & 7;
14946: OpcodeFamily = 7; CurrentInstrCycles = 18;
14947: {{ uae_u32 src = srcreg;
14948: {m68k_incpc(2);
14949: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
14950: BusCyclePenalty += 2;
14951: { uae_s8 dst = get_byte(dsta);
14952: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
14953: { int flgs = ((uae_s8)(src)) < 0;
14954: int flgo = ((uae_s8)(dst)) < 0;
14955: int flgn = ((uae_s8)(newv)) < 0;
14956: SET_ZFLG (((uae_s8)(newv)) == 0);
14957: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
14958: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
14959: COPY_CARRY;
14960: SET_NFLG (flgn != 0);
14961: put_byte(dsta,newv);
14962: }}}}}}}}return 18;
14963: }
14964: unsigned long REGPARAM2 CPUFUNC(op_5138_0)(uae_u32 opcode) /* SUB */
14965: {
14966: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14967: OpcodeFamily = 7; CurrentInstrCycles = 16;
14968: {{ uae_u32 src = srcreg;
14969: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
14970: { uae_s8 dst = get_byte(dsta);
14971: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
14972: { int flgs = ((uae_s8)(src)) < 0;
14973: int flgo = ((uae_s8)(dst)) < 0;
14974: int flgn = ((uae_s8)(newv)) < 0;
14975: SET_ZFLG (((uae_s8)(newv)) == 0);
14976: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
14977: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
14978: COPY_CARRY;
14979: SET_NFLG (flgn != 0);
14980: put_byte(dsta,newv);
14981: }}}}}}}m68k_incpc(4);
14982: return 16;
14983: }
14984: unsigned long REGPARAM2 CPUFUNC(op_5139_0)(uae_u32 opcode) /* SUB */
14985: {
14986: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
14987: OpcodeFamily = 7; CurrentInstrCycles = 20;
14988: {{ uae_u32 src = srcreg;
14989: { uaecptr dsta = get_ilong(2);
14990: { uae_s8 dst = get_byte(dsta);
14991: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
14992: { int flgs = ((uae_s8)(src)) < 0;
14993: int flgo = ((uae_s8)(dst)) < 0;
14994: int flgn = ((uae_s8)(newv)) < 0;
14995: SET_ZFLG (((uae_s8)(newv)) == 0);
14996: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
14997: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
14998: COPY_CARRY;
14999: SET_NFLG (flgn != 0);
15000: put_byte(dsta,newv);
15001: }}}}}}}m68k_incpc(6);
15002: return 20;
15003: }
15004: unsigned long REGPARAM2 CPUFUNC(op_5140_0)(uae_u32 opcode) /* SUB */
15005: {
15006: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15007: uae_u32 dstreg = opcode & 7;
15008: OpcodeFamily = 7; CurrentInstrCycles = 4;
15009: {{ uae_u32 src = srcreg;
15010: { uae_s16 dst = m68k_dreg(regs, dstreg);
15011: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
15012: { int flgs = ((uae_s16)(src)) < 0;
15013: int flgo = ((uae_s16)(dst)) < 0;
15014: int flgn = ((uae_s16)(newv)) < 0;
15015: SET_ZFLG (((uae_s16)(newv)) == 0);
15016: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15017: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
15018: COPY_CARRY;
15019: SET_NFLG (flgn != 0);
15020: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
15021: }}}}}}m68k_incpc(2);
15022: return 4;
15023: }
15024: unsigned long REGPARAM2 CPUFUNC(op_5148_0)(uae_u32 opcode) /* SUBA */
15025: {
15026: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15027: uae_u32 dstreg = opcode & 7;
15028: OpcodeFamily = 8; CurrentInstrCycles = 8;
15029: {{ uae_u32 src = srcreg;
15030: { uae_s32 dst = m68k_areg(regs, dstreg);
15031: { uae_u32 newv = dst - src;
15032: m68k_areg(regs, dstreg) = (newv);
15033: }}}}m68k_incpc(2);
15034: return 8;
15035: }
15036: unsigned long REGPARAM2 CPUFUNC(op_5150_0)(uae_u32 opcode) /* SUB */
15037: {
15038: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15039: uae_u32 dstreg = opcode & 7;
15040: OpcodeFamily = 7; CurrentInstrCycles = 12;
15041: {{ uae_u32 src = srcreg;
15042: { uaecptr dsta = m68k_areg(regs, dstreg);
15043: { uae_s16 dst = get_word(dsta);
15044: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
15045: { int flgs = ((uae_s16)(src)) < 0;
15046: int flgo = ((uae_s16)(dst)) < 0;
15047: int flgn = ((uae_s16)(newv)) < 0;
15048: SET_ZFLG (((uae_s16)(newv)) == 0);
15049: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15050: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
15051: COPY_CARRY;
15052: SET_NFLG (flgn != 0);
15053: put_word(dsta,newv);
15054: }}}}}}}m68k_incpc(2);
15055: return 12;
15056: }
15057: unsigned long REGPARAM2 CPUFUNC(op_5158_0)(uae_u32 opcode) /* SUB */
15058: {
15059: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15060: uae_u32 dstreg = opcode & 7;
15061: OpcodeFamily = 7; CurrentInstrCycles = 12;
15062: {{ uae_u32 src = srcreg;
15063: { uaecptr dsta = m68k_areg(regs, dstreg);
15064: { uae_s16 dst = get_word(dsta);
15065: m68k_areg(regs, dstreg) += 2;
15066: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
15067: { int flgs = ((uae_s16)(src)) < 0;
15068: int flgo = ((uae_s16)(dst)) < 0;
15069: int flgn = ((uae_s16)(newv)) < 0;
15070: SET_ZFLG (((uae_s16)(newv)) == 0);
15071: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15072: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
15073: COPY_CARRY;
15074: SET_NFLG (flgn != 0);
15075: put_word(dsta,newv);
15076: }}}}}}}m68k_incpc(2);
15077: return 12;
15078: }
15079: unsigned long REGPARAM2 CPUFUNC(op_5160_0)(uae_u32 opcode) /* SUB */
15080: {
15081: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15082: uae_u32 dstreg = opcode & 7;
15083: OpcodeFamily = 7; CurrentInstrCycles = 14;
15084: {{ uae_u32 src = srcreg;
15085: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
15086: { uae_s16 dst = get_word(dsta);
15087: m68k_areg (regs, dstreg) = dsta;
15088: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
15089: { int flgs = ((uae_s16)(src)) < 0;
15090: int flgo = ((uae_s16)(dst)) < 0;
15091: int flgn = ((uae_s16)(newv)) < 0;
15092: SET_ZFLG (((uae_s16)(newv)) == 0);
15093: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15094: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
15095: COPY_CARRY;
15096: SET_NFLG (flgn != 0);
15097: put_word(dsta,newv);
15098: }}}}}}}m68k_incpc(2);
15099: return 14;
15100: }
15101: unsigned long REGPARAM2 CPUFUNC(op_5168_0)(uae_u32 opcode) /* SUB */
15102: {
15103: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15104: uae_u32 dstreg = opcode & 7;
15105: OpcodeFamily = 7; CurrentInstrCycles = 16;
15106: {{ uae_u32 src = srcreg;
15107: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
15108: { uae_s16 dst = get_word(dsta);
15109: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
15110: { int flgs = ((uae_s16)(src)) < 0;
15111: int flgo = ((uae_s16)(dst)) < 0;
15112: int flgn = ((uae_s16)(newv)) < 0;
15113: SET_ZFLG (((uae_s16)(newv)) == 0);
15114: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15115: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
15116: COPY_CARRY;
15117: SET_NFLG (flgn != 0);
15118: put_word(dsta,newv);
15119: }}}}}}}m68k_incpc(4);
15120: return 16;
15121: }
15122: unsigned long REGPARAM2 CPUFUNC(op_5170_0)(uae_u32 opcode) /* SUB */
15123: {
15124: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15125: uae_u32 dstreg = opcode & 7;
15126: OpcodeFamily = 7; CurrentInstrCycles = 18;
15127: {{ uae_u32 src = srcreg;
15128: {m68k_incpc(2);
15129: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
15130: BusCyclePenalty += 2;
15131: { uae_s16 dst = get_word(dsta);
15132: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
15133: { int flgs = ((uae_s16)(src)) < 0;
15134: int flgo = ((uae_s16)(dst)) < 0;
15135: int flgn = ((uae_s16)(newv)) < 0;
15136: SET_ZFLG (((uae_s16)(newv)) == 0);
15137: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15138: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
15139: COPY_CARRY;
15140: SET_NFLG (flgn != 0);
15141: put_word(dsta,newv);
15142: }}}}}}}}return 18;
15143: }
15144: unsigned long REGPARAM2 CPUFUNC(op_5178_0)(uae_u32 opcode) /* SUB */
15145: {
15146: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15147: OpcodeFamily = 7; CurrentInstrCycles = 16;
15148: {{ uae_u32 src = srcreg;
15149: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
15150: { uae_s16 dst = get_word(dsta);
15151: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
15152: { int flgs = ((uae_s16)(src)) < 0;
15153: int flgo = ((uae_s16)(dst)) < 0;
15154: int flgn = ((uae_s16)(newv)) < 0;
15155: SET_ZFLG (((uae_s16)(newv)) == 0);
15156: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15157: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
15158: COPY_CARRY;
15159: SET_NFLG (flgn != 0);
15160: put_word(dsta,newv);
15161: }}}}}}}m68k_incpc(4);
15162: return 16;
15163: }
15164: unsigned long REGPARAM2 CPUFUNC(op_5179_0)(uae_u32 opcode) /* SUB */
15165: {
15166: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15167: OpcodeFamily = 7; CurrentInstrCycles = 20;
15168: {{ uae_u32 src = srcreg;
15169: { uaecptr dsta = get_ilong(2);
15170: { uae_s16 dst = get_word(dsta);
15171: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
15172: { int flgs = ((uae_s16)(src)) < 0;
15173: int flgo = ((uae_s16)(dst)) < 0;
15174: int flgn = ((uae_s16)(newv)) < 0;
15175: SET_ZFLG (((uae_s16)(newv)) == 0);
15176: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15177: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
15178: COPY_CARRY;
15179: SET_NFLG (flgn != 0);
15180: put_word(dsta,newv);
15181: }}}}}}}m68k_incpc(6);
15182: return 20;
15183: }
15184: unsigned long REGPARAM2 CPUFUNC(op_5180_0)(uae_u32 opcode) /* SUB */
15185: {
15186: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15187: uae_u32 dstreg = opcode & 7;
15188: OpcodeFamily = 7; CurrentInstrCycles = 8;
15189: {{ uae_u32 src = srcreg;
15190: { uae_s32 dst = m68k_dreg(regs, dstreg);
15191: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
15192: { int flgs = ((uae_s32)(src)) < 0;
15193: int flgo = ((uae_s32)(dst)) < 0;
15194: int flgn = ((uae_s32)(newv)) < 0;
15195: SET_ZFLG (((uae_s32)(newv)) == 0);
15196: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15197: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
15198: COPY_CARRY;
15199: SET_NFLG (flgn != 0);
15200: m68k_dreg(regs, dstreg) = (newv);
15201: }}}}}}m68k_incpc(2);
15202: return 8;
15203: }
15204: unsigned long REGPARAM2 CPUFUNC(op_5188_0)(uae_u32 opcode) /* SUBA */
15205: {
15206: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15207: uae_u32 dstreg = opcode & 7;
15208: OpcodeFamily = 8; CurrentInstrCycles = 8;
15209: {{ uae_u32 src = srcreg;
15210: { uae_s32 dst = m68k_areg(regs, dstreg);
15211: { uae_u32 newv = dst - src;
15212: m68k_areg(regs, dstreg) = (newv);
15213: }}}}m68k_incpc(2);
15214: return 8;
15215: }
15216: unsigned long REGPARAM2 CPUFUNC(op_5190_0)(uae_u32 opcode) /* SUB */
15217: {
15218: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15219: uae_u32 dstreg = opcode & 7;
15220: OpcodeFamily = 7; CurrentInstrCycles = 20;
15221: {{ uae_u32 src = srcreg;
15222: { uaecptr dsta = m68k_areg(regs, dstreg);
15223: { uae_s32 dst = get_long(dsta);
15224: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
15225: { int flgs = ((uae_s32)(src)) < 0;
15226: int flgo = ((uae_s32)(dst)) < 0;
15227: int flgn = ((uae_s32)(newv)) < 0;
15228: SET_ZFLG (((uae_s32)(newv)) == 0);
15229: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15230: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
15231: COPY_CARRY;
15232: SET_NFLG (flgn != 0);
15233: put_long(dsta,newv);
15234: }}}}}}}m68k_incpc(2);
15235: return 20;
15236: }
15237: unsigned long REGPARAM2 CPUFUNC(op_5198_0)(uae_u32 opcode) /* SUB */
15238: {
15239: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15240: uae_u32 dstreg = opcode & 7;
15241: OpcodeFamily = 7; CurrentInstrCycles = 20;
15242: {{ uae_u32 src = srcreg;
15243: { uaecptr dsta = m68k_areg(regs, dstreg);
15244: { uae_s32 dst = get_long(dsta);
15245: m68k_areg(regs, dstreg) += 4;
15246: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
15247: { int flgs = ((uae_s32)(src)) < 0;
15248: int flgo = ((uae_s32)(dst)) < 0;
15249: int flgn = ((uae_s32)(newv)) < 0;
15250: SET_ZFLG (((uae_s32)(newv)) == 0);
15251: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15252: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
15253: COPY_CARRY;
15254: SET_NFLG (flgn != 0);
15255: put_long(dsta,newv);
15256: }}}}}}}m68k_incpc(2);
15257: return 20;
15258: }
15259: unsigned long REGPARAM2 CPUFUNC(op_51a0_0)(uae_u32 opcode) /* SUB */
15260: {
15261: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15262: uae_u32 dstreg = opcode & 7;
15263: OpcodeFamily = 7; CurrentInstrCycles = 22;
15264: {{ uae_u32 src = srcreg;
15265: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
15266: { uae_s32 dst = get_long(dsta);
15267: m68k_areg (regs, dstreg) = dsta;
15268: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
15269: { int flgs = ((uae_s32)(src)) < 0;
15270: int flgo = ((uae_s32)(dst)) < 0;
15271: int flgn = ((uae_s32)(newv)) < 0;
15272: SET_ZFLG (((uae_s32)(newv)) == 0);
15273: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15274: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
15275: COPY_CARRY;
15276: SET_NFLG (flgn != 0);
15277: put_long(dsta,newv);
15278: }}}}}}}m68k_incpc(2);
15279: return 22;
15280: }
15281: unsigned long REGPARAM2 CPUFUNC(op_51a8_0)(uae_u32 opcode) /* SUB */
15282: {
15283: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15284: uae_u32 dstreg = opcode & 7;
15285: OpcodeFamily = 7; CurrentInstrCycles = 24;
15286: {{ uae_u32 src = srcreg;
15287: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
15288: { uae_s32 dst = get_long(dsta);
15289: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
15290: { int flgs = ((uae_s32)(src)) < 0;
15291: int flgo = ((uae_s32)(dst)) < 0;
15292: int flgn = ((uae_s32)(newv)) < 0;
15293: SET_ZFLG (((uae_s32)(newv)) == 0);
15294: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15295: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
15296: COPY_CARRY;
15297: SET_NFLG (flgn != 0);
15298: put_long(dsta,newv);
15299: }}}}}}}m68k_incpc(4);
15300: return 24;
15301: }
15302: unsigned long REGPARAM2 CPUFUNC(op_51b0_0)(uae_u32 opcode) /* SUB */
15303: {
15304: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15305: uae_u32 dstreg = opcode & 7;
15306: OpcodeFamily = 7; CurrentInstrCycles = 26;
15307: {{ uae_u32 src = srcreg;
15308: {m68k_incpc(2);
15309: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
15310: BusCyclePenalty += 2;
15311: { uae_s32 dst = get_long(dsta);
15312: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
15313: { int flgs = ((uae_s32)(src)) < 0;
15314: int flgo = ((uae_s32)(dst)) < 0;
15315: int flgn = ((uae_s32)(newv)) < 0;
15316: SET_ZFLG (((uae_s32)(newv)) == 0);
15317: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15318: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
15319: COPY_CARRY;
15320: SET_NFLG (flgn != 0);
15321: put_long(dsta,newv);
15322: }}}}}}}}return 26;
15323: }
15324: unsigned long REGPARAM2 CPUFUNC(op_51b8_0)(uae_u32 opcode) /* SUB */
15325: {
15326: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15327: OpcodeFamily = 7; CurrentInstrCycles = 24;
15328: {{ uae_u32 src = srcreg;
15329: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
15330: { uae_s32 dst = get_long(dsta);
15331: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
15332: { int flgs = ((uae_s32)(src)) < 0;
15333: int flgo = ((uae_s32)(dst)) < 0;
15334: int flgn = ((uae_s32)(newv)) < 0;
15335: SET_ZFLG (((uae_s32)(newv)) == 0);
15336: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15337: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
15338: COPY_CARRY;
15339: SET_NFLG (flgn != 0);
15340: put_long(dsta,newv);
15341: }}}}}}}m68k_incpc(4);
15342: return 24;
15343: }
15344: unsigned long REGPARAM2 CPUFUNC(op_51b9_0)(uae_u32 opcode) /* SUB */
15345: {
15346: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
15347: OpcodeFamily = 7; CurrentInstrCycles = 28;
15348: {{ uae_u32 src = srcreg;
15349: { uaecptr dsta = get_ilong(2);
15350: { uae_s32 dst = get_long(dsta);
15351: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
15352: { int flgs = ((uae_s32)(src)) < 0;
15353: int flgo = ((uae_s32)(dst)) < 0;
15354: int flgn = ((uae_s32)(newv)) < 0;
15355: SET_ZFLG (((uae_s32)(newv)) == 0);
15356: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
15357: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
15358: COPY_CARRY;
15359: SET_NFLG (flgn != 0);
15360: put_long(dsta,newv);
15361: }}}}}}}m68k_incpc(6);
15362: return 28;
15363: }
15364: unsigned long REGPARAM2 CPUFUNC(op_51c0_0)(uae_u32 opcode) /* Scc */
15365: {
15366: uae_u32 srcreg = (opcode & 7);
15367: OpcodeFamily = 59; CurrentInstrCycles = 4;
15368: {{{ int val = cctrue(1) ? 0xff : 0;
15369: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
15370: if (val) { m68k_incpc(2) ; return 4+2; }
15371: }}}m68k_incpc(2);
15372: return 4;
15373: }
15374: unsigned long REGPARAM2 CPUFUNC(op_51c8_0)(uae_u32 opcode) /* DBcc */
15375: {
15376: uae_u32 srcreg = (opcode & 7);
15377: OpcodeFamily = 58; CurrentInstrCycles = 12;
15378: {{ uae_s16 src = m68k_dreg(regs, srcreg);
15379: { uae_s16 offs = get_iword(2);
15380: if (!cctrue(1)) {
15381: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
15382: if (src) {
15383: m68k_incpc((uae_s32)offs + 2);
15384: return 10;
15385: } else {
15386: m68k_incpc(4);
15387: return 14;
15388: }
15389: }
15390: }}}m68k_incpc(4);
15391: endlabel1000: ;
15392: return 12;
15393: }
15394: unsigned long REGPARAM2 CPUFUNC(op_51d0_0)(uae_u32 opcode) /* Scc */
15395: {
15396: uae_u32 srcreg = (opcode & 7);
15397: OpcodeFamily = 59; CurrentInstrCycles = 12;
15398: {{ uaecptr srca = m68k_areg(regs, srcreg);
15399: { int val = cctrue(1) ? 0xff : 0;
15400: put_byte(srca,val);
15401: }}}m68k_incpc(2);
15402: return 12;
15403: }
15404: unsigned long REGPARAM2 CPUFUNC(op_51d8_0)(uae_u32 opcode) /* Scc */
15405: {
15406: uae_u32 srcreg = (opcode & 7);
15407: OpcodeFamily = 59; CurrentInstrCycles = 12;
15408: {{ uaecptr srca = m68k_areg(regs, srcreg);
15409: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
15410: { int val = cctrue(1) ? 0xff : 0;
15411: put_byte(srca,val);
15412: }}}m68k_incpc(2);
15413: return 12;
15414: }
15415: unsigned long REGPARAM2 CPUFUNC(op_51e0_0)(uae_u32 opcode) /* Scc */
15416: {
15417: uae_u32 srcreg = (opcode & 7);
15418: OpcodeFamily = 59; CurrentInstrCycles = 14;
15419: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
15420: m68k_areg (regs, srcreg) = srca;
15421: { int val = cctrue(1) ? 0xff : 0;
15422: put_byte(srca,val);
15423: }}}m68k_incpc(2);
15424: return 14;
15425: }
15426: unsigned long REGPARAM2 CPUFUNC(op_51e8_0)(uae_u32 opcode) /* Scc */
15427: {
15428: uae_u32 srcreg = (opcode & 7);
15429: OpcodeFamily = 59; CurrentInstrCycles = 16;
15430: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
15431: { int val = cctrue(1) ? 0xff : 0;
15432: put_byte(srca,val);
15433: }}}m68k_incpc(4);
15434: return 16;
15435: }
15436: unsigned long REGPARAM2 CPUFUNC(op_51f0_0)(uae_u32 opcode) /* Scc */
15437: {
15438: uae_u32 srcreg = (opcode & 7);
15439: OpcodeFamily = 59; CurrentInstrCycles = 18;
15440: {{m68k_incpc(2);
15441: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
15442: BusCyclePenalty += 2;
15443: { int val = cctrue(1) ? 0xff : 0;
15444: put_byte(srca,val);
15445: }}}}return 18;
15446: }
15447: unsigned long REGPARAM2 CPUFUNC(op_51f8_0)(uae_u32 opcode) /* Scc */
15448: {
15449: OpcodeFamily = 59; CurrentInstrCycles = 16;
15450: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
15451: { int val = cctrue(1) ? 0xff : 0;
15452: put_byte(srca,val);
15453: }}}m68k_incpc(4);
15454: return 16;
15455: }
15456: unsigned long REGPARAM2 CPUFUNC(op_51f9_0)(uae_u32 opcode) /* Scc */
15457: {
15458: OpcodeFamily = 59; CurrentInstrCycles = 20;
15459: {{ uaecptr srca = get_ilong(2);
15460: { int val = cctrue(1) ? 0xff : 0;
15461: put_byte(srca,val);
15462: }}}m68k_incpc(6);
15463: return 20;
15464: }
15465: unsigned long REGPARAM2 CPUFUNC(op_51fa_0)(uae_u32 opcode) /* TRAPcc */
15466: {
15467: OpcodeFamily = 102; CurrentInstrCycles = 8;
15468: {{ uae_s16 dummy = get_iword(2);
15469: if (cctrue(1)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1008; }
15470: }}m68k_incpc(4);
15471: endlabel1008: ;
15472: return 8;
15473: }
15474: unsigned long REGPARAM2 CPUFUNC(op_51fb_0)(uae_u32 opcode) /* TRAPcc */
15475: {
15476: OpcodeFamily = 102; CurrentInstrCycles = 12;
15477: {{ uae_s32 dummy = get_ilong(2);
15478: if (cctrue(1)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1009; }
15479: }}m68k_incpc(6);
15480: endlabel1009: ;
15481: return 12;
15482: }
15483: unsigned long REGPARAM2 CPUFUNC(op_51fc_0)(uae_u32 opcode) /* TRAPcc */
15484: {
15485: OpcodeFamily = 102; CurrentInstrCycles = 4;
15486: { if (cctrue(1)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1010; }
15487: }m68k_incpc(2);
15488: endlabel1010: ;
15489: return 4;
15490: }
15491: unsigned long REGPARAM2 CPUFUNC(op_52c0_0)(uae_u32 opcode) /* Scc */
15492: {
15493: uae_u32 srcreg = (opcode & 7);
15494: OpcodeFamily = 59; CurrentInstrCycles = 4;
15495: {{{ int val = cctrue(2) ? 0xff : 0;
15496: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
15497: if (val) { m68k_incpc(2) ; return 4+2; }
15498: }}}m68k_incpc(2);
15499: return 4;
15500: }
15501: unsigned long REGPARAM2 CPUFUNC(op_52c8_0)(uae_u32 opcode) /* DBcc */
15502: {
15503: uae_u32 srcreg = (opcode & 7);
15504: OpcodeFamily = 58; CurrentInstrCycles = 12;
15505: {{ uae_s16 src = m68k_dreg(regs, srcreg);
15506: { uae_s16 offs = get_iword(2);
15507: if (!cctrue(2)) {
15508: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
15509: if (src) {
15510: m68k_incpc((uae_s32)offs + 2);
15511: return 10;
15512: } else {
15513: m68k_incpc(4);
15514: return 14;
15515: }
15516: }
15517: }}}m68k_incpc(4);
15518: endlabel1012: ;
15519: return 12;
15520: }
15521: unsigned long REGPARAM2 CPUFUNC(op_52d0_0)(uae_u32 opcode) /* Scc */
15522: {
15523: uae_u32 srcreg = (opcode & 7);
15524: OpcodeFamily = 59; CurrentInstrCycles = 12;
15525: {{ uaecptr srca = m68k_areg(regs, srcreg);
15526: { int val = cctrue(2) ? 0xff : 0;
15527: put_byte(srca,val);
15528: }}}m68k_incpc(2);
15529: return 12;
15530: }
15531: unsigned long REGPARAM2 CPUFUNC(op_52d8_0)(uae_u32 opcode) /* Scc */
15532: {
15533: uae_u32 srcreg = (opcode & 7);
15534: OpcodeFamily = 59; CurrentInstrCycles = 12;
15535: {{ uaecptr srca = m68k_areg(regs, srcreg);
15536: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
15537: { int val = cctrue(2) ? 0xff : 0;
15538: put_byte(srca,val);
15539: }}}m68k_incpc(2);
15540: return 12;
15541: }
15542: unsigned long REGPARAM2 CPUFUNC(op_52e0_0)(uae_u32 opcode) /* Scc */
15543: {
15544: uae_u32 srcreg = (opcode & 7);
15545: OpcodeFamily = 59; CurrentInstrCycles = 14;
15546: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
15547: m68k_areg (regs, srcreg) = srca;
15548: { int val = cctrue(2) ? 0xff : 0;
15549: put_byte(srca,val);
15550: }}}m68k_incpc(2);
15551: return 14;
15552: }
15553: unsigned long REGPARAM2 CPUFUNC(op_52e8_0)(uae_u32 opcode) /* Scc */
15554: {
15555: uae_u32 srcreg = (opcode & 7);
15556: OpcodeFamily = 59; CurrentInstrCycles = 16;
15557: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
15558: { int val = cctrue(2) ? 0xff : 0;
15559: put_byte(srca,val);
15560: }}}m68k_incpc(4);
15561: return 16;
15562: }
15563: unsigned long REGPARAM2 CPUFUNC(op_52f0_0)(uae_u32 opcode) /* Scc */
15564: {
15565: uae_u32 srcreg = (opcode & 7);
15566: OpcodeFamily = 59; CurrentInstrCycles = 18;
15567: {{m68k_incpc(2);
15568: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
15569: BusCyclePenalty += 2;
15570: { int val = cctrue(2) ? 0xff : 0;
15571: put_byte(srca,val);
15572: }}}}return 18;
15573: }
15574: unsigned long REGPARAM2 CPUFUNC(op_52f8_0)(uae_u32 opcode) /* Scc */
15575: {
15576: OpcodeFamily = 59; CurrentInstrCycles = 16;
15577: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
15578: { int val = cctrue(2) ? 0xff : 0;
15579: put_byte(srca,val);
15580: }}}m68k_incpc(4);
15581: return 16;
15582: }
15583: unsigned long REGPARAM2 CPUFUNC(op_52f9_0)(uae_u32 opcode) /* Scc */
15584: {
15585: OpcodeFamily = 59; CurrentInstrCycles = 20;
15586: {{ uaecptr srca = get_ilong(2);
15587: { int val = cctrue(2) ? 0xff : 0;
15588: put_byte(srca,val);
15589: }}}m68k_incpc(6);
15590: return 20;
15591: }
15592: unsigned long REGPARAM2 CPUFUNC(op_52fa_0)(uae_u32 opcode) /* TRAPcc */
15593: {
15594: OpcodeFamily = 102; CurrentInstrCycles = 8;
15595: {{ uae_s16 dummy = get_iword(2);
15596: if (cctrue(2)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1020; }
15597: }}m68k_incpc(4);
15598: endlabel1020: ;
15599: return 8;
15600: }
15601: unsigned long REGPARAM2 CPUFUNC(op_52fb_0)(uae_u32 opcode) /* TRAPcc */
15602: {
15603: OpcodeFamily = 102; CurrentInstrCycles = 12;
15604: {{ uae_s32 dummy = get_ilong(2);
15605: if (cctrue(2)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1021; }
15606: }}m68k_incpc(6);
15607: endlabel1021: ;
15608: return 12;
15609: }
15610: unsigned long REGPARAM2 CPUFUNC(op_52fc_0)(uae_u32 opcode) /* TRAPcc */
15611: {
15612: OpcodeFamily = 102; CurrentInstrCycles = 4;
15613: { if (cctrue(2)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1022; }
15614: }m68k_incpc(2);
15615: endlabel1022: ;
15616: return 4;
15617: }
15618: unsigned long REGPARAM2 CPUFUNC(op_53c0_0)(uae_u32 opcode) /* Scc */
15619: {
15620: uae_u32 srcreg = (opcode & 7);
15621: OpcodeFamily = 59; CurrentInstrCycles = 4;
15622: {{{ int val = cctrue(3) ? 0xff : 0;
15623: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
15624: if (val) { m68k_incpc(2) ; return 4+2; }
15625: }}}m68k_incpc(2);
15626: return 4;
15627: }
15628: unsigned long REGPARAM2 CPUFUNC(op_53c8_0)(uae_u32 opcode) /* DBcc */
15629: {
15630: uae_u32 srcreg = (opcode & 7);
15631: OpcodeFamily = 58; CurrentInstrCycles = 12;
15632: {{ uae_s16 src = m68k_dreg(regs, srcreg);
15633: { uae_s16 offs = get_iword(2);
15634: if (!cctrue(3)) {
15635: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
15636: if (src) {
15637: m68k_incpc((uae_s32)offs + 2);
15638: return 10;
15639: } else {
15640: m68k_incpc(4);
15641: return 14;
15642: }
15643: }
15644: }}}m68k_incpc(4);
15645: endlabel1024: ;
15646: return 12;
15647: }
15648: unsigned long REGPARAM2 CPUFUNC(op_53d0_0)(uae_u32 opcode) /* Scc */
15649: {
15650: uae_u32 srcreg = (opcode & 7);
15651: OpcodeFamily = 59; CurrentInstrCycles = 12;
15652: {{ uaecptr srca = m68k_areg(regs, srcreg);
15653: { int val = cctrue(3) ? 0xff : 0;
15654: put_byte(srca,val);
15655: }}}m68k_incpc(2);
15656: return 12;
15657: }
15658: unsigned long REGPARAM2 CPUFUNC(op_53d8_0)(uae_u32 opcode) /* Scc */
15659: {
15660: uae_u32 srcreg = (opcode & 7);
15661: OpcodeFamily = 59; CurrentInstrCycles = 12;
15662: {{ uaecptr srca = m68k_areg(regs, srcreg);
15663: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
15664: { int val = cctrue(3) ? 0xff : 0;
15665: put_byte(srca,val);
15666: }}}m68k_incpc(2);
15667: return 12;
15668: }
15669: unsigned long REGPARAM2 CPUFUNC(op_53e0_0)(uae_u32 opcode) /* Scc */
15670: {
15671: uae_u32 srcreg = (opcode & 7);
15672: OpcodeFamily = 59; CurrentInstrCycles = 14;
15673: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
15674: m68k_areg (regs, srcreg) = srca;
15675: { int val = cctrue(3) ? 0xff : 0;
15676: put_byte(srca,val);
15677: }}}m68k_incpc(2);
15678: return 14;
15679: }
15680: unsigned long REGPARAM2 CPUFUNC(op_53e8_0)(uae_u32 opcode) /* Scc */
15681: {
15682: uae_u32 srcreg = (opcode & 7);
15683: OpcodeFamily = 59; CurrentInstrCycles = 16;
15684: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
15685: { int val = cctrue(3) ? 0xff : 0;
15686: put_byte(srca,val);
15687: }}}m68k_incpc(4);
15688: return 16;
15689: }
15690: unsigned long REGPARAM2 CPUFUNC(op_53f0_0)(uae_u32 opcode) /* Scc */
15691: {
15692: uae_u32 srcreg = (opcode & 7);
15693: OpcodeFamily = 59; CurrentInstrCycles = 18;
15694: {{m68k_incpc(2);
15695: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
15696: BusCyclePenalty += 2;
15697: { int val = cctrue(3) ? 0xff : 0;
15698: put_byte(srca,val);
15699: }}}}return 18;
15700: }
15701: unsigned long REGPARAM2 CPUFUNC(op_53f8_0)(uae_u32 opcode) /* Scc */
15702: {
15703: OpcodeFamily = 59; CurrentInstrCycles = 16;
15704: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
15705: { int val = cctrue(3) ? 0xff : 0;
15706: put_byte(srca,val);
15707: }}}m68k_incpc(4);
15708: return 16;
15709: }
15710: unsigned long REGPARAM2 CPUFUNC(op_53f9_0)(uae_u32 opcode) /* Scc */
15711: {
15712: OpcodeFamily = 59; CurrentInstrCycles = 20;
15713: {{ uaecptr srca = get_ilong(2);
15714: { int val = cctrue(3) ? 0xff : 0;
15715: put_byte(srca,val);
15716: }}}m68k_incpc(6);
15717: return 20;
15718: }
15719: unsigned long REGPARAM2 CPUFUNC(op_53fa_0)(uae_u32 opcode) /* TRAPcc */
15720: {
15721: OpcodeFamily = 102; CurrentInstrCycles = 8;
15722: {{ uae_s16 dummy = get_iword(2);
15723: if (cctrue(3)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1032; }
15724: }}m68k_incpc(4);
15725: endlabel1032: ;
15726: return 8;
15727: }
15728: unsigned long REGPARAM2 CPUFUNC(op_53fb_0)(uae_u32 opcode) /* TRAPcc */
15729: {
15730: OpcodeFamily = 102; CurrentInstrCycles = 12;
15731: {{ uae_s32 dummy = get_ilong(2);
15732: if (cctrue(3)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1033; }
15733: }}m68k_incpc(6);
15734: endlabel1033: ;
15735: return 12;
15736: }
15737: unsigned long REGPARAM2 CPUFUNC(op_53fc_0)(uae_u32 opcode) /* TRAPcc */
15738: {
15739: OpcodeFamily = 102; CurrentInstrCycles = 4;
15740: { if (cctrue(3)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1034; }
15741: }m68k_incpc(2);
15742: endlabel1034: ;
15743: return 4;
15744: }
15745: unsigned long REGPARAM2 CPUFUNC(op_54c0_0)(uae_u32 opcode) /* Scc */
15746: {
15747: uae_u32 srcreg = (opcode & 7);
15748: OpcodeFamily = 59; CurrentInstrCycles = 4;
15749: {{{ int val = cctrue(4) ? 0xff : 0;
15750: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
15751: if (val) { m68k_incpc(2) ; return 4+2; }
15752: }}}m68k_incpc(2);
15753: return 4;
15754: }
15755: unsigned long REGPARAM2 CPUFUNC(op_54c8_0)(uae_u32 opcode) /* DBcc */
15756: {
15757: uae_u32 srcreg = (opcode & 7);
15758: OpcodeFamily = 58; CurrentInstrCycles = 12;
15759: {{ uae_s16 src = m68k_dreg(regs, srcreg);
15760: { uae_s16 offs = get_iword(2);
15761: if (!cctrue(4)) {
15762: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
15763: if (src) {
15764: m68k_incpc((uae_s32)offs + 2);
15765: return 10;
15766: } else {
15767: m68k_incpc(4);
15768: return 14;
15769: }
15770: }
15771: }}}m68k_incpc(4);
15772: endlabel1036: ;
15773: return 12;
15774: }
15775: unsigned long REGPARAM2 CPUFUNC(op_54d0_0)(uae_u32 opcode) /* Scc */
15776: {
15777: uae_u32 srcreg = (opcode & 7);
15778: OpcodeFamily = 59; CurrentInstrCycles = 12;
15779: {{ uaecptr srca = m68k_areg(regs, srcreg);
15780: { int val = cctrue(4) ? 0xff : 0;
15781: put_byte(srca,val);
15782: }}}m68k_incpc(2);
15783: return 12;
15784: }
15785: unsigned long REGPARAM2 CPUFUNC(op_54d8_0)(uae_u32 opcode) /* Scc */
15786: {
15787: uae_u32 srcreg = (opcode & 7);
15788: OpcodeFamily = 59; CurrentInstrCycles = 12;
15789: {{ uaecptr srca = m68k_areg(regs, srcreg);
15790: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
15791: { int val = cctrue(4) ? 0xff : 0;
15792: put_byte(srca,val);
15793: }}}m68k_incpc(2);
15794: return 12;
15795: }
15796: unsigned long REGPARAM2 CPUFUNC(op_54e0_0)(uae_u32 opcode) /* Scc */
15797: {
15798: uae_u32 srcreg = (opcode & 7);
15799: OpcodeFamily = 59; CurrentInstrCycles = 14;
15800: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
15801: m68k_areg (regs, srcreg) = srca;
15802: { int val = cctrue(4) ? 0xff : 0;
15803: put_byte(srca,val);
15804: }}}m68k_incpc(2);
15805: return 14;
15806: }
15807: unsigned long REGPARAM2 CPUFUNC(op_54e8_0)(uae_u32 opcode) /* Scc */
15808: {
15809: uae_u32 srcreg = (opcode & 7);
15810: OpcodeFamily = 59; CurrentInstrCycles = 16;
15811: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
15812: { int val = cctrue(4) ? 0xff : 0;
15813: put_byte(srca,val);
15814: }}}m68k_incpc(4);
15815: return 16;
15816: }
15817: unsigned long REGPARAM2 CPUFUNC(op_54f0_0)(uae_u32 opcode) /* Scc */
15818: {
15819: uae_u32 srcreg = (opcode & 7);
15820: OpcodeFamily = 59; CurrentInstrCycles = 18;
15821: {{m68k_incpc(2);
15822: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
15823: BusCyclePenalty += 2;
15824: { int val = cctrue(4) ? 0xff : 0;
15825: put_byte(srca,val);
15826: }}}}return 18;
15827: }
15828: unsigned long REGPARAM2 CPUFUNC(op_54f8_0)(uae_u32 opcode) /* Scc */
15829: {
15830: OpcodeFamily = 59; CurrentInstrCycles = 16;
15831: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
15832: { int val = cctrue(4) ? 0xff : 0;
15833: put_byte(srca,val);
15834: }}}m68k_incpc(4);
15835: return 16;
15836: }
15837: unsigned long REGPARAM2 CPUFUNC(op_54f9_0)(uae_u32 opcode) /* Scc */
15838: {
15839: OpcodeFamily = 59; CurrentInstrCycles = 20;
15840: {{ uaecptr srca = get_ilong(2);
15841: { int val = cctrue(4) ? 0xff : 0;
15842: put_byte(srca,val);
15843: }}}m68k_incpc(6);
15844: return 20;
15845: }
15846: unsigned long REGPARAM2 CPUFUNC(op_54fa_0)(uae_u32 opcode) /* TRAPcc */
15847: {
15848: OpcodeFamily = 102; CurrentInstrCycles = 8;
15849: {{ uae_s16 dummy = get_iword(2);
15850: if (cctrue(4)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1044; }
15851: }}m68k_incpc(4);
15852: endlabel1044: ;
15853: return 8;
15854: }
15855: unsigned long REGPARAM2 CPUFUNC(op_54fb_0)(uae_u32 opcode) /* TRAPcc */
15856: {
15857: OpcodeFamily = 102; CurrentInstrCycles = 12;
15858: {{ uae_s32 dummy = get_ilong(2);
15859: if (cctrue(4)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1045; }
15860: }}m68k_incpc(6);
15861: endlabel1045: ;
15862: return 12;
15863: }
15864: unsigned long REGPARAM2 CPUFUNC(op_54fc_0)(uae_u32 opcode) /* TRAPcc */
15865: {
15866: OpcodeFamily = 102; CurrentInstrCycles = 4;
15867: { if (cctrue(4)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1046; }
15868: }m68k_incpc(2);
15869: endlabel1046: ;
15870: return 4;
15871: }
15872: unsigned long REGPARAM2 CPUFUNC(op_55c0_0)(uae_u32 opcode) /* Scc */
15873: {
15874: uae_u32 srcreg = (opcode & 7);
15875: OpcodeFamily = 59; CurrentInstrCycles = 4;
15876: {{{ int val = cctrue(5) ? 0xff : 0;
15877: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
15878: if (val) { m68k_incpc(2) ; return 4+2; }
15879: }}}m68k_incpc(2);
15880: return 4;
15881: }
15882: unsigned long REGPARAM2 CPUFUNC(op_55c8_0)(uae_u32 opcode) /* DBcc */
15883: {
15884: uae_u32 srcreg = (opcode & 7);
15885: OpcodeFamily = 58; CurrentInstrCycles = 12;
15886: {{ uae_s16 src = m68k_dreg(regs, srcreg);
15887: { uae_s16 offs = get_iword(2);
15888: if (!cctrue(5)) {
15889: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
15890: if (src) {
15891: m68k_incpc((uae_s32)offs + 2);
15892: return 10;
15893: } else {
15894: m68k_incpc(4);
15895: return 14;
15896: }
15897: }
15898: }}}m68k_incpc(4);
15899: endlabel1048: ;
15900: return 12;
15901: }
15902: unsigned long REGPARAM2 CPUFUNC(op_55d0_0)(uae_u32 opcode) /* Scc */
15903: {
15904: uae_u32 srcreg = (opcode & 7);
15905: OpcodeFamily = 59; CurrentInstrCycles = 12;
15906: {{ uaecptr srca = m68k_areg(regs, srcreg);
15907: { int val = cctrue(5) ? 0xff : 0;
15908: put_byte(srca,val);
15909: }}}m68k_incpc(2);
15910: return 12;
15911: }
15912: unsigned long REGPARAM2 CPUFUNC(op_55d8_0)(uae_u32 opcode) /* Scc */
15913: {
15914: uae_u32 srcreg = (opcode & 7);
15915: OpcodeFamily = 59; CurrentInstrCycles = 12;
15916: {{ uaecptr srca = m68k_areg(regs, srcreg);
15917: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
15918: { int val = cctrue(5) ? 0xff : 0;
15919: put_byte(srca,val);
15920: }}}m68k_incpc(2);
15921: return 12;
15922: }
15923: unsigned long REGPARAM2 CPUFUNC(op_55e0_0)(uae_u32 opcode) /* Scc */
15924: {
15925: uae_u32 srcreg = (opcode & 7);
15926: OpcodeFamily = 59; CurrentInstrCycles = 14;
15927: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
15928: m68k_areg (regs, srcreg) = srca;
15929: { int val = cctrue(5) ? 0xff : 0;
15930: put_byte(srca,val);
15931: }}}m68k_incpc(2);
15932: return 14;
15933: }
15934: unsigned long REGPARAM2 CPUFUNC(op_55e8_0)(uae_u32 opcode) /* Scc */
15935: {
15936: uae_u32 srcreg = (opcode & 7);
15937: OpcodeFamily = 59; CurrentInstrCycles = 16;
15938: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
15939: { int val = cctrue(5) ? 0xff : 0;
15940: put_byte(srca,val);
15941: }}}m68k_incpc(4);
15942: return 16;
15943: }
15944: unsigned long REGPARAM2 CPUFUNC(op_55f0_0)(uae_u32 opcode) /* Scc */
15945: {
15946: uae_u32 srcreg = (opcode & 7);
15947: OpcodeFamily = 59; CurrentInstrCycles = 18;
15948: {{m68k_incpc(2);
15949: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
15950: BusCyclePenalty += 2;
15951: { int val = cctrue(5) ? 0xff : 0;
15952: put_byte(srca,val);
15953: }}}}return 18;
15954: }
15955: unsigned long REGPARAM2 CPUFUNC(op_55f8_0)(uae_u32 opcode) /* Scc */
15956: {
15957: OpcodeFamily = 59; CurrentInstrCycles = 16;
15958: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
15959: { int val = cctrue(5) ? 0xff : 0;
15960: put_byte(srca,val);
15961: }}}m68k_incpc(4);
15962: return 16;
15963: }
15964: unsigned long REGPARAM2 CPUFUNC(op_55f9_0)(uae_u32 opcode) /* Scc */
15965: {
15966: OpcodeFamily = 59; CurrentInstrCycles = 20;
15967: {{ uaecptr srca = get_ilong(2);
15968: { int val = cctrue(5) ? 0xff : 0;
15969: put_byte(srca,val);
15970: }}}m68k_incpc(6);
15971: return 20;
15972: }
15973: unsigned long REGPARAM2 CPUFUNC(op_55fa_0)(uae_u32 opcode) /* TRAPcc */
15974: {
15975: OpcodeFamily = 102; CurrentInstrCycles = 8;
15976: {{ uae_s16 dummy = get_iword(2);
15977: if (cctrue(5)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1056; }
15978: }}m68k_incpc(4);
15979: endlabel1056: ;
15980: return 8;
15981: }
15982: unsigned long REGPARAM2 CPUFUNC(op_55fb_0)(uae_u32 opcode) /* TRAPcc */
15983: {
15984: OpcodeFamily = 102; CurrentInstrCycles = 12;
15985: {{ uae_s32 dummy = get_ilong(2);
15986: if (cctrue(5)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1057; }
15987: }}m68k_incpc(6);
15988: endlabel1057: ;
15989: return 12;
15990: }
15991: unsigned long REGPARAM2 CPUFUNC(op_55fc_0)(uae_u32 opcode) /* TRAPcc */
15992: {
15993: OpcodeFamily = 102; CurrentInstrCycles = 4;
15994: { if (cctrue(5)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1058; }
15995: }m68k_incpc(2);
15996: endlabel1058: ;
15997: return 4;
15998: }
15999: unsigned long REGPARAM2 CPUFUNC(op_56c0_0)(uae_u32 opcode) /* Scc */
16000: {
16001: uae_u32 srcreg = (opcode & 7);
16002: OpcodeFamily = 59; CurrentInstrCycles = 4;
16003: {{{ int val = cctrue(6) ? 0xff : 0;
16004: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
16005: if (val) { m68k_incpc(2) ; return 4+2; }
16006: }}}m68k_incpc(2);
16007: return 4;
16008: }
16009: unsigned long REGPARAM2 CPUFUNC(op_56c8_0)(uae_u32 opcode) /* DBcc */
16010: {
16011: uae_u32 srcreg = (opcode & 7);
16012: OpcodeFamily = 58; CurrentInstrCycles = 12;
16013: {{ uae_s16 src = m68k_dreg(regs, srcreg);
16014: { uae_s16 offs = get_iword(2);
16015: if (!cctrue(6)) {
16016: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
16017: if (src) {
16018: m68k_incpc((uae_s32)offs + 2);
16019: return 10;
16020: } else {
16021: m68k_incpc(4);
16022: return 14;
16023: }
16024: }
16025: }}}m68k_incpc(4);
16026: endlabel1060: ;
16027: return 12;
16028: }
16029: unsigned long REGPARAM2 CPUFUNC(op_56d0_0)(uae_u32 opcode) /* Scc */
16030: {
16031: uae_u32 srcreg = (opcode & 7);
16032: OpcodeFamily = 59; CurrentInstrCycles = 12;
16033: {{ uaecptr srca = m68k_areg(regs, srcreg);
16034: { int val = cctrue(6) ? 0xff : 0;
16035: put_byte(srca,val);
16036: }}}m68k_incpc(2);
16037: return 12;
16038: }
16039: unsigned long REGPARAM2 CPUFUNC(op_56d8_0)(uae_u32 opcode) /* Scc */
16040: {
16041: uae_u32 srcreg = (opcode & 7);
16042: OpcodeFamily = 59; CurrentInstrCycles = 12;
16043: {{ uaecptr srca = m68k_areg(regs, srcreg);
16044: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
16045: { int val = cctrue(6) ? 0xff : 0;
16046: put_byte(srca,val);
16047: }}}m68k_incpc(2);
16048: return 12;
16049: }
16050: unsigned long REGPARAM2 CPUFUNC(op_56e0_0)(uae_u32 opcode) /* Scc */
16051: {
16052: uae_u32 srcreg = (opcode & 7);
16053: OpcodeFamily = 59; CurrentInstrCycles = 14;
16054: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
16055: m68k_areg (regs, srcreg) = srca;
16056: { int val = cctrue(6) ? 0xff : 0;
16057: put_byte(srca,val);
16058: }}}m68k_incpc(2);
16059: return 14;
16060: }
16061: unsigned long REGPARAM2 CPUFUNC(op_56e8_0)(uae_u32 opcode) /* Scc */
16062: {
16063: uae_u32 srcreg = (opcode & 7);
16064: OpcodeFamily = 59; CurrentInstrCycles = 16;
16065: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
16066: { int val = cctrue(6) ? 0xff : 0;
16067: put_byte(srca,val);
16068: }}}m68k_incpc(4);
16069: return 16;
16070: }
16071: unsigned long REGPARAM2 CPUFUNC(op_56f0_0)(uae_u32 opcode) /* Scc */
16072: {
16073: uae_u32 srcreg = (opcode & 7);
16074: OpcodeFamily = 59; CurrentInstrCycles = 18;
16075: {{m68k_incpc(2);
16076: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
16077: BusCyclePenalty += 2;
16078: { int val = cctrue(6) ? 0xff : 0;
16079: put_byte(srca,val);
16080: }}}}return 18;
16081: }
16082: unsigned long REGPARAM2 CPUFUNC(op_56f8_0)(uae_u32 opcode) /* Scc */
16083: {
16084: OpcodeFamily = 59; CurrentInstrCycles = 16;
16085: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
16086: { int val = cctrue(6) ? 0xff : 0;
16087: put_byte(srca,val);
16088: }}}m68k_incpc(4);
16089: return 16;
16090: }
16091: unsigned long REGPARAM2 CPUFUNC(op_56f9_0)(uae_u32 opcode) /* Scc */
16092: {
16093: OpcodeFamily = 59; CurrentInstrCycles = 20;
16094: {{ uaecptr srca = get_ilong(2);
16095: { int val = cctrue(6) ? 0xff : 0;
16096: put_byte(srca,val);
16097: }}}m68k_incpc(6);
16098: return 20;
16099: }
16100: unsigned long REGPARAM2 CPUFUNC(op_56fa_0)(uae_u32 opcode) /* TRAPcc */
16101: {
16102: OpcodeFamily = 102; CurrentInstrCycles = 8;
16103: {{ uae_s16 dummy = get_iword(2);
16104: if (cctrue(6)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1068; }
16105: }}m68k_incpc(4);
16106: endlabel1068: ;
16107: return 8;
16108: }
16109: unsigned long REGPARAM2 CPUFUNC(op_56fb_0)(uae_u32 opcode) /* TRAPcc */
16110: {
16111: OpcodeFamily = 102; CurrentInstrCycles = 12;
16112: {{ uae_s32 dummy = get_ilong(2);
16113: if (cctrue(6)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1069; }
16114: }}m68k_incpc(6);
16115: endlabel1069: ;
16116: return 12;
16117: }
16118: unsigned long REGPARAM2 CPUFUNC(op_56fc_0)(uae_u32 opcode) /* TRAPcc */
16119: {
16120: OpcodeFamily = 102; CurrentInstrCycles = 4;
16121: { if (cctrue(6)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1070; }
16122: }m68k_incpc(2);
16123: endlabel1070: ;
16124: return 4;
16125: }
16126: unsigned long REGPARAM2 CPUFUNC(op_57c0_0)(uae_u32 opcode) /* Scc */
16127: {
16128: uae_u32 srcreg = (opcode & 7);
16129: OpcodeFamily = 59; CurrentInstrCycles = 4;
16130: {{{ int val = cctrue(7) ? 0xff : 0;
16131: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
16132: if (val) { m68k_incpc(2) ; return 4+2; }
16133: }}}m68k_incpc(2);
16134: return 4;
16135: }
16136: unsigned long REGPARAM2 CPUFUNC(op_57c8_0)(uae_u32 opcode) /* DBcc */
16137: {
16138: uae_u32 srcreg = (opcode & 7);
16139: OpcodeFamily = 58; CurrentInstrCycles = 12;
16140: {{ uae_s16 src = m68k_dreg(regs, srcreg);
16141: { uae_s16 offs = get_iword(2);
16142: if (!cctrue(7)) {
16143: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
16144: if (src) {
16145: m68k_incpc((uae_s32)offs + 2);
16146: return 10;
16147: } else {
16148: m68k_incpc(4);
16149: return 14;
16150: }
16151: }
16152: }}}m68k_incpc(4);
16153: endlabel1072: ;
16154: return 12;
16155: }
16156: unsigned long REGPARAM2 CPUFUNC(op_57d0_0)(uae_u32 opcode) /* Scc */
16157: {
16158: uae_u32 srcreg = (opcode & 7);
16159: OpcodeFamily = 59; CurrentInstrCycles = 12;
16160: {{ uaecptr srca = m68k_areg(regs, srcreg);
16161: { int val = cctrue(7) ? 0xff : 0;
16162: put_byte(srca,val);
16163: }}}m68k_incpc(2);
16164: return 12;
16165: }
16166: unsigned long REGPARAM2 CPUFUNC(op_57d8_0)(uae_u32 opcode) /* Scc */
16167: {
16168: uae_u32 srcreg = (opcode & 7);
16169: OpcodeFamily = 59; CurrentInstrCycles = 12;
16170: {{ uaecptr srca = m68k_areg(regs, srcreg);
16171: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
16172: { int val = cctrue(7) ? 0xff : 0;
16173: put_byte(srca,val);
16174: }}}m68k_incpc(2);
16175: return 12;
16176: }
16177: unsigned long REGPARAM2 CPUFUNC(op_57e0_0)(uae_u32 opcode) /* Scc */
16178: {
16179: uae_u32 srcreg = (opcode & 7);
16180: OpcodeFamily = 59; CurrentInstrCycles = 14;
16181: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
16182: m68k_areg (regs, srcreg) = srca;
16183: { int val = cctrue(7) ? 0xff : 0;
16184: put_byte(srca,val);
16185: }}}m68k_incpc(2);
16186: return 14;
16187: }
16188: unsigned long REGPARAM2 CPUFUNC(op_57e8_0)(uae_u32 opcode) /* Scc */
16189: {
16190: uae_u32 srcreg = (opcode & 7);
16191: OpcodeFamily = 59; CurrentInstrCycles = 16;
16192: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
16193: { int val = cctrue(7) ? 0xff : 0;
16194: put_byte(srca,val);
16195: }}}m68k_incpc(4);
16196: return 16;
16197: }
16198: unsigned long REGPARAM2 CPUFUNC(op_57f0_0)(uae_u32 opcode) /* Scc */
16199: {
16200: uae_u32 srcreg = (opcode & 7);
16201: OpcodeFamily = 59; CurrentInstrCycles = 18;
16202: {{m68k_incpc(2);
16203: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
16204: BusCyclePenalty += 2;
16205: { int val = cctrue(7) ? 0xff : 0;
16206: put_byte(srca,val);
16207: }}}}return 18;
16208: }
16209: unsigned long REGPARAM2 CPUFUNC(op_57f8_0)(uae_u32 opcode) /* Scc */
16210: {
16211: OpcodeFamily = 59; CurrentInstrCycles = 16;
16212: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
16213: { int val = cctrue(7) ? 0xff : 0;
16214: put_byte(srca,val);
16215: }}}m68k_incpc(4);
16216: return 16;
16217: }
16218: unsigned long REGPARAM2 CPUFUNC(op_57f9_0)(uae_u32 opcode) /* Scc */
16219: {
16220: OpcodeFamily = 59; CurrentInstrCycles = 20;
16221: {{ uaecptr srca = get_ilong(2);
16222: { int val = cctrue(7) ? 0xff : 0;
16223: put_byte(srca,val);
16224: }}}m68k_incpc(6);
16225: return 20;
16226: }
16227: unsigned long REGPARAM2 CPUFUNC(op_57fa_0)(uae_u32 opcode) /* TRAPcc */
16228: {
16229: OpcodeFamily = 102; CurrentInstrCycles = 8;
16230: {{ uae_s16 dummy = get_iword(2);
16231: if (cctrue(7)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1080; }
16232: }}m68k_incpc(4);
16233: endlabel1080: ;
16234: return 8;
16235: }
16236: unsigned long REGPARAM2 CPUFUNC(op_57fb_0)(uae_u32 opcode) /* TRAPcc */
16237: {
16238: OpcodeFamily = 102; CurrentInstrCycles = 12;
16239: {{ uae_s32 dummy = get_ilong(2);
16240: if (cctrue(7)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1081; }
16241: }}m68k_incpc(6);
16242: endlabel1081: ;
16243: return 12;
16244: }
16245: unsigned long REGPARAM2 CPUFUNC(op_57fc_0)(uae_u32 opcode) /* TRAPcc */
16246: {
16247: OpcodeFamily = 102; CurrentInstrCycles = 4;
16248: { if (cctrue(7)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1082; }
16249: }m68k_incpc(2);
16250: endlabel1082: ;
16251: return 4;
16252: }
16253: unsigned long REGPARAM2 CPUFUNC(op_58c0_0)(uae_u32 opcode) /* Scc */
16254: {
16255: uae_u32 srcreg = (opcode & 7);
16256: OpcodeFamily = 59; CurrentInstrCycles = 4;
16257: {{{ int val = cctrue(8) ? 0xff : 0;
16258: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
16259: if (val) { m68k_incpc(2) ; return 4+2; }
16260: }}}m68k_incpc(2);
16261: return 4;
16262: }
16263: unsigned long REGPARAM2 CPUFUNC(op_58c8_0)(uae_u32 opcode) /* DBcc */
16264: {
16265: uae_u32 srcreg = (opcode & 7);
16266: OpcodeFamily = 58; CurrentInstrCycles = 12;
16267: {{ uae_s16 src = m68k_dreg(regs, srcreg);
16268: { uae_s16 offs = get_iword(2);
16269: if (!cctrue(8)) {
16270: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
16271: if (src) {
16272: m68k_incpc((uae_s32)offs + 2);
16273: return 10;
16274: } else {
16275: m68k_incpc(4);
16276: return 14;
16277: }
16278: }
16279: }}}m68k_incpc(4);
16280: endlabel1084: ;
16281: return 12;
16282: }
16283: unsigned long REGPARAM2 CPUFUNC(op_58d0_0)(uae_u32 opcode) /* Scc */
16284: {
16285: uae_u32 srcreg = (opcode & 7);
16286: OpcodeFamily = 59; CurrentInstrCycles = 12;
16287: {{ uaecptr srca = m68k_areg(regs, srcreg);
16288: { int val = cctrue(8) ? 0xff : 0;
16289: put_byte(srca,val);
16290: }}}m68k_incpc(2);
16291: return 12;
16292: }
16293: unsigned long REGPARAM2 CPUFUNC(op_58d8_0)(uae_u32 opcode) /* Scc */
16294: {
16295: uae_u32 srcreg = (opcode & 7);
16296: OpcodeFamily = 59; CurrentInstrCycles = 12;
16297: {{ uaecptr srca = m68k_areg(regs, srcreg);
16298: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
16299: { int val = cctrue(8) ? 0xff : 0;
16300: put_byte(srca,val);
16301: }}}m68k_incpc(2);
16302: return 12;
16303: }
16304: unsigned long REGPARAM2 CPUFUNC(op_58e0_0)(uae_u32 opcode) /* Scc */
16305: {
16306: uae_u32 srcreg = (opcode & 7);
16307: OpcodeFamily = 59; CurrentInstrCycles = 14;
16308: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
16309: m68k_areg (regs, srcreg) = srca;
16310: { int val = cctrue(8) ? 0xff : 0;
16311: put_byte(srca,val);
16312: }}}m68k_incpc(2);
16313: return 14;
16314: }
16315: unsigned long REGPARAM2 CPUFUNC(op_58e8_0)(uae_u32 opcode) /* Scc */
16316: {
16317: uae_u32 srcreg = (opcode & 7);
16318: OpcodeFamily = 59; CurrentInstrCycles = 16;
16319: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
16320: { int val = cctrue(8) ? 0xff : 0;
16321: put_byte(srca,val);
16322: }}}m68k_incpc(4);
16323: return 16;
16324: }
16325: unsigned long REGPARAM2 CPUFUNC(op_58f0_0)(uae_u32 opcode) /* Scc */
16326: {
16327: uae_u32 srcreg = (opcode & 7);
16328: OpcodeFamily = 59; CurrentInstrCycles = 18;
16329: {{m68k_incpc(2);
16330: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
16331: BusCyclePenalty += 2;
16332: { int val = cctrue(8) ? 0xff : 0;
16333: put_byte(srca,val);
16334: }}}}return 18;
16335: }
16336: unsigned long REGPARAM2 CPUFUNC(op_58f8_0)(uae_u32 opcode) /* Scc */
16337: {
16338: OpcodeFamily = 59; CurrentInstrCycles = 16;
16339: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
16340: { int val = cctrue(8) ? 0xff : 0;
16341: put_byte(srca,val);
16342: }}}m68k_incpc(4);
16343: return 16;
16344: }
16345: unsigned long REGPARAM2 CPUFUNC(op_58f9_0)(uae_u32 opcode) /* Scc */
16346: {
16347: OpcodeFamily = 59; CurrentInstrCycles = 20;
16348: {{ uaecptr srca = get_ilong(2);
16349: { int val = cctrue(8) ? 0xff : 0;
16350: put_byte(srca,val);
16351: }}}m68k_incpc(6);
16352: return 20;
16353: }
16354: unsigned long REGPARAM2 CPUFUNC(op_58fa_0)(uae_u32 opcode) /* TRAPcc */
16355: {
16356: OpcodeFamily = 102; CurrentInstrCycles = 8;
16357: {{ uae_s16 dummy = get_iword(2);
16358: if (cctrue(8)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1092; }
16359: }}m68k_incpc(4);
16360: endlabel1092: ;
16361: return 8;
16362: }
16363: unsigned long REGPARAM2 CPUFUNC(op_58fb_0)(uae_u32 opcode) /* TRAPcc */
16364: {
16365: OpcodeFamily = 102; CurrentInstrCycles = 12;
16366: {{ uae_s32 dummy = get_ilong(2);
16367: if (cctrue(8)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1093; }
16368: }}m68k_incpc(6);
16369: endlabel1093: ;
16370: return 12;
16371: }
16372: unsigned long REGPARAM2 CPUFUNC(op_58fc_0)(uae_u32 opcode) /* TRAPcc */
16373: {
16374: OpcodeFamily = 102; CurrentInstrCycles = 4;
16375: { if (cctrue(8)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1094; }
16376: }m68k_incpc(2);
16377: endlabel1094: ;
16378: return 4;
16379: }
16380: unsigned long REGPARAM2 CPUFUNC(op_59c0_0)(uae_u32 opcode) /* Scc */
16381: {
16382: uae_u32 srcreg = (opcode & 7);
16383: OpcodeFamily = 59; CurrentInstrCycles = 4;
16384: {{{ int val = cctrue(9) ? 0xff : 0;
16385: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
16386: if (val) { m68k_incpc(2) ; return 4+2; }
16387: }}}m68k_incpc(2);
16388: return 4;
16389: }
16390: unsigned long REGPARAM2 CPUFUNC(op_59c8_0)(uae_u32 opcode) /* DBcc */
16391: {
16392: uae_u32 srcreg = (opcode & 7);
16393: OpcodeFamily = 58; CurrentInstrCycles = 12;
16394: {{ uae_s16 src = m68k_dreg(regs, srcreg);
16395: { uae_s16 offs = get_iword(2);
16396: if (!cctrue(9)) {
16397: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
16398: if (src) {
16399: m68k_incpc((uae_s32)offs + 2);
16400: return 10;
16401: } else {
16402: m68k_incpc(4);
16403: return 14;
16404: }
16405: }
16406: }}}m68k_incpc(4);
16407: endlabel1096: ;
16408: return 12;
16409: }
16410: unsigned long REGPARAM2 CPUFUNC(op_59d0_0)(uae_u32 opcode) /* Scc */
16411: {
16412: uae_u32 srcreg = (opcode & 7);
16413: OpcodeFamily = 59; CurrentInstrCycles = 12;
16414: {{ uaecptr srca = m68k_areg(regs, srcreg);
16415: { int val = cctrue(9) ? 0xff : 0;
16416: put_byte(srca,val);
16417: }}}m68k_incpc(2);
16418: return 12;
16419: }
16420: unsigned long REGPARAM2 CPUFUNC(op_59d8_0)(uae_u32 opcode) /* Scc */
16421: {
16422: uae_u32 srcreg = (opcode & 7);
16423: OpcodeFamily = 59; CurrentInstrCycles = 12;
16424: {{ uaecptr srca = m68k_areg(regs, srcreg);
16425: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
16426: { int val = cctrue(9) ? 0xff : 0;
16427: put_byte(srca,val);
16428: }}}m68k_incpc(2);
16429: return 12;
16430: }
16431: unsigned long REGPARAM2 CPUFUNC(op_59e0_0)(uae_u32 opcode) /* Scc */
16432: {
16433: uae_u32 srcreg = (opcode & 7);
16434: OpcodeFamily = 59; CurrentInstrCycles = 14;
16435: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
16436: m68k_areg (regs, srcreg) = srca;
16437: { int val = cctrue(9) ? 0xff : 0;
16438: put_byte(srca,val);
16439: }}}m68k_incpc(2);
16440: return 14;
16441: }
16442: unsigned long REGPARAM2 CPUFUNC(op_59e8_0)(uae_u32 opcode) /* Scc */
16443: {
16444: uae_u32 srcreg = (opcode & 7);
16445: OpcodeFamily = 59; CurrentInstrCycles = 16;
16446: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
16447: { int val = cctrue(9) ? 0xff : 0;
16448: put_byte(srca,val);
16449: }}}m68k_incpc(4);
16450: return 16;
16451: }
16452: unsigned long REGPARAM2 CPUFUNC(op_59f0_0)(uae_u32 opcode) /* Scc */
16453: {
16454: uae_u32 srcreg = (opcode & 7);
16455: OpcodeFamily = 59; CurrentInstrCycles = 18;
16456: {{m68k_incpc(2);
16457: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
16458: BusCyclePenalty += 2;
16459: { int val = cctrue(9) ? 0xff : 0;
16460: put_byte(srca,val);
16461: }}}}return 18;
16462: }
16463: unsigned long REGPARAM2 CPUFUNC(op_59f8_0)(uae_u32 opcode) /* Scc */
16464: {
16465: OpcodeFamily = 59; CurrentInstrCycles = 16;
16466: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
16467: { int val = cctrue(9) ? 0xff : 0;
16468: put_byte(srca,val);
16469: }}}m68k_incpc(4);
16470: return 16;
16471: }
16472: unsigned long REGPARAM2 CPUFUNC(op_59f9_0)(uae_u32 opcode) /* Scc */
16473: {
16474: OpcodeFamily = 59; CurrentInstrCycles = 20;
16475: {{ uaecptr srca = get_ilong(2);
16476: { int val = cctrue(9) ? 0xff : 0;
16477: put_byte(srca,val);
16478: }}}m68k_incpc(6);
16479: return 20;
16480: }
16481: unsigned long REGPARAM2 CPUFUNC(op_59fa_0)(uae_u32 opcode) /* TRAPcc */
16482: {
16483: OpcodeFamily = 102; CurrentInstrCycles = 8;
16484: {{ uae_s16 dummy = get_iword(2);
16485: if (cctrue(9)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1104; }
16486: }}m68k_incpc(4);
16487: endlabel1104: ;
16488: return 8;
16489: }
16490: unsigned long REGPARAM2 CPUFUNC(op_59fb_0)(uae_u32 opcode) /* TRAPcc */
16491: {
16492: OpcodeFamily = 102; CurrentInstrCycles = 12;
16493: {{ uae_s32 dummy = get_ilong(2);
16494: if (cctrue(9)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1105; }
16495: }}m68k_incpc(6);
16496: endlabel1105: ;
16497: return 12;
16498: }
16499: unsigned long REGPARAM2 CPUFUNC(op_59fc_0)(uae_u32 opcode) /* TRAPcc */
16500: {
16501: OpcodeFamily = 102; CurrentInstrCycles = 4;
16502: { if (cctrue(9)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1106; }
16503: }m68k_incpc(2);
16504: endlabel1106: ;
16505: return 4;
16506: }
16507: unsigned long REGPARAM2 CPUFUNC(op_5ac0_0)(uae_u32 opcode) /* Scc */
16508: {
16509: uae_u32 srcreg = (opcode & 7);
16510: OpcodeFamily = 59; CurrentInstrCycles = 4;
16511: {{{ int val = cctrue(10) ? 0xff : 0;
16512: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
16513: if (val) { m68k_incpc(2) ; return 4+2; }
16514: }}}m68k_incpc(2);
16515: return 4;
16516: }
16517: unsigned long REGPARAM2 CPUFUNC(op_5ac8_0)(uae_u32 opcode) /* DBcc */
16518: {
16519: uae_u32 srcreg = (opcode & 7);
16520: OpcodeFamily = 58; CurrentInstrCycles = 12;
16521: {{ uae_s16 src = m68k_dreg(regs, srcreg);
16522: { uae_s16 offs = get_iword(2);
16523: if (!cctrue(10)) {
16524: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
16525: if (src) {
16526: m68k_incpc((uae_s32)offs + 2);
16527: return 10;
16528: } else {
16529: m68k_incpc(4);
16530: return 14;
16531: }
16532: }
16533: }}}m68k_incpc(4);
16534: endlabel1108: ;
16535: return 12;
16536: }
16537: unsigned long REGPARAM2 CPUFUNC(op_5ad0_0)(uae_u32 opcode) /* Scc */
16538: {
16539: uae_u32 srcreg = (opcode & 7);
16540: OpcodeFamily = 59; CurrentInstrCycles = 12;
16541: {{ uaecptr srca = m68k_areg(regs, srcreg);
16542: { int val = cctrue(10) ? 0xff : 0;
16543: put_byte(srca,val);
16544: }}}m68k_incpc(2);
16545: return 12;
16546: }
16547: unsigned long REGPARAM2 CPUFUNC(op_5ad8_0)(uae_u32 opcode) /* Scc */
16548: {
16549: uae_u32 srcreg = (opcode & 7);
16550: OpcodeFamily = 59; CurrentInstrCycles = 12;
16551: {{ uaecptr srca = m68k_areg(regs, srcreg);
16552: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
16553: { int val = cctrue(10) ? 0xff : 0;
16554: put_byte(srca,val);
16555: }}}m68k_incpc(2);
16556: return 12;
16557: }
16558: unsigned long REGPARAM2 CPUFUNC(op_5ae0_0)(uae_u32 opcode) /* Scc */
16559: {
16560: uae_u32 srcreg = (opcode & 7);
16561: OpcodeFamily = 59; CurrentInstrCycles = 14;
16562: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
16563: m68k_areg (regs, srcreg) = srca;
16564: { int val = cctrue(10) ? 0xff : 0;
16565: put_byte(srca,val);
16566: }}}m68k_incpc(2);
16567: return 14;
16568: }
16569: unsigned long REGPARAM2 CPUFUNC(op_5ae8_0)(uae_u32 opcode) /* Scc */
16570: {
16571: uae_u32 srcreg = (opcode & 7);
16572: OpcodeFamily = 59; CurrentInstrCycles = 16;
16573: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
16574: { int val = cctrue(10) ? 0xff : 0;
16575: put_byte(srca,val);
16576: }}}m68k_incpc(4);
16577: return 16;
16578: }
16579: unsigned long REGPARAM2 CPUFUNC(op_5af0_0)(uae_u32 opcode) /* Scc */
16580: {
16581: uae_u32 srcreg = (opcode & 7);
16582: OpcodeFamily = 59; CurrentInstrCycles = 18;
16583: {{m68k_incpc(2);
16584: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
16585: BusCyclePenalty += 2;
16586: { int val = cctrue(10) ? 0xff : 0;
16587: put_byte(srca,val);
16588: }}}}return 18;
16589: }
16590: unsigned long REGPARAM2 CPUFUNC(op_5af8_0)(uae_u32 opcode) /* Scc */
16591: {
16592: OpcodeFamily = 59; CurrentInstrCycles = 16;
16593: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
16594: { int val = cctrue(10) ? 0xff : 0;
16595: put_byte(srca,val);
16596: }}}m68k_incpc(4);
16597: return 16;
16598: }
16599: unsigned long REGPARAM2 CPUFUNC(op_5af9_0)(uae_u32 opcode) /* Scc */
16600: {
16601: OpcodeFamily = 59; CurrentInstrCycles = 20;
16602: {{ uaecptr srca = get_ilong(2);
16603: { int val = cctrue(10) ? 0xff : 0;
16604: put_byte(srca,val);
16605: }}}m68k_incpc(6);
16606: return 20;
16607: }
16608: unsigned long REGPARAM2 CPUFUNC(op_5afa_0)(uae_u32 opcode) /* TRAPcc */
16609: {
16610: OpcodeFamily = 102; CurrentInstrCycles = 8;
16611: {{ uae_s16 dummy = get_iword(2);
16612: if (cctrue(10)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1116; }
16613: }}m68k_incpc(4);
16614: endlabel1116: ;
16615: return 8;
16616: }
16617: unsigned long REGPARAM2 CPUFUNC(op_5afb_0)(uae_u32 opcode) /* TRAPcc */
16618: {
16619: OpcodeFamily = 102; CurrentInstrCycles = 12;
16620: {{ uae_s32 dummy = get_ilong(2);
16621: if (cctrue(10)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1117; }
16622: }}m68k_incpc(6);
16623: endlabel1117: ;
16624: return 12;
16625: }
16626: unsigned long REGPARAM2 CPUFUNC(op_5afc_0)(uae_u32 opcode) /* TRAPcc */
16627: {
16628: OpcodeFamily = 102; CurrentInstrCycles = 4;
16629: { if (cctrue(10)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1118; }
16630: }m68k_incpc(2);
16631: endlabel1118: ;
16632: return 4;
16633: }
16634: unsigned long REGPARAM2 CPUFUNC(op_5bc0_0)(uae_u32 opcode) /* Scc */
16635: {
16636: uae_u32 srcreg = (opcode & 7);
16637: OpcodeFamily = 59; CurrentInstrCycles = 4;
16638: {{{ int val = cctrue(11) ? 0xff : 0;
16639: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
16640: if (val) { m68k_incpc(2) ; return 4+2; }
16641: }}}m68k_incpc(2);
16642: return 4;
16643: }
16644: unsigned long REGPARAM2 CPUFUNC(op_5bc8_0)(uae_u32 opcode) /* DBcc */
16645: {
16646: uae_u32 srcreg = (opcode & 7);
16647: OpcodeFamily = 58; CurrentInstrCycles = 12;
16648: {{ uae_s16 src = m68k_dreg(regs, srcreg);
16649: { uae_s16 offs = get_iword(2);
16650: if (!cctrue(11)) {
16651: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
16652: if (src) {
16653: m68k_incpc((uae_s32)offs + 2);
16654: return 10;
16655: } else {
16656: m68k_incpc(4);
16657: return 14;
16658: }
16659: }
16660: }}}m68k_incpc(4);
16661: endlabel1120: ;
16662: return 12;
16663: }
16664: unsigned long REGPARAM2 CPUFUNC(op_5bd0_0)(uae_u32 opcode) /* Scc */
16665: {
16666: uae_u32 srcreg = (opcode & 7);
16667: OpcodeFamily = 59; CurrentInstrCycles = 12;
16668: {{ uaecptr srca = m68k_areg(regs, srcreg);
16669: { int val = cctrue(11) ? 0xff : 0;
16670: put_byte(srca,val);
16671: }}}m68k_incpc(2);
16672: return 12;
16673: }
16674: unsigned long REGPARAM2 CPUFUNC(op_5bd8_0)(uae_u32 opcode) /* Scc */
16675: {
16676: uae_u32 srcreg = (opcode & 7);
16677: OpcodeFamily = 59; CurrentInstrCycles = 12;
16678: {{ uaecptr srca = m68k_areg(regs, srcreg);
16679: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
16680: { int val = cctrue(11) ? 0xff : 0;
16681: put_byte(srca,val);
16682: }}}m68k_incpc(2);
16683: return 12;
16684: }
16685: unsigned long REGPARAM2 CPUFUNC(op_5be0_0)(uae_u32 opcode) /* Scc */
16686: {
16687: uae_u32 srcreg = (opcode & 7);
16688: OpcodeFamily = 59; CurrentInstrCycles = 14;
16689: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
16690: m68k_areg (regs, srcreg) = srca;
16691: { int val = cctrue(11) ? 0xff : 0;
16692: put_byte(srca,val);
16693: }}}m68k_incpc(2);
16694: return 14;
16695: }
16696: unsigned long REGPARAM2 CPUFUNC(op_5be8_0)(uae_u32 opcode) /* Scc */
16697: {
16698: uae_u32 srcreg = (opcode & 7);
16699: OpcodeFamily = 59; CurrentInstrCycles = 16;
16700: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
16701: { int val = cctrue(11) ? 0xff : 0;
16702: put_byte(srca,val);
16703: }}}m68k_incpc(4);
16704: return 16;
16705: }
16706: unsigned long REGPARAM2 CPUFUNC(op_5bf0_0)(uae_u32 opcode) /* Scc */
16707: {
16708: uae_u32 srcreg = (opcode & 7);
16709: OpcodeFamily = 59; CurrentInstrCycles = 18;
16710: {{m68k_incpc(2);
16711: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
16712: BusCyclePenalty += 2;
16713: { int val = cctrue(11) ? 0xff : 0;
16714: put_byte(srca,val);
16715: }}}}return 18;
16716: }
16717: unsigned long REGPARAM2 CPUFUNC(op_5bf8_0)(uae_u32 opcode) /* Scc */
16718: {
16719: OpcodeFamily = 59; CurrentInstrCycles = 16;
16720: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
16721: { int val = cctrue(11) ? 0xff : 0;
16722: put_byte(srca,val);
16723: }}}m68k_incpc(4);
16724: return 16;
16725: }
16726: unsigned long REGPARAM2 CPUFUNC(op_5bf9_0)(uae_u32 opcode) /* Scc */
16727: {
16728: OpcodeFamily = 59; CurrentInstrCycles = 20;
16729: {{ uaecptr srca = get_ilong(2);
16730: { int val = cctrue(11) ? 0xff : 0;
16731: put_byte(srca,val);
16732: }}}m68k_incpc(6);
16733: return 20;
16734: }
16735: unsigned long REGPARAM2 CPUFUNC(op_5bfa_0)(uae_u32 opcode) /* TRAPcc */
16736: {
16737: OpcodeFamily = 102; CurrentInstrCycles = 8;
16738: {{ uae_s16 dummy = get_iword(2);
16739: if (cctrue(11)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1128; }
16740: }}m68k_incpc(4);
16741: endlabel1128: ;
16742: return 8;
16743: }
16744: unsigned long REGPARAM2 CPUFUNC(op_5bfb_0)(uae_u32 opcode) /* TRAPcc */
16745: {
16746: OpcodeFamily = 102; CurrentInstrCycles = 12;
16747: {{ uae_s32 dummy = get_ilong(2);
16748: if (cctrue(11)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1129; }
16749: }}m68k_incpc(6);
16750: endlabel1129: ;
16751: return 12;
16752: }
16753: unsigned long REGPARAM2 CPUFUNC(op_5bfc_0)(uae_u32 opcode) /* TRAPcc */
16754: {
16755: OpcodeFamily = 102; CurrentInstrCycles = 4;
16756: { if (cctrue(11)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1130; }
16757: }m68k_incpc(2);
16758: endlabel1130: ;
16759: return 4;
16760: }
16761: unsigned long REGPARAM2 CPUFUNC(op_5cc0_0)(uae_u32 opcode) /* Scc */
16762: {
16763: uae_u32 srcreg = (opcode & 7);
16764: OpcodeFamily = 59; CurrentInstrCycles = 4;
16765: {{{ int val = cctrue(12) ? 0xff : 0;
16766: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
16767: if (val) { m68k_incpc(2) ; return 4+2; }
16768: }}}m68k_incpc(2);
16769: return 4;
16770: }
16771: unsigned long REGPARAM2 CPUFUNC(op_5cc8_0)(uae_u32 opcode) /* DBcc */
16772: {
16773: uae_u32 srcreg = (opcode & 7);
16774: OpcodeFamily = 58; CurrentInstrCycles = 12;
16775: {{ uae_s16 src = m68k_dreg(regs, srcreg);
16776: { uae_s16 offs = get_iword(2);
16777: if (!cctrue(12)) {
16778: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
16779: if (src) {
16780: m68k_incpc((uae_s32)offs + 2);
16781: return 10;
16782: } else {
16783: m68k_incpc(4);
16784: return 14;
16785: }
16786: }
16787: }}}m68k_incpc(4);
16788: endlabel1132: ;
16789: return 12;
16790: }
16791: unsigned long REGPARAM2 CPUFUNC(op_5cd0_0)(uae_u32 opcode) /* Scc */
16792: {
16793: uae_u32 srcreg = (opcode & 7);
16794: OpcodeFamily = 59; CurrentInstrCycles = 12;
16795: {{ uaecptr srca = m68k_areg(regs, srcreg);
16796: { int val = cctrue(12) ? 0xff : 0;
16797: put_byte(srca,val);
16798: }}}m68k_incpc(2);
16799: return 12;
16800: }
16801: unsigned long REGPARAM2 CPUFUNC(op_5cd8_0)(uae_u32 opcode) /* Scc */
16802: {
16803: uae_u32 srcreg = (opcode & 7);
16804: OpcodeFamily = 59; CurrentInstrCycles = 12;
16805: {{ uaecptr srca = m68k_areg(regs, srcreg);
16806: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
16807: { int val = cctrue(12) ? 0xff : 0;
16808: put_byte(srca,val);
16809: }}}m68k_incpc(2);
16810: return 12;
16811: }
16812: unsigned long REGPARAM2 CPUFUNC(op_5ce0_0)(uae_u32 opcode) /* Scc */
16813: {
16814: uae_u32 srcreg = (opcode & 7);
16815: OpcodeFamily = 59; CurrentInstrCycles = 14;
16816: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
16817: m68k_areg (regs, srcreg) = srca;
16818: { int val = cctrue(12) ? 0xff : 0;
16819: put_byte(srca,val);
16820: }}}m68k_incpc(2);
16821: return 14;
16822: }
16823: unsigned long REGPARAM2 CPUFUNC(op_5ce8_0)(uae_u32 opcode) /* Scc */
16824: {
16825: uae_u32 srcreg = (opcode & 7);
16826: OpcodeFamily = 59; CurrentInstrCycles = 16;
16827: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
16828: { int val = cctrue(12) ? 0xff : 0;
16829: put_byte(srca,val);
16830: }}}m68k_incpc(4);
16831: return 16;
16832: }
16833: unsigned long REGPARAM2 CPUFUNC(op_5cf0_0)(uae_u32 opcode) /* Scc */
16834: {
16835: uae_u32 srcreg = (opcode & 7);
16836: OpcodeFamily = 59; CurrentInstrCycles = 18;
16837: {{m68k_incpc(2);
16838: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
16839: BusCyclePenalty += 2;
16840: { int val = cctrue(12) ? 0xff : 0;
16841: put_byte(srca,val);
16842: }}}}return 18;
16843: }
16844: unsigned long REGPARAM2 CPUFUNC(op_5cf8_0)(uae_u32 opcode) /* Scc */
16845: {
16846: OpcodeFamily = 59; CurrentInstrCycles = 16;
16847: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
16848: { int val = cctrue(12) ? 0xff : 0;
16849: put_byte(srca,val);
16850: }}}m68k_incpc(4);
16851: return 16;
16852: }
16853: unsigned long REGPARAM2 CPUFUNC(op_5cf9_0)(uae_u32 opcode) /* Scc */
16854: {
16855: OpcodeFamily = 59; CurrentInstrCycles = 20;
16856: {{ uaecptr srca = get_ilong(2);
16857: { int val = cctrue(12) ? 0xff : 0;
16858: put_byte(srca,val);
16859: }}}m68k_incpc(6);
16860: return 20;
16861: }
16862: unsigned long REGPARAM2 CPUFUNC(op_5cfa_0)(uae_u32 opcode) /* TRAPcc */
16863: {
16864: OpcodeFamily = 102; CurrentInstrCycles = 8;
16865: {{ uae_s16 dummy = get_iword(2);
16866: if (cctrue(12)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1140; }
16867: }}m68k_incpc(4);
16868: endlabel1140: ;
16869: return 8;
16870: }
16871: unsigned long REGPARAM2 CPUFUNC(op_5cfb_0)(uae_u32 opcode) /* TRAPcc */
16872: {
16873: OpcodeFamily = 102; CurrentInstrCycles = 12;
16874: {{ uae_s32 dummy = get_ilong(2);
16875: if (cctrue(12)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1141; }
16876: }}m68k_incpc(6);
16877: endlabel1141: ;
16878: return 12;
16879: }
16880: unsigned long REGPARAM2 CPUFUNC(op_5cfc_0)(uae_u32 opcode) /* TRAPcc */
16881: {
16882: OpcodeFamily = 102; CurrentInstrCycles = 4;
16883: { if (cctrue(12)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1142; }
16884: }m68k_incpc(2);
16885: endlabel1142: ;
16886: return 4;
16887: }
16888: unsigned long REGPARAM2 CPUFUNC(op_5dc0_0)(uae_u32 opcode) /* Scc */
16889: {
16890: uae_u32 srcreg = (opcode & 7);
16891: OpcodeFamily = 59; CurrentInstrCycles = 4;
16892: {{{ int val = cctrue(13) ? 0xff : 0;
16893: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
16894: if (val) { m68k_incpc(2) ; return 4+2; }
16895: }}}m68k_incpc(2);
16896: return 4;
16897: }
16898: unsigned long REGPARAM2 CPUFUNC(op_5dc8_0)(uae_u32 opcode) /* DBcc */
16899: {
16900: uae_u32 srcreg = (opcode & 7);
16901: OpcodeFamily = 58; CurrentInstrCycles = 12;
16902: {{ uae_s16 src = m68k_dreg(regs, srcreg);
16903: { uae_s16 offs = get_iword(2);
16904: if (!cctrue(13)) {
16905: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
16906: if (src) {
16907: m68k_incpc((uae_s32)offs + 2);
16908: return 10;
16909: } else {
16910: m68k_incpc(4);
16911: return 14;
16912: }
16913: }
16914: }}}m68k_incpc(4);
16915: endlabel1144: ;
16916: return 12;
16917: }
16918: unsigned long REGPARAM2 CPUFUNC(op_5dd0_0)(uae_u32 opcode) /* Scc */
16919: {
16920: uae_u32 srcreg = (opcode & 7);
16921: OpcodeFamily = 59; CurrentInstrCycles = 12;
16922: {{ uaecptr srca = m68k_areg(regs, srcreg);
16923: { int val = cctrue(13) ? 0xff : 0;
16924: put_byte(srca,val);
16925: }}}m68k_incpc(2);
16926: return 12;
16927: }
16928: unsigned long REGPARAM2 CPUFUNC(op_5dd8_0)(uae_u32 opcode) /* Scc */
16929: {
16930: uae_u32 srcreg = (opcode & 7);
16931: OpcodeFamily = 59; CurrentInstrCycles = 12;
16932: {{ uaecptr srca = m68k_areg(regs, srcreg);
16933: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
16934: { int val = cctrue(13) ? 0xff : 0;
16935: put_byte(srca,val);
16936: }}}m68k_incpc(2);
16937: return 12;
16938: }
16939: unsigned long REGPARAM2 CPUFUNC(op_5de0_0)(uae_u32 opcode) /* Scc */
16940: {
16941: uae_u32 srcreg = (opcode & 7);
16942: OpcodeFamily = 59; CurrentInstrCycles = 14;
16943: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
16944: m68k_areg (regs, srcreg) = srca;
16945: { int val = cctrue(13) ? 0xff : 0;
16946: put_byte(srca,val);
16947: }}}m68k_incpc(2);
16948: return 14;
16949: }
16950: unsigned long REGPARAM2 CPUFUNC(op_5de8_0)(uae_u32 opcode) /* Scc */
16951: {
16952: uae_u32 srcreg = (opcode & 7);
16953: OpcodeFamily = 59; CurrentInstrCycles = 16;
16954: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
16955: { int val = cctrue(13) ? 0xff : 0;
16956: put_byte(srca,val);
16957: }}}m68k_incpc(4);
16958: return 16;
16959: }
16960: unsigned long REGPARAM2 CPUFUNC(op_5df0_0)(uae_u32 opcode) /* Scc */
16961: {
16962: uae_u32 srcreg = (opcode & 7);
16963: OpcodeFamily = 59; CurrentInstrCycles = 18;
16964: {{m68k_incpc(2);
16965: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
16966: BusCyclePenalty += 2;
16967: { int val = cctrue(13) ? 0xff : 0;
16968: put_byte(srca,val);
16969: }}}}return 18;
16970: }
16971: unsigned long REGPARAM2 CPUFUNC(op_5df8_0)(uae_u32 opcode) /* Scc */
16972: {
16973: OpcodeFamily = 59; CurrentInstrCycles = 16;
16974: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
16975: { int val = cctrue(13) ? 0xff : 0;
16976: put_byte(srca,val);
16977: }}}m68k_incpc(4);
16978: return 16;
16979: }
16980: unsigned long REGPARAM2 CPUFUNC(op_5df9_0)(uae_u32 opcode) /* Scc */
16981: {
16982: OpcodeFamily = 59; CurrentInstrCycles = 20;
16983: {{ uaecptr srca = get_ilong(2);
16984: { int val = cctrue(13) ? 0xff : 0;
16985: put_byte(srca,val);
16986: }}}m68k_incpc(6);
16987: return 20;
16988: }
16989: unsigned long REGPARAM2 CPUFUNC(op_5dfa_0)(uae_u32 opcode) /* TRAPcc */
16990: {
16991: OpcodeFamily = 102; CurrentInstrCycles = 8;
16992: {{ uae_s16 dummy = get_iword(2);
16993: if (cctrue(13)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1152; }
16994: }}m68k_incpc(4);
16995: endlabel1152: ;
16996: return 8;
16997: }
16998: unsigned long REGPARAM2 CPUFUNC(op_5dfb_0)(uae_u32 opcode) /* TRAPcc */
16999: {
17000: OpcodeFamily = 102; CurrentInstrCycles = 12;
17001: {{ uae_s32 dummy = get_ilong(2);
17002: if (cctrue(13)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1153; }
17003: }}m68k_incpc(6);
17004: endlabel1153: ;
17005: return 12;
17006: }
17007: unsigned long REGPARAM2 CPUFUNC(op_5dfc_0)(uae_u32 opcode) /* TRAPcc */
17008: {
17009: OpcodeFamily = 102; CurrentInstrCycles = 4;
17010: { if (cctrue(13)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1154; }
17011: }m68k_incpc(2);
17012: endlabel1154: ;
17013: return 4;
17014: }
17015: unsigned long REGPARAM2 CPUFUNC(op_5ec0_0)(uae_u32 opcode) /* Scc */
17016: {
17017: uae_u32 srcreg = (opcode & 7);
17018: OpcodeFamily = 59; CurrentInstrCycles = 4;
17019: {{{ int val = cctrue(14) ? 0xff : 0;
17020: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
17021: if (val) { m68k_incpc(2) ; return 4+2; }
17022: }}}m68k_incpc(2);
17023: return 4;
17024: }
17025: unsigned long REGPARAM2 CPUFUNC(op_5ec8_0)(uae_u32 opcode) /* DBcc */
17026: {
17027: uae_u32 srcreg = (opcode & 7);
17028: OpcodeFamily = 58; CurrentInstrCycles = 12;
17029: {{ uae_s16 src = m68k_dreg(regs, srcreg);
17030: { uae_s16 offs = get_iword(2);
17031: if (!cctrue(14)) {
17032: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
17033: if (src) {
17034: m68k_incpc((uae_s32)offs + 2);
17035: return 10;
17036: } else {
17037: m68k_incpc(4);
17038: return 14;
17039: }
17040: }
17041: }}}m68k_incpc(4);
17042: endlabel1156: ;
17043: return 12;
17044: }
17045: unsigned long REGPARAM2 CPUFUNC(op_5ed0_0)(uae_u32 opcode) /* Scc */
17046: {
17047: uae_u32 srcreg = (opcode & 7);
17048: OpcodeFamily = 59; CurrentInstrCycles = 12;
17049: {{ uaecptr srca = m68k_areg(regs, srcreg);
17050: { int val = cctrue(14) ? 0xff : 0;
17051: put_byte(srca,val);
17052: }}}m68k_incpc(2);
17053: return 12;
17054: }
17055: unsigned long REGPARAM2 CPUFUNC(op_5ed8_0)(uae_u32 opcode) /* Scc */
17056: {
17057: uae_u32 srcreg = (opcode & 7);
17058: OpcodeFamily = 59; CurrentInstrCycles = 12;
17059: {{ uaecptr srca = m68k_areg(regs, srcreg);
17060: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
17061: { int val = cctrue(14) ? 0xff : 0;
17062: put_byte(srca,val);
17063: }}}m68k_incpc(2);
17064: return 12;
17065: }
17066: unsigned long REGPARAM2 CPUFUNC(op_5ee0_0)(uae_u32 opcode) /* Scc */
17067: {
17068: uae_u32 srcreg = (opcode & 7);
17069: OpcodeFamily = 59; CurrentInstrCycles = 14;
17070: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
17071: m68k_areg (regs, srcreg) = srca;
17072: { int val = cctrue(14) ? 0xff : 0;
17073: put_byte(srca,val);
17074: }}}m68k_incpc(2);
17075: return 14;
17076: }
17077: unsigned long REGPARAM2 CPUFUNC(op_5ee8_0)(uae_u32 opcode) /* Scc */
17078: {
17079: uae_u32 srcreg = (opcode & 7);
17080: OpcodeFamily = 59; CurrentInstrCycles = 16;
17081: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
17082: { int val = cctrue(14) ? 0xff : 0;
17083: put_byte(srca,val);
17084: }}}m68k_incpc(4);
17085: return 16;
17086: }
17087: unsigned long REGPARAM2 CPUFUNC(op_5ef0_0)(uae_u32 opcode) /* Scc */
17088: {
17089: uae_u32 srcreg = (opcode & 7);
17090: OpcodeFamily = 59; CurrentInstrCycles = 18;
17091: {{m68k_incpc(2);
17092: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
17093: BusCyclePenalty += 2;
17094: { int val = cctrue(14) ? 0xff : 0;
17095: put_byte(srca,val);
17096: }}}}return 18;
17097: }
17098: unsigned long REGPARAM2 CPUFUNC(op_5ef8_0)(uae_u32 opcode) /* Scc */
17099: {
17100: OpcodeFamily = 59; CurrentInstrCycles = 16;
17101: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
17102: { int val = cctrue(14) ? 0xff : 0;
17103: put_byte(srca,val);
17104: }}}m68k_incpc(4);
17105: return 16;
17106: }
17107: unsigned long REGPARAM2 CPUFUNC(op_5ef9_0)(uae_u32 opcode) /* Scc */
17108: {
17109: OpcodeFamily = 59; CurrentInstrCycles = 20;
17110: {{ uaecptr srca = get_ilong(2);
17111: { int val = cctrue(14) ? 0xff : 0;
17112: put_byte(srca,val);
17113: }}}m68k_incpc(6);
17114: return 20;
17115: }
17116: unsigned long REGPARAM2 CPUFUNC(op_5efa_0)(uae_u32 opcode) /* TRAPcc */
17117: {
17118: OpcodeFamily = 102; CurrentInstrCycles = 8;
17119: {{ uae_s16 dummy = get_iword(2);
17120: if (cctrue(14)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1164; }
17121: }}m68k_incpc(4);
17122: endlabel1164: ;
17123: return 8;
17124: }
17125: unsigned long REGPARAM2 CPUFUNC(op_5efb_0)(uae_u32 opcode) /* TRAPcc */
17126: {
17127: OpcodeFamily = 102; CurrentInstrCycles = 12;
17128: {{ uae_s32 dummy = get_ilong(2);
17129: if (cctrue(14)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1165; }
17130: }}m68k_incpc(6);
17131: endlabel1165: ;
17132: return 12;
17133: }
17134: unsigned long REGPARAM2 CPUFUNC(op_5efc_0)(uae_u32 opcode) /* TRAPcc */
17135: {
17136: OpcodeFamily = 102; CurrentInstrCycles = 4;
17137: { if (cctrue(14)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1166; }
17138: }m68k_incpc(2);
17139: endlabel1166: ;
17140: return 4;
17141: }
17142: unsigned long REGPARAM2 CPUFUNC(op_5fc0_0)(uae_u32 opcode) /* Scc */
17143: {
17144: uae_u32 srcreg = (opcode & 7);
17145: OpcodeFamily = 59; CurrentInstrCycles = 4;
17146: {{{ int val = cctrue(15) ? 0xff : 0;
17147: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
17148: if (val) { m68k_incpc(2) ; return 4+2; }
17149: }}}m68k_incpc(2);
17150: return 4;
17151: }
17152: unsigned long REGPARAM2 CPUFUNC(op_5fc8_0)(uae_u32 opcode) /* DBcc */
17153: {
17154: uae_u32 srcreg = (opcode & 7);
17155: OpcodeFamily = 58; CurrentInstrCycles = 12;
17156: {{ uae_s16 src = m68k_dreg(regs, srcreg);
17157: { uae_s16 offs = get_iword(2);
17158: if (!cctrue(15)) {
17159: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
17160: if (src) {
17161: m68k_incpc((uae_s32)offs + 2);
17162: return 10;
17163: } else {
17164: m68k_incpc(4);
17165: return 14;
17166: }
17167: }
17168: }}}m68k_incpc(4);
17169: endlabel1168: ;
17170: return 12;
17171: }
17172: unsigned long REGPARAM2 CPUFUNC(op_5fd0_0)(uae_u32 opcode) /* Scc */
17173: {
17174: uae_u32 srcreg = (opcode & 7);
17175: OpcodeFamily = 59; CurrentInstrCycles = 12;
17176: {{ uaecptr srca = m68k_areg(regs, srcreg);
17177: { int val = cctrue(15) ? 0xff : 0;
17178: put_byte(srca,val);
17179: }}}m68k_incpc(2);
17180: return 12;
17181: }
17182: unsigned long REGPARAM2 CPUFUNC(op_5fd8_0)(uae_u32 opcode) /* Scc */
17183: {
17184: uae_u32 srcreg = (opcode & 7);
17185: OpcodeFamily = 59; CurrentInstrCycles = 12;
17186: {{ uaecptr srca = m68k_areg(regs, srcreg);
17187: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
17188: { int val = cctrue(15) ? 0xff : 0;
17189: put_byte(srca,val);
17190: }}}m68k_incpc(2);
17191: return 12;
17192: }
17193: unsigned long REGPARAM2 CPUFUNC(op_5fe0_0)(uae_u32 opcode) /* Scc */
17194: {
17195: uae_u32 srcreg = (opcode & 7);
17196: OpcodeFamily = 59; CurrentInstrCycles = 14;
17197: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
17198: m68k_areg (regs, srcreg) = srca;
17199: { int val = cctrue(15) ? 0xff : 0;
17200: put_byte(srca,val);
17201: }}}m68k_incpc(2);
17202: return 14;
17203: }
17204: #endif
17205:
17206: #ifdef PART_6
17207: unsigned long REGPARAM2 CPUFUNC(op_5fe8_0)(uae_u32 opcode) /* Scc */
17208: {
17209: uae_u32 srcreg = (opcode & 7);
17210: OpcodeFamily = 59; CurrentInstrCycles = 16;
17211: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
17212: { int val = cctrue(15) ? 0xff : 0;
17213: put_byte(srca,val);
17214: }}}m68k_incpc(4);
17215: return 16;
17216: }
17217: unsigned long REGPARAM2 CPUFUNC(op_5ff0_0)(uae_u32 opcode) /* Scc */
17218: {
17219: uae_u32 srcreg = (opcode & 7);
17220: OpcodeFamily = 59; CurrentInstrCycles = 18;
17221: {{m68k_incpc(2);
17222: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
17223: BusCyclePenalty += 2;
17224: { int val = cctrue(15) ? 0xff : 0;
17225: put_byte(srca,val);
17226: }}}}return 18;
17227: }
17228: unsigned long REGPARAM2 CPUFUNC(op_5ff8_0)(uae_u32 opcode) /* Scc */
17229: {
17230: OpcodeFamily = 59; CurrentInstrCycles = 16;
17231: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
17232: { int val = cctrue(15) ? 0xff : 0;
17233: put_byte(srca,val);
17234: }}}m68k_incpc(4);
17235: return 16;
17236: }
17237: unsigned long REGPARAM2 CPUFUNC(op_5ff9_0)(uae_u32 opcode) /* Scc */
17238: {
17239: OpcodeFamily = 59; CurrentInstrCycles = 20;
17240: {{ uaecptr srca = get_ilong(2);
17241: { int val = cctrue(15) ? 0xff : 0;
17242: put_byte(srca,val);
17243: }}}m68k_incpc(6);
17244: return 20;
17245: }
17246: unsigned long REGPARAM2 CPUFUNC(op_5ffa_0)(uae_u32 opcode) /* TRAPcc */
17247: {
17248: OpcodeFamily = 102; CurrentInstrCycles = 8;
17249: {{ uae_s16 dummy = get_iword(2);
17250: if (cctrue(15)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1176; }
17251: }}m68k_incpc(4);
17252: endlabel1176: ;
17253: return 8;
17254: }
17255: unsigned long REGPARAM2 CPUFUNC(op_5ffb_0)(uae_u32 opcode) /* TRAPcc */
17256: {
17257: OpcodeFamily = 102; CurrentInstrCycles = 12;
17258: {{ uae_s32 dummy = get_ilong(2);
17259: if (cctrue(15)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1177; }
17260: }}m68k_incpc(6);
17261: endlabel1177: ;
17262: return 12;
17263: }
17264: unsigned long REGPARAM2 CPUFUNC(op_5ffc_0)(uae_u32 opcode) /* TRAPcc */
17265: {
17266: OpcodeFamily = 102; CurrentInstrCycles = 4;
17267: { if (cctrue(15)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel1178; }
17268: }m68k_incpc(2);
17269: endlabel1178: ;
17270: return 4;
17271: }
17272: unsigned long REGPARAM2 CPUFUNC(op_6000_0)(uae_u32 opcode) /* Bcc */
17273: {
17274: OpcodeFamily = 55; CurrentInstrCycles = 12;
17275: {{ uae_s16 src = get_iword(2);
17276: if (!cctrue(0)) goto didnt_jump;
17277: m68k_incpc ((uae_s32)src + 2);
17278: return 10;
17279: didnt_jump:;
17280: }}m68k_incpc(4);
17281: endlabel1179: ;
17282: return 12;
17283: }
17284: unsigned long REGPARAM2 CPUFUNC(op_6001_0)(uae_u32 opcode) /* Bcc */
17285: {
17286: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17287: OpcodeFamily = 55; CurrentInstrCycles = 8;
17288: {{ uae_u32 src = srcreg;
17289: if (!cctrue(0)) goto didnt_jump;
17290: m68k_incpc ((uae_s32)src + 2);
17291: return 10;
17292: didnt_jump:;
17293: }}m68k_incpc(2);
17294: endlabel1180: ;
17295: return 8;
17296: }
17297: unsigned long REGPARAM2 CPUFUNC(op_60ff_0)(uae_u32 opcode) /* Bcc */
17298: {
17299: OpcodeFamily = 55; CurrentInstrCycles = 12;
17300: {{ uae_s32 src = get_ilong(2);
17301: if (!cctrue(0)) goto didnt_jump;
17302: m68k_incpc ((uae_s32)src + 2);
17303: return 10;
17304: didnt_jump:;
17305: }}m68k_incpc(6);
17306: endlabel1181: ;
17307: return 12;
17308: }
17309: unsigned long REGPARAM2 CPUFUNC(op_6100_0)(uae_u32 opcode) /* BSR */
17310: {
17311: OpcodeFamily = 54; CurrentInstrCycles = 18;
17312: {{ uae_s16 src = get_iword(2);
17313: uae_s32 s = (uae_s32)src + 2;
17314: m68k_do_bsr(m68k_getpc() + 4, s);
17315: }}return 18;
17316: }
17317: unsigned long REGPARAM2 CPUFUNC(op_6101_0)(uae_u32 opcode) /* BSR */
17318: {
17319: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17320: OpcodeFamily = 54; CurrentInstrCycles = 18;
17321: {{ uae_u32 src = srcreg;
17322: uae_s32 s = (uae_s32)src + 2;
17323: m68k_do_bsr(m68k_getpc() + 2, s);
17324: }}return 18;
17325: }
17326: unsigned long REGPARAM2 CPUFUNC(op_61ff_0)(uae_u32 opcode) /* BSR */
17327: {
17328: OpcodeFamily = 54; CurrentInstrCycles = 18;
17329: {{ uae_s32 src = get_ilong(2);
17330: uae_s32 s = (uae_s32)src + 2;
17331: m68k_do_bsr(m68k_getpc() + 6, s);
17332: }}return 18;
17333: }
17334: unsigned long REGPARAM2 CPUFUNC(op_6200_0)(uae_u32 opcode) /* Bcc */
17335: {
17336: OpcodeFamily = 55; CurrentInstrCycles = 12;
17337: {{ uae_s16 src = get_iword(2);
17338: if (!cctrue(2)) goto didnt_jump;
17339: m68k_incpc ((uae_s32)src + 2);
17340: return 10;
17341: didnt_jump:;
17342: }}m68k_incpc(4);
17343: endlabel1185: ;
17344: return 12;
17345: }
17346: unsigned long REGPARAM2 CPUFUNC(op_6201_0)(uae_u32 opcode) /* Bcc */
17347: {
17348: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17349: OpcodeFamily = 55; CurrentInstrCycles = 8;
17350: {{ uae_u32 src = srcreg;
17351: if (!cctrue(2)) goto didnt_jump;
17352: m68k_incpc ((uae_s32)src + 2);
17353: return 10;
17354: didnt_jump:;
17355: }}m68k_incpc(2);
17356: endlabel1186: ;
17357: return 8;
17358: }
17359: unsigned long REGPARAM2 CPUFUNC(op_62ff_0)(uae_u32 opcode) /* Bcc */
17360: {
17361: OpcodeFamily = 55; CurrentInstrCycles = 12;
17362: {{ uae_s32 src = get_ilong(2);
17363: if (!cctrue(2)) goto didnt_jump;
17364: m68k_incpc ((uae_s32)src + 2);
17365: return 10;
17366: didnt_jump:;
17367: }}m68k_incpc(6);
17368: endlabel1187: ;
17369: return 12;
17370: }
17371: unsigned long REGPARAM2 CPUFUNC(op_6300_0)(uae_u32 opcode) /* Bcc */
17372: {
17373: OpcodeFamily = 55; CurrentInstrCycles = 12;
17374: {{ uae_s16 src = get_iword(2);
17375: if (!cctrue(3)) goto didnt_jump;
17376: m68k_incpc ((uae_s32)src + 2);
17377: return 10;
17378: didnt_jump:;
17379: }}m68k_incpc(4);
17380: endlabel1188: ;
17381: return 12;
17382: }
17383: unsigned long REGPARAM2 CPUFUNC(op_6301_0)(uae_u32 opcode) /* Bcc */
17384: {
17385: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17386: OpcodeFamily = 55; CurrentInstrCycles = 8;
17387: {{ uae_u32 src = srcreg;
17388: if (!cctrue(3)) goto didnt_jump;
17389: m68k_incpc ((uae_s32)src + 2);
17390: return 10;
17391: didnt_jump:;
17392: }}m68k_incpc(2);
17393: endlabel1189: ;
17394: return 8;
17395: }
17396: unsigned long REGPARAM2 CPUFUNC(op_63ff_0)(uae_u32 opcode) /* Bcc */
17397: {
17398: OpcodeFamily = 55; CurrentInstrCycles = 12;
17399: {{ uae_s32 src = get_ilong(2);
17400: if (!cctrue(3)) goto didnt_jump;
17401: m68k_incpc ((uae_s32)src + 2);
17402: return 10;
17403: didnt_jump:;
17404: }}m68k_incpc(6);
17405: endlabel1190: ;
17406: return 12;
17407: }
17408: unsigned long REGPARAM2 CPUFUNC(op_6400_0)(uae_u32 opcode) /* Bcc */
17409: {
17410: OpcodeFamily = 55; CurrentInstrCycles = 12;
17411: {{ uae_s16 src = get_iword(2);
17412: if (!cctrue(4)) goto didnt_jump;
17413: m68k_incpc ((uae_s32)src + 2);
17414: return 10;
17415: didnt_jump:;
17416: }}m68k_incpc(4);
17417: endlabel1191: ;
17418: return 12;
17419: }
17420: unsigned long REGPARAM2 CPUFUNC(op_6401_0)(uae_u32 opcode) /* Bcc */
17421: {
17422: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17423: OpcodeFamily = 55; CurrentInstrCycles = 8;
17424: {{ uae_u32 src = srcreg;
17425: if (!cctrue(4)) goto didnt_jump;
17426: m68k_incpc ((uae_s32)src + 2);
17427: return 10;
17428: didnt_jump:;
17429: }}m68k_incpc(2);
17430: endlabel1192: ;
17431: return 8;
17432: }
17433: unsigned long REGPARAM2 CPUFUNC(op_64ff_0)(uae_u32 opcode) /* Bcc */
17434: {
17435: OpcodeFamily = 55; CurrentInstrCycles = 12;
17436: {{ uae_s32 src = get_ilong(2);
17437: if (!cctrue(4)) goto didnt_jump;
17438: m68k_incpc ((uae_s32)src + 2);
17439: return 10;
17440: didnt_jump:;
17441: }}m68k_incpc(6);
17442: endlabel1193: ;
17443: return 12;
17444: }
17445: unsigned long REGPARAM2 CPUFUNC(op_6500_0)(uae_u32 opcode) /* Bcc */
17446: {
17447: OpcodeFamily = 55; CurrentInstrCycles = 12;
17448: {{ uae_s16 src = get_iword(2);
17449: if (!cctrue(5)) goto didnt_jump;
17450: m68k_incpc ((uae_s32)src + 2);
17451: return 10;
17452: didnt_jump:;
17453: }}m68k_incpc(4);
17454: endlabel1194: ;
17455: return 12;
17456: }
17457: unsigned long REGPARAM2 CPUFUNC(op_6501_0)(uae_u32 opcode) /* Bcc */
17458: {
17459: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17460: OpcodeFamily = 55; CurrentInstrCycles = 8;
17461: {{ uae_u32 src = srcreg;
17462: if (!cctrue(5)) goto didnt_jump;
17463: m68k_incpc ((uae_s32)src + 2);
17464: return 10;
17465: didnt_jump:;
17466: }}m68k_incpc(2);
17467: endlabel1195: ;
17468: return 8;
17469: }
17470: unsigned long REGPARAM2 CPUFUNC(op_65ff_0)(uae_u32 opcode) /* Bcc */
17471: {
17472: OpcodeFamily = 55; CurrentInstrCycles = 12;
17473: {{ uae_s32 src = get_ilong(2);
17474: if (!cctrue(5)) goto didnt_jump;
17475: m68k_incpc ((uae_s32)src + 2);
17476: return 10;
17477: didnt_jump:;
17478: }}m68k_incpc(6);
17479: endlabel1196: ;
17480: return 12;
17481: }
17482: unsigned long REGPARAM2 CPUFUNC(op_6600_0)(uae_u32 opcode) /* Bcc */
17483: {
17484: OpcodeFamily = 55; CurrentInstrCycles = 12;
17485: {{ uae_s16 src = get_iword(2);
17486: if (!cctrue(6)) goto didnt_jump;
17487: m68k_incpc ((uae_s32)src + 2);
17488: return 10;
17489: didnt_jump:;
17490: }}m68k_incpc(4);
17491: endlabel1197: ;
17492: return 12;
17493: }
17494: unsigned long REGPARAM2 CPUFUNC(op_6601_0)(uae_u32 opcode) /* Bcc */
17495: {
17496: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17497: OpcodeFamily = 55; CurrentInstrCycles = 8;
17498: {{ uae_u32 src = srcreg;
17499: if (!cctrue(6)) goto didnt_jump;
17500: m68k_incpc ((uae_s32)src + 2);
17501: return 10;
17502: didnt_jump:;
17503: }}m68k_incpc(2);
17504: endlabel1198: ;
17505: return 8;
17506: }
17507: unsigned long REGPARAM2 CPUFUNC(op_66ff_0)(uae_u32 opcode) /* Bcc */
17508: {
17509: OpcodeFamily = 55; CurrentInstrCycles = 12;
17510: {{ uae_s32 src = get_ilong(2);
17511: if (!cctrue(6)) goto didnt_jump;
17512: m68k_incpc ((uae_s32)src + 2);
17513: return 10;
17514: didnt_jump:;
17515: }}m68k_incpc(6);
17516: endlabel1199: ;
17517: return 12;
17518: }
17519: unsigned long REGPARAM2 CPUFUNC(op_6700_0)(uae_u32 opcode) /* Bcc */
17520: {
17521: OpcodeFamily = 55; CurrentInstrCycles = 12;
17522: {{ uae_s16 src = get_iword(2);
17523: if (!cctrue(7)) goto didnt_jump;
17524: m68k_incpc ((uae_s32)src + 2);
17525: return 10;
17526: didnt_jump:;
17527: }}m68k_incpc(4);
17528: endlabel1200: ;
17529: return 12;
17530: }
17531: unsigned long REGPARAM2 CPUFUNC(op_6701_0)(uae_u32 opcode) /* Bcc */
17532: {
17533: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17534: OpcodeFamily = 55; CurrentInstrCycles = 8;
17535: {{ uae_u32 src = srcreg;
17536: if (!cctrue(7)) goto didnt_jump;
17537: m68k_incpc ((uae_s32)src + 2);
17538: return 10;
17539: didnt_jump:;
17540: }}m68k_incpc(2);
17541: endlabel1201: ;
17542: return 8;
17543: }
17544: unsigned long REGPARAM2 CPUFUNC(op_67ff_0)(uae_u32 opcode) /* Bcc */
17545: {
17546: OpcodeFamily = 55; CurrentInstrCycles = 12;
17547: {{ uae_s32 src = get_ilong(2);
17548: if (!cctrue(7)) goto didnt_jump;
17549: m68k_incpc ((uae_s32)src + 2);
17550: return 10;
17551: didnt_jump:;
17552: }}m68k_incpc(6);
17553: endlabel1202: ;
17554: return 12;
17555: }
17556: unsigned long REGPARAM2 CPUFUNC(op_6800_0)(uae_u32 opcode) /* Bcc */
17557: {
17558: OpcodeFamily = 55; CurrentInstrCycles = 12;
17559: {{ uae_s16 src = get_iword(2);
17560: if (!cctrue(8)) goto didnt_jump;
17561: m68k_incpc ((uae_s32)src + 2);
17562: return 10;
17563: didnt_jump:;
17564: }}m68k_incpc(4);
17565: endlabel1203: ;
17566: return 12;
17567: }
17568: unsigned long REGPARAM2 CPUFUNC(op_6801_0)(uae_u32 opcode) /* Bcc */
17569: {
17570: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17571: OpcodeFamily = 55; CurrentInstrCycles = 8;
17572: {{ uae_u32 src = srcreg;
17573: if (!cctrue(8)) goto didnt_jump;
17574: m68k_incpc ((uae_s32)src + 2);
17575: return 10;
17576: didnt_jump:;
17577: }}m68k_incpc(2);
17578: endlabel1204: ;
17579: return 8;
17580: }
17581: unsigned long REGPARAM2 CPUFUNC(op_68ff_0)(uae_u32 opcode) /* Bcc */
17582: {
17583: OpcodeFamily = 55; CurrentInstrCycles = 12;
17584: {{ uae_s32 src = get_ilong(2);
17585: if (!cctrue(8)) goto didnt_jump;
17586: m68k_incpc ((uae_s32)src + 2);
17587: return 10;
17588: didnt_jump:;
17589: }}m68k_incpc(6);
17590: endlabel1205: ;
17591: return 12;
17592: }
17593: unsigned long REGPARAM2 CPUFUNC(op_6900_0)(uae_u32 opcode) /* Bcc */
17594: {
17595: OpcodeFamily = 55; CurrentInstrCycles = 12;
17596: {{ uae_s16 src = get_iword(2);
17597: if (!cctrue(9)) goto didnt_jump;
17598: m68k_incpc ((uae_s32)src + 2);
17599: return 10;
17600: didnt_jump:;
17601: }}m68k_incpc(4);
17602: endlabel1206: ;
17603: return 12;
17604: }
17605: unsigned long REGPARAM2 CPUFUNC(op_6901_0)(uae_u32 opcode) /* Bcc */
17606: {
17607: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17608: OpcodeFamily = 55; CurrentInstrCycles = 8;
17609: {{ uae_u32 src = srcreg;
17610: if (!cctrue(9)) goto didnt_jump;
17611: m68k_incpc ((uae_s32)src + 2);
17612: return 10;
17613: didnt_jump:;
17614: }}m68k_incpc(2);
17615: endlabel1207: ;
17616: return 8;
17617: }
17618: unsigned long REGPARAM2 CPUFUNC(op_69ff_0)(uae_u32 opcode) /* Bcc */
17619: {
17620: OpcodeFamily = 55; CurrentInstrCycles = 12;
17621: {{ uae_s32 src = get_ilong(2);
17622: if (!cctrue(9)) goto didnt_jump;
17623: m68k_incpc ((uae_s32)src + 2);
17624: return 10;
17625: didnt_jump:;
17626: }}m68k_incpc(6);
17627: endlabel1208: ;
17628: return 12;
17629: }
17630: unsigned long REGPARAM2 CPUFUNC(op_6a00_0)(uae_u32 opcode) /* Bcc */
17631: {
17632: OpcodeFamily = 55; CurrentInstrCycles = 12;
17633: {{ uae_s16 src = get_iword(2);
17634: if (!cctrue(10)) goto didnt_jump;
17635: m68k_incpc ((uae_s32)src + 2);
17636: return 10;
17637: didnt_jump:;
17638: }}m68k_incpc(4);
17639: endlabel1209: ;
17640: return 12;
17641: }
17642: unsigned long REGPARAM2 CPUFUNC(op_6a01_0)(uae_u32 opcode) /* Bcc */
17643: {
17644: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17645: OpcodeFamily = 55; CurrentInstrCycles = 8;
17646: {{ uae_u32 src = srcreg;
17647: if (!cctrue(10)) goto didnt_jump;
17648: m68k_incpc ((uae_s32)src + 2);
17649: return 10;
17650: didnt_jump:;
17651: }}m68k_incpc(2);
17652: endlabel1210: ;
17653: return 8;
17654: }
17655: unsigned long REGPARAM2 CPUFUNC(op_6aff_0)(uae_u32 opcode) /* Bcc */
17656: {
17657: OpcodeFamily = 55; CurrentInstrCycles = 12;
17658: {{ uae_s32 src = get_ilong(2);
17659: if (!cctrue(10)) goto didnt_jump;
17660: m68k_incpc ((uae_s32)src + 2);
17661: return 10;
17662: didnt_jump:;
17663: }}m68k_incpc(6);
17664: endlabel1211: ;
17665: return 12;
17666: }
17667: unsigned long REGPARAM2 CPUFUNC(op_6b00_0)(uae_u32 opcode) /* Bcc */
17668: {
17669: OpcodeFamily = 55; CurrentInstrCycles = 12;
17670: {{ uae_s16 src = get_iword(2);
17671: if (!cctrue(11)) goto didnt_jump;
17672: m68k_incpc ((uae_s32)src + 2);
17673: return 10;
17674: didnt_jump:;
17675: }}m68k_incpc(4);
17676: endlabel1212: ;
17677: return 12;
17678: }
17679: unsigned long REGPARAM2 CPUFUNC(op_6b01_0)(uae_u32 opcode) /* Bcc */
17680: {
17681: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17682: OpcodeFamily = 55; CurrentInstrCycles = 8;
17683: {{ uae_u32 src = srcreg;
17684: if (!cctrue(11)) goto didnt_jump;
17685: m68k_incpc ((uae_s32)src + 2);
17686: return 10;
17687: didnt_jump:;
17688: }}m68k_incpc(2);
17689: endlabel1213: ;
17690: return 8;
17691: }
17692: unsigned long REGPARAM2 CPUFUNC(op_6bff_0)(uae_u32 opcode) /* Bcc */
17693: {
17694: OpcodeFamily = 55; CurrentInstrCycles = 12;
17695: {{ uae_s32 src = get_ilong(2);
17696: if (!cctrue(11)) goto didnt_jump;
17697: m68k_incpc ((uae_s32)src + 2);
17698: return 10;
17699: didnt_jump:;
17700: }}m68k_incpc(6);
17701: endlabel1214: ;
17702: return 12;
17703: }
17704: unsigned long REGPARAM2 CPUFUNC(op_6c00_0)(uae_u32 opcode) /* Bcc */
17705: {
17706: OpcodeFamily = 55; CurrentInstrCycles = 12;
17707: {{ uae_s16 src = get_iword(2);
17708: if (!cctrue(12)) goto didnt_jump;
17709: m68k_incpc ((uae_s32)src + 2);
17710: return 10;
17711: didnt_jump:;
17712: }}m68k_incpc(4);
17713: endlabel1215: ;
17714: return 12;
17715: }
17716: unsigned long REGPARAM2 CPUFUNC(op_6c01_0)(uae_u32 opcode) /* Bcc */
17717: {
17718: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17719: OpcodeFamily = 55; CurrentInstrCycles = 8;
17720: {{ uae_u32 src = srcreg;
17721: if (!cctrue(12)) goto didnt_jump;
17722: m68k_incpc ((uae_s32)src + 2);
17723: return 10;
17724: didnt_jump:;
17725: }}m68k_incpc(2);
17726: endlabel1216: ;
17727: return 8;
17728: }
17729: unsigned long REGPARAM2 CPUFUNC(op_6cff_0)(uae_u32 opcode) /* Bcc */
17730: {
17731: OpcodeFamily = 55; CurrentInstrCycles = 12;
17732: {{ uae_s32 src = get_ilong(2);
17733: if (!cctrue(12)) goto didnt_jump;
17734: m68k_incpc ((uae_s32)src + 2);
17735: return 10;
17736: didnt_jump:;
17737: }}m68k_incpc(6);
17738: endlabel1217: ;
17739: return 12;
17740: }
17741: unsigned long REGPARAM2 CPUFUNC(op_6d00_0)(uae_u32 opcode) /* Bcc */
17742: {
17743: OpcodeFamily = 55; CurrentInstrCycles = 12;
17744: {{ uae_s16 src = get_iword(2);
17745: if (!cctrue(13)) goto didnt_jump;
17746: m68k_incpc ((uae_s32)src + 2);
17747: return 10;
17748: didnt_jump:;
17749: }}m68k_incpc(4);
17750: endlabel1218: ;
17751: return 12;
17752: }
17753: unsigned long REGPARAM2 CPUFUNC(op_6d01_0)(uae_u32 opcode) /* Bcc */
17754: {
17755: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17756: OpcodeFamily = 55; CurrentInstrCycles = 8;
17757: {{ uae_u32 src = srcreg;
17758: if (!cctrue(13)) goto didnt_jump;
17759: m68k_incpc ((uae_s32)src + 2);
17760: return 10;
17761: didnt_jump:;
17762: }}m68k_incpc(2);
17763: endlabel1219: ;
17764: return 8;
17765: }
17766: unsigned long REGPARAM2 CPUFUNC(op_6dff_0)(uae_u32 opcode) /* Bcc */
17767: {
17768: OpcodeFamily = 55; CurrentInstrCycles = 12;
17769: {{ uae_s32 src = get_ilong(2);
17770: if (!cctrue(13)) goto didnt_jump;
17771: m68k_incpc ((uae_s32)src + 2);
17772: return 10;
17773: didnt_jump:;
17774: }}m68k_incpc(6);
17775: endlabel1220: ;
17776: return 12;
17777: }
17778: unsigned long REGPARAM2 CPUFUNC(op_6e00_0)(uae_u32 opcode) /* Bcc */
17779: {
17780: OpcodeFamily = 55; CurrentInstrCycles = 12;
17781: {{ uae_s16 src = get_iword(2);
17782: if (!cctrue(14)) goto didnt_jump;
17783: m68k_incpc ((uae_s32)src + 2);
17784: return 10;
17785: didnt_jump:;
17786: }}m68k_incpc(4);
17787: endlabel1221: ;
17788: return 12;
17789: }
17790: unsigned long REGPARAM2 CPUFUNC(op_6e01_0)(uae_u32 opcode) /* Bcc */
17791: {
17792: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17793: OpcodeFamily = 55; CurrentInstrCycles = 8;
17794: {{ uae_u32 src = srcreg;
17795: if (!cctrue(14)) goto didnt_jump;
17796: m68k_incpc ((uae_s32)src + 2);
17797: return 10;
17798: didnt_jump:;
17799: }}m68k_incpc(2);
17800: endlabel1222: ;
17801: return 8;
17802: }
17803: unsigned long REGPARAM2 CPUFUNC(op_6eff_0)(uae_u32 opcode) /* Bcc */
17804: {
17805: OpcodeFamily = 55; CurrentInstrCycles = 12;
17806: {{ uae_s32 src = get_ilong(2);
17807: if (!cctrue(14)) goto didnt_jump;
17808: m68k_incpc ((uae_s32)src + 2);
17809: return 10;
17810: didnt_jump:;
17811: }}m68k_incpc(6);
17812: endlabel1223: ;
17813: return 12;
17814: }
17815: unsigned long REGPARAM2 CPUFUNC(op_6f00_0)(uae_u32 opcode) /* Bcc */
17816: {
17817: OpcodeFamily = 55; CurrentInstrCycles = 12;
17818: {{ uae_s16 src = get_iword(2);
17819: if (!cctrue(15)) goto didnt_jump;
17820: m68k_incpc ((uae_s32)src + 2);
17821: return 10;
17822: didnt_jump:;
17823: }}m68k_incpc(4);
17824: endlabel1224: ;
17825: return 12;
17826: }
17827: unsigned long REGPARAM2 CPUFUNC(op_6f01_0)(uae_u32 opcode) /* Bcc */
17828: {
17829: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17830: OpcodeFamily = 55; CurrentInstrCycles = 8;
17831: {{ uae_u32 src = srcreg;
17832: if (!cctrue(15)) goto didnt_jump;
17833: m68k_incpc ((uae_s32)src + 2);
17834: return 10;
17835: didnt_jump:;
17836: }}m68k_incpc(2);
17837: endlabel1225: ;
17838: return 8;
17839: }
17840: unsigned long REGPARAM2 CPUFUNC(op_6fff_0)(uae_u32 opcode) /* Bcc */
17841: {
17842: OpcodeFamily = 55; CurrentInstrCycles = 12;
17843: {{ uae_s32 src = get_ilong(2);
17844: if (!cctrue(15)) goto didnt_jump;
17845: m68k_incpc ((uae_s32)src + 2);
17846: return 10;
17847: didnt_jump:;
17848: }}m68k_incpc(6);
17849: endlabel1226: ;
17850: return 12;
17851: }
17852: unsigned long REGPARAM2 CPUFUNC(op_7000_0)(uae_u32 opcode) /* MOVE */
17853: {
17854: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
17855: uae_u32 dstreg = (opcode >> 9) & 7;
17856: OpcodeFamily = 30; CurrentInstrCycles = 4;
17857: {{ uae_u32 src = srcreg;
17858: { CLEAR_CZNV;
17859: SET_ZFLG (((uae_s32)(src)) == 0);
17860: SET_NFLG (((uae_s32)(src)) < 0);
17861: m68k_dreg(regs, dstreg) = (src);
17862: }}}m68k_incpc(2);
17863: return 4;
17864: }
17865: unsigned long REGPARAM2 CPUFUNC(op_8000_0)(uae_u32 opcode) /* OR */
17866: {
17867: uae_u32 srcreg = (opcode & 7);
17868: uae_u32 dstreg = (opcode >> 9) & 7;
17869: OpcodeFamily = 1; CurrentInstrCycles = 4;
17870: {{ uae_s8 src = m68k_dreg(regs, srcreg);
17871: { uae_s8 dst = m68k_dreg(regs, dstreg);
17872: src |= dst;
17873: CLEAR_CZNV;
17874: SET_ZFLG (((uae_s8)(src)) == 0);
17875: SET_NFLG (((uae_s8)(src)) < 0);
17876: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
17877: }}}m68k_incpc(2);
17878: return 4;
17879: }
17880: unsigned long REGPARAM2 CPUFUNC(op_8010_0)(uae_u32 opcode) /* OR */
17881: {
17882: uae_u32 srcreg = (opcode & 7);
17883: uae_u32 dstreg = (opcode >> 9) & 7;
17884: OpcodeFamily = 1; CurrentInstrCycles = 8;
17885: {{ uaecptr srca = m68k_areg(regs, srcreg);
17886: { uae_s8 src = get_byte(srca);
17887: { uae_s8 dst = m68k_dreg(regs, dstreg);
17888: src |= dst;
17889: CLEAR_CZNV;
17890: SET_ZFLG (((uae_s8)(src)) == 0);
17891: SET_NFLG (((uae_s8)(src)) < 0);
17892: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
17893: }}}}m68k_incpc(2);
17894: return 8;
17895: }
17896: unsigned long REGPARAM2 CPUFUNC(op_8018_0)(uae_u32 opcode) /* OR */
17897: {
17898: uae_u32 srcreg = (opcode & 7);
17899: uae_u32 dstreg = (opcode >> 9) & 7;
17900: OpcodeFamily = 1; CurrentInstrCycles = 8;
17901: {{ uaecptr srca = m68k_areg(regs, srcreg);
17902: { uae_s8 src = get_byte(srca);
17903: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
17904: { uae_s8 dst = m68k_dreg(regs, dstreg);
17905: src |= dst;
17906: CLEAR_CZNV;
17907: SET_ZFLG (((uae_s8)(src)) == 0);
17908: SET_NFLG (((uae_s8)(src)) < 0);
17909: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
17910: }}}}m68k_incpc(2);
17911: return 8;
17912: }
17913: unsigned long REGPARAM2 CPUFUNC(op_8020_0)(uae_u32 opcode) /* OR */
17914: {
17915: uae_u32 srcreg = (opcode & 7);
17916: uae_u32 dstreg = (opcode >> 9) & 7;
17917: OpcodeFamily = 1; CurrentInstrCycles = 10;
17918: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
17919: { uae_s8 src = get_byte(srca);
17920: m68k_areg (regs, srcreg) = srca;
17921: { uae_s8 dst = m68k_dreg(regs, dstreg);
17922: src |= dst;
17923: CLEAR_CZNV;
17924: SET_ZFLG (((uae_s8)(src)) == 0);
17925: SET_NFLG (((uae_s8)(src)) < 0);
17926: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
17927: }}}}m68k_incpc(2);
17928: return 10;
17929: }
17930: unsigned long REGPARAM2 CPUFUNC(op_8028_0)(uae_u32 opcode) /* OR */
17931: {
17932: uae_u32 srcreg = (opcode & 7);
17933: uae_u32 dstreg = (opcode >> 9) & 7;
17934: OpcodeFamily = 1; CurrentInstrCycles = 12;
17935: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
17936: { uae_s8 src = get_byte(srca);
17937: { uae_s8 dst = m68k_dreg(regs, dstreg);
17938: src |= dst;
17939: CLEAR_CZNV;
17940: SET_ZFLG (((uae_s8)(src)) == 0);
17941: SET_NFLG (((uae_s8)(src)) < 0);
17942: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
17943: }}}}m68k_incpc(4);
17944: return 12;
17945: }
17946: unsigned long REGPARAM2 CPUFUNC(op_8030_0)(uae_u32 opcode) /* OR */
17947: {
17948: uae_u32 srcreg = (opcode & 7);
17949: uae_u32 dstreg = (opcode >> 9) & 7;
17950: OpcodeFamily = 1; CurrentInstrCycles = 14;
17951: {{m68k_incpc(2);
17952: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
17953: BusCyclePenalty += 2;
17954: { uae_s8 src = get_byte(srca);
17955: { uae_s8 dst = m68k_dreg(regs, dstreg);
17956: src |= dst;
17957: CLEAR_CZNV;
17958: SET_ZFLG (((uae_s8)(src)) == 0);
17959: SET_NFLG (((uae_s8)(src)) < 0);
17960: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
17961: }}}}}return 14;
17962: }
17963: unsigned long REGPARAM2 CPUFUNC(op_8038_0)(uae_u32 opcode) /* OR */
17964: {
17965: uae_u32 dstreg = (opcode >> 9) & 7;
17966: OpcodeFamily = 1; CurrentInstrCycles = 12;
17967: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
17968: { uae_s8 src = get_byte(srca);
17969: { uae_s8 dst = m68k_dreg(regs, dstreg);
17970: src |= dst;
17971: CLEAR_CZNV;
17972: SET_ZFLG (((uae_s8)(src)) == 0);
17973: SET_NFLG (((uae_s8)(src)) < 0);
17974: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
17975: }}}}m68k_incpc(4);
17976: return 12;
17977: }
17978: unsigned long REGPARAM2 CPUFUNC(op_8039_0)(uae_u32 opcode) /* OR */
17979: {
17980: uae_u32 dstreg = (opcode >> 9) & 7;
17981: OpcodeFamily = 1; CurrentInstrCycles = 16;
17982: {{ uaecptr srca = get_ilong(2);
17983: { uae_s8 src = get_byte(srca);
17984: { uae_s8 dst = m68k_dreg(regs, dstreg);
17985: src |= dst;
17986: CLEAR_CZNV;
17987: SET_ZFLG (((uae_s8)(src)) == 0);
17988: SET_NFLG (((uae_s8)(src)) < 0);
17989: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
17990: }}}}m68k_incpc(6);
17991: return 16;
17992: }
17993: unsigned long REGPARAM2 CPUFUNC(op_803a_0)(uae_u32 opcode) /* OR */
17994: {
17995: uae_u32 dstreg = (opcode >> 9) & 7;
17996: OpcodeFamily = 1; CurrentInstrCycles = 12;
17997: {{ uaecptr srca = m68k_getpc () + 2;
17998: srca += (uae_s32)(uae_s16)get_iword(2);
17999: { uae_s8 src = get_byte(srca);
18000: { uae_s8 dst = m68k_dreg(regs, dstreg);
18001: src |= dst;
18002: CLEAR_CZNV;
18003: SET_ZFLG (((uae_s8)(src)) == 0);
18004: SET_NFLG (((uae_s8)(src)) < 0);
18005: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
18006: }}}}m68k_incpc(4);
18007: return 12;
18008: }
18009: unsigned long REGPARAM2 CPUFUNC(op_803b_0)(uae_u32 opcode) /* OR */
18010: {
18011: uae_u32 dstreg = (opcode >> 9) & 7;
18012: OpcodeFamily = 1; CurrentInstrCycles = 14;
18013: {{m68k_incpc(2);
18014: { uaecptr tmppc = m68k_getpc();
18015: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
18016: BusCyclePenalty += 2;
18017: { uae_s8 src = get_byte(srca);
18018: { uae_s8 dst = m68k_dreg(regs, dstreg);
18019: src |= dst;
18020: CLEAR_CZNV;
18021: SET_ZFLG (((uae_s8)(src)) == 0);
18022: SET_NFLG (((uae_s8)(src)) < 0);
18023: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
18024: }}}}}return 14;
18025: }
18026: unsigned long REGPARAM2 CPUFUNC(op_803c_0)(uae_u32 opcode) /* OR */
18027: {
18028: uae_u32 dstreg = (opcode >> 9) & 7;
18029: OpcodeFamily = 1; CurrentInstrCycles = 8;
18030: {{ uae_s8 src = get_ibyte(2);
18031: { uae_s8 dst = m68k_dreg(regs, dstreg);
18032: src |= dst;
18033: CLEAR_CZNV;
18034: SET_ZFLG (((uae_s8)(src)) == 0);
18035: SET_NFLG (((uae_s8)(src)) < 0);
18036: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
18037: }}}m68k_incpc(4);
18038: return 8;
18039: }
18040: unsigned long REGPARAM2 CPUFUNC(op_8040_0)(uae_u32 opcode) /* OR */
18041: {
18042: uae_u32 srcreg = (opcode & 7);
18043: uae_u32 dstreg = (opcode >> 9) & 7;
18044: OpcodeFamily = 1; CurrentInstrCycles = 4;
18045: {{ uae_s16 src = m68k_dreg(regs, srcreg);
18046: { uae_s16 dst = m68k_dreg(regs, dstreg);
18047: src |= dst;
18048: CLEAR_CZNV;
18049: SET_ZFLG (((uae_s16)(src)) == 0);
18050: SET_NFLG (((uae_s16)(src)) < 0);
18051: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18052: }}}m68k_incpc(2);
18053: return 4;
18054: }
18055: unsigned long REGPARAM2 CPUFUNC(op_8050_0)(uae_u32 opcode) /* OR */
18056: {
18057: uae_u32 srcreg = (opcode & 7);
18058: uae_u32 dstreg = (opcode >> 9) & 7;
18059: OpcodeFamily = 1; CurrentInstrCycles = 8;
18060: {{ uaecptr srca = m68k_areg(regs, srcreg);
18061: { uae_s16 src = get_word(srca);
18062: { uae_s16 dst = m68k_dreg(regs, dstreg);
18063: src |= dst;
18064: CLEAR_CZNV;
18065: SET_ZFLG (((uae_s16)(src)) == 0);
18066: SET_NFLG (((uae_s16)(src)) < 0);
18067: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18068: }}}}m68k_incpc(2);
18069: return 8;
18070: }
18071: unsigned long REGPARAM2 CPUFUNC(op_8058_0)(uae_u32 opcode) /* OR */
18072: {
18073: uae_u32 srcreg = (opcode & 7);
18074: uae_u32 dstreg = (opcode >> 9) & 7;
18075: OpcodeFamily = 1; CurrentInstrCycles = 8;
18076: {{ uaecptr srca = m68k_areg(regs, srcreg);
18077: { uae_s16 src = get_word(srca);
18078: m68k_areg(regs, srcreg) += 2;
18079: { uae_s16 dst = m68k_dreg(regs, dstreg);
18080: src |= dst;
18081: CLEAR_CZNV;
18082: SET_ZFLG (((uae_s16)(src)) == 0);
18083: SET_NFLG (((uae_s16)(src)) < 0);
18084: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18085: }}}}m68k_incpc(2);
18086: return 8;
18087: }
18088: unsigned long REGPARAM2 CPUFUNC(op_8060_0)(uae_u32 opcode) /* OR */
18089: {
18090: uae_u32 srcreg = (opcode & 7);
18091: uae_u32 dstreg = (opcode >> 9) & 7;
18092: OpcodeFamily = 1; CurrentInstrCycles = 10;
18093: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
18094: { uae_s16 src = get_word(srca);
18095: m68k_areg (regs, srcreg) = srca;
18096: { uae_s16 dst = m68k_dreg(regs, dstreg);
18097: src |= dst;
18098: CLEAR_CZNV;
18099: SET_ZFLG (((uae_s16)(src)) == 0);
18100: SET_NFLG (((uae_s16)(src)) < 0);
18101: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18102: }}}}m68k_incpc(2);
18103: return 10;
18104: }
18105: unsigned long REGPARAM2 CPUFUNC(op_8068_0)(uae_u32 opcode) /* OR */
18106: {
18107: uae_u32 srcreg = (opcode & 7);
18108: uae_u32 dstreg = (opcode >> 9) & 7;
18109: OpcodeFamily = 1; CurrentInstrCycles = 12;
18110: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
18111: { uae_s16 src = get_word(srca);
18112: { uae_s16 dst = m68k_dreg(regs, dstreg);
18113: src |= dst;
18114: CLEAR_CZNV;
18115: SET_ZFLG (((uae_s16)(src)) == 0);
18116: SET_NFLG (((uae_s16)(src)) < 0);
18117: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18118: }}}}m68k_incpc(4);
18119: return 12;
18120: }
18121: unsigned long REGPARAM2 CPUFUNC(op_8070_0)(uae_u32 opcode) /* OR */
18122: {
18123: uae_u32 srcreg = (opcode & 7);
18124: uae_u32 dstreg = (opcode >> 9) & 7;
18125: OpcodeFamily = 1; CurrentInstrCycles = 14;
18126: {{m68k_incpc(2);
18127: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
18128: BusCyclePenalty += 2;
18129: { uae_s16 src = get_word(srca);
18130: { uae_s16 dst = m68k_dreg(regs, dstreg);
18131: src |= dst;
18132: CLEAR_CZNV;
18133: SET_ZFLG (((uae_s16)(src)) == 0);
18134: SET_NFLG (((uae_s16)(src)) < 0);
18135: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18136: }}}}}return 14;
18137: }
18138: unsigned long REGPARAM2 CPUFUNC(op_8078_0)(uae_u32 opcode) /* OR */
18139: {
18140: uae_u32 dstreg = (opcode >> 9) & 7;
18141: OpcodeFamily = 1; CurrentInstrCycles = 12;
18142: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
18143: { uae_s16 src = get_word(srca);
18144: { uae_s16 dst = m68k_dreg(regs, dstreg);
18145: src |= dst;
18146: CLEAR_CZNV;
18147: SET_ZFLG (((uae_s16)(src)) == 0);
18148: SET_NFLG (((uae_s16)(src)) < 0);
18149: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18150: }}}}m68k_incpc(4);
18151: return 12;
18152: }
18153: unsigned long REGPARAM2 CPUFUNC(op_8079_0)(uae_u32 opcode) /* OR */
18154: {
18155: uae_u32 dstreg = (opcode >> 9) & 7;
18156: OpcodeFamily = 1; CurrentInstrCycles = 16;
18157: {{ uaecptr srca = get_ilong(2);
18158: { uae_s16 src = get_word(srca);
18159: { uae_s16 dst = m68k_dreg(regs, dstreg);
18160: src |= dst;
18161: CLEAR_CZNV;
18162: SET_ZFLG (((uae_s16)(src)) == 0);
18163: SET_NFLG (((uae_s16)(src)) < 0);
18164: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18165: }}}}m68k_incpc(6);
18166: return 16;
18167: }
18168: unsigned long REGPARAM2 CPUFUNC(op_807a_0)(uae_u32 opcode) /* OR */
18169: {
18170: uae_u32 dstreg = (opcode >> 9) & 7;
18171: OpcodeFamily = 1; CurrentInstrCycles = 12;
18172: {{ uaecptr srca = m68k_getpc () + 2;
18173: srca += (uae_s32)(uae_s16)get_iword(2);
18174: { uae_s16 src = get_word(srca);
18175: { uae_s16 dst = m68k_dreg(regs, dstreg);
18176: src |= dst;
18177: CLEAR_CZNV;
18178: SET_ZFLG (((uae_s16)(src)) == 0);
18179: SET_NFLG (((uae_s16)(src)) < 0);
18180: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18181: }}}}m68k_incpc(4);
18182: return 12;
18183: }
18184: unsigned long REGPARAM2 CPUFUNC(op_807b_0)(uae_u32 opcode) /* OR */
18185: {
18186: uae_u32 dstreg = (opcode >> 9) & 7;
18187: OpcodeFamily = 1; CurrentInstrCycles = 14;
18188: {{m68k_incpc(2);
18189: { uaecptr tmppc = m68k_getpc();
18190: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
18191: BusCyclePenalty += 2;
18192: { uae_s16 src = get_word(srca);
18193: { uae_s16 dst = m68k_dreg(regs, dstreg);
18194: src |= dst;
18195: CLEAR_CZNV;
18196: SET_ZFLG (((uae_s16)(src)) == 0);
18197: SET_NFLG (((uae_s16)(src)) < 0);
18198: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18199: }}}}}return 14;
18200: }
18201: unsigned long REGPARAM2 CPUFUNC(op_807c_0)(uae_u32 opcode) /* OR */
18202: {
18203: uae_u32 dstreg = (opcode >> 9) & 7;
18204: OpcodeFamily = 1; CurrentInstrCycles = 8;
18205: {{ uae_s16 src = get_iword(2);
18206: { uae_s16 dst = m68k_dreg(regs, dstreg);
18207: src |= dst;
18208: CLEAR_CZNV;
18209: SET_ZFLG (((uae_s16)(src)) == 0);
18210: SET_NFLG (((uae_s16)(src)) < 0);
18211: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
18212: }}}m68k_incpc(4);
18213: return 8;
18214: }
18215: unsigned long REGPARAM2 CPUFUNC(op_8080_0)(uae_u32 opcode) /* OR */
18216: {
18217: uae_u32 srcreg = (opcode & 7);
18218: uae_u32 dstreg = (opcode >> 9) & 7;
18219: OpcodeFamily = 1; CurrentInstrCycles = 8;
18220: {{ uae_s32 src = m68k_dreg(regs, srcreg);
18221: { uae_s32 dst = m68k_dreg(regs, dstreg);
18222: src |= dst;
18223: CLEAR_CZNV;
18224: SET_ZFLG (((uae_s32)(src)) == 0);
18225: SET_NFLG (((uae_s32)(src)) < 0);
18226: m68k_dreg(regs, dstreg) = (src);
18227: }}}m68k_incpc(2);
18228: return 8;
18229: }
18230: unsigned long REGPARAM2 CPUFUNC(op_8090_0)(uae_u32 opcode) /* OR */
18231: {
18232: uae_u32 srcreg = (opcode & 7);
18233: uae_u32 dstreg = (opcode >> 9) & 7;
18234: OpcodeFamily = 1; CurrentInstrCycles = 14;
18235: {{ uaecptr srca = m68k_areg(regs, srcreg);
18236: { uae_s32 src = get_long(srca);
18237: { uae_s32 dst = m68k_dreg(regs, dstreg);
18238: src |= dst;
18239: CLEAR_CZNV;
18240: SET_ZFLG (((uae_s32)(src)) == 0);
18241: SET_NFLG (((uae_s32)(src)) < 0);
18242: m68k_dreg(regs, dstreg) = (src);
18243: }}}}m68k_incpc(2);
18244: return 14;
18245: }
18246: unsigned long REGPARAM2 CPUFUNC(op_8098_0)(uae_u32 opcode) /* OR */
18247: {
18248: uae_u32 srcreg = (opcode & 7);
18249: uae_u32 dstreg = (opcode >> 9) & 7;
18250: OpcodeFamily = 1; CurrentInstrCycles = 14;
18251: {{ uaecptr srca = m68k_areg(regs, srcreg);
18252: { uae_s32 src = get_long(srca);
18253: m68k_areg(regs, srcreg) += 4;
18254: { uae_s32 dst = m68k_dreg(regs, dstreg);
18255: src |= dst;
18256: CLEAR_CZNV;
18257: SET_ZFLG (((uae_s32)(src)) == 0);
18258: SET_NFLG (((uae_s32)(src)) < 0);
18259: m68k_dreg(regs, dstreg) = (src);
18260: }}}}m68k_incpc(2);
18261: return 14;
18262: }
18263: unsigned long REGPARAM2 CPUFUNC(op_80a0_0)(uae_u32 opcode) /* OR */
18264: {
18265: uae_u32 srcreg = (opcode & 7);
18266: uae_u32 dstreg = (opcode >> 9) & 7;
18267: OpcodeFamily = 1; CurrentInstrCycles = 16;
18268: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
18269: { uae_s32 src = get_long(srca);
18270: m68k_areg (regs, srcreg) = srca;
18271: { uae_s32 dst = m68k_dreg(regs, dstreg);
18272: src |= dst;
18273: CLEAR_CZNV;
18274: SET_ZFLG (((uae_s32)(src)) == 0);
18275: SET_NFLG (((uae_s32)(src)) < 0);
18276: m68k_dreg(regs, dstreg) = (src);
18277: }}}}m68k_incpc(2);
18278: return 16;
18279: }
18280: unsigned long REGPARAM2 CPUFUNC(op_80a8_0)(uae_u32 opcode) /* OR */
18281: {
18282: uae_u32 srcreg = (opcode & 7);
18283: uae_u32 dstreg = (opcode >> 9) & 7;
18284: OpcodeFamily = 1; CurrentInstrCycles = 18;
18285: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
18286: { uae_s32 src = get_long(srca);
18287: { uae_s32 dst = m68k_dreg(regs, dstreg);
18288: src |= dst;
18289: CLEAR_CZNV;
18290: SET_ZFLG (((uae_s32)(src)) == 0);
18291: SET_NFLG (((uae_s32)(src)) < 0);
18292: m68k_dreg(regs, dstreg) = (src);
18293: }}}}m68k_incpc(4);
18294: return 18;
18295: }
18296: unsigned long REGPARAM2 CPUFUNC(op_80b0_0)(uae_u32 opcode) /* OR */
18297: {
18298: uae_u32 srcreg = (opcode & 7);
18299: uae_u32 dstreg = (opcode >> 9) & 7;
18300: OpcodeFamily = 1; CurrentInstrCycles = 20;
18301: {{m68k_incpc(2);
18302: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
18303: BusCyclePenalty += 2;
18304: { uae_s32 src = get_long(srca);
18305: { uae_s32 dst = m68k_dreg(regs, dstreg);
18306: src |= dst;
18307: CLEAR_CZNV;
18308: SET_ZFLG (((uae_s32)(src)) == 0);
18309: SET_NFLG (((uae_s32)(src)) < 0);
18310: m68k_dreg(regs, dstreg) = (src);
18311: }}}}}return 20;
18312: }
18313: unsigned long REGPARAM2 CPUFUNC(op_80b8_0)(uae_u32 opcode) /* OR */
18314: {
18315: uae_u32 dstreg = (opcode >> 9) & 7;
18316: OpcodeFamily = 1; CurrentInstrCycles = 18;
18317: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
18318: { uae_s32 src = get_long(srca);
18319: { uae_s32 dst = m68k_dreg(regs, dstreg);
18320: src |= dst;
18321: CLEAR_CZNV;
18322: SET_ZFLG (((uae_s32)(src)) == 0);
18323: SET_NFLG (((uae_s32)(src)) < 0);
18324: m68k_dreg(regs, dstreg) = (src);
18325: }}}}m68k_incpc(4);
18326: return 18;
18327: }
18328: unsigned long REGPARAM2 CPUFUNC(op_80b9_0)(uae_u32 opcode) /* OR */
18329: {
18330: uae_u32 dstreg = (opcode >> 9) & 7;
18331: OpcodeFamily = 1; CurrentInstrCycles = 22;
18332: {{ uaecptr srca = get_ilong(2);
18333: { uae_s32 src = get_long(srca);
18334: { uae_s32 dst = m68k_dreg(regs, dstreg);
18335: src |= dst;
18336: CLEAR_CZNV;
18337: SET_ZFLG (((uae_s32)(src)) == 0);
18338: SET_NFLG (((uae_s32)(src)) < 0);
18339: m68k_dreg(regs, dstreg) = (src);
18340: }}}}m68k_incpc(6);
18341: return 22;
18342: }
18343: unsigned long REGPARAM2 CPUFUNC(op_80ba_0)(uae_u32 opcode) /* OR */
18344: {
18345: uae_u32 dstreg = (opcode >> 9) & 7;
18346: OpcodeFamily = 1; CurrentInstrCycles = 18;
18347: {{ uaecptr srca = m68k_getpc () + 2;
18348: srca += (uae_s32)(uae_s16)get_iword(2);
18349: { uae_s32 src = get_long(srca);
18350: { uae_s32 dst = m68k_dreg(regs, dstreg);
18351: src |= dst;
18352: CLEAR_CZNV;
18353: SET_ZFLG (((uae_s32)(src)) == 0);
18354: SET_NFLG (((uae_s32)(src)) < 0);
18355: m68k_dreg(regs, dstreg) = (src);
18356: }}}}m68k_incpc(4);
18357: return 18;
18358: }
18359: unsigned long REGPARAM2 CPUFUNC(op_80bb_0)(uae_u32 opcode) /* OR */
18360: {
18361: uae_u32 dstreg = (opcode >> 9) & 7;
18362: OpcodeFamily = 1; CurrentInstrCycles = 20;
18363: {{m68k_incpc(2);
18364: { uaecptr tmppc = m68k_getpc();
18365: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
18366: BusCyclePenalty += 2;
18367: { uae_s32 src = get_long(srca);
18368: { uae_s32 dst = m68k_dreg(regs, dstreg);
18369: src |= dst;
18370: CLEAR_CZNV;
18371: SET_ZFLG (((uae_s32)(src)) == 0);
18372: SET_NFLG (((uae_s32)(src)) < 0);
18373: m68k_dreg(regs, dstreg) = (src);
18374: }}}}}return 20;
18375: }
18376: unsigned long REGPARAM2 CPUFUNC(op_80bc_0)(uae_u32 opcode) /* OR */
18377: {
18378: uae_u32 dstreg = (opcode >> 9) & 7;
18379: OpcodeFamily = 1; CurrentInstrCycles = 16;
18380: {{ uae_s32 src = get_ilong(2);
18381: { uae_s32 dst = m68k_dreg(regs, dstreg);
18382: src |= dst;
18383: CLEAR_CZNV;
18384: SET_ZFLG (((uae_s32)(src)) == 0);
18385: SET_NFLG (((uae_s32)(src)) < 0);
18386: m68k_dreg(regs, dstreg) = (src);
18387: }}}m68k_incpc(6);
18388: return 16;
18389: }
18390: unsigned long REGPARAM2 CPUFUNC(op_80c0_0)(uae_u32 opcode) /* DIVU */
18391: {
18392: uae_u32 srcreg = (opcode & 7);
18393: uae_u32 dstreg = (opcode >> 9) & 7;
18394: unsigned int retcycles = 0;
18395: OpcodeFamily = 60; CurrentInstrCycles = 4;
18396: { uaecptr oldpc = m68k_getpc();
18397: { uae_s16 src = m68k_dreg(regs, srcreg);
18398: { uae_s32 dst = m68k_dreg(regs, dstreg);
18399: m68k_incpc(2);
18400: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1261; } else {
18401: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18402: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18403: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18404: {
18405: CLEAR_CZNV;
18406: SET_ZFLG (((uae_s16)(newv)) == 0);
18407: SET_NFLG (((uae_s16)(newv)) < 0);
18408: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18409: m68k_dreg(regs, dstreg) = (newv);
18410: }
18411: }
18412: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18413: }}}endlabel1261: ;
18414: return (4+retcycles);
18415: }
18416: unsigned long REGPARAM2 CPUFUNC(op_80d0_0)(uae_u32 opcode) /* DIVU */
18417: {
18418: uae_u32 srcreg = (opcode & 7);
18419: uae_u32 dstreg = (opcode >> 9) & 7;
18420: unsigned int retcycles = 0;
18421: OpcodeFamily = 60; CurrentInstrCycles = 8;
18422: { uaecptr oldpc = m68k_getpc();
18423: { uaecptr srca = m68k_areg(regs, srcreg);
18424: { uae_s16 src = get_word(srca);
18425: { uae_s32 dst = m68k_dreg(regs, dstreg);
18426: m68k_incpc(2);
18427: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1262; } else {
18428: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18429: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18430: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18431: {
18432: CLEAR_CZNV;
18433: SET_ZFLG (((uae_s16)(newv)) == 0);
18434: SET_NFLG (((uae_s16)(newv)) < 0);
18435: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18436: m68k_dreg(regs, dstreg) = (newv);
18437: }
18438: }
18439: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18440: }}}}endlabel1262: ;
18441: return (8+retcycles);
18442: }
18443: unsigned long REGPARAM2 CPUFUNC(op_80d8_0)(uae_u32 opcode) /* DIVU */
18444: {
18445: uae_u32 srcreg = (opcode & 7);
18446: uae_u32 dstreg = (opcode >> 9) & 7;
18447: unsigned int retcycles = 0;
18448: OpcodeFamily = 60; CurrentInstrCycles = 8;
18449: { uaecptr oldpc = m68k_getpc();
18450: { uaecptr srca = m68k_areg(regs, srcreg);
18451: { uae_s16 src = get_word(srca);
18452: m68k_areg(regs, srcreg) += 2;
18453: { uae_s32 dst = m68k_dreg(regs, dstreg);
18454: m68k_incpc(2);
18455: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1263; } else {
18456: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18457: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18458: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18459: {
18460: CLEAR_CZNV;
18461: SET_ZFLG (((uae_s16)(newv)) == 0);
18462: SET_NFLG (((uae_s16)(newv)) < 0);
18463: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18464: m68k_dreg(regs, dstreg) = (newv);
18465: }
18466: }
18467: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18468: }}}}endlabel1263: ;
18469: return (8+retcycles);
18470: }
18471: unsigned long REGPARAM2 CPUFUNC(op_80e0_0)(uae_u32 opcode) /* DIVU */
18472: {
18473: uae_u32 srcreg = (opcode & 7);
18474: uae_u32 dstreg = (opcode >> 9) & 7;
18475: unsigned int retcycles = 0;
18476: OpcodeFamily = 60; CurrentInstrCycles = 10;
18477: { uaecptr oldpc = m68k_getpc();
18478: { uaecptr srca = m68k_areg(regs, srcreg) - 2;
18479: { uae_s16 src = get_word(srca);
18480: m68k_areg (regs, srcreg) = srca;
18481: { uae_s32 dst = m68k_dreg(regs, dstreg);
18482: m68k_incpc(2);
18483: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1264; } else {
18484: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18485: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18486: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18487: {
18488: CLEAR_CZNV;
18489: SET_ZFLG (((uae_s16)(newv)) == 0);
18490: SET_NFLG (((uae_s16)(newv)) < 0);
18491: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18492: m68k_dreg(regs, dstreg) = (newv);
18493: }
18494: }
18495: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18496: }}}}endlabel1264: ;
18497: return (10+retcycles);
18498: }
18499: unsigned long REGPARAM2 CPUFUNC(op_80e8_0)(uae_u32 opcode) /* DIVU */
18500: {
18501: uae_u32 srcreg = (opcode & 7);
18502: uae_u32 dstreg = (opcode >> 9) & 7;
18503: unsigned int retcycles = 0;
18504: OpcodeFamily = 60; CurrentInstrCycles = 12;
18505: { uaecptr oldpc = m68k_getpc();
18506: { uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
18507: { uae_s16 src = get_word(srca);
18508: { uae_s32 dst = m68k_dreg(regs, dstreg);
18509: m68k_incpc(4);
18510: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1265; } else {
18511: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18512: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18513: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18514: {
18515: CLEAR_CZNV;
18516: SET_ZFLG (((uae_s16)(newv)) == 0);
18517: SET_NFLG (((uae_s16)(newv)) < 0);
18518: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18519: m68k_dreg(regs, dstreg) = (newv);
18520: }
18521: }
18522: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18523: }}}}endlabel1265: ;
18524: return (12+retcycles);
18525: }
18526: unsigned long REGPARAM2 CPUFUNC(op_80f0_0)(uae_u32 opcode) /* DIVU */
18527: {
18528: uae_u32 srcreg = (opcode & 7);
18529: uae_u32 dstreg = (opcode >> 9) & 7;
18530: unsigned int retcycles = 0;
18531: OpcodeFamily = 60; CurrentInstrCycles = 14;
18532: { uaecptr oldpc = m68k_getpc();
18533: {m68k_incpc(2);
18534: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
18535: BusCyclePenalty += 2;
18536: { uae_s16 src = get_word(srca);
18537: { uae_s32 dst = m68k_dreg(regs, dstreg);
18538: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1266; } else {
18539: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18540: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18541: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18542: {
18543: CLEAR_CZNV;
18544: SET_ZFLG (((uae_s16)(newv)) == 0);
18545: SET_NFLG (((uae_s16)(newv)) < 0);
18546: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18547: m68k_dreg(regs, dstreg) = (newv);
18548: }
18549: }
18550: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18551: }}}}}endlabel1266: ;
18552: return (14+retcycles);
18553: }
18554: unsigned long REGPARAM2 CPUFUNC(op_80f8_0)(uae_u32 opcode) /* DIVU */
18555: {
18556: uae_u32 dstreg = (opcode >> 9) & 7;
18557: unsigned int retcycles = 0;
18558: OpcodeFamily = 60; CurrentInstrCycles = 12;
18559: { uaecptr oldpc = m68k_getpc();
18560: { uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
18561: { uae_s16 src = get_word(srca);
18562: { uae_s32 dst = m68k_dreg(regs, dstreg);
18563: m68k_incpc(4);
18564: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1267; } else {
18565: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18566: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18567: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18568: {
18569: CLEAR_CZNV;
18570: SET_ZFLG (((uae_s16)(newv)) == 0);
18571: SET_NFLG (((uae_s16)(newv)) < 0);
18572: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18573: m68k_dreg(regs, dstreg) = (newv);
18574: }
18575: }
18576: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18577: }}}}endlabel1267: ;
18578: return (12+retcycles);
18579: }
18580: unsigned long REGPARAM2 CPUFUNC(op_80f9_0)(uae_u32 opcode) /* DIVU */
18581: {
18582: uae_u32 dstreg = (opcode >> 9) & 7;
18583: unsigned int retcycles = 0;
18584: OpcodeFamily = 60; CurrentInstrCycles = 16;
18585: { uaecptr oldpc = m68k_getpc();
18586: { uaecptr srca = get_ilong(2);
18587: { uae_s16 src = get_word(srca);
18588: { uae_s32 dst = m68k_dreg(regs, dstreg);
18589: m68k_incpc(6);
18590: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1268; } else {
18591: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18592: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18593: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18594: {
18595: CLEAR_CZNV;
18596: SET_ZFLG (((uae_s16)(newv)) == 0);
18597: SET_NFLG (((uae_s16)(newv)) < 0);
18598: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18599: m68k_dreg(regs, dstreg) = (newv);
18600: }
18601: }
18602: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18603: }}}}endlabel1268: ;
18604: return (16+retcycles);
18605: }
18606: unsigned long REGPARAM2 CPUFUNC(op_80fa_0)(uae_u32 opcode) /* DIVU */
18607: {
18608: uae_u32 dstreg = (opcode >> 9) & 7;
18609: unsigned int retcycles = 0;
18610: OpcodeFamily = 60; CurrentInstrCycles = 12;
18611: { uaecptr oldpc = m68k_getpc();
18612: { uaecptr srca = m68k_getpc () + 2;
18613: srca += (uae_s32)(uae_s16)get_iword(2);
18614: { uae_s16 src = get_word(srca);
18615: { uae_s32 dst = m68k_dreg(regs, dstreg);
18616: m68k_incpc(4);
18617: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1269; } else {
18618: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18619: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18620: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18621: {
18622: CLEAR_CZNV;
18623: SET_ZFLG (((uae_s16)(newv)) == 0);
18624: SET_NFLG (((uae_s16)(newv)) < 0);
18625: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18626: m68k_dreg(regs, dstreg) = (newv);
18627: }
18628: }
18629: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18630: }}}}endlabel1269: ;
18631: return (12+retcycles);
18632: }
18633: unsigned long REGPARAM2 CPUFUNC(op_80fb_0)(uae_u32 opcode) /* DIVU */
18634: {
18635: uae_u32 dstreg = (opcode >> 9) & 7;
18636: unsigned int retcycles = 0;
18637: OpcodeFamily = 60; CurrentInstrCycles = 14;
18638: { uaecptr oldpc = m68k_getpc();
18639: {m68k_incpc(2);
18640: { uaecptr tmppc = m68k_getpc();
18641: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
18642: BusCyclePenalty += 2;
18643: { uae_s16 src = get_word(srca);
18644: { uae_s32 dst = m68k_dreg(regs, dstreg);
18645: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1270; } else {
18646: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18647: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18648: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18649: {
18650: CLEAR_CZNV;
18651: SET_ZFLG (((uae_s16)(newv)) == 0);
18652: SET_NFLG (((uae_s16)(newv)) < 0);
18653: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18654: m68k_dreg(regs, dstreg) = (newv);
18655: }
18656: }
18657: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18658: }}}}}endlabel1270: ;
18659: return (14+retcycles);
18660: }
18661: unsigned long REGPARAM2 CPUFUNC(op_80fc_0)(uae_u32 opcode) /* DIVU */
18662: {
18663: uae_u32 dstreg = (opcode >> 9) & 7;
18664: unsigned int retcycles = 0;
18665: OpcodeFamily = 60; CurrentInstrCycles = 8;
18666: { uaecptr oldpc = m68k_getpc();
18667: { uae_s16 src = get_iword(2);
18668: { uae_s32 dst = m68k_dreg(regs, dstreg);
18669: m68k_incpc(4);
18670: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1271; } else {
18671: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
18672: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
18673: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
18674: {
18675: CLEAR_CZNV;
18676: SET_ZFLG (((uae_s16)(newv)) == 0);
18677: SET_NFLG (((uae_s16)(newv)) < 0);
18678: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
18679: m68k_dreg(regs, dstreg) = (newv);
18680: }
18681: }
18682: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
18683: }}}endlabel1271: ;
18684: return (8+retcycles);
18685: }
18686: unsigned long REGPARAM2 CPUFUNC(op_8100_0)(uae_u32 opcode) /* SBCD */
18687: {
18688: uae_u32 srcreg = (opcode & 7);
18689: uae_u32 dstreg = (opcode >> 9) & 7;
18690: OpcodeFamily = 10; CurrentInstrCycles = 6;
18691: {{ uae_s8 src = m68k_dreg(regs, srcreg);
18692: { uae_s8 dst = m68k_dreg(regs, dstreg);
18693: { uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);
18694: uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
18695: uae_u16 newv, tmp_newv;
18696: int bcd = 0;
18697: newv = tmp_newv = newv_hi + newv_lo;
18698: if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
18699: if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
18700: SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);
18701: COPY_CARRY;
18702: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
18703: SET_NFLG (((uae_s8)(newv)) < 0);
18704: SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
18705: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
18706: }}}}m68k_incpc(2);
18707: return 6;
18708: }
18709: unsigned long REGPARAM2 CPUFUNC(op_8108_0)(uae_u32 opcode) /* SBCD */
18710: {
18711: uae_u32 srcreg = (opcode & 7);
18712: uae_u32 dstreg = (opcode >> 9) & 7;
18713: OpcodeFamily = 10; CurrentInstrCycles = 18;
18714: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
18715: { uae_s8 src = get_byte(srca);
18716: m68k_areg (regs, srcreg) = srca;
18717: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
18718: { uae_s8 dst = get_byte(dsta);
18719: m68k_areg (regs, dstreg) = dsta;
18720: { uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);
18721: uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
18722: uae_u16 newv, tmp_newv;
18723: int bcd = 0;
18724: newv = tmp_newv = newv_hi + newv_lo;
18725: if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
18726: if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
18727: SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);
18728: COPY_CARRY;
18729: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
18730: SET_NFLG (((uae_s8)(newv)) < 0);
18731: SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
18732: put_byte(dsta,newv);
18733: }}}}}}m68k_incpc(2);
18734: return 18;
18735: }
18736: unsigned long REGPARAM2 CPUFUNC(op_8110_0)(uae_u32 opcode) /* OR */
18737: {
18738: uae_u32 srcreg = ((opcode >> 9) & 7);
18739: uae_u32 dstreg = opcode & 7;
18740: OpcodeFamily = 1; CurrentInstrCycles = 12;
18741: {{ uae_s8 src = m68k_dreg(regs, srcreg);
18742: { uaecptr dsta = m68k_areg(regs, dstreg);
18743: { uae_s8 dst = get_byte(dsta);
18744: src |= dst;
18745: CLEAR_CZNV;
18746: SET_ZFLG (((uae_s8)(src)) == 0);
18747: SET_NFLG (((uae_s8)(src)) < 0);
18748: put_byte(dsta,src);
18749: }}}}m68k_incpc(2);
18750: return 12;
18751: }
18752: unsigned long REGPARAM2 CPUFUNC(op_8118_0)(uae_u32 opcode) /* OR */
18753: {
18754: uae_u32 srcreg = ((opcode >> 9) & 7);
18755: uae_u32 dstreg = opcode & 7;
18756: OpcodeFamily = 1; CurrentInstrCycles = 12;
18757: {{ uae_s8 src = m68k_dreg(regs, srcreg);
18758: { uaecptr dsta = m68k_areg(regs, dstreg);
18759: { uae_s8 dst = get_byte(dsta);
18760: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
18761: src |= dst;
18762: CLEAR_CZNV;
18763: SET_ZFLG (((uae_s8)(src)) == 0);
18764: SET_NFLG (((uae_s8)(src)) < 0);
18765: put_byte(dsta,src);
18766: }}}}m68k_incpc(2);
18767: return 12;
18768: }
18769: unsigned long REGPARAM2 CPUFUNC(op_8120_0)(uae_u32 opcode) /* OR */
18770: {
18771: uae_u32 srcreg = ((opcode >> 9) & 7);
18772: uae_u32 dstreg = opcode & 7;
18773: OpcodeFamily = 1; CurrentInstrCycles = 14;
18774: {{ uae_s8 src = m68k_dreg(regs, srcreg);
18775: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
18776: { uae_s8 dst = get_byte(dsta);
18777: m68k_areg (regs, dstreg) = dsta;
18778: src |= dst;
18779: CLEAR_CZNV;
18780: SET_ZFLG (((uae_s8)(src)) == 0);
18781: SET_NFLG (((uae_s8)(src)) < 0);
18782: put_byte(dsta,src);
18783: }}}}m68k_incpc(2);
18784: return 14;
18785: }
18786: unsigned long REGPARAM2 CPUFUNC(op_8128_0)(uae_u32 opcode) /* OR */
18787: {
18788: uae_u32 srcreg = ((opcode >> 9) & 7);
18789: uae_u32 dstreg = opcode & 7;
18790: OpcodeFamily = 1; CurrentInstrCycles = 16;
18791: {{ uae_s8 src = m68k_dreg(regs, srcreg);
18792: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
18793: { uae_s8 dst = get_byte(dsta);
18794: src |= dst;
18795: CLEAR_CZNV;
18796: SET_ZFLG (((uae_s8)(src)) == 0);
18797: SET_NFLG (((uae_s8)(src)) < 0);
18798: put_byte(dsta,src);
18799: }}}}m68k_incpc(4);
18800: return 16;
18801: }
18802: unsigned long REGPARAM2 CPUFUNC(op_8130_0)(uae_u32 opcode) /* OR */
18803: {
18804: uae_u32 srcreg = ((opcode >> 9) & 7);
18805: uae_u32 dstreg = opcode & 7;
18806: OpcodeFamily = 1; CurrentInstrCycles = 18;
18807: {{ uae_s8 src = m68k_dreg(regs, srcreg);
18808: {m68k_incpc(2);
18809: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
18810: BusCyclePenalty += 2;
18811: { uae_s8 dst = get_byte(dsta);
18812: src |= dst;
18813: CLEAR_CZNV;
18814: SET_ZFLG (((uae_s8)(src)) == 0);
18815: SET_NFLG (((uae_s8)(src)) < 0);
18816: put_byte(dsta,src);
18817: }}}}}return 18;
18818: }
18819: unsigned long REGPARAM2 CPUFUNC(op_8138_0)(uae_u32 opcode) /* OR */
18820: {
18821: uae_u32 srcreg = ((opcode >> 9) & 7);
18822: OpcodeFamily = 1; CurrentInstrCycles = 16;
18823: {{ uae_s8 src = m68k_dreg(regs, srcreg);
18824: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
18825: { uae_s8 dst = get_byte(dsta);
18826: src |= dst;
18827: CLEAR_CZNV;
18828: SET_ZFLG (((uae_s8)(src)) == 0);
18829: SET_NFLG (((uae_s8)(src)) < 0);
18830: put_byte(dsta,src);
18831: }}}}m68k_incpc(4);
18832: return 16;
18833: }
18834: unsigned long REGPARAM2 CPUFUNC(op_8139_0)(uae_u32 opcode) /* OR */
18835: {
18836: uae_u32 srcreg = ((opcode >> 9) & 7);
18837: OpcodeFamily = 1; CurrentInstrCycles = 20;
18838: {{ uae_s8 src = m68k_dreg(regs, srcreg);
18839: { uaecptr dsta = get_ilong(2);
18840: { uae_s8 dst = get_byte(dsta);
18841: src |= dst;
18842: CLEAR_CZNV;
18843: SET_ZFLG (((uae_s8)(src)) == 0);
18844: SET_NFLG (((uae_s8)(src)) < 0);
18845: put_byte(dsta,src);
18846: }}}}m68k_incpc(6);
18847: return 20;
18848: }
18849: unsigned long REGPARAM2 CPUFUNC(op_8140_0)(uae_u32 opcode) /* PACK */
18850: {
18851: uae_u32 srcreg = (opcode & 7);
18852: uae_u32 dstreg = (opcode >> 9) & 7;
18853: OpcodeFamily = 96; CurrentInstrCycles = 8;
18854: { uae_u16 val = m68k_dreg(regs, srcreg) + get_iword(2);
18855: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
18856: }m68k_incpc(4);
18857: return 8;
18858: }
18859: unsigned long REGPARAM2 CPUFUNC(op_8148_0)(uae_u32 opcode) /* PACK */
18860: {
18861: uae_u32 srcreg = (opcode & 7);
18862: uae_u32 dstreg = (opcode >> 9) & 7;
18863: OpcodeFamily = 96; CurrentInstrCycles = 8;
18864: { uae_u16 val;
18865: m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];
18866: val = (uae_u16)get_byte(m68k_areg(regs, srcreg));
18867: m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];
18868: val = (val | ((uae_u16)get_byte(m68k_areg(regs, srcreg)) << 8)) + get_iword(2);
18869: m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
18870: put_byte(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
18871: }m68k_incpc(4);
18872: return 8;
18873: }
18874: unsigned long REGPARAM2 CPUFUNC(op_8150_0)(uae_u32 opcode) /* OR */
18875: {
18876: uae_u32 srcreg = ((opcode >> 9) & 7);
18877: uae_u32 dstreg = opcode & 7;
18878: OpcodeFamily = 1; CurrentInstrCycles = 12;
18879: {{ uae_s16 src = m68k_dreg(regs, srcreg);
18880: { uaecptr dsta = m68k_areg(regs, dstreg);
18881: { uae_s16 dst = get_word(dsta);
18882: src |= dst;
18883: CLEAR_CZNV;
18884: SET_ZFLG (((uae_s16)(src)) == 0);
18885: SET_NFLG (((uae_s16)(src)) < 0);
18886: put_word(dsta,src);
18887: }}}}m68k_incpc(2);
18888: return 12;
18889: }
18890: unsigned long REGPARAM2 CPUFUNC(op_8158_0)(uae_u32 opcode) /* OR */
18891: {
18892: uae_u32 srcreg = ((opcode >> 9) & 7);
18893: uae_u32 dstreg = opcode & 7;
18894: OpcodeFamily = 1; CurrentInstrCycles = 12;
18895: {{ uae_s16 src = m68k_dreg(regs, srcreg);
18896: { uaecptr dsta = m68k_areg(regs, dstreg);
18897: { uae_s16 dst = get_word(dsta);
18898: m68k_areg(regs, dstreg) += 2;
18899: src |= dst;
18900: CLEAR_CZNV;
18901: SET_ZFLG (((uae_s16)(src)) == 0);
18902: SET_NFLG (((uae_s16)(src)) < 0);
18903: put_word(dsta,src);
18904: }}}}m68k_incpc(2);
18905: return 12;
18906: }
18907: unsigned long REGPARAM2 CPUFUNC(op_8160_0)(uae_u32 opcode) /* OR */
18908: {
18909: uae_u32 srcreg = ((opcode >> 9) & 7);
18910: uae_u32 dstreg = opcode & 7;
18911: OpcodeFamily = 1; CurrentInstrCycles = 14;
18912: {{ uae_s16 src = m68k_dreg(regs, srcreg);
18913: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
18914: { uae_s16 dst = get_word(dsta);
18915: m68k_areg (regs, dstreg) = dsta;
18916: src |= dst;
18917: CLEAR_CZNV;
18918: SET_ZFLG (((uae_s16)(src)) == 0);
18919: SET_NFLG (((uae_s16)(src)) < 0);
18920: put_word(dsta,src);
18921: }}}}m68k_incpc(2);
18922: return 14;
18923: }
18924: unsigned long REGPARAM2 CPUFUNC(op_8168_0)(uae_u32 opcode) /* OR */
18925: {
18926: uae_u32 srcreg = ((opcode >> 9) & 7);
18927: uae_u32 dstreg = opcode & 7;
18928: OpcodeFamily = 1; CurrentInstrCycles = 16;
18929: {{ uae_s16 src = m68k_dreg(regs, srcreg);
18930: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
18931: { uae_s16 dst = get_word(dsta);
18932: src |= dst;
18933: CLEAR_CZNV;
18934: SET_ZFLG (((uae_s16)(src)) == 0);
18935: SET_NFLG (((uae_s16)(src)) < 0);
18936: put_word(dsta,src);
18937: }}}}m68k_incpc(4);
18938: return 16;
18939: }
18940: unsigned long REGPARAM2 CPUFUNC(op_8170_0)(uae_u32 opcode) /* OR */
18941: {
18942: uae_u32 srcreg = ((opcode >> 9) & 7);
18943: uae_u32 dstreg = opcode & 7;
18944: OpcodeFamily = 1; CurrentInstrCycles = 18;
18945: {{ uae_s16 src = m68k_dreg(regs, srcreg);
18946: {m68k_incpc(2);
18947: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
18948: BusCyclePenalty += 2;
18949: { uae_s16 dst = get_word(dsta);
18950: src |= dst;
18951: CLEAR_CZNV;
18952: SET_ZFLG (((uae_s16)(src)) == 0);
18953: SET_NFLG (((uae_s16)(src)) < 0);
18954: put_word(dsta,src);
18955: }}}}}return 18;
18956: }
18957: unsigned long REGPARAM2 CPUFUNC(op_8178_0)(uae_u32 opcode) /* OR */
18958: {
18959: uae_u32 srcreg = ((opcode >> 9) & 7);
18960: OpcodeFamily = 1; CurrentInstrCycles = 16;
18961: {{ uae_s16 src = m68k_dreg(regs, srcreg);
18962: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
18963: { uae_s16 dst = get_word(dsta);
18964: src |= dst;
18965: CLEAR_CZNV;
18966: SET_ZFLG (((uae_s16)(src)) == 0);
18967: SET_NFLG (((uae_s16)(src)) < 0);
18968: put_word(dsta,src);
18969: }}}}m68k_incpc(4);
18970: return 16;
18971: }
18972: unsigned long REGPARAM2 CPUFUNC(op_8179_0)(uae_u32 opcode) /* OR */
18973: {
18974: uae_u32 srcreg = ((opcode >> 9) & 7);
18975: OpcodeFamily = 1; CurrentInstrCycles = 20;
18976: {{ uae_s16 src = m68k_dreg(regs, srcreg);
18977: { uaecptr dsta = get_ilong(2);
18978: { uae_s16 dst = get_word(dsta);
18979: src |= dst;
18980: CLEAR_CZNV;
18981: SET_ZFLG (((uae_s16)(src)) == 0);
18982: SET_NFLG (((uae_s16)(src)) < 0);
18983: put_word(dsta,src);
18984: }}}}m68k_incpc(6);
18985: return 20;
18986: }
18987: unsigned long REGPARAM2 CPUFUNC(op_8180_0)(uae_u32 opcode) /* UNPK */
18988: {
18989: uae_u32 srcreg = (opcode & 7);
18990: uae_u32 dstreg = (opcode >> 9) & 7;
18991: OpcodeFamily = 97; CurrentInstrCycles = 8;
18992: { uae_u16 val = m68k_dreg(regs, srcreg);
18993: val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword(2);
18994: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);
18995: }m68k_incpc(4);
18996: return 8;
18997: }
18998: unsigned long REGPARAM2 CPUFUNC(op_8188_0)(uae_u32 opcode) /* UNPK */
18999: {
19000: uae_u32 srcreg = (opcode & 7);
19001: uae_u32 dstreg = (opcode >> 9) & 7;
19002: OpcodeFamily = 97; CurrentInstrCycles = 8;
19003: { uae_u16 val;
19004: m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];
19005: val = (uae_u16)get_byte(m68k_areg(regs, srcreg));
19006: val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword(2);
19007: m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
19008: put_byte(m68k_areg(regs, dstreg),val);
19009: m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
19010: put_byte(m68k_areg(regs, dstreg),val >> 8);
19011: }m68k_incpc(4);
19012: return 8;
19013: }
19014: unsigned long REGPARAM2 CPUFUNC(op_8190_0)(uae_u32 opcode) /* OR */
19015: {
19016: uae_u32 srcreg = ((opcode >> 9) & 7);
19017: uae_u32 dstreg = opcode & 7;
19018: OpcodeFamily = 1; CurrentInstrCycles = 20;
19019: {{ uae_s32 src = m68k_dreg(regs, srcreg);
19020: { uaecptr dsta = m68k_areg(regs, dstreg);
19021: { uae_s32 dst = get_long(dsta);
19022: src |= dst;
19023: CLEAR_CZNV;
19024: SET_ZFLG (((uae_s32)(src)) == 0);
19025: SET_NFLG (((uae_s32)(src)) < 0);
19026: put_long(dsta,src);
19027: }}}}m68k_incpc(2);
19028: return 20;
19029: }
19030: unsigned long REGPARAM2 CPUFUNC(op_8198_0)(uae_u32 opcode) /* OR */
19031: {
19032: uae_u32 srcreg = ((opcode >> 9) & 7);
19033: uae_u32 dstreg = opcode & 7;
19034: OpcodeFamily = 1; CurrentInstrCycles = 20;
19035: {{ uae_s32 src = m68k_dreg(regs, srcreg);
19036: { uaecptr dsta = m68k_areg(regs, dstreg);
19037: { uae_s32 dst = get_long(dsta);
19038: m68k_areg(regs, dstreg) += 4;
19039: src |= dst;
19040: CLEAR_CZNV;
19041: SET_ZFLG (((uae_s32)(src)) == 0);
19042: SET_NFLG (((uae_s32)(src)) < 0);
19043: put_long(dsta,src);
19044: }}}}m68k_incpc(2);
19045: return 20;
19046: }
19047: unsigned long REGPARAM2 CPUFUNC(op_81a0_0)(uae_u32 opcode) /* OR */
19048: {
19049: uae_u32 srcreg = ((opcode >> 9) & 7);
19050: uae_u32 dstreg = opcode & 7;
19051: OpcodeFamily = 1; CurrentInstrCycles = 22;
19052: {{ uae_s32 src = m68k_dreg(regs, srcreg);
19053: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
19054: { uae_s32 dst = get_long(dsta);
19055: m68k_areg (regs, dstreg) = dsta;
19056: src |= dst;
19057: CLEAR_CZNV;
19058: SET_ZFLG (((uae_s32)(src)) == 0);
19059: SET_NFLG (((uae_s32)(src)) < 0);
19060: put_long(dsta,src);
19061: }}}}m68k_incpc(2);
19062: return 22;
19063: }
19064: unsigned long REGPARAM2 CPUFUNC(op_81a8_0)(uae_u32 opcode) /* OR */
19065: {
19066: uae_u32 srcreg = ((opcode >> 9) & 7);
19067: uae_u32 dstreg = opcode & 7;
19068: OpcodeFamily = 1; CurrentInstrCycles = 24;
19069: {{ uae_s32 src = m68k_dreg(regs, srcreg);
19070: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
19071: { uae_s32 dst = get_long(dsta);
19072: src |= dst;
19073: CLEAR_CZNV;
19074: SET_ZFLG (((uae_s32)(src)) == 0);
19075: SET_NFLG (((uae_s32)(src)) < 0);
19076: put_long(dsta,src);
19077: }}}}m68k_incpc(4);
19078: return 24;
19079: }
19080: unsigned long REGPARAM2 CPUFUNC(op_81b0_0)(uae_u32 opcode) /* OR */
19081: {
19082: uae_u32 srcreg = ((opcode >> 9) & 7);
19083: uae_u32 dstreg = opcode & 7;
19084: OpcodeFamily = 1; CurrentInstrCycles = 26;
19085: {{ uae_s32 src = m68k_dreg(regs, srcreg);
19086: {m68k_incpc(2);
19087: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
19088: BusCyclePenalty += 2;
19089: { uae_s32 dst = get_long(dsta);
19090: src |= dst;
19091: CLEAR_CZNV;
19092: SET_ZFLG (((uae_s32)(src)) == 0);
19093: SET_NFLG (((uae_s32)(src)) < 0);
19094: put_long(dsta,src);
19095: }}}}}return 26;
19096: }
19097: unsigned long REGPARAM2 CPUFUNC(op_81b8_0)(uae_u32 opcode) /* OR */
19098: {
19099: uae_u32 srcreg = ((opcode >> 9) & 7);
19100: OpcodeFamily = 1; CurrentInstrCycles = 24;
19101: {{ uae_s32 src = m68k_dreg(regs, srcreg);
19102: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
19103: { uae_s32 dst = get_long(dsta);
19104: src |= dst;
19105: CLEAR_CZNV;
19106: SET_ZFLG (((uae_s32)(src)) == 0);
19107: SET_NFLG (((uae_s32)(src)) < 0);
19108: put_long(dsta,src);
19109: }}}}m68k_incpc(4);
19110: return 24;
19111: }
19112: unsigned long REGPARAM2 CPUFUNC(op_81b9_0)(uae_u32 opcode) /* OR */
19113: {
19114: uae_u32 srcreg = ((opcode >> 9) & 7);
19115: OpcodeFamily = 1; CurrentInstrCycles = 28;
19116: {{ uae_s32 src = m68k_dreg(regs, srcreg);
19117: { uaecptr dsta = get_ilong(2);
19118: { uae_s32 dst = get_long(dsta);
19119: src |= dst;
19120: CLEAR_CZNV;
19121: SET_ZFLG (((uae_s32)(src)) == 0);
19122: SET_NFLG (((uae_s32)(src)) < 0);
19123: put_long(dsta,src);
19124: }}}}m68k_incpc(6);
19125: return 28;
19126: }
19127: unsigned long REGPARAM2 CPUFUNC(op_81c0_0)(uae_u32 opcode) /* DIVS */
19128: {
19129: uae_u32 srcreg = (opcode & 7);
19130: uae_u32 dstreg = (opcode >> 9) & 7;
19131: unsigned int retcycles = 0;
19132: OpcodeFamily = 61; CurrentInstrCycles = 4;
19133: { uaecptr oldpc = m68k_getpc();
19134: { uae_s16 src = m68k_dreg(regs, srcreg);
19135: { uae_s32 dst = m68k_dreg(regs, dstreg);
19136: m68k_incpc(2);
19137: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1299; } else {
19138: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19139: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19140: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19141: {
19142: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19143: CLEAR_CZNV;
19144: SET_ZFLG (((uae_s16)(newv)) == 0);
19145: SET_NFLG (((uae_s16)(newv)) < 0);
19146: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19147: m68k_dreg(regs, dstreg) = (newv);
19148: }
19149: }
19150: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19151: }}}endlabel1299: ;
19152: return (4+retcycles);
19153: }
19154: unsigned long REGPARAM2 CPUFUNC(op_81d0_0)(uae_u32 opcode) /* DIVS */
19155: {
19156: uae_u32 srcreg = (opcode & 7);
19157: uae_u32 dstreg = (opcode >> 9) & 7;
19158: unsigned int retcycles = 0;
19159: OpcodeFamily = 61; CurrentInstrCycles = 8;
19160: { uaecptr oldpc = m68k_getpc();
19161: { uaecptr srca = m68k_areg(regs, srcreg);
19162: { uae_s16 src = get_word(srca);
19163: { uae_s32 dst = m68k_dreg(regs, dstreg);
19164: m68k_incpc(2);
19165: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1300; } else {
19166: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19167: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19168: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19169: {
19170: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19171: CLEAR_CZNV;
19172: SET_ZFLG (((uae_s16)(newv)) == 0);
19173: SET_NFLG (((uae_s16)(newv)) < 0);
19174: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19175: m68k_dreg(regs, dstreg) = (newv);
19176: }
19177: }
19178: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19179: }}}}endlabel1300: ;
19180: return (8+retcycles);
19181: }
19182: unsigned long REGPARAM2 CPUFUNC(op_81d8_0)(uae_u32 opcode) /* DIVS */
19183: {
19184: uae_u32 srcreg = (opcode & 7);
19185: uae_u32 dstreg = (opcode >> 9) & 7;
19186: unsigned int retcycles = 0;
19187: OpcodeFamily = 61; CurrentInstrCycles = 8;
19188: { uaecptr oldpc = m68k_getpc();
19189: { uaecptr srca = m68k_areg(regs, srcreg);
19190: { uae_s16 src = get_word(srca);
19191: m68k_areg(regs, srcreg) += 2;
19192: { uae_s32 dst = m68k_dreg(regs, dstreg);
19193: m68k_incpc(2);
19194: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1301; } else {
19195: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19196: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19197: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19198: {
19199: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19200: CLEAR_CZNV;
19201: SET_ZFLG (((uae_s16)(newv)) == 0);
19202: SET_NFLG (((uae_s16)(newv)) < 0);
19203: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19204: m68k_dreg(regs, dstreg) = (newv);
19205: }
19206: }
19207: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19208: }}}}endlabel1301: ;
19209: return (8+retcycles);
19210: }
19211: unsigned long REGPARAM2 CPUFUNC(op_81e0_0)(uae_u32 opcode) /* DIVS */
19212: {
19213: uae_u32 srcreg = (opcode & 7);
19214: uae_u32 dstreg = (opcode >> 9) & 7;
19215: unsigned int retcycles = 0;
19216: OpcodeFamily = 61; CurrentInstrCycles = 10;
19217: { uaecptr oldpc = m68k_getpc();
19218: { uaecptr srca = m68k_areg(regs, srcreg) - 2;
19219: { uae_s16 src = get_word(srca);
19220: m68k_areg (regs, srcreg) = srca;
19221: { uae_s32 dst = m68k_dreg(regs, dstreg);
19222: m68k_incpc(2);
19223: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1302; } else {
19224: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19225: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19226: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19227: {
19228: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19229: CLEAR_CZNV;
19230: SET_ZFLG (((uae_s16)(newv)) == 0);
19231: SET_NFLG (((uae_s16)(newv)) < 0);
19232: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19233: m68k_dreg(regs, dstreg) = (newv);
19234: }
19235: }
19236: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19237: }}}}endlabel1302: ;
19238: return (10+retcycles);
19239: }
19240: unsigned long REGPARAM2 CPUFUNC(op_81e8_0)(uae_u32 opcode) /* DIVS */
19241: {
19242: uae_u32 srcreg = (opcode & 7);
19243: uae_u32 dstreg = (opcode >> 9) & 7;
19244: unsigned int retcycles = 0;
19245: OpcodeFamily = 61; CurrentInstrCycles = 12;
19246: { uaecptr oldpc = m68k_getpc();
19247: { uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
19248: { uae_s16 src = get_word(srca);
19249: { uae_s32 dst = m68k_dreg(regs, dstreg);
19250: m68k_incpc(4);
19251: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1303; } else {
19252: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19253: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19254: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19255: {
19256: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19257: CLEAR_CZNV;
19258: SET_ZFLG (((uae_s16)(newv)) == 0);
19259: SET_NFLG (((uae_s16)(newv)) < 0);
19260: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19261: m68k_dreg(regs, dstreg) = (newv);
19262: }
19263: }
19264: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19265: }}}}endlabel1303: ;
19266: return (12+retcycles);
19267: }
19268: unsigned long REGPARAM2 CPUFUNC(op_81f0_0)(uae_u32 opcode) /* DIVS */
19269: {
19270: uae_u32 srcreg = (opcode & 7);
19271: uae_u32 dstreg = (opcode >> 9) & 7;
19272: unsigned int retcycles = 0;
19273: OpcodeFamily = 61; CurrentInstrCycles = 14;
19274: { uaecptr oldpc = m68k_getpc();
19275: {m68k_incpc(2);
19276: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
19277: BusCyclePenalty += 2;
19278: { uae_s16 src = get_word(srca);
19279: { uae_s32 dst = m68k_dreg(regs, dstreg);
19280: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1304; } else {
19281: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19282: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19283: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19284: {
19285: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19286: CLEAR_CZNV;
19287: SET_ZFLG (((uae_s16)(newv)) == 0);
19288: SET_NFLG (((uae_s16)(newv)) < 0);
19289: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19290: m68k_dreg(regs, dstreg) = (newv);
19291: }
19292: }
19293: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19294: }}}}}endlabel1304: ;
19295: return (14+retcycles);
19296: }
19297: unsigned long REGPARAM2 CPUFUNC(op_81f8_0)(uae_u32 opcode) /* DIVS */
19298: {
19299: uae_u32 dstreg = (opcode >> 9) & 7;
19300: unsigned int retcycles = 0;
19301: OpcodeFamily = 61; CurrentInstrCycles = 12;
19302: { uaecptr oldpc = m68k_getpc();
19303: { uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
19304: { uae_s16 src = get_word(srca);
19305: { uae_s32 dst = m68k_dreg(regs, dstreg);
19306: m68k_incpc(4);
19307: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1305; } else {
19308: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19309: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19310: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19311: {
19312: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19313: CLEAR_CZNV;
19314: SET_ZFLG (((uae_s16)(newv)) == 0);
19315: SET_NFLG (((uae_s16)(newv)) < 0);
19316: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19317: m68k_dreg(regs, dstreg) = (newv);
19318: }
19319: }
19320: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19321: }}}}endlabel1305: ;
19322: return (12+retcycles);
19323: }
19324: unsigned long REGPARAM2 CPUFUNC(op_81f9_0)(uae_u32 opcode) /* DIVS */
19325: {
19326: uae_u32 dstreg = (opcode >> 9) & 7;
19327: unsigned int retcycles = 0;
19328: OpcodeFamily = 61; CurrentInstrCycles = 16;
19329: { uaecptr oldpc = m68k_getpc();
19330: { uaecptr srca = get_ilong(2);
19331: { uae_s16 src = get_word(srca);
19332: { uae_s32 dst = m68k_dreg(regs, dstreg);
19333: m68k_incpc(6);
19334: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1306; } else {
19335: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19336: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19337: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19338: {
19339: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19340: CLEAR_CZNV;
19341: SET_ZFLG (((uae_s16)(newv)) == 0);
19342: SET_NFLG (((uae_s16)(newv)) < 0);
19343: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19344: m68k_dreg(regs, dstreg) = (newv);
19345: }
19346: }
19347: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19348: }}}}endlabel1306: ;
19349: return (16+retcycles);
19350: }
19351: unsigned long REGPARAM2 CPUFUNC(op_81fa_0)(uae_u32 opcode) /* DIVS */
19352: {
19353: uae_u32 dstreg = (opcode >> 9) & 7;
19354: unsigned int retcycles = 0;
19355: OpcodeFamily = 61; CurrentInstrCycles = 12;
19356: { uaecptr oldpc = m68k_getpc();
19357: { uaecptr srca = m68k_getpc () + 2;
19358: srca += (uae_s32)(uae_s16)get_iword(2);
19359: { uae_s16 src = get_word(srca);
19360: { uae_s32 dst = m68k_dreg(regs, dstreg);
19361: m68k_incpc(4);
19362: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1307; } else {
19363: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19364: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19365: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19366: {
19367: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19368: CLEAR_CZNV;
19369: SET_ZFLG (((uae_s16)(newv)) == 0);
19370: SET_NFLG (((uae_s16)(newv)) < 0);
19371: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19372: m68k_dreg(regs, dstreg) = (newv);
19373: }
19374: }
19375: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19376: }}}}endlabel1307: ;
19377: return (12+retcycles);
19378: }
19379: unsigned long REGPARAM2 CPUFUNC(op_81fb_0)(uae_u32 opcode) /* DIVS */
19380: {
19381: uae_u32 dstreg = (opcode >> 9) & 7;
19382: unsigned int retcycles = 0;
19383: OpcodeFamily = 61; CurrentInstrCycles = 14;
19384: { uaecptr oldpc = m68k_getpc();
19385: {m68k_incpc(2);
19386: { uaecptr tmppc = m68k_getpc();
19387: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
19388: BusCyclePenalty += 2;
19389: { uae_s16 src = get_word(srca);
19390: { uae_s32 dst = m68k_dreg(regs, dstreg);
19391: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1308; } else {
19392: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19393: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19394: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19395: {
19396: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19397: CLEAR_CZNV;
19398: SET_ZFLG (((uae_s16)(newv)) == 0);
19399: SET_NFLG (((uae_s16)(newv)) < 0);
19400: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19401: m68k_dreg(regs, dstreg) = (newv);
19402: }
19403: }
19404: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19405: }}}}}endlabel1308: ;
19406: return (14+retcycles);
19407: }
19408: unsigned long REGPARAM2 CPUFUNC(op_81fc_0)(uae_u32 opcode) /* DIVS */
19409: {
19410: uae_u32 dstreg = (opcode >> 9) & 7;
19411: unsigned int retcycles = 0;
19412: OpcodeFamily = 61; CurrentInstrCycles = 8;
19413: { uaecptr oldpc = m68k_getpc();
19414: { uae_s16 src = get_iword(2);
19415: { uae_s32 dst = m68k_dreg(regs, dstreg);
19416: m68k_incpc(4);
19417: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1309; } else {
19418: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
19419: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
19420: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
19421: {
19422: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
19423: CLEAR_CZNV;
19424: SET_ZFLG (((uae_s16)(newv)) == 0);
19425: SET_NFLG (((uae_s16)(newv)) < 0);
19426: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
19427: m68k_dreg(regs, dstreg) = (newv);
19428: }
19429: }
19430: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
19431: }}}endlabel1309: ;
19432: return (8+retcycles);
19433: }
19434: unsigned long REGPARAM2 CPUFUNC(op_9000_0)(uae_u32 opcode) /* SUB */
19435: {
19436: uae_u32 srcreg = (opcode & 7);
19437: uae_u32 dstreg = (opcode >> 9) & 7;
19438: OpcodeFamily = 7; CurrentInstrCycles = 4;
19439: {{ uae_s8 src = m68k_dreg(regs, srcreg);
19440: { uae_s8 dst = m68k_dreg(regs, dstreg);
19441: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19442: { int flgs = ((uae_s8)(src)) < 0;
19443: int flgo = ((uae_s8)(dst)) < 0;
19444: int flgn = ((uae_s8)(newv)) < 0;
19445: SET_ZFLG (((uae_s8)(newv)) == 0);
19446: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19447: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19448: COPY_CARRY;
19449: SET_NFLG (flgn != 0);
19450: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19451: }}}}}}m68k_incpc(2);
19452: return 4;
19453: }
19454: unsigned long REGPARAM2 CPUFUNC(op_9010_0)(uae_u32 opcode) /* SUB */
19455: {
19456: uae_u32 srcreg = (opcode & 7);
19457: uae_u32 dstreg = (opcode >> 9) & 7;
19458: OpcodeFamily = 7; CurrentInstrCycles = 8;
19459: {{ uaecptr srca = m68k_areg(regs, srcreg);
19460: { uae_s8 src = get_byte(srca);
19461: { uae_s8 dst = m68k_dreg(regs, dstreg);
19462: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19463: { int flgs = ((uae_s8)(src)) < 0;
19464: int flgo = ((uae_s8)(dst)) < 0;
19465: int flgn = ((uae_s8)(newv)) < 0;
19466: SET_ZFLG (((uae_s8)(newv)) == 0);
19467: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19468: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19469: COPY_CARRY;
19470: SET_NFLG (flgn != 0);
19471: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19472: }}}}}}}m68k_incpc(2);
19473: return 8;
19474: }
19475: unsigned long REGPARAM2 CPUFUNC(op_9018_0)(uae_u32 opcode) /* SUB */
19476: {
19477: uae_u32 srcreg = (opcode & 7);
19478: uae_u32 dstreg = (opcode >> 9) & 7;
19479: OpcodeFamily = 7; CurrentInstrCycles = 8;
19480: {{ uaecptr srca = m68k_areg(regs, srcreg);
19481: { uae_s8 src = get_byte(srca);
19482: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
19483: { uae_s8 dst = m68k_dreg(regs, dstreg);
19484: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19485: { int flgs = ((uae_s8)(src)) < 0;
19486: int flgo = ((uae_s8)(dst)) < 0;
19487: int flgn = ((uae_s8)(newv)) < 0;
19488: SET_ZFLG (((uae_s8)(newv)) == 0);
19489: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19490: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19491: COPY_CARRY;
19492: SET_NFLG (flgn != 0);
19493: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19494: }}}}}}}m68k_incpc(2);
19495: return 8;
19496: }
19497: unsigned long REGPARAM2 CPUFUNC(op_9020_0)(uae_u32 opcode) /* SUB */
19498: {
19499: uae_u32 srcreg = (opcode & 7);
19500: uae_u32 dstreg = (opcode >> 9) & 7;
19501: OpcodeFamily = 7; CurrentInstrCycles = 10;
19502: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
19503: { uae_s8 src = get_byte(srca);
19504: m68k_areg (regs, srcreg) = srca;
19505: { uae_s8 dst = m68k_dreg(regs, dstreg);
19506: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19507: { int flgs = ((uae_s8)(src)) < 0;
19508: int flgo = ((uae_s8)(dst)) < 0;
19509: int flgn = ((uae_s8)(newv)) < 0;
19510: SET_ZFLG (((uae_s8)(newv)) == 0);
19511: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19512: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19513: COPY_CARRY;
19514: SET_NFLG (flgn != 0);
19515: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19516: }}}}}}}m68k_incpc(2);
19517: return 10;
19518: }
19519: unsigned long REGPARAM2 CPUFUNC(op_9028_0)(uae_u32 opcode) /* SUB */
19520: {
19521: uae_u32 srcreg = (opcode & 7);
19522: uae_u32 dstreg = (opcode >> 9) & 7;
19523: OpcodeFamily = 7; CurrentInstrCycles = 12;
19524: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
19525: { uae_s8 src = get_byte(srca);
19526: { uae_s8 dst = m68k_dreg(regs, dstreg);
19527: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19528: { int flgs = ((uae_s8)(src)) < 0;
19529: int flgo = ((uae_s8)(dst)) < 0;
19530: int flgn = ((uae_s8)(newv)) < 0;
19531: SET_ZFLG (((uae_s8)(newv)) == 0);
19532: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19533: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19534: COPY_CARRY;
19535: SET_NFLG (flgn != 0);
19536: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19537: }}}}}}}m68k_incpc(4);
19538: return 12;
19539: }
19540: unsigned long REGPARAM2 CPUFUNC(op_9030_0)(uae_u32 opcode) /* SUB */
19541: {
19542: uae_u32 srcreg = (opcode & 7);
19543: uae_u32 dstreg = (opcode >> 9) & 7;
19544: OpcodeFamily = 7; CurrentInstrCycles = 14;
19545: {{m68k_incpc(2);
19546: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
19547: BusCyclePenalty += 2;
19548: { uae_s8 src = get_byte(srca);
19549: { uae_s8 dst = m68k_dreg(regs, dstreg);
19550: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19551: { int flgs = ((uae_s8)(src)) < 0;
19552: int flgo = ((uae_s8)(dst)) < 0;
19553: int flgn = ((uae_s8)(newv)) < 0;
19554: SET_ZFLG (((uae_s8)(newv)) == 0);
19555: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19556: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19557: COPY_CARRY;
19558: SET_NFLG (flgn != 0);
19559: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19560: }}}}}}}}return 14;
19561: }
19562: unsigned long REGPARAM2 CPUFUNC(op_9038_0)(uae_u32 opcode) /* SUB */
19563: {
19564: uae_u32 dstreg = (opcode >> 9) & 7;
19565: OpcodeFamily = 7; CurrentInstrCycles = 12;
19566: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
19567: { uae_s8 src = get_byte(srca);
19568: { uae_s8 dst = m68k_dreg(regs, dstreg);
19569: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19570: { int flgs = ((uae_s8)(src)) < 0;
19571: int flgo = ((uae_s8)(dst)) < 0;
19572: int flgn = ((uae_s8)(newv)) < 0;
19573: SET_ZFLG (((uae_s8)(newv)) == 0);
19574: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19575: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19576: COPY_CARRY;
19577: SET_NFLG (flgn != 0);
19578: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19579: }}}}}}}m68k_incpc(4);
19580: return 12;
19581: }
19582: unsigned long REGPARAM2 CPUFUNC(op_9039_0)(uae_u32 opcode) /* SUB */
19583: {
19584: uae_u32 dstreg = (opcode >> 9) & 7;
19585: OpcodeFamily = 7; CurrentInstrCycles = 16;
19586: {{ uaecptr srca = get_ilong(2);
19587: { uae_s8 src = get_byte(srca);
19588: { uae_s8 dst = m68k_dreg(regs, dstreg);
19589: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19590: { int flgs = ((uae_s8)(src)) < 0;
19591: int flgo = ((uae_s8)(dst)) < 0;
19592: int flgn = ((uae_s8)(newv)) < 0;
19593: SET_ZFLG (((uae_s8)(newv)) == 0);
19594: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19595: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19596: COPY_CARRY;
19597: SET_NFLG (flgn != 0);
19598: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19599: }}}}}}}m68k_incpc(6);
19600: return 16;
19601: }
19602: unsigned long REGPARAM2 CPUFUNC(op_903a_0)(uae_u32 opcode) /* SUB */
19603: {
19604: uae_u32 dstreg = (opcode >> 9) & 7;
19605: OpcodeFamily = 7; CurrentInstrCycles = 12;
19606: {{ uaecptr srca = m68k_getpc () + 2;
19607: srca += (uae_s32)(uae_s16)get_iword(2);
19608: { uae_s8 src = get_byte(srca);
19609: { uae_s8 dst = m68k_dreg(regs, dstreg);
19610: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19611: { int flgs = ((uae_s8)(src)) < 0;
19612: int flgo = ((uae_s8)(dst)) < 0;
19613: int flgn = ((uae_s8)(newv)) < 0;
19614: SET_ZFLG (((uae_s8)(newv)) == 0);
19615: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19616: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19617: COPY_CARRY;
19618: SET_NFLG (flgn != 0);
19619: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19620: }}}}}}}m68k_incpc(4);
19621: return 12;
19622: }
19623: unsigned long REGPARAM2 CPUFUNC(op_903b_0)(uae_u32 opcode) /* SUB */
19624: {
19625: uae_u32 dstreg = (opcode >> 9) & 7;
19626: OpcodeFamily = 7; CurrentInstrCycles = 14;
19627: {{m68k_incpc(2);
19628: { uaecptr tmppc = m68k_getpc();
19629: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
19630: BusCyclePenalty += 2;
19631: { uae_s8 src = get_byte(srca);
19632: { uae_s8 dst = m68k_dreg(regs, dstreg);
19633: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19634: { int flgs = ((uae_s8)(src)) < 0;
19635: int flgo = ((uae_s8)(dst)) < 0;
19636: int flgn = ((uae_s8)(newv)) < 0;
19637: SET_ZFLG (((uae_s8)(newv)) == 0);
19638: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19639: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19640: COPY_CARRY;
19641: SET_NFLG (flgn != 0);
19642: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19643: }}}}}}}}return 14;
19644: }
19645: unsigned long REGPARAM2 CPUFUNC(op_903c_0)(uae_u32 opcode) /* SUB */
19646: {
19647: uae_u32 dstreg = (opcode >> 9) & 7;
19648: OpcodeFamily = 7; CurrentInstrCycles = 8;
19649: {{ uae_s8 src = get_ibyte(2);
19650: { uae_s8 dst = m68k_dreg(regs, dstreg);
19651: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
19652: { int flgs = ((uae_s8)(src)) < 0;
19653: int flgo = ((uae_s8)(dst)) < 0;
19654: int flgn = ((uae_s8)(newv)) < 0;
19655: SET_ZFLG (((uae_s8)(newv)) == 0);
19656: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19657: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
19658: COPY_CARRY;
19659: SET_NFLG (flgn != 0);
19660: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
19661: }}}}}}m68k_incpc(4);
19662: return 8;
19663: }
19664: unsigned long REGPARAM2 CPUFUNC(op_9040_0)(uae_u32 opcode) /* SUB */
19665: {
19666: uae_u32 srcreg = (opcode & 7);
19667: uae_u32 dstreg = (opcode >> 9) & 7;
19668: OpcodeFamily = 7; CurrentInstrCycles = 4;
19669: {{ uae_s16 src = m68k_dreg(regs, srcreg);
19670: { uae_s16 dst = m68k_dreg(regs, dstreg);
19671: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19672: { int flgs = ((uae_s16)(src)) < 0;
19673: int flgo = ((uae_s16)(dst)) < 0;
19674: int flgn = ((uae_s16)(newv)) < 0;
19675: SET_ZFLG (((uae_s16)(newv)) == 0);
19676: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19677: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19678: COPY_CARRY;
19679: SET_NFLG (flgn != 0);
19680: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19681: }}}}}}m68k_incpc(2);
19682: return 4;
19683: }
19684: unsigned long REGPARAM2 CPUFUNC(op_9048_0)(uae_u32 opcode) /* SUB */
19685: {
19686: uae_u32 srcreg = (opcode & 7);
19687: uae_u32 dstreg = (opcode >> 9) & 7;
19688: OpcodeFamily = 7; CurrentInstrCycles = 4;
19689: {{ uae_s16 src = m68k_areg(regs, srcreg);
19690: { uae_s16 dst = m68k_dreg(regs, dstreg);
19691: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19692: { int flgs = ((uae_s16)(src)) < 0;
19693: int flgo = ((uae_s16)(dst)) < 0;
19694: int flgn = ((uae_s16)(newv)) < 0;
19695: SET_ZFLG (((uae_s16)(newv)) == 0);
19696: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19697: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19698: COPY_CARRY;
19699: SET_NFLG (flgn != 0);
19700: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19701: }}}}}}m68k_incpc(2);
19702: return 4;
19703: }
19704: unsigned long REGPARAM2 CPUFUNC(op_9050_0)(uae_u32 opcode) /* SUB */
19705: {
19706: uae_u32 srcreg = (opcode & 7);
19707: uae_u32 dstreg = (opcode >> 9) & 7;
19708: OpcodeFamily = 7; CurrentInstrCycles = 8;
19709: {{ uaecptr srca = m68k_areg(regs, srcreg);
19710: { uae_s16 src = get_word(srca);
19711: { uae_s16 dst = m68k_dreg(regs, dstreg);
19712: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19713: { int flgs = ((uae_s16)(src)) < 0;
19714: int flgo = ((uae_s16)(dst)) < 0;
19715: int flgn = ((uae_s16)(newv)) < 0;
19716: SET_ZFLG (((uae_s16)(newv)) == 0);
19717: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19718: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19719: COPY_CARRY;
19720: SET_NFLG (flgn != 0);
19721: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19722: }}}}}}}m68k_incpc(2);
19723: return 8;
19724: }
19725: unsigned long REGPARAM2 CPUFUNC(op_9058_0)(uae_u32 opcode) /* SUB */
19726: {
19727: uae_u32 srcreg = (opcode & 7);
19728: uae_u32 dstreg = (opcode >> 9) & 7;
19729: OpcodeFamily = 7; CurrentInstrCycles = 8;
19730: {{ uaecptr srca = m68k_areg(regs, srcreg);
19731: { uae_s16 src = get_word(srca);
19732: m68k_areg(regs, srcreg) += 2;
19733: { uae_s16 dst = m68k_dreg(regs, dstreg);
19734: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19735: { int flgs = ((uae_s16)(src)) < 0;
19736: int flgo = ((uae_s16)(dst)) < 0;
19737: int flgn = ((uae_s16)(newv)) < 0;
19738: SET_ZFLG (((uae_s16)(newv)) == 0);
19739: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19740: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19741: COPY_CARRY;
19742: SET_NFLG (flgn != 0);
19743: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19744: }}}}}}}m68k_incpc(2);
19745: return 8;
19746: }
19747: unsigned long REGPARAM2 CPUFUNC(op_9060_0)(uae_u32 opcode) /* SUB */
19748: {
19749: uae_u32 srcreg = (opcode & 7);
19750: uae_u32 dstreg = (opcode >> 9) & 7;
19751: OpcodeFamily = 7; CurrentInstrCycles = 10;
19752: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
19753: { uae_s16 src = get_word(srca);
19754: m68k_areg (regs, srcreg) = srca;
19755: { uae_s16 dst = m68k_dreg(regs, dstreg);
19756: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19757: { int flgs = ((uae_s16)(src)) < 0;
19758: int flgo = ((uae_s16)(dst)) < 0;
19759: int flgn = ((uae_s16)(newv)) < 0;
19760: SET_ZFLG (((uae_s16)(newv)) == 0);
19761: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19762: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19763: COPY_CARRY;
19764: SET_NFLG (flgn != 0);
19765: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19766: }}}}}}}m68k_incpc(2);
19767: return 10;
19768: }
19769: unsigned long REGPARAM2 CPUFUNC(op_9068_0)(uae_u32 opcode) /* SUB */
19770: {
19771: uae_u32 srcreg = (opcode & 7);
19772: uae_u32 dstreg = (opcode >> 9) & 7;
19773: OpcodeFamily = 7; CurrentInstrCycles = 12;
19774: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
19775: { uae_s16 src = get_word(srca);
19776: { uae_s16 dst = m68k_dreg(regs, dstreg);
19777: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19778: { int flgs = ((uae_s16)(src)) < 0;
19779: int flgo = ((uae_s16)(dst)) < 0;
19780: int flgn = ((uae_s16)(newv)) < 0;
19781: SET_ZFLG (((uae_s16)(newv)) == 0);
19782: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19783: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19784: COPY_CARRY;
19785: SET_NFLG (flgn != 0);
19786: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19787: }}}}}}}m68k_incpc(4);
19788: return 12;
19789: }
19790: unsigned long REGPARAM2 CPUFUNC(op_9070_0)(uae_u32 opcode) /* SUB */
19791: {
19792: uae_u32 srcreg = (opcode & 7);
19793: uae_u32 dstreg = (opcode >> 9) & 7;
19794: OpcodeFamily = 7; CurrentInstrCycles = 14;
19795: {{m68k_incpc(2);
19796: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
19797: BusCyclePenalty += 2;
19798: { uae_s16 src = get_word(srca);
19799: { uae_s16 dst = m68k_dreg(regs, dstreg);
19800: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19801: { int flgs = ((uae_s16)(src)) < 0;
19802: int flgo = ((uae_s16)(dst)) < 0;
19803: int flgn = ((uae_s16)(newv)) < 0;
19804: SET_ZFLG (((uae_s16)(newv)) == 0);
19805: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19806: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19807: COPY_CARRY;
19808: SET_NFLG (flgn != 0);
19809: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19810: }}}}}}}}return 14;
19811: }
19812: unsigned long REGPARAM2 CPUFUNC(op_9078_0)(uae_u32 opcode) /* SUB */
19813: {
19814: uae_u32 dstreg = (opcode >> 9) & 7;
19815: OpcodeFamily = 7; CurrentInstrCycles = 12;
19816: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
19817: { uae_s16 src = get_word(srca);
19818: { uae_s16 dst = m68k_dreg(regs, dstreg);
19819: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19820: { int flgs = ((uae_s16)(src)) < 0;
19821: int flgo = ((uae_s16)(dst)) < 0;
19822: int flgn = ((uae_s16)(newv)) < 0;
19823: SET_ZFLG (((uae_s16)(newv)) == 0);
19824: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19825: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19826: COPY_CARRY;
19827: SET_NFLG (flgn != 0);
19828: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19829: }}}}}}}m68k_incpc(4);
19830: return 12;
19831: }
19832: unsigned long REGPARAM2 CPUFUNC(op_9079_0)(uae_u32 opcode) /* SUB */
19833: {
19834: uae_u32 dstreg = (opcode >> 9) & 7;
19835: OpcodeFamily = 7; CurrentInstrCycles = 16;
19836: {{ uaecptr srca = get_ilong(2);
19837: { uae_s16 src = get_word(srca);
19838: { uae_s16 dst = m68k_dreg(regs, dstreg);
19839: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19840: { int flgs = ((uae_s16)(src)) < 0;
19841: int flgo = ((uae_s16)(dst)) < 0;
19842: int flgn = ((uae_s16)(newv)) < 0;
19843: SET_ZFLG (((uae_s16)(newv)) == 0);
19844: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19845: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19846: COPY_CARRY;
19847: SET_NFLG (flgn != 0);
19848: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19849: }}}}}}}m68k_incpc(6);
19850: return 16;
19851: }
19852: unsigned long REGPARAM2 CPUFUNC(op_907a_0)(uae_u32 opcode) /* SUB */
19853: {
19854: uae_u32 dstreg = (opcode >> 9) & 7;
19855: OpcodeFamily = 7; CurrentInstrCycles = 12;
19856: {{ uaecptr srca = m68k_getpc () + 2;
19857: srca += (uae_s32)(uae_s16)get_iword(2);
19858: { uae_s16 src = get_word(srca);
19859: { uae_s16 dst = m68k_dreg(regs, dstreg);
19860: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19861: { int flgs = ((uae_s16)(src)) < 0;
19862: int flgo = ((uae_s16)(dst)) < 0;
19863: int flgn = ((uae_s16)(newv)) < 0;
19864: SET_ZFLG (((uae_s16)(newv)) == 0);
19865: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19866: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19867: COPY_CARRY;
19868: SET_NFLG (flgn != 0);
19869: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19870: }}}}}}}m68k_incpc(4);
19871: return 12;
19872: }
19873: unsigned long REGPARAM2 CPUFUNC(op_907b_0)(uae_u32 opcode) /* SUB */
19874: {
19875: uae_u32 dstreg = (opcode >> 9) & 7;
19876: OpcodeFamily = 7; CurrentInstrCycles = 14;
19877: {{m68k_incpc(2);
19878: { uaecptr tmppc = m68k_getpc();
19879: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
19880: BusCyclePenalty += 2;
19881: { uae_s16 src = get_word(srca);
19882: { uae_s16 dst = m68k_dreg(regs, dstreg);
19883: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19884: { int flgs = ((uae_s16)(src)) < 0;
19885: int flgo = ((uae_s16)(dst)) < 0;
19886: int flgn = ((uae_s16)(newv)) < 0;
19887: SET_ZFLG (((uae_s16)(newv)) == 0);
19888: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19889: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19890: COPY_CARRY;
19891: SET_NFLG (flgn != 0);
19892: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19893: }}}}}}}}return 14;
19894: }
19895: unsigned long REGPARAM2 CPUFUNC(op_907c_0)(uae_u32 opcode) /* SUB */
19896: {
19897: uae_u32 dstreg = (opcode >> 9) & 7;
19898: OpcodeFamily = 7; CurrentInstrCycles = 8;
19899: {{ uae_s16 src = get_iword(2);
19900: { uae_s16 dst = m68k_dreg(regs, dstreg);
19901: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
19902: { int flgs = ((uae_s16)(src)) < 0;
19903: int flgo = ((uae_s16)(dst)) < 0;
19904: int flgn = ((uae_s16)(newv)) < 0;
19905: SET_ZFLG (((uae_s16)(newv)) == 0);
19906: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19907: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
19908: COPY_CARRY;
19909: SET_NFLG (flgn != 0);
19910: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
19911: }}}}}}m68k_incpc(4);
19912: return 8;
19913: }
19914: unsigned long REGPARAM2 CPUFUNC(op_9080_0)(uae_u32 opcode) /* SUB */
19915: {
19916: uae_u32 srcreg = (opcode & 7);
19917: uae_u32 dstreg = (opcode >> 9) & 7;
19918: OpcodeFamily = 7; CurrentInstrCycles = 8;
19919: {{ uae_s32 src = m68k_dreg(regs, srcreg);
19920: { uae_s32 dst = m68k_dreg(regs, dstreg);
19921: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
19922: { int flgs = ((uae_s32)(src)) < 0;
19923: int flgo = ((uae_s32)(dst)) < 0;
19924: int flgn = ((uae_s32)(newv)) < 0;
19925: SET_ZFLG (((uae_s32)(newv)) == 0);
19926: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19927: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
19928: COPY_CARRY;
19929: SET_NFLG (flgn != 0);
19930: m68k_dreg(regs, dstreg) = (newv);
19931: }}}}}}m68k_incpc(2);
19932: return 8;
19933: }
19934: unsigned long REGPARAM2 CPUFUNC(op_9088_0)(uae_u32 opcode) /* SUB */
19935: {
19936: uae_u32 srcreg = (opcode & 7);
19937: uae_u32 dstreg = (opcode >> 9) & 7;
19938: OpcodeFamily = 7; CurrentInstrCycles = 8;
19939: {{ uae_s32 src = m68k_areg(regs, srcreg);
19940: { uae_s32 dst = m68k_dreg(regs, dstreg);
19941: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
19942: { int flgs = ((uae_s32)(src)) < 0;
19943: int flgo = ((uae_s32)(dst)) < 0;
19944: int flgn = ((uae_s32)(newv)) < 0;
19945: SET_ZFLG (((uae_s32)(newv)) == 0);
19946: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19947: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
19948: COPY_CARRY;
19949: SET_NFLG (flgn != 0);
19950: m68k_dreg(regs, dstreg) = (newv);
19951: }}}}}}m68k_incpc(2);
19952: return 8;
19953: }
19954: unsigned long REGPARAM2 CPUFUNC(op_9090_0)(uae_u32 opcode) /* SUB */
19955: {
19956: uae_u32 srcreg = (opcode & 7);
19957: uae_u32 dstreg = (opcode >> 9) & 7;
19958: OpcodeFamily = 7; CurrentInstrCycles = 14;
19959: {{ uaecptr srca = m68k_areg(regs, srcreg);
19960: { uae_s32 src = get_long(srca);
19961: { uae_s32 dst = m68k_dreg(regs, dstreg);
19962: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
19963: { int flgs = ((uae_s32)(src)) < 0;
19964: int flgo = ((uae_s32)(dst)) < 0;
19965: int flgn = ((uae_s32)(newv)) < 0;
19966: SET_ZFLG (((uae_s32)(newv)) == 0);
19967: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19968: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
19969: COPY_CARRY;
19970: SET_NFLG (flgn != 0);
19971: m68k_dreg(regs, dstreg) = (newv);
19972: }}}}}}}m68k_incpc(2);
19973: return 14;
19974: }
19975: unsigned long REGPARAM2 CPUFUNC(op_9098_0)(uae_u32 opcode) /* SUB */
19976: {
19977: uae_u32 srcreg = (opcode & 7);
19978: uae_u32 dstreg = (opcode >> 9) & 7;
19979: OpcodeFamily = 7; CurrentInstrCycles = 14;
19980: {{ uaecptr srca = m68k_areg(regs, srcreg);
19981: { uae_s32 src = get_long(srca);
19982: m68k_areg(regs, srcreg) += 4;
19983: { uae_s32 dst = m68k_dreg(regs, dstreg);
19984: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
19985: { int flgs = ((uae_s32)(src)) < 0;
19986: int flgo = ((uae_s32)(dst)) < 0;
19987: int flgn = ((uae_s32)(newv)) < 0;
19988: SET_ZFLG (((uae_s32)(newv)) == 0);
19989: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
19990: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
19991: COPY_CARRY;
19992: SET_NFLG (flgn != 0);
19993: m68k_dreg(regs, dstreg) = (newv);
19994: }}}}}}}m68k_incpc(2);
19995: return 14;
19996: }
19997: unsigned long REGPARAM2 CPUFUNC(op_90a0_0)(uae_u32 opcode) /* SUB */
19998: {
19999: uae_u32 srcreg = (opcode & 7);
20000: uae_u32 dstreg = (opcode >> 9) & 7;
20001: OpcodeFamily = 7; CurrentInstrCycles = 16;
20002: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
20003: { uae_s32 src = get_long(srca);
20004: m68k_areg (regs, srcreg) = srca;
20005: { uae_s32 dst = m68k_dreg(regs, dstreg);
20006: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20007: { int flgs = ((uae_s32)(src)) < 0;
20008: int flgo = ((uae_s32)(dst)) < 0;
20009: int flgn = ((uae_s32)(newv)) < 0;
20010: SET_ZFLG (((uae_s32)(newv)) == 0);
20011: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20012: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20013: COPY_CARRY;
20014: SET_NFLG (flgn != 0);
20015: m68k_dreg(regs, dstreg) = (newv);
20016: }}}}}}}m68k_incpc(2);
20017: return 16;
20018: }
20019: unsigned long REGPARAM2 CPUFUNC(op_90a8_0)(uae_u32 opcode) /* SUB */
20020: {
20021: uae_u32 srcreg = (opcode & 7);
20022: uae_u32 dstreg = (opcode >> 9) & 7;
20023: OpcodeFamily = 7; CurrentInstrCycles = 18;
20024: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
20025: { uae_s32 src = get_long(srca);
20026: { uae_s32 dst = m68k_dreg(regs, dstreg);
20027: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20028: { int flgs = ((uae_s32)(src)) < 0;
20029: int flgo = ((uae_s32)(dst)) < 0;
20030: int flgn = ((uae_s32)(newv)) < 0;
20031: SET_ZFLG (((uae_s32)(newv)) == 0);
20032: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20033: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20034: COPY_CARRY;
20035: SET_NFLG (flgn != 0);
20036: m68k_dreg(regs, dstreg) = (newv);
20037: }}}}}}}m68k_incpc(4);
20038: return 18;
20039: }
20040: unsigned long REGPARAM2 CPUFUNC(op_90b0_0)(uae_u32 opcode) /* SUB */
20041: {
20042: uae_u32 srcreg = (opcode & 7);
20043: uae_u32 dstreg = (opcode >> 9) & 7;
20044: OpcodeFamily = 7; CurrentInstrCycles = 20;
20045: {{m68k_incpc(2);
20046: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
20047: BusCyclePenalty += 2;
20048: { uae_s32 src = get_long(srca);
20049: { uae_s32 dst = m68k_dreg(regs, dstreg);
20050: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20051: { int flgs = ((uae_s32)(src)) < 0;
20052: int flgo = ((uae_s32)(dst)) < 0;
20053: int flgn = ((uae_s32)(newv)) < 0;
20054: SET_ZFLG (((uae_s32)(newv)) == 0);
20055: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20056: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20057: COPY_CARRY;
20058: SET_NFLG (flgn != 0);
20059: m68k_dreg(regs, dstreg) = (newv);
20060: }}}}}}}}return 20;
20061: }
20062: unsigned long REGPARAM2 CPUFUNC(op_90b8_0)(uae_u32 opcode) /* SUB */
20063: {
20064: uae_u32 dstreg = (opcode >> 9) & 7;
20065: OpcodeFamily = 7; CurrentInstrCycles = 18;
20066: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
20067: { uae_s32 src = get_long(srca);
20068: { uae_s32 dst = m68k_dreg(regs, dstreg);
20069: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20070: { int flgs = ((uae_s32)(src)) < 0;
20071: int flgo = ((uae_s32)(dst)) < 0;
20072: int flgn = ((uae_s32)(newv)) < 0;
20073: SET_ZFLG (((uae_s32)(newv)) == 0);
20074: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20075: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20076: COPY_CARRY;
20077: SET_NFLG (flgn != 0);
20078: m68k_dreg(regs, dstreg) = (newv);
20079: }}}}}}}m68k_incpc(4);
20080: return 18;
20081: }
20082: unsigned long REGPARAM2 CPUFUNC(op_90b9_0)(uae_u32 opcode) /* SUB */
20083: {
20084: uae_u32 dstreg = (opcode >> 9) & 7;
20085: OpcodeFamily = 7; CurrentInstrCycles = 22;
20086: {{ uaecptr srca = get_ilong(2);
20087: { uae_s32 src = get_long(srca);
20088: { uae_s32 dst = m68k_dreg(regs, dstreg);
20089: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20090: { int flgs = ((uae_s32)(src)) < 0;
20091: int flgo = ((uae_s32)(dst)) < 0;
20092: int flgn = ((uae_s32)(newv)) < 0;
20093: SET_ZFLG (((uae_s32)(newv)) == 0);
20094: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20095: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20096: COPY_CARRY;
20097: SET_NFLG (flgn != 0);
20098: m68k_dreg(regs, dstreg) = (newv);
20099: }}}}}}}m68k_incpc(6);
20100: return 22;
20101: }
20102: unsigned long REGPARAM2 CPUFUNC(op_90ba_0)(uae_u32 opcode) /* SUB */
20103: {
20104: uae_u32 dstreg = (opcode >> 9) & 7;
20105: OpcodeFamily = 7; CurrentInstrCycles = 18;
20106: {{ uaecptr srca = m68k_getpc () + 2;
20107: srca += (uae_s32)(uae_s16)get_iword(2);
20108: { uae_s32 src = get_long(srca);
20109: { uae_s32 dst = m68k_dreg(regs, dstreg);
20110: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20111: { int flgs = ((uae_s32)(src)) < 0;
20112: int flgo = ((uae_s32)(dst)) < 0;
20113: int flgn = ((uae_s32)(newv)) < 0;
20114: SET_ZFLG (((uae_s32)(newv)) == 0);
20115: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20116: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20117: COPY_CARRY;
20118: SET_NFLG (flgn != 0);
20119: m68k_dreg(regs, dstreg) = (newv);
20120: }}}}}}}m68k_incpc(4);
20121: return 18;
20122: }
20123: unsigned long REGPARAM2 CPUFUNC(op_90bb_0)(uae_u32 opcode) /* SUB */
20124: {
20125: uae_u32 dstreg = (opcode >> 9) & 7;
20126: OpcodeFamily = 7; CurrentInstrCycles = 20;
20127: {{m68k_incpc(2);
20128: { uaecptr tmppc = m68k_getpc();
20129: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
20130: BusCyclePenalty += 2;
20131: { uae_s32 src = get_long(srca);
20132: { uae_s32 dst = m68k_dreg(regs, dstreg);
20133: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20134: { int flgs = ((uae_s32)(src)) < 0;
20135: int flgo = ((uae_s32)(dst)) < 0;
20136: int flgn = ((uae_s32)(newv)) < 0;
20137: SET_ZFLG (((uae_s32)(newv)) == 0);
20138: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20139: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20140: COPY_CARRY;
20141: SET_NFLG (flgn != 0);
20142: m68k_dreg(regs, dstreg) = (newv);
20143: }}}}}}}}return 20;
20144: }
20145: unsigned long REGPARAM2 CPUFUNC(op_90bc_0)(uae_u32 opcode) /* SUB */
20146: {
20147: uae_u32 dstreg = (opcode >> 9) & 7;
20148: OpcodeFamily = 7; CurrentInstrCycles = 16;
20149: {{ uae_s32 src = get_ilong(2);
20150: { uae_s32 dst = m68k_dreg(regs, dstreg);
20151: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20152: { int flgs = ((uae_s32)(src)) < 0;
20153: int flgo = ((uae_s32)(dst)) < 0;
20154: int flgn = ((uae_s32)(newv)) < 0;
20155: SET_ZFLG (((uae_s32)(newv)) == 0);
20156: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20157: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20158: COPY_CARRY;
20159: SET_NFLG (flgn != 0);
20160: m68k_dreg(regs, dstreg) = (newv);
20161: }}}}}}m68k_incpc(6);
20162: return 16;
20163: }
20164: unsigned long REGPARAM2 CPUFUNC(op_90c0_0)(uae_u32 opcode) /* SUBA */
20165: {
20166: uae_u32 srcreg = (opcode & 7);
20167: uae_u32 dstreg = (opcode >> 9) & 7;
20168: OpcodeFamily = 8; CurrentInstrCycles = 8;
20169: {{ uae_s16 src = m68k_dreg(regs, srcreg);
20170: { uae_s32 dst = m68k_areg(regs, dstreg);
20171: { uae_u32 newv = dst - src;
20172: m68k_areg(regs, dstreg) = (newv);
20173: }}}}m68k_incpc(2);
20174: return 8;
20175: }
20176: unsigned long REGPARAM2 CPUFUNC(op_90c8_0)(uae_u32 opcode) /* SUBA */
20177: {
20178: uae_u32 srcreg = (opcode & 7);
20179: uae_u32 dstreg = (opcode >> 9) & 7;
20180: OpcodeFamily = 8; CurrentInstrCycles = 8;
20181: {{ uae_s16 src = m68k_areg(regs, srcreg);
20182: { uae_s32 dst = m68k_areg(regs, dstreg);
20183: { uae_u32 newv = dst - src;
20184: m68k_areg(regs, dstreg) = (newv);
20185: }}}}m68k_incpc(2);
20186: return 8;
20187: }
20188: unsigned long REGPARAM2 CPUFUNC(op_90d0_0)(uae_u32 opcode) /* SUBA */
20189: {
20190: uae_u32 srcreg = (opcode & 7);
20191: uae_u32 dstreg = (opcode >> 9) & 7;
20192: OpcodeFamily = 8; CurrentInstrCycles = 12;
20193: {{ uaecptr srca = m68k_areg(regs, srcreg);
20194: { uae_s16 src = get_word(srca);
20195: { uae_s32 dst = m68k_areg(regs, dstreg);
20196: { uae_u32 newv = dst - src;
20197: m68k_areg(regs, dstreg) = (newv);
20198: }}}}}m68k_incpc(2);
20199: return 12;
20200: }
20201: unsigned long REGPARAM2 CPUFUNC(op_90d8_0)(uae_u32 opcode) /* SUBA */
20202: {
20203: uae_u32 srcreg = (opcode & 7);
20204: uae_u32 dstreg = (opcode >> 9) & 7;
20205: OpcodeFamily = 8; CurrentInstrCycles = 12;
20206: {{ uaecptr srca = m68k_areg(regs, srcreg);
20207: { uae_s16 src = get_word(srca);
20208: m68k_areg(regs, srcreg) += 2;
20209: { uae_s32 dst = m68k_areg(regs, dstreg);
20210: { uae_u32 newv = dst - src;
20211: m68k_areg(regs, dstreg) = (newv);
20212: }}}}}m68k_incpc(2);
20213: return 12;
20214: }
20215: unsigned long REGPARAM2 CPUFUNC(op_90e0_0)(uae_u32 opcode) /* SUBA */
20216: {
20217: uae_u32 srcreg = (opcode & 7);
20218: uae_u32 dstreg = (opcode >> 9) & 7;
20219: OpcodeFamily = 8; CurrentInstrCycles = 14;
20220: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
20221: { uae_s16 src = get_word(srca);
20222: m68k_areg (regs, srcreg) = srca;
20223: { uae_s32 dst = m68k_areg(regs, dstreg);
20224: { uae_u32 newv = dst - src;
20225: m68k_areg(regs, dstreg) = (newv);
20226: }}}}}m68k_incpc(2);
20227: return 14;
20228: }
20229: unsigned long REGPARAM2 CPUFUNC(op_90e8_0)(uae_u32 opcode) /* SUBA */
20230: {
20231: uae_u32 srcreg = (opcode & 7);
20232: uae_u32 dstreg = (opcode >> 9) & 7;
20233: OpcodeFamily = 8; CurrentInstrCycles = 16;
20234: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
20235: { uae_s16 src = get_word(srca);
20236: { uae_s32 dst = m68k_areg(regs, dstreg);
20237: { uae_u32 newv = dst - src;
20238: m68k_areg(regs, dstreg) = (newv);
20239: }}}}}m68k_incpc(4);
20240: return 16;
20241: }
20242: unsigned long REGPARAM2 CPUFUNC(op_90f0_0)(uae_u32 opcode) /* SUBA */
20243: {
20244: uae_u32 srcreg = (opcode & 7);
20245: uae_u32 dstreg = (opcode >> 9) & 7;
20246: OpcodeFamily = 8; CurrentInstrCycles = 18;
20247: {{m68k_incpc(2);
20248: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
20249: BusCyclePenalty += 2;
20250: { uae_s16 src = get_word(srca);
20251: { uae_s32 dst = m68k_areg(regs, dstreg);
20252: { uae_u32 newv = dst - src;
20253: m68k_areg(regs, dstreg) = (newv);
20254: }}}}}}return 18;
20255: }
20256: unsigned long REGPARAM2 CPUFUNC(op_90f8_0)(uae_u32 opcode) /* SUBA */
20257: {
20258: uae_u32 dstreg = (opcode >> 9) & 7;
20259: OpcodeFamily = 8; CurrentInstrCycles = 16;
20260: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
20261: { uae_s16 src = get_word(srca);
20262: { uae_s32 dst = m68k_areg(regs, dstreg);
20263: { uae_u32 newv = dst - src;
20264: m68k_areg(regs, dstreg) = (newv);
20265: }}}}}m68k_incpc(4);
20266: return 16;
20267: }
20268: unsigned long REGPARAM2 CPUFUNC(op_90f9_0)(uae_u32 opcode) /* SUBA */
20269: {
20270: uae_u32 dstreg = (opcode >> 9) & 7;
20271: OpcodeFamily = 8; CurrentInstrCycles = 20;
20272: {{ uaecptr srca = get_ilong(2);
20273: { uae_s16 src = get_word(srca);
20274: { uae_s32 dst = m68k_areg(regs, dstreg);
20275: { uae_u32 newv = dst - src;
20276: m68k_areg(regs, dstreg) = (newv);
20277: }}}}}m68k_incpc(6);
20278: return 20;
20279: }
20280: unsigned long REGPARAM2 CPUFUNC(op_90fa_0)(uae_u32 opcode) /* SUBA */
20281: {
20282: uae_u32 dstreg = (opcode >> 9) & 7;
20283: OpcodeFamily = 8; CurrentInstrCycles = 16;
20284: {{ uaecptr srca = m68k_getpc () + 2;
20285: srca += (uae_s32)(uae_s16)get_iword(2);
20286: { uae_s16 src = get_word(srca);
20287: { uae_s32 dst = m68k_areg(regs, dstreg);
20288: { uae_u32 newv = dst - src;
20289: m68k_areg(regs, dstreg) = (newv);
20290: }}}}}m68k_incpc(4);
20291: return 16;
20292: }
20293: unsigned long REGPARAM2 CPUFUNC(op_90fb_0)(uae_u32 opcode) /* SUBA */
20294: {
20295: uae_u32 dstreg = (opcode >> 9) & 7;
20296: OpcodeFamily = 8; CurrentInstrCycles = 18;
20297: {{m68k_incpc(2);
20298: { uaecptr tmppc = m68k_getpc();
20299: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
20300: BusCyclePenalty += 2;
20301: { uae_s16 src = get_word(srca);
20302: { uae_s32 dst = m68k_areg(regs, dstreg);
20303: { uae_u32 newv = dst - src;
20304: m68k_areg(regs, dstreg) = (newv);
20305: }}}}}}return 18;
20306: }
20307: unsigned long REGPARAM2 CPUFUNC(op_90fc_0)(uae_u32 opcode) /* SUBA */
20308: {
20309: uae_u32 dstreg = (opcode >> 9) & 7;
20310: OpcodeFamily = 8; CurrentInstrCycles = 12;
20311: {{ uae_s16 src = get_iword(2);
20312: { uae_s32 dst = m68k_areg(regs, dstreg);
20313: { uae_u32 newv = dst - src;
20314: m68k_areg(regs, dstreg) = (newv);
20315: }}}}m68k_incpc(4);
20316: return 12;
20317: }
20318: unsigned long REGPARAM2 CPUFUNC(op_9100_0)(uae_u32 opcode) /* SUBX */
20319: {
20320: uae_u32 srcreg = (opcode & 7);
20321: uae_u32 dstreg = (opcode >> 9) & 7;
20322: OpcodeFamily = 9; CurrentInstrCycles = 4;
20323: {{ uae_s8 src = m68k_dreg(regs, srcreg);
20324: { uae_s8 dst = m68k_dreg(regs, dstreg);
20325: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
20326: { int flgs = ((uae_s8)(src)) < 0;
20327: int flgo = ((uae_s8)(dst)) < 0;
20328: int flgn = ((uae_s8)(newv)) < 0;
20329: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
20330: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
20331: COPY_CARRY;
20332: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
20333: SET_NFLG (((uae_s8)(newv)) < 0);
20334: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
20335: }}}}}m68k_incpc(2);
20336: return 4;
20337: }
20338: unsigned long REGPARAM2 CPUFUNC(op_9108_0)(uae_u32 opcode) /* SUBX */
20339: {
20340: uae_u32 srcreg = (opcode & 7);
20341: uae_u32 dstreg = (opcode >> 9) & 7;
20342: OpcodeFamily = 9; CurrentInstrCycles = 18;
20343: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
20344: { uae_s8 src = get_byte(srca);
20345: m68k_areg (regs, srcreg) = srca;
20346: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
20347: { uae_s8 dst = get_byte(dsta);
20348: m68k_areg (regs, dstreg) = dsta;
20349: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
20350: { int flgs = ((uae_s8)(src)) < 0;
20351: int flgo = ((uae_s8)(dst)) < 0;
20352: int flgn = ((uae_s8)(newv)) < 0;
20353: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
20354: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
20355: COPY_CARRY;
20356: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
20357: SET_NFLG (((uae_s8)(newv)) < 0);
20358: put_byte(dsta,newv);
20359: }}}}}}}m68k_incpc(2);
20360: return 18;
20361: }
20362: unsigned long REGPARAM2 CPUFUNC(op_9110_0)(uae_u32 opcode) /* SUB */
20363: {
20364: uae_u32 srcreg = ((opcode >> 9) & 7);
20365: uae_u32 dstreg = opcode & 7;
20366: OpcodeFamily = 7; CurrentInstrCycles = 12;
20367: {{ uae_s8 src = m68k_dreg(regs, srcreg);
20368: { uaecptr dsta = m68k_areg(regs, dstreg);
20369: { uae_s8 dst = get_byte(dsta);
20370: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
20371: { int flgs = ((uae_s8)(src)) < 0;
20372: int flgo = ((uae_s8)(dst)) < 0;
20373: int flgn = ((uae_s8)(newv)) < 0;
20374: SET_ZFLG (((uae_s8)(newv)) == 0);
20375: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20376: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
20377: COPY_CARRY;
20378: SET_NFLG (flgn != 0);
20379: put_byte(dsta,newv);
20380: }}}}}}}m68k_incpc(2);
20381: return 12;
20382: }
20383: unsigned long REGPARAM2 CPUFUNC(op_9118_0)(uae_u32 opcode) /* SUB */
20384: {
20385: uae_u32 srcreg = ((opcode >> 9) & 7);
20386: uae_u32 dstreg = opcode & 7;
20387: OpcodeFamily = 7; CurrentInstrCycles = 12;
20388: {{ uae_s8 src = m68k_dreg(regs, srcreg);
20389: { uaecptr dsta = m68k_areg(regs, dstreg);
20390: { uae_s8 dst = get_byte(dsta);
20391: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
20392: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
20393: { int flgs = ((uae_s8)(src)) < 0;
20394: int flgo = ((uae_s8)(dst)) < 0;
20395: int flgn = ((uae_s8)(newv)) < 0;
20396: SET_ZFLG (((uae_s8)(newv)) == 0);
20397: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20398: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
20399: COPY_CARRY;
20400: SET_NFLG (flgn != 0);
20401: put_byte(dsta,newv);
20402: }}}}}}}m68k_incpc(2);
20403: return 12;
20404: }
20405: unsigned long REGPARAM2 CPUFUNC(op_9120_0)(uae_u32 opcode) /* SUB */
20406: {
20407: uae_u32 srcreg = ((opcode >> 9) & 7);
20408: uae_u32 dstreg = opcode & 7;
20409: OpcodeFamily = 7; CurrentInstrCycles = 14;
20410: {{ uae_s8 src = m68k_dreg(regs, srcreg);
20411: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
20412: { uae_s8 dst = get_byte(dsta);
20413: m68k_areg (regs, dstreg) = dsta;
20414: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
20415: { int flgs = ((uae_s8)(src)) < 0;
20416: int flgo = ((uae_s8)(dst)) < 0;
20417: int flgn = ((uae_s8)(newv)) < 0;
20418: SET_ZFLG (((uae_s8)(newv)) == 0);
20419: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20420: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
20421: COPY_CARRY;
20422: SET_NFLG (flgn != 0);
20423: put_byte(dsta,newv);
20424: }}}}}}}m68k_incpc(2);
20425: return 14;
20426: }
20427: unsigned long REGPARAM2 CPUFUNC(op_9128_0)(uae_u32 opcode) /* SUB */
20428: {
20429: uae_u32 srcreg = ((opcode >> 9) & 7);
20430: uae_u32 dstreg = opcode & 7;
20431: OpcodeFamily = 7; CurrentInstrCycles = 16;
20432: {{ uae_s8 src = m68k_dreg(regs, srcreg);
20433: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
20434: { uae_s8 dst = get_byte(dsta);
20435: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
20436: { int flgs = ((uae_s8)(src)) < 0;
20437: int flgo = ((uae_s8)(dst)) < 0;
20438: int flgn = ((uae_s8)(newv)) < 0;
20439: SET_ZFLG (((uae_s8)(newv)) == 0);
20440: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20441: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
20442: COPY_CARRY;
20443: SET_NFLG (flgn != 0);
20444: put_byte(dsta,newv);
20445: }}}}}}}m68k_incpc(4);
20446: return 16;
20447: }
20448: unsigned long REGPARAM2 CPUFUNC(op_9130_0)(uae_u32 opcode) /* SUB */
20449: {
20450: uae_u32 srcreg = ((opcode >> 9) & 7);
20451: uae_u32 dstreg = opcode & 7;
20452: OpcodeFamily = 7; CurrentInstrCycles = 18;
20453: {{ uae_s8 src = m68k_dreg(regs, srcreg);
20454: {m68k_incpc(2);
20455: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
20456: BusCyclePenalty += 2;
20457: { uae_s8 dst = get_byte(dsta);
20458: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
20459: { int flgs = ((uae_s8)(src)) < 0;
20460: int flgo = ((uae_s8)(dst)) < 0;
20461: int flgn = ((uae_s8)(newv)) < 0;
20462: SET_ZFLG (((uae_s8)(newv)) == 0);
20463: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20464: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
20465: COPY_CARRY;
20466: SET_NFLG (flgn != 0);
20467: put_byte(dsta,newv);
20468: }}}}}}}}return 18;
20469: }
20470: unsigned long REGPARAM2 CPUFUNC(op_9138_0)(uae_u32 opcode) /* SUB */
20471: {
20472: uae_u32 srcreg = ((opcode >> 9) & 7);
20473: OpcodeFamily = 7; CurrentInstrCycles = 16;
20474: {{ uae_s8 src = m68k_dreg(regs, srcreg);
20475: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
20476: { uae_s8 dst = get_byte(dsta);
20477: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
20478: { int flgs = ((uae_s8)(src)) < 0;
20479: int flgo = ((uae_s8)(dst)) < 0;
20480: int flgn = ((uae_s8)(newv)) < 0;
20481: SET_ZFLG (((uae_s8)(newv)) == 0);
20482: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20483: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
20484: COPY_CARRY;
20485: SET_NFLG (flgn != 0);
20486: put_byte(dsta,newv);
20487: }}}}}}}m68k_incpc(4);
20488: return 16;
20489: }
20490: unsigned long REGPARAM2 CPUFUNC(op_9139_0)(uae_u32 opcode) /* SUB */
20491: {
20492: uae_u32 srcreg = ((opcode >> 9) & 7);
20493: OpcodeFamily = 7; CurrentInstrCycles = 20;
20494: {{ uae_s8 src = m68k_dreg(regs, srcreg);
20495: { uaecptr dsta = get_ilong(2);
20496: { uae_s8 dst = get_byte(dsta);
20497: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
20498: { int flgs = ((uae_s8)(src)) < 0;
20499: int flgo = ((uae_s8)(dst)) < 0;
20500: int flgn = ((uae_s8)(newv)) < 0;
20501: SET_ZFLG (((uae_s8)(newv)) == 0);
20502: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20503: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
20504: COPY_CARRY;
20505: SET_NFLG (flgn != 0);
20506: put_byte(dsta,newv);
20507: }}}}}}}m68k_incpc(6);
20508: return 20;
20509: }
20510: unsigned long REGPARAM2 CPUFUNC(op_9140_0)(uae_u32 opcode) /* SUBX */
20511: {
20512: uae_u32 srcreg = (opcode & 7);
20513: uae_u32 dstreg = (opcode >> 9) & 7;
20514: OpcodeFamily = 9; CurrentInstrCycles = 4;
20515: {{ uae_s16 src = m68k_dreg(regs, srcreg);
20516: { uae_s16 dst = m68k_dreg(regs, dstreg);
20517: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
20518: { int flgs = ((uae_s16)(src)) < 0;
20519: int flgo = ((uae_s16)(dst)) < 0;
20520: int flgn = ((uae_s16)(newv)) < 0;
20521: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
20522: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
20523: COPY_CARRY;
20524: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
20525: SET_NFLG (((uae_s16)(newv)) < 0);
20526: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
20527: }}}}}m68k_incpc(2);
20528: return 4;
20529: }
20530: unsigned long REGPARAM2 CPUFUNC(op_9148_0)(uae_u32 opcode) /* SUBX */
20531: {
20532: uae_u32 srcreg = (opcode & 7);
20533: uae_u32 dstreg = (opcode >> 9) & 7;
20534: OpcodeFamily = 9; CurrentInstrCycles = 18;
20535: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
20536: { uae_s16 src = get_word(srca);
20537: m68k_areg (regs, srcreg) = srca;
20538: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
20539: { uae_s16 dst = get_word(dsta);
20540: m68k_areg (regs, dstreg) = dsta;
20541: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
20542: { int flgs = ((uae_s16)(src)) < 0;
20543: int flgo = ((uae_s16)(dst)) < 0;
20544: int flgn = ((uae_s16)(newv)) < 0;
20545: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
20546: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
20547: COPY_CARRY;
20548: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
20549: SET_NFLG (((uae_s16)(newv)) < 0);
20550: put_word(dsta,newv);
20551: }}}}}}}m68k_incpc(2);
20552: return 18;
20553: }
20554: unsigned long REGPARAM2 CPUFUNC(op_9150_0)(uae_u32 opcode) /* SUB */
20555: {
20556: uae_u32 srcreg = ((opcode >> 9) & 7);
20557: uae_u32 dstreg = opcode & 7;
20558: OpcodeFamily = 7; CurrentInstrCycles = 12;
20559: {{ uae_s16 src = m68k_dreg(regs, srcreg);
20560: { uaecptr dsta = m68k_areg(regs, dstreg);
20561: { uae_s16 dst = get_word(dsta);
20562: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
20563: { int flgs = ((uae_s16)(src)) < 0;
20564: int flgo = ((uae_s16)(dst)) < 0;
20565: int flgn = ((uae_s16)(newv)) < 0;
20566: SET_ZFLG (((uae_s16)(newv)) == 0);
20567: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20568: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
20569: COPY_CARRY;
20570: SET_NFLG (flgn != 0);
20571: put_word(dsta,newv);
20572: }}}}}}}m68k_incpc(2);
20573: return 12;
20574: }
20575: unsigned long REGPARAM2 CPUFUNC(op_9158_0)(uae_u32 opcode) /* SUB */
20576: {
20577: uae_u32 srcreg = ((opcode >> 9) & 7);
20578: uae_u32 dstreg = opcode & 7;
20579: OpcodeFamily = 7; CurrentInstrCycles = 12;
20580: {{ uae_s16 src = m68k_dreg(regs, srcreg);
20581: { uaecptr dsta = m68k_areg(regs, dstreg);
20582: { uae_s16 dst = get_word(dsta);
20583: m68k_areg(regs, dstreg) += 2;
20584: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
20585: { int flgs = ((uae_s16)(src)) < 0;
20586: int flgo = ((uae_s16)(dst)) < 0;
20587: int flgn = ((uae_s16)(newv)) < 0;
20588: SET_ZFLG (((uae_s16)(newv)) == 0);
20589: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20590: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
20591: COPY_CARRY;
20592: SET_NFLG (flgn != 0);
20593: put_word(dsta,newv);
20594: }}}}}}}m68k_incpc(2);
20595: return 12;
20596: }
20597: unsigned long REGPARAM2 CPUFUNC(op_9160_0)(uae_u32 opcode) /* SUB */
20598: {
20599: uae_u32 srcreg = ((opcode >> 9) & 7);
20600: uae_u32 dstreg = opcode & 7;
20601: OpcodeFamily = 7; CurrentInstrCycles = 14;
20602: {{ uae_s16 src = m68k_dreg(regs, srcreg);
20603: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
20604: { uae_s16 dst = get_word(dsta);
20605: m68k_areg (regs, dstreg) = dsta;
20606: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
20607: { int flgs = ((uae_s16)(src)) < 0;
20608: int flgo = ((uae_s16)(dst)) < 0;
20609: int flgn = ((uae_s16)(newv)) < 0;
20610: SET_ZFLG (((uae_s16)(newv)) == 0);
20611: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20612: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
20613: COPY_CARRY;
20614: SET_NFLG (flgn != 0);
20615: put_word(dsta,newv);
20616: }}}}}}}m68k_incpc(2);
20617: return 14;
20618: }
20619: unsigned long REGPARAM2 CPUFUNC(op_9168_0)(uae_u32 opcode) /* SUB */
20620: {
20621: uae_u32 srcreg = ((opcode >> 9) & 7);
20622: uae_u32 dstreg = opcode & 7;
20623: OpcodeFamily = 7; CurrentInstrCycles = 16;
20624: {{ uae_s16 src = m68k_dreg(regs, srcreg);
20625: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
20626: { uae_s16 dst = get_word(dsta);
20627: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
20628: { int flgs = ((uae_s16)(src)) < 0;
20629: int flgo = ((uae_s16)(dst)) < 0;
20630: int flgn = ((uae_s16)(newv)) < 0;
20631: SET_ZFLG (((uae_s16)(newv)) == 0);
20632: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20633: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
20634: COPY_CARRY;
20635: SET_NFLG (flgn != 0);
20636: put_word(dsta,newv);
20637: }}}}}}}m68k_incpc(4);
20638: return 16;
20639: }
20640: unsigned long REGPARAM2 CPUFUNC(op_9170_0)(uae_u32 opcode) /* SUB */
20641: {
20642: uae_u32 srcreg = ((opcode >> 9) & 7);
20643: uae_u32 dstreg = opcode & 7;
20644: OpcodeFamily = 7; CurrentInstrCycles = 18;
20645: {{ uae_s16 src = m68k_dreg(regs, srcreg);
20646: {m68k_incpc(2);
20647: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
20648: BusCyclePenalty += 2;
20649: { uae_s16 dst = get_word(dsta);
20650: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
20651: { int flgs = ((uae_s16)(src)) < 0;
20652: int flgo = ((uae_s16)(dst)) < 0;
20653: int flgn = ((uae_s16)(newv)) < 0;
20654: SET_ZFLG (((uae_s16)(newv)) == 0);
20655: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20656: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
20657: COPY_CARRY;
20658: SET_NFLG (flgn != 0);
20659: put_word(dsta,newv);
20660: }}}}}}}}return 18;
20661: }
20662: unsigned long REGPARAM2 CPUFUNC(op_9178_0)(uae_u32 opcode) /* SUB */
20663: {
20664: uae_u32 srcreg = ((opcode >> 9) & 7);
20665: OpcodeFamily = 7; CurrentInstrCycles = 16;
20666: {{ uae_s16 src = m68k_dreg(regs, srcreg);
20667: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
20668: { uae_s16 dst = get_word(dsta);
20669: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
20670: { int flgs = ((uae_s16)(src)) < 0;
20671: int flgo = ((uae_s16)(dst)) < 0;
20672: int flgn = ((uae_s16)(newv)) < 0;
20673: SET_ZFLG (((uae_s16)(newv)) == 0);
20674: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20675: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
20676: COPY_CARRY;
20677: SET_NFLG (flgn != 0);
20678: put_word(dsta,newv);
20679: }}}}}}}m68k_incpc(4);
20680: return 16;
20681: }
20682: unsigned long REGPARAM2 CPUFUNC(op_9179_0)(uae_u32 opcode) /* SUB */
20683: {
20684: uae_u32 srcreg = ((opcode >> 9) & 7);
20685: OpcodeFamily = 7; CurrentInstrCycles = 20;
20686: {{ uae_s16 src = m68k_dreg(regs, srcreg);
20687: { uaecptr dsta = get_ilong(2);
20688: { uae_s16 dst = get_word(dsta);
20689: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
20690: { int flgs = ((uae_s16)(src)) < 0;
20691: int flgo = ((uae_s16)(dst)) < 0;
20692: int flgn = ((uae_s16)(newv)) < 0;
20693: SET_ZFLG (((uae_s16)(newv)) == 0);
20694: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20695: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
20696: COPY_CARRY;
20697: SET_NFLG (flgn != 0);
20698: put_word(dsta,newv);
20699: }}}}}}}m68k_incpc(6);
20700: return 20;
20701: }
20702: unsigned long REGPARAM2 CPUFUNC(op_9180_0)(uae_u32 opcode) /* SUBX */
20703: {
20704: uae_u32 srcreg = (opcode & 7);
20705: uae_u32 dstreg = (opcode >> 9) & 7;
20706: OpcodeFamily = 9; CurrentInstrCycles = 8;
20707: {{ uae_s32 src = m68k_dreg(regs, srcreg);
20708: { uae_s32 dst = m68k_dreg(regs, dstreg);
20709: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
20710: { int flgs = ((uae_s32)(src)) < 0;
20711: int flgo = ((uae_s32)(dst)) < 0;
20712: int flgn = ((uae_s32)(newv)) < 0;
20713: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
20714: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
20715: COPY_CARRY;
20716: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
20717: SET_NFLG (((uae_s32)(newv)) < 0);
20718: m68k_dreg(regs, dstreg) = (newv);
20719: }}}}}m68k_incpc(2);
20720: return 8;
20721: }
20722: unsigned long REGPARAM2 CPUFUNC(op_9188_0)(uae_u32 opcode) /* SUBX */
20723: {
20724: uae_u32 srcreg = (opcode & 7);
20725: uae_u32 dstreg = (opcode >> 9) & 7;
20726: OpcodeFamily = 9; CurrentInstrCycles = 30;
20727: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
20728: { uae_s32 src = get_long(srca);
20729: m68k_areg (regs, srcreg) = srca;
20730: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
20731: { uae_s32 dst = get_long(dsta);
20732: m68k_areg (regs, dstreg) = dsta;
20733: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
20734: { int flgs = ((uae_s32)(src)) < 0;
20735: int flgo = ((uae_s32)(dst)) < 0;
20736: int flgn = ((uae_s32)(newv)) < 0;
20737: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
20738: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
20739: COPY_CARRY;
20740: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
20741: SET_NFLG (((uae_s32)(newv)) < 0);
20742: put_long(dsta,newv);
20743: }}}}}}}m68k_incpc(2);
20744: return 30;
20745: }
20746: unsigned long REGPARAM2 CPUFUNC(op_9190_0)(uae_u32 opcode) /* SUB */
20747: {
20748: uae_u32 srcreg = ((opcode >> 9) & 7);
20749: uae_u32 dstreg = opcode & 7;
20750: OpcodeFamily = 7; CurrentInstrCycles = 20;
20751: {{ uae_s32 src = m68k_dreg(regs, srcreg);
20752: { uaecptr dsta = m68k_areg(regs, dstreg);
20753: { uae_s32 dst = get_long(dsta);
20754: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20755: { int flgs = ((uae_s32)(src)) < 0;
20756: int flgo = ((uae_s32)(dst)) < 0;
20757: int flgn = ((uae_s32)(newv)) < 0;
20758: SET_ZFLG (((uae_s32)(newv)) == 0);
20759: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20760: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20761: COPY_CARRY;
20762: SET_NFLG (flgn != 0);
20763: put_long(dsta,newv);
20764: }}}}}}}m68k_incpc(2);
20765: return 20;
20766: }
20767: unsigned long REGPARAM2 CPUFUNC(op_9198_0)(uae_u32 opcode) /* SUB */
20768: {
20769: uae_u32 srcreg = ((opcode >> 9) & 7);
20770: uae_u32 dstreg = opcode & 7;
20771: OpcodeFamily = 7; CurrentInstrCycles = 20;
20772: {{ uae_s32 src = m68k_dreg(regs, srcreg);
20773: { uaecptr dsta = m68k_areg(regs, dstreg);
20774: { uae_s32 dst = get_long(dsta);
20775: m68k_areg(regs, dstreg) += 4;
20776: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20777: { int flgs = ((uae_s32)(src)) < 0;
20778: int flgo = ((uae_s32)(dst)) < 0;
20779: int flgn = ((uae_s32)(newv)) < 0;
20780: SET_ZFLG (((uae_s32)(newv)) == 0);
20781: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20782: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20783: COPY_CARRY;
20784: SET_NFLG (flgn != 0);
20785: put_long(dsta,newv);
20786: }}}}}}}m68k_incpc(2);
20787: return 20;
20788: }
20789: unsigned long REGPARAM2 CPUFUNC(op_91a0_0)(uae_u32 opcode) /* SUB */
20790: {
20791: uae_u32 srcreg = ((opcode >> 9) & 7);
20792: uae_u32 dstreg = opcode & 7;
20793: OpcodeFamily = 7; CurrentInstrCycles = 22;
20794: {{ uae_s32 src = m68k_dreg(regs, srcreg);
20795: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
20796: { uae_s32 dst = get_long(dsta);
20797: m68k_areg (regs, dstreg) = dsta;
20798: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20799: { int flgs = ((uae_s32)(src)) < 0;
20800: int flgo = ((uae_s32)(dst)) < 0;
20801: int flgn = ((uae_s32)(newv)) < 0;
20802: SET_ZFLG (((uae_s32)(newv)) == 0);
20803: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20804: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20805: COPY_CARRY;
20806: SET_NFLG (flgn != 0);
20807: put_long(dsta,newv);
20808: }}}}}}}m68k_incpc(2);
20809: return 22;
20810: }
20811: unsigned long REGPARAM2 CPUFUNC(op_91a8_0)(uae_u32 opcode) /* SUB */
20812: {
20813: uae_u32 srcreg = ((opcode >> 9) & 7);
20814: uae_u32 dstreg = opcode & 7;
20815: OpcodeFamily = 7; CurrentInstrCycles = 24;
20816: {{ uae_s32 src = m68k_dreg(regs, srcreg);
20817: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
20818: { uae_s32 dst = get_long(dsta);
20819: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20820: { int flgs = ((uae_s32)(src)) < 0;
20821: int flgo = ((uae_s32)(dst)) < 0;
20822: int flgn = ((uae_s32)(newv)) < 0;
20823: SET_ZFLG (((uae_s32)(newv)) == 0);
20824: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20825: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20826: COPY_CARRY;
20827: SET_NFLG (flgn != 0);
20828: put_long(dsta,newv);
20829: }}}}}}}m68k_incpc(4);
20830: return 24;
20831: }
20832: unsigned long REGPARAM2 CPUFUNC(op_91b0_0)(uae_u32 opcode) /* SUB */
20833: {
20834: uae_u32 srcreg = ((opcode >> 9) & 7);
20835: uae_u32 dstreg = opcode & 7;
20836: OpcodeFamily = 7; CurrentInstrCycles = 26;
20837: {{ uae_s32 src = m68k_dreg(regs, srcreg);
20838: {m68k_incpc(2);
20839: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
20840: BusCyclePenalty += 2;
20841: { uae_s32 dst = get_long(dsta);
20842: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20843: { int flgs = ((uae_s32)(src)) < 0;
20844: int flgo = ((uae_s32)(dst)) < 0;
20845: int flgn = ((uae_s32)(newv)) < 0;
20846: SET_ZFLG (((uae_s32)(newv)) == 0);
20847: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20848: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20849: COPY_CARRY;
20850: SET_NFLG (flgn != 0);
20851: put_long(dsta,newv);
20852: }}}}}}}}return 26;
20853: }
20854: unsigned long REGPARAM2 CPUFUNC(op_91b8_0)(uae_u32 opcode) /* SUB */
20855: {
20856: uae_u32 srcreg = ((opcode >> 9) & 7);
20857: OpcodeFamily = 7; CurrentInstrCycles = 24;
20858: {{ uae_s32 src = m68k_dreg(regs, srcreg);
20859: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
20860: { uae_s32 dst = get_long(dsta);
20861: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20862: { int flgs = ((uae_s32)(src)) < 0;
20863: int flgo = ((uae_s32)(dst)) < 0;
20864: int flgn = ((uae_s32)(newv)) < 0;
20865: SET_ZFLG (((uae_s32)(newv)) == 0);
20866: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20867: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20868: COPY_CARRY;
20869: SET_NFLG (flgn != 0);
20870: put_long(dsta,newv);
20871: }}}}}}}m68k_incpc(4);
20872: return 24;
20873: }
20874: unsigned long REGPARAM2 CPUFUNC(op_91b9_0)(uae_u32 opcode) /* SUB */
20875: {
20876: uae_u32 srcreg = ((opcode >> 9) & 7);
20877: OpcodeFamily = 7; CurrentInstrCycles = 28;
20878: {{ uae_s32 src = m68k_dreg(regs, srcreg);
20879: { uaecptr dsta = get_ilong(2);
20880: { uae_s32 dst = get_long(dsta);
20881: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
20882: { int flgs = ((uae_s32)(src)) < 0;
20883: int flgo = ((uae_s32)(dst)) < 0;
20884: int flgn = ((uae_s32)(newv)) < 0;
20885: SET_ZFLG (((uae_s32)(newv)) == 0);
20886: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
20887: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
20888: COPY_CARRY;
20889: SET_NFLG (flgn != 0);
20890: put_long(dsta,newv);
20891: }}}}}}}m68k_incpc(6);
20892: return 28;
20893: }
20894: unsigned long REGPARAM2 CPUFUNC(op_91c0_0)(uae_u32 opcode) /* SUBA */
20895: {
20896: uae_u32 srcreg = (opcode & 7);
20897: uae_u32 dstreg = (opcode >> 9) & 7;
20898: OpcodeFamily = 8; CurrentInstrCycles = 8;
20899: {{ uae_s32 src = m68k_dreg(regs, srcreg);
20900: { uae_s32 dst = m68k_areg(regs, dstreg);
20901: { uae_u32 newv = dst - src;
20902: m68k_areg(regs, dstreg) = (newv);
20903: }}}}m68k_incpc(2);
20904: return 8;
20905: }
20906: unsigned long REGPARAM2 CPUFUNC(op_91c8_0)(uae_u32 opcode) /* SUBA */
20907: {
20908: uae_u32 srcreg = (opcode & 7);
20909: uae_u32 dstreg = (opcode >> 9) & 7;
20910: OpcodeFamily = 8; CurrentInstrCycles = 8;
20911: {{ uae_s32 src = m68k_areg(regs, srcreg);
20912: { uae_s32 dst = m68k_areg(regs, dstreg);
20913: { uae_u32 newv = dst - src;
20914: m68k_areg(regs, dstreg) = (newv);
20915: }}}}m68k_incpc(2);
20916: return 8;
20917: }
20918: unsigned long REGPARAM2 CPUFUNC(op_91d0_0)(uae_u32 opcode) /* SUBA */
20919: {
20920: uae_u32 srcreg = (opcode & 7);
20921: uae_u32 dstreg = (opcode >> 9) & 7;
20922: OpcodeFamily = 8; CurrentInstrCycles = 14;
20923: {{ uaecptr srca = m68k_areg(regs, srcreg);
20924: { uae_s32 src = get_long(srca);
20925: { uae_s32 dst = m68k_areg(regs, dstreg);
20926: { uae_u32 newv = dst - src;
20927: m68k_areg(regs, dstreg) = (newv);
20928: }}}}}m68k_incpc(2);
20929: return 14;
20930: }
20931: unsigned long REGPARAM2 CPUFUNC(op_91d8_0)(uae_u32 opcode) /* SUBA */
20932: {
20933: uae_u32 srcreg = (opcode & 7);
20934: uae_u32 dstreg = (opcode >> 9) & 7;
20935: OpcodeFamily = 8; CurrentInstrCycles = 14;
20936: {{ uaecptr srca = m68k_areg(regs, srcreg);
20937: { uae_s32 src = get_long(srca);
20938: m68k_areg(regs, srcreg) += 4;
20939: { uae_s32 dst = m68k_areg(regs, dstreg);
20940: { uae_u32 newv = dst - src;
20941: m68k_areg(regs, dstreg) = (newv);
20942: }}}}}m68k_incpc(2);
20943: return 14;
20944: }
20945: unsigned long REGPARAM2 CPUFUNC(op_91e0_0)(uae_u32 opcode) /* SUBA */
20946: {
20947: uae_u32 srcreg = (opcode & 7);
20948: uae_u32 dstreg = (opcode >> 9) & 7;
20949: OpcodeFamily = 8; CurrentInstrCycles = 16;
20950: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
20951: { uae_s32 src = get_long(srca);
20952: m68k_areg (regs, srcreg) = srca;
20953: { uae_s32 dst = m68k_areg(regs, dstreg);
20954: { uae_u32 newv = dst - src;
20955: m68k_areg(regs, dstreg) = (newv);
20956: }}}}}m68k_incpc(2);
20957: return 16;
20958: }
20959: unsigned long REGPARAM2 CPUFUNC(op_91e8_0)(uae_u32 opcode) /* SUBA */
20960: {
20961: uae_u32 srcreg = (opcode & 7);
20962: uae_u32 dstreg = (opcode >> 9) & 7;
20963: OpcodeFamily = 8; CurrentInstrCycles = 18;
20964: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
20965: { uae_s32 src = get_long(srca);
20966: { uae_s32 dst = m68k_areg(regs, dstreg);
20967: { uae_u32 newv = dst - src;
20968: m68k_areg(regs, dstreg) = (newv);
20969: }}}}}m68k_incpc(4);
20970: return 18;
20971: }
20972: unsigned long REGPARAM2 CPUFUNC(op_91f0_0)(uae_u32 opcode) /* SUBA */
20973: {
20974: uae_u32 srcreg = (opcode & 7);
20975: uae_u32 dstreg = (opcode >> 9) & 7;
20976: OpcodeFamily = 8; CurrentInstrCycles = 20;
20977: {{m68k_incpc(2);
20978: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
20979: BusCyclePenalty += 2;
20980: { uae_s32 src = get_long(srca);
20981: { uae_s32 dst = m68k_areg(regs, dstreg);
20982: { uae_u32 newv = dst - src;
20983: m68k_areg(regs, dstreg) = (newv);
20984: }}}}}}return 20;
20985: }
20986: unsigned long REGPARAM2 CPUFUNC(op_91f8_0)(uae_u32 opcode) /* SUBA */
20987: {
20988: uae_u32 dstreg = (opcode >> 9) & 7;
20989: OpcodeFamily = 8; CurrentInstrCycles = 18;
20990: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
20991: { uae_s32 src = get_long(srca);
20992: { uae_s32 dst = m68k_areg(regs, dstreg);
20993: { uae_u32 newv = dst - src;
20994: m68k_areg(regs, dstreg) = (newv);
20995: }}}}}m68k_incpc(4);
20996: return 18;
20997: }
20998: unsigned long REGPARAM2 CPUFUNC(op_91f9_0)(uae_u32 opcode) /* SUBA */
20999: {
21000: uae_u32 dstreg = (opcode >> 9) & 7;
21001: OpcodeFamily = 8; CurrentInstrCycles = 22;
21002: {{ uaecptr srca = get_ilong(2);
21003: { uae_s32 src = get_long(srca);
21004: { uae_s32 dst = m68k_areg(regs, dstreg);
21005: { uae_u32 newv = dst - src;
21006: m68k_areg(regs, dstreg) = (newv);
21007: }}}}}m68k_incpc(6);
21008: return 22;
21009: }
21010: unsigned long REGPARAM2 CPUFUNC(op_91fa_0)(uae_u32 opcode) /* SUBA */
21011: {
21012: uae_u32 dstreg = (opcode >> 9) & 7;
21013: OpcodeFamily = 8; CurrentInstrCycles = 18;
21014: {{ uaecptr srca = m68k_getpc () + 2;
21015: srca += (uae_s32)(uae_s16)get_iword(2);
21016: { uae_s32 src = get_long(srca);
21017: { uae_s32 dst = m68k_areg(regs, dstreg);
21018: { uae_u32 newv = dst - src;
21019: m68k_areg(regs, dstreg) = (newv);
21020: }}}}}m68k_incpc(4);
21021: return 18;
21022: }
21023: unsigned long REGPARAM2 CPUFUNC(op_91fb_0)(uae_u32 opcode) /* SUBA */
21024: {
21025: uae_u32 dstreg = (opcode >> 9) & 7;
21026: OpcodeFamily = 8; CurrentInstrCycles = 20;
21027: {{m68k_incpc(2);
21028: { uaecptr tmppc = m68k_getpc();
21029: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
21030: BusCyclePenalty += 2;
21031: { uae_s32 src = get_long(srca);
21032: { uae_s32 dst = m68k_areg(regs, dstreg);
21033: { uae_u32 newv = dst - src;
21034: m68k_areg(regs, dstreg) = (newv);
21035: }}}}}}return 20;
21036: }
21037: unsigned long REGPARAM2 CPUFUNC(op_91fc_0)(uae_u32 opcode) /* SUBA */
21038: {
21039: uae_u32 dstreg = (opcode >> 9) & 7;
21040: OpcodeFamily = 8; CurrentInstrCycles = 16;
21041: {{ uae_s32 src = get_ilong(2);
21042: { uae_s32 dst = m68k_areg(regs, dstreg);
21043: { uae_u32 newv = dst - src;
21044: m68k_areg(regs, dstreg) = (newv);
21045: }}}}m68k_incpc(6);
21046: return 16;
21047: }
21048: unsigned long REGPARAM2 CPUFUNC(op_b000_0)(uae_u32 opcode) /* CMP */
21049: {
21050: uae_u32 srcreg = (opcode & 7);
21051: uae_u32 dstreg = (opcode >> 9) & 7;
21052: OpcodeFamily = 25; CurrentInstrCycles = 4;
21053: {{ uae_s8 src = m68k_dreg(regs, srcreg);
21054: { uae_s8 dst = m68k_dreg(regs, dstreg);
21055: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21056: { int flgs = ((uae_s8)(src)) < 0;
21057: int flgo = ((uae_s8)(dst)) < 0;
21058: int flgn = ((uae_s8)(newv)) < 0;
21059: SET_ZFLG (((uae_s8)(newv)) == 0);
21060: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21061: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21062: SET_NFLG (flgn != 0);
21063: }}}}}}m68k_incpc(2);
21064: return 4;
21065: }
21066: unsigned long REGPARAM2 CPUFUNC(op_b010_0)(uae_u32 opcode) /* CMP */
21067: {
21068: uae_u32 srcreg = (opcode & 7);
21069: uae_u32 dstreg = (opcode >> 9) & 7;
21070: OpcodeFamily = 25; CurrentInstrCycles = 8;
21071: {{ uaecptr srca = m68k_areg(regs, srcreg);
21072: { uae_s8 src = get_byte(srca);
21073: { uae_s8 dst = m68k_dreg(regs, dstreg);
21074: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21075: { int flgs = ((uae_s8)(src)) < 0;
21076: int flgo = ((uae_s8)(dst)) < 0;
21077: int flgn = ((uae_s8)(newv)) < 0;
21078: SET_ZFLG (((uae_s8)(newv)) == 0);
21079: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21080: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21081: SET_NFLG (flgn != 0);
21082: }}}}}}}m68k_incpc(2);
21083: return 8;
21084: }
21085: unsigned long REGPARAM2 CPUFUNC(op_b018_0)(uae_u32 opcode) /* CMP */
21086: {
21087: uae_u32 srcreg = (opcode & 7);
21088: uae_u32 dstreg = (opcode >> 9) & 7;
21089: OpcodeFamily = 25; CurrentInstrCycles = 8;
21090: {{ uaecptr srca = m68k_areg(regs, srcreg);
21091: { uae_s8 src = get_byte(srca);
21092: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
21093: { uae_s8 dst = m68k_dreg(regs, dstreg);
21094: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21095: { int flgs = ((uae_s8)(src)) < 0;
21096: int flgo = ((uae_s8)(dst)) < 0;
21097: int flgn = ((uae_s8)(newv)) < 0;
21098: SET_ZFLG (((uae_s8)(newv)) == 0);
21099: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21100: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21101: SET_NFLG (flgn != 0);
21102: }}}}}}}m68k_incpc(2);
21103: return 8;
21104: }
21105: unsigned long REGPARAM2 CPUFUNC(op_b020_0)(uae_u32 opcode) /* CMP */
21106: {
21107: uae_u32 srcreg = (opcode & 7);
21108: uae_u32 dstreg = (opcode >> 9) & 7;
21109: OpcodeFamily = 25; CurrentInstrCycles = 10;
21110: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
21111: { uae_s8 src = get_byte(srca);
21112: m68k_areg (regs, srcreg) = srca;
21113: { uae_s8 dst = m68k_dreg(regs, dstreg);
21114: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21115: { int flgs = ((uae_s8)(src)) < 0;
21116: int flgo = ((uae_s8)(dst)) < 0;
21117: int flgn = ((uae_s8)(newv)) < 0;
21118: SET_ZFLG (((uae_s8)(newv)) == 0);
21119: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21120: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21121: SET_NFLG (flgn != 0);
21122: }}}}}}}m68k_incpc(2);
21123: return 10;
21124: }
21125: unsigned long REGPARAM2 CPUFUNC(op_b028_0)(uae_u32 opcode) /* CMP */
21126: {
21127: uae_u32 srcreg = (opcode & 7);
21128: uae_u32 dstreg = (opcode >> 9) & 7;
21129: OpcodeFamily = 25; CurrentInstrCycles = 12;
21130: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
21131: { uae_s8 src = get_byte(srca);
21132: { uae_s8 dst = m68k_dreg(regs, dstreg);
21133: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21134: { int flgs = ((uae_s8)(src)) < 0;
21135: int flgo = ((uae_s8)(dst)) < 0;
21136: int flgn = ((uae_s8)(newv)) < 0;
21137: SET_ZFLG (((uae_s8)(newv)) == 0);
21138: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21139: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21140: SET_NFLG (flgn != 0);
21141: }}}}}}}m68k_incpc(4);
21142: return 12;
21143: }
21144: unsigned long REGPARAM2 CPUFUNC(op_b030_0)(uae_u32 opcode) /* CMP */
21145: {
21146: uae_u32 srcreg = (opcode & 7);
21147: uae_u32 dstreg = (opcode >> 9) & 7;
21148: OpcodeFamily = 25; CurrentInstrCycles = 14;
21149: {{m68k_incpc(2);
21150: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
21151: BusCyclePenalty += 2;
21152: { uae_s8 src = get_byte(srca);
21153: { uae_s8 dst = m68k_dreg(regs, dstreg);
21154: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21155: { int flgs = ((uae_s8)(src)) < 0;
21156: int flgo = ((uae_s8)(dst)) < 0;
21157: int flgn = ((uae_s8)(newv)) < 0;
21158: SET_ZFLG (((uae_s8)(newv)) == 0);
21159: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21160: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21161: SET_NFLG (flgn != 0);
21162: }}}}}}}}return 14;
21163: }
21164: unsigned long REGPARAM2 CPUFUNC(op_b038_0)(uae_u32 opcode) /* CMP */
21165: {
21166: uae_u32 dstreg = (opcode >> 9) & 7;
21167: OpcodeFamily = 25; CurrentInstrCycles = 12;
21168: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
21169: { uae_s8 src = get_byte(srca);
21170: { uae_s8 dst = m68k_dreg(regs, dstreg);
21171: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21172: { int flgs = ((uae_s8)(src)) < 0;
21173: int flgo = ((uae_s8)(dst)) < 0;
21174: int flgn = ((uae_s8)(newv)) < 0;
21175: SET_ZFLG (((uae_s8)(newv)) == 0);
21176: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21177: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21178: SET_NFLG (flgn != 0);
21179: }}}}}}}m68k_incpc(4);
21180: return 12;
21181: }
21182: unsigned long REGPARAM2 CPUFUNC(op_b039_0)(uae_u32 opcode) /* CMP */
21183: {
21184: uae_u32 dstreg = (opcode >> 9) & 7;
21185: OpcodeFamily = 25; CurrentInstrCycles = 16;
21186: {{ uaecptr srca = get_ilong(2);
21187: { uae_s8 src = get_byte(srca);
21188: { uae_s8 dst = m68k_dreg(regs, dstreg);
21189: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21190: { int flgs = ((uae_s8)(src)) < 0;
21191: int flgo = ((uae_s8)(dst)) < 0;
21192: int flgn = ((uae_s8)(newv)) < 0;
21193: SET_ZFLG (((uae_s8)(newv)) == 0);
21194: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21195: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21196: SET_NFLG (flgn != 0);
21197: }}}}}}}m68k_incpc(6);
21198: return 16;
21199: }
21200: unsigned long REGPARAM2 CPUFUNC(op_b03a_0)(uae_u32 opcode) /* CMP */
21201: {
21202: uae_u32 dstreg = (opcode >> 9) & 7;
21203: OpcodeFamily = 25; CurrentInstrCycles = 12;
21204: {{ uaecptr srca = m68k_getpc () + 2;
21205: srca += (uae_s32)(uae_s16)get_iword(2);
21206: { uae_s8 src = get_byte(srca);
21207: { uae_s8 dst = m68k_dreg(regs, dstreg);
21208: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21209: { int flgs = ((uae_s8)(src)) < 0;
21210: int flgo = ((uae_s8)(dst)) < 0;
21211: int flgn = ((uae_s8)(newv)) < 0;
21212: SET_ZFLG (((uae_s8)(newv)) == 0);
21213: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21214: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21215: SET_NFLG (flgn != 0);
21216: }}}}}}}m68k_incpc(4);
21217: return 12;
21218: }
21219: unsigned long REGPARAM2 CPUFUNC(op_b03b_0)(uae_u32 opcode) /* CMP */
21220: {
21221: uae_u32 dstreg = (opcode >> 9) & 7;
21222: OpcodeFamily = 25; CurrentInstrCycles = 14;
21223: {{m68k_incpc(2);
21224: { uaecptr tmppc = m68k_getpc();
21225: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
21226: BusCyclePenalty += 2;
21227: { uae_s8 src = get_byte(srca);
21228: { uae_s8 dst = m68k_dreg(regs, dstreg);
21229: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21230: { int flgs = ((uae_s8)(src)) < 0;
21231: int flgo = ((uae_s8)(dst)) < 0;
21232: int flgn = ((uae_s8)(newv)) < 0;
21233: SET_ZFLG (((uae_s8)(newv)) == 0);
21234: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21235: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21236: SET_NFLG (flgn != 0);
21237: }}}}}}}}return 14;
21238: }
21239: #endif
21240:
21241: #ifdef PART_7
21242: unsigned long REGPARAM2 CPUFUNC(op_b03c_0)(uae_u32 opcode) /* CMP */
21243: {
21244: uae_u32 dstreg = (opcode >> 9) & 7;
21245: OpcodeFamily = 25; CurrentInstrCycles = 8;
21246: {{ uae_s8 src = get_ibyte(2);
21247: { uae_s8 dst = m68k_dreg(regs, dstreg);
21248: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21249: { int flgs = ((uae_s8)(src)) < 0;
21250: int flgo = ((uae_s8)(dst)) < 0;
21251: int flgn = ((uae_s8)(newv)) < 0;
21252: SET_ZFLG (((uae_s8)(newv)) == 0);
21253: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21254: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21255: SET_NFLG (flgn != 0);
21256: }}}}}}m68k_incpc(4);
21257: return 8;
21258: }
21259: unsigned long REGPARAM2 CPUFUNC(op_b040_0)(uae_u32 opcode) /* CMP */
21260: {
21261: uae_u32 srcreg = (opcode & 7);
21262: uae_u32 dstreg = (opcode >> 9) & 7;
21263: OpcodeFamily = 25; CurrentInstrCycles = 4;
21264: {{ uae_s16 src = m68k_dreg(regs, srcreg);
21265: { uae_s16 dst = m68k_dreg(regs, dstreg);
21266: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21267: { int flgs = ((uae_s16)(src)) < 0;
21268: int flgo = ((uae_s16)(dst)) < 0;
21269: int flgn = ((uae_s16)(newv)) < 0;
21270: SET_ZFLG (((uae_s16)(newv)) == 0);
21271: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21272: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21273: SET_NFLG (flgn != 0);
21274: }}}}}}m68k_incpc(2);
21275: return 4;
21276: }
21277: unsigned long REGPARAM2 CPUFUNC(op_b048_0)(uae_u32 opcode) /* CMP */
21278: {
21279: uae_u32 srcreg = (opcode & 7);
21280: uae_u32 dstreg = (opcode >> 9) & 7;
21281: OpcodeFamily = 25; CurrentInstrCycles = 4;
21282: {{ uae_s16 src = m68k_areg(regs, srcreg);
21283: { uae_s16 dst = m68k_dreg(regs, dstreg);
21284: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21285: { int flgs = ((uae_s16)(src)) < 0;
21286: int flgo = ((uae_s16)(dst)) < 0;
21287: int flgn = ((uae_s16)(newv)) < 0;
21288: SET_ZFLG (((uae_s16)(newv)) == 0);
21289: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21290: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21291: SET_NFLG (flgn != 0);
21292: }}}}}}m68k_incpc(2);
21293: return 4;
21294: }
21295: unsigned long REGPARAM2 CPUFUNC(op_b050_0)(uae_u32 opcode) /* CMP */
21296: {
21297: uae_u32 srcreg = (opcode & 7);
21298: uae_u32 dstreg = (opcode >> 9) & 7;
21299: OpcodeFamily = 25; CurrentInstrCycles = 8;
21300: {{ uaecptr srca = m68k_areg(regs, srcreg);
21301: { uae_s16 src = get_word(srca);
21302: { uae_s16 dst = m68k_dreg(regs, dstreg);
21303: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21304: { int flgs = ((uae_s16)(src)) < 0;
21305: int flgo = ((uae_s16)(dst)) < 0;
21306: int flgn = ((uae_s16)(newv)) < 0;
21307: SET_ZFLG (((uae_s16)(newv)) == 0);
21308: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21309: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21310: SET_NFLG (flgn != 0);
21311: }}}}}}}m68k_incpc(2);
21312: return 8;
21313: }
21314: unsigned long REGPARAM2 CPUFUNC(op_b058_0)(uae_u32 opcode) /* CMP */
21315: {
21316: uae_u32 srcreg = (opcode & 7);
21317: uae_u32 dstreg = (opcode >> 9) & 7;
21318: OpcodeFamily = 25; CurrentInstrCycles = 8;
21319: {{ uaecptr srca = m68k_areg(regs, srcreg);
21320: { uae_s16 src = get_word(srca);
21321: m68k_areg(regs, srcreg) += 2;
21322: { uae_s16 dst = m68k_dreg(regs, dstreg);
21323: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21324: { int flgs = ((uae_s16)(src)) < 0;
21325: int flgo = ((uae_s16)(dst)) < 0;
21326: int flgn = ((uae_s16)(newv)) < 0;
21327: SET_ZFLG (((uae_s16)(newv)) == 0);
21328: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21329: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21330: SET_NFLG (flgn != 0);
21331: }}}}}}}m68k_incpc(2);
21332: return 8;
21333: }
21334: unsigned long REGPARAM2 CPUFUNC(op_b060_0)(uae_u32 opcode) /* CMP */
21335: {
21336: uae_u32 srcreg = (opcode & 7);
21337: uae_u32 dstreg = (opcode >> 9) & 7;
21338: OpcodeFamily = 25; CurrentInstrCycles = 10;
21339: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
21340: { uae_s16 src = get_word(srca);
21341: m68k_areg (regs, srcreg) = srca;
21342: { uae_s16 dst = m68k_dreg(regs, dstreg);
21343: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21344: { int flgs = ((uae_s16)(src)) < 0;
21345: int flgo = ((uae_s16)(dst)) < 0;
21346: int flgn = ((uae_s16)(newv)) < 0;
21347: SET_ZFLG (((uae_s16)(newv)) == 0);
21348: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21349: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21350: SET_NFLG (flgn != 0);
21351: }}}}}}}m68k_incpc(2);
21352: return 10;
21353: }
21354: unsigned long REGPARAM2 CPUFUNC(op_b068_0)(uae_u32 opcode) /* CMP */
21355: {
21356: uae_u32 srcreg = (opcode & 7);
21357: uae_u32 dstreg = (opcode >> 9) & 7;
21358: OpcodeFamily = 25; CurrentInstrCycles = 12;
21359: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
21360: { uae_s16 src = get_word(srca);
21361: { uae_s16 dst = m68k_dreg(regs, dstreg);
21362: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21363: { int flgs = ((uae_s16)(src)) < 0;
21364: int flgo = ((uae_s16)(dst)) < 0;
21365: int flgn = ((uae_s16)(newv)) < 0;
21366: SET_ZFLG (((uae_s16)(newv)) == 0);
21367: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21368: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21369: SET_NFLG (flgn != 0);
21370: }}}}}}}m68k_incpc(4);
21371: return 12;
21372: }
21373: unsigned long REGPARAM2 CPUFUNC(op_b070_0)(uae_u32 opcode) /* CMP */
21374: {
21375: uae_u32 srcreg = (opcode & 7);
21376: uae_u32 dstreg = (opcode >> 9) & 7;
21377: OpcodeFamily = 25; CurrentInstrCycles = 14;
21378: {{m68k_incpc(2);
21379: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
21380: BusCyclePenalty += 2;
21381: { uae_s16 src = get_word(srca);
21382: { uae_s16 dst = m68k_dreg(regs, dstreg);
21383: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21384: { int flgs = ((uae_s16)(src)) < 0;
21385: int flgo = ((uae_s16)(dst)) < 0;
21386: int flgn = ((uae_s16)(newv)) < 0;
21387: SET_ZFLG (((uae_s16)(newv)) == 0);
21388: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21389: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21390: SET_NFLG (flgn != 0);
21391: }}}}}}}}return 14;
21392: }
21393: unsigned long REGPARAM2 CPUFUNC(op_b078_0)(uae_u32 opcode) /* CMP */
21394: {
21395: uae_u32 dstreg = (opcode >> 9) & 7;
21396: OpcodeFamily = 25; CurrentInstrCycles = 12;
21397: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
21398: { uae_s16 src = get_word(srca);
21399: { uae_s16 dst = m68k_dreg(regs, dstreg);
21400: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21401: { int flgs = ((uae_s16)(src)) < 0;
21402: int flgo = ((uae_s16)(dst)) < 0;
21403: int flgn = ((uae_s16)(newv)) < 0;
21404: SET_ZFLG (((uae_s16)(newv)) == 0);
21405: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21406: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21407: SET_NFLG (flgn != 0);
21408: }}}}}}}m68k_incpc(4);
21409: return 12;
21410: }
21411: unsigned long REGPARAM2 CPUFUNC(op_b079_0)(uae_u32 opcode) /* CMP */
21412: {
21413: uae_u32 dstreg = (opcode >> 9) & 7;
21414: OpcodeFamily = 25; CurrentInstrCycles = 16;
21415: {{ uaecptr srca = get_ilong(2);
21416: { uae_s16 src = get_word(srca);
21417: { uae_s16 dst = m68k_dreg(regs, dstreg);
21418: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21419: { int flgs = ((uae_s16)(src)) < 0;
21420: int flgo = ((uae_s16)(dst)) < 0;
21421: int flgn = ((uae_s16)(newv)) < 0;
21422: SET_ZFLG (((uae_s16)(newv)) == 0);
21423: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21424: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21425: SET_NFLG (flgn != 0);
21426: }}}}}}}m68k_incpc(6);
21427: return 16;
21428: }
21429: unsigned long REGPARAM2 CPUFUNC(op_b07a_0)(uae_u32 opcode) /* CMP */
21430: {
21431: uae_u32 dstreg = (opcode >> 9) & 7;
21432: OpcodeFamily = 25; CurrentInstrCycles = 12;
21433: {{ uaecptr srca = m68k_getpc () + 2;
21434: srca += (uae_s32)(uae_s16)get_iword(2);
21435: { uae_s16 src = get_word(srca);
21436: { uae_s16 dst = m68k_dreg(regs, dstreg);
21437: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21438: { int flgs = ((uae_s16)(src)) < 0;
21439: int flgo = ((uae_s16)(dst)) < 0;
21440: int flgn = ((uae_s16)(newv)) < 0;
21441: SET_ZFLG (((uae_s16)(newv)) == 0);
21442: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21443: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21444: SET_NFLG (flgn != 0);
21445: }}}}}}}m68k_incpc(4);
21446: return 12;
21447: }
21448: unsigned long REGPARAM2 CPUFUNC(op_b07b_0)(uae_u32 opcode) /* CMP */
21449: {
21450: uae_u32 dstreg = (opcode >> 9) & 7;
21451: OpcodeFamily = 25; CurrentInstrCycles = 14;
21452: {{m68k_incpc(2);
21453: { uaecptr tmppc = m68k_getpc();
21454: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
21455: BusCyclePenalty += 2;
21456: { uae_s16 src = get_word(srca);
21457: { uae_s16 dst = m68k_dreg(regs, dstreg);
21458: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21459: { int flgs = ((uae_s16)(src)) < 0;
21460: int flgo = ((uae_s16)(dst)) < 0;
21461: int flgn = ((uae_s16)(newv)) < 0;
21462: SET_ZFLG (((uae_s16)(newv)) == 0);
21463: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21464: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21465: SET_NFLG (flgn != 0);
21466: }}}}}}}}return 14;
21467: }
21468: unsigned long REGPARAM2 CPUFUNC(op_b07c_0)(uae_u32 opcode) /* CMP */
21469: {
21470: uae_u32 dstreg = (opcode >> 9) & 7;
21471: OpcodeFamily = 25; CurrentInstrCycles = 8;
21472: {{ uae_s16 src = get_iword(2);
21473: { uae_s16 dst = m68k_dreg(regs, dstreg);
21474: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
21475: { int flgs = ((uae_s16)(src)) < 0;
21476: int flgo = ((uae_s16)(dst)) < 0;
21477: int flgn = ((uae_s16)(newv)) < 0;
21478: SET_ZFLG (((uae_s16)(newv)) == 0);
21479: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21480: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
21481: SET_NFLG (flgn != 0);
21482: }}}}}}m68k_incpc(4);
21483: return 8;
21484: }
21485: unsigned long REGPARAM2 CPUFUNC(op_b080_0)(uae_u32 opcode) /* CMP */
21486: {
21487: uae_u32 srcreg = (opcode & 7);
21488: uae_u32 dstreg = (opcode >> 9) & 7;
21489: OpcodeFamily = 25; CurrentInstrCycles = 6;
21490: {{ uae_s32 src = m68k_dreg(regs, srcreg);
21491: { uae_s32 dst = m68k_dreg(regs, dstreg);
21492: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21493: { int flgs = ((uae_s32)(src)) < 0;
21494: int flgo = ((uae_s32)(dst)) < 0;
21495: int flgn = ((uae_s32)(newv)) < 0;
21496: SET_ZFLG (((uae_s32)(newv)) == 0);
21497: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21498: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21499: SET_NFLG (flgn != 0);
21500: }}}}}}m68k_incpc(2);
21501: return 6;
21502: }
21503: unsigned long REGPARAM2 CPUFUNC(op_b088_0)(uae_u32 opcode) /* CMP */
21504: {
21505: uae_u32 srcreg = (opcode & 7);
21506: uae_u32 dstreg = (opcode >> 9) & 7;
21507: OpcodeFamily = 25; CurrentInstrCycles = 6;
21508: {{ uae_s32 src = m68k_areg(regs, srcreg);
21509: { uae_s32 dst = m68k_dreg(regs, dstreg);
21510: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21511: { int flgs = ((uae_s32)(src)) < 0;
21512: int flgo = ((uae_s32)(dst)) < 0;
21513: int flgn = ((uae_s32)(newv)) < 0;
21514: SET_ZFLG (((uae_s32)(newv)) == 0);
21515: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21516: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21517: SET_NFLG (flgn != 0);
21518: }}}}}}m68k_incpc(2);
21519: return 6;
21520: }
21521: unsigned long REGPARAM2 CPUFUNC(op_b090_0)(uae_u32 opcode) /* CMP */
21522: {
21523: uae_u32 srcreg = (opcode & 7);
21524: uae_u32 dstreg = (opcode >> 9) & 7;
21525: OpcodeFamily = 25; CurrentInstrCycles = 14;
21526: {{ uaecptr srca = m68k_areg(regs, srcreg);
21527: { uae_s32 src = get_long(srca);
21528: { uae_s32 dst = m68k_dreg(regs, dstreg);
21529: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21530: { int flgs = ((uae_s32)(src)) < 0;
21531: int flgo = ((uae_s32)(dst)) < 0;
21532: int flgn = ((uae_s32)(newv)) < 0;
21533: SET_ZFLG (((uae_s32)(newv)) == 0);
21534: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21535: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21536: SET_NFLG (flgn != 0);
21537: }}}}}}}m68k_incpc(2);
21538: return 14;
21539: }
21540: unsigned long REGPARAM2 CPUFUNC(op_b098_0)(uae_u32 opcode) /* CMP */
21541: {
21542: uae_u32 srcreg = (opcode & 7);
21543: uae_u32 dstreg = (opcode >> 9) & 7;
21544: OpcodeFamily = 25; CurrentInstrCycles = 14;
21545: {{ uaecptr srca = m68k_areg(regs, srcreg);
21546: { uae_s32 src = get_long(srca);
21547: m68k_areg(regs, srcreg) += 4;
21548: { uae_s32 dst = m68k_dreg(regs, dstreg);
21549: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21550: { int flgs = ((uae_s32)(src)) < 0;
21551: int flgo = ((uae_s32)(dst)) < 0;
21552: int flgn = ((uae_s32)(newv)) < 0;
21553: SET_ZFLG (((uae_s32)(newv)) == 0);
21554: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21555: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21556: SET_NFLG (flgn != 0);
21557: }}}}}}}m68k_incpc(2);
21558: return 14;
21559: }
21560: unsigned long REGPARAM2 CPUFUNC(op_b0a0_0)(uae_u32 opcode) /* CMP */
21561: {
21562: uae_u32 srcreg = (opcode & 7);
21563: uae_u32 dstreg = (opcode >> 9) & 7;
21564: OpcodeFamily = 25; CurrentInstrCycles = 16;
21565: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
21566: { uae_s32 src = get_long(srca);
21567: m68k_areg (regs, srcreg) = srca;
21568: { uae_s32 dst = m68k_dreg(regs, dstreg);
21569: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21570: { int flgs = ((uae_s32)(src)) < 0;
21571: int flgo = ((uae_s32)(dst)) < 0;
21572: int flgn = ((uae_s32)(newv)) < 0;
21573: SET_ZFLG (((uae_s32)(newv)) == 0);
21574: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21575: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21576: SET_NFLG (flgn != 0);
21577: }}}}}}}m68k_incpc(2);
21578: return 16;
21579: }
21580: unsigned long REGPARAM2 CPUFUNC(op_b0a8_0)(uae_u32 opcode) /* CMP */
21581: {
21582: uae_u32 srcreg = (opcode & 7);
21583: uae_u32 dstreg = (opcode >> 9) & 7;
21584: OpcodeFamily = 25; CurrentInstrCycles = 18;
21585: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
21586: { uae_s32 src = get_long(srca);
21587: { uae_s32 dst = m68k_dreg(regs, dstreg);
21588: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21589: { int flgs = ((uae_s32)(src)) < 0;
21590: int flgo = ((uae_s32)(dst)) < 0;
21591: int flgn = ((uae_s32)(newv)) < 0;
21592: SET_ZFLG (((uae_s32)(newv)) == 0);
21593: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21594: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21595: SET_NFLG (flgn != 0);
21596: }}}}}}}m68k_incpc(4);
21597: return 18;
21598: }
21599: unsigned long REGPARAM2 CPUFUNC(op_b0b0_0)(uae_u32 opcode) /* CMP */
21600: {
21601: uae_u32 srcreg = (opcode & 7);
21602: uae_u32 dstreg = (opcode >> 9) & 7;
21603: OpcodeFamily = 25; CurrentInstrCycles = 20;
21604: {{m68k_incpc(2);
21605: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
21606: BusCyclePenalty += 2;
21607: { uae_s32 src = get_long(srca);
21608: { uae_s32 dst = m68k_dreg(regs, dstreg);
21609: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21610: { int flgs = ((uae_s32)(src)) < 0;
21611: int flgo = ((uae_s32)(dst)) < 0;
21612: int flgn = ((uae_s32)(newv)) < 0;
21613: SET_ZFLG (((uae_s32)(newv)) == 0);
21614: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21615: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21616: SET_NFLG (flgn != 0);
21617: }}}}}}}}return 20;
21618: }
21619: unsigned long REGPARAM2 CPUFUNC(op_b0b8_0)(uae_u32 opcode) /* CMP */
21620: {
21621: uae_u32 dstreg = (opcode >> 9) & 7;
21622: OpcodeFamily = 25; CurrentInstrCycles = 18;
21623: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
21624: { uae_s32 src = get_long(srca);
21625: { uae_s32 dst = m68k_dreg(regs, dstreg);
21626: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21627: { int flgs = ((uae_s32)(src)) < 0;
21628: int flgo = ((uae_s32)(dst)) < 0;
21629: int flgn = ((uae_s32)(newv)) < 0;
21630: SET_ZFLG (((uae_s32)(newv)) == 0);
21631: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21632: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21633: SET_NFLG (flgn != 0);
21634: }}}}}}}m68k_incpc(4);
21635: return 18;
21636: }
21637: unsigned long REGPARAM2 CPUFUNC(op_b0b9_0)(uae_u32 opcode) /* CMP */
21638: {
21639: uae_u32 dstreg = (opcode >> 9) & 7;
21640: OpcodeFamily = 25; CurrentInstrCycles = 22;
21641: {{ uaecptr srca = get_ilong(2);
21642: { uae_s32 src = get_long(srca);
21643: { uae_s32 dst = m68k_dreg(regs, dstreg);
21644: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21645: { int flgs = ((uae_s32)(src)) < 0;
21646: int flgo = ((uae_s32)(dst)) < 0;
21647: int flgn = ((uae_s32)(newv)) < 0;
21648: SET_ZFLG (((uae_s32)(newv)) == 0);
21649: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21650: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21651: SET_NFLG (flgn != 0);
21652: }}}}}}}m68k_incpc(6);
21653: return 22;
21654: }
21655: unsigned long REGPARAM2 CPUFUNC(op_b0ba_0)(uae_u32 opcode) /* CMP */
21656: {
21657: uae_u32 dstreg = (opcode >> 9) & 7;
21658: OpcodeFamily = 25; CurrentInstrCycles = 18;
21659: {{ uaecptr srca = m68k_getpc () + 2;
21660: srca += (uae_s32)(uae_s16)get_iword(2);
21661: { uae_s32 src = get_long(srca);
21662: { uae_s32 dst = m68k_dreg(regs, dstreg);
21663: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21664: { int flgs = ((uae_s32)(src)) < 0;
21665: int flgo = ((uae_s32)(dst)) < 0;
21666: int flgn = ((uae_s32)(newv)) < 0;
21667: SET_ZFLG (((uae_s32)(newv)) == 0);
21668: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21669: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21670: SET_NFLG (flgn != 0);
21671: }}}}}}}m68k_incpc(4);
21672: return 18;
21673: }
21674: unsigned long REGPARAM2 CPUFUNC(op_b0bb_0)(uae_u32 opcode) /* CMP */
21675: {
21676: uae_u32 dstreg = (opcode >> 9) & 7;
21677: OpcodeFamily = 25; CurrentInstrCycles = 20;
21678: {{m68k_incpc(2);
21679: { uaecptr tmppc = m68k_getpc();
21680: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
21681: BusCyclePenalty += 2;
21682: { uae_s32 src = get_long(srca);
21683: { uae_s32 dst = m68k_dreg(regs, dstreg);
21684: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21685: { int flgs = ((uae_s32)(src)) < 0;
21686: int flgo = ((uae_s32)(dst)) < 0;
21687: int flgn = ((uae_s32)(newv)) < 0;
21688: SET_ZFLG (((uae_s32)(newv)) == 0);
21689: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21690: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21691: SET_NFLG (flgn != 0);
21692: }}}}}}}}return 20;
21693: }
21694: unsigned long REGPARAM2 CPUFUNC(op_b0bc_0)(uae_u32 opcode) /* CMP */
21695: {
21696: uae_u32 dstreg = (opcode >> 9) & 7;
21697: OpcodeFamily = 25; CurrentInstrCycles = 14;
21698: {{ uae_s32 src = get_ilong(2);
21699: { uae_s32 dst = m68k_dreg(regs, dstreg);
21700: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21701: { int flgs = ((uae_s32)(src)) < 0;
21702: int flgo = ((uae_s32)(dst)) < 0;
21703: int flgn = ((uae_s32)(newv)) < 0;
21704: SET_ZFLG (((uae_s32)(newv)) == 0);
21705: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21706: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21707: SET_NFLG (flgn != 0);
21708: }}}}}}m68k_incpc(6);
21709: return 14;
21710: }
21711: unsigned long REGPARAM2 CPUFUNC(op_b0c0_0)(uae_u32 opcode) /* CMPA */
21712: {
21713: uae_u32 srcreg = (opcode & 7);
21714: uae_u32 dstreg = (opcode >> 9) & 7;
21715: OpcodeFamily = 27; CurrentInstrCycles = 6;
21716: {{ uae_s16 src = m68k_dreg(regs, srcreg);
21717: { uae_s32 dst = m68k_areg(regs, dstreg);
21718: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21719: { int flgs = ((uae_s32)(src)) < 0;
21720: int flgo = ((uae_s32)(dst)) < 0;
21721: int flgn = ((uae_s32)(newv)) < 0;
21722: SET_ZFLG (((uae_s32)(newv)) == 0);
21723: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21724: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21725: SET_NFLG (flgn != 0);
21726: }}}}}}m68k_incpc(2);
21727: return 6;
21728: }
21729: unsigned long REGPARAM2 CPUFUNC(op_b0c8_0)(uae_u32 opcode) /* CMPA */
21730: {
21731: uae_u32 srcreg = (opcode & 7);
21732: uae_u32 dstreg = (opcode >> 9) & 7;
21733: OpcodeFamily = 27; CurrentInstrCycles = 6;
21734: {{ uae_s16 src = m68k_areg(regs, srcreg);
21735: { uae_s32 dst = m68k_areg(regs, dstreg);
21736: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21737: { int flgs = ((uae_s32)(src)) < 0;
21738: int flgo = ((uae_s32)(dst)) < 0;
21739: int flgn = ((uae_s32)(newv)) < 0;
21740: SET_ZFLG (((uae_s32)(newv)) == 0);
21741: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21742: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21743: SET_NFLG (flgn != 0);
21744: }}}}}}m68k_incpc(2);
21745: return 6;
21746: }
21747: unsigned long REGPARAM2 CPUFUNC(op_b0d0_0)(uae_u32 opcode) /* CMPA */
21748: {
21749: uae_u32 srcreg = (opcode & 7);
21750: uae_u32 dstreg = (opcode >> 9) & 7;
21751: OpcodeFamily = 27; CurrentInstrCycles = 10;
21752: {{ uaecptr srca = m68k_areg(regs, srcreg);
21753: { uae_s16 src = get_word(srca);
21754: { uae_s32 dst = m68k_areg(regs, dstreg);
21755: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21756: { int flgs = ((uae_s32)(src)) < 0;
21757: int flgo = ((uae_s32)(dst)) < 0;
21758: int flgn = ((uae_s32)(newv)) < 0;
21759: SET_ZFLG (((uae_s32)(newv)) == 0);
21760: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21761: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21762: SET_NFLG (flgn != 0);
21763: }}}}}}}m68k_incpc(2);
21764: return 10;
21765: }
21766: unsigned long REGPARAM2 CPUFUNC(op_b0d8_0)(uae_u32 opcode) /* CMPA */
21767: {
21768: uae_u32 srcreg = (opcode & 7);
21769: uae_u32 dstreg = (opcode >> 9) & 7;
21770: OpcodeFamily = 27; CurrentInstrCycles = 10;
21771: {{ uaecptr srca = m68k_areg(regs, srcreg);
21772: { uae_s16 src = get_word(srca);
21773: m68k_areg(regs, srcreg) += 2;
21774: { uae_s32 dst = m68k_areg(regs, dstreg);
21775: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21776: { int flgs = ((uae_s32)(src)) < 0;
21777: int flgo = ((uae_s32)(dst)) < 0;
21778: int flgn = ((uae_s32)(newv)) < 0;
21779: SET_ZFLG (((uae_s32)(newv)) == 0);
21780: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21781: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21782: SET_NFLG (flgn != 0);
21783: }}}}}}}m68k_incpc(2);
21784: return 10;
21785: }
21786: unsigned long REGPARAM2 CPUFUNC(op_b0e0_0)(uae_u32 opcode) /* CMPA */
21787: {
21788: uae_u32 srcreg = (opcode & 7);
21789: uae_u32 dstreg = (opcode >> 9) & 7;
21790: OpcodeFamily = 27; CurrentInstrCycles = 12;
21791: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
21792: { uae_s16 src = get_word(srca);
21793: m68k_areg (regs, srcreg) = srca;
21794: { uae_s32 dst = m68k_areg(regs, dstreg);
21795: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21796: { int flgs = ((uae_s32)(src)) < 0;
21797: int flgo = ((uae_s32)(dst)) < 0;
21798: int flgn = ((uae_s32)(newv)) < 0;
21799: SET_ZFLG (((uae_s32)(newv)) == 0);
21800: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21801: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21802: SET_NFLG (flgn != 0);
21803: }}}}}}}m68k_incpc(2);
21804: return 12;
21805: }
21806: unsigned long REGPARAM2 CPUFUNC(op_b0e8_0)(uae_u32 opcode) /* CMPA */
21807: {
21808: uae_u32 srcreg = (opcode & 7);
21809: uae_u32 dstreg = (opcode >> 9) & 7;
21810: OpcodeFamily = 27; CurrentInstrCycles = 14;
21811: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
21812: { uae_s16 src = get_word(srca);
21813: { uae_s32 dst = m68k_areg(regs, dstreg);
21814: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21815: { int flgs = ((uae_s32)(src)) < 0;
21816: int flgo = ((uae_s32)(dst)) < 0;
21817: int flgn = ((uae_s32)(newv)) < 0;
21818: SET_ZFLG (((uae_s32)(newv)) == 0);
21819: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21820: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21821: SET_NFLG (flgn != 0);
21822: }}}}}}}m68k_incpc(4);
21823: return 14;
21824: }
21825: unsigned long REGPARAM2 CPUFUNC(op_b0f0_0)(uae_u32 opcode) /* CMPA */
21826: {
21827: uae_u32 srcreg = (opcode & 7);
21828: uae_u32 dstreg = (opcode >> 9) & 7;
21829: OpcodeFamily = 27; CurrentInstrCycles = 16;
21830: {{m68k_incpc(2);
21831: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
21832: BusCyclePenalty += 2;
21833: { uae_s16 src = get_word(srca);
21834: { uae_s32 dst = m68k_areg(regs, dstreg);
21835: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21836: { int flgs = ((uae_s32)(src)) < 0;
21837: int flgo = ((uae_s32)(dst)) < 0;
21838: int flgn = ((uae_s32)(newv)) < 0;
21839: SET_ZFLG (((uae_s32)(newv)) == 0);
21840: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21841: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21842: SET_NFLG (flgn != 0);
21843: }}}}}}}}return 16;
21844: }
21845: unsigned long REGPARAM2 CPUFUNC(op_b0f8_0)(uae_u32 opcode) /* CMPA */
21846: {
21847: uae_u32 dstreg = (opcode >> 9) & 7;
21848: OpcodeFamily = 27; CurrentInstrCycles = 14;
21849: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
21850: { uae_s16 src = get_word(srca);
21851: { uae_s32 dst = m68k_areg(regs, dstreg);
21852: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21853: { int flgs = ((uae_s32)(src)) < 0;
21854: int flgo = ((uae_s32)(dst)) < 0;
21855: int flgn = ((uae_s32)(newv)) < 0;
21856: SET_ZFLG (((uae_s32)(newv)) == 0);
21857: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21858: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21859: SET_NFLG (flgn != 0);
21860: }}}}}}}m68k_incpc(4);
21861: return 14;
21862: }
21863: unsigned long REGPARAM2 CPUFUNC(op_b0f9_0)(uae_u32 opcode) /* CMPA */
21864: {
21865: uae_u32 dstreg = (opcode >> 9) & 7;
21866: OpcodeFamily = 27; CurrentInstrCycles = 18;
21867: {{ uaecptr srca = get_ilong(2);
21868: { uae_s16 src = get_word(srca);
21869: { uae_s32 dst = m68k_areg(regs, dstreg);
21870: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21871: { int flgs = ((uae_s32)(src)) < 0;
21872: int flgo = ((uae_s32)(dst)) < 0;
21873: int flgn = ((uae_s32)(newv)) < 0;
21874: SET_ZFLG (((uae_s32)(newv)) == 0);
21875: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21876: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21877: SET_NFLG (flgn != 0);
21878: }}}}}}}m68k_incpc(6);
21879: return 18;
21880: }
21881: unsigned long REGPARAM2 CPUFUNC(op_b0fa_0)(uae_u32 opcode) /* CMPA */
21882: {
21883: uae_u32 dstreg = (opcode >> 9) & 7;
21884: OpcodeFamily = 27; CurrentInstrCycles = 14;
21885: {{ uaecptr srca = m68k_getpc () + 2;
21886: srca += (uae_s32)(uae_s16)get_iword(2);
21887: { uae_s16 src = get_word(srca);
21888: { uae_s32 dst = m68k_areg(regs, dstreg);
21889: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21890: { int flgs = ((uae_s32)(src)) < 0;
21891: int flgo = ((uae_s32)(dst)) < 0;
21892: int flgn = ((uae_s32)(newv)) < 0;
21893: SET_ZFLG (((uae_s32)(newv)) == 0);
21894: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21895: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21896: SET_NFLG (flgn != 0);
21897: }}}}}}}m68k_incpc(4);
21898: return 14;
21899: }
21900: unsigned long REGPARAM2 CPUFUNC(op_b0fb_0)(uae_u32 opcode) /* CMPA */
21901: {
21902: uae_u32 dstreg = (opcode >> 9) & 7;
21903: OpcodeFamily = 27; CurrentInstrCycles = 16;
21904: {{m68k_incpc(2);
21905: { uaecptr tmppc = m68k_getpc();
21906: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
21907: BusCyclePenalty += 2;
21908: { uae_s16 src = get_word(srca);
21909: { uae_s32 dst = m68k_areg(regs, dstreg);
21910: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21911: { int flgs = ((uae_s32)(src)) < 0;
21912: int flgo = ((uae_s32)(dst)) < 0;
21913: int flgn = ((uae_s32)(newv)) < 0;
21914: SET_ZFLG (((uae_s32)(newv)) == 0);
21915: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21916: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21917: SET_NFLG (flgn != 0);
21918: }}}}}}}}return 16;
21919: }
21920: unsigned long REGPARAM2 CPUFUNC(op_b0fc_0)(uae_u32 opcode) /* CMPA */
21921: {
21922: uae_u32 dstreg = (opcode >> 9) & 7;
21923: OpcodeFamily = 27; CurrentInstrCycles = 10;
21924: {{ uae_s16 src = get_iword(2);
21925: { uae_s32 dst = m68k_areg(regs, dstreg);
21926: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
21927: { int flgs = ((uae_s32)(src)) < 0;
21928: int flgo = ((uae_s32)(dst)) < 0;
21929: int flgn = ((uae_s32)(newv)) < 0;
21930: SET_ZFLG (((uae_s32)(newv)) == 0);
21931: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21932: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
21933: SET_NFLG (flgn != 0);
21934: }}}}}}m68k_incpc(4);
21935: return 10;
21936: }
21937: unsigned long REGPARAM2 CPUFUNC(op_b100_0)(uae_u32 opcode) /* EOR */
21938: {
21939: uae_u32 srcreg = ((opcode >> 9) & 7);
21940: uae_u32 dstreg = opcode & 7;
21941: OpcodeFamily = 3; CurrentInstrCycles = 4;
21942: {{ uae_s8 src = m68k_dreg(regs, srcreg);
21943: { uae_s8 dst = m68k_dreg(regs, dstreg);
21944: src ^= dst;
21945: CLEAR_CZNV;
21946: SET_ZFLG (((uae_s8)(src)) == 0);
21947: SET_NFLG (((uae_s8)(src)) < 0);
21948: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
21949: }}}m68k_incpc(2);
21950: return 4;
21951: }
21952: unsigned long REGPARAM2 CPUFUNC(op_b108_0)(uae_u32 opcode) /* CMPM */
21953: {
21954: uae_u32 srcreg = (opcode & 7);
21955: uae_u32 dstreg = (opcode >> 9) & 7;
21956: OpcodeFamily = 26; CurrentInstrCycles = 12;
21957: {{ uaecptr srca = m68k_areg(regs, srcreg);
21958: { uae_s8 src = get_byte(srca);
21959: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
21960: { uaecptr dsta = m68k_areg(regs, dstreg);
21961: { uae_s8 dst = get_byte(dsta);
21962: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
21963: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
21964: { int flgs = ((uae_s8)(src)) < 0;
21965: int flgo = ((uae_s8)(dst)) < 0;
21966: int flgn = ((uae_s8)(newv)) < 0;
21967: SET_ZFLG (((uae_s8)(newv)) == 0);
21968: SET_VFLG ((flgs != flgo) && (flgn != flgo));
21969: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
21970: SET_NFLG (flgn != 0);
21971: }}}}}}}}m68k_incpc(2);
21972: return 12;
21973: }
21974: unsigned long REGPARAM2 CPUFUNC(op_b110_0)(uae_u32 opcode) /* EOR */
21975: {
21976: uae_u32 srcreg = ((opcode >> 9) & 7);
21977: uae_u32 dstreg = opcode & 7;
21978: OpcodeFamily = 3; CurrentInstrCycles = 12;
21979: {{ uae_s8 src = m68k_dreg(regs, srcreg);
21980: { uaecptr dsta = m68k_areg(regs, dstreg);
21981: { uae_s8 dst = get_byte(dsta);
21982: src ^= dst;
21983: CLEAR_CZNV;
21984: SET_ZFLG (((uae_s8)(src)) == 0);
21985: SET_NFLG (((uae_s8)(src)) < 0);
21986: put_byte(dsta,src);
21987: }}}}m68k_incpc(2);
21988: return 12;
21989: }
21990: unsigned long REGPARAM2 CPUFUNC(op_b118_0)(uae_u32 opcode) /* EOR */
21991: {
21992: uae_u32 srcreg = ((opcode >> 9) & 7);
21993: uae_u32 dstreg = opcode & 7;
21994: OpcodeFamily = 3; CurrentInstrCycles = 12;
21995: {{ uae_s8 src = m68k_dreg(regs, srcreg);
21996: { uaecptr dsta = m68k_areg(regs, dstreg);
21997: { uae_s8 dst = get_byte(dsta);
21998: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
21999: src ^= dst;
22000: CLEAR_CZNV;
22001: SET_ZFLG (((uae_s8)(src)) == 0);
22002: SET_NFLG (((uae_s8)(src)) < 0);
22003: put_byte(dsta,src);
22004: }}}}m68k_incpc(2);
22005: return 12;
22006: }
22007: unsigned long REGPARAM2 CPUFUNC(op_b120_0)(uae_u32 opcode) /* EOR */
22008: {
22009: uae_u32 srcreg = ((opcode >> 9) & 7);
22010: uae_u32 dstreg = opcode & 7;
22011: OpcodeFamily = 3; CurrentInstrCycles = 14;
22012: {{ uae_s8 src = m68k_dreg(regs, srcreg);
22013: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
22014: { uae_s8 dst = get_byte(dsta);
22015: m68k_areg (regs, dstreg) = dsta;
22016: src ^= dst;
22017: CLEAR_CZNV;
22018: SET_ZFLG (((uae_s8)(src)) == 0);
22019: SET_NFLG (((uae_s8)(src)) < 0);
22020: put_byte(dsta,src);
22021: }}}}m68k_incpc(2);
22022: return 14;
22023: }
22024: unsigned long REGPARAM2 CPUFUNC(op_b128_0)(uae_u32 opcode) /* EOR */
22025: {
22026: uae_u32 srcreg = ((opcode >> 9) & 7);
22027: uae_u32 dstreg = opcode & 7;
22028: OpcodeFamily = 3; CurrentInstrCycles = 16;
22029: {{ uae_s8 src = m68k_dreg(regs, srcreg);
22030: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
22031: { uae_s8 dst = get_byte(dsta);
22032: src ^= dst;
22033: CLEAR_CZNV;
22034: SET_ZFLG (((uae_s8)(src)) == 0);
22035: SET_NFLG (((uae_s8)(src)) < 0);
22036: put_byte(dsta,src);
22037: }}}}m68k_incpc(4);
22038: return 16;
22039: }
22040: unsigned long REGPARAM2 CPUFUNC(op_b130_0)(uae_u32 opcode) /* EOR */
22041: {
22042: uae_u32 srcreg = ((opcode >> 9) & 7);
22043: uae_u32 dstreg = opcode & 7;
22044: OpcodeFamily = 3; CurrentInstrCycles = 18;
22045: {{ uae_s8 src = m68k_dreg(regs, srcreg);
22046: {m68k_incpc(2);
22047: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
22048: BusCyclePenalty += 2;
22049: { uae_s8 dst = get_byte(dsta);
22050: src ^= dst;
22051: CLEAR_CZNV;
22052: SET_ZFLG (((uae_s8)(src)) == 0);
22053: SET_NFLG (((uae_s8)(src)) < 0);
22054: put_byte(dsta,src);
22055: }}}}}return 18;
22056: }
22057: unsigned long REGPARAM2 CPUFUNC(op_b138_0)(uae_u32 opcode) /* EOR */
22058: {
22059: uae_u32 srcreg = ((opcode >> 9) & 7);
22060: OpcodeFamily = 3; CurrentInstrCycles = 16;
22061: {{ uae_s8 src = m68k_dreg(regs, srcreg);
22062: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
22063: { uae_s8 dst = get_byte(dsta);
22064: src ^= dst;
22065: CLEAR_CZNV;
22066: SET_ZFLG (((uae_s8)(src)) == 0);
22067: SET_NFLG (((uae_s8)(src)) < 0);
22068: put_byte(dsta,src);
22069: }}}}m68k_incpc(4);
22070: return 16;
22071: }
22072: unsigned long REGPARAM2 CPUFUNC(op_b139_0)(uae_u32 opcode) /* EOR */
22073: {
22074: uae_u32 srcreg = ((opcode >> 9) & 7);
22075: OpcodeFamily = 3; CurrentInstrCycles = 20;
22076: {{ uae_s8 src = m68k_dreg(regs, srcreg);
22077: { uaecptr dsta = get_ilong(2);
22078: { uae_s8 dst = get_byte(dsta);
22079: src ^= dst;
22080: CLEAR_CZNV;
22081: SET_ZFLG (((uae_s8)(src)) == 0);
22082: SET_NFLG (((uae_s8)(src)) < 0);
22083: put_byte(dsta,src);
22084: }}}}m68k_incpc(6);
22085: return 20;
22086: }
22087: unsigned long REGPARAM2 CPUFUNC(op_b140_0)(uae_u32 opcode) /* EOR */
22088: {
22089: uae_u32 srcreg = ((opcode >> 9) & 7);
22090: uae_u32 dstreg = opcode & 7;
22091: OpcodeFamily = 3; CurrentInstrCycles = 4;
22092: {{ uae_s16 src = m68k_dreg(regs, srcreg);
22093: { uae_s16 dst = m68k_dreg(regs, dstreg);
22094: src ^= dst;
22095: CLEAR_CZNV;
22096: SET_ZFLG (((uae_s16)(src)) == 0);
22097: SET_NFLG (((uae_s16)(src)) < 0);
22098: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22099: }}}m68k_incpc(2);
22100: return 4;
22101: }
22102: unsigned long REGPARAM2 CPUFUNC(op_b148_0)(uae_u32 opcode) /* CMPM */
22103: {
22104: uae_u32 srcreg = (opcode & 7);
22105: uae_u32 dstreg = (opcode >> 9) & 7;
22106: OpcodeFamily = 26; CurrentInstrCycles = 12;
22107: {{ uaecptr srca = m68k_areg(regs, srcreg);
22108: { uae_s16 src = get_word(srca);
22109: m68k_areg(regs, srcreg) += 2;
22110: { uaecptr dsta = m68k_areg(regs, dstreg);
22111: { uae_s16 dst = get_word(dsta);
22112: m68k_areg(regs, dstreg) += 2;
22113: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
22114: { int flgs = ((uae_s16)(src)) < 0;
22115: int flgo = ((uae_s16)(dst)) < 0;
22116: int flgn = ((uae_s16)(newv)) < 0;
22117: SET_ZFLG (((uae_s16)(newv)) == 0);
22118: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22119: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
22120: SET_NFLG (flgn != 0);
22121: }}}}}}}}m68k_incpc(2);
22122: return 12;
22123: }
22124: unsigned long REGPARAM2 CPUFUNC(op_b150_0)(uae_u32 opcode) /* EOR */
22125: {
22126: uae_u32 srcreg = ((opcode >> 9) & 7);
22127: uae_u32 dstreg = opcode & 7;
22128: OpcodeFamily = 3; CurrentInstrCycles = 12;
22129: {{ uae_s16 src = m68k_dreg(regs, srcreg);
22130: { uaecptr dsta = m68k_areg(regs, dstreg);
22131: { uae_s16 dst = get_word(dsta);
22132: src ^= dst;
22133: CLEAR_CZNV;
22134: SET_ZFLG (((uae_s16)(src)) == 0);
22135: SET_NFLG (((uae_s16)(src)) < 0);
22136: put_word(dsta,src);
22137: }}}}m68k_incpc(2);
22138: return 12;
22139: }
22140: unsigned long REGPARAM2 CPUFUNC(op_b158_0)(uae_u32 opcode) /* EOR */
22141: {
22142: uae_u32 srcreg = ((opcode >> 9) & 7);
22143: uae_u32 dstreg = opcode & 7;
22144: OpcodeFamily = 3; CurrentInstrCycles = 12;
22145: {{ uae_s16 src = m68k_dreg(regs, srcreg);
22146: { uaecptr dsta = m68k_areg(regs, dstreg);
22147: { uae_s16 dst = get_word(dsta);
22148: m68k_areg(regs, dstreg) += 2;
22149: src ^= dst;
22150: CLEAR_CZNV;
22151: SET_ZFLG (((uae_s16)(src)) == 0);
22152: SET_NFLG (((uae_s16)(src)) < 0);
22153: put_word(dsta,src);
22154: }}}}m68k_incpc(2);
22155: return 12;
22156: }
22157: unsigned long REGPARAM2 CPUFUNC(op_b160_0)(uae_u32 opcode) /* EOR */
22158: {
22159: uae_u32 srcreg = ((opcode >> 9) & 7);
22160: uae_u32 dstreg = opcode & 7;
22161: OpcodeFamily = 3; CurrentInstrCycles = 14;
22162: {{ uae_s16 src = m68k_dreg(regs, srcreg);
22163: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
22164: { uae_s16 dst = get_word(dsta);
22165: m68k_areg (regs, dstreg) = dsta;
22166: src ^= dst;
22167: CLEAR_CZNV;
22168: SET_ZFLG (((uae_s16)(src)) == 0);
22169: SET_NFLG (((uae_s16)(src)) < 0);
22170: put_word(dsta,src);
22171: }}}}m68k_incpc(2);
22172: return 14;
22173: }
22174: unsigned long REGPARAM2 CPUFUNC(op_b168_0)(uae_u32 opcode) /* EOR */
22175: {
22176: uae_u32 srcreg = ((opcode >> 9) & 7);
22177: uae_u32 dstreg = opcode & 7;
22178: OpcodeFamily = 3; CurrentInstrCycles = 16;
22179: {{ uae_s16 src = m68k_dreg(regs, srcreg);
22180: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
22181: { uae_s16 dst = get_word(dsta);
22182: src ^= dst;
22183: CLEAR_CZNV;
22184: SET_ZFLG (((uae_s16)(src)) == 0);
22185: SET_NFLG (((uae_s16)(src)) < 0);
22186: put_word(dsta,src);
22187: }}}}m68k_incpc(4);
22188: return 16;
22189: }
22190: unsigned long REGPARAM2 CPUFUNC(op_b170_0)(uae_u32 opcode) /* EOR */
22191: {
22192: uae_u32 srcreg = ((opcode >> 9) & 7);
22193: uae_u32 dstreg = opcode & 7;
22194: OpcodeFamily = 3; CurrentInstrCycles = 18;
22195: {{ uae_s16 src = m68k_dreg(regs, srcreg);
22196: {m68k_incpc(2);
22197: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
22198: BusCyclePenalty += 2;
22199: { uae_s16 dst = get_word(dsta);
22200: src ^= dst;
22201: CLEAR_CZNV;
22202: SET_ZFLG (((uae_s16)(src)) == 0);
22203: SET_NFLG (((uae_s16)(src)) < 0);
22204: put_word(dsta,src);
22205: }}}}}return 18;
22206: }
22207: unsigned long REGPARAM2 CPUFUNC(op_b178_0)(uae_u32 opcode) /* EOR */
22208: {
22209: uae_u32 srcreg = ((opcode >> 9) & 7);
22210: OpcodeFamily = 3; CurrentInstrCycles = 16;
22211: {{ uae_s16 src = m68k_dreg(regs, srcreg);
22212: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
22213: { uae_s16 dst = get_word(dsta);
22214: src ^= dst;
22215: CLEAR_CZNV;
22216: SET_ZFLG (((uae_s16)(src)) == 0);
22217: SET_NFLG (((uae_s16)(src)) < 0);
22218: put_word(dsta,src);
22219: }}}}m68k_incpc(4);
22220: return 16;
22221: }
22222: unsigned long REGPARAM2 CPUFUNC(op_b179_0)(uae_u32 opcode) /* EOR */
22223: {
22224: uae_u32 srcreg = ((opcode >> 9) & 7);
22225: OpcodeFamily = 3; CurrentInstrCycles = 20;
22226: {{ uae_s16 src = m68k_dreg(regs, srcreg);
22227: { uaecptr dsta = get_ilong(2);
22228: { uae_s16 dst = get_word(dsta);
22229: src ^= dst;
22230: CLEAR_CZNV;
22231: SET_ZFLG (((uae_s16)(src)) == 0);
22232: SET_NFLG (((uae_s16)(src)) < 0);
22233: put_word(dsta,src);
22234: }}}}m68k_incpc(6);
22235: return 20;
22236: }
22237: unsigned long REGPARAM2 CPUFUNC(op_b180_0)(uae_u32 opcode) /* EOR */
22238: {
22239: uae_u32 srcreg = ((opcode >> 9) & 7);
22240: uae_u32 dstreg = opcode & 7;
22241: OpcodeFamily = 3; CurrentInstrCycles = 8;
22242: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22243: { uae_s32 dst = m68k_dreg(regs, dstreg);
22244: src ^= dst;
22245: CLEAR_CZNV;
22246: SET_ZFLG (((uae_s32)(src)) == 0);
22247: SET_NFLG (((uae_s32)(src)) < 0);
22248: m68k_dreg(regs, dstreg) = (src);
22249: }}}m68k_incpc(2);
22250: return 8;
22251: }
22252: unsigned long REGPARAM2 CPUFUNC(op_b188_0)(uae_u32 opcode) /* CMPM */
22253: {
22254: uae_u32 srcreg = (opcode & 7);
22255: uae_u32 dstreg = (opcode >> 9) & 7;
22256: OpcodeFamily = 26; CurrentInstrCycles = 20;
22257: {{ uaecptr srca = m68k_areg(regs, srcreg);
22258: { uae_s32 src = get_long(srca);
22259: m68k_areg(regs, srcreg) += 4;
22260: { uaecptr dsta = m68k_areg(regs, dstreg);
22261: { uae_s32 dst = get_long(dsta);
22262: m68k_areg(regs, dstreg) += 4;
22263: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22264: { int flgs = ((uae_s32)(src)) < 0;
22265: int flgo = ((uae_s32)(dst)) < 0;
22266: int flgn = ((uae_s32)(newv)) < 0;
22267: SET_ZFLG (((uae_s32)(newv)) == 0);
22268: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22269: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22270: SET_NFLG (flgn != 0);
22271: }}}}}}}}m68k_incpc(2);
22272: return 20;
22273: }
22274: unsigned long REGPARAM2 CPUFUNC(op_b190_0)(uae_u32 opcode) /* EOR */
22275: {
22276: uae_u32 srcreg = ((opcode >> 9) & 7);
22277: uae_u32 dstreg = opcode & 7;
22278: OpcodeFamily = 3; CurrentInstrCycles = 20;
22279: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22280: { uaecptr dsta = m68k_areg(regs, dstreg);
22281: { uae_s32 dst = get_long(dsta);
22282: src ^= dst;
22283: CLEAR_CZNV;
22284: SET_ZFLG (((uae_s32)(src)) == 0);
22285: SET_NFLG (((uae_s32)(src)) < 0);
22286: put_long(dsta,src);
22287: }}}}m68k_incpc(2);
22288: return 20;
22289: }
22290: unsigned long REGPARAM2 CPUFUNC(op_b198_0)(uae_u32 opcode) /* EOR */
22291: {
22292: uae_u32 srcreg = ((opcode >> 9) & 7);
22293: uae_u32 dstreg = opcode & 7;
22294: OpcodeFamily = 3; CurrentInstrCycles = 20;
22295: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22296: { uaecptr dsta = m68k_areg(regs, dstreg);
22297: { uae_s32 dst = get_long(dsta);
22298: m68k_areg(regs, dstreg) += 4;
22299: src ^= dst;
22300: CLEAR_CZNV;
22301: SET_ZFLG (((uae_s32)(src)) == 0);
22302: SET_NFLG (((uae_s32)(src)) < 0);
22303: put_long(dsta,src);
22304: }}}}m68k_incpc(2);
22305: return 20;
22306: }
22307: unsigned long REGPARAM2 CPUFUNC(op_b1a0_0)(uae_u32 opcode) /* EOR */
22308: {
22309: uae_u32 srcreg = ((opcode >> 9) & 7);
22310: uae_u32 dstreg = opcode & 7;
22311: OpcodeFamily = 3; CurrentInstrCycles = 22;
22312: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22313: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
22314: { uae_s32 dst = get_long(dsta);
22315: m68k_areg (regs, dstreg) = dsta;
22316: src ^= dst;
22317: CLEAR_CZNV;
22318: SET_ZFLG (((uae_s32)(src)) == 0);
22319: SET_NFLG (((uae_s32)(src)) < 0);
22320: put_long(dsta,src);
22321: }}}}m68k_incpc(2);
22322: return 22;
22323: }
22324: unsigned long REGPARAM2 CPUFUNC(op_b1a8_0)(uae_u32 opcode) /* EOR */
22325: {
22326: uae_u32 srcreg = ((opcode >> 9) & 7);
22327: uae_u32 dstreg = opcode & 7;
22328: OpcodeFamily = 3; CurrentInstrCycles = 24;
22329: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22330: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
22331: { uae_s32 dst = get_long(dsta);
22332: src ^= dst;
22333: CLEAR_CZNV;
22334: SET_ZFLG (((uae_s32)(src)) == 0);
22335: SET_NFLG (((uae_s32)(src)) < 0);
22336: put_long(dsta,src);
22337: }}}}m68k_incpc(4);
22338: return 24;
22339: }
22340: unsigned long REGPARAM2 CPUFUNC(op_b1b0_0)(uae_u32 opcode) /* EOR */
22341: {
22342: uae_u32 srcreg = ((opcode >> 9) & 7);
22343: uae_u32 dstreg = opcode & 7;
22344: OpcodeFamily = 3; CurrentInstrCycles = 26;
22345: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22346: {m68k_incpc(2);
22347: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
22348: BusCyclePenalty += 2;
22349: { uae_s32 dst = get_long(dsta);
22350: src ^= dst;
22351: CLEAR_CZNV;
22352: SET_ZFLG (((uae_s32)(src)) == 0);
22353: SET_NFLG (((uae_s32)(src)) < 0);
22354: put_long(dsta,src);
22355: }}}}}return 26;
22356: }
22357: unsigned long REGPARAM2 CPUFUNC(op_b1b8_0)(uae_u32 opcode) /* EOR */
22358: {
22359: uae_u32 srcreg = ((opcode >> 9) & 7);
22360: OpcodeFamily = 3; CurrentInstrCycles = 24;
22361: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22362: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
22363: { uae_s32 dst = get_long(dsta);
22364: src ^= dst;
22365: CLEAR_CZNV;
22366: SET_ZFLG (((uae_s32)(src)) == 0);
22367: SET_NFLG (((uae_s32)(src)) < 0);
22368: put_long(dsta,src);
22369: }}}}m68k_incpc(4);
22370: return 24;
22371: }
22372: unsigned long REGPARAM2 CPUFUNC(op_b1b9_0)(uae_u32 opcode) /* EOR */
22373: {
22374: uae_u32 srcreg = ((opcode >> 9) & 7);
22375: OpcodeFamily = 3; CurrentInstrCycles = 28;
22376: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22377: { uaecptr dsta = get_ilong(2);
22378: { uae_s32 dst = get_long(dsta);
22379: src ^= dst;
22380: CLEAR_CZNV;
22381: SET_ZFLG (((uae_s32)(src)) == 0);
22382: SET_NFLG (((uae_s32)(src)) < 0);
22383: put_long(dsta,src);
22384: }}}}m68k_incpc(6);
22385: return 28;
22386: }
22387: unsigned long REGPARAM2 CPUFUNC(op_b1c0_0)(uae_u32 opcode) /* CMPA */
22388: {
22389: uae_u32 srcreg = (opcode & 7);
22390: uae_u32 dstreg = (opcode >> 9) & 7;
22391: OpcodeFamily = 27; CurrentInstrCycles = 6;
22392: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22393: { uae_s32 dst = m68k_areg(regs, dstreg);
22394: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22395: { int flgs = ((uae_s32)(src)) < 0;
22396: int flgo = ((uae_s32)(dst)) < 0;
22397: int flgn = ((uae_s32)(newv)) < 0;
22398: SET_ZFLG (((uae_s32)(newv)) == 0);
22399: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22400: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22401: SET_NFLG (flgn != 0);
22402: }}}}}}m68k_incpc(2);
22403: return 6;
22404: }
22405: unsigned long REGPARAM2 CPUFUNC(op_b1c8_0)(uae_u32 opcode) /* CMPA */
22406: {
22407: uae_u32 srcreg = (opcode & 7);
22408: uae_u32 dstreg = (opcode >> 9) & 7;
22409: OpcodeFamily = 27; CurrentInstrCycles = 6;
22410: {{ uae_s32 src = m68k_areg(regs, srcreg);
22411: { uae_s32 dst = m68k_areg(regs, dstreg);
22412: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22413: { int flgs = ((uae_s32)(src)) < 0;
22414: int flgo = ((uae_s32)(dst)) < 0;
22415: int flgn = ((uae_s32)(newv)) < 0;
22416: SET_ZFLG (((uae_s32)(newv)) == 0);
22417: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22418: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22419: SET_NFLG (flgn != 0);
22420: }}}}}}m68k_incpc(2);
22421: return 6;
22422: }
22423: unsigned long REGPARAM2 CPUFUNC(op_b1d0_0)(uae_u32 opcode) /* CMPA */
22424: {
22425: uae_u32 srcreg = (opcode & 7);
22426: uae_u32 dstreg = (opcode >> 9) & 7;
22427: OpcodeFamily = 27; CurrentInstrCycles = 14;
22428: {{ uaecptr srca = m68k_areg(regs, srcreg);
22429: { uae_s32 src = get_long(srca);
22430: { uae_s32 dst = m68k_areg(regs, dstreg);
22431: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22432: { int flgs = ((uae_s32)(src)) < 0;
22433: int flgo = ((uae_s32)(dst)) < 0;
22434: int flgn = ((uae_s32)(newv)) < 0;
22435: SET_ZFLG (((uae_s32)(newv)) == 0);
22436: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22437: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22438: SET_NFLG (flgn != 0);
22439: }}}}}}}m68k_incpc(2);
22440: return 14;
22441: }
22442: unsigned long REGPARAM2 CPUFUNC(op_b1d8_0)(uae_u32 opcode) /* CMPA */
22443: {
22444: uae_u32 srcreg = (opcode & 7);
22445: uae_u32 dstreg = (opcode >> 9) & 7;
22446: OpcodeFamily = 27; CurrentInstrCycles = 14;
22447: {{ uaecptr srca = m68k_areg(regs, srcreg);
22448: { uae_s32 src = get_long(srca);
22449: m68k_areg(regs, srcreg) += 4;
22450: { uae_s32 dst = m68k_areg(regs, dstreg);
22451: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22452: { int flgs = ((uae_s32)(src)) < 0;
22453: int flgo = ((uae_s32)(dst)) < 0;
22454: int flgn = ((uae_s32)(newv)) < 0;
22455: SET_ZFLG (((uae_s32)(newv)) == 0);
22456: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22457: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22458: SET_NFLG (flgn != 0);
22459: }}}}}}}m68k_incpc(2);
22460: return 14;
22461: }
22462: unsigned long REGPARAM2 CPUFUNC(op_b1e0_0)(uae_u32 opcode) /* CMPA */
22463: {
22464: uae_u32 srcreg = (opcode & 7);
22465: uae_u32 dstreg = (opcode >> 9) & 7;
22466: OpcodeFamily = 27; CurrentInstrCycles = 16;
22467: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
22468: { uae_s32 src = get_long(srca);
22469: m68k_areg (regs, srcreg) = srca;
22470: { uae_s32 dst = m68k_areg(regs, dstreg);
22471: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22472: { int flgs = ((uae_s32)(src)) < 0;
22473: int flgo = ((uae_s32)(dst)) < 0;
22474: int flgn = ((uae_s32)(newv)) < 0;
22475: SET_ZFLG (((uae_s32)(newv)) == 0);
22476: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22477: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22478: SET_NFLG (flgn != 0);
22479: }}}}}}}m68k_incpc(2);
22480: return 16;
22481: }
22482: unsigned long REGPARAM2 CPUFUNC(op_b1e8_0)(uae_u32 opcode) /* CMPA */
22483: {
22484: uae_u32 srcreg = (opcode & 7);
22485: uae_u32 dstreg = (opcode >> 9) & 7;
22486: OpcodeFamily = 27; CurrentInstrCycles = 18;
22487: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
22488: { uae_s32 src = get_long(srca);
22489: { uae_s32 dst = m68k_areg(regs, dstreg);
22490: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22491: { int flgs = ((uae_s32)(src)) < 0;
22492: int flgo = ((uae_s32)(dst)) < 0;
22493: int flgn = ((uae_s32)(newv)) < 0;
22494: SET_ZFLG (((uae_s32)(newv)) == 0);
22495: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22496: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22497: SET_NFLG (flgn != 0);
22498: }}}}}}}m68k_incpc(4);
22499: return 18;
22500: }
22501: unsigned long REGPARAM2 CPUFUNC(op_b1f0_0)(uae_u32 opcode) /* CMPA */
22502: {
22503: uae_u32 srcreg = (opcode & 7);
22504: uae_u32 dstreg = (opcode >> 9) & 7;
22505: OpcodeFamily = 27; CurrentInstrCycles = 20;
22506: {{m68k_incpc(2);
22507: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
22508: BusCyclePenalty += 2;
22509: { uae_s32 src = get_long(srca);
22510: { uae_s32 dst = m68k_areg(regs, dstreg);
22511: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22512: { int flgs = ((uae_s32)(src)) < 0;
22513: int flgo = ((uae_s32)(dst)) < 0;
22514: int flgn = ((uae_s32)(newv)) < 0;
22515: SET_ZFLG (((uae_s32)(newv)) == 0);
22516: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22517: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22518: SET_NFLG (flgn != 0);
22519: }}}}}}}}return 20;
22520: }
22521: unsigned long REGPARAM2 CPUFUNC(op_b1f8_0)(uae_u32 opcode) /* CMPA */
22522: {
22523: uae_u32 dstreg = (opcode >> 9) & 7;
22524: OpcodeFamily = 27; CurrentInstrCycles = 18;
22525: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
22526: { uae_s32 src = get_long(srca);
22527: { uae_s32 dst = m68k_areg(regs, dstreg);
22528: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22529: { int flgs = ((uae_s32)(src)) < 0;
22530: int flgo = ((uae_s32)(dst)) < 0;
22531: int flgn = ((uae_s32)(newv)) < 0;
22532: SET_ZFLG (((uae_s32)(newv)) == 0);
22533: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22534: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22535: SET_NFLG (flgn != 0);
22536: }}}}}}}m68k_incpc(4);
22537: return 18;
22538: }
22539: unsigned long REGPARAM2 CPUFUNC(op_b1f9_0)(uae_u32 opcode) /* CMPA */
22540: {
22541: uae_u32 dstreg = (opcode >> 9) & 7;
22542: OpcodeFamily = 27; CurrentInstrCycles = 22;
22543: {{ uaecptr srca = get_ilong(2);
22544: { uae_s32 src = get_long(srca);
22545: { uae_s32 dst = m68k_areg(regs, dstreg);
22546: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22547: { int flgs = ((uae_s32)(src)) < 0;
22548: int flgo = ((uae_s32)(dst)) < 0;
22549: int flgn = ((uae_s32)(newv)) < 0;
22550: SET_ZFLG (((uae_s32)(newv)) == 0);
22551: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22552: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22553: SET_NFLG (flgn != 0);
22554: }}}}}}}m68k_incpc(6);
22555: return 22;
22556: }
22557: unsigned long REGPARAM2 CPUFUNC(op_b1fa_0)(uae_u32 opcode) /* CMPA */
22558: {
22559: uae_u32 dstreg = (opcode >> 9) & 7;
22560: OpcodeFamily = 27; CurrentInstrCycles = 18;
22561: {{ uaecptr srca = m68k_getpc () + 2;
22562: srca += (uae_s32)(uae_s16)get_iword(2);
22563: { uae_s32 src = get_long(srca);
22564: { uae_s32 dst = m68k_areg(regs, dstreg);
22565: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22566: { int flgs = ((uae_s32)(src)) < 0;
22567: int flgo = ((uae_s32)(dst)) < 0;
22568: int flgn = ((uae_s32)(newv)) < 0;
22569: SET_ZFLG (((uae_s32)(newv)) == 0);
22570: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22571: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22572: SET_NFLG (flgn != 0);
22573: }}}}}}}m68k_incpc(4);
22574: return 18;
22575: }
22576: unsigned long REGPARAM2 CPUFUNC(op_b1fb_0)(uae_u32 opcode) /* CMPA */
22577: {
22578: uae_u32 dstreg = (opcode >> 9) & 7;
22579: OpcodeFamily = 27; CurrentInstrCycles = 20;
22580: {{m68k_incpc(2);
22581: { uaecptr tmppc = m68k_getpc();
22582: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
22583: BusCyclePenalty += 2;
22584: { uae_s32 src = get_long(srca);
22585: { uae_s32 dst = m68k_areg(regs, dstreg);
22586: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22587: { int flgs = ((uae_s32)(src)) < 0;
22588: int flgo = ((uae_s32)(dst)) < 0;
22589: int flgn = ((uae_s32)(newv)) < 0;
22590: SET_ZFLG (((uae_s32)(newv)) == 0);
22591: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22592: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22593: SET_NFLG (flgn != 0);
22594: }}}}}}}}return 20;
22595: }
22596: unsigned long REGPARAM2 CPUFUNC(op_b1fc_0)(uae_u32 opcode) /* CMPA */
22597: {
22598: uae_u32 dstreg = (opcode >> 9) & 7;
22599: OpcodeFamily = 27; CurrentInstrCycles = 14;
22600: {{ uae_s32 src = get_ilong(2);
22601: { uae_s32 dst = m68k_areg(regs, dstreg);
22602: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
22603: { int flgs = ((uae_s32)(src)) < 0;
22604: int flgo = ((uae_s32)(dst)) < 0;
22605: int flgn = ((uae_s32)(newv)) < 0;
22606: SET_ZFLG (((uae_s32)(newv)) == 0);
22607: SET_VFLG ((flgs != flgo) && (flgn != flgo));
22608: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
22609: SET_NFLG (flgn != 0);
22610: }}}}}}m68k_incpc(6);
22611: return 14;
22612: }
22613: unsigned long REGPARAM2 CPUFUNC(op_c000_0)(uae_u32 opcode) /* AND */
22614: {
22615: uae_u32 srcreg = (opcode & 7);
22616: uae_u32 dstreg = (opcode >> 9) & 7;
22617: OpcodeFamily = 2; CurrentInstrCycles = 4;
22618: {{ uae_s8 src = m68k_dreg(regs, srcreg);
22619: { uae_s8 dst = m68k_dreg(regs, dstreg);
22620: src &= dst;
22621: CLEAR_CZNV;
22622: SET_ZFLG (((uae_s8)(src)) == 0);
22623: SET_NFLG (((uae_s8)(src)) < 0);
22624: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22625: }}}m68k_incpc(2);
22626: return 4;
22627: }
22628: unsigned long REGPARAM2 CPUFUNC(op_c010_0)(uae_u32 opcode) /* AND */
22629: {
22630: uae_u32 srcreg = (opcode & 7);
22631: uae_u32 dstreg = (opcode >> 9) & 7;
22632: OpcodeFamily = 2; CurrentInstrCycles = 8;
22633: {{ uaecptr srca = m68k_areg(regs, srcreg);
22634: { uae_s8 src = get_byte(srca);
22635: { uae_s8 dst = m68k_dreg(regs, dstreg);
22636: src &= dst;
22637: CLEAR_CZNV;
22638: SET_ZFLG (((uae_s8)(src)) == 0);
22639: SET_NFLG (((uae_s8)(src)) < 0);
22640: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22641: }}}}m68k_incpc(2);
22642: return 8;
22643: }
22644: unsigned long REGPARAM2 CPUFUNC(op_c018_0)(uae_u32 opcode) /* AND */
22645: {
22646: uae_u32 srcreg = (opcode & 7);
22647: uae_u32 dstreg = (opcode >> 9) & 7;
22648: OpcodeFamily = 2; CurrentInstrCycles = 8;
22649: {{ uaecptr srca = m68k_areg(regs, srcreg);
22650: { uae_s8 src = get_byte(srca);
22651: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
22652: { uae_s8 dst = m68k_dreg(regs, dstreg);
22653: src &= dst;
22654: CLEAR_CZNV;
22655: SET_ZFLG (((uae_s8)(src)) == 0);
22656: SET_NFLG (((uae_s8)(src)) < 0);
22657: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22658: }}}}m68k_incpc(2);
22659: return 8;
22660: }
22661: unsigned long REGPARAM2 CPUFUNC(op_c020_0)(uae_u32 opcode) /* AND */
22662: {
22663: uae_u32 srcreg = (opcode & 7);
22664: uae_u32 dstreg = (opcode >> 9) & 7;
22665: OpcodeFamily = 2; CurrentInstrCycles = 10;
22666: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
22667: { uae_s8 src = get_byte(srca);
22668: m68k_areg (regs, srcreg) = srca;
22669: { uae_s8 dst = m68k_dreg(regs, dstreg);
22670: src &= dst;
22671: CLEAR_CZNV;
22672: SET_ZFLG (((uae_s8)(src)) == 0);
22673: SET_NFLG (((uae_s8)(src)) < 0);
22674: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22675: }}}}m68k_incpc(2);
22676: return 10;
22677: }
22678: unsigned long REGPARAM2 CPUFUNC(op_c028_0)(uae_u32 opcode) /* AND */
22679: {
22680: uae_u32 srcreg = (opcode & 7);
22681: uae_u32 dstreg = (opcode >> 9) & 7;
22682: OpcodeFamily = 2; CurrentInstrCycles = 12;
22683: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
22684: { uae_s8 src = get_byte(srca);
22685: { uae_s8 dst = m68k_dreg(regs, dstreg);
22686: src &= dst;
22687: CLEAR_CZNV;
22688: SET_ZFLG (((uae_s8)(src)) == 0);
22689: SET_NFLG (((uae_s8)(src)) < 0);
22690: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22691: }}}}m68k_incpc(4);
22692: return 12;
22693: }
22694: unsigned long REGPARAM2 CPUFUNC(op_c030_0)(uae_u32 opcode) /* AND */
22695: {
22696: uae_u32 srcreg = (opcode & 7);
22697: uae_u32 dstreg = (opcode >> 9) & 7;
22698: OpcodeFamily = 2; CurrentInstrCycles = 14;
22699: {{m68k_incpc(2);
22700: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
22701: BusCyclePenalty += 2;
22702: { uae_s8 src = get_byte(srca);
22703: { uae_s8 dst = m68k_dreg(regs, dstreg);
22704: src &= dst;
22705: CLEAR_CZNV;
22706: SET_ZFLG (((uae_s8)(src)) == 0);
22707: SET_NFLG (((uae_s8)(src)) < 0);
22708: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22709: }}}}}return 14;
22710: }
22711: unsigned long REGPARAM2 CPUFUNC(op_c038_0)(uae_u32 opcode) /* AND */
22712: {
22713: uae_u32 dstreg = (opcode >> 9) & 7;
22714: OpcodeFamily = 2; CurrentInstrCycles = 12;
22715: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
22716: { uae_s8 src = get_byte(srca);
22717: { uae_s8 dst = m68k_dreg(regs, dstreg);
22718: src &= dst;
22719: CLEAR_CZNV;
22720: SET_ZFLG (((uae_s8)(src)) == 0);
22721: SET_NFLG (((uae_s8)(src)) < 0);
22722: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22723: }}}}m68k_incpc(4);
22724: return 12;
22725: }
22726: unsigned long REGPARAM2 CPUFUNC(op_c039_0)(uae_u32 opcode) /* AND */
22727: {
22728: uae_u32 dstreg = (opcode >> 9) & 7;
22729: OpcodeFamily = 2; CurrentInstrCycles = 16;
22730: {{ uaecptr srca = get_ilong(2);
22731: { uae_s8 src = get_byte(srca);
22732: { uae_s8 dst = m68k_dreg(regs, dstreg);
22733: src &= dst;
22734: CLEAR_CZNV;
22735: SET_ZFLG (((uae_s8)(src)) == 0);
22736: SET_NFLG (((uae_s8)(src)) < 0);
22737: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22738: }}}}m68k_incpc(6);
22739: return 16;
22740: }
22741: unsigned long REGPARAM2 CPUFUNC(op_c03a_0)(uae_u32 opcode) /* AND */
22742: {
22743: uae_u32 dstreg = (opcode >> 9) & 7;
22744: OpcodeFamily = 2; CurrentInstrCycles = 12;
22745: {{ uaecptr srca = m68k_getpc () + 2;
22746: srca += (uae_s32)(uae_s16)get_iword(2);
22747: { uae_s8 src = get_byte(srca);
22748: { uae_s8 dst = m68k_dreg(regs, dstreg);
22749: src &= dst;
22750: CLEAR_CZNV;
22751: SET_ZFLG (((uae_s8)(src)) == 0);
22752: SET_NFLG (((uae_s8)(src)) < 0);
22753: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22754: }}}}m68k_incpc(4);
22755: return 12;
22756: }
22757: unsigned long REGPARAM2 CPUFUNC(op_c03b_0)(uae_u32 opcode) /* AND */
22758: {
22759: uae_u32 dstreg = (opcode >> 9) & 7;
22760: OpcodeFamily = 2; CurrentInstrCycles = 14;
22761: {{m68k_incpc(2);
22762: { uaecptr tmppc = m68k_getpc();
22763: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
22764: BusCyclePenalty += 2;
22765: { uae_s8 src = get_byte(srca);
22766: { uae_s8 dst = m68k_dreg(regs, dstreg);
22767: src &= dst;
22768: CLEAR_CZNV;
22769: SET_ZFLG (((uae_s8)(src)) == 0);
22770: SET_NFLG (((uae_s8)(src)) < 0);
22771: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22772: }}}}}return 14;
22773: }
22774: unsigned long REGPARAM2 CPUFUNC(op_c03c_0)(uae_u32 opcode) /* AND */
22775: {
22776: uae_u32 dstreg = (opcode >> 9) & 7;
22777: OpcodeFamily = 2; CurrentInstrCycles = 8;
22778: {{ uae_s8 src = get_ibyte(2);
22779: { uae_s8 dst = m68k_dreg(regs, dstreg);
22780: src &= dst;
22781: CLEAR_CZNV;
22782: SET_ZFLG (((uae_s8)(src)) == 0);
22783: SET_NFLG (((uae_s8)(src)) < 0);
22784: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
22785: }}}m68k_incpc(4);
22786: return 8;
22787: }
22788: unsigned long REGPARAM2 CPUFUNC(op_c040_0)(uae_u32 opcode) /* AND */
22789: {
22790: uae_u32 srcreg = (opcode & 7);
22791: uae_u32 dstreg = (opcode >> 9) & 7;
22792: OpcodeFamily = 2; CurrentInstrCycles = 4;
22793: {{ uae_s16 src = m68k_dreg(regs, srcreg);
22794: { uae_s16 dst = m68k_dreg(regs, dstreg);
22795: src &= dst;
22796: CLEAR_CZNV;
22797: SET_ZFLG (((uae_s16)(src)) == 0);
22798: SET_NFLG (((uae_s16)(src)) < 0);
22799: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22800: }}}m68k_incpc(2);
22801: return 4;
22802: }
22803: unsigned long REGPARAM2 CPUFUNC(op_c050_0)(uae_u32 opcode) /* AND */
22804: {
22805: uae_u32 srcreg = (opcode & 7);
22806: uae_u32 dstreg = (opcode >> 9) & 7;
22807: OpcodeFamily = 2; CurrentInstrCycles = 8;
22808: {{ uaecptr srca = m68k_areg(regs, srcreg);
22809: { uae_s16 src = get_word(srca);
22810: { uae_s16 dst = m68k_dreg(regs, dstreg);
22811: src &= dst;
22812: CLEAR_CZNV;
22813: SET_ZFLG (((uae_s16)(src)) == 0);
22814: SET_NFLG (((uae_s16)(src)) < 0);
22815: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22816: }}}}m68k_incpc(2);
22817: return 8;
22818: }
22819: unsigned long REGPARAM2 CPUFUNC(op_c058_0)(uae_u32 opcode) /* AND */
22820: {
22821: uae_u32 srcreg = (opcode & 7);
22822: uae_u32 dstreg = (opcode >> 9) & 7;
22823: OpcodeFamily = 2; CurrentInstrCycles = 8;
22824: {{ uaecptr srca = m68k_areg(regs, srcreg);
22825: { uae_s16 src = get_word(srca);
22826: m68k_areg(regs, srcreg) += 2;
22827: { uae_s16 dst = m68k_dreg(regs, dstreg);
22828: src &= dst;
22829: CLEAR_CZNV;
22830: SET_ZFLG (((uae_s16)(src)) == 0);
22831: SET_NFLG (((uae_s16)(src)) < 0);
22832: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22833: }}}}m68k_incpc(2);
22834: return 8;
22835: }
22836: unsigned long REGPARAM2 CPUFUNC(op_c060_0)(uae_u32 opcode) /* AND */
22837: {
22838: uae_u32 srcreg = (opcode & 7);
22839: uae_u32 dstreg = (opcode >> 9) & 7;
22840: OpcodeFamily = 2; CurrentInstrCycles = 10;
22841: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
22842: { uae_s16 src = get_word(srca);
22843: m68k_areg (regs, srcreg) = srca;
22844: { uae_s16 dst = m68k_dreg(regs, dstreg);
22845: src &= dst;
22846: CLEAR_CZNV;
22847: SET_ZFLG (((uae_s16)(src)) == 0);
22848: SET_NFLG (((uae_s16)(src)) < 0);
22849: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22850: }}}}m68k_incpc(2);
22851: return 10;
22852: }
22853: unsigned long REGPARAM2 CPUFUNC(op_c068_0)(uae_u32 opcode) /* AND */
22854: {
22855: uae_u32 srcreg = (opcode & 7);
22856: uae_u32 dstreg = (opcode >> 9) & 7;
22857: OpcodeFamily = 2; CurrentInstrCycles = 12;
22858: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
22859: { uae_s16 src = get_word(srca);
22860: { uae_s16 dst = m68k_dreg(regs, dstreg);
22861: src &= dst;
22862: CLEAR_CZNV;
22863: SET_ZFLG (((uae_s16)(src)) == 0);
22864: SET_NFLG (((uae_s16)(src)) < 0);
22865: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22866: }}}}m68k_incpc(4);
22867: return 12;
22868: }
22869: unsigned long REGPARAM2 CPUFUNC(op_c070_0)(uae_u32 opcode) /* AND */
22870: {
22871: uae_u32 srcreg = (opcode & 7);
22872: uae_u32 dstreg = (opcode >> 9) & 7;
22873: OpcodeFamily = 2; CurrentInstrCycles = 14;
22874: {{m68k_incpc(2);
22875: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
22876: BusCyclePenalty += 2;
22877: { uae_s16 src = get_word(srca);
22878: { uae_s16 dst = m68k_dreg(regs, dstreg);
22879: src &= dst;
22880: CLEAR_CZNV;
22881: SET_ZFLG (((uae_s16)(src)) == 0);
22882: SET_NFLG (((uae_s16)(src)) < 0);
22883: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22884: }}}}}return 14;
22885: }
22886: unsigned long REGPARAM2 CPUFUNC(op_c078_0)(uae_u32 opcode) /* AND */
22887: {
22888: uae_u32 dstreg = (opcode >> 9) & 7;
22889: OpcodeFamily = 2; CurrentInstrCycles = 12;
22890: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
22891: { uae_s16 src = get_word(srca);
22892: { uae_s16 dst = m68k_dreg(regs, dstreg);
22893: src &= dst;
22894: CLEAR_CZNV;
22895: SET_ZFLG (((uae_s16)(src)) == 0);
22896: SET_NFLG (((uae_s16)(src)) < 0);
22897: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22898: }}}}m68k_incpc(4);
22899: return 12;
22900: }
22901: unsigned long REGPARAM2 CPUFUNC(op_c079_0)(uae_u32 opcode) /* AND */
22902: {
22903: uae_u32 dstreg = (opcode >> 9) & 7;
22904: OpcodeFamily = 2; CurrentInstrCycles = 16;
22905: {{ uaecptr srca = get_ilong(2);
22906: { uae_s16 src = get_word(srca);
22907: { uae_s16 dst = m68k_dreg(regs, dstreg);
22908: src &= dst;
22909: CLEAR_CZNV;
22910: SET_ZFLG (((uae_s16)(src)) == 0);
22911: SET_NFLG (((uae_s16)(src)) < 0);
22912: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22913: }}}}m68k_incpc(6);
22914: return 16;
22915: }
22916: unsigned long REGPARAM2 CPUFUNC(op_c07a_0)(uae_u32 opcode) /* AND */
22917: {
22918: uae_u32 dstreg = (opcode >> 9) & 7;
22919: OpcodeFamily = 2; CurrentInstrCycles = 12;
22920: {{ uaecptr srca = m68k_getpc () + 2;
22921: srca += (uae_s32)(uae_s16)get_iword(2);
22922: { uae_s16 src = get_word(srca);
22923: { uae_s16 dst = m68k_dreg(regs, dstreg);
22924: src &= dst;
22925: CLEAR_CZNV;
22926: SET_ZFLG (((uae_s16)(src)) == 0);
22927: SET_NFLG (((uae_s16)(src)) < 0);
22928: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22929: }}}}m68k_incpc(4);
22930: return 12;
22931: }
22932: unsigned long REGPARAM2 CPUFUNC(op_c07b_0)(uae_u32 opcode) /* AND */
22933: {
22934: uae_u32 dstreg = (opcode >> 9) & 7;
22935: OpcodeFamily = 2; CurrentInstrCycles = 14;
22936: {{m68k_incpc(2);
22937: { uaecptr tmppc = m68k_getpc();
22938: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
22939: BusCyclePenalty += 2;
22940: { uae_s16 src = get_word(srca);
22941: { uae_s16 dst = m68k_dreg(regs, dstreg);
22942: src &= dst;
22943: CLEAR_CZNV;
22944: SET_ZFLG (((uae_s16)(src)) == 0);
22945: SET_NFLG (((uae_s16)(src)) < 0);
22946: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22947: }}}}}return 14;
22948: }
22949: unsigned long REGPARAM2 CPUFUNC(op_c07c_0)(uae_u32 opcode) /* AND */
22950: {
22951: uae_u32 dstreg = (opcode >> 9) & 7;
22952: OpcodeFamily = 2; CurrentInstrCycles = 8;
22953: {{ uae_s16 src = get_iword(2);
22954: { uae_s16 dst = m68k_dreg(regs, dstreg);
22955: src &= dst;
22956: CLEAR_CZNV;
22957: SET_ZFLG (((uae_s16)(src)) == 0);
22958: SET_NFLG (((uae_s16)(src)) < 0);
22959: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
22960: }}}m68k_incpc(4);
22961: return 8;
22962: }
22963: unsigned long REGPARAM2 CPUFUNC(op_c080_0)(uae_u32 opcode) /* AND */
22964: {
22965: uae_u32 srcreg = (opcode & 7);
22966: uae_u32 dstreg = (opcode >> 9) & 7;
22967: OpcodeFamily = 2; CurrentInstrCycles = 8;
22968: {{ uae_s32 src = m68k_dreg(regs, srcreg);
22969: { uae_s32 dst = m68k_dreg(regs, dstreg);
22970: src &= dst;
22971: CLEAR_CZNV;
22972: SET_ZFLG (((uae_s32)(src)) == 0);
22973: SET_NFLG (((uae_s32)(src)) < 0);
22974: m68k_dreg(regs, dstreg) = (src);
22975: }}}m68k_incpc(2);
22976: return 8;
22977: }
22978: unsigned long REGPARAM2 CPUFUNC(op_c090_0)(uae_u32 opcode) /* AND */
22979: {
22980: uae_u32 srcreg = (opcode & 7);
22981: uae_u32 dstreg = (opcode >> 9) & 7;
22982: OpcodeFamily = 2; CurrentInstrCycles = 14;
22983: {{ uaecptr srca = m68k_areg(regs, srcreg);
22984: { uae_s32 src = get_long(srca);
22985: { uae_s32 dst = m68k_dreg(regs, dstreg);
22986: src &= dst;
22987: CLEAR_CZNV;
22988: SET_ZFLG (((uae_s32)(src)) == 0);
22989: SET_NFLG (((uae_s32)(src)) < 0);
22990: m68k_dreg(regs, dstreg) = (src);
22991: }}}}m68k_incpc(2);
22992: return 14;
22993: }
22994: unsigned long REGPARAM2 CPUFUNC(op_c098_0)(uae_u32 opcode) /* AND */
22995: {
22996: uae_u32 srcreg = (opcode & 7);
22997: uae_u32 dstreg = (opcode >> 9) & 7;
22998: OpcodeFamily = 2; CurrentInstrCycles = 14;
22999: {{ uaecptr srca = m68k_areg(regs, srcreg);
23000: { uae_s32 src = get_long(srca);
23001: m68k_areg(regs, srcreg) += 4;
23002: { uae_s32 dst = m68k_dreg(regs, dstreg);
23003: src &= dst;
23004: CLEAR_CZNV;
23005: SET_ZFLG (((uae_s32)(src)) == 0);
23006: SET_NFLG (((uae_s32)(src)) < 0);
23007: m68k_dreg(regs, dstreg) = (src);
23008: }}}}m68k_incpc(2);
23009: return 14;
23010: }
23011: unsigned long REGPARAM2 CPUFUNC(op_c0a0_0)(uae_u32 opcode) /* AND */
23012: {
23013: uae_u32 srcreg = (opcode & 7);
23014: uae_u32 dstreg = (opcode >> 9) & 7;
23015: OpcodeFamily = 2; CurrentInstrCycles = 16;
23016: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
23017: { uae_s32 src = get_long(srca);
23018: m68k_areg (regs, srcreg) = srca;
23019: { uae_s32 dst = m68k_dreg(regs, dstreg);
23020: src &= dst;
23021: CLEAR_CZNV;
23022: SET_ZFLG (((uae_s32)(src)) == 0);
23023: SET_NFLG (((uae_s32)(src)) < 0);
23024: m68k_dreg(regs, dstreg) = (src);
23025: }}}}m68k_incpc(2);
23026: return 16;
23027: }
23028: unsigned long REGPARAM2 CPUFUNC(op_c0a8_0)(uae_u32 opcode) /* AND */
23029: {
23030: uae_u32 srcreg = (opcode & 7);
23031: uae_u32 dstreg = (opcode >> 9) & 7;
23032: OpcodeFamily = 2; CurrentInstrCycles = 18;
23033: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
23034: { uae_s32 src = get_long(srca);
23035: { uae_s32 dst = m68k_dreg(regs, dstreg);
23036: src &= dst;
23037: CLEAR_CZNV;
23038: SET_ZFLG (((uae_s32)(src)) == 0);
23039: SET_NFLG (((uae_s32)(src)) < 0);
23040: m68k_dreg(regs, dstreg) = (src);
23041: }}}}m68k_incpc(4);
23042: return 18;
23043: }
23044: unsigned long REGPARAM2 CPUFUNC(op_c0b0_0)(uae_u32 opcode) /* AND */
23045: {
23046: uae_u32 srcreg = (opcode & 7);
23047: uae_u32 dstreg = (opcode >> 9) & 7;
23048: OpcodeFamily = 2; CurrentInstrCycles = 20;
23049: {{m68k_incpc(2);
23050: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
23051: BusCyclePenalty += 2;
23052: { uae_s32 src = get_long(srca);
23053: { uae_s32 dst = m68k_dreg(regs, dstreg);
23054: src &= dst;
23055: CLEAR_CZNV;
23056: SET_ZFLG (((uae_s32)(src)) == 0);
23057: SET_NFLG (((uae_s32)(src)) < 0);
23058: m68k_dreg(regs, dstreg) = (src);
23059: }}}}}return 20;
23060: }
23061: unsigned long REGPARAM2 CPUFUNC(op_c0b8_0)(uae_u32 opcode) /* AND */
23062: {
23063: uae_u32 dstreg = (opcode >> 9) & 7;
23064: OpcodeFamily = 2; CurrentInstrCycles = 18;
23065: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
23066: { uae_s32 src = get_long(srca);
23067: { uae_s32 dst = m68k_dreg(regs, dstreg);
23068: src &= dst;
23069: CLEAR_CZNV;
23070: SET_ZFLG (((uae_s32)(src)) == 0);
23071: SET_NFLG (((uae_s32)(src)) < 0);
23072: m68k_dreg(regs, dstreg) = (src);
23073: }}}}m68k_incpc(4);
23074: return 18;
23075: }
23076: unsigned long REGPARAM2 CPUFUNC(op_c0b9_0)(uae_u32 opcode) /* AND */
23077: {
23078: uae_u32 dstreg = (opcode >> 9) & 7;
23079: OpcodeFamily = 2; CurrentInstrCycles = 22;
23080: {{ uaecptr srca = get_ilong(2);
23081: { uae_s32 src = get_long(srca);
23082: { uae_s32 dst = m68k_dreg(regs, dstreg);
23083: src &= dst;
23084: CLEAR_CZNV;
23085: SET_ZFLG (((uae_s32)(src)) == 0);
23086: SET_NFLG (((uae_s32)(src)) < 0);
23087: m68k_dreg(regs, dstreg) = (src);
23088: }}}}m68k_incpc(6);
23089: return 22;
23090: }
23091: unsigned long REGPARAM2 CPUFUNC(op_c0ba_0)(uae_u32 opcode) /* AND */
23092: {
23093: uae_u32 dstreg = (opcode >> 9) & 7;
23094: OpcodeFamily = 2; CurrentInstrCycles = 18;
23095: {{ uaecptr srca = m68k_getpc () + 2;
23096: srca += (uae_s32)(uae_s16)get_iword(2);
23097: { uae_s32 src = get_long(srca);
23098: { uae_s32 dst = m68k_dreg(regs, dstreg);
23099: src &= dst;
23100: CLEAR_CZNV;
23101: SET_ZFLG (((uae_s32)(src)) == 0);
23102: SET_NFLG (((uae_s32)(src)) < 0);
23103: m68k_dreg(regs, dstreg) = (src);
23104: }}}}m68k_incpc(4);
23105: return 18;
23106: }
23107: unsigned long REGPARAM2 CPUFUNC(op_c0bb_0)(uae_u32 opcode) /* AND */
23108: {
23109: uae_u32 dstreg = (opcode >> 9) & 7;
23110: OpcodeFamily = 2; CurrentInstrCycles = 20;
23111: {{m68k_incpc(2);
23112: { uaecptr tmppc = m68k_getpc();
23113: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
23114: BusCyclePenalty += 2;
23115: { uae_s32 src = get_long(srca);
23116: { uae_s32 dst = m68k_dreg(regs, dstreg);
23117: src &= dst;
23118: CLEAR_CZNV;
23119: SET_ZFLG (((uae_s32)(src)) == 0);
23120: SET_NFLG (((uae_s32)(src)) < 0);
23121: m68k_dreg(regs, dstreg) = (src);
23122: }}}}}return 20;
23123: }
23124: unsigned long REGPARAM2 CPUFUNC(op_c0bc_0)(uae_u32 opcode) /* AND */
23125: {
23126: uae_u32 dstreg = (opcode >> 9) & 7;
23127: OpcodeFamily = 2; CurrentInstrCycles = 16;
23128: {{ uae_s32 src = get_ilong(2);
23129: { uae_s32 dst = m68k_dreg(regs, dstreg);
23130: src &= dst;
23131: CLEAR_CZNV;
23132: SET_ZFLG (((uae_s32)(src)) == 0);
23133: SET_NFLG (((uae_s32)(src)) < 0);
23134: m68k_dreg(regs, dstreg) = (src);
23135: }}}m68k_incpc(6);
23136: return 16;
23137: }
23138: unsigned long REGPARAM2 CPUFUNC(op_c0c0_0)(uae_u32 opcode) /* MULU */
23139: {
23140: uae_u32 srcreg = (opcode & 7);
23141: uae_u32 dstreg = (opcode >> 9) & 7;
23142: unsigned int retcycles = 0;
23143: OpcodeFamily = 62; CurrentInstrCycles = 38;
23144: {{ uae_s16 src = m68k_dreg(regs, srcreg);
23145: { uae_s16 dst = m68k_dreg(regs, dstreg);
23146: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23147: CLEAR_CZNV;
23148: SET_ZFLG (((uae_s32)(newv)) == 0);
23149: SET_NFLG (((uae_s32)(newv)) < 0);
23150: m68k_dreg(regs, dstreg) = (newv);
23151: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23152: }}}}m68k_incpc(2);
23153: return (38+retcycles*2);
23154: }
23155: unsigned long REGPARAM2 CPUFUNC(op_c0d0_0)(uae_u32 opcode) /* MULU */
23156: {
23157: uae_u32 srcreg = (opcode & 7);
23158: uae_u32 dstreg = (opcode >> 9) & 7;
23159: unsigned int retcycles = 0;
23160: OpcodeFamily = 62; CurrentInstrCycles = 42;
23161: {{ uaecptr srca = m68k_areg(regs, srcreg);
23162: { uae_s16 src = get_word(srca);
23163: { uae_s16 dst = m68k_dreg(regs, dstreg);
23164: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23165: CLEAR_CZNV;
23166: SET_ZFLG (((uae_s32)(newv)) == 0);
23167: SET_NFLG (((uae_s32)(newv)) < 0);
23168: m68k_dreg(regs, dstreg) = (newv);
23169: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23170: }}}}}m68k_incpc(2);
23171: return (42+retcycles*2);
23172: }
23173: unsigned long REGPARAM2 CPUFUNC(op_c0d8_0)(uae_u32 opcode) /* MULU */
23174: {
23175: uae_u32 srcreg = (opcode & 7);
23176: uae_u32 dstreg = (opcode >> 9) & 7;
23177: unsigned int retcycles = 0;
23178: OpcodeFamily = 62; CurrentInstrCycles = 42;
23179: {{ uaecptr srca = m68k_areg(regs, srcreg);
23180: { uae_s16 src = get_word(srca);
23181: m68k_areg(regs, srcreg) += 2;
23182: { uae_s16 dst = m68k_dreg(regs, dstreg);
23183: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23184: CLEAR_CZNV;
23185: SET_ZFLG (((uae_s32)(newv)) == 0);
23186: SET_NFLG (((uae_s32)(newv)) < 0);
23187: m68k_dreg(regs, dstreg) = (newv);
23188: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23189: }}}}}m68k_incpc(2);
23190: return (42+retcycles*2);
23191: }
23192: unsigned long REGPARAM2 CPUFUNC(op_c0e0_0)(uae_u32 opcode) /* MULU */
23193: {
23194: uae_u32 srcreg = (opcode & 7);
23195: uae_u32 dstreg = (opcode >> 9) & 7;
23196: unsigned int retcycles = 0;
23197: OpcodeFamily = 62; CurrentInstrCycles = 44;
23198: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
23199: { uae_s16 src = get_word(srca);
23200: m68k_areg (regs, srcreg) = srca;
23201: { uae_s16 dst = m68k_dreg(regs, dstreg);
23202: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23203: CLEAR_CZNV;
23204: SET_ZFLG (((uae_s32)(newv)) == 0);
23205: SET_NFLG (((uae_s32)(newv)) < 0);
23206: m68k_dreg(regs, dstreg) = (newv);
23207: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23208: }}}}}m68k_incpc(2);
23209: return (44+retcycles*2);
23210: }
23211: unsigned long REGPARAM2 CPUFUNC(op_c0e8_0)(uae_u32 opcode) /* MULU */
23212: {
23213: uae_u32 srcreg = (opcode & 7);
23214: uae_u32 dstreg = (opcode >> 9) & 7;
23215: unsigned int retcycles = 0;
23216: OpcodeFamily = 62; CurrentInstrCycles = 46;
23217: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
23218: { uae_s16 src = get_word(srca);
23219: { uae_s16 dst = m68k_dreg(regs, dstreg);
23220: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23221: CLEAR_CZNV;
23222: SET_ZFLG (((uae_s32)(newv)) == 0);
23223: SET_NFLG (((uae_s32)(newv)) < 0);
23224: m68k_dreg(regs, dstreg) = (newv);
23225: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23226: }}}}}m68k_incpc(4);
23227: return (46+retcycles*2);
23228: }
23229: unsigned long REGPARAM2 CPUFUNC(op_c0f0_0)(uae_u32 opcode) /* MULU */
23230: {
23231: uae_u32 srcreg = (opcode & 7);
23232: uae_u32 dstreg = (opcode >> 9) & 7;
23233: unsigned int retcycles = 0;
23234: OpcodeFamily = 62; CurrentInstrCycles = 48;
23235: {{m68k_incpc(2);
23236: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
23237: BusCyclePenalty += 2;
23238: { uae_s16 src = get_word(srca);
23239: { uae_s16 dst = m68k_dreg(regs, dstreg);
23240: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23241: CLEAR_CZNV;
23242: SET_ZFLG (((uae_s32)(newv)) == 0);
23243: SET_NFLG (((uae_s32)(newv)) < 0);
23244: m68k_dreg(regs, dstreg) = (newv);
23245: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23246: }}}}}} return (48+retcycles*2);
23247: }
23248: unsigned long REGPARAM2 CPUFUNC(op_c0f8_0)(uae_u32 opcode) /* MULU */
23249: {
23250: uae_u32 dstreg = (opcode >> 9) & 7;
23251: unsigned int retcycles = 0;
23252: OpcodeFamily = 62; CurrentInstrCycles = 46;
23253: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
23254: { uae_s16 src = get_word(srca);
23255: { uae_s16 dst = m68k_dreg(regs, dstreg);
23256: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23257: CLEAR_CZNV;
23258: SET_ZFLG (((uae_s32)(newv)) == 0);
23259: SET_NFLG (((uae_s32)(newv)) < 0);
23260: m68k_dreg(regs, dstreg) = (newv);
23261: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23262: }}}}}m68k_incpc(4);
23263: return (46+retcycles*2);
23264: }
23265: unsigned long REGPARAM2 CPUFUNC(op_c0f9_0)(uae_u32 opcode) /* MULU */
23266: {
23267: uae_u32 dstreg = (opcode >> 9) & 7;
23268: unsigned int retcycles = 0;
23269: OpcodeFamily = 62; CurrentInstrCycles = 50;
23270: {{ uaecptr srca = get_ilong(2);
23271: { uae_s16 src = get_word(srca);
23272: { uae_s16 dst = m68k_dreg(regs, dstreg);
23273: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23274: CLEAR_CZNV;
23275: SET_ZFLG (((uae_s32)(newv)) == 0);
23276: SET_NFLG (((uae_s32)(newv)) < 0);
23277: m68k_dreg(regs, dstreg) = (newv);
23278: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23279: }}}}}m68k_incpc(6);
23280: return (50+retcycles*2);
23281: }
23282: unsigned long REGPARAM2 CPUFUNC(op_c0fa_0)(uae_u32 opcode) /* MULU */
23283: {
23284: uae_u32 dstreg = (opcode >> 9) & 7;
23285: unsigned int retcycles = 0;
23286: OpcodeFamily = 62; CurrentInstrCycles = 46;
23287: {{ uaecptr srca = m68k_getpc () + 2;
23288: srca += (uae_s32)(uae_s16)get_iword(2);
23289: { uae_s16 src = get_word(srca);
23290: { uae_s16 dst = m68k_dreg(regs, dstreg);
23291: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23292: CLEAR_CZNV;
23293: SET_ZFLG (((uae_s32)(newv)) == 0);
23294: SET_NFLG (((uae_s32)(newv)) < 0);
23295: m68k_dreg(regs, dstreg) = (newv);
23296: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23297: }}}}}m68k_incpc(4);
23298: return (46+retcycles*2);
23299: }
23300: unsigned long REGPARAM2 CPUFUNC(op_c0fb_0)(uae_u32 opcode) /* MULU */
23301: {
23302: uae_u32 dstreg = (opcode >> 9) & 7;
23303: unsigned int retcycles = 0;
23304: OpcodeFamily = 62; CurrentInstrCycles = 48;
23305: {{m68k_incpc(2);
23306: { uaecptr tmppc = m68k_getpc();
23307: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
23308: BusCyclePenalty += 2;
23309: { uae_s16 src = get_word(srca);
23310: { uae_s16 dst = m68k_dreg(regs, dstreg);
23311: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23312: CLEAR_CZNV;
23313: SET_ZFLG (((uae_s32)(newv)) == 0);
23314: SET_NFLG (((uae_s32)(newv)) < 0);
23315: m68k_dreg(regs, dstreg) = (newv);
23316: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23317: }}}}}} return (48+retcycles*2);
23318: }
23319: unsigned long REGPARAM2 CPUFUNC(op_c0fc_0)(uae_u32 opcode) /* MULU */
23320: {
23321: uae_u32 dstreg = (opcode >> 9) & 7;
23322: unsigned int retcycles = 0;
23323: OpcodeFamily = 62; CurrentInstrCycles = 42;
23324: {{ uae_s16 src = get_iword(2);
23325: { uae_s16 dst = m68k_dreg(regs, dstreg);
23326: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
23327: CLEAR_CZNV;
23328: SET_ZFLG (((uae_s32)(newv)) == 0);
23329: SET_NFLG (((uae_s32)(newv)) < 0);
23330: m68k_dreg(regs, dstreg) = (newv);
23331: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
23332: }}}}m68k_incpc(4);
23333: return (42+retcycles*2);
23334: }
23335: unsigned long REGPARAM2 CPUFUNC(op_c100_0)(uae_u32 opcode) /* ABCD */
23336: {
23337: uae_u32 srcreg = (opcode & 7);
23338: uae_u32 dstreg = (opcode >> 9) & 7;
23339: OpcodeFamily = 14; CurrentInstrCycles = 6;
23340: {{ uae_s8 src = m68k_dreg(regs, srcreg);
23341: { uae_s8 dst = m68k_dreg(regs, dstreg);
23342: { uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);
23343: uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
23344: uae_u16 newv, tmp_newv;
23345: int cflg;
23346: newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; }
23347: cflg = (newv & 0x3F0) > 0x90;
23348: if (cflg) newv += 0x60;
23349: SET_CFLG (cflg);
23350: COPY_CARRY;
23351: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
23352: SET_NFLG (((uae_s8)(newv)) < 0);
23353: SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
23354: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
23355: }}}}m68k_incpc(2);
23356: return 6;
23357: }
23358: unsigned long REGPARAM2 CPUFUNC(op_c108_0)(uae_u32 opcode) /* ABCD */
23359: {
23360: uae_u32 srcreg = (opcode & 7);
23361: uae_u32 dstreg = (opcode >> 9) & 7;
23362: OpcodeFamily = 14; CurrentInstrCycles = 18;
23363: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
23364: { uae_s8 src = get_byte(srca);
23365: m68k_areg (regs, srcreg) = srca;
23366: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
23367: { uae_s8 dst = get_byte(dsta);
23368: m68k_areg (regs, dstreg) = dsta;
23369: { uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);
23370: uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
23371: uae_u16 newv, tmp_newv;
23372: int cflg;
23373: newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; }
23374: cflg = (newv & 0x3F0) > 0x90;
23375: if (cflg) newv += 0x60;
23376: SET_CFLG (cflg);
23377: COPY_CARRY;
23378: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
23379: SET_NFLG (((uae_s8)(newv)) < 0);
23380: SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
23381: put_byte(dsta,newv);
23382: }}}}}}m68k_incpc(2);
23383: return 18;
23384: }
23385: unsigned long REGPARAM2 CPUFUNC(op_c110_0)(uae_u32 opcode) /* AND */
23386: {
23387: uae_u32 srcreg = ((opcode >> 9) & 7);
23388: uae_u32 dstreg = opcode & 7;
23389: OpcodeFamily = 2; CurrentInstrCycles = 12;
23390: {{ uae_s8 src = m68k_dreg(regs, srcreg);
23391: { uaecptr dsta = m68k_areg(regs, dstreg);
23392: { uae_s8 dst = get_byte(dsta);
23393: src &= dst;
23394: CLEAR_CZNV;
23395: SET_ZFLG (((uae_s8)(src)) == 0);
23396: SET_NFLG (((uae_s8)(src)) < 0);
23397: put_byte(dsta,src);
23398: }}}}m68k_incpc(2);
23399: return 12;
23400: }
23401: unsigned long REGPARAM2 CPUFUNC(op_c118_0)(uae_u32 opcode) /* AND */
23402: {
23403: uae_u32 srcreg = ((opcode >> 9) & 7);
23404: uae_u32 dstreg = opcode & 7;
23405: OpcodeFamily = 2; CurrentInstrCycles = 12;
23406: {{ uae_s8 src = m68k_dreg(regs, srcreg);
23407: { uaecptr dsta = m68k_areg(regs, dstreg);
23408: { uae_s8 dst = get_byte(dsta);
23409: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
23410: src &= dst;
23411: CLEAR_CZNV;
23412: SET_ZFLG (((uae_s8)(src)) == 0);
23413: SET_NFLG (((uae_s8)(src)) < 0);
23414: put_byte(dsta,src);
23415: }}}}m68k_incpc(2);
23416: return 12;
23417: }
23418: unsigned long REGPARAM2 CPUFUNC(op_c120_0)(uae_u32 opcode) /* AND */
23419: {
23420: uae_u32 srcreg = ((opcode >> 9) & 7);
23421: uae_u32 dstreg = opcode & 7;
23422: OpcodeFamily = 2; CurrentInstrCycles = 14;
23423: {{ uae_s8 src = m68k_dreg(regs, srcreg);
23424: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
23425: { uae_s8 dst = get_byte(dsta);
23426: m68k_areg (regs, dstreg) = dsta;
23427: src &= dst;
23428: CLEAR_CZNV;
23429: SET_ZFLG (((uae_s8)(src)) == 0);
23430: SET_NFLG (((uae_s8)(src)) < 0);
23431: put_byte(dsta,src);
23432: }}}}m68k_incpc(2);
23433: return 14;
23434: }
23435: unsigned long REGPARAM2 CPUFUNC(op_c128_0)(uae_u32 opcode) /* AND */
23436: {
23437: uae_u32 srcreg = ((opcode >> 9) & 7);
23438: uae_u32 dstreg = opcode & 7;
23439: OpcodeFamily = 2; CurrentInstrCycles = 16;
23440: {{ uae_s8 src = m68k_dreg(regs, srcreg);
23441: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
23442: { uae_s8 dst = get_byte(dsta);
23443: src &= dst;
23444: CLEAR_CZNV;
23445: SET_ZFLG (((uae_s8)(src)) == 0);
23446: SET_NFLG (((uae_s8)(src)) < 0);
23447: put_byte(dsta,src);
23448: }}}}m68k_incpc(4);
23449: return 16;
23450: }
23451: unsigned long REGPARAM2 CPUFUNC(op_c130_0)(uae_u32 opcode) /* AND */
23452: {
23453: uae_u32 srcreg = ((opcode >> 9) & 7);
23454: uae_u32 dstreg = opcode & 7;
23455: OpcodeFamily = 2; CurrentInstrCycles = 18;
23456: {{ uae_s8 src = m68k_dreg(regs, srcreg);
23457: {m68k_incpc(2);
23458: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
23459: BusCyclePenalty += 2;
23460: { uae_s8 dst = get_byte(dsta);
23461: src &= dst;
23462: CLEAR_CZNV;
23463: SET_ZFLG (((uae_s8)(src)) == 0);
23464: SET_NFLG (((uae_s8)(src)) < 0);
23465: put_byte(dsta,src);
23466: }}}}}return 18;
23467: }
23468: unsigned long REGPARAM2 CPUFUNC(op_c138_0)(uae_u32 opcode) /* AND */
23469: {
23470: uae_u32 srcreg = ((opcode >> 9) & 7);
23471: OpcodeFamily = 2; CurrentInstrCycles = 16;
23472: {{ uae_s8 src = m68k_dreg(regs, srcreg);
23473: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
23474: { uae_s8 dst = get_byte(dsta);
23475: src &= dst;
23476: CLEAR_CZNV;
23477: SET_ZFLG (((uae_s8)(src)) == 0);
23478: SET_NFLG (((uae_s8)(src)) < 0);
23479: put_byte(dsta,src);
23480: }}}}m68k_incpc(4);
23481: return 16;
23482: }
23483: unsigned long REGPARAM2 CPUFUNC(op_c139_0)(uae_u32 opcode) /* AND */
23484: {
23485: uae_u32 srcreg = ((opcode >> 9) & 7);
23486: OpcodeFamily = 2; CurrentInstrCycles = 20;
23487: {{ uae_s8 src = m68k_dreg(regs, srcreg);
23488: { uaecptr dsta = get_ilong(2);
23489: { uae_s8 dst = get_byte(dsta);
23490: src &= dst;
23491: CLEAR_CZNV;
23492: SET_ZFLG (((uae_s8)(src)) == 0);
23493: SET_NFLG (((uae_s8)(src)) < 0);
23494: put_byte(dsta,src);
23495: }}}}m68k_incpc(6);
23496: return 20;
23497: }
23498: unsigned long REGPARAM2 CPUFUNC(op_c140_0)(uae_u32 opcode) /* EXG */
23499: {
23500: uae_u32 srcreg = ((opcode >> 9) & 7);
23501: uae_u32 dstreg = opcode & 7;
23502: OpcodeFamily = 35; CurrentInstrCycles = 6;
23503: {{ uae_s32 src = m68k_dreg(regs, srcreg);
23504: { uae_s32 dst = m68k_dreg(regs, dstreg);
23505: m68k_dreg(regs, srcreg) = (dst);
23506: m68k_dreg(regs, dstreg) = (src);
23507: }}}m68k_incpc(2);
23508: return 6;
23509: }
23510: unsigned long REGPARAM2 CPUFUNC(op_c148_0)(uae_u32 opcode) /* EXG */
23511: {
23512: uae_u32 srcreg = ((opcode >> 9) & 7);
23513: uae_u32 dstreg = opcode & 7;
23514: OpcodeFamily = 35; CurrentInstrCycles = 6;
23515: {{ uae_s32 src = m68k_areg(regs, srcreg);
23516: { uae_s32 dst = m68k_areg(regs, dstreg);
23517: m68k_areg(regs, srcreg) = (dst);
23518: m68k_areg(regs, dstreg) = (src);
23519: }}}m68k_incpc(2);
23520: return 6;
23521: }
23522: unsigned long REGPARAM2 CPUFUNC(op_c150_0)(uae_u32 opcode) /* AND */
23523: {
23524: uae_u32 srcreg = ((opcode >> 9) & 7);
23525: uae_u32 dstreg = opcode & 7;
23526: OpcodeFamily = 2; CurrentInstrCycles = 12;
23527: {{ uae_s16 src = m68k_dreg(regs, srcreg);
23528: { uaecptr dsta = m68k_areg(regs, dstreg);
23529: { uae_s16 dst = get_word(dsta);
23530: src &= dst;
23531: CLEAR_CZNV;
23532: SET_ZFLG (((uae_s16)(src)) == 0);
23533: SET_NFLG (((uae_s16)(src)) < 0);
23534: put_word(dsta,src);
23535: }}}}m68k_incpc(2);
23536: return 12;
23537: }
23538: unsigned long REGPARAM2 CPUFUNC(op_c158_0)(uae_u32 opcode) /* AND */
23539: {
23540: uae_u32 srcreg = ((opcode >> 9) & 7);
23541: uae_u32 dstreg = opcode & 7;
23542: OpcodeFamily = 2; CurrentInstrCycles = 12;
23543: {{ uae_s16 src = m68k_dreg(regs, srcreg);
23544: { uaecptr dsta = m68k_areg(regs, dstreg);
23545: { uae_s16 dst = get_word(dsta);
23546: m68k_areg(regs, dstreg) += 2;
23547: src &= dst;
23548: CLEAR_CZNV;
23549: SET_ZFLG (((uae_s16)(src)) == 0);
23550: SET_NFLG (((uae_s16)(src)) < 0);
23551: put_word(dsta,src);
23552: }}}}m68k_incpc(2);
23553: return 12;
23554: }
23555: unsigned long REGPARAM2 CPUFUNC(op_c160_0)(uae_u32 opcode) /* AND */
23556: {
23557: uae_u32 srcreg = ((opcode >> 9) & 7);
23558: uae_u32 dstreg = opcode & 7;
23559: OpcodeFamily = 2; CurrentInstrCycles = 14;
23560: {{ uae_s16 src = m68k_dreg(regs, srcreg);
23561: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
23562: { uae_s16 dst = get_word(dsta);
23563: m68k_areg (regs, dstreg) = dsta;
23564: src &= dst;
23565: CLEAR_CZNV;
23566: SET_ZFLG (((uae_s16)(src)) == 0);
23567: SET_NFLG (((uae_s16)(src)) < 0);
23568: put_word(dsta,src);
23569: }}}}m68k_incpc(2);
23570: return 14;
23571: }
23572: unsigned long REGPARAM2 CPUFUNC(op_c168_0)(uae_u32 opcode) /* AND */
23573: {
23574: uae_u32 srcreg = ((opcode >> 9) & 7);
23575: uae_u32 dstreg = opcode & 7;
23576: OpcodeFamily = 2; CurrentInstrCycles = 16;
23577: {{ uae_s16 src = m68k_dreg(regs, srcreg);
23578: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
23579: { uae_s16 dst = get_word(dsta);
23580: src &= dst;
23581: CLEAR_CZNV;
23582: SET_ZFLG (((uae_s16)(src)) == 0);
23583: SET_NFLG (((uae_s16)(src)) < 0);
23584: put_word(dsta,src);
23585: }}}}m68k_incpc(4);
23586: return 16;
23587: }
23588: unsigned long REGPARAM2 CPUFUNC(op_c170_0)(uae_u32 opcode) /* AND */
23589: {
23590: uae_u32 srcreg = ((opcode >> 9) & 7);
23591: uae_u32 dstreg = opcode & 7;
23592: OpcodeFamily = 2; CurrentInstrCycles = 18;
23593: {{ uae_s16 src = m68k_dreg(regs, srcreg);
23594: {m68k_incpc(2);
23595: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
23596: BusCyclePenalty += 2;
23597: { uae_s16 dst = get_word(dsta);
23598: src &= dst;
23599: CLEAR_CZNV;
23600: SET_ZFLG (((uae_s16)(src)) == 0);
23601: SET_NFLG (((uae_s16)(src)) < 0);
23602: put_word(dsta,src);
23603: }}}}}return 18;
23604: }
23605: unsigned long REGPARAM2 CPUFUNC(op_c178_0)(uae_u32 opcode) /* AND */
23606: {
23607: uae_u32 srcreg = ((opcode >> 9) & 7);
23608: OpcodeFamily = 2; CurrentInstrCycles = 16;
23609: {{ uae_s16 src = m68k_dreg(regs, srcreg);
23610: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
23611: { uae_s16 dst = get_word(dsta);
23612: src &= dst;
23613: CLEAR_CZNV;
23614: SET_ZFLG (((uae_s16)(src)) == 0);
23615: SET_NFLG (((uae_s16)(src)) < 0);
23616: put_word(dsta,src);
23617: }}}}m68k_incpc(4);
23618: return 16;
23619: }
23620: unsigned long REGPARAM2 CPUFUNC(op_c179_0)(uae_u32 opcode) /* AND */
23621: {
23622: uae_u32 srcreg = ((opcode >> 9) & 7);
23623: OpcodeFamily = 2; CurrentInstrCycles = 20;
23624: {{ uae_s16 src = m68k_dreg(regs, srcreg);
23625: { uaecptr dsta = get_ilong(2);
23626: { uae_s16 dst = get_word(dsta);
23627: src &= dst;
23628: CLEAR_CZNV;
23629: SET_ZFLG (((uae_s16)(src)) == 0);
23630: SET_NFLG (((uae_s16)(src)) < 0);
23631: put_word(dsta,src);
23632: }}}}m68k_incpc(6);
23633: return 20;
23634: }
23635: unsigned long REGPARAM2 CPUFUNC(op_c188_0)(uae_u32 opcode) /* EXG */
23636: {
23637: uae_u32 srcreg = ((opcode >> 9) & 7);
23638: uae_u32 dstreg = opcode & 7;
23639: OpcodeFamily = 35; CurrentInstrCycles = 6;
23640: {{ uae_s32 src = m68k_dreg(regs, srcreg);
23641: { uae_s32 dst = m68k_areg(regs, dstreg);
23642: m68k_dreg(regs, srcreg) = (dst);
23643: m68k_areg(regs, dstreg) = (src);
23644: }}}m68k_incpc(2);
23645: return 6;
23646: }
23647: unsigned long REGPARAM2 CPUFUNC(op_c190_0)(uae_u32 opcode) /* AND */
23648: {
23649: uae_u32 srcreg = ((opcode >> 9) & 7);
23650: uae_u32 dstreg = opcode & 7;
23651: OpcodeFamily = 2; CurrentInstrCycles = 20;
23652: {{ uae_s32 src = m68k_dreg(regs, srcreg);
23653: { uaecptr dsta = m68k_areg(regs, dstreg);
23654: { uae_s32 dst = get_long(dsta);
23655: src &= dst;
23656: CLEAR_CZNV;
23657: SET_ZFLG (((uae_s32)(src)) == 0);
23658: SET_NFLG (((uae_s32)(src)) < 0);
23659: put_long(dsta,src);
23660: }}}}m68k_incpc(2);
23661: return 20;
23662: }
23663: unsigned long REGPARAM2 CPUFUNC(op_c198_0)(uae_u32 opcode) /* AND */
23664: {
23665: uae_u32 srcreg = ((opcode >> 9) & 7);
23666: uae_u32 dstreg = opcode & 7;
23667: OpcodeFamily = 2; CurrentInstrCycles = 20;
23668: {{ uae_s32 src = m68k_dreg(regs, srcreg);
23669: { uaecptr dsta = m68k_areg(regs, dstreg);
23670: { uae_s32 dst = get_long(dsta);
23671: m68k_areg(regs, dstreg) += 4;
23672: src &= dst;
23673: CLEAR_CZNV;
23674: SET_ZFLG (((uae_s32)(src)) == 0);
23675: SET_NFLG (((uae_s32)(src)) < 0);
23676: put_long(dsta,src);
23677: }}}}m68k_incpc(2);
23678: return 20;
23679: }
23680: unsigned long REGPARAM2 CPUFUNC(op_c1a0_0)(uae_u32 opcode) /* AND */
23681: {
23682: uae_u32 srcreg = ((opcode >> 9) & 7);
23683: uae_u32 dstreg = opcode & 7;
23684: OpcodeFamily = 2; CurrentInstrCycles = 22;
23685: {{ uae_s32 src = m68k_dreg(regs, srcreg);
23686: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
23687: { uae_s32 dst = get_long(dsta);
23688: m68k_areg (regs, dstreg) = dsta;
23689: src &= dst;
23690: CLEAR_CZNV;
23691: SET_ZFLG (((uae_s32)(src)) == 0);
23692: SET_NFLG (((uae_s32)(src)) < 0);
23693: put_long(dsta,src);
23694: }}}}m68k_incpc(2);
23695: return 22;
23696: }
23697: unsigned long REGPARAM2 CPUFUNC(op_c1a8_0)(uae_u32 opcode) /* AND */
23698: {
23699: uae_u32 srcreg = ((opcode >> 9) & 7);
23700: uae_u32 dstreg = opcode & 7;
23701: OpcodeFamily = 2; CurrentInstrCycles = 24;
23702: {{ uae_s32 src = m68k_dreg(regs, srcreg);
23703: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
23704: { uae_s32 dst = get_long(dsta);
23705: src &= dst;
23706: CLEAR_CZNV;
23707: SET_ZFLG (((uae_s32)(src)) == 0);
23708: SET_NFLG (((uae_s32)(src)) < 0);
23709: put_long(dsta,src);
23710: }}}}m68k_incpc(4);
23711: return 24;
23712: }
23713: unsigned long REGPARAM2 CPUFUNC(op_c1b0_0)(uae_u32 opcode) /* AND */
23714: {
23715: uae_u32 srcreg = ((opcode >> 9) & 7);
23716: uae_u32 dstreg = opcode & 7;
23717: OpcodeFamily = 2; CurrentInstrCycles = 26;
23718: {{ uae_s32 src = m68k_dreg(regs, srcreg);
23719: {m68k_incpc(2);
23720: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
23721: BusCyclePenalty += 2;
23722: { uae_s32 dst = get_long(dsta);
23723: src &= dst;
23724: CLEAR_CZNV;
23725: SET_ZFLG (((uae_s32)(src)) == 0);
23726: SET_NFLG (((uae_s32)(src)) < 0);
23727: put_long(dsta,src);
23728: }}}}}return 26;
23729: }
23730: unsigned long REGPARAM2 CPUFUNC(op_c1b8_0)(uae_u32 opcode) /* AND */
23731: {
23732: uae_u32 srcreg = ((opcode >> 9) & 7);
23733: OpcodeFamily = 2; CurrentInstrCycles = 24;
23734: {{ uae_s32 src = m68k_dreg(regs, srcreg);
23735: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
23736: { uae_s32 dst = get_long(dsta);
23737: src &= dst;
23738: CLEAR_CZNV;
23739: SET_ZFLG (((uae_s32)(src)) == 0);
23740: SET_NFLG (((uae_s32)(src)) < 0);
23741: put_long(dsta,src);
23742: }}}}m68k_incpc(4);
23743: return 24;
23744: }
23745: unsigned long REGPARAM2 CPUFUNC(op_c1b9_0)(uae_u32 opcode) /* AND */
23746: {
23747: uae_u32 srcreg = ((opcode >> 9) & 7);
23748: OpcodeFamily = 2; CurrentInstrCycles = 28;
23749: {{ uae_s32 src = m68k_dreg(regs, srcreg);
23750: { uaecptr dsta = get_ilong(2);
23751: { uae_s32 dst = get_long(dsta);
23752: src &= dst;
23753: CLEAR_CZNV;
23754: SET_ZFLG (((uae_s32)(src)) == 0);
23755: SET_NFLG (((uae_s32)(src)) < 0);
23756: put_long(dsta,src);
23757: }}}}m68k_incpc(6);
23758: return 28;
23759: }
23760: unsigned long REGPARAM2 CPUFUNC(op_c1c0_0)(uae_u32 opcode) /* MULS */
23761: {
23762: uae_u32 srcreg = (opcode & 7);
23763: uae_u32 dstreg = (opcode >> 9) & 7;
23764: unsigned int retcycles = 0;
23765: OpcodeFamily = 63; CurrentInstrCycles = 38;
23766: {{ uae_s16 src = m68k_dreg(regs, srcreg);
23767: { uae_s16 dst = m68k_dreg(regs, dstreg);
23768: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23769: uae_u32 src2;
23770: CLEAR_CZNV;
23771: SET_ZFLG (((uae_s32)(newv)) == 0);
23772: SET_NFLG (((uae_s32)(newv)) < 0);
23773: m68k_dreg(regs, dstreg) = (newv);
23774: src2 = ((uae_u32)src) << 1;
23775: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23776: }}}}m68k_incpc(2);
23777: return (38+retcycles*2);
23778: }
23779: unsigned long REGPARAM2 CPUFUNC(op_c1d0_0)(uae_u32 opcode) /* MULS */
23780: {
23781: uae_u32 srcreg = (opcode & 7);
23782: uae_u32 dstreg = (opcode >> 9) & 7;
23783: unsigned int retcycles = 0;
23784: OpcodeFamily = 63; CurrentInstrCycles = 42;
23785: {{ uaecptr srca = m68k_areg(regs, srcreg);
23786: { uae_s16 src = get_word(srca);
23787: { uae_s16 dst = m68k_dreg(regs, dstreg);
23788: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23789: uae_u32 src2;
23790: CLEAR_CZNV;
23791: SET_ZFLG (((uae_s32)(newv)) == 0);
23792: SET_NFLG (((uae_s32)(newv)) < 0);
23793: m68k_dreg(regs, dstreg) = (newv);
23794: src2 = ((uae_u32)src) << 1;
23795: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23796: }}}}}m68k_incpc(2);
23797: return (42+retcycles*2);
23798: }
23799: unsigned long REGPARAM2 CPUFUNC(op_c1d8_0)(uae_u32 opcode) /* MULS */
23800: {
23801: uae_u32 srcreg = (opcode & 7);
23802: uae_u32 dstreg = (opcode >> 9) & 7;
23803: unsigned int retcycles = 0;
23804: OpcodeFamily = 63; CurrentInstrCycles = 42;
23805: {{ uaecptr srca = m68k_areg(regs, srcreg);
23806: { uae_s16 src = get_word(srca);
23807: m68k_areg(regs, srcreg) += 2;
23808: { uae_s16 dst = m68k_dreg(regs, dstreg);
23809: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23810: uae_u32 src2;
23811: CLEAR_CZNV;
23812: SET_ZFLG (((uae_s32)(newv)) == 0);
23813: SET_NFLG (((uae_s32)(newv)) < 0);
23814: m68k_dreg(regs, dstreg) = (newv);
23815: src2 = ((uae_u32)src) << 1;
23816: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23817: }}}}}m68k_incpc(2);
23818: return (42+retcycles*2);
23819: }
23820: unsigned long REGPARAM2 CPUFUNC(op_c1e0_0)(uae_u32 opcode) /* MULS */
23821: {
23822: uae_u32 srcreg = (opcode & 7);
23823: uae_u32 dstreg = (opcode >> 9) & 7;
23824: unsigned int retcycles = 0;
23825: OpcodeFamily = 63; CurrentInstrCycles = 44;
23826: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
23827: { uae_s16 src = get_word(srca);
23828: m68k_areg (regs, srcreg) = srca;
23829: { uae_s16 dst = m68k_dreg(regs, dstreg);
23830: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23831: uae_u32 src2;
23832: CLEAR_CZNV;
23833: SET_ZFLG (((uae_s32)(newv)) == 0);
23834: SET_NFLG (((uae_s32)(newv)) < 0);
23835: m68k_dreg(regs, dstreg) = (newv);
23836: src2 = ((uae_u32)src) << 1;
23837: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23838: }}}}}m68k_incpc(2);
23839: return (44+retcycles*2);
23840: }
23841: unsigned long REGPARAM2 CPUFUNC(op_c1e8_0)(uae_u32 opcode) /* MULS */
23842: {
23843: uae_u32 srcreg = (opcode & 7);
23844: uae_u32 dstreg = (opcode >> 9) & 7;
23845: unsigned int retcycles = 0;
23846: OpcodeFamily = 63; CurrentInstrCycles = 46;
23847: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
23848: { uae_s16 src = get_word(srca);
23849: { uae_s16 dst = m68k_dreg(regs, dstreg);
23850: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23851: uae_u32 src2;
23852: CLEAR_CZNV;
23853: SET_ZFLG (((uae_s32)(newv)) == 0);
23854: SET_NFLG (((uae_s32)(newv)) < 0);
23855: m68k_dreg(regs, dstreg) = (newv);
23856: src2 = ((uae_u32)src) << 1;
23857: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23858: }}}}}m68k_incpc(4);
23859: return (46+retcycles*2);
23860: }
23861: unsigned long REGPARAM2 CPUFUNC(op_c1f0_0)(uae_u32 opcode) /* MULS */
23862: {
23863: uae_u32 srcreg = (opcode & 7);
23864: uae_u32 dstreg = (opcode >> 9) & 7;
23865: unsigned int retcycles = 0;
23866: OpcodeFamily = 63; CurrentInstrCycles = 48;
23867: {{m68k_incpc(2);
23868: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
23869: BusCyclePenalty += 2;
23870: { uae_s16 src = get_word(srca);
23871: { uae_s16 dst = m68k_dreg(regs, dstreg);
23872: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23873: uae_u32 src2;
23874: CLEAR_CZNV;
23875: SET_ZFLG (((uae_s32)(newv)) == 0);
23876: SET_NFLG (((uae_s32)(newv)) < 0);
23877: m68k_dreg(regs, dstreg) = (newv);
23878: src2 = ((uae_u32)src) << 1;
23879: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23880: }}}}}} return (48+retcycles*2);
23881: }
23882: unsigned long REGPARAM2 CPUFUNC(op_c1f8_0)(uae_u32 opcode) /* MULS */
23883: {
23884: uae_u32 dstreg = (opcode >> 9) & 7;
23885: unsigned int retcycles = 0;
23886: OpcodeFamily = 63; CurrentInstrCycles = 46;
23887: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
23888: { uae_s16 src = get_word(srca);
23889: { uae_s16 dst = m68k_dreg(regs, dstreg);
23890: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23891: uae_u32 src2;
23892: CLEAR_CZNV;
23893: SET_ZFLG (((uae_s32)(newv)) == 0);
23894: SET_NFLG (((uae_s32)(newv)) < 0);
23895: m68k_dreg(regs, dstreg) = (newv);
23896: src2 = ((uae_u32)src) << 1;
23897: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23898: }}}}}m68k_incpc(4);
23899: return (46+retcycles*2);
23900: }
23901: unsigned long REGPARAM2 CPUFUNC(op_c1f9_0)(uae_u32 opcode) /* MULS */
23902: {
23903: uae_u32 dstreg = (opcode >> 9) & 7;
23904: unsigned int retcycles = 0;
23905: OpcodeFamily = 63; CurrentInstrCycles = 50;
23906: {{ uaecptr srca = get_ilong(2);
23907: { uae_s16 src = get_word(srca);
23908: { uae_s16 dst = m68k_dreg(regs, dstreg);
23909: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23910: uae_u32 src2;
23911: CLEAR_CZNV;
23912: SET_ZFLG (((uae_s32)(newv)) == 0);
23913: SET_NFLG (((uae_s32)(newv)) < 0);
23914: m68k_dreg(regs, dstreg) = (newv);
23915: src2 = ((uae_u32)src) << 1;
23916: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23917: }}}}}m68k_incpc(6);
23918: return (50+retcycles*2);
23919: }
23920: unsigned long REGPARAM2 CPUFUNC(op_c1fa_0)(uae_u32 opcode) /* MULS */
23921: {
23922: uae_u32 dstreg = (opcode >> 9) & 7;
23923: unsigned int retcycles = 0;
23924: OpcodeFamily = 63; CurrentInstrCycles = 46;
23925: {{ uaecptr srca = m68k_getpc () + 2;
23926: srca += (uae_s32)(uae_s16)get_iword(2);
23927: { uae_s16 src = get_word(srca);
23928: { uae_s16 dst = m68k_dreg(regs, dstreg);
23929: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23930: uae_u32 src2;
23931: CLEAR_CZNV;
23932: SET_ZFLG (((uae_s32)(newv)) == 0);
23933: SET_NFLG (((uae_s32)(newv)) < 0);
23934: m68k_dreg(regs, dstreg) = (newv);
23935: src2 = ((uae_u32)src) << 1;
23936: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23937: }}}}}m68k_incpc(4);
23938: return (46+retcycles*2);
23939: }
23940: unsigned long REGPARAM2 CPUFUNC(op_c1fb_0)(uae_u32 opcode) /* MULS */
23941: {
23942: uae_u32 dstreg = (opcode >> 9) & 7;
23943: unsigned int retcycles = 0;
23944: OpcodeFamily = 63; CurrentInstrCycles = 48;
23945: {{m68k_incpc(2);
23946: { uaecptr tmppc = m68k_getpc();
23947: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
23948: BusCyclePenalty += 2;
23949: { uae_s16 src = get_word(srca);
23950: { uae_s16 dst = m68k_dreg(regs, dstreg);
23951: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23952: uae_u32 src2;
23953: CLEAR_CZNV;
23954: SET_ZFLG (((uae_s32)(newv)) == 0);
23955: SET_NFLG (((uae_s32)(newv)) < 0);
23956: m68k_dreg(regs, dstreg) = (newv);
23957: src2 = ((uae_u32)src) << 1;
23958: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23959: }}}}}} return (48+retcycles*2);
23960: }
23961: unsigned long REGPARAM2 CPUFUNC(op_c1fc_0)(uae_u32 opcode) /* MULS */
23962: {
23963: uae_u32 dstreg = (opcode >> 9) & 7;
23964: unsigned int retcycles = 0;
23965: OpcodeFamily = 63; CurrentInstrCycles = 42;
23966: {{ uae_s16 src = get_iword(2);
23967: { uae_s16 dst = m68k_dreg(regs, dstreg);
23968: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
23969: uae_u32 src2;
23970: CLEAR_CZNV;
23971: SET_ZFLG (((uae_s32)(newv)) == 0);
23972: SET_NFLG (((uae_s32)(newv)) < 0);
23973: m68k_dreg(regs, dstreg) = (newv);
23974: src2 = ((uae_u32)src) << 1;
23975: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
23976: }}}}m68k_incpc(4);
23977: return (42+retcycles*2);
23978: }
23979: unsigned long REGPARAM2 CPUFUNC(op_d000_0)(uae_u32 opcode) /* ADD */
23980: {
23981: uae_u32 srcreg = (opcode & 7);
23982: uae_u32 dstreg = (opcode >> 9) & 7;
23983: OpcodeFamily = 11; CurrentInstrCycles = 4;
23984: {{ uae_s8 src = m68k_dreg(regs, srcreg);
23985: { uae_s8 dst = m68k_dreg(regs, dstreg);
23986: { refill_prefetch (m68k_getpc(), 2);
23987: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
23988: { int flgs = ((uae_s8)(src)) < 0;
23989: int flgo = ((uae_s8)(dst)) < 0;
23990: int flgn = ((uae_s8)(newv)) < 0;
23991: SET_ZFLG (((uae_s8)(newv)) == 0);
23992: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
23993: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
23994: COPY_CARRY;
23995: SET_NFLG (flgn != 0);
23996: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
23997: }}}}}}m68k_incpc(2);
23998: return 4;
23999: }
24000: unsigned long REGPARAM2 CPUFUNC(op_d010_0)(uae_u32 opcode) /* ADD */
24001: {
24002: uae_u32 srcreg = (opcode & 7);
24003: uae_u32 dstreg = (opcode >> 9) & 7;
24004: OpcodeFamily = 11; CurrentInstrCycles = 8;
24005: {{ uaecptr srca = m68k_areg(regs, srcreg);
24006: { uae_s8 src = get_byte(srca);
24007: { uae_s8 dst = m68k_dreg(regs, dstreg);
24008: { refill_prefetch (m68k_getpc(), 2);
24009: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24010: { int flgs = ((uae_s8)(src)) < 0;
24011: int flgo = ((uae_s8)(dst)) < 0;
24012: int flgn = ((uae_s8)(newv)) < 0;
24013: SET_ZFLG (((uae_s8)(newv)) == 0);
24014: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24015: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24016: COPY_CARRY;
24017: SET_NFLG (flgn != 0);
24018: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24019: }}}}}}}m68k_incpc(2);
24020: return 8;
24021: }
24022: unsigned long REGPARAM2 CPUFUNC(op_d018_0)(uae_u32 opcode) /* ADD */
24023: {
24024: uae_u32 srcreg = (opcode & 7);
24025: uae_u32 dstreg = (opcode >> 9) & 7;
24026: OpcodeFamily = 11; CurrentInstrCycles = 8;
24027: {{ uaecptr srca = m68k_areg(regs, srcreg);
24028: { uae_s8 src = get_byte(srca);
24029: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
24030: { uae_s8 dst = m68k_dreg(regs, dstreg);
24031: { refill_prefetch (m68k_getpc(), 2);
24032: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24033: { int flgs = ((uae_s8)(src)) < 0;
24034: int flgo = ((uae_s8)(dst)) < 0;
24035: int flgn = ((uae_s8)(newv)) < 0;
24036: SET_ZFLG (((uae_s8)(newv)) == 0);
24037: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24038: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24039: COPY_CARRY;
24040: SET_NFLG (flgn != 0);
24041: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24042: }}}}}}}m68k_incpc(2);
24043: return 8;
24044: }
24045: unsigned long REGPARAM2 CPUFUNC(op_d020_0)(uae_u32 opcode) /* ADD */
24046: {
24047: uae_u32 srcreg = (opcode & 7);
24048: uae_u32 dstreg = (opcode >> 9) & 7;
24049: OpcodeFamily = 11; CurrentInstrCycles = 10;
24050: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
24051: { uae_s8 src = get_byte(srca);
24052: m68k_areg (regs, srcreg) = srca;
24053: { uae_s8 dst = m68k_dreg(regs, dstreg);
24054: { refill_prefetch (m68k_getpc(), 2);
24055: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24056: { int flgs = ((uae_s8)(src)) < 0;
24057: int flgo = ((uae_s8)(dst)) < 0;
24058: int flgn = ((uae_s8)(newv)) < 0;
24059: SET_ZFLG (((uae_s8)(newv)) == 0);
24060: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24061: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24062: COPY_CARRY;
24063: SET_NFLG (flgn != 0);
24064: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24065: }}}}}}}m68k_incpc(2);
24066: return 10;
24067: }
24068: unsigned long REGPARAM2 CPUFUNC(op_d028_0)(uae_u32 opcode) /* ADD */
24069: {
24070: uae_u32 srcreg = (opcode & 7);
24071: uae_u32 dstreg = (opcode >> 9) & 7;
24072: OpcodeFamily = 11; CurrentInstrCycles = 12;
24073: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
24074: { uae_s8 src = get_byte(srca);
24075: { uae_s8 dst = m68k_dreg(regs, dstreg);
24076: { refill_prefetch (m68k_getpc(), 2);
24077: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24078: { int flgs = ((uae_s8)(src)) < 0;
24079: int flgo = ((uae_s8)(dst)) < 0;
24080: int flgn = ((uae_s8)(newv)) < 0;
24081: SET_ZFLG (((uae_s8)(newv)) == 0);
24082: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24083: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24084: COPY_CARRY;
24085: SET_NFLG (flgn != 0);
24086: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24087: }}}}}}}m68k_incpc(4);
24088: return 12;
24089: }
24090: unsigned long REGPARAM2 CPUFUNC(op_d030_0)(uae_u32 opcode) /* ADD */
24091: {
24092: uae_u32 srcreg = (opcode & 7);
24093: uae_u32 dstreg = (opcode >> 9) & 7;
24094: OpcodeFamily = 11; CurrentInstrCycles = 14;
24095: {{m68k_incpc(2);
24096: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
24097: BusCyclePenalty += 2;
24098: { uae_s8 src = get_byte(srca);
24099: { uae_s8 dst = m68k_dreg(regs, dstreg);
24100: { refill_prefetch (m68k_getpc(), 2);
24101: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24102: { int flgs = ((uae_s8)(src)) < 0;
24103: int flgo = ((uae_s8)(dst)) < 0;
24104: int flgn = ((uae_s8)(newv)) < 0;
24105: SET_ZFLG (((uae_s8)(newv)) == 0);
24106: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24107: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24108: COPY_CARRY;
24109: SET_NFLG (flgn != 0);
24110: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24111: }}}}}}}}return 14;
24112: }
24113: unsigned long REGPARAM2 CPUFUNC(op_d038_0)(uae_u32 opcode) /* ADD */
24114: {
24115: uae_u32 dstreg = (opcode >> 9) & 7;
24116: OpcodeFamily = 11; CurrentInstrCycles = 12;
24117: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
24118: { uae_s8 src = get_byte(srca);
24119: { uae_s8 dst = m68k_dreg(regs, dstreg);
24120: { refill_prefetch (m68k_getpc(), 2);
24121: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24122: { int flgs = ((uae_s8)(src)) < 0;
24123: int flgo = ((uae_s8)(dst)) < 0;
24124: int flgn = ((uae_s8)(newv)) < 0;
24125: SET_ZFLG (((uae_s8)(newv)) == 0);
24126: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24127: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24128: COPY_CARRY;
24129: SET_NFLG (flgn != 0);
24130: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24131: }}}}}}}m68k_incpc(4);
24132: return 12;
24133: }
24134: unsigned long REGPARAM2 CPUFUNC(op_d039_0)(uae_u32 opcode) /* ADD */
24135: {
24136: uae_u32 dstreg = (opcode >> 9) & 7;
24137: OpcodeFamily = 11; CurrentInstrCycles = 16;
24138: {{ uaecptr srca = get_ilong(2);
24139: { uae_s8 src = get_byte(srca);
24140: { uae_s8 dst = m68k_dreg(regs, dstreg);
24141: { refill_prefetch (m68k_getpc(), 2);
24142: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24143: { int flgs = ((uae_s8)(src)) < 0;
24144: int flgo = ((uae_s8)(dst)) < 0;
24145: int flgn = ((uae_s8)(newv)) < 0;
24146: SET_ZFLG (((uae_s8)(newv)) == 0);
24147: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24148: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24149: COPY_CARRY;
24150: SET_NFLG (flgn != 0);
24151: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24152: }}}}}}}m68k_incpc(6);
24153: return 16;
24154: }
24155: unsigned long REGPARAM2 CPUFUNC(op_d03a_0)(uae_u32 opcode) /* ADD */
24156: {
24157: uae_u32 dstreg = (opcode >> 9) & 7;
24158: OpcodeFamily = 11; CurrentInstrCycles = 12;
24159: {{ uaecptr srca = m68k_getpc () + 2;
24160: srca += (uae_s32)(uae_s16)get_iword(2);
24161: { uae_s8 src = get_byte(srca);
24162: { uae_s8 dst = m68k_dreg(regs, dstreg);
24163: { refill_prefetch (m68k_getpc(), 2);
24164: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24165: { int flgs = ((uae_s8)(src)) < 0;
24166: int flgo = ((uae_s8)(dst)) < 0;
24167: int flgn = ((uae_s8)(newv)) < 0;
24168: SET_ZFLG (((uae_s8)(newv)) == 0);
24169: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24170: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24171: COPY_CARRY;
24172: SET_NFLG (flgn != 0);
24173: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24174: }}}}}}}m68k_incpc(4);
24175: return 12;
24176: }
24177: unsigned long REGPARAM2 CPUFUNC(op_d03b_0)(uae_u32 opcode) /* ADD */
24178: {
24179: uae_u32 dstreg = (opcode >> 9) & 7;
24180: OpcodeFamily = 11; CurrentInstrCycles = 14;
24181: {{m68k_incpc(2);
24182: { uaecptr tmppc = m68k_getpc();
24183: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
24184: BusCyclePenalty += 2;
24185: { uae_s8 src = get_byte(srca);
24186: { uae_s8 dst = m68k_dreg(regs, dstreg);
24187: { refill_prefetch (m68k_getpc(), 2);
24188: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24189: { int flgs = ((uae_s8)(src)) < 0;
24190: int flgo = ((uae_s8)(dst)) < 0;
24191: int flgn = ((uae_s8)(newv)) < 0;
24192: SET_ZFLG (((uae_s8)(newv)) == 0);
24193: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24194: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24195: COPY_CARRY;
24196: SET_NFLG (flgn != 0);
24197: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24198: }}}}}}}}return 14;
24199: }
24200: unsigned long REGPARAM2 CPUFUNC(op_d03c_0)(uae_u32 opcode) /* ADD */
24201: {
24202: uae_u32 dstreg = (opcode >> 9) & 7;
24203: OpcodeFamily = 11; CurrentInstrCycles = 8;
24204: {{ uae_s8 src = get_ibyte(2);
24205: { uae_s8 dst = m68k_dreg(regs, dstreg);
24206: { refill_prefetch (m68k_getpc(), 2);
24207: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24208: { int flgs = ((uae_s8)(src)) < 0;
24209: int flgo = ((uae_s8)(dst)) < 0;
24210: int flgn = ((uae_s8)(newv)) < 0;
24211: SET_ZFLG (((uae_s8)(newv)) == 0);
24212: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24213: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24214: COPY_CARRY;
24215: SET_NFLG (flgn != 0);
24216: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24217: }}}}}}m68k_incpc(4);
24218: return 8;
24219: }
24220: unsigned long REGPARAM2 CPUFUNC(op_d040_0)(uae_u32 opcode) /* ADD */
24221: {
24222: uae_u32 srcreg = (opcode & 7);
24223: uae_u32 dstreg = (opcode >> 9) & 7;
24224: OpcodeFamily = 11; CurrentInstrCycles = 4;
24225: {{ uae_s16 src = m68k_dreg(regs, srcreg);
24226: { uae_s16 dst = m68k_dreg(regs, dstreg);
24227: { refill_prefetch (m68k_getpc(), 2);
24228: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24229: { int flgs = ((uae_s16)(src)) < 0;
24230: int flgo = ((uae_s16)(dst)) < 0;
24231: int flgn = ((uae_s16)(newv)) < 0;
24232: SET_ZFLG (((uae_s16)(newv)) == 0);
24233: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24234: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24235: COPY_CARRY;
24236: SET_NFLG (flgn != 0);
24237: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24238: }}}}}}m68k_incpc(2);
24239: return 4;
24240: }
24241: unsigned long REGPARAM2 CPUFUNC(op_d048_0)(uae_u32 opcode) /* ADD */
24242: {
24243: uae_u32 srcreg = (opcode & 7);
24244: uae_u32 dstreg = (opcode >> 9) & 7;
24245: OpcodeFamily = 11; CurrentInstrCycles = 4;
24246: {{ uae_s16 src = m68k_areg(regs, srcreg);
24247: { uae_s16 dst = m68k_dreg(regs, dstreg);
24248: { refill_prefetch (m68k_getpc(), 2);
24249: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24250: { int flgs = ((uae_s16)(src)) < 0;
24251: int flgo = ((uae_s16)(dst)) < 0;
24252: int flgn = ((uae_s16)(newv)) < 0;
24253: SET_ZFLG (((uae_s16)(newv)) == 0);
24254: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24255: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24256: COPY_CARRY;
24257: SET_NFLG (flgn != 0);
24258: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24259: }}}}}}m68k_incpc(2);
24260: return 4;
24261: }
24262: unsigned long REGPARAM2 CPUFUNC(op_d050_0)(uae_u32 opcode) /* ADD */
24263: {
24264: uae_u32 srcreg = (opcode & 7);
24265: uae_u32 dstreg = (opcode >> 9) & 7;
24266: OpcodeFamily = 11; CurrentInstrCycles = 8;
24267: {{ uaecptr srca = m68k_areg(regs, srcreg);
24268: { uae_s16 src = get_word(srca);
24269: { uae_s16 dst = m68k_dreg(regs, dstreg);
24270: { refill_prefetch (m68k_getpc(), 2);
24271: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24272: { int flgs = ((uae_s16)(src)) < 0;
24273: int flgo = ((uae_s16)(dst)) < 0;
24274: int flgn = ((uae_s16)(newv)) < 0;
24275: SET_ZFLG (((uae_s16)(newv)) == 0);
24276: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24277: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24278: COPY_CARRY;
24279: SET_NFLG (flgn != 0);
24280: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24281: }}}}}}}m68k_incpc(2);
24282: return 8;
24283: }
24284: unsigned long REGPARAM2 CPUFUNC(op_d058_0)(uae_u32 opcode) /* ADD */
24285: {
24286: uae_u32 srcreg = (opcode & 7);
24287: uae_u32 dstreg = (opcode >> 9) & 7;
24288: OpcodeFamily = 11; CurrentInstrCycles = 8;
24289: {{ uaecptr srca = m68k_areg(regs, srcreg);
24290: { uae_s16 src = get_word(srca);
24291: m68k_areg(regs, srcreg) += 2;
24292: { uae_s16 dst = m68k_dreg(regs, dstreg);
24293: { refill_prefetch (m68k_getpc(), 2);
24294: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24295: { int flgs = ((uae_s16)(src)) < 0;
24296: int flgo = ((uae_s16)(dst)) < 0;
24297: int flgn = ((uae_s16)(newv)) < 0;
24298: SET_ZFLG (((uae_s16)(newv)) == 0);
24299: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24300: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24301: COPY_CARRY;
24302: SET_NFLG (flgn != 0);
24303: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24304: }}}}}}}m68k_incpc(2);
24305: return 8;
24306: }
24307: unsigned long REGPARAM2 CPUFUNC(op_d060_0)(uae_u32 opcode) /* ADD */
24308: {
24309: uae_u32 srcreg = (opcode & 7);
24310: uae_u32 dstreg = (opcode >> 9) & 7;
24311: OpcodeFamily = 11; CurrentInstrCycles = 10;
24312: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
24313: { uae_s16 src = get_word(srca);
24314: m68k_areg (regs, srcreg) = srca;
24315: { uae_s16 dst = m68k_dreg(regs, dstreg);
24316: { refill_prefetch (m68k_getpc(), 2);
24317: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24318: { int flgs = ((uae_s16)(src)) < 0;
24319: int flgo = ((uae_s16)(dst)) < 0;
24320: int flgn = ((uae_s16)(newv)) < 0;
24321: SET_ZFLG (((uae_s16)(newv)) == 0);
24322: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24323: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24324: COPY_CARRY;
24325: SET_NFLG (flgn != 0);
24326: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24327: }}}}}}}m68k_incpc(2);
24328: return 10;
24329: }
24330: unsigned long REGPARAM2 CPUFUNC(op_d068_0)(uae_u32 opcode) /* ADD */
24331: {
24332: uae_u32 srcreg = (opcode & 7);
24333: uae_u32 dstreg = (opcode >> 9) & 7;
24334: OpcodeFamily = 11; CurrentInstrCycles = 12;
24335: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
24336: { uae_s16 src = get_word(srca);
24337: { uae_s16 dst = m68k_dreg(regs, dstreg);
24338: { refill_prefetch (m68k_getpc(), 2);
24339: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24340: { int flgs = ((uae_s16)(src)) < 0;
24341: int flgo = ((uae_s16)(dst)) < 0;
24342: int flgn = ((uae_s16)(newv)) < 0;
24343: SET_ZFLG (((uae_s16)(newv)) == 0);
24344: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24345: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24346: COPY_CARRY;
24347: SET_NFLG (flgn != 0);
24348: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24349: }}}}}}}m68k_incpc(4);
24350: return 12;
24351: }
24352: unsigned long REGPARAM2 CPUFUNC(op_d070_0)(uae_u32 opcode) /* ADD */
24353: {
24354: uae_u32 srcreg = (opcode & 7);
24355: uae_u32 dstreg = (opcode >> 9) & 7;
24356: OpcodeFamily = 11; CurrentInstrCycles = 14;
24357: {{m68k_incpc(2);
24358: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
24359: BusCyclePenalty += 2;
24360: { uae_s16 src = get_word(srca);
24361: { uae_s16 dst = m68k_dreg(regs, dstreg);
24362: { refill_prefetch (m68k_getpc(), 2);
24363: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24364: { int flgs = ((uae_s16)(src)) < 0;
24365: int flgo = ((uae_s16)(dst)) < 0;
24366: int flgn = ((uae_s16)(newv)) < 0;
24367: SET_ZFLG (((uae_s16)(newv)) == 0);
24368: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24369: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24370: COPY_CARRY;
24371: SET_NFLG (flgn != 0);
24372: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24373: }}}}}}}}return 14;
24374: }
24375: unsigned long REGPARAM2 CPUFUNC(op_d078_0)(uae_u32 opcode) /* ADD */
24376: {
24377: uae_u32 dstreg = (opcode >> 9) & 7;
24378: OpcodeFamily = 11; CurrentInstrCycles = 12;
24379: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
24380: { uae_s16 src = get_word(srca);
24381: { uae_s16 dst = m68k_dreg(regs, dstreg);
24382: { refill_prefetch (m68k_getpc(), 2);
24383: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24384: { int flgs = ((uae_s16)(src)) < 0;
24385: int flgo = ((uae_s16)(dst)) < 0;
24386: int flgn = ((uae_s16)(newv)) < 0;
24387: SET_ZFLG (((uae_s16)(newv)) == 0);
24388: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24389: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24390: COPY_CARRY;
24391: SET_NFLG (flgn != 0);
24392: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24393: }}}}}}}m68k_incpc(4);
24394: return 12;
24395: }
24396: unsigned long REGPARAM2 CPUFUNC(op_d079_0)(uae_u32 opcode) /* ADD */
24397: {
24398: uae_u32 dstreg = (opcode >> 9) & 7;
24399: OpcodeFamily = 11; CurrentInstrCycles = 16;
24400: {{ uaecptr srca = get_ilong(2);
24401: { uae_s16 src = get_word(srca);
24402: { uae_s16 dst = m68k_dreg(regs, dstreg);
24403: { refill_prefetch (m68k_getpc(), 2);
24404: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24405: { int flgs = ((uae_s16)(src)) < 0;
24406: int flgo = ((uae_s16)(dst)) < 0;
24407: int flgn = ((uae_s16)(newv)) < 0;
24408: SET_ZFLG (((uae_s16)(newv)) == 0);
24409: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24410: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24411: COPY_CARRY;
24412: SET_NFLG (flgn != 0);
24413: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24414: }}}}}}}m68k_incpc(6);
24415: return 16;
24416: }
24417: unsigned long REGPARAM2 CPUFUNC(op_d07a_0)(uae_u32 opcode) /* ADD */
24418: {
24419: uae_u32 dstreg = (opcode >> 9) & 7;
24420: OpcodeFamily = 11; CurrentInstrCycles = 12;
24421: {{ uaecptr srca = m68k_getpc () + 2;
24422: srca += (uae_s32)(uae_s16)get_iword(2);
24423: { uae_s16 src = get_word(srca);
24424: { uae_s16 dst = m68k_dreg(regs, dstreg);
24425: { refill_prefetch (m68k_getpc(), 2);
24426: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24427: { int flgs = ((uae_s16)(src)) < 0;
24428: int flgo = ((uae_s16)(dst)) < 0;
24429: int flgn = ((uae_s16)(newv)) < 0;
24430: SET_ZFLG (((uae_s16)(newv)) == 0);
24431: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24432: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24433: COPY_CARRY;
24434: SET_NFLG (flgn != 0);
24435: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24436: }}}}}}}m68k_incpc(4);
24437: return 12;
24438: }
24439: unsigned long REGPARAM2 CPUFUNC(op_d07b_0)(uae_u32 opcode) /* ADD */
24440: {
24441: uae_u32 dstreg = (opcode >> 9) & 7;
24442: OpcodeFamily = 11; CurrentInstrCycles = 14;
24443: {{m68k_incpc(2);
24444: { uaecptr tmppc = m68k_getpc();
24445: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
24446: BusCyclePenalty += 2;
24447: { uae_s16 src = get_word(srca);
24448: { uae_s16 dst = m68k_dreg(regs, dstreg);
24449: { refill_prefetch (m68k_getpc(), 2);
24450: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24451: { int flgs = ((uae_s16)(src)) < 0;
24452: int flgo = ((uae_s16)(dst)) < 0;
24453: int flgn = ((uae_s16)(newv)) < 0;
24454: SET_ZFLG (((uae_s16)(newv)) == 0);
24455: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24456: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24457: COPY_CARRY;
24458: SET_NFLG (flgn != 0);
24459: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24460: }}}}}}}}return 14;
24461: }
24462: unsigned long REGPARAM2 CPUFUNC(op_d07c_0)(uae_u32 opcode) /* ADD */
24463: {
24464: uae_u32 dstreg = (opcode >> 9) & 7;
24465: OpcodeFamily = 11; CurrentInstrCycles = 8;
24466: {{ uae_s16 src = get_iword(2);
24467: { uae_s16 dst = m68k_dreg(regs, dstreg);
24468: { refill_prefetch (m68k_getpc(), 2);
24469: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
24470: { int flgs = ((uae_s16)(src)) < 0;
24471: int flgo = ((uae_s16)(dst)) < 0;
24472: int flgn = ((uae_s16)(newv)) < 0;
24473: SET_ZFLG (((uae_s16)(newv)) == 0);
24474: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24475: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
24476: COPY_CARRY;
24477: SET_NFLG (flgn != 0);
24478: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
24479: }}}}}}m68k_incpc(4);
24480: return 8;
24481: }
24482: unsigned long REGPARAM2 CPUFUNC(op_d080_0)(uae_u32 opcode) /* ADD */
24483: {
24484: uae_u32 srcreg = (opcode & 7);
24485: uae_u32 dstreg = (opcode >> 9) & 7;
24486: OpcodeFamily = 11; CurrentInstrCycles = 8;
24487: {{ uae_s32 src = m68k_dreg(regs, srcreg);
24488: { uae_s32 dst = m68k_dreg(regs, dstreg);
24489: { refill_prefetch (m68k_getpc(), 2);
24490: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24491: { int flgs = ((uae_s32)(src)) < 0;
24492: int flgo = ((uae_s32)(dst)) < 0;
24493: int flgn = ((uae_s32)(newv)) < 0;
24494: SET_ZFLG (((uae_s32)(newv)) == 0);
24495: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24496: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24497: COPY_CARRY;
24498: SET_NFLG (flgn != 0);
24499: m68k_dreg(regs, dstreg) = (newv);
24500: }}}}}}m68k_incpc(2);
24501: return 8;
24502: }
24503: unsigned long REGPARAM2 CPUFUNC(op_d088_0)(uae_u32 opcode) /* ADD */
24504: {
24505: uae_u32 srcreg = (opcode & 7);
24506: uae_u32 dstreg = (opcode >> 9) & 7;
24507: OpcodeFamily = 11; CurrentInstrCycles = 8;
24508: {{ uae_s32 src = m68k_areg(regs, srcreg);
24509: { uae_s32 dst = m68k_dreg(regs, dstreg);
24510: { refill_prefetch (m68k_getpc(), 2);
24511: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24512: { int flgs = ((uae_s32)(src)) < 0;
24513: int flgo = ((uae_s32)(dst)) < 0;
24514: int flgn = ((uae_s32)(newv)) < 0;
24515: SET_ZFLG (((uae_s32)(newv)) == 0);
24516: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24517: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24518: COPY_CARRY;
24519: SET_NFLG (flgn != 0);
24520: m68k_dreg(regs, dstreg) = (newv);
24521: }}}}}}m68k_incpc(2);
24522: return 8;
24523: }
24524: unsigned long REGPARAM2 CPUFUNC(op_d090_0)(uae_u32 opcode) /* ADD */
24525: {
24526: uae_u32 srcreg = (opcode & 7);
24527: uae_u32 dstreg = (opcode >> 9) & 7;
24528: OpcodeFamily = 11; CurrentInstrCycles = 14;
24529: {{ uaecptr srca = m68k_areg(regs, srcreg);
24530: { uae_s32 src = get_long(srca);
24531: { uae_s32 dst = m68k_dreg(regs, dstreg);
24532: { refill_prefetch (m68k_getpc(), 2);
24533: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24534: { int flgs = ((uae_s32)(src)) < 0;
24535: int flgo = ((uae_s32)(dst)) < 0;
24536: int flgn = ((uae_s32)(newv)) < 0;
24537: SET_ZFLG (((uae_s32)(newv)) == 0);
24538: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24539: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24540: COPY_CARRY;
24541: SET_NFLG (flgn != 0);
24542: m68k_dreg(regs, dstreg) = (newv);
24543: }}}}}}}m68k_incpc(2);
24544: return 14;
24545: }
24546: unsigned long REGPARAM2 CPUFUNC(op_d098_0)(uae_u32 opcode) /* ADD */
24547: {
24548: uae_u32 srcreg = (opcode & 7);
24549: uae_u32 dstreg = (opcode >> 9) & 7;
24550: OpcodeFamily = 11; CurrentInstrCycles = 14;
24551: {{ uaecptr srca = m68k_areg(regs, srcreg);
24552: { uae_s32 src = get_long(srca);
24553: m68k_areg(regs, srcreg) += 4;
24554: { uae_s32 dst = m68k_dreg(regs, dstreg);
24555: { refill_prefetch (m68k_getpc(), 2);
24556: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24557: { int flgs = ((uae_s32)(src)) < 0;
24558: int flgo = ((uae_s32)(dst)) < 0;
24559: int flgn = ((uae_s32)(newv)) < 0;
24560: SET_ZFLG (((uae_s32)(newv)) == 0);
24561: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24562: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24563: COPY_CARRY;
24564: SET_NFLG (flgn != 0);
24565: m68k_dreg(regs, dstreg) = (newv);
24566: }}}}}}}m68k_incpc(2);
24567: return 14;
24568: }
24569: unsigned long REGPARAM2 CPUFUNC(op_d0a0_0)(uae_u32 opcode) /* ADD */
24570: {
24571: uae_u32 srcreg = (opcode & 7);
24572: uae_u32 dstreg = (opcode >> 9) & 7;
24573: OpcodeFamily = 11; CurrentInstrCycles = 16;
24574: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
24575: { uae_s32 src = get_long(srca);
24576: m68k_areg (regs, srcreg) = srca;
24577: { uae_s32 dst = m68k_dreg(regs, dstreg);
24578: { refill_prefetch (m68k_getpc(), 2);
24579: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24580: { int flgs = ((uae_s32)(src)) < 0;
24581: int flgo = ((uae_s32)(dst)) < 0;
24582: int flgn = ((uae_s32)(newv)) < 0;
24583: SET_ZFLG (((uae_s32)(newv)) == 0);
24584: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24585: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24586: COPY_CARRY;
24587: SET_NFLG (flgn != 0);
24588: m68k_dreg(regs, dstreg) = (newv);
24589: }}}}}}}m68k_incpc(2);
24590: return 16;
24591: }
24592: unsigned long REGPARAM2 CPUFUNC(op_d0a8_0)(uae_u32 opcode) /* ADD */
24593: {
24594: uae_u32 srcreg = (opcode & 7);
24595: uae_u32 dstreg = (opcode >> 9) & 7;
24596: OpcodeFamily = 11; CurrentInstrCycles = 18;
24597: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
24598: { uae_s32 src = get_long(srca);
24599: { uae_s32 dst = m68k_dreg(regs, dstreg);
24600: { refill_prefetch (m68k_getpc(), 2);
24601: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24602: { int flgs = ((uae_s32)(src)) < 0;
24603: int flgo = ((uae_s32)(dst)) < 0;
24604: int flgn = ((uae_s32)(newv)) < 0;
24605: SET_ZFLG (((uae_s32)(newv)) == 0);
24606: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24607: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24608: COPY_CARRY;
24609: SET_NFLG (flgn != 0);
24610: m68k_dreg(regs, dstreg) = (newv);
24611: }}}}}}}m68k_incpc(4);
24612: return 18;
24613: }
24614: unsigned long REGPARAM2 CPUFUNC(op_d0b0_0)(uae_u32 opcode) /* ADD */
24615: {
24616: uae_u32 srcreg = (opcode & 7);
24617: uae_u32 dstreg = (opcode >> 9) & 7;
24618: OpcodeFamily = 11; CurrentInstrCycles = 20;
24619: {{m68k_incpc(2);
24620: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
24621: BusCyclePenalty += 2;
24622: { uae_s32 src = get_long(srca);
24623: { uae_s32 dst = m68k_dreg(regs, dstreg);
24624: { refill_prefetch (m68k_getpc(), 2);
24625: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24626: { int flgs = ((uae_s32)(src)) < 0;
24627: int flgo = ((uae_s32)(dst)) < 0;
24628: int flgn = ((uae_s32)(newv)) < 0;
24629: SET_ZFLG (((uae_s32)(newv)) == 0);
24630: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24631: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24632: COPY_CARRY;
24633: SET_NFLG (flgn != 0);
24634: m68k_dreg(regs, dstreg) = (newv);
24635: }}}}}}}}return 20;
24636: }
24637: unsigned long REGPARAM2 CPUFUNC(op_d0b8_0)(uae_u32 opcode) /* ADD */
24638: {
24639: uae_u32 dstreg = (opcode >> 9) & 7;
24640: OpcodeFamily = 11; CurrentInstrCycles = 18;
24641: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
24642: { uae_s32 src = get_long(srca);
24643: { uae_s32 dst = m68k_dreg(regs, dstreg);
24644: { refill_prefetch (m68k_getpc(), 2);
24645: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24646: { int flgs = ((uae_s32)(src)) < 0;
24647: int flgo = ((uae_s32)(dst)) < 0;
24648: int flgn = ((uae_s32)(newv)) < 0;
24649: SET_ZFLG (((uae_s32)(newv)) == 0);
24650: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24651: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24652: COPY_CARRY;
24653: SET_NFLG (flgn != 0);
24654: m68k_dreg(regs, dstreg) = (newv);
24655: }}}}}}}m68k_incpc(4);
24656: return 18;
24657: }
24658: unsigned long REGPARAM2 CPUFUNC(op_d0b9_0)(uae_u32 opcode) /* ADD */
24659: {
24660: uae_u32 dstreg = (opcode >> 9) & 7;
24661: OpcodeFamily = 11; CurrentInstrCycles = 22;
24662: {{ uaecptr srca = get_ilong(2);
24663: { uae_s32 src = get_long(srca);
24664: { uae_s32 dst = m68k_dreg(regs, dstreg);
24665: { refill_prefetch (m68k_getpc(), 2);
24666: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24667: { int flgs = ((uae_s32)(src)) < 0;
24668: int flgo = ((uae_s32)(dst)) < 0;
24669: int flgn = ((uae_s32)(newv)) < 0;
24670: SET_ZFLG (((uae_s32)(newv)) == 0);
24671: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24672: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24673: COPY_CARRY;
24674: SET_NFLG (flgn != 0);
24675: m68k_dreg(regs, dstreg) = (newv);
24676: }}}}}}}m68k_incpc(6);
24677: return 22;
24678: }
24679: unsigned long REGPARAM2 CPUFUNC(op_d0ba_0)(uae_u32 opcode) /* ADD */
24680: {
24681: uae_u32 dstreg = (opcode >> 9) & 7;
24682: OpcodeFamily = 11; CurrentInstrCycles = 18;
24683: {{ uaecptr srca = m68k_getpc () + 2;
24684: srca += (uae_s32)(uae_s16)get_iword(2);
24685: { uae_s32 src = get_long(srca);
24686: { uae_s32 dst = m68k_dreg(regs, dstreg);
24687: { refill_prefetch (m68k_getpc(), 2);
24688: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24689: { int flgs = ((uae_s32)(src)) < 0;
24690: int flgo = ((uae_s32)(dst)) < 0;
24691: int flgn = ((uae_s32)(newv)) < 0;
24692: SET_ZFLG (((uae_s32)(newv)) == 0);
24693: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24694: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24695: COPY_CARRY;
24696: SET_NFLG (flgn != 0);
24697: m68k_dreg(regs, dstreg) = (newv);
24698: }}}}}}}m68k_incpc(4);
24699: return 18;
24700: }
24701: unsigned long REGPARAM2 CPUFUNC(op_d0bb_0)(uae_u32 opcode) /* ADD */
24702: {
24703: uae_u32 dstreg = (opcode >> 9) & 7;
24704: OpcodeFamily = 11; CurrentInstrCycles = 20;
24705: {{m68k_incpc(2);
24706: { uaecptr tmppc = m68k_getpc();
24707: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
24708: BusCyclePenalty += 2;
24709: { uae_s32 src = get_long(srca);
24710: { uae_s32 dst = m68k_dreg(regs, dstreg);
24711: { refill_prefetch (m68k_getpc(), 2);
24712: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24713: { int flgs = ((uae_s32)(src)) < 0;
24714: int flgo = ((uae_s32)(dst)) < 0;
24715: int flgn = ((uae_s32)(newv)) < 0;
24716: SET_ZFLG (((uae_s32)(newv)) == 0);
24717: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24718: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24719: COPY_CARRY;
24720: SET_NFLG (flgn != 0);
24721: m68k_dreg(regs, dstreg) = (newv);
24722: }}}}}}}}return 20;
24723: }
24724: unsigned long REGPARAM2 CPUFUNC(op_d0bc_0)(uae_u32 opcode) /* ADD */
24725: {
24726: uae_u32 dstreg = (opcode >> 9) & 7;
24727: OpcodeFamily = 11; CurrentInstrCycles = 16;
24728: {{ uae_s32 src = get_ilong(2);
24729: { uae_s32 dst = m68k_dreg(regs, dstreg);
24730: { refill_prefetch (m68k_getpc(), 2);
24731: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
24732: { int flgs = ((uae_s32)(src)) < 0;
24733: int flgo = ((uae_s32)(dst)) < 0;
24734: int flgn = ((uae_s32)(newv)) < 0;
24735: SET_ZFLG (((uae_s32)(newv)) == 0);
24736: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24737: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
24738: COPY_CARRY;
24739: SET_NFLG (flgn != 0);
24740: m68k_dreg(regs, dstreg) = (newv);
24741: }}}}}}m68k_incpc(6);
24742: return 16;
24743: }
24744: unsigned long REGPARAM2 CPUFUNC(op_d0c0_0)(uae_u32 opcode) /* ADDA */
24745: {
24746: uae_u32 srcreg = (opcode & 7);
24747: uae_u32 dstreg = (opcode >> 9) & 7;
24748: OpcodeFamily = 12; CurrentInstrCycles = 8;
24749: {{ uae_s16 src = m68k_dreg(regs, srcreg);
24750: { uae_s32 dst = m68k_areg(regs, dstreg);
24751: { uae_u32 newv = dst + src;
24752: m68k_areg(regs, dstreg) = (newv);
24753: }}}}m68k_incpc(2);
24754: return 8;
24755: }
24756: unsigned long REGPARAM2 CPUFUNC(op_d0c8_0)(uae_u32 opcode) /* ADDA */
24757: {
24758: uae_u32 srcreg = (opcode & 7);
24759: uae_u32 dstreg = (opcode >> 9) & 7;
24760: OpcodeFamily = 12; CurrentInstrCycles = 8;
24761: {{ uae_s16 src = m68k_areg(regs, srcreg);
24762: { uae_s32 dst = m68k_areg(regs, dstreg);
24763: { uae_u32 newv = dst + src;
24764: m68k_areg(regs, dstreg) = (newv);
24765: }}}}m68k_incpc(2);
24766: return 8;
24767: }
24768: unsigned long REGPARAM2 CPUFUNC(op_d0d0_0)(uae_u32 opcode) /* ADDA */
24769: {
24770: uae_u32 srcreg = (opcode & 7);
24771: uae_u32 dstreg = (opcode >> 9) & 7;
24772: OpcodeFamily = 12; CurrentInstrCycles = 12;
24773: {{ uaecptr srca = m68k_areg(regs, srcreg);
24774: { uae_s16 src = get_word(srca);
24775: { uae_s32 dst = m68k_areg(regs, dstreg);
24776: { uae_u32 newv = dst + src;
24777: m68k_areg(regs, dstreg) = (newv);
24778: }}}}}m68k_incpc(2);
24779: return 12;
24780: }
24781: unsigned long REGPARAM2 CPUFUNC(op_d0d8_0)(uae_u32 opcode) /* ADDA */
24782: {
24783: uae_u32 srcreg = (opcode & 7);
24784: uae_u32 dstreg = (opcode >> 9) & 7;
24785: OpcodeFamily = 12; CurrentInstrCycles = 12;
24786: {{ uaecptr srca = m68k_areg(regs, srcreg);
24787: { uae_s16 src = get_word(srca);
24788: m68k_areg(regs, srcreg) += 2;
24789: { uae_s32 dst = m68k_areg(regs, dstreg);
24790: { uae_u32 newv = dst + src;
24791: m68k_areg(regs, dstreg) = (newv);
24792: }}}}}m68k_incpc(2);
24793: return 12;
24794: }
24795: unsigned long REGPARAM2 CPUFUNC(op_d0e0_0)(uae_u32 opcode) /* ADDA */
24796: {
24797: uae_u32 srcreg = (opcode & 7);
24798: uae_u32 dstreg = (opcode >> 9) & 7;
24799: OpcodeFamily = 12; CurrentInstrCycles = 14;
24800: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
24801: { uae_s16 src = get_word(srca);
24802: m68k_areg (regs, srcreg) = srca;
24803: { uae_s32 dst = m68k_areg(regs, dstreg);
24804: { uae_u32 newv = dst + src;
24805: m68k_areg(regs, dstreg) = (newv);
24806: }}}}}m68k_incpc(2);
24807: return 14;
24808: }
24809: unsigned long REGPARAM2 CPUFUNC(op_d0e8_0)(uae_u32 opcode) /* ADDA */
24810: {
24811: uae_u32 srcreg = (opcode & 7);
24812: uae_u32 dstreg = (opcode >> 9) & 7;
24813: OpcodeFamily = 12; CurrentInstrCycles = 16;
24814: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
24815: { uae_s16 src = get_word(srca);
24816: { uae_s32 dst = m68k_areg(regs, dstreg);
24817: { uae_u32 newv = dst + src;
24818: m68k_areg(regs, dstreg) = (newv);
24819: }}}}}m68k_incpc(4);
24820: return 16;
24821: }
24822: unsigned long REGPARAM2 CPUFUNC(op_d0f0_0)(uae_u32 opcode) /* ADDA */
24823: {
24824: uae_u32 srcreg = (opcode & 7);
24825: uae_u32 dstreg = (opcode >> 9) & 7;
24826: OpcodeFamily = 12; CurrentInstrCycles = 18;
24827: {{m68k_incpc(2);
24828: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
24829: BusCyclePenalty += 2;
24830: { uae_s16 src = get_word(srca);
24831: { uae_s32 dst = m68k_areg(regs, dstreg);
24832: { uae_u32 newv = dst + src;
24833: m68k_areg(regs, dstreg) = (newv);
24834: }}}}}}return 18;
24835: }
24836: unsigned long REGPARAM2 CPUFUNC(op_d0f8_0)(uae_u32 opcode) /* ADDA */
24837: {
24838: uae_u32 dstreg = (opcode >> 9) & 7;
24839: OpcodeFamily = 12; CurrentInstrCycles = 16;
24840: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
24841: { uae_s16 src = get_word(srca);
24842: { uae_s32 dst = m68k_areg(regs, dstreg);
24843: { uae_u32 newv = dst + src;
24844: m68k_areg(regs, dstreg) = (newv);
24845: }}}}}m68k_incpc(4);
24846: return 16;
24847: }
24848: unsigned long REGPARAM2 CPUFUNC(op_d0f9_0)(uae_u32 opcode) /* ADDA */
24849: {
24850: uae_u32 dstreg = (opcode >> 9) & 7;
24851: OpcodeFamily = 12; CurrentInstrCycles = 20;
24852: {{ uaecptr srca = get_ilong(2);
24853: { uae_s16 src = get_word(srca);
24854: { uae_s32 dst = m68k_areg(regs, dstreg);
24855: { uae_u32 newv = dst + src;
24856: m68k_areg(regs, dstreg) = (newv);
24857: }}}}}m68k_incpc(6);
24858: return 20;
24859: }
24860: unsigned long REGPARAM2 CPUFUNC(op_d0fa_0)(uae_u32 opcode) /* ADDA */
24861: {
24862: uae_u32 dstreg = (opcode >> 9) & 7;
24863: OpcodeFamily = 12; CurrentInstrCycles = 16;
24864: {{ uaecptr srca = m68k_getpc () + 2;
24865: srca += (uae_s32)(uae_s16)get_iword(2);
24866: { uae_s16 src = get_word(srca);
24867: { uae_s32 dst = m68k_areg(regs, dstreg);
24868: { uae_u32 newv = dst + src;
24869: m68k_areg(regs, dstreg) = (newv);
24870: }}}}}m68k_incpc(4);
24871: return 16;
24872: }
24873: unsigned long REGPARAM2 CPUFUNC(op_d0fb_0)(uae_u32 opcode) /* ADDA */
24874: {
24875: uae_u32 dstreg = (opcode >> 9) & 7;
24876: OpcodeFamily = 12; CurrentInstrCycles = 18;
24877: {{m68k_incpc(2);
24878: { uaecptr tmppc = m68k_getpc();
24879: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
24880: BusCyclePenalty += 2;
24881: { uae_s16 src = get_word(srca);
24882: { uae_s32 dst = m68k_areg(regs, dstreg);
24883: { uae_u32 newv = dst + src;
24884: m68k_areg(regs, dstreg) = (newv);
24885: }}}}}}return 18;
24886: }
24887: unsigned long REGPARAM2 CPUFUNC(op_d0fc_0)(uae_u32 opcode) /* ADDA */
24888: {
24889: uae_u32 dstreg = (opcode >> 9) & 7;
24890: OpcodeFamily = 12; CurrentInstrCycles = 12;
24891: {{ uae_s16 src = get_iword(2);
24892: { uae_s32 dst = m68k_areg(regs, dstreg);
24893: { uae_u32 newv = dst + src;
24894: m68k_areg(regs, dstreg) = (newv);
24895: }}}}m68k_incpc(4);
24896: return 12;
24897: }
24898: unsigned long REGPARAM2 CPUFUNC(op_d100_0)(uae_u32 opcode) /* ADDX */
24899: {
24900: uae_u32 srcreg = (opcode & 7);
24901: uae_u32 dstreg = (opcode >> 9) & 7;
24902: OpcodeFamily = 13; CurrentInstrCycles = 4;
24903: {{ uae_s8 src = m68k_dreg(regs, srcreg);
24904: { uae_s8 dst = m68k_dreg(regs, dstreg);
24905: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
24906: { int flgs = ((uae_s8)(src)) < 0;
24907: int flgo = ((uae_s8)(dst)) < 0;
24908: int flgn = ((uae_s8)(newv)) < 0;
24909: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24910: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
24911: COPY_CARRY;
24912: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
24913: SET_NFLG (((uae_s8)(newv)) < 0);
24914: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
24915: }}}}}m68k_incpc(2);
24916: return 4;
24917: }
24918: unsigned long REGPARAM2 CPUFUNC(op_d108_0)(uae_u32 opcode) /* ADDX */
24919: {
24920: uae_u32 srcreg = (opcode & 7);
24921: uae_u32 dstreg = (opcode >> 9) & 7;
24922: OpcodeFamily = 13; CurrentInstrCycles = 18;
24923: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
24924: { uae_s8 src = get_byte(srca);
24925: m68k_areg (regs, srcreg) = srca;
24926: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
24927: { uae_s8 dst = get_byte(dsta);
24928: m68k_areg (regs, dstreg) = dsta;
24929: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
24930: { int flgs = ((uae_s8)(src)) < 0;
24931: int flgo = ((uae_s8)(dst)) < 0;
24932: int flgn = ((uae_s8)(newv)) < 0;
24933: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24934: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
24935: COPY_CARRY;
24936: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
24937: SET_NFLG (((uae_s8)(newv)) < 0);
24938: put_byte(dsta,newv);
24939: }}}}}}}m68k_incpc(2);
24940: return 18;
24941: }
24942: unsigned long REGPARAM2 CPUFUNC(op_d110_0)(uae_u32 opcode) /* ADD */
24943: {
24944: uae_u32 srcreg = ((opcode >> 9) & 7);
24945: uae_u32 dstreg = opcode & 7;
24946: OpcodeFamily = 11; CurrentInstrCycles = 12;
24947: {{ uae_s8 src = m68k_dreg(regs, srcreg);
24948: { uaecptr dsta = m68k_areg(regs, dstreg);
24949: { uae_s8 dst = get_byte(dsta);
24950: { refill_prefetch (m68k_getpc(), 2);
24951: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24952: { int flgs = ((uae_s8)(src)) < 0;
24953: int flgo = ((uae_s8)(dst)) < 0;
24954: int flgn = ((uae_s8)(newv)) < 0;
24955: SET_ZFLG (((uae_s8)(newv)) == 0);
24956: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24957: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24958: COPY_CARRY;
24959: SET_NFLG (flgn != 0);
24960: put_byte(dsta,newv);
24961: }}}}}}}m68k_incpc(2);
24962: return 12;
24963: }
24964: unsigned long REGPARAM2 CPUFUNC(op_d118_0)(uae_u32 opcode) /* ADD */
24965: {
24966: uae_u32 srcreg = ((opcode >> 9) & 7);
24967: uae_u32 dstreg = opcode & 7;
24968: OpcodeFamily = 11; CurrentInstrCycles = 12;
24969: {{ uae_s8 src = m68k_dreg(regs, srcreg);
24970: { uaecptr dsta = m68k_areg(regs, dstreg);
24971: { uae_s8 dst = get_byte(dsta);
24972: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
24973: { refill_prefetch (m68k_getpc(), 2);
24974: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24975: { int flgs = ((uae_s8)(src)) < 0;
24976: int flgo = ((uae_s8)(dst)) < 0;
24977: int flgn = ((uae_s8)(newv)) < 0;
24978: SET_ZFLG (((uae_s8)(newv)) == 0);
24979: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
24980: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
24981: COPY_CARRY;
24982: SET_NFLG (flgn != 0);
24983: put_byte(dsta,newv);
24984: }}}}}}}m68k_incpc(2);
24985: return 12;
24986: }
24987: unsigned long REGPARAM2 CPUFUNC(op_d120_0)(uae_u32 opcode) /* ADD */
24988: {
24989: uae_u32 srcreg = ((opcode >> 9) & 7);
24990: uae_u32 dstreg = opcode & 7;
24991: OpcodeFamily = 11; CurrentInstrCycles = 14;
24992: {{ uae_s8 src = m68k_dreg(regs, srcreg);
24993: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
24994: { uae_s8 dst = get_byte(dsta);
24995: m68k_areg (regs, dstreg) = dsta;
24996: { refill_prefetch (m68k_getpc(), 2);
24997: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
24998: { int flgs = ((uae_s8)(src)) < 0;
24999: int flgo = ((uae_s8)(dst)) < 0;
25000: int flgn = ((uae_s8)(newv)) < 0;
25001: SET_ZFLG (((uae_s8)(newv)) == 0);
25002: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25003: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
25004: COPY_CARRY;
25005: SET_NFLG (flgn != 0);
25006: put_byte(dsta,newv);
25007: }}}}}}}m68k_incpc(2);
25008: return 14;
25009: }
25010: unsigned long REGPARAM2 CPUFUNC(op_d128_0)(uae_u32 opcode) /* ADD */
25011: {
25012: uae_u32 srcreg = ((opcode >> 9) & 7);
25013: uae_u32 dstreg = opcode & 7;
25014: OpcodeFamily = 11; CurrentInstrCycles = 16;
25015: {{ uae_s8 src = m68k_dreg(regs, srcreg);
25016: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
25017: { uae_s8 dst = get_byte(dsta);
25018: { refill_prefetch (m68k_getpc(), 2);
25019: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
25020: { int flgs = ((uae_s8)(src)) < 0;
25021: int flgo = ((uae_s8)(dst)) < 0;
25022: int flgn = ((uae_s8)(newv)) < 0;
25023: SET_ZFLG (((uae_s8)(newv)) == 0);
25024: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25025: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
25026: COPY_CARRY;
25027: SET_NFLG (flgn != 0);
25028: put_byte(dsta,newv);
25029: }}}}}}}m68k_incpc(4);
25030: return 16;
25031: }
25032: unsigned long REGPARAM2 CPUFUNC(op_d130_0)(uae_u32 opcode) /* ADD */
25033: {
25034: uae_u32 srcreg = ((opcode >> 9) & 7);
25035: uae_u32 dstreg = opcode & 7;
25036: OpcodeFamily = 11; CurrentInstrCycles = 18;
25037: {{ uae_s8 src = m68k_dreg(regs, srcreg);
25038: {m68k_incpc(2);
25039: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
25040: BusCyclePenalty += 2;
25041: { uae_s8 dst = get_byte(dsta);
25042: { refill_prefetch (m68k_getpc(), 2);
25043: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
25044: { int flgs = ((uae_s8)(src)) < 0;
25045: int flgo = ((uae_s8)(dst)) < 0;
25046: int flgn = ((uae_s8)(newv)) < 0;
25047: SET_ZFLG (((uae_s8)(newv)) == 0);
25048: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25049: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
25050: COPY_CARRY;
25051: SET_NFLG (flgn != 0);
25052: put_byte(dsta,newv);
25053: }}}}}}}}return 18;
25054: }
25055: unsigned long REGPARAM2 CPUFUNC(op_d138_0)(uae_u32 opcode) /* ADD */
25056: {
25057: uae_u32 srcreg = ((opcode >> 9) & 7);
25058: OpcodeFamily = 11; CurrentInstrCycles = 16;
25059: {{ uae_s8 src = m68k_dreg(regs, srcreg);
25060: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
25061: { uae_s8 dst = get_byte(dsta);
25062: { refill_prefetch (m68k_getpc(), 2);
25063: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
25064: { int flgs = ((uae_s8)(src)) < 0;
25065: int flgo = ((uae_s8)(dst)) < 0;
25066: int flgn = ((uae_s8)(newv)) < 0;
25067: SET_ZFLG (((uae_s8)(newv)) == 0);
25068: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25069: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
25070: COPY_CARRY;
25071: SET_NFLG (flgn != 0);
25072: put_byte(dsta,newv);
25073: }}}}}}}m68k_incpc(4);
25074: return 16;
25075: }
25076: unsigned long REGPARAM2 CPUFUNC(op_d139_0)(uae_u32 opcode) /* ADD */
25077: {
25078: uae_u32 srcreg = ((opcode >> 9) & 7);
25079: OpcodeFamily = 11; CurrentInstrCycles = 20;
25080: {{ uae_s8 src = m68k_dreg(regs, srcreg);
25081: { uaecptr dsta = get_ilong(2);
25082: { uae_s8 dst = get_byte(dsta);
25083: { refill_prefetch (m68k_getpc(), 2);
25084: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
25085: { int flgs = ((uae_s8)(src)) < 0;
25086: int flgo = ((uae_s8)(dst)) < 0;
25087: int flgn = ((uae_s8)(newv)) < 0;
25088: SET_ZFLG (((uae_s8)(newv)) == 0);
25089: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25090: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
25091: COPY_CARRY;
25092: SET_NFLG (flgn != 0);
25093: put_byte(dsta,newv);
25094: }}}}}}}m68k_incpc(6);
25095: return 20;
25096: }
25097: unsigned long REGPARAM2 CPUFUNC(op_d140_0)(uae_u32 opcode) /* ADDX */
25098: {
25099: uae_u32 srcreg = (opcode & 7);
25100: uae_u32 dstreg = (opcode >> 9) & 7;
25101: OpcodeFamily = 13; CurrentInstrCycles = 4;
25102: {{ uae_s16 src = m68k_dreg(regs, srcreg);
25103: { uae_s16 dst = m68k_dreg(regs, dstreg);
25104: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
25105: { int flgs = ((uae_s16)(src)) < 0;
25106: int flgo = ((uae_s16)(dst)) < 0;
25107: int flgn = ((uae_s16)(newv)) < 0;
25108: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25109: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
25110: COPY_CARRY;
25111: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
25112: SET_NFLG (((uae_s16)(newv)) < 0);
25113: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
25114: }}}}}m68k_incpc(2);
25115: return 4;
25116: }
25117: unsigned long REGPARAM2 CPUFUNC(op_d148_0)(uae_u32 opcode) /* ADDX */
25118: {
25119: uae_u32 srcreg = (opcode & 7);
25120: uae_u32 dstreg = (opcode >> 9) & 7;
25121: OpcodeFamily = 13; CurrentInstrCycles = 18;
25122: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
25123: { uae_s16 src = get_word(srca);
25124: m68k_areg (regs, srcreg) = srca;
25125: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
25126: { uae_s16 dst = get_word(dsta);
25127: m68k_areg (regs, dstreg) = dsta;
25128: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
25129: { int flgs = ((uae_s16)(src)) < 0;
25130: int flgo = ((uae_s16)(dst)) < 0;
25131: int flgn = ((uae_s16)(newv)) < 0;
25132: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25133: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
25134: COPY_CARRY;
25135: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
25136: SET_NFLG (((uae_s16)(newv)) < 0);
25137: put_word(dsta,newv);
25138: }}}}}}}m68k_incpc(2);
25139: return 18;
25140: }
25141: unsigned long REGPARAM2 CPUFUNC(op_d150_0)(uae_u32 opcode) /* ADD */
25142: {
25143: uae_u32 srcreg = ((opcode >> 9) & 7);
25144: uae_u32 dstreg = opcode & 7;
25145: OpcodeFamily = 11; CurrentInstrCycles = 12;
25146: {{ uae_s16 src = m68k_dreg(regs, srcreg);
25147: { uaecptr dsta = m68k_areg(regs, dstreg);
25148: { uae_s16 dst = get_word(dsta);
25149: { refill_prefetch (m68k_getpc(), 2);
25150: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
25151: { int flgs = ((uae_s16)(src)) < 0;
25152: int flgo = ((uae_s16)(dst)) < 0;
25153: int flgn = ((uae_s16)(newv)) < 0;
25154: SET_ZFLG (((uae_s16)(newv)) == 0);
25155: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25156: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
25157: COPY_CARRY;
25158: SET_NFLG (flgn != 0);
25159: put_word(dsta,newv);
25160: }}}}}}}m68k_incpc(2);
25161: return 12;
25162: }
25163: unsigned long REGPARAM2 CPUFUNC(op_d158_0)(uae_u32 opcode) /* ADD */
25164: {
25165: uae_u32 srcreg = ((opcode >> 9) & 7);
25166: uae_u32 dstreg = opcode & 7;
25167: OpcodeFamily = 11; CurrentInstrCycles = 12;
25168: {{ uae_s16 src = m68k_dreg(regs, srcreg);
25169: { uaecptr dsta = m68k_areg(regs, dstreg);
25170: { uae_s16 dst = get_word(dsta);
25171: m68k_areg(regs, dstreg) += 2;
25172: { refill_prefetch (m68k_getpc(), 2);
25173: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
25174: { int flgs = ((uae_s16)(src)) < 0;
25175: int flgo = ((uae_s16)(dst)) < 0;
25176: int flgn = ((uae_s16)(newv)) < 0;
25177: SET_ZFLG (((uae_s16)(newv)) == 0);
25178: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25179: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
25180: COPY_CARRY;
25181: SET_NFLG (flgn != 0);
25182: put_word(dsta,newv);
25183: }}}}}}}m68k_incpc(2);
25184: return 12;
25185: }
25186: unsigned long REGPARAM2 CPUFUNC(op_d160_0)(uae_u32 opcode) /* ADD */
25187: {
25188: uae_u32 srcreg = ((opcode >> 9) & 7);
25189: uae_u32 dstreg = opcode & 7;
25190: OpcodeFamily = 11; CurrentInstrCycles = 14;
25191: {{ uae_s16 src = m68k_dreg(regs, srcreg);
25192: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
25193: { uae_s16 dst = get_word(dsta);
25194: m68k_areg (regs, dstreg) = dsta;
25195: { refill_prefetch (m68k_getpc(), 2);
25196: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
25197: { int flgs = ((uae_s16)(src)) < 0;
25198: int flgo = ((uae_s16)(dst)) < 0;
25199: int flgn = ((uae_s16)(newv)) < 0;
25200: SET_ZFLG (((uae_s16)(newv)) == 0);
25201: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25202: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
25203: COPY_CARRY;
25204: SET_NFLG (flgn != 0);
25205: put_word(dsta,newv);
25206: }}}}}}}m68k_incpc(2);
25207: return 14;
25208: }
25209: unsigned long REGPARAM2 CPUFUNC(op_d168_0)(uae_u32 opcode) /* ADD */
25210: {
25211: uae_u32 srcreg = ((opcode >> 9) & 7);
25212: uae_u32 dstreg = opcode & 7;
25213: OpcodeFamily = 11; CurrentInstrCycles = 16;
25214: {{ uae_s16 src = m68k_dreg(regs, srcreg);
25215: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
25216: { uae_s16 dst = get_word(dsta);
25217: { refill_prefetch (m68k_getpc(), 2);
25218: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
25219: { int flgs = ((uae_s16)(src)) < 0;
25220: int flgo = ((uae_s16)(dst)) < 0;
25221: int flgn = ((uae_s16)(newv)) < 0;
25222: SET_ZFLG (((uae_s16)(newv)) == 0);
25223: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25224: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
25225: COPY_CARRY;
25226: SET_NFLG (flgn != 0);
25227: put_word(dsta,newv);
25228: }}}}}}}m68k_incpc(4);
25229: return 16;
25230: }
25231: unsigned long REGPARAM2 CPUFUNC(op_d170_0)(uae_u32 opcode) /* ADD */
25232: {
25233: uae_u32 srcreg = ((opcode >> 9) & 7);
25234: uae_u32 dstreg = opcode & 7;
25235: OpcodeFamily = 11; CurrentInstrCycles = 18;
25236: {{ uae_s16 src = m68k_dreg(regs, srcreg);
25237: {m68k_incpc(2);
25238: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
25239: BusCyclePenalty += 2;
25240: { uae_s16 dst = get_word(dsta);
25241: { refill_prefetch (m68k_getpc(), 2);
25242: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
25243: { int flgs = ((uae_s16)(src)) < 0;
25244: int flgo = ((uae_s16)(dst)) < 0;
25245: int flgn = ((uae_s16)(newv)) < 0;
25246: SET_ZFLG (((uae_s16)(newv)) == 0);
25247: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25248: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
25249: COPY_CARRY;
25250: SET_NFLG (flgn != 0);
25251: put_word(dsta,newv);
25252: }}}}}}}}return 18;
25253: }
25254: unsigned long REGPARAM2 CPUFUNC(op_d178_0)(uae_u32 opcode) /* ADD */
25255: {
25256: uae_u32 srcreg = ((opcode >> 9) & 7);
25257: OpcodeFamily = 11; CurrentInstrCycles = 16;
25258: {{ uae_s16 src = m68k_dreg(regs, srcreg);
25259: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
25260: { uae_s16 dst = get_word(dsta);
25261: { refill_prefetch (m68k_getpc(), 2);
25262: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
25263: { int flgs = ((uae_s16)(src)) < 0;
25264: int flgo = ((uae_s16)(dst)) < 0;
25265: int flgn = ((uae_s16)(newv)) < 0;
25266: SET_ZFLG (((uae_s16)(newv)) == 0);
25267: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25268: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
25269: COPY_CARRY;
25270: SET_NFLG (flgn != 0);
25271: put_word(dsta,newv);
25272: }}}}}}}m68k_incpc(4);
25273: return 16;
25274: }
25275: unsigned long REGPARAM2 CPUFUNC(op_d179_0)(uae_u32 opcode) /* ADD */
25276: {
25277: uae_u32 srcreg = ((opcode >> 9) & 7);
25278: OpcodeFamily = 11; CurrentInstrCycles = 20;
25279: {{ uae_s16 src = m68k_dreg(regs, srcreg);
25280: { uaecptr dsta = get_ilong(2);
25281: { uae_s16 dst = get_word(dsta);
25282: { refill_prefetch (m68k_getpc(), 2);
25283: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
25284: { int flgs = ((uae_s16)(src)) < 0;
25285: int flgo = ((uae_s16)(dst)) < 0;
25286: int flgn = ((uae_s16)(newv)) < 0;
25287: SET_ZFLG (((uae_s16)(newv)) == 0);
25288: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25289: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
25290: COPY_CARRY;
25291: SET_NFLG (flgn != 0);
25292: put_word(dsta,newv);
25293: }}}}}}}m68k_incpc(6);
25294: return 20;
25295: }
25296: unsigned long REGPARAM2 CPUFUNC(op_d180_0)(uae_u32 opcode) /* ADDX */
25297: {
25298: uae_u32 srcreg = (opcode & 7);
25299: uae_u32 dstreg = (opcode >> 9) & 7;
25300: OpcodeFamily = 13; CurrentInstrCycles = 8;
25301: {{ uae_s32 src = m68k_dreg(regs, srcreg);
25302: { uae_s32 dst = m68k_dreg(regs, dstreg);
25303: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
25304: { int flgs = ((uae_s32)(src)) < 0;
25305: int flgo = ((uae_s32)(dst)) < 0;
25306: int flgn = ((uae_s32)(newv)) < 0;
25307: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25308: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
25309: COPY_CARRY;
25310: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
25311: SET_NFLG (((uae_s32)(newv)) < 0);
25312: m68k_dreg(regs, dstreg) = (newv);
25313: }}}}}m68k_incpc(2);
25314: return 8;
25315: }
25316: unsigned long REGPARAM2 CPUFUNC(op_d188_0)(uae_u32 opcode) /* ADDX */
25317: {
25318: uae_u32 srcreg = (opcode & 7);
25319: uae_u32 dstreg = (opcode >> 9) & 7;
25320: OpcodeFamily = 13; CurrentInstrCycles = 30;
25321: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
25322: { uae_s32 src = get_long(srca);
25323: m68k_areg (regs, srcreg) = srca;
25324: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
25325: { uae_s32 dst = get_long(dsta);
25326: m68k_areg (regs, dstreg) = dsta;
25327: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
25328: { int flgs = ((uae_s32)(src)) < 0;
25329: int flgo = ((uae_s32)(dst)) < 0;
25330: int flgn = ((uae_s32)(newv)) < 0;
25331: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25332: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
25333: COPY_CARRY;
25334: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
25335: SET_NFLG (((uae_s32)(newv)) < 0);
25336: put_long(dsta,newv);
25337: }}}}}}}m68k_incpc(2);
25338: return 30;
25339: }
25340: unsigned long REGPARAM2 CPUFUNC(op_d190_0)(uae_u32 opcode) /* ADD */
25341: {
25342: uae_u32 srcreg = ((opcode >> 9) & 7);
25343: uae_u32 dstreg = opcode & 7;
25344: OpcodeFamily = 11; CurrentInstrCycles = 20;
25345: {{ uae_s32 src = m68k_dreg(regs, srcreg);
25346: { uaecptr dsta = m68k_areg(regs, dstreg);
25347: { uae_s32 dst = get_long(dsta);
25348: { refill_prefetch (m68k_getpc(), 2);
25349: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
25350: { int flgs = ((uae_s32)(src)) < 0;
25351: int flgo = ((uae_s32)(dst)) < 0;
25352: int flgn = ((uae_s32)(newv)) < 0;
25353: SET_ZFLG (((uae_s32)(newv)) == 0);
25354: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25355: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
25356: COPY_CARRY;
25357: SET_NFLG (flgn != 0);
25358: put_long(dsta,newv);
25359: }}}}}}}m68k_incpc(2);
25360: return 20;
25361: }
25362: unsigned long REGPARAM2 CPUFUNC(op_d198_0)(uae_u32 opcode) /* ADD */
25363: {
25364: uae_u32 srcreg = ((opcode >> 9) & 7);
25365: uae_u32 dstreg = opcode & 7;
25366: OpcodeFamily = 11; CurrentInstrCycles = 20;
25367: {{ uae_s32 src = m68k_dreg(regs, srcreg);
25368: { uaecptr dsta = m68k_areg(regs, dstreg);
25369: { uae_s32 dst = get_long(dsta);
25370: m68k_areg(regs, dstreg) += 4;
25371: { refill_prefetch (m68k_getpc(), 2);
25372: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
25373: { int flgs = ((uae_s32)(src)) < 0;
25374: int flgo = ((uae_s32)(dst)) < 0;
25375: int flgn = ((uae_s32)(newv)) < 0;
25376: SET_ZFLG (((uae_s32)(newv)) == 0);
25377: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25378: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
25379: COPY_CARRY;
25380: SET_NFLG (flgn != 0);
25381: put_long(dsta,newv);
25382: }}}}}}}m68k_incpc(2);
25383: return 20;
25384: }
25385: unsigned long REGPARAM2 CPUFUNC(op_d1a0_0)(uae_u32 opcode) /* ADD */
25386: {
25387: uae_u32 srcreg = ((opcode >> 9) & 7);
25388: uae_u32 dstreg = opcode & 7;
25389: OpcodeFamily = 11; CurrentInstrCycles = 22;
25390: {{ uae_s32 src = m68k_dreg(regs, srcreg);
25391: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
25392: { uae_s32 dst = get_long(dsta);
25393: m68k_areg (regs, dstreg) = dsta;
25394: { refill_prefetch (m68k_getpc(), 2);
25395: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
25396: { int flgs = ((uae_s32)(src)) < 0;
25397: int flgo = ((uae_s32)(dst)) < 0;
25398: int flgn = ((uae_s32)(newv)) < 0;
25399: SET_ZFLG (((uae_s32)(newv)) == 0);
25400: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25401: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
25402: COPY_CARRY;
25403: SET_NFLG (flgn != 0);
25404: put_long(dsta,newv);
25405: }}}}}}}m68k_incpc(2);
25406: return 22;
25407: }
25408: unsigned long REGPARAM2 CPUFUNC(op_d1a8_0)(uae_u32 opcode) /* ADD */
25409: {
25410: uae_u32 srcreg = ((opcode >> 9) & 7);
25411: uae_u32 dstreg = opcode & 7;
25412: OpcodeFamily = 11; CurrentInstrCycles = 24;
25413: {{ uae_s32 src = m68k_dreg(regs, srcreg);
25414: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(2);
25415: { uae_s32 dst = get_long(dsta);
25416: { refill_prefetch (m68k_getpc(), 2);
25417: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
25418: { int flgs = ((uae_s32)(src)) < 0;
25419: int flgo = ((uae_s32)(dst)) < 0;
25420: int flgn = ((uae_s32)(newv)) < 0;
25421: SET_ZFLG (((uae_s32)(newv)) == 0);
25422: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25423: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
25424: COPY_CARRY;
25425: SET_NFLG (flgn != 0);
25426: put_long(dsta,newv);
25427: }}}}}}}m68k_incpc(4);
25428: return 24;
25429: }
25430: unsigned long REGPARAM2 CPUFUNC(op_d1b0_0)(uae_u32 opcode) /* ADD */
25431: {
25432: uae_u32 srcreg = ((opcode >> 9) & 7);
25433: uae_u32 dstreg = opcode & 7;
25434: OpcodeFamily = 11; CurrentInstrCycles = 26;
25435: {{ uae_s32 src = m68k_dreg(regs, srcreg);
25436: {m68k_incpc(2);
25437: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
25438: BusCyclePenalty += 2;
25439: { uae_s32 dst = get_long(dsta);
25440: { refill_prefetch (m68k_getpc(), 2);
25441: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
25442: { int flgs = ((uae_s32)(src)) < 0;
25443: int flgo = ((uae_s32)(dst)) < 0;
25444: int flgn = ((uae_s32)(newv)) < 0;
25445: SET_ZFLG (((uae_s32)(newv)) == 0);
25446: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25447: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
25448: COPY_CARRY;
25449: SET_NFLG (flgn != 0);
25450: put_long(dsta,newv);
25451: }}}}}}}}return 26;
25452: }
25453: unsigned long REGPARAM2 CPUFUNC(op_d1b8_0)(uae_u32 opcode) /* ADD */
25454: {
25455: uae_u32 srcreg = ((opcode >> 9) & 7);
25456: OpcodeFamily = 11; CurrentInstrCycles = 24;
25457: {{ uae_s32 src = m68k_dreg(regs, srcreg);
25458: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(2);
25459: { uae_s32 dst = get_long(dsta);
25460: { refill_prefetch (m68k_getpc(), 2);
25461: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
25462: { int flgs = ((uae_s32)(src)) < 0;
25463: int flgo = ((uae_s32)(dst)) < 0;
25464: int flgn = ((uae_s32)(newv)) < 0;
25465: SET_ZFLG (((uae_s32)(newv)) == 0);
25466: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25467: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
25468: COPY_CARRY;
25469: SET_NFLG (flgn != 0);
25470: put_long(dsta,newv);
25471: }}}}}}}m68k_incpc(4);
25472: return 24;
25473: }
25474: unsigned long REGPARAM2 CPUFUNC(op_d1b9_0)(uae_u32 opcode) /* ADD */
25475: {
25476: uae_u32 srcreg = ((opcode >> 9) & 7);
25477: OpcodeFamily = 11; CurrentInstrCycles = 28;
25478: {{ uae_s32 src = m68k_dreg(regs, srcreg);
25479: { uaecptr dsta = get_ilong(2);
25480: { uae_s32 dst = get_long(dsta);
25481: { refill_prefetch (m68k_getpc(), 2);
25482: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
25483: { int flgs = ((uae_s32)(src)) < 0;
25484: int flgo = ((uae_s32)(dst)) < 0;
25485: int flgn = ((uae_s32)(newv)) < 0;
25486: SET_ZFLG (((uae_s32)(newv)) == 0);
25487: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
25488: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
25489: COPY_CARRY;
25490: SET_NFLG (flgn != 0);
25491: put_long(dsta,newv);
25492: }}}}}}}m68k_incpc(6);
25493: return 28;
25494: }
25495: unsigned long REGPARAM2 CPUFUNC(op_d1c0_0)(uae_u32 opcode) /* ADDA */
25496: {
25497: uae_u32 srcreg = (opcode & 7);
25498: uae_u32 dstreg = (opcode >> 9) & 7;
25499: OpcodeFamily = 12; CurrentInstrCycles = 8;
25500: {{ uae_s32 src = m68k_dreg(regs, srcreg);
25501: { uae_s32 dst = m68k_areg(regs, dstreg);
25502: { uae_u32 newv = dst + src;
25503: m68k_areg(regs, dstreg) = (newv);
25504: }}}}m68k_incpc(2);
25505: return 8;
25506: }
25507: unsigned long REGPARAM2 CPUFUNC(op_d1c8_0)(uae_u32 opcode) /* ADDA */
25508: {
25509: uae_u32 srcreg = (opcode & 7);
25510: uae_u32 dstreg = (opcode >> 9) & 7;
25511: OpcodeFamily = 12; CurrentInstrCycles = 8;
25512: {{ uae_s32 src = m68k_areg(regs, srcreg);
25513: { uae_s32 dst = m68k_areg(regs, dstreg);
25514: { uae_u32 newv = dst + src;
25515: m68k_areg(regs, dstreg) = (newv);
25516: }}}}m68k_incpc(2);
25517: return 8;
25518: }
25519: unsigned long REGPARAM2 CPUFUNC(op_d1d0_0)(uae_u32 opcode) /* ADDA */
25520: {
25521: uae_u32 srcreg = (opcode & 7);
25522: uae_u32 dstreg = (opcode >> 9) & 7;
25523: OpcodeFamily = 12; CurrentInstrCycles = 14;
25524: {{ uaecptr srca = m68k_areg(regs, srcreg);
25525: { uae_s32 src = get_long(srca);
25526: { uae_s32 dst = m68k_areg(regs, dstreg);
25527: { uae_u32 newv = dst + src;
25528: m68k_areg(regs, dstreg) = (newv);
25529: }}}}}m68k_incpc(2);
25530: return 14;
25531: }
25532: #endif
25533:
25534: #ifdef PART_8
25535: unsigned long REGPARAM2 CPUFUNC(op_d1d8_0)(uae_u32 opcode) /* ADDA */
25536: {
25537: uae_u32 srcreg = (opcode & 7);
25538: uae_u32 dstreg = (opcode >> 9) & 7;
25539: OpcodeFamily = 12; CurrentInstrCycles = 14;
25540: {{ uaecptr srca = m68k_areg(regs, srcreg);
25541: { uae_s32 src = get_long(srca);
25542: m68k_areg(regs, srcreg) += 4;
25543: { uae_s32 dst = m68k_areg(regs, dstreg);
25544: { uae_u32 newv = dst + src;
25545: m68k_areg(regs, dstreg) = (newv);
25546: }}}}}m68k_incpc(2);
25547: return 14;
25548: }
25549: unsigned long REGPARAM2 CPUFUNC(op_d1e0_0)(uae_u32 opcode) /* ADDA */
25550: {
25551: uae_u32 srcreg = (opcode & 7);
25552: uae_u32 dstreg = (opcode >> 9) & 7;
25553: OpcodeFamily = 12; CurrentInstrCycles = 16;
25554: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
25555: { uae_s32 src = get_long(srca);
25556: m68k_areg (regs, srcreg) = srca;
25557: { uae_s32 dst = m68k_areg(regs, dstreg);
25558: { uae_u32 newv = dst + src;
25559: m68k_areg(regs, dstreg) = (newv);
25560: }}}}}m68k_incpc(2);
25561: return 16;
25562: }
25563: unsigned long REGPARAM2 CPUFUNC(op_d1e8_0)(uae_u32 opcode) /* ADDA */
25564: {
25565: uae_u32 srcreg = (opcode & 7);
25566: uae_u32 dstreg = (opcode >> 9) & 7;
25567: OpcodeFamily = 12; CurrentInstrCycles = 18;
25568: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
25569: { uae_s32 src = get_long(srca);
25570: { uae_s32 dst = m68k_areg(regs, dstreg);
25571: { uae_u32 newv = dst + src;
25572: m68k_areg(regs, dstreg) = (newv);
25573: }}}}}m68k_incpc(4);
25574: return 18;
25575: }
25576: unsigned long REGPARAM2 CPUFUNC(op_d1f0_0)(uae_u32 opcode) /* ADDA */
25577: {
25578: uae_u32 srcreg = (opcode & 7);
25579: uae_u32 dstreg = (opcode >> 9) & 7;
25580: OpcodeFamily = 12; CurrentInstrCycles = 20;
25581: {{m68k_incpc(2);
25582: { uaecptr srca = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
25583: BusCyclePenalty += 2;
25584: { uae_s32 src = get_long(srca);
25585: { uae_s32 dst = m68k_areg(regs, dstreg);
25586: { uae_u32 newv = dst + src;
25587: m68k_areg(regs, dstreg) = (newv);
25588: }}}}}}return 20;
25589: }
25590: unsigned long REGPARAM2 CPUFUNC(op_d1f8_0)(uae_u32 opcode) /* ADDA */
25591: {
25592: uae_u32 dstreg = (opcode >> 9) & 7;
25593: OpcodeFamily = 12; CurrentInstrCycles = 18;
25594: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
25595: { uae_s32 src = get_long(srca);
25596: { uae_s32 dst = m68k_areg(regs, dstreg);
25597: { uae_u32 newv = dst + src;
25598: m68k_areg(regs, dstreg) = (newv);
25599: }}}}}m68k_incpc(4);
25600: return 18;
25601: }
25602: unsigned long REGPARAM2 CPUFUNC(op_d1f9_0)(uae_u32 opcode) /* ADDA */
25603: {
25604: uae_u32 dstreg = (opcode >> 9) & 7;
25605: OpcodeFamily = 12; CurrentInstrCycles = 22;
25606: {{ uaecptr srca = get_ilong(2);
25607: { uae_s32 src = get_long(srca);
25608: { uae_s32 dst = m68k_areg(regs, dstreg);
25609: { uae_u32 newv = dst + src;
25610: m68k_areg(regs, dstreg) = (newv);
25611: }}}}}m68k_incpc(6);
25612: return 22;
25613: }
25614: unsigned long REGPARAM2 CPUFUNC(op_d1fa_0)(uae_u32 opcode) /* ADDA */
25615: {
25616: uae_u32 dstreg = (opcode >> 9) & 7;
25617: OpcodeFamily = 12; CurrentInstrCycles = 18;
25618: {{ uaecptr srca = m68k_getpc () + 2;
25619: srca += (uae_s32)(uae_s16)get_iword(2);
25620: { uae_s32 src = get_long(srca);
25621: { uae_s32 dst = m68k_areg(regs, dstreg);
25622: { uae_u32 newv = dst + src;
25623: m68k_areg(regs, dstreg) = (newv);
25624: }}}}}m68k_incpc(4);
25625: return 18;
25626: }
25627: unsigned long REGPARAM2 CPUFUNC(op_d1fb_0)(uae_u32 opcode) /* ADDA */
25628: {
25629: uae_u32 dstreg = (opcode >> 9) & 7;
25630: OpcodeFamily = 12; CurrentInstrCycles = 20;
25631: {{m68k_incpc(2);
25632: { uaecptr tmppc = m68k_getpc();
25633: uaecptr srca = get_disp_ea_020(tmppc, next_iword());
25634: BusCyclePenalty += 2;
25635: { uae_s32 src = get_long(srca);
25636: { uae_s32 dst = m68k_areg(regs, dstreg);
25637: { uae_u32 newv = dst + src;
25638: m68k_areg(regs, dstreg) = (newv);
25639: }}}}}}return 20;
25640: }
25641: unsigned long REGPARAM2 CPUFUNC(op_d1fc_0)(uae_u32 opcode) /* ADDA */
25642: {
25643: uae_u32 dstreg = (opcode >> 9) & 7;
25644: OpcodeFamily = 12; CurrentInstrCycles = 16;
25645: {{ uae_s32 src = get_ilong(2);
25646: { uae_s32 dst = m68k_areg(regs, dstreg);
25647: { uae_u32 newv = dst + src;
25648: m68k_areg(regs, dstreg) = (newv);
25649: }}}}m68k_incpc(6);
25650: return 16;
25651: }
25652: unsigned long REGPARAM2 CPUFUNC(op_e000_0)(uae_u32 opcode) /* ASR */
25653: {
25654: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
25655: uae_u32 dstreg = opcode & 7;
25656: unsigned int retcycles = 0;
25657: OpcodeFamily = 64; CurrentInstrCycles = 4;
25658: {{ uae_u32 cnt = srcreg;
25659: { uae_s8 data = m68k_dreg(regs, dstreg);
25660: { uae_u32 val = (uae_u8)data;
25661: uae_u32 sign = (0x80 & val) >> 7;
25662: cnt &= 63;
25663: retcycles = cnt;
25664: CLEAR_CZNV;
25665: if (cnt >= 8) {
25666: val = 0xff & (uae_u32)-sign;
25667: SET_CFLG (sign);
25668: COPY_CARRY;
25669: } else {
25670: val >>= cnt - 1;
25671: SET_CFLG (val & 1);
25672: COPY_CARRY;
25673: val >>= 1;
25674: val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
25675: val &= 0xff;
25676: }
25677: SET_ZFLG (((uae_s8)(val)) == 0);
25678: SET_NFLG (((uae_s8)(val)) < 0);
25679: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
25680: }}}}m68k_incpc(2);
25681: return (6+retcycles*2);
25682: }
25683: unsigned long REGPARAM2 CPUFUNC(op_e008_0)(uae_u32 opcode) /* LSR */
25684: {
25685: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
25686: uae_u32 dstreg = opcode & 7;
25687: unsigned int retcycles = 0;
25688: OpcodeFamily = 66; CurrentInstrCycles = 4;
25689: {{ uae_u32 cnt = srcreg;
25690: { uae_s8 data = m68k_dreg(regs, dstreg);
25691: { uae_u32 val = (uae_u8)data;
25692: cnt &= 63;
25693: retcycles = cnt;
25694: CLEAR_CZNV;
25695: if (cnt >= 8) {
25696: SET_CFLG ((cnt == 8) & (val >> 7));
25697: COPY_CARRY;
25698: val = 0;
25699: } else {
25700: val >>= cnt - 1;
25701: SET_CFLG (val & 1);
25702: COPY_CARRY;
25703: val >>= 1;
25704: }
25705: SET_ZFLG (((uae_s8)(val)) == 0);
25706: SET_NFLG (((uae_s8)(val)) < 0);
25707: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
25708: }}}}m68k_incpc(2);
25709: return (6+retcycles*2);
25710: }
25711: unsigned long REGPARAM2 CPUFUNC(op_e010_0)(uae_u32 opcode) /* ROXR */
25712: {
25713: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
25714: uae_u32 dstreg = opcode & 7;
25715: unsigned int retcycles = 0;
25716: OpcodeFamily = 71; CurrentInstrCycles = 4;
25717: {{ uae_u32 cnt = srcreg;
25718: { uae_s8 data = m68k_dreg(regs, dstreg);
25719: { uae_u32 val = (uae_u8)data;
25720: cnt &= 63;
25721: retcycles = cnt;
25722: CLEAR_CZNV;
25723: { cnt--;
25724: {
25725: uae_u32 carry;
25726: uae_u32 hival = (val << 1) | GET_XFLG;
25727: hival <<= (7 - cnt);
25728: val >>= cnt;
25729: carry = val & 1;
25730: val >>= 1;
25731: val |= hival;
25732: SET_XFLG (carry);
25733: val &= 0xff;
25734: } }
25735: SET_CFLG (GET_XFLG);
25736: SET_ZFLG (((uae_s8)(val)) == 0);
25737: SET_NFLG (((uae_s8)(val)) < 0);
25738: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
25739: }}}}m68k_incpc(2);
25740: return (6+retcycles*2);
25741: }
25742: unsigned long REGPARAM2 CPUFUNC(op_e018_0)(uae_u32 opcode) /* ROR */
25743: {
25744: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
25745: uae_u32 dstreg = opcode & 7;
25746: unsigned int retcycles = 0;
25747: OpcodeFamily = 69; CurrentInstrCycles = 4;
25748: {{ uae_u32 cnt = srcreg;
25749: { uae_s8 data = m68k_dreg(regs, dstreg);
25750: { uae_u32 val = (uae_u8)data;
25751: cnt &= 63;
25752: retcycles = cnt;
25753: CLEAR_CZNV;
25754: { uae_u32 hival;
25755: cnt &= 7;
25756: hival = val << (8 - cnt);
25757: val >>= cnt;
25758: val |= hival;
25759: val &= 0xff;
25760: SET_CFLG ((val & 0x80) >> 7);
25761: }
25762: SET_ZFLG (((uae_s8)(val)) == 0);
25763: SET_NFLG (((uae_s8)(val)) < 0);
25764: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
25765: }}}}m68k_incpc(2);
25766: return (6+retcycles*2);
25767: }
25768: unsigned long REGPARAM2 CPUFUNC(op_e020_0)(uae_u32 opcode) /* ASR */
25769: {
25770: uae_u32 srcreg = ((opcode >> 9) & 7);
25771: uae_u32 dstreg = opcode & 7;
25772: unsigned int retcycles = 0;
25773: OpcodeFamily = 64; CurrentInstrCycles = 4;
25774: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
25775: { uae_s8 data = m68k_dreg(regs, dstreg);
25776: { uae_u32 val = (uae_u8)data;
25777: uae_u32 sign = (0x80 & val) >> 7;
25778: cnt &= 63;
25779: retcycles = cnt;
25780: CLEAR_CZNV;
25781: if (cnt >= 8) {
25782: val = 0xff & (uae_u32)-sign;
25783: SET_CFLG (sign);
25784: COPY_CARRY;
25785: } else if (cnt > 0) {
25786: val >>= cnt - 1;
25787: SET_CFLG (val & 1);
25788: COPY_CARRY;
25789: val >>= 1;
25790: val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
25791: val &= 0xff;
25792: }
25793: SET_ZFLG (((uae_s8)(val)) == 0);
25794: SET_NFLG (((uae_s8)(val)) < 0);
25795: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
25796: }}}}m68k_incpc(2);
25797: return (6+retcycles*2);
25798: }
25799: unsigned long REGPARAM2 CPUFUNC(op_e028_0)(uae_u32 opcode) /* LSR */
25800: {
25801: uae_u32 srcreg = ((opcode >> 9) & 7);
25802: uae_u32 dstreg = opcode & 7;
25803: unsigned int retcycles = 0;
25804: OpcodeFamily = 66; CurrentInstrCycles = 4;
25805: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
25806: { uae_s8 data = m68k_dreg(regs, dstreg);
25807: { uae_u32 val = (uae_u8)data;
25808: cnt &= 63;
25809: retcycles = cnt;
25810: CLEAR_CZNV;
25811: if (cnt >= 8) {
25812: SET_CFLG ((cnt == 8) & (val >> 7));
25813: COPY_CARRY;
25814: val = 0;
25815: } else if (cnt > 0) {
25816: val >>= cnt - 1;
25817: SET_CFLG (val & 1);
25818: COPY_CARRY;
25819: val >>= 1;
25820: }
25821: SET_ZFLG (((uae_s8)(val)) == 0);
25822: SET_NFLG (((uae_s8)(val)) < 0);
25823: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
25824: }}}}m68k_incpc(2);
25825: return (6+retcycles*2);
25826: }
25827: unsigned long REGPARAM2 CPUFUNC(op_e030_0)(uae_u32 opcode) /* ROXR */
25828: {
25829: uae_u32 srcreg = ((opcode >> 9) & 7);
25830: uae_u32 dstreg = opcode & 7;
25831: unsigned int retcycles = 0;
25832: OpcodeFamily = 71; CurrentInstrCycles = 4;
25833: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
25834: { uae_s8 data = m68k_dreg(regs, dstreg);
25835: { uae_u32 val = (uae_u8)data;
25836: cnt &= 63;
25837: retcycles = cnt;
25838: CLEAR_CZNV;
25839: if (cnt >= 36) cnt -= 36;
25840: if (cnt >= 18) cnt -= 18;
25841: if (cnt >= 9) cnt -= 9;
25842: if (cnt > 0) {
25843: cnt--;
25844: {
25845: uae_u32 carry;
25846: uae_u32 hival = (val << 1) | GET_XFLG;
25847: hival <<= (7 - cnt);
25848: val >>= cnt;
25849: carry = val & 1;
25850: val >>= 1;
25851: val |= hival;
25852: SET_XFLG (carry);
25853: val &= 0xff;
25854: } }
25855: SET_CFLG (GET_XFLG);
25856: SET_ZFLG (((uae_s8)(val)) == 0);
25857: SET_NFLG (((uae_s8)(val)) < 0);
25858: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
25859: }}}}m68k_incpc(2);
25860: return (6+retcycles*2);
25861: }
25862: unsigned long REGPARAM2 CPUFUNC(op_e038_0)(uae_u32 opcode) /* ROR */
25863: {
25864: uae_u32 srcreg = ((opcode >> 9) & 7);
25865: uae_u32 dstreg = opcode & 7;
25866: unsigned int retcycles = 0;
25867: OpcodeFamily = 69; CurrentInstrCycles = 4;
25868: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
25869: { uae_s8 data = m68k_dreg(regs, dstreg);
25870: { uae_u32 val = (uae_u8)data;
25871: cnt &= 63;
25872: retcycles = cnt;
25873: CLEAR_CZNV;
25874: if (cnt > 0) { uae_u32 hival;
25875: cnt &= 7;
25876: hival = val << (8 - cnt);
25877: val >>= cnt;
25878: val |= hival;
25879: val &= 0xff;
25880: SET_CFLG ((val & 0x80) >> 7);
25881: }
25882: SET_ZFLG (((uae_s8)(val)) == 0);
25883: SET_NFLG (((uae_s8)(val)) < 0);
25884: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
25885: }}}}m68k_incpc(2);
25886: return (6+retcycles*2);
25887: }
25888: unsigned long REGPARAM2 CPUFUNC(op_e040_0)(uae_u32 opcode) /* ASR */
25889: {
25890: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
25891: uae_u32 dstreg = opcode & 7;
25892: unsigned int retcycles = 0;
25893: OpcodeFamily = 64; CurrentInstrCycles = 4;
25894: {{ uae_u32 cnt = srcreg;
25895: { uae_s16 data = m68k_dreg(regs, dstreg);
25896: { uae_u32 val = (uae_u16)data;
25897: uae_u32 sign = (0x8000 & val) >> 15;
25898: cnt &= 63;
25899: retcycles = cnt;
25900: CLEAR_CZNV;
25901: if (cnt >= 16) {
25902: val = 0xffff & (uae_u32)-sign;
25903: SET_CFLG (sign);
25904: COPY_CARRY;
25905: } else {
25906: val >>= cnt - 1;
25907: SET_CFLG (val & 1);
25908: COPY_CARRY;
25909: val >>= 1;
25910: val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
25911: val &= 0xffff;
25912: }
25913: SET_ZFLG (((uae_s16)(val)) == 0);
25914: SET_NFLG (((uae_s16)(val)) < 0);
25915: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
25916: }}}}m68k_incpc(2);
25917: return (6+retcycles*2);
25918: }
25919: unsigned long REGPARAM2 CPUFUNC(op_e048_0)(uae_u32 opcode) /* LSR */
25920: {
25921: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
25922: uae_u32 dstreg = opcode & 7;
25923: unsigned int retcycles = 0;
25924: OpcodeFamily = 66; CurrentInstrCycles = 4;
25925: {{ uae_u32 cnt = srcreg;
25926: { uae_s16 data = m68k_dreg(regs, dstreg);
25927: { uae_u32 val = (uae_u16)data;
25928: cnt &= 63;
25929: retcycles = cnt;
25930: CLEAR_CZNV;
25931: if (cnt >= 16) {
25932: SET_CFLG ((cnt == 16) & (val >> 15));
25933: COPY_CARRY;
25934: val = 0;
25935: } else {
25936: val >>= cnt - 1;
25937: SET_CFLG (val & 1);
25938: COPY_CARRY;
25939: val >>= 1;
25940: }
25941: SET_ZFLG (((uae_s16)(val)) == 0);
25942: SET_NFLG (((uae_s16)(val)) < 0);
25943: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
25944: }}}}m68k_incpc(2);
25945: return (6+retcycles*2);
25946: }
25947: unsigned long REGPARAM2 CPUFUNC(op_e050_0)(uae_u32 opcode) /* ROXR */
25948: {
25949: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
25950: uae_u32 dstreg = opcode & 7;
25951: unsigned int retcycles = 0;
25952: OpcodeFamily = 71; CurrentInstrCycles = 4;
25953: {{ uae_u32 cnt = srcreg;
25954: { uae_s16 data = m68k_dreg(regs, dstreg);
25955: { uae_u32 val = (uae_u16)data;
25956: cnt &= 63;
25957: retcycles = cnt;
25958: CLEAR_CZNV;
25959: { cnt--;
25960: {
25961: uae_u32 carry;
25962: uae_u32 hival = (val << 1) | GET_XFLG;
25963: hival <<= (15 - cnt);
25964: val >>= cnt;
25965: carry = val & 1;
25966: val >>= 1;
25967: val |= hival;
25968: SET_XFLG (carry);
25969: val &= 0xffff;
25970: } }
25971: SET_CFLG (GET_XFLG);
25972: SET_ZFLG (((uae_s16)(val)) == 0);
25973: SET_NFLG (((uae_s16)(val)) < 0);
25974: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
25975: }}}}m68k_incpc(2);
25976: return (6+retcycles*2);
25977: }
25978: unsigned long REGPARAM2 CPUFUNC(op_e058_0)(uae_u32 opcode) /* ROR */
25979: {
25980: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
25981: uae_u32 dstreg = opcode & 7;
25982: unsigned int retcycles = 0;
25983: OpcodeFamily = 69; CurrentInstrCycles = 4;
25984: {{ uae_u32 cnt = srcreg;
25985: { uae_s16 data = m68k_dreg(regs, dstreg);
25986: { uae_u32 val = (uae_u16)data;
25987: cnt &= 63;
25988: retcycles = cnt;
25989: CLEAR_CZNV;
25990: { uae_u32 hival;
25991: cnt &= 15;
25992: hival = val << (16 - cnt);
25993: val >>= cnt;
25994: val |= hival;
25995: val &= 0xffff;
25996: SET_CFLG ((val & 0x8000) >> 15);
25997: }
25998: SET_ZFLG (((uae_s16)(val)) == 0);
25999: SET_NFLG (((uae_s16)(val)) < 0);
26000: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26001: }}}}m68k_incpc(2);
26002: return (6+retcycles*2);
26003: }
26004: unsigned long REGPARAM2 CPUFUNC(op_e060_0)(uae_u32 opcode) /* ASR */
26005: {
26006: uae_u32 srcreg = ((opcode >> 9) & 7);
26007: uae_u32 dstreg = opcode & 7;
26008: unsigned int retcycles = 0;
26009: OpcodeFamily = 64; CurrentInstrCycles = 4;
26010: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
26011: { uae_s16 data = m68k_dreg(regs, dstreg);
26012: { uae_u32 val = (uae_u16)data;
26013: uae_u32 sign = (0x8000 & val) >> 15;
26014: cnt &= 63;
26015: retcycles = cnt;
26016: CLEAR_CZNV;
26017: if (cnt >= 16) {
26018: val = 0xffff & (uae_u32)-sign;
26019: SET_CFLG (sign);
26020: COPY_CARRY;
26021: } else if (cnt > 0) {
26022: val >>= cnt - 1;
26023: SET_CFLG (val & 1);
26024: COPY_CARRY;
26025: val >>= 1;
26026: val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
26027: val &= 0xffff;
26028: }
26029: SET_ZFLG (((uae_s16)(val)) == 0);
26030: SET_NFLG (((uae_s16)(val)) < 0);
26031: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26032: }}}}m68k_incpc(2);
26033: return (6+retcycles*2);
26034: }
26035: unsigned long REGPARAM2 CPUFUNC(op_e068_0)(uae_u32 opcode) /* LSR */
26036: {
26037: uae_u32 srcreg = ((opcode >> 9) & 7);
26038: uae_u32 dstreg = opcode & 7;
26039: unsigned int retcycles = 0;
26040: OpcodeFamily = 66; CurrentInstrCycles = 4;
26041: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
26042: { uae_s16 data = m68k_dreg(regs, dstreg);
26043: { uae_u32 val = (uae_u16)data;
26044: cnt &= 63;
26045: retcycles = cnt;
26046: CLEAR_CZNV;
26047: if (cnt >= 16) {
26048: SET_CFLG ((cnt == 16) & (val >> 15));
26049: COPY_CARRY;
26050: val = 0;
26051: } else if (cnt > 0) {
26052: val >>= cnt - 1;
26053: SET_CFLG (val & 1);
26054: COPY_CARRY;
26055: val >>= 1;
26056: }
26057: SET_ZFLG (((uae_s16)(val)) == 0);
26058: SET_NFLG (((uae_s16)(val)) < 0);
26059: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26060: }}}}m68k_incpc(2);
26061: return (6+retcycles*2);
26062: }
26063: unsigned long REGPARAM2 CPUFUNC(op_e070_0)(uae_u32 opcode) /* ROXR */
26064: {
26065: uae_u32 srcreg = ((opcode >> 9) & 7);
26066: uae_u32 dstreg = opcode & 7;
26067: unsigned int retcycles = 0;
26068: OpcodeFamily = 71; CurrentInstrCycles = 4;
26069: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
26070: { uae_s16 data = m68k_dreg(regs, dstreg);
26071: { uae_u32 val = (uae_u16)data;
26072: cnt &= 63;
26073: retcycles = cnt;
26074: CLEAR_CZNV;
26075: if (cnt >= 34) cnt -= 34;
26076: if (cnt >= 17) cnt -= 17;
26077: if (cnt > 0) {
26078: cnt--;
26079: {
26080: uae_u32 carry;
26081: uae_u32 hival = (val << 1) | GET_XFLG;
26082: hival <<= (15 - cnt);
26083: val >>= cnt;
26084: carry = val & 1;
26085: val >>= 1;
26086: val |= hival;
26087: SET_XFLG (carry);
26088: val &= 0xffff;
26089: } }
26090: SET_CFLG (GET_XFLG);
26091: SET_ZFLG (((uae_s16)(val)) == 0);
26092: SET_NFLG (((uae_s16)(val)) < 0);
26093: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26094: }}}}m68k_incpc(2);
26095: return (6+retcycles*2);
26096: }
26097: unsigned long REGPARAM2 CPUFUNC(op_e078_0)(uae_u32 opcode) /* ROR */
26098: {
26099: uae_u32 srcreg = ((opcode >> 9) & 7);
26100: uae_u32 dstreg = opcode & 7;
26101: unsigned int retcycles = 0;
26102: OpcodeFamily = 69; CurrentInstrCycles = 4;
26103: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
26104: { uae_s16 data = m68k_dreg(regs, dstreg);
26105: { uae_u32 val = (uae_u16)data;
26106: cnt &= 63;
26107: retcycles = cnt;
26108: CLEAR_CZNV;
26109: if (cnt > 0) { uae_u32 hival;
26110: cnt &= 15;
26111: hival = val << (16 - cnt);
26112: val >>= cnt;
26113: val |= hival;
26114: val &= 0xffff;
26115: SET_CFLG ((val & 0x8000) >> 15);
26116: }
26117: SET_ZFLG (((uae_s16)(val)) == 0);
26118: SET_NFLG (((uae_s16)(val)) < 0);
26119: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26120: }}}}m68k_incpc(2);
26121: return (6+retcycles*2);
26122: }
26123: unsigned long REGPARAM2 CPUFUNC(op_e080_0)(uae_u32 opcode) /* ASR */
26124: {
26125: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26126: uae_u32 dstreg = opcode & 7;
26127: unsigned int retcycles = 0;
26128: OpcodeFamily = 64; CurrentInstrCycles = 4;
26129: {{ uae_u32 cnt = srcreg;
26130: { uae_s32 data = m68k_dreg(regs, dstreg);
26131: { uae_u32 val = data;
26132: uae_u32 sign = (0x80000000 & val) >> 31;
26133: cnt &= 63;
26134: retcycles = cnt;
26135: CLEAR_CZNV;
26136: if (cnt >= 32) {
26137: val = 0xffffffff & (uae_u32)-sign;
26138: SET_CFLG (sign);
26139: COPY_CARRY;
26140: } else {
26141: val >>= cnt - 1;
26142: SET_CFLG (val & 1);
26143: COPY_CARRY;
26144: val >>= 1;
26145: val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
26146: val &= 0xffffffff;
26147: }
26148: SET_ZFLG (((uae_s32)(val)) == 0);
26149: SET_NFLG (((uae_s32)(val)) < 0);
26150: m68k_dreg(regs, dstreg) = (val);
26151: }}}}m68k_incpc(2);
26152: return (8+retcycles*2);
26153: }
26154: unsigned long REGPARAM2 CPUFUNC(op_e088_0)(uae_u32 opcode) /* LSR */
26155: {
26156: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26157: uae_u32 dstreg = opcode & 7;
26158: unsigned int retcycles = 0;
26159: OpcodeFamily = 66; CurrentInstrCycles = 4;
26160: {{ uae_u32 cnt = srcreg;
26161: { uae_s32 data = m68k_dreg(regs, dstreg);
26162: { uae_u32 val = data;
26163: cnt &= 63;
26164: retcycles = cnt;
26165: CLEAR_CZNV;
26166: if (cnt >= 32) {
26167: SET_CFLG ((cnt == 32) & (val >> 31));
26168: COPY_CARRY;
26169: val = 0;
26170: } else {
26171: val >>= cnt - 1;
26172: SET_CFLG (val & 1);
26173: COPY_CARRY;
26174: val >>= 1;
26175: }
26176: SET_ZFLG (((uae_s32)(val)) == 0);
26177: SET_NFLG (((uae_s32)(val)) < 0);
26178: m68k_dreg(regs, dstreg) = (val);
26179: }}}}m68k_incpc(2);
26180: return (8+retcycles*2);
26181: }
26182: unsigned long REGPARAM2 CPUFUNC(op_e090_0)(uae_u32 opcode) /* ROXR */
26183: {
26184: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26185: uae_u32 dstreg = opcode & 7;
26186: unsigned int retcycles = 0;
26187: OpcodeFamily = 71; CurrentInstrCycles = 4;
26188: {{ uae_u32 cnt = srcreg;
26189: { uae_s32 data = m68k_dreg(regs, dstreg);
26190: { uae_u32 val = data;
26191: cnt &= 63;
26192: retcycles = cnt;
26193: CLEAR_CZNV;
26194: { cnt--;
26195: {
26196: uae_u32 carry;
26197: uae_u32 hival = (val << 1) | GET_XFLG;
26198: hival <<= (31 - cnt);
26199: val >>= cnt;
26200: carry = val & 1;
26201: val >>= 1;
26202: val |= hival;
26203: SET_XFLG (carry);
26204: val &= 0xffffffff;
26205: } }
26206: SET_CFLG (GET_XFLG);
26207: SET_ZFLG (((uae_s32)(val)) == 0);
26208: SET_NFLG (((uae_s32)(val)) < 0);
26209: m68k_dreg(regs, dstreg) = (val);
26210: }}}}m68k_incpc(2);
26211: return (8+retcycles*2);
26212: }
26213: unsigned long REGPARAM2 CPUFUNC(op_e098_0)(uae_u32 opcode) /* ROR */
26214: {
26215: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26216: uae_u32 dstreg = opcode & 7;
26217: unsigned int retcycles = 0;
26218: OpcodeFamily = 69; CurrentInstrCycles = 4;
26219: {{ uae_u32 cnt = srcreg;
26220: { uae_s32 data = m68k_dreg(regs, dstreg);
26221: { uae_u32 val = data;
26222: cnt &= 63;
26223: retcycles = cnt;
26224: CLEAR_CZNV;
26225: { uae_u32 hival;
26226: cnt &= 31;
26227: hival = val << (32 - cnt);
26228: val >>= cnt;
26229: val |= hival;
26230: val &= 0xffffffff;
26231: SET_CFLG ((val & 0x80000000) >> 31);
26232: }
26233: SET_ZFLG (((uae_s32)(val)) == 0);
26234: SET_NFLG (((uae_s32)(val)) < 0);
26235: m68k_dreg(regs, dstreg) = (val);
26236: }}}}m68k_incpc(2);
26237: return (8+retcycles*2);
26238: }
26239: unsigned long REGPARAM2 CPUFUNC(op_e0a0_0)(uae_u32 opcode) /* ASR */
26240: {
26241: uae_u32 srcreg = ((opcode >> 9) & 7);
26242: uae_u32 dstreg = opcode & 7;
26243: unsigned int retcycles = 0;
26244: OpcodeFamily = 64; CurrentInstrCycles = 4;
26245: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
26246: { uae_s32 data = m68k_dreg(regs, dstreg);
26247: { uae_u32 val = data;
26248: uae_u32 sign = (0x80000000 & val) >> 31;
26249: cnt &= 63;
26250: retcycles = cnt;
26251: CLEAR_CZNV;
26252: if (cnt >= 32) {
26253: val = 0xffffffff & (uae_u32)-sign;
26254: SET_CFLG (sign);
26255: COPY_CARRY;
26256: } else if (cnt > 0) {
26257: val >>= cnt - 1;
26258: SET_CFLG (val & 1);
26259: COPY_CARRY;
26260: val >>= 1;
26261: val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
26262: val &= 0xffffffff;
26263: }
26264: SET_ZFLG (((uae_s32)(val)) == 0);
26265: SET_NFLG (((uae_s32)(val)) < 0);
26266: m68k_dreg(regs, dstreg) = (val);
26267: }}}}m68k_incpc(2);
26268: return (8+retcycles*2);
26269: }
26270: unsigned long REGPARAM2 CPUFUNC(op_e0a8_0)(uae_u32 opcode) /* LSR */
26271: {
26272: uae_u32 srcreg = ((opcode >> 9) & 7);
26273: uae_u32 dstreg = opcode & 7;
26274: unsigned int retcycles = 0;
26275: OpcodeFamily = 66; CurrentInstrCycles = 4;
26276: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
26277: { uae_s32 data = m68k_dreg(regs, dstreg);
26278: { uae_u32 val = data;
26279: cnt &= 63;
26280: retcycles = cnt;
26281: CLEAR_CZNV;
26282: if (cnt >= 32) {
26283: SET_CFLG ((cnt == 32) & (val >> 31));
26284: COPY_CARRY;
26285: val = 0;
26286: } else if (cnt > 0) {
26287: val >>= cnt - 1;
26288: SET_CFLG (val & 1);
26289: COPY_CARRY;
26290: val >>= 1;
26291: }
26292: SET_ZFLG (((uae_s32)(val)) == 0);
26293: SET_NFLG (((uae_s32)(val)) < 0);
26294: m68k_dreg(regs, dstreg) = (val);
26295: }}}}m68k_incpc(2);
26296: return (8+retcycles*2);
26297: }
26298: unsigned long REGPARAM2 CPUFUNC(op_e0b0_0)(uae_u32 opcode) /* ROXR */
26299: {
26300: uae_u32 srcreg = ((opcode >> 9) & 7);
26301: uae_u32 dstreg = opcode & 7;
26302: unsigned int retcycles = 0;
26303: OpcodeFamily = 71; CurrentInstrCycles = 4;
26304: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
26305: { uae_s32 data = m68k_dreg(regs, dstreg);
26306: { uae_u32 val = data;
26307: cnt &= 63;
26308: retcycles = cnt;
26309: CLEAR_CZNV;
26310: if (cnt >= 33) cnt -= 33;
26311: if (cnt > 0) {
26312: cnt--;
26313: {
26314: uae_u32 carry;
26315: uae_u32 hival = (val << 1) | GET_XFLG;
26316: hival <<= (31 - cnt);
26317: val >>= cnt;
26318: carry = val & 1;
26319: val >>= 1;
26320: val |= hival;
26321: SET_XFLG (carry);
26322: val &= 0xffffffff;
26323: } }
26324: SET_CFLG (GET_XFLG);
26325: SET_ZFLG (((uae_s32)(val)) == 0);
26326: SET_NFLG (((uae_s32)(val)) < 0);
26327: m68k_dreg(regs, dstreg) = (val);
26328: }}}}m68k_incpc(2);
26329: return (8+retcycles*2);
26330: }
26331: unsigned long REGPARAM2 CPUFUNC(op_e0b8_0)(uae_u32 opcode) /* ROR */
26332: {
26333: uae_u32 srcreg = ((opcode >> 9) & 7);
26334: uae_u32 dstreg = opcode & 7;
26335: unsigned int retcycles = 0;
26336: OpcodeFamily = 69; CurrentInstrCycles = 4;
26337: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
26338: { uae_s32 data = m68k_dreg(regs, dstreg);
26339: { uae_u32 val = data;
26340: cnt &= 63;
26341: retcycles = cnt;
26342: CLEAR_CZNV;
26343: if (cnt > 0) { uae_u32 hival;
26344: cnt &= 31;
26345: hival = val << (32 - cnt);
26346: val >>= cnt;
26347: val |= hival;
26348: val &= 0xffffffff;
26349: SET_CFLG ((val & 0x80000000) >> 31);
26350: }
26351: SET_ZFLG (((uae_s32)(val)) == 0);
26352: SET_NFLG (((uae_s32)(val)) < 0);
26353: m68k_dreg(regs, dstreg) = (val);
26354: }}}}m68k_incpc(2);
26355: return (8+retcycles*2);
26356: }
26357: unsigned long REGPARAM2 CPUFUNC(op_e0d0_0)(uae_u32 opcode) /* ASRW */
26358: {
26359: uae_u32 srcreg = (opcode & 7);
26360: OpcodeFamily = 72; CurrentInstrCycles = 12;
26361: {{ uaecptr dataa = m68k_areg(regs, srcreg);
26362: { uae_s16 data = get_word(dataa);
26363: { uae_u32 val = (uae_u16)data;
26364: uae_u32 sign = 0x8000 & val;
26365: uae_u32 cflg = val & 1;
26366: val = (val >> 1) | sign;
26367: CLEAR_CZNV;
26368: SET_ZFLG (((uae_s16)(val)) == 0);
26369: SET_NFLG (((uae_s16)(val)) < 0);
26370: SET_CFLG (cflg);
26371: COPY_CARRY;
26372: put_word(dataa,val);
26373: }}}}m68k_incpc(2);
26374: return 12;
26375: }
26376: unsigned long REGPARAM2 CPUFUNC(op_e0d8_0)(uae_u32 opcode) /* ASRW */
26377: {
26378: uae_u32 srcreg = (opcode & 7);
26379: OpcodeFamily = 72; CurrentInstrCycles = 12;
26380: {{ uaecptr dataa = m68k_areg(regs, srcreg);
26381: { uae_s16 data = get_word(dataa);
26382: m68k_areg(regs, srcreg) += 2;
26383: { uae_u32 val = (uae_u16)data;
26384: uae_u32 sign = 0x8000 & val;
26385: uae_u32 cflg = val & 1;
26386: val = (val >> 1) | sign;
26387: CLEAR_CZNV;
26388: SET_ZFLG (((uae_s16)(val)) == 0);
26389: SET_NFLG (((uae_s16)(val)) < 0);
26390: SET_CFLG (cflg);
26391: COPY_CARRY;
26392: put_word(dataa,val);
26393: }}}}m68k_incpc(2);
26394: return 12;
26395: }
26396: unsigned long REGPARAM2 CPUFUNC(op_e0e0_0)(uae_u32 opcode) /* ASRW */
26397: {
26398: uae_u32 srcreg = (opcode & 7);
26399: OpcodeFamily = 72; CurrentInstrCycles = 14;
26400: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
26401: { uae_s16 data = get_word(dataa);
26402: m68k_areg (regs, srcreg) = dataa;
26403: { uae_u32 val = (uae_u16)data;
26404: uae_u32 sign = 0x8000 & val;
26405: uae_u32 cflg = val & 1;
26406: val = (val >> 1) | sign;
26407: CLEAR_CZNV;
26408: SET_ZFLG (((uae_s16)(val)) == 0);
26409: SET_NFLG (((uae_s16)(val)) < 0);
26410: SET_CFLG (cflg);
26411: COPY_CARRY;
26412: put_word(dataa,val);
26413: }}}}m68k_incpc(2);
26414: return 14;
26415: }
26416: unsigned long REGPARAM2 CPUFUNC(op_e0e8_0)(uae_u32 opcode) /* ASRW */
26417: {
26418: uae_u32 srcreg = (opcode & 7);
26419: OpcodeFamily = 72; CurrentInstrCycles = 16;
26420: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
26421: { uae_s16 data = get_word(dataa);
26422: { uae_u32 val = (uae_u16)data;
26423: uae_u32 sign = 0x8000 & val;
26424: uae_u32 cflg = val & 1;
26425: val = (val >> 1) | sign;
26426: CLEAR_CZNV;
26427: SET_ZFLG (((uae_s16)(val)) == 0);
26428: SET_NFLG (((uae_s16)(val)) < 0);
26429: SET_CFLG (cflg);
26430: COPY_CARRY;
26431: put_word(dataa,val);
26432: }}}}m68k_incpc(4);
26433: return 16;
26434: }
26435: unsigned long REGPARAM2 CPUFUNC(op_e0f0_0)(uae_u32 opcode) /* ASRW */
26436: {
26437: uae_u32 srcreg = (opcode & 7);
26438: OpcodeFamily = 72; CurrentInstrCycles = 18;
26439: {{m68k_incpc(2);
26440: { uaecptr dataa = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
26441: BusCyclePenalty += 2;
26442: { uae_s16 data = get_word(dataa);
26443: { uae_u32 val = (uae_u16)data;
26444: uae_u32 sign = 0x8000 & val;
26445: uae_u32 cflg = val & 1;
26446: val = (val >> 1) | sign;
26447: CLEAR_CZNV;
26448: SET_ZFLG (((uae_s16)(val)) == 0);
26449: SET_NFLG (((uae_s16)(val)) < 0);
26450: SET_CFLG (cflg);
26451: COPY_CARRY;
26452: put_word(dataa,val);
26453: }}}}}return 18;
26454: }
26455: unsigned long REGPARAM2 CPUFUNC(op_e0f8_0)(uae_u32 opcode) /* ASRW */
26456: {
26457: OpcodeFamily = 72; CurrentInstrCycles = 16;
26458: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword(2);
26459: { uae_s16 data = get_word(dataa);
26460: { uae_u32 val = (uae_u16)data;
26461: uae_u32 sign = 0x8000 & val;
26462: uae_u32 cflg = val & 1;
26463: val = (val >> 1) | sign;
26464: CLEAR_CZNV;
26465: SET_ZFLG (((uae_s16)(val)) == 0);
26466: SET_NFLG (((uae_s16)(val)) < 0);
26467: SET_CFLG (cflg);
26468: COPY_CARRY;
26469: put_word(dataa,val);
26470: }}}}m68k_incpc(4);
26471: return 16;
26472: }
26473: unsigned long REGPARAM2 CPUFUNC(op_e0f9_0)(uae_u32 opcode) /* ASRW */
26474: {
26475: OpcodeFamily = 72; CurrentInstrCycles = 20;
26476: {{ uaecptr dataa = get_ilong(2);
26477: { uae_s16 data = get_word(dataa);
26478: { uae_u32 val = (uae_u16)data;
26479: uae_u32 sign = 0x8000 & val;
26480: uae_u32 cflg = val & 1;
26481: val = (val >> 1) | sign;
26482: CLEAR_CZNV;
26483: SET_ZFLG (((uae_s16)(val)) == 0);
26484: SET_NFLG (((uae_s16)(val)) < 0);
26485: SET_CFLG (cflg);
26486: COPY_CARRY;
26487: put_word(dataa,val);
26488: }}}}m68k_incpc(6);
26489: return 20;
26490: }
26491: unsigned long REGPARAM2 CPUFUNC(op_e100_0)(uae_u32 opcode) /* ASL */
26492: {
26493: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26494: uae_u32 dstreg = opcode & 7;
26495: unsigned int retcycles = 0;
26496: OpcodeFamily = 65; CurrentInstrCycles = 4;
26497: {{ uae_u32 cnt = srcreg;
26498: { uae_s8 data = m68k_dreg(regs, dstreg);
26499: { uae_u32 val = (uae_u8)data;
26500: cnt &= 63;
26501: retcycles = cnt;
26502: CLEAR_CZNV;
26503: if (cnt >= 8) {
26504: SET_VFLG (val != 0);
26505: SET_CFLG (cnt == 8 ? val & 1 : 0);
26506: COPY_CARRY;
26507: val = 0;
26508: } else {
26509: uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
26510: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
26511: val <<= cnt - 1;
26512: SET_CFLG ((val & 0x80) >> 7);
26513: COPY_CARRY;
26514: val <<= 1;
26515: val &= 0xff;
26516: }
26517: SET_ZFLG (((uae_s8)(val)) == 0);
26518: SET_NFLG (((uae_s8)(val)) < 0);
26519: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
26520: }}}}m68k_incpc(2);
26521: return (6+retcycles*2);
26522: }
26523: unsigned long REGPARAM2 CPUFUNC(op_e108_0)(uae_u32 opcode) /* LSL */
26524: {
26525: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26526: uae_u32 dstreg = opcode & 7;
26527: unsigned int retcycles = 0;
26528: OpcodeFamily = 67; CurrentInstrCycles = 4;
26529: {{ uae_u32 cnt = srcreg;
26530: { uae_s8 data = m68k_dreg(regs, dstreg);
26531: { uae_u32 val = (uae_u8)data;
26532: cnt &= 63;
26533: retcycles = cnt;
26534: CLEAR_CZNV;
26535: if (cnt >= 8) {
26536: SET_CFLG (cnt == 8 ? val & 1 : 0);
26537: COPY_CARRY;
26538: val = 0;
26539: } else {
26540: val <<= (cnt - 1);
26541: SET_CFLG ((val & 0x80) >> 7);
26542: COPY_CARRY;
26543: val <<= 1;
26544: val &= 0xff;
26545: }
26546: SET_ZFLG (((uae_s8)(val)) == 0);
26547: SET_NFLG (((uae_s8)(val)) < 0);
26548: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
26549: }}}}m68k_incpc(2);
26550: return (6+retcycles*2);
26551: }
26552: unsigned long REGPARAM2 CPUFUNC(op_e110_0)(uae_u32 opcode) /* ROXL */
26553: {
26554: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26555: uae_u32 dstreg = opcode & 7;
26556: unsigned int retcycles = 0;
26557: OpcodeFamily = 70; CurrentInstrCycles = 4;
26558: {{ uae_u32 cnt = srcreg;
26559: { uae_s8 data = m68k_dreg(regs, dstreg);
26560: { uae_u32 val = (uae_u8)data;
26561: cnt &= 63;
26562: retcycles = cnt;
26563: CLEAR_CZNV;
26564: { cnt--;
26565: {
26566: uae_u32 carry;
26567: uae_u32 loval = val >> (7 - cnt);
26568: carry = loval & 1;
26569: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
26570: SET_XFLG (carry);
26571: val &= 0xff;
26572: } }
26573: SET_CFLG (GET_XFLG);
26574: SET_ZFLG (((uae_s8)(val)) == 0);
26575: SET_NFLG (((uae_s8)(val)) < 0);
26576: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
26577: }}}}m68k_incpc(2);
26578: return (6+retcycles*2);
26579: }
26580: unsigned long REGPARAM2 CPUFUNC(op_e118_0)(uae_u32 opcode) /* ROL */
26581: {
26582: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26583: uae_u32 dstreg = opcode & 7;
26584: unsigned int retcycles = 0;
26585: OpcodeFamily = 68; CurrentInstrCycles = 4;
26586: {{ uae_u32 cnt = srcreg;
26587: { uae_s8 data = m68k_dreg(regs, dstreg);
26588: { uae_u32 val = (uae_u8)data;
26589: cnt &= 63;
26590: retcycles = cnt;
26591: CLEAR_CZNV;
26592: { uae_u32 loval;
26593: cnt &= 7;
26594: loval = val >> (8 - cnt);
26595: val <<= cnt;
26596: val |= loval;
26597: val &= 0xff;
26598: SET_CFLG (val & 1);
26599: }
26600: SET_ZFLG (((uae_s8)(val)) == 0);
26601: SET_NFLG (((uae_s8)(val)) < 0);
26602: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
26603: }}}}m68k_incpc(2);
26604: return (6+retcycles*2);
26605: }
26606: unsigned long REGPARAM2 CPUFUNC(op_e120_0)(uae_u32 opcode) /* ASL */
26607: {
26608: uae_u32 srcreg = ((opcode >> 9) & 7);
26609: uae_u32 dstreg = opcode & 7;
26610: unsigned int retcycles = 0;
26611: OpcodeFamily = 65; CurrentInstrCycles = 4;
26612: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
26613: { uae_s8 data = m68k_dreg(regs, dstreg);
26614: { uae_u32 val = (uae_u8)data;
26615: cnt &= 63;
26616: retcycles = cnt;
26617: CLEAR_CZNV;
26618: if (cnt >= 8) {
26619: SET_VFLG (val != 0);
26620: SET_CFLG (cnt == 8 ? val & 1 : 0);
26621: COPY_CARRY;
26622: val = 0;
26623: } else if (cnt > 0) {
26624: uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
26625: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
26626: val <<= cnt - 1;
26627: SET_CFLG ((val & 0x80) >> 7);
26628: COPY_CARRY;
26629: val <<= 1;
26630: val &= 0xff;
26631: }
26632: SET_ZFLG (((uae_s8)(val)) == 0);
26633: SET_NFLG (((uae_s8)(val)) < 0);
26634: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
26635: }}}}m68k_incpc(2);
26636: return (6+retcycles*2);
26637: }
26638: unsigned long REGPARAM2 CPUFUNC(op_e128_0)(uae_u32 opcode) /* LSL */
26639: {
26640: uae_u32 srcreg = ((opcode >> 9) & 7);
26641: uae_u32 dstreg = opcode & 7;
26642: unsigned int retcycles = 0;
26643: OpcodeFamily = 67; CurrentInstrCycles = 4;
26644: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
26645: { uae_s8 data = m68k_dreg(regs, dstreg);
26646: { uae_u32 val = (uae_u8)data;
26647: cnt &= 63;
26648: retcycles = cnt;
26649: CLEAR_CZNV;
26650: if (cnt >= 8) {
26651: SET_CFLG (cnt == 8 ? val & 1 : 0);
26652: COPY_CARRY;
26653: val = 0;
26654: } else if (cnt > 0) {
26655: val <<= (cnt - 1);
26656: SET_CFLG ((val & 0x80) >> 7);
26657: COPY_CARRY;
26658: val <<= 1;
26659: val &= 0xff;
26660: }
26661: SET_ZFLG (((uae_s8)(val)) == 0);
26662: SET_NFLG (((uae_s8)(val)) < 0);
26663: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
26664: }}}}m68k_incpc(2);
26665: return (6+retcycles*2);
26666: }
26667: unsigned long REGPARAM2 CPUFUNC(op_e130_0)(uae_u32 opcode) /* ROXL */
26668: {
26669: uae_u32 srcreg = ((opcode >> 9) & 7);
26670: uae_u32 dstreg = opcode & 7;
26671: unsigned int retcycles = 0;
26672: OpcodeFamily = 70; CurrentInstrCycles = 4;
26673: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
26674: { uae_s8 data = m68k_dreg(regs, dstreg);
26675: { uae_u32 val = (uae_u8)data;
26676: cnt &= 63;
26677: retcycles = cnt;
26678: CLEAR_CZNV;
26679: if (cnt >= 36) cnt -= 36;
26680: if (cnt >= 18) cnt -= 18;
26681: if (cnt >= 9) cnt -= 9;
26682: if (cnt > 0) {
26683: cnt--;
26684: {
26685: uae_u32 carry;
26686: uae_u32 loval = val >> (7 - cnt);
26687: carry = loval & 1;
26688: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
26689: SET_XFLG (carry);
26690: val &= 0xff;
26691: } }
26692: SET_CFLG (GET_XFLG);
26693: SET_ZFLG (((uae_s8)(val)) == 0);
26694: SET_NFLG (((uae_s8)(val)) < 0);
26695: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
26696: }}}}m68k_incpc(2);
26697: return (6+retcycles*2);
26698: }
26699: unsigned long REGPARAM2 CPUFUNC(op_e138_0)(uae_u32 opcode) /* ROL */
26700: {
26701: uae_u32 srcreg = ((opcode >> 9) & 7);
26702: uae_u32 dstreg = opcode & 7;
26703: unsigned int retcycles = 0;
26704: OpcodeFamily = 68; CurrentInstrCycles = 4;
26705: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
26706: { uae_s8 data = m68k_dreg(regs, dstreg);
26707: { uae_u32 val = (uae_u8)data;
26708: cnt &= 63;
26709: retcycles = cnt;
26710: CLEAR_CZNV;
26711: if (cnt > 0) {
26712: uae_u32 loval;
26713: cnt &= 7;
26714: loval = val >> (8 - cnt);
26715: val <<= cnt;
26716: val |= loval;
26717: val &= 0xff;
26718: SET_CFLG (val & 1);
26719: }
26720: SET_ZFLG (((uae_s8)(val)) == 0);
26721: SET_NFLG (((uae_s8)(val)) < 0);
26722: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
26723: }}}}m68k_incpc(2);
26724: return (6+retcycles*2);
26725: }
26726: unsigned long REGPARAM2 CPUFUNC(op_e140_0)(uae_u32 opcode) /* ASL */
26727: {
26728: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26729: uae_u32 dstreg = opcode & 7;
26730: unsigned int retcycles = 0;
26731: OpcodeFamily = 65; CurrentInstrCycles = 4;
26732: {{ uae_u32 cnt = srcreg;
26733: { uae_s16 data = m68k_dreg(regs, dstreg);
26734: { uae_u32 val = (uae_u16)data;
26735: cnt &= 63;
26736: retcycles = cnt;
26737: CLEAR_CZNV;
26738: if (cnt >= 16) {
26739: SET_VFLG (val != 0);
26740: SET_CFLG (cnt == 16 ? val & 1 : 0);
26741: COPY_CARRY;
26742: val = 0;
26743: } else {
26744: uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
26745: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
26746: val <<= cnt - 1;
26747: SET_CFLG ((val & 0x8000) >> 15);
26748: COPY_CARRY;
26749: val <<= 1;
26750: val &= 0xffff;
26751: }
26752: SET_ZFLG (((uae_s16)(val)) == 0);
26753: SET_NFLG (((uae_s16)(val)) < 0);
26754: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26755: }}}}m68k_incpc(2);
26756: return (6+retcycles*2);
26757: }
26758: unsigned long REGPARAM2 CPUFUNC(op_e148_0)(uae_u32 opcode) /* LSL */
26759: {
26760: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26761: uae_u32 dstreg = opcode & 7;
26762: unsigned int retcycles = 0;
26763: OpcodeFamily = 67; CurrentInstrCycles = 4;
26764: {{ uae_u32 cnt = srcreg;
26765: { uae_s16 data = m68k_dreg(regs, dstreg);
26766: { uae_u32 val = (uae_u16)data;
26767: cnt &= 63;
26768: retcycles = cnt;
26769: CLEAR_CZNV;
26770: if (cnt >= 16) {
26771: SET_CFLG (cnt == 16 ? val & 1 : 0);
26772: COPY_CARRY;
26773: val = 0;
26774: } else {
26775: val <<= (cnt - 1);
26776: SET_CFLG ((val & 0x8000) >> 15);
26777: COPY_CARRY;
26778: val <<= 1;
26779: val &= 0xffff;
26780: }
26781: SET_ZFLG (((uae_s16)(val)) == 0);
26782: SET_NFLG (((uae_s16)(val)) < 0);
26783: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26784: }}}}m68k_incpc(2);
26785: return (6+retcycles*2);
26786: }
26787: unsigned long REGPARAM2 CPUFUNC(op_e150_0)(uae_u32 opcode) /* ROXL */
26788: {
26789: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26790: uae_u32 dstreg = opcode & 7;
26791: unsigned int retcycles = 0;
26792: OpcodeFamily = 70; CurrentInstrCycles = 4;
26793: {{ uae_u32 cnt = srcreg;
26794: { uae_s16 data = m68k_dreg(regs, dstreg);
26795: { uae_u32 val = (uae_u16)data;
26796: cnt &= 63;
26797: retcycles = cnt;
26798: CLEAR_CZNV;
26799: { cnt--;
26800: {
26801: uae_u32 carry;
26802: uae_u32 loval = val >> (15 - cnt);
26803: carry = loval & 1;
26804: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
26805: SET_XFLG (carry);
26806: val &= 0xffff;
26807: } }
26808: SET_CFLG (GET_XFLG);
26809: SET_ZFLG (((uae_s16)(val)) == 0);
26810: SET_NFLG (((uae_s16)(val)) < 0);
26811: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26812: }}}}m68k_incpc(2);
26813: return (6+retcycles*2);
26814: }
26815: unsigned long REGPARAM2 CPUFUNC(op_e158_0)(uae_u32 opcode) /* ROL */
26816: {
26817: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26818: uae_u32 dstreg = opcode & 7;
26819: unsigned int retcycles = 0;
26820: OpcodeFamily = 68; CurrentInstrCycles = 4;
26821: {{ uae_u32 cnt = srcreg;
26822: { uae_s16 data = m68k_dreg(regs, dstreg);
26823: { uae_u32 val = (uae_u16)data;
26824: cnt &= 63;
26825: retcycles = cnt;
26826: CLEAR_CZNV;
26827: { uae_u32 loval;
26828: cnt &= 15;
26829: loval = val >> (16 - cnt);
26830: val <<= cnt;
26831: val |= loval;
26832: val &= 0xffff;
26833: SET_CFLG (val & 1);
26834: }
26835: SET_ZFLG (((uae_s16)(val)) == 0);
26836: SET_NFLG (((uae_s16)(val)) < 0);
26837: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26838: }}}}m68k_incpc(2);
26839: return (6+retcycles*2);
26840: }
26841: unsigned long REGPARAM2 CPUFUNC(op_e160_0)(uae_u32 opcode) /* ASL */
26842: {
26843: uae_u32 srcreg = ((opcode >> 9) & 7);
26844: uae_u32 dstreg = opcode & 7;
26845: unsigned int retcycles = 0;
26846: OpcodeFamily = 65; CurrentInstrCycles = 4;
26847: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
26848: { uae_s16 data = m68k_dreg(regs, dstreg);
26849: { uae_u32 val = (uae_u16)data;
26850: cnt &= 63;
26851: retcycles = cnt;
26852: CLEAR_CZNV;
26853: if (cnt >= 16) {
26854: SET_VFLG (val != 0);
26855: SET_CFLG (cnt == 16 ? val & 1 : 0);
26856: COPY_CARRY;
26857: val = 0;
26858: } else if (cnt > 0) {
26859: uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
26860: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
26861: val <<= cnt - 1;
26862: SET_CFLG ((val & 0x8000) >> 15);
26863: COPY_CARRY;
26864: val <<= 1;
26865: val &= 0xffff;
26866: }
26867: SET_ZFLG (((uae_s16)(val)) == 0);
26868: SET_NFLG (((uae_s16)(val)) < 0);
26869: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26870: }}}}m68k_incpc(2);
26871: return (6+retcycles*2);
26872: }
26873: unsigned long REGPARAM2 CPUFUNC(op_e168_0)(uae_u32 opcode) /* LSL */
26874: {
26875: uae_u32 srcreg = ((opcode >> 9) & 7);
26876: uae_u32 dstreg = opcode & 7;
26877: unsigned int retcycles = 0;
26878: OpcodeFamily = 67; CurrentInstrCycles = 4;
26879: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
26880: { uae_s16 data = m68k_dreg(regs, dstreg);
26881: { uae_u32 val = (uae_u16)data;
26882: cnt &= 63;
26883: retcycles = cnt;
26884: CLEAR_CZNV;
26885: if (cnt >= 16) {
26886: SET_CFLG (cnt == 16 ? val & 1 : 0);
26887: COPY_CARRY;
26888: val = 0;
26889: } else if (cnt > 0) {
26890: val <<= (cnt - 1);
26891: SET_CFLG ((val & 0x8000) >> 15);
26892: COPY_CARRY;
26893: val <<= 1;
26894: val &= 0xffff;
26895: }
26896: SET_ZFLG (((uae_s16)(val)) == 0);
26897: SET_NFLG (((uae_s16)(val)) < 0);
26898: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26899: }}}}m68k_incpc(2);
26900: return (6+retcycles*2);
26901: }
26902: unsigned long REGPARAM2 CPUFUNC(op_e170_0)(uae_u32 opcode) /* ROXL */
26903: {
26904: uae_u32 srcreg = ((opcode >> 9) & 7);
26905: uae_u32 dstreg = opcode & 7;
26906: unsigned int retcycles = 0;
26907: OpcodeFamily = 70; CurrentInstrCycles = 4;
26908: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
26909: { uae_s16 data = m68k_dreg(regs, dstreg);
26910: { uae_u32 val = (uae_u16)data;
26911: cnt &= 63;
26912: retcycles = cnt;
26913: CLEAR_CZNV;
26914: if (cnt >= 34) cnt -= 34;
26915: if (cnt >= 17) cnt -= 17;
26916: if (cnt > 0) {
26917: cnt--;
26918: {
26919: uae_u32 carry;
26920: uae_u32 loval = val >> (15 - cnt);
26921: carry = loval & 1;
26922: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
26923: SET_XFLG (carry);
26924: val &= 0xffff;
26925: } }
26926: SET_CFLG (GET_XFLG);
26927: SET_ZFLG (((uae_s16)(val)) == 0);
26928: SET_NFLG (((uae_s16)(val)) < 0);
26929: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26930: }}}}m68k_incpc(2);
26931: return (6+retcycles*2);
26932: }
26933: unsigned long REGPARAM2 CPUFUNC(op_e178_0)(uae_u32 opcode) /* ROL */
26934: {
26935: uae_u32 srcreg = ((opcode >> 9) & 7);
26936: uae_u32 dstreg = opcode & 7;
26937: unsigned int retcycles = 0;
26938: OpcodeFamily = 68; CurrentInstrCycles = 4;
26939: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
26940: { uae_s16 data = m68k_dreg(regs, dstreg);
26941: { uae_u32 val = (uae_u16)data;
26942: cnt &= 63;
26943: retcycles = cnt;
26944: CLEAR_CZNV;
26945: if (cnt > 0) {
26946: uae_u32 loval;
26947: cnt &= 15;
26948: loval = val >> (16 - cnt);
26949: val <<= cnt;
26950: val |= loval;
26951: val &= 0xffff;
26952: SET_CFLG (val & 1);
26953: }
26954: SET_ZFLG (((uae_s16)(val)) == 0);
26955: SET_NFLG (((uae_s16)(val)) < 0);
26956: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
26957: }}}}m68k_incpc(2);
26958: return (6+retcycles*2);
26959: }
26960: unsigned long REGPARAM2 CPUFUNC(op_e180_0)(uae_u32 opcode) /* ASL */
26961: {
26962: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26963: uae_u32 dstreg = opcode & 7;
26964: unsigned int retcycles = 0;
26965: OpcodeFamily = 65; CurrentInstrCycles = 4;
26966: {{ uae_u32 cnt = srcreg;
26967: { uae_s32 data = m68k_dreg(regs, dstreg);
26968: { uae_u32 val = data;
26969: cnt &= 63;
26970: retcycles = cnt;
26971: CLEAR_CZNV;
26972: if (cnt >= 32) {
26973: SET_VFLG (val != 0);
26974: SET_CFLG (cnt == 32 ? val & 1 : 0);
26975: COPY_CARRY;
26976: val = 0;
26977: } else {
26978: uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
26979: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
26980: val <<= cnt - 1;
26981: SET_CFLG ((val & 0x80000000) >> 31);
26982: COPY_CARRY;
26983: val <<= 1;
26984: val &= 0xffffffff;
26985: }
26986: SET_ZFLG (((uae_s32)(val)) == 0);
26987: SET_NFLG (((uae_s32)(val)) < 0);
26988: m68k_dreg(regs, dstreg) = (val);
26989: }}}}m68k_incpc(2);
26990: return (8+retcycles*2);
26991: }
26992: unsigned long REGPARAM2 CPUFUNC(op_e188_0)(uae_u32 opcode) /* LSL */
26993: {
26994: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
26995: uae_u32 dstreg = opcode & 7;
26996: unsigned int retcycles = 0;
26997: OpcodeFamily = 67; CurrentInstrCycles = 4;
26998: {{ uae_u32 cnt = srcreg;
26999: { uae_s32 data = m68k_dreg(regs, dstreg);
27000: { uae_u32 val = data;
27001: cnt &= 63;
27002: retcycles = cnt;
27003: CLEAR_CZNV;
27004: if (cnt >= 32) {
27005: SET_CFLG (cnt == 32 ? val & 1 : 0);
27006: COPY_CARRY;
27007: val = 0;
27008: } else {
27009: val <<= (cnt - 1);
27010: SET_CFLG ((val & 0x80000000) >> 31);
27011: COPY_CARRY;
27012: val <<= 1;
27013: val &= 0xffffffff;
27014: }
27015: SET_ZFLG (((uae_s32)(val)) == 0);
27016: SET_NFLG (((uae_s32)(val)) < 0);
27017: m68k_dreg(regs, dstreg) = (val);
27018: }}}}m68k_incpc(2);
27019: return (8+retcycles*2);
27020: }
27021: unsigned long REGPARAM2 CPUFUNC(op_e190_0)(uae_u32 opcode) /* ROXL */
27022: {
27023: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
27024: uae_u32 dstreg = opcode & 7;
27025: unsigned int retcycles = 0;
27026: OpcodeFamily = 70; CurrentInstrCycles = 4;
27027: {{ uae_u32 cnt = srcreg;
27028: { uae_s32 data = m68k_dreg(regs, dstreg);
27029: { uae_u32 val = data;
27030: cnt &= 63;
27031: retcycles = cnt;
27032: CLEAR_CZNV;
27033: { cnt--;
27034: {
27035: uae_u32 carry;
27036: uae_u32 loval = val >> (31 - cnt);
27037: carry = loval & 1;
27038: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
27039: SET_XFLG (carry);
27040: val &= 0xffffffff;
27041: } }
27042: SET_CFLG (GET_XFLG);
27043: SET_ZFLG (((uae_s32)(val)) == 0);
27044: SET_NFLG (((uae_s32)(val)) < 0);
27045: m68k_dreg(regs, dstreg) = (val);
27046: }}}}m68k_incpc(2);
27047: return (8+retcycles*2);
27048: }
27049: unsigned long REGPARAM2 CPUFUNC(op_e198_0)(uae_u32 opcode) /* ROL */
27050: {
27051: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
27052: uae_u32 dstreg = opcode & 7;
27053: unsigned int retcycles = 0;
27054: OpcodeFamily = 68; CurrentInstrCycles = 4;
27055: {{ uae_u32 cnt = srcreg;
27056: { uae_s32 data = m68k_dreg(regs, dstreg);
27057: { uae_u32 val = data;
27058: cnt &= 63;
27059: retcycles = cnt;
27060: CLEAR_CZNV;
27061: { uae_u32 loval;
27062: cnt &= 31;
27063: loval = val >> (32 - cnt);
27064: val <<= cnt;
27065: val |= loval;
27066: val &= 0xffffffff;
27067: SET_CFLG (val & 1);
27068: }
27069: SET_ZFLG (((uae_s32)(val)) == 0);
27070: SET_NFLG (((uae_s32)(val)) < 0);
27071: m68k_dreg(regs, dstreg) = (val);
27072: }}}}m68k_incpc(2);
27073: return (8+retcycles*2);
27074: }
27075: unsigned long REGPARAM2 CPUFUNC(op_e1a0_0)(uae_u32 opcode) /* ASL */
27076: {
27077: uae_u32 srcreg = ((opcode >> 9) & 7);
27078: uae_u32 dstreg = opcode & 7;
27079: unsigned int retcycles = 0;
27080: OpcodeFamily = 65; CurrentInstrCycles = 4;
27081: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
27082: { uae_s32 data = m68k_dreg(regs, dstreg);
27083: { uae_u32 val = data;
27084: cnt &= 63;
27085: retcycles = cnt;
27086: CLEAR_CZNV;
27087: if (cnt >= 32) {
27088: SET_VFLG (val != 0);
27089: SET_CFLG (cnt == 32 ? val & 1 : 0);
27090: COPY_CARRY;
27091: val = 0;
27092: } else if (cnt > 0) {
27093: uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
27094: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
27095: val <<= cnt - 1;
27096: SET_CFLG ((val & 0x80000000) >> 31);
27097: COPY_CARRY;
27098: val <<= 1;
27099: val &= 0xffffffff;
27100: }
27101: SET_ZFLG (((uae_s32)(val)) == 0);
27102: SET_NFLG (((uae_s32)(val)) < 0);
27103: m68k_dreg(regs, dstreg) = (val);
27104: }}}}m68k_incpc(2);
27105: return (8+retcycles*2);
27106: }
27107: unsigned long REGPARAM2 CPUFUNC(op_e1a8_0)(uae_u32 opcode) /* LSL */
27108: {
27109: uae_u32 srcreg = ((opcode >> 9) & 7);
27110: uae_u32 dstreg = opcode & 7;
27111: unsigned int retcycles = 0;
27112: OpcodeFamily = 67; CurrentInstrCycles = 4;
27113: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
27114: { uae_s32 data = m68k_dreg(regs, dstreg);
27115: { uae_u32 val = data;
27116: cnt &= 63;
27117: retcycles = cnt;
27118: CLEAR_CZNV;
27119: if (cnt >= 32) {
27120: SET_CFLG (cnt == 32 ? val & 1 : 0);
27121: COPY_CARRY;
27122: val = 0;
27123: } else if (cnt > 0) {
27124: val <<= (cnt - 1);
27125: SET_CFLG ((val & 0x80000000) >> 31);
27126: COPY_CARRY;
27127: val <<= 1;
27128: val &= 0xffffffff;
27129: }
27130: SET_ZFLG (((uae_s32)(val)) == 0);
27131: SET_NFLG (((uae_s32)(val)) < 0);
27132: m68k_dreg(regs, dstreg) = (val);
27133: }}}}m68k_incpc(2);
27134: return (8+retcycles*2);
27135: }
27136: unsigned long REGPARAM2 CPUFUNC(op_e1b0_0)(uae_u32 opcode) /* ROXL */
27137: {
27138: uae_u32 srcreg = ((opcode >> 9) & 7);
27139: uae_u32 dstreg = opcode & 7;
27140: unsigned int retcycles = 0;
27141: OpcodeFamily = 70; CurrentInstrCycles = 4;
27142: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
27143: { uae_s32 data = m68k_dreg(regs, dstreg);
27144: { uae_u32 val = data;
27145: cnt &= 63;
27146: retcycles = cnt;
27147: CLEAR_CZNV;
27148: if (cnt >= 33) cnt -= 33;
27149: if (cnt > 0) {
27150: cnt--;
27151: {
27152: uae_u32 carry;
27153: uae_u32 loval = val >> (31 - cnt);
27154: carry = loval & 1;
27155: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
27156: SET_XFLG (carry);
27157: val &= 0xffffffff;
27158: } }
27159: SET_CFLG (GET_XFLG);
27160: SET_ZFLG (((uae_s32)(val)) == 0);
27161: SET_NFLG (((uae_s32)(val)) < 0);
27162: m68k_dreg(regs, dstreg) = (val);
27163: }}}}m68k_incpc(2);
27164: return (8+retcycles*2);
27165: }
27166: unsigned long REGPARAM2 CPUFUNC(op_e1b8_0)(uae_u32 opcode) /* ROL */
27167: {
27168: uae_u32 srcreg = ((opcode >> 9) & 7);
27169: uae_u32 dstreg = opcode & 7;
27170: unsigned int retcycles = 0;
27171: OpcodeFamily = 68; CurrentInstrCycles = 4;
27172: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
27173: { uae_s32 data = m68k_dreg(regs, dstreg);
27174: { uae_u32 val = data;
27175: cnt &= 63;
27176: retcycles = cnt;
27177: CLEAR_CZNV;
27178: if (cnt > 0) {
27179: uae_u32 loval;
27180: cnt &= 31;
27181: loval = val >> (32 - cnt);
27182: val <<= cnt;
27183: val |= loval;
27184: val &= 0xffffffff;
27185: SET_CFLG (val & 1);
27186: }
27187: SET_ZFLG (((uae_s32)(val)) == 0);
27188: SET_NFLG (((uae_s32)(val)) < 0);
27189: m68k_dreg(regs, dstreg) = (val);
27190: }}}}m68k_incpc(2);
27191: return (8+retcycles*2);
27192: }
27193: unsigned long REGPARAM2 CPUFUNC(op_e1d0_0)(uae_u32 opcode) /* ASLW */
27194: {
27195: uae_u32 srcreg = (opcode & 7);
27196: OpcodeFamily = 73; CurrentInstrCycles = 12;
27197: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27198: { uae_s16 data = get_word(dataa);
27199: { uae_u32 val = (uae_u16)data;
27200: uae_u32 sign = 0x8000 & val;
27201: uae_u32 sign2;
27202: val <<= 1;
27203: CLEAR_CZNV;
27204: SET_ZFLG (((uae_s16)(val)) == 0);
27205: SET_NFLG (((uae_s16)(val)) < 0);
27206: sign2 = 0x8000 & val;
27207: SET_CFLG (sign != 0);
27208: COPY_CARRY;
27209: SET_VFLG (GET_VFLG | (sign2 != sign));
27210: put_word(dataa,val);
27211: }}}}m68k_incpc(2);
27212: return 12;
27213: }
27214: unsigned long REGPARAM2 CPUFUNC(op_e1d8_0)(uae_u32 opcode) /* ASLW */
27215: {
27216: uae_u32 srcreg = (opcode & 7);
27217: OpcodeFamily = 73; CurrentInstrCycles = 12;
27218: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27219: { uae_s16 data = get_word(dataa);
27220: m68k_areg(regs, srcreg) += 2;
27221: { uae_u32 val = (uae_u16)data;
27222: uae_u32 sign = 0x8000 & val;
27223: uae_u32 sign2;
27224: val <<= 1;
27225: CLEAR_CZNV;
27226: SET_ZFLG (((uae_s16)(val)) == 0);
27227: SET_NFLG (((uae_s16)(val)) < 0);
27228: sign2 = 0x8000 & val;
27229: SET_CFLG (sign != 0);
27230: COPY_CARRY;
27231: SET_VFLG (GET_VFLG | (sign2 != sign));
27232: put_word(dataa,val);
27233: }}}}m68k_incpc(2);
27234: return 12;
27235: }
27236: unsigned long REGPARAM2 CPUFUNC(op_e1e0_0)(uae_u32 opcode) /* ASLW */
27237: {
27238: uae_u32 srcreg = (opcode & 7);
27239: OpcodeFamily = 73; CurrentInstrCycles = 14;
27240: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
27241: { uae_s16 data = get_word(dataa);
27242: m68k_areg (regs, srcreg) = dataa;
27243: { uae_u32 val = (uae_u16)data;
27244: uae_u32 sign = 0x8000 & val;
27245: uae_u32 sign2;
27246: val <<= 1;
27247: CLEAR_CZNV;
27248: SET_ZFLG (((uae_s16)(val)) == 0);
27249: SET_NFLG (((uae_s16)(val)) < 0);
27250: sign2 = 0x8000 & val;
27251: SET_CFLG (sign != 0);
27252: COPY_CARRY;
27253: SET_VFLG (GET_VFLG | (sign2 != sign));
27254: put_word(dataa,val);
27255: }}}}m68k_incpc(2);
27256: return 14;
27257: }
27258: unsigned long REGPARAM2 CPUFUNC(op_e1e8_0)(uae_u32 opcode) /* ASLW */
27259: {
27260: uae_u32 srcreg = (opcode & 7);
27261: OpcodeFamily = 73; CurrentInstrCycles = 16;
27262: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
27263: { uae_s16 data = get_word(dataa);
27264: { uae_u32 val = (uae_u16)data;
27265: uae_u32 sign = 0x8000 & val;
27266: uae_u32 sign2;
27267: val <<= 1;
27268: CLEAR_CZNV;
27269: SET_ZFLG (((uae_s16)(val)) == 0);
27270: SET_NFLG (((uae_s16)(val)) < 0);
27271: sign2 = 0x8000 & val;
27272: SET_CFLG (sign != 0);
27273: COPY_CARRY;
27274: SET_VFLG (GET_VFLG | (sign2 != sign));
27275: put_word(dataa,val);
27276: }}}}m68k_incpc(4);
27277: return 16;
27278: }
27279: unsigned long REGPARAM2 CPUFUNC(op_e1f0_0)(uae_u32 opcode) /* ASLW */
27280: {
27281: uae_u32 srcreg = (opcode & 7);
27282: OpcodeFamily = 73; CurrentInstrCycles = 18;
27283: {{m68k_incpc(2);
27284: { uaecptr dataa = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
27285: BusCyclePenalty += 2;
27286: { uae_s16 data = get_word(dataa);
27287: { uae_u32 val = (uae_u16)data;
27288: uae_u32 sign = 0x8000 & val;
27289: uae_u32 sign2;
27290: val <<= 1;
27291: CLEAR_CZNV;
27292: SET_ZFLG (((uae_s16)(val)) == 0);
27293: SET_NFLG (((uae_s16)(val)) < 0);
27294: sign2 = 0x8000 & val;
27295: SET_CFLG (sign != 0);
27296: COPY_CARRY;
27297: SET_VFLG (GET_VFLG | (sign2 != sign));
27298: put_word(dataa,val);
27299: }}}}}return 18;
27300: }
27301: unsigned long REGPARAM2 CPUFUNC(op_e1f8_0)(uae_u32 opcode) /* ASLW */
27302: {
27303: OpcodeFamily = 73; CurrentInstrCycles = 16;
27304: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword(2);
27305: { uae_s16 data = get_word(dataa);
27306: { uae_u32 val = (uae_u16)data;
27307: uae_u32 sign = 0x8000 & val;
27308: uae_u32 sign2;
27309: val <<= 1;
27310: CLEAR_CZNV;
27311: SET_ZFLG (((uae_s16)(val)) == 0);
27312: SET_NFLG (((uae_s16)(val)) < 0);
27313: sign2 = 0x8000 & val;
27314: SET_CFLG (sign != 0);
27315: COPY_CARRY;
27316: SET_VFLG (GET_VFLG | (sign2 != sign));
27317: put_word(dataa,val);
27318: }}}}m68k_incpc(4);
27319: return 16;
27320: }
27321: unsigned long REGPARAM2 CPUFUNC(op_e1f9_0)(uae_u32 opcode) /* ASLW */
27322: {
27323: OpcodeFamily = 73; CurrentInstrCycles = 20;
27324: {{ uaecptr dataa = get_ilong(2);
27325: { uae_s16 data = get_word(dataa);
27326: { uae_u32 val = (uae_u16)data;
27327: uae_u32 sign = 0x8000 & val;
27328: uae_u32 sign2;
27329: val <<= 1;
27330: CLEAR_CZNV;
27331: SET_ZFLG (((uae_s16)(val)) == 0);
27332: SET_NFLG (((uae_s16)(val)) < 0);
27333: sign2 = 0x8000 & val;
27334: SET_CFLG (sign != 0);
27335: COPY_CARRY;
27336: SET_VFLG (GET_VFLG | (sign2 != sign));
27337: put_word(dataa,val);
27338: }}}}m68k_incpc(6);
27339: return 20;
27340: }
27341: unsigned long REGPARAM2 CPUFUNC(op_e2d0_0)(uae_u32 opcode) /* LSRW */
27342: {
27343: uae_u32 srcreg = (opcode & 7);
27344: OpcodeFamily = 74; CurrentInstrCycles = 12;
27345: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27346: { uae_s16 data = get_word(dataa);
27347: { uae_u32 val = (uae_u16)data;
27348: uae_u32 carry = val & 1;
27349: val >>= 1;
27350: CLEAR_CZNV;
27351: SET_ZFLG (((uae_s16)(val)) == 0);
27352: SET_NFLG (((uae_s16)(val)) < 0);
27353: SET_CFLG (carry);
27354: COPY_CARRY;
27355: put_word(dataa,val);
27356: }}}}m68k_incpc(2);
27357: return 12;
27358: }
27359: unsigned long REGPARAM2 CPUFUNC(op_e2d8_0)(uae_u32 opcode) /* LSRW */
27360: {
27361: uae_u32 srcreg = (opcode & 7);
27362: OpcodeFamily = 74; CurrentInstrCycles = 12;
27363: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27364: { uae_s16 data = get_word(dataa);
27365: m68k_areg(regs, srcreg) += 2;
27366: { uae_u32 val = (uae_u16)data;
27367: uae_u32 carry = val & 1;
27368: val >>= 1;
27369: CLEAR_CZNV;
27370: SET_ZFLG (((uae_s16)(val)) == 0);
27371: SET_NFLG (((uae_s16)(val)) < 0);
27372: SET_CFLG (carry);
27373: COPY_CARRY;
27374: put_word(dataa,val);
27375: }}}}m68k_incpc(2);
27376: return 12;
27377: }
27378: unsigned long REGPARAM2 CPUFUNC(op_e2e0_0)(uae_u32 opcode) /* LSRW */
27379: {
27380: uae_u32 srcreg = (opcode & 7);
27381: OpcodeFamily = 74; CurrentInstrCycles = 14;
27382: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
27383: { uae_s16 data = get_word(dataa);
27384: m68k_areg (regs, srcreg) = dataa;
27385: { uae_u32 val = (uae_u16)data;
27386: uae_u32 carry = val & 1;
27387: val >>= 1;
27388: CLEAR_CZNV;
27389: SET_ZFLG (((uae_s16)(val)) == 0);
27390: SET_NFLG (((uae_s16)(val)) < 0);
27391: SET_CFLG (carry);
27392: COPY_CARRY;
27393: put_word(dataa,val);
27394: }}}}m68k_incpc(2);
27395: return 14;
27396: }
27397: unsigned long REGPARAM2 CPUFUNC(op_e2e8_0)(uae_u32 opcode) /* LSRW */
27398: {
27399: uae_u32 srcreg = (opcode & 7);
27400: OpcodeFamily = 74; CurrentInstrCycles = 16;
27401: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
27402: { uae_s16 data = get_word(dataa);
27403: { uae_u32 val = (uae_u16)data;
27404: uae_u32 carry = val & 1;
27405: val >>= 1;
27406: CLEAR_CZNV;
27407: SET_ZFLG (((uae_s16)(val)) == 0);
27408: SET_NFLG (((uae_s16)(val)) < 0);
27409: SET_CFLG (carry);
27410: COPY_CARRY;
27411: put_word(dataa,val);
27412: }}}}m68k_incpc(4);
27413: return 16;
27414: }
27415: unsigned long REGPARAM2 CPUFUNC(op_e2f0_0)(uae_u32 opcode) /* LSRW */
27416: {
27417: uae_u32 srcreg = (opcode & 7);
27418: OpcodeFamily = 74; CurrentInstrCycles = 18;
27419: {{m68k_incpc(2);
27420: { uaecptr dataa = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
27421: BusCyclePenalty += 2;
27422: { uae_s16 data = get_word(dataa);
27423: { uae_u32 val = (uae_u16)data;
27424: uae_u32 carry = val & 1;
27425: val >>= 1;
27426: CLEAR_CZNV;
27427: SET_ZFLG (((uae_s16)(val)) == 0);
27428: SET_NFLG (((uae_s16)(val)) < 0);
27429: SET_CFLG (carry);
27430: COPY_CARRY;
27431: put_word(dataa,val);
27432: }}}}}return 18;
27433: }
27434: unsigned long REGPARAM2 CPUFUNC(op_e2f8_0)(uae_u32 opcode) /* LSRW */
27435: {
27436: OpcodeFamily = 74; CurrentInstrCycles = 16;
27437: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword(2);
27438: { uae_s16 data = get_word(dataa);
27439: { uae_u32 val = (uae_u16)data;
27440: uae_u32 carry = val & 1;
27441: val >>= 1;
27442: CLEAR_CZNV;
27443: SET_ZFLG (((uae_s16)(val)) == 0);
27444: SET_NFLG (((uae_s16)(val)) < 0);
27445: SET_CFLG (carry);
27446: COPY_CARRY;
27447: put_word(dataa,val);
27448: }}}}m68k_incpc(4);
27449: return 16;
27450: }
27451: unsigned long REGPARAM2 CPUFUNC(op_e2f9_0)(uae_u32 opcode) /* LSRW */
27452: {
27453: OpcodeFamily = 74; CurrentInstrCycles = 20;
27454: {{ uaecptr dataa = get_ilong(2);
27455: { uae_s16 data = get_word(dataa);
27456: { uae_u32 val = (uae_u16)data;
27457: uae_u32 carry = val & 1;
27458: val >>= 1;
27459: CLEAR_CZNV;
27460: SET_ZFLG (((uae_s16)(val)) == 0);
27461: SET_NFLG (((uae_s16)(val)) < 0);
27462: SET_CFLG (carry);
27463: COPY_CARRY;
27464: put_word(dataa,val);
27465: }}}}m68k_incpc(6);
27466: return 20;
27467: }
27468: unsigned long REGPARAM2 CPUFUNC(op_e3d0_0)(uae_u32 opcode) /* LSLW */
27469: {
27470: uae_u32 srcreg = (opcode & 7);
27471: OpcodeFamily = 75; CurrentInstrCycles = 12;
27472: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27473: { uae_s16 data = get_word(dataa);
27474: { uae_u16 val = data;
27475: uae_u32 carry = val & 0x8000;
27476: val <<= 1;
27477: CLEAR_CZNV;
27478: SET_ZFLG (((uae_s16)(val)) == 0);
27479: SET_NFLG (((uae_s16)(val)) < 0);
27480: SET_CFLG (carry >> 15);
27481: COPY_CARRY;
27482: put_word(dataa,val);
27483: }}}}m68k_incpc(2);
27484: return 12;
27485: }
27486: unsigned long REGPARAM2 CPUFUNC(op_e3d8_0)(uae_u32 opcode) /* LSLW */
27487: {
27488: uae_u32 srcreg = (opcode & 7);
27489: OpcodeFamily = 75; CurrentInstrCycles = 12;
27490: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27491: { uae_s16 data = get_word(dataa);
27492: m68k_areg(regs, srcreg) += 2;
27493: { uae_u16 val = data;
27494: uae_u32 carry = val & 0x8000;
27495: val <<= 1;
27496: CLEAR_CZNV;
27497: SET_ZFLG (((uae_s16)(val)) == 0);
27498: SET_NFLG (((uae_s16)(val)) < 0);
27499: SET_CFLG (carry >> 15);
27500: COPY_CARRY;
27501: put_word(dataa,val);
27502: }}}}m68k_incpc(2);
27503: return 12;
27504: }
27505: unsigned long REGPARAM2 CPUFUNC(op_e3e0_0)(uae_u32 opcode) /* LSLW */
27506: {
27507: uae_u32 srcreg = (opcode & 7);
27508: OpcodeFamily = 75; CurrentInstrCycles = 14;
27509: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
27510: { uae_s16 data = get_word(dataa);
27511: m68k_areg (regs, srcreg) = dataa;
27512: { uae_u16 val = data;
27513: uae_u32 carry = val & 0x8000;
27514: val <<= 1;
27515: CLEAR_CZNV;
27516: SET_ZFLG (((uae_s16)(val)) == 0);
27517: SET_NFLG (((uae_s16)(val)) < 0);
27518: SET_CFLG (carry >> 15);
27519: COPY_CARRY;
27520: put_word(dataa,val);
27521: }}}}m68k_incpc(2);
27522: return 14;
27523: }
27524: unsigned long REGPARAM2 CPUFUNC(op_e3e8_0)(uae_u32 opcode) /* LSLW */
27525: {
27526: uae_u32 srcreg = (opcode & 7);
27527: OpcodeFamily = 75; CurrentInstrCycles = 16;
27528: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
27529: { uae_s16 data = get_word(dataa);
27530: { uae_u16 val = data;
27531: uae_u32 carry = val & 0x8000;
27532: val <<= 1;
27533: CLEAR_CZNV;
27534: SET_ZFLG (((uae_s16)(val)) == 0);
27535: SET_NFLG (((uae_s16)(val)) < 0);
27536: SET_CFLG (carry >> 15);
27537: COPY_CARRY;
27538: put_word(dataa,val);
27539: }}}}m68k_incpc(4);
27540: return 16;
27541: }
27542: unsigned long REGPARAM2 CPUFUNC(op_e3f0_0)(uae_u32 opcode) /* LSLW */
27543: {
27544: uae_u32 srcreg = (opcode & 7);
27545: OpcodeFamily = 75; CurrentInstrCycles = 18;
27546: {{m68k_incpc(2);
27547: { uaecptr dataa = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
27548: BusCyclePenalty += 2;
27549: { uae_s16 data = get_word(dataa);
27550: { uae_u16 val = data;
27551: uae_u32 carry = val & 0x8000;
27552: val <<= 1;
27553: CLEAR_CZNV;
27554: SET_ZFLG (((uae_s16)(val)) == 0);
27555: SET_NFLG (((uae_s16)(val)) < 0);
27556: SET_CFLG (carry >> 15);
27557: COPY_CARRY;
27558: put_word(dataa,val);
27559: }}}}}return 18;
27560: }
27561: unsigned long REGPARAM2 CPUFUNC(op_e3f8_0)(uae_u32 opcode) /* LSLW */
27562: {
27563: OpcodeFamily = 75; CurrentInstrCycles = 16;
27564: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword(2);
27565: { uae_s16 data = get_word(dataa);
27566: { uae_u16 val = data;
27567: uae_u32 carry = val & 0x8000;
27568: val <<= 1;
27569: CLEAR_CZNV;
27570: SET_ZFLG (((uae_s16)(val)) == 0);
27571: SET_NFLG (((uae_s16)(val)) < 0);
27572: SET_CFLG (carry >> 15);
27573: COPY_CARRY;
27574: put_word(dataa,val);
27575: }}}}m68k_incpc(4);
27576: return 16;
27577: }
27578: unsigned long REGPARAM2 CPUFUNC(op_e3f9_0)(uae_u32 opcode) /* LSLW */
27579: {
27580: OpcodeFamily = 75; CurrentInstrCycles = 20;
27581: {{ uaecptr dataa = get_ilong(2);
27582: { uae_s16 data = get_word(dataa);
27583: { uae_u16 val = data;
27584: uae_u32 carry = val & 0x8000;
27585: val <<= 1;
27586: CLEAR_CZNV;
27587: SET_ZFLG (((uae_s16)(val)) == 0);
27588: SET_NFLG (((uae_s16)(val)) < 0);
27589: SET_CFLG (carry >> 15);
27590: COPY_CARRY;
27591: put_word(dataa,val);
27592: }}}}m68k_incpc(6);
27593: return 20;
27594: }
27595: unsigned long REGPARAM2 CPUFUNC(op_e4d0_0)(uae_u32 opcode) /* ROXRW */
27596: {
27597: uae_u32 srcreg = (opcode & 7);
27598: OpcodeFamily = 79; CurrentInstrCycles = 12;
27599: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27600: { uae_s16 data = get_word(dataa);
27601: { uae_u16 val = data;
27602: uae_u32 carry = val & 1;
27603: val >>= 1;
27604: if (GET_XFLG) val |= 0x8000;
27605: CLEAR_CZNV;
27606: SET_ZFLG (((uae_s16)(val)) == 0);
27607: SET_NFLG (((uae_s16)(val)) < 0);
27608: SET_CFLG (carry);
27609: COPY_CARRY;
27610: put_word(dataa,val);
27611: }}}}m68k_incpc(2);
27612: return 12;
27613: }
27614: unsigned long REGPARAM2 CPUFUNC(op_e4d8_0)(uae_u32 opcode) /* ROXRW */
27615: {
27616: uae_u32 srcreg = (opcode & 7);
27617: OpcodeFamily = 79; CurrentInstrCycles = 12;
27618: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27619: { uae_s16 data = get_word(dataa);
27620: m68k_areg(regs, srcreg) += 2;
27621: { uae_u16 val = data;
27622: uae_u32 carry = val & 1;
27623: val >>= 1;
27624: if (GET_XFLG) val |= 0x8000;
27625: CLEAR_CZNV;
27626: SET_ZFLG (((uae_s16)(val)) == 0);
27627: SET_NFLG (((uae_s16)(val)) < 0);
27628: SET_CFLG (carry);
27629: COPY_CARRY;
27630: put_word(dataa,val);
27631: }}}}m68k_incpc(2);
27632: return 12;
27633: }
27634: unsigned long REGPARAM2 CPUFUNC(op_e4e0_0)(uae_u32 opcode) /* ROXRW */
27635: {
27636: uae_u32 srcreg = (opcode & 7);
27637: OpcodeFamily = 79; CurrentInstrCycles = 14;
27638: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
27639: { uae_s16 data = get_word(dataa);
27640: m68k_areg (regs, srcreg) = dataa;
27641: { uae_u16 val = data;
27642: uae_u32 carry = val & 1;
27643: val >>= 1;
27644: if (GET_XFLG) val |= 0x8000;
27645: CLEAR_CZNV;
27646: SET_ZFLG (((uae_s16)(val)) == 0);
27647: SET_NFLG (((uae_s16)(val)) < 0);
27648: SET_CFLG (carry);
27649: COPY_CARRY;
27650: put_word(dataa,val);
27651: }}}}m68k_incpc(2);
27652: return 14;
27653: }
27654: unsigned long REGPARAM2 CPUFUNC(op_e4e8_0)(uae_u32 opcode) /* ROXRW */
27655: {
27656: uae_u32 srcreg = (opcode & 7);
27657: OpcodeFamily = 79; CurrentInstrCycles = 16;
27658: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
27659: { uae_s16 data = get_word(dataa);
27660: { uae_u16 val = data;
27661: uae_u32 carry = val & 1;
27662: val >>= 1;
27663: if (GET_XFLG) val |= 0x8000;
27664: CLEAR_CZNV;
27665: SET_ZFLG (((uae_s16)(val)) == 0);
27666: SET_NFLG (((uae_s16)(val)) < 0);
27667: SET_CFLG (carry);
27668: COPY_CARRY;
27669: put_word(dataa,val);
27670: }}}}m68k_incpc(4);
27671: return 16;
27672: }
27673: unsigned long REGPARAM2 CPUFUNC(op_e4f0_0)(uae_u32 opcode) /* ROXRW */
27674: {
27675: uae_u32 srcreg = (opcode & 7);
27676: OpcodeFamily = 79; CurrentInstrCycles = 18;
27677: {{m68k_incpc(2);
27678: { uaecptr dataa = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
27679: BusCyclePenalty += 2;
27680: { uae_s16 data = get_word(dataa);
27681: { uae_u16 val = data;
27682: uae_u32 carry = val & 1;
27683: val >>= 1;
27684: if (GET_XFLG) val |= 0x8000;
27685: CLEAR_CZNV;
27686: SET_ZFLG (((uae_s16)(val)) == 0);
27687: SET_NFLG (((uae_s16)(val)) < 0);
27688: SET_CFLG (carry);
27689: COPY_CARRY;
27690: put_word(dataa,val);
27691: }}}}}return 18;
27692: }
27693: unsigned long REGPARAM2 CPUFUNC(op_e4f8_0)(uae_u32 opcode) /* ROXRW */
27694: {
27695: OpcodeFamily = 79; CurrentInstrCycles = 16;
27696: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword(2);
27697: { uae_s16 data = get_word(dataa);
27698: { uae_u16 val = data;
27699: uae_u32 carry = val & 1;
27700: val >>= 1;
27701: if (GET_XFLG) val |= 0x8000;
27702: CLEAR_CZNV;
27703: SET_ZFLG (((uae_s16)(val)) == 0);
27704: SET_NFLG (((uae_s16)(val)) < 0);
27705: SET_CFLG (carry);
27706: COPY_CARRY;
27707: put_word(dataa,val);
27708: }}}}m68k_incpc(4);
27709: return 16;
27710: }
27711: unsigned long REGPARAM2 CPUFUNC(op_e4f9_0)(uae_u32 opcode) /* ROXRW */
27712: {
27713: OpcodeFamily = 79; CurrentInstrCycles = 20;
27714: {{ uaecptr dataa = get_ilong(2);
27715: { uae_s16 data = get_word(dataa);
27716: { uae_u16 val = data;
27717: uae_u32 carry = val & 1;
27718: val >>= 1;
27719: if (GET_XFLG) val |= 0x8000;
27720: CLEAR_CZNV;
27721: SET_ZFLG (((uae_s16)(val)) == 0);
27722: SET_NFLG (((uae_s16)(val)) < 0);
27723: SET_CFLG (carry);
27724: COPY_CARRY;
27725: put_word(dataa,val);
27726: }}}}m68k_incpc(6);
27727: return 20;
27728: }
27729: unsigned long REGPARAM2 CPUFUNC(op_e5d0_0)(uae_u32 opcode) /* ROXLW */
27730: {
27731: uae_u32 srcreg = (opcode & 7);
27732: OpcodeFamily = 78; CurrentInstrCycles = 12;
27733: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27734: { uae_s16 data = get_word(dataa);
27735: { uae_u16 val = data;
27736: uae_u32 carry = val & 0x8000;
27737: val <<= 1;
27738: if (GET_XFLG) val |= 1;
27739: CLEAR_CZNV;
27740: SET_ZFLG (((uae_s16)(val)) == 0);
27741: SET_NFLG (((uae_s16)(val)) < 0);
27742: SET_CFLG (carry >> 15);
27743: COPY_CARRY;
27744: put_word(dataa,val);
27745: }}}}m68k_incpc(2);
27746: return 12;
27747: }
27748: unsigned long REGPARAM2 CPUFUNC(op_e5d8_0)(uae_u32 opcode) /* ROXLW */
27749: {
27750: uae_u32 srcreg = (opcode & 7);
27751: OpcodeFamily = 78; CurrentInstrCycles = 12;
27752: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27753: { uae_s16 data = get_word(dataa);
27754: m68k_areg(regs, srcreg) += 2;
27755: { uae_u16 val = data;
27756: uae_u32 carry = val & 0x8000;
27757: val <<= 1;
27758: if (GET_XFLG) val |= 1;
27759: CLEAR_CZNV;
27760: SET_ZFLG (((uae_s16)(val)) == 0);
27761: SET_NFLG (((uae_s16)(val)) < 0);
27762: SET_CFLG (carry >> 15);
27763: COPY_CARRY;
27764: put_word(dataa,val);
27765: }}}}m68k_incpc(2);
27766: return 12;
27767: }
27768: unsigned long REGPARAM2 CPUFUNC(op_e5e0_0)(uae_u32 opcode) /* ROXLW */
27769: {
27770: uae_u32 srcreg = (opcode & 7);
27771: OpcodeFamily = 78; CurrentInstrCycles = 14;
27772: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
27773: { uae_s16 data = get_word(dataa);
27774: m68k_areg (regs, srcreg) = dataa;
27775: { uae_u16 val = data;
27776: uae_u32 carry = val & 0x8000;
27777: val <<= 1;
27778: if (GET_XFLG) val |= 1;
27779: CLEAR_CZNV;
27780: SET_ZFLG (((uae_s16)(val)) == 0);
27781: SET_NFLG (((uae_s16)(val)) < 0);
27782: SET_CFLG (carry >> 15);
27783: COPY_CARRY;
27784: put_word(dataa,val);
27785: }}}}m68k_incpc(2);
27786: return 14;
27787: }
27788: unsigned long REGPARAM2 CPUFUNC(op_e5e8_0)(uae_u32 opcode) /* ROXLW */
27789: {
27790: uae_u32 srcreg = (opcode & 7);
27791: OpcodeFamily = 78; CurrentInstrCycles = 16;
27792: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
27793: { uae_s16 data = get_word(dataa);
27794: { uae_u16 val = data;
27795: uae_u32 carry = val & 0x8000;
27796: val <<= 1;
27797: if (GET_XFLG) val |= 1;
27798: CLEAR_CZNV;
27799: SET_ZFLG (((uae_s16)(val)) == 0);
27800: SET_NFLG (((uae_s16)(val)) < 0);
27801: SET_CFLG (carry >> 15);
27802: COPY_CARRY;
27803: put_word(dataa,val);
27804: }}}}m68k_incpc(4);
27805: return 16;
27806: }
27807: unsigned long REGPARAM2 CPUFUNC(op_e5f0_0)(uae_u32 opcode) /* ROXLW */
27808: {
27809: uae_u32 srcreg = (opcode & 7);
27810: OpcodeFamily = 78; CurrentInstrCycles = 18;
27811: {{m68k_incpc(2);
27812: { uaecptr dataa = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
27813: BusCyclePenalty += 2;
27814: { uae_s16 data = get_word(dataa);
27815: { uae_u16 val = data;
27816: uae_u32 carry = val & 0x8000;
27817: val <<= 1;
27818: if (GET_XFLG) val |= 1;
27819: CLEAR_CZNV;
27820: SET_ZFLG (((uae_s16)(val)) == 0);
27821: SET_NFLG (((uae_s16)(val)) < 0);
27822: SET_CFLG (carry >> 15);
27823: COPY_CARRY;
27824: put_word(dataa,val);
27825: }}}}}return 18;
27826: }
27827: unsigned long REGPARAM2 CPUFUNC(op_e5f8_0)(uae_u32 opcode) /* ROXLW */
27828: {
27829: OpcodeFamily = 78; CurrentInstrCycles = 16;
27830: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword(2);
27831: { uae_s16 data = get_word(dataa);
27832: { uae_u16 val = data;
27833: uae_u32 carry = val & 0x8000;
27834: val <<= 1;
27835: if (GET_XFLG) val |= 1;
27836: CLEAR_CZNV;
27837: SET_ZFLG (((uae_s16)(val)) == 0);
27838: SET_NFLG (((uae_s16)(val)) < 0);
27839: SET_CFLG (carry >> 15);
27840: COPY_CARRY;
27841: put_word(dataa,val);
27842: }}}}m68k_incpc(4);
27843: return 16;
27844: }
27845: unsigned long REGPARAM2 CPUFUNC(op_e5f9_0)(uae_u32 opcode) /* ROXLW */
27846: {
27847: OpcodeFamily = 78; CurrentInstrCycles = 20;
27848: {{ uaecptr dataa = get_ilong(2);
27849: { uae_s16 data = get_word(dataa);
27850: { uae_u16 val = data;
27851: uae_u32 carry = val & 0x8000;
27852: val <<= 1;
27853: if (GET_XFLG) val |= 1;
27854: CLEAR_CZNV;
27855: SET_ZFLG (((uae_s16)(val)) == 0);
27856: SET_NFLG (((uae_s16)(val)) < 0);
27857: SET_CFLG (carry >> 15);
27858: COPY_CARRY;
27859: put_word(dataa,val);
27860: }}}}m68k_incpc(6);
27861: return 20;
27862: }
27863: unsigned long REGPARAM2 CPUFUNC(op_e6d0_0)(uae_u32 opcode) /* RORW */
27864: {
27865: uae_u32 srcreg = (opcode & 7);
27866: OpcodeFamily = 77; CurrentInstrCycles = 12;
27867: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27868: { uae_s16 data = get_word(dataa);
27869: { uae_u16 val = data;
27870: uae_u32 carry = val & 1;
27871: val >>= 1;
27872: if (carry) val |= 0x8000;
27873: CLEAR_CZNV;
27874: SET_ZFLG (((uae_s16)(val)) == 0);
27875: SET_NFLG (((uae_s16)(val)) < 0);
27876: SET_CFLG (carry);
27877: put_word(dataa,val);
27878: }}}}m68k_incpc(2);
27879: return 12;
27880: }
27881: unsigned long REGPARAM2 CPUFUNC(op_e6d8_0)(uae_u32 opcode) /* RORW */
27882: {
27883: uae_u32 srcreg = (opcode & 7);
27884: OpcodeFamily = 77; CurrentInstrCycles = 12;
27885: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27886: { uae_s16 data = get_word(dataa);
27887: m68k_areg(regs, srcreg) += 2;
27888: { uae_u16 val = data;
27889: uae_u32 carry = val & 1;
27890: val >>= 1;
27891: if (carry) val |= 0x8000;
27892: CLEAR_CZNV;
27893: SET_ZFLG (((uae_s16)(val)) == 0);
27894: SET_NFLG (((uae_s16)(val)) < 0);
27895: SET_CFLG (carry);
27896: put_word(dataa,val);
27897: }}}}m68k_incpc(2);
27898: return 12;
27899: }
27900: unsigned long REGPARAM2 CPUFUNC(op_e6e0_0)(uae_u32 opcode) /* RORW */
27901: {
27902: uae_u32 srcreg = (opcode & 7);
27903: OpcodeFamily = 77; CurrentInstrCycles = 14;
27904: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
27905: { uae_s16 data = get_word(dataa);
27906: m68k_areg (regs, srcreg) = dataa;
27907: { uae_u16 val = data;
27908: uae_u32 carry = val & 1;
27909: val >>= 1;
27910: if (carry) val |= 0x8000;
27911: CLEAR_CZNV;
27912: SET_ZFLG (((uae_s16)(val)) == 0);
27913: SET_NFLG (((uae_s16)(val)) < 0);
27914: SET_CFLG (carry);
27915: put_word(dataa,val);
27916: }}}}m68k_incpc(2);
27917: return 14;
27918: }
27919: unsigned long REGPARAM2 CPUFUNC(op_e6e8_0)(uae_u32 opcode) /* RORW */
27920: {
27921: uae_u32 srcreg = (opcode & 7);
27922: OpcodeFamily = 77; CurrentInstrCycles = 16;
27923: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
27924: { uae_s16 data = get_word(dataa);
27925: { uae_u16 val = data;
27926: uae_u32 carry = val & 1;
27927: val >>= 1;
27928: if (carry) val |= 0x8000;
27929: CLEAR_CZNV;
27930: SET_ZFLG (((uae_s16)(val)) == 0);
27931: SET_NFLG (((uae_s16)(val)) < 0);
27932: SET_CFLG (carry);
27933: put_word(dataa,val);
27934: }}}}m68k_incpc(4);
27935: return 16;
27936: }
27937: unsigned long REGPARAM2 CPUFUNC(op_e6f0_0)(uae_u32 opcode) /* RORW */
27938: {
27939: uae_u32 srcreg = (opcode & 7);
27940: OpcodeFamily = 77; CurrentInstrCycles = 18;
27941: {{m68k_incpc(2);
27942: { uaecptr dataa = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
27943: BusCyclePenalty += 2;
27944: { uae_s16 data = get_word(dataa);
27945: { uae_u16 val = data;
27946: uae_u32 carry = val & 1;
27947: val >>= 1;
27948: if (carry) val |= 0x8000;
27949: CLEAR_CZNV;
27950: SET_ZFLG (((uae_s16)(val)) == 0);
27951: SET_NFLG (((uae_s16)(val)) < 0);
27952: SET_CFLG (carry);
27953: put_word(dataa,val);
27954: }}}}}return 18;
27955: }
27956: unsigned long REGPARAM2 CPUFUNC(op_e6f8_0)(uae_u32 opcode) /* RORW */
27957: {
27958: OpcodeFamily = 77; CurrentInstrCycles = 16;
27959: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword(2);
27960: { uae_s16 data = get_word(dataa);
27961: { uae_u16 val = data;
27962: uae_u32 carry = val & 1;
27963: val >>= 1;
27964: if (carry) val |= 0x8000;
27965: CLEAR_CZNV;
27966: SET_ZFLG (((uae_s16)(val)) == 0);
27967: SET_NFLG (((uae_s16)(val)) < 0);
27968: SET_CFLG (carry);
27969: put_word(dataa,val);
27970: }}}}m68k_incpc(4);
27971: return 16;
27972: }
27973: unsigned long REGPARAM2 CPUFUNC(op_e6f9_0)(uae_u32 opcode) /* RORW */
27974: {
27975: OpcodeFamily = 77; CurrentInstrCycles = 20;
27976: {{ uaecptr dataa = get_ilong(2);
27977: { uae_s16 data = get_word(dataa);
27978: { uae_u16 val = data;
27979: uae_u32 carry = val & 1;
27980: val >>= 1;
27981: if (carry) val |= 0x8000;
27982: CLEAR_CZNV;
27983: SET_ZFLG (((uae_s16)(val)) == 0);
27984: SET_NFLG (((uae_s16)(val)) < 0);
27985: SET_CFLG (carry);
27986: put_word(dataa,val);
27987: }}}}m68k_incpc(6);
27988: return 20;
27989: }
27990: unsigned long REGPARAM2 CPUFUNC(op_e7d0_0)(uae_u32 opcode) /* ROLW */
27991: {
27992: uae_u32 srcreg = (opcode & 7);
27993: OpcodeFamily = 76; CurrentInstrCycles = 12;
27994: {{ uaecptr dataa = m68k_areg(regs, srcreg);
27995: { uae_s16 data = get_word(dataa);
27996: { uae_u16 val = data;
27997: uae_u32 carry = val & 0x8000;
27998: val <<= 1;
27999: if (carry) val |= 1;
28000: CLEAR_CZNV;
28001: SET_ZFLG (((uae_s16)(val)) == 0);
28002: SET_NFLG (((uae_s16)(val)) < 0);
28003: SET_CFLG (carry >> 15);
28004: put_word(dataa,val);
28005: }}}}m68k_incpc(2);
28006: return 12;
28007: }
28008: unsigned long REGPARAM2 CPUFUNC(op_e7d8_0)(uae_u32 opcode) /* ROLW */
28009: {
28010: uae_u32 srcreg = (opcode & 7);
28011: OpcodeFamily = 76; CurrentInstrCycles = 12;
28012: {{ uaecptr dataa = m68k_areg(regs, srcreg);
28013: { uae_s16 data = get_word(dataa);
28014: m68k_areg(regs, srcreg) += 2;
28015: { uae_u16 val = data;
28016: uae_u32 carry = val & 0x8000;
28017: val <<= 1;
28018: if (carry) val |= 1;
28019: CLEAR_CZNV;
28020: SET_ZFLG (((uae_s16)(val)) == 0);
28021: SET_NFLG (((uae_s16)(val)) < 0);
28022: SET_CFLG (carry >> 15);
28023: put_word(dataa,val);
28024: }}}}m68k_incpc(2);
28025: return 12;
28026: }
28027: unsigned long REGPARAM2 CPUFUNC(op_e7e0_0)(uae_u32 opcode) /* ROLW */
28028: {
28029: uae_u32 srcreg = (opcode & 7);
28030: OpcodeFamily = 76; CurrentInstrCycles = 14;
28031: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
28032: { uae_s16 data = get_word(dataa);
28033: m68k_areg (regs, srcreg) = dataa;
28034: { uae_u16 val = data;
28035: uae_u32 carry = val & 0x8000;
28036: val <<= 1;
28037: if (carry) val |= 1;
28038: CLEAR_CZNV;
28039: SET_ZFLG (((uae_s16)(val)) == 0);
28040: SET_NFLG (((uae_s16)(val)) < 0);
28041: SET_CFLG (carry >> 15);
28042: put_word(dataa,val);
28043: }}}}m68k_incpc(2);
28044: return 14;
28045: }
28046: unsigned long REGPARAM2 CPUFUNC(op_e7e8_0)(uae_u32 opcode) /* ROLW */
28047: {
28048: uae_u32 srcreg = (opcode & 7);
28049: OpcodeFamily = 76; CurrentInstrCycles = 16;
28050: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
28051: { uae_s16 data = get_word(dataa);
28052: { uae_u16 val = data;
28053: uae_u32 carry = val & 0x8000;
28054: val <<= 1;
28055: if (carry) val |= 1;
28056: CLEAR_CZNV;
28057: SET_ZFLG (((uae_s16)(val)) == 0);
28058: SET_NFLG (((uae_s16)(val)) < 0);
28059: SET_CFLG (carry >> 15);
28060: put_word(dataa,val);
28061: }}}}m68k_incpc(4);
28062: return 16;
28063: }
28064: unsigned long REGPARAM2 CPUFUNC(op_e7f0_0)(uae_u32 opcode) /* ROLW */
28065: {
28066: uae_u32 srcreg = (opcode & 7);
28067: OpcodeFamily = 76; CurrentInstrCycles = 18;
28068: {{m68k_incpc(2);
28069: { uaecptr dataa = get_disp_ea_020(m68k_areg(regs, srcreg), next_iword());
28070: BusCyclePenalty += 2;
28071: { uae_s16 data = get_word(dataa);
28072: { uae_u16 val = data;
28073: uae_u32 carry = val & 0x8000;
28074: val <<= 1;
28075: if (carry) val |= 1;
28076: CLEAR_CZNV;
28077: SET_ZFLG (((uae_s16)(val)) == 0);
28078: SET_NFLG (((uae_s16)(val)) < 0);
28079: SET_CFLG (carry >> 15);
28080: put_word(dataa,val);
28081: }}}}}return 18;
28082: }
28083: unsigned long REGPARAM2 CPUFUNC(op_e7f8_0)(uae_u32 opcode) /* ROLW */
28084: {
28085: OpcodeFamily = 76; CurrentInstrCycles = 16;
28086: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword(2);
28087: { uae_s16 data = get_word(dataa);
28088: { uae_u16 val = data;
28089: uae_u32 carry = val & 0x8000;
28090: val <<= 1;
28091: if (carry) val |= 1;
28092: CLEAR_CZNV;
28093: SET_ZFLG (((uae_s16)(val)) == 0);
28094: SET_NFLG (((uae_s16)(val)) < 0);
28095: SET_CFLG (carry >> 15);
28096: put_word(dataa,val);
28097: }}}}m68k_incpc(4);
28098: return 16;
28099: }
28100: unsigned long REGPARAM2 CPUFUNC(op_e7f9_0)(uae_u32 opcode) /* ROLW */
28101: {
28102: OpcodeFamily = 76; CurrentInstrCycles = 20;
28103: {{ uaecptr dataa = get_ilong(2);
28104: { uae_s16 data = get_word(dataa);
28105: { uae_u16 val = data;
28106: uae_u32 carry = val & 0x8000;
28107: val <<= 1;
28108: if (carry) val |= 1;
28109: CLEAR_CZNV;
28110: SET_ZFLG (((uae_s16)(val)) == 0);
28111: SET_NFLG (((uae_s16)(val)) < 0);
28112: SET_CFLG (carry >> 15);
28113: put_word(dataa,val);
28114: }}}}m68k_incpc(6);
28115: return 20;
28116: }
28117: unsigned long REGPARAM2 CPUFUNC(op_e8c0_0)(uae_u32 opcode) /* BFTST */
28118: {
28119: uae_u32 dstreg = opcode & 7;
28120: OpcodeFamily = 88; CurrentInstrCycles = 8;
28121: {{ uae_s16 extra = get_iword(2);
28122: {{ uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28123: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28124: uae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);
28125: tmp >>= (32 - width);
28126: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28127: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28128: }}}}m68k_incpc(4);
28129: return 8;
28130: }
28131: unsigned long REGPARAM2 CPUFUNC(op_e8d0_0)(uae_u32 opcode) /* BFTST */
28132: {
28133: uae_u32 dstreg = opcode & 7;
28134: OpcodeFamily = 88; CurrentInstrCycles = 8;
28135: {{ uae_s16 extra = get_iword(2);
28136: { uaecptr dsta = m68k_areg(regs, dstreg);
28137: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28138: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28139: uae_u32 tmp,bf0,bf1;
28140: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28141: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28142: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28143: tmp >>= (32 - width);
28144: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28145: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28146: }}}}m68k_incpc(4);
28147: return 8;
28148: }
28149: unsigned long REGPARAM2 CPUFUNC(op_e8e8_0)(uae_u32 opcode) /* BFTST */
28150: {
28151: uae_u32 dstreg = opcode & 7;
28152: OpcodeFamily = 88; CurrentInstrCycles = 12;
28153: {{ uae_s16 extra = get_iword(2);
28154: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
28155: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28156: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28157: uae_u32 tmp,bf0,bf1;
28158: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28159: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28160: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28161: tmp >>= (32 - width);
28162: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28163: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28164: }}}}m68k_incpc(6);
28165: return 12;
28166: }
28167: unsigned long REGPARAM2 CPUFUNC(op_e8f0_0)(uae_u32 opcode) /* BFTST */
28168: {
28169: uae_u32 dstreg = opcode & 7;
28170: OpcodeFamily = 88; CurrentInstrCycles = 14;
28171: {{ uae_s16 extra = get_iword(2);
28172: {m68k_incpc(4);
28173: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
28174: BusCyclePenalty += 2;
28175: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28176: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28177: uae_u32 tmp,bf0,bf1;
28178: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28179: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28180: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28181: tmp >>= (32 - width);
28182: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28183: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28184: }}}}}return 14;
28185: }
28186: unsigned long REGPARAM2 CPUFUNC(op_e8f8_0)(uae_u32 opcode) /* BFTST */
28187: {
28188: OpcodeFamily = 88; CurrentInstrCycles = 12;
28189: {{ uae_s16 extra = get_iword(2);
28190: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
28191: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28192: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28193: uae_u32 tmp,bf0,bf1;
28194: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28195: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28196: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28197: tmp >>= (32 - width);
28198: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28199: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28200: }}}}m68k_incpc(6);
28201: return 12;
28202: }
28203: unsigned long REGPARAM2 CPUFUNC(op_e8f9_0)(uae_u32 opcode) /* BFTST */
28204: {
28205: OpcodeFamily = 88; CurrentInstrCycles = 16;
28206: {{ uae_s16 extra = get_iword(2);
28207: { uaecptr dsta = get_ilong(4);
28208: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28209: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28210: uae_u32 tmp,bf0,bf1;
28211: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28212: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28213: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28214: tmp >>= (32 - width);
28215: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28216: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28217: }}}}m68k_incpc(8);
28218: return 16;
28219: }
28220: unsigned long REGPARAM2 CPUFUNC(op_e8fa_0)(uae_u32 opcode) /* BFTST */
28221: {
28222: uae_u32 dstreg = 2;
28223: OpcodeFamily = 88; CurrentInstrCycles = 12;
28224: {{ uae_s16 extra = get_iword(2);
28225: { uaecptr dsta = m68k_getpc () + 4;
28226: dsta += (uae_s32)(uae_s16)get_iword(4);
28227: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28228: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28229: uae_u32 tmp,bf0,bf1;
28230: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28231: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28232: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28233: tmp >>= (32 - width);
28234: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28235: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28236: }}}}m68k_incpc(6);
28237: return 12;
28238: }
28239: unsigned long REGPARAM2 CPUFUNC(op_e8fb_0)(uae_u32 opcode) /* BFTST */
28240: {
28241: uae_u32 dstreg = 3;
28242: OpcodeFamily = 88; CurrentInstrCycles = 14;
28243: {{ uae_s16 extra = get_iword(2);
28244: {m68k_incpc(4);
28245: { uaecptr tmppc = m68k_getpc();
28246: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
28247: BusCyclePenalty += 2;
28248: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28249: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28250: uae_u32 tmp,bf0,bf1;
28251: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28252: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28253: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28254: tmp >>= (32 - width);
28255: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28256: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28257: }}}}}return 14;
28258: }
28259: unsigned long REGPARAM2 CPUFUNC(op_e9c0_0)(uae_u32 opcode) /* BFEXTU */
28260: {
28261: uae_u32 dstreg = opcode & 7;
28262: OpcodeFamily = 89; CurrentInstrCycles = 8;
28263: {{ uae_s16 extra = get_iword(2);
28264: {{ uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28265: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28266: uae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);
28267: tmp >>= (32 - width);
28268: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28269: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28270: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28271: }}}}m68k_incpc(4);
28272: return 8;
28273: }
28274: unsigned long REGPARAM2 CPUFUNC(op_e9d0_0)(uae_u32 opcode) /* BFEXTU */
28275: {
28276: uae_u32 dstreg = opcode & 7;
28277: OpcodeFamily = 89; CurrentInstrCycles = 8;
28278: {{ uae_s16 extra = get_iword(2);
28279: { uaecptr dsta = m68k_areg(regs, dstreg);
28280: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28281: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28282: uae_u32 tmp,bf0,bf1;
28283: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28284: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28285: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28286: tmp >>= (32 - width);
28287: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28288: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28289: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28290: }}}}m68k_incpc(4);
28291: return 8;
28292: }
28293: unsigned long REGPARAM2 CPUFUNC(op_e9e8_0)(uae_u32 opcode) /* BFEXTU */
28294: {
28295: uae_u32 dstreg = opcode & 7;
28296: OpcodeFamily = 89; CurrentInstrCycles = 12;
28297: {{ uae_s16 extra = get_iword(2);
28298: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
28299: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28300: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28301: uae_u32 tmp,bf0,bf1;
28302: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28303: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28304: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28305: tmp >>= (32 - width);
28306: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28307: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28308: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28309: }}}}m68k_incpc(6);
28310: return 12;
28311: }
28312: unsigned long REGPARAM2 CPUFUNC(op_e9f0_0)(uae_u32 opcode) /* BFEXTU */
28313: {
28314: uae_u32 dstreg = opcode & 7;
28315: OpcodeFamily = 89; CurrentInstrCycles = 14;
28316: {{ uae_s16 extra = get_iword(2);
28317: {m68k_incpc(4);
28318: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
28319: BusCyclePenalty += 2;
28320: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28321: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28322: uae_u32 tmp,bf0,bf1;
28323: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28324: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28325: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28326: tmp >>= (32 - width);
28327: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28328: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28329: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28330: }}}}}return 14;
28331: }
28332: unsigned long REGPARAM2 CPUFUNC(op_e9f8_0)(uae_u32 opcode) /* BFEXTU */
28333: {
28334: OpcodeFamily = 89; CurrentInstrCycles = 12;
28335: {{ uae_s16 extra = get_iword(2);
28336: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
28337: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28338: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28339: uae_u32 tmp,bf0,bf1;
28340: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28341: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28342: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28343: tmp >>= (32 - width);
28344: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28345: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28346: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28347: }}}}m68k_incpc(6);
28348: return 12;
28349: }
28350: unsigned long REGPARAM2 CPUFUNC(op_e9f9_0)(uae_u32 opcode) /* BFEXTU */
28351: {
28352: OpcodeFamily = 89; CurrentInstrCycles = 16;
28353: {{ uae_s16 extra = get_iword(2);
28354: { uaecptr dsta = get_ilong(4);
28355: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28356: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28357: uae_u32 tmp,bf0,bf1;
28358: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28359: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28360: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28361: tmp >>= (32 - width);
28362: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28363: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28364: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28365: }}}}m68k_incpc(8);
28366: return 16;
28367: }
28368: unsigned long REGPARAM2 CPUFUNC(op_e9fa_0)(uae_u32 opcode) /* BFEXTU */
28369: {
28370: uae_u32 dstreg = 2;
28371: OpcodeFamily = 89; CurrentInstrCycles = 12;
28372: {{ uae_s16 extra = get_iword(2);
28373: { uaecptr dsta = m68k_getpc () + 4;
28374: dsta += (uae_s32)(uae_s16)get_iword(4);
28375: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28376: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28377: uae_u32 tmp,bf0,bf1;
28378: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28379: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28380: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28381: tmp >>= (32 - width);
28382: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28383: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28384: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28385: }}}}m68k_incpc(6);
28386: return 12;
28387: }
28388: unsigned long REGPARAM2 CPUFUNC(op_e9fb_0)(uae_u32 opcode) /* BFEXTU */
28389: {
28390: uae_u32 dstreg = 3;
28391: OpcodeFamily = 89; CurrentInstrCycles = 14;
28392: {{ uae_s16 extra = get_iword(2);
28393: {m68k_incpc(4);
28394: { uaecptr tmppc = m68k_getpc();
28395: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
28396: BusCyclePenalty += 2;
28397: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28398: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28399: uae_u32 tmp,bf0,bf1;
28400: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28401: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28402: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28403: tmp >>= (32 - width);
28404: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28405: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28406: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28407: }}}}}return 14;
28408: }
28409: unsigned long REGPARAM2 CPUFUNC(op_eac0_0)(uae_u32 opcode) /* BFCHG */
28410: {
28411: uae_u32 dstreg = opcode & 7;
28412: OpcodeFamily = 90; CurrentInstrCycles = 8;
28413: {{ uae_s16 extra = get_iword(2);
28414: {{ uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28415: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28416: uae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);
28417: tmp >>= (32 - width);
28418: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28419: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28420: tmp = ~tmp;
28421: tmp <<= (32 - width);
28422: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :
28423: (0xffffffff << (32 - (offset & 0x1f))))) |
28424: (tmp >> (offset & 0x1f)) |
28425: (((offset & 0x1f) + width) >= 32 ? 0 :
28426: (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));
28427: }}}}m68k_incpc(4);
28428: return 8;
28429: }
28430: unsigned long REGPARAM2 CPUFUNC(op_ead0_0)(uae_u32 opcode) /* BFCHG */
28431: {
28432: uae_u32 dstreg = opcode & 7;
28433: OpcodeFamily = 90; CurrentInstrCycles = 8;
28434: {{ uae_s16 extra = get_iword(2);
28435: { uaecptr dsta = m68k_areg(regs, dstreg);
28436: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28437: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28438: uae_u32 tmp,bf0,bf1;
28439: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28440: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28441: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28442: tmp >>= (32 - width);
28443: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28444: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28445: tmp = ~tmp;
28446: tmp <<= (32 - width);
28447: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28448: (tmp >> (offset & 7)) |
28449: (((offset & 7) + width) >= 32 ? 0 :
28450: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28451: put_long(dsta,bf0 );
28452: if (((offset & 7) + width) > 32) {
28453: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28454: (tmp << (8 - (offset & 7)));
28455: put_byte(dsta+4,bf1);
28456: }
28457: }}}}m68k_incpc(4);
28458: return 8;
28459: }
28460: unsigned long REGPARAM2 CPUFUNC(op_eae8_0)(uae_u32 opcode) /* BFCHG */
28461: {
28462: uae_u32 dstreg = opcode & 7;
28463: OpcodeFamily = 90; CurrentInstrCycles = 12;
28464: {{ uae_s16 extra = get_iword(2);
28465: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
28466: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28467: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28468: uae_u32 tmp,bf0,bf1;
28469: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28470: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28471: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28472: tmp >>= (32 - width);
28473: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28474: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28475: tmp = ~tmp;
28476: tmp <<= (32 - width);
28477: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28478: (tmp >> (offset & 7)) |
28479: (((offset & 7) + width) >= 32 ? 0 :
28480: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28481: put_long(dsta,bf0 );
28482: if (((offset & 7) + width) > 32) {
28483: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28484: (tmp << (8 - (offset & 7)));
28485: put_byte(dsta+4,bf1);
28486: }
28487: }}}}m68k_incpc(6);
28488: return 12;
28489: }
28490: unsigned long REGPARAM2 CPUFUNC(op_eaf0_0)(uae_u32 opcode) /* BFCHG */
28491: {
28492: uae_u32 dstreg = opcode & 7;
28493: OpcodeFamily = 90; CurrentInstrCycles = 14;
28494: {{ uae_s16 extra = get_iword(2);
28495: {m68k_incpc(4);
28496: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
28497: BusCyclePenalty += 2;
28498: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28499: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28500: uae_u32 tmp,bf0,bf1;
28501: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28502: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28503: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28504: tmp >>= (32 - width);
28505: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28506: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28507: tmp = ~tmp;
28508: tmp <<= (32 - width);
28509: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28510: (tmp >> (offset & 7)) |
28511: (((offset & 7) + width) >= 32 ? 0 :
28512: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28513: put_long(dsta,bf0 );
28514: if (((offset & 7) + width) > 32) {
28515: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28516: (tmp << (8 - (offset & 7)));
28517: put_byte(dsta+4,bf1);
28518: }
28519: }}}}}return 14;
28520: }
28521: unsigned long REGPARAM2 CPUFUNC(op_eaf8_0)(uae_u32 opcode) /* BFCHG */
28522: {
28523: OpcodeFamily = 90; CurrentInstrCycles = 12;
28524: {{ uae_s16 extra = get_iword(2);
28525: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
28526: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28527: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28528: uae_u32 tmp,bf0,bf1;
28529: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28530: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28531: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28532: tmp >>= (32 - width);
28533: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28534: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28535: tmp = ~tmp;
28536: tmp <<= (32 - width);
28537: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28538: (tmp >> (offset & 7)) |
28539: (((offset & 7) + width) >= 32 ? 0 :
28540: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28541: put_long(dsta,bf0 );
28542: if (((offset & 7) + width) > 32) {
28543: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28544: (tmp << (8 - (offset & 7)));
28545: put_byte(dsta+4,bf1);
28546: }
28547: }}}}m68k_incpc(6);
28548: return 12;
28549: }
28550: unsigned long REGPARAM2 CPUFUNC(op_eaf9_0)(uae_u32 opcode) /* BFCHG */
28551: {
28552: OpcodeFamily = 90; CurrentInstrCycles = 16;
28553: {{ uae_s16 extra = get_iword(2);
28554: { uaecptr dsta = get_ilong(4);
28555: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28556: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28557: uae_u32 tmp,bf0,bf1;
28558: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28559: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28560: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28561: tmp >>= (32 - width);
28562: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28563: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28564: tmp = ~tmp;
28565: tmp <<= (32 - width);
28566: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28567: (tmp >> (offset & 7)) |
28568: (((offset & 7) + width) >= 32 ? 0 :
28569: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28570: put_long(dsta,bf0 );
28571: if (((offset & 7) + width) > 32) {
28572: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28573: (tmp << (8 - (offset & 7)));
28574: put_byte(dsta+4,bf1);
28575: }
28576: }}}}m68k_incpc(8);
28577: return 16;
28578: }
28579: unsigned long REGPARAM2 CPUFUNC(op_ebc0_0)(uae_u32 opcode) /* BFEXTS */
28580: {
28581: uae_u32 dstreg = opcode & 7;
28582: OpcodeFamily = 91; CurrentInstrCycles = 8;
28583: {{ uae_s16 extra = get_iword(2);
28584: {{ uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28585: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28586: uae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);
28587: tmp >>= (32 - width);
28588: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28589: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28590: if (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);
28591: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28592: }}}}m68k_incpc(4);
28593: return 8;
28594: }
28595: unsigned long REGPARAM2 CPUFUNC(op_ebd0_0)(uae_u32 opcode) /* BFEXTS */
28596: {
28597: uae_u32 dstreg = opcode & 7;
28598: OpcodeFamily = 91; CurrentInstrCycles = 8;
28599: {{ uae_s16 extra = get_iword(2);
28600: { uaecptr dsta = m68k_areg(regs, dstreg);
28601: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28602: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28603: uae_u32 tmp,bf0,bf1;
28604: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28605: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28606: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28607: tmp >>= (32 - width);
28608: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28609: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28610: if (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);
28611: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28612: }}}}m68k_incpc(4);
28613: return 8;
28614: }
28615: unsigned long REGPARAM2 CPUFUNC(op_ebe8_0)(uae_u32 opcode) /* BFEXTS */
28616: {
28617: uae_u32 dstreg = opcode & 7;
28618: OpcodeFamily = 91; CurrentInstrCycles = 12;
28619: {{ uae_s16 extra = get_iword(2);
28620: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
28621: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28622: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28623: uae_u32 tmp,bf0,bf1;
28624: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28625: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28626: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28627: tmp >>= (32 - width);
28628: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28629: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28630: if (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);
28631: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28632: }}}}m68k_incpc(6);
28633: return 12;
28634: }
28635: unsigned long REGPARAM2 CPUFUNC(op_ebf0_0)(uae_u32 opcode) /* BFEXTS */
28636: {
28637: uae_u32 dstreg = opcode & 7;
28638: OpcodeFamily = 91; CurrentInstrCycles = 14;
28639: {{ uae_s16 extra = get_iword(2);
28640: {m68k_incpc(4);
28641: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
28642: BusCyclePenalty += 2;
28643: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28644: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28645: uae_u32 tmp,bf0,bf1;
28646: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28647: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28648: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28649: tmp >>= (32 - width);
28650: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28651: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28652: if (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);
28653: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28654: }}}}}return 14;
28655: }
28656: unsigned long REGPARAM2 CPUFUNC(op_ebf8_0)(uae_u32 opcode) /* BFEXTS */
28657: {
28658: OpcodeFamily = 91; CurrentInstrCycles = 12;
28659: {{ uae_s16 extra = get_iword(2);
28660: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
28661: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28662: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28663: uae_u32 tmp,bf0,bf1;
28664: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28665: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28666: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28667: tmp >>= (32 - width);
28668: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28669: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28670: if (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);
28671: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28672: }}}}m68k_incpc(6);
28673: return 12;
28674: }
28675: unsigned long REGPARAM2 CPUFUNC(op_ebf9_0)(uae_u32 opcode) /* BFEXTS */
28676: {
28677: OpcodeFamily = 91; CurrentInstrCycles = 16;
28678: {{ uae_s16 extra = get_iword(2);
28679: { uaecptr dsta = get_ilong(4);
28680: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28681: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28682: uae_u32 tmp,bf0,bf1;
28683: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28684: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28685: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28686: tmp >>= (32 - width);
28687: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28688: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28689: if (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);
28690: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28691: }}}}m68k_incpc(8);
28692: return 16;
28693: }
28694: unsigned long REGPARAM2 CPUFUNC(op_ebfa_0)(uae_u32 opcode) /* BFEXTS */
28695: {
28696: uae_u32 dstreg = 2;
28697: OpcodeFamily = 91; CurrentInstrCycles = 12;
28698: {{ uae_s16 extra = get_iword(2);
28699: { uaecptr dsta = m68k_getpc () + 4;
28700: dsta += (uae_s32)(uae_s16)get_iword(4);
28701: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28702: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28703: uae_u32 tmp,bf0,bf1;
28704: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28705: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28706: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28707: tmp >>= (32 - width);
28708: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28709: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28710: if (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);
28711: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28712: }}}}m68k_incpc(6);
28713: return 12;
28714: }
28715: unsigned long REGPARAM2 CPUFUNC(op_ebfb_0)(uae_u32 opcode) /* BFEXTS */
28716: {
28717: uae_u32 dstreg = 3;
28718: OpcodeFamily = 91; CurrentInstrCycles = 14;
28719: {{ uae_s16 extra = get_iword(2);
28720: {m68k_incpc(4);
28721: { uaecptr tmppc = m68k_getpc();
28722: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
28723: BusCyclePenalty += 2;
28724: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28725: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28726: uae_u32 tmp,bf0,bf1;
28727: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28728: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28729: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28730: tmp >>= (32 - width);
28731: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28732: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28733: if (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);
28734: m68k_dreg(regs, (extra >> 12) & 7) = tmp;
28735: }}}}}return 14;
28736: }
28737: unsigned long REGPARAM2 CPUFUNC(op_ecc0_0)(uae_u32 opcode) /* BFCLR */
28738: {
28739: uae_u32 dstreg = opcode & 7;
28740: OpcodeFamily = 92; CurrentInstrCycles = 8;
28741: {{ uae_s16 extra = get_iword(2);
28742: {{ uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28743: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28744: uae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);
28745: tmp >>= (32 - width);
28746: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28747: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28748: tmp = 0;
28749: tmp <<= (32 - width);
28750: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :
28751: (0xffffffff << (32 - (offset & 0x1f))))) |
28752: (tmp >> (offset & 0x1f)) |
28753: (((offset & 0x1f) + width) >= 32 ? 0 :
28754: (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));
28755: }}}}m68k_incpc(4);
28756: return 8;
28757: }
28758: unsigned long REGPARAM2 CPUFUNC(op_ecd0_0)(uae_u32 opcode) /* BFCLR */
28759: {
28760: uae_u32 dstreg = opcode & 7;
28761: OpcodeFamily = 92; CurrentInstrCycles = 8;
28762: {{ uae_s16 extra = get_iword(2);
28763: { uaecptr dsta = m68k_areg(regs, dstreg);
28764: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28765: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28766: uae_u32 tmp,bf0,bf1;
28767: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28768: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28769: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28770: tmp >>= (32 - width);
28771: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28772: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28773: tmp = 0;
28774: tmp <<= (32 - width);
28775: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28776: (tmp >> (offset & 7)) |
28777: (((offset & 7) + width) >= 32 ? 0 :
28778: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28779: put_long(dsta,bf0 );
28780: if (((offset & 7) + width) > 32) {
28781: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28782: (tmp << (8 - (offset & 7)));
28783: put_byte(dsta+4,bf1);
28784: }
28785: }}}}m68k_incpc(4);
28786: return 8;
28787: }
28788: unsigned long REGPARAM2 CPUFUNC(op_ece8_0)(uae_u32 opcode) /* BFCLR */
28789: {
28790: uae_u32 dstreg = opcode & 7;
28791: OpcodeFamily = 92; CurrentInstrCycles = 12;
28792: {{ uae_s16 extra = get_iword(2);
28793: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
28794: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28795: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28796: uae_u32 tmp,bf0,bf1;
28797: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28798: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28799: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28800: tmp >>= (32 - width);
28801: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28802: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28803: tmp = 0;
28804: tmp <<= (32 - width);
28805: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28806: (tmp >> (offset & 7)) |
28807: (((offset & 7) + width) >= 32 ? 0 :
28808: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28809: put_long(dsta,bf0 );
28810: if (((offset & 7) + width) > 32) {
28811: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28812: (tmp << (8 - (offset & 7)));
28813: put_byte(dsta+4,bf1);
28814: }
28815: }}}}m68k_incpc(6);
28816: return 12;
28817: }
28818: unsigned long REGPARAM2 CPUFUNC(op_ecf0_0)(uae_u32 opcode) /* BFCLR */
28819: {
28820: uae_u32 dstreg = opcode & 7;
28821: OpcodeFamily = 92; CurrentInstrCycles = 14;
28822: {{ uae_s16 extra = get_iword(2);
28823: {m68k_incpc(4);
28824: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
28825: BusCyclePenalty += 2;
28826: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28827: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28828: uae_u32 tmp,bf0,bf1;
28829: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28830: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28831: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28832: tmp >>= (32 - width);
28833: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28834: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28835: tmp = 0;
28836: tmp <<= (32 - width);
28837: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28838: (tmp >> (offset & 7)) |
28839: (((offset & 7) + width) >= 32 ? 0 :
28840: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28841: put_long(dsta,bf0 );
28842: if (((offset & 7) + width) > 32) {
28843: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28844: (tmp << (8 - (offset & 7)));
28845: put_byte(dsta+4,bf1);
28846: }
28847: }}}}}return 14;
28848: }
28849: unsigned long REGPARAM2 CPUFUNC(op_ecf8_0)(uae_u32 opcode) /* BFCLR */
28850: {
28851: OpcodeFamily = 92; CurrentInstrCycles = 12;
28852: {{ uae_s16 extra = get_iword(2);
28853: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
28854: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28855: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28856: uae_u32 tmp,bf0,bf1;
28857: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28858: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28859: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28860: tmp >>= (32 - width);
28861: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28862: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28863: tmp = 0;
28864: tmp <<= (32 - width);
28865: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28866: (tmp >> (offset & 7)) |
28867: (((offset & 7) + width) >= 32 ? 0 :
28868: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28869: put_long(dsta,bf0 );
28870: if (((offset & 7) + width) > 32) {
28871: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28872: (tmp << (8 - (offset & 7)));
28873: put_byte(dsta+4,bf1);
28874: }
28875: }}}}m68k_incpc(6);
28876: return 12;
28877: }
28878: unsigned long REGPARAM2 CPUFUNC(op_ecf9_0)(uae_u32 opcode) /* BFCLR */
28879: {
28880: OpcodeFamily = 92; CurrentInstrCycles = 16;
28881: {{ uae_s16 extra = get_iword(2);
28882: { uaecptr dsta = get_ilong(4);
28883: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28884: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28885: uae_u32 tmp,bf0,bf1;
28886: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28887: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28888: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28889: tmp >>= (32 - width);
28890: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28891: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28892: tmp = 0;
28893: tmp <<= (32 - width);
28894: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
28895: (tmp >> (offset & 7)) |
28896: (((offset & 7) + width) >= 32 ? 0 :
28897: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
28898: put_long(dsta,bf0 );
28899: if (((offset & 7) + width) > 32) {
28900: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
28901: (tmp << (8 - (offset & 7)));
28902: put_byte(dsta+4,bf1);
28903: }
28904: }}}}m68k_incpc(8);
28905: return 16;
28906: }
28907: unsigned long REGPARAM2 CPUFUNC(op_edc0_0)(uae_u32 opcode) /* BFFFO */
28908: {
28909: uae_u32 dstreg = opcode & 7;
28910: OpcodeFamily = 93; CurrentInstrCycles = 8;
28911: {{ uae_s16 extra = get_iword(2);
28912: {{ uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28913: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28914: uae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);
28915: tmp >>= (32 - width);
28916: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28917: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28918: { uae_u32 mask = 1 << (width-1);
28919: while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
28920: m68k_dreg(regs, (extra >> 12) & 7) = offset;
28921: }}}}m68k_incpc(4);
28922: return 8;
28923: }
28924: unsigned long REGPARAM2 CPUFUNC(op_edd0_0)(uae_u32 opcode) /* BFFFO */
28925: {
28926: uae_u32 dstreg = opcode & 7;
28927: OpcodeFamily = 93; CurrentInstrCycles = 8;
28928: {{ uae_s16 extra = get_iword(2);
28929: { uaecptr dsta = m68k_areg(regs, dstreg);
28930: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28931: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28932: uae_u32 tmp,bf0,bf1;
28933: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28934: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28935: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28936: tmp >>= (32 - width);
28937: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28938: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28939: { uae_u32 mask = 1 << (width-1);
28940: while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
28941: m68k_dreg(regs, (extra >> 12) & 7) = offset;
28942: }}}}m68k_incpc(4);
28943: return 8;
28944: }
28945: unsigned long REGPARAM2 CPUFUNC(op_ede8_0)(uae_u32 opcode) /* BFFFO */
28946: {
28947: uae_u32 dstreg = opcode & 7;
28948: OpcodeFamily = 93; CurrentInstrCycles = 12;
28949: {{ uae_s16 extra = get_iword(2);
28950: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
28951: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28952: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28953: uae_u32 tmp,bf0,bf1;
28954: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28955: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28956: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28957: tmp >>= (32 - width);
28958: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28959: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28960: { uae_u32 mask = 1 << (width-1);
28961: while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
28962: m68k_dreg(regs, (extra >> 12) & 7) = offset;
28963: }}}}m68k_incpc(6);
28964: return 12;
28965: }
28966: unsigned long REGPARAM2 CPUFUNC(op_edf0_0)(uae_u32 opcode) /* BFFFO */
28967: {
28968: uae_u32 dstreg = opcode & 7;
28969: OpcodeFamily = 93; CurrentInstrCycles = 14;
28970: {{ uae_s16 extra = get_iword(2);
28971: {m68k_incpc(4);
28972: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
28973: BusCyclePenalty += 2;
28974: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28975: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28976: uae_u32 tmp,bf0,bf1;
28977: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28978: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28979: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28980: tmp >>= (32 - width);
28981: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
28982: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
28983: { uae_u32 mask = 1 << (width-1);
28984: while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
28985: m68k_dreg(regs, (extra >> 12) & 7) = offset;
28986: }}}}}return 14;
28987: }
28988: unsigned long REGPARAM2 CPUFUNC(op_edf8_0)(uae_u32 opcode) /* BFFFO */
28989: {
28990: OpcodeFamily = 93; CurrentInstrCycles = 12;
28991: {{ uae_s16 extra = get_iword(2);
28992: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
28993: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
28994: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
28995: uae_u32 tmp,bf0,bf1;
28996: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
28997: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
28998: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
28999: tmp >>= (32 - width);
29000: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29001: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29002: { uae_u32 mask = 1 << (width-1);
29003: while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
29004: m68k_dreg(regs, (extra >> 12) & 7) = offset;
29005: }}}}m68k_incpc(6);
29006: return 12;
29007: }
29008: unsigned long REGPARAM2 CPUFUNC(op_edf9_0)(uae_u32 opcode) /* BFFFO */
29009: {
29010: OpcodeFamily = 93; CurrentInstrCycles = 16;
29011: {{ uae_s16 extra = get_iword(2);
29012: { uaecptr dsta = get_ilong(4);
29013: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29014: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29015: uae_u32 tmp,bf0,bf1;
29016: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29017: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29018: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29019: tmp >>= (32 - width);
29020: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29021: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29022: { uae_u32 mask = 1 << (width-1);
29023: while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
29024: m68k_dreg(regs, (extra >> 12) & 7) = offset;
29025: }}}}m68k_incpc(8);
29026: return 16;
29027: }
29028: unsigned long REGPARAM2 CPUFUNC(op_edfa_0)(uae_u32 opcode) /* BFFFO */
29029: {
29030: uae_u32 dstreg = 2;
29031: OpcodeFamily = 93; CurrentInstrCycles = 12;
29032: {{ uae_s16 extra = get_iword(2);
29033: { uaecptr dsta = m68k_getpc () + 4;
29034: dsta += (uae_s32)(uae_s16)get_iword(4);
29035: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29036: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29037: uae_u32 tmp,bf0,bf1;
29038: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29039: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29040: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29041: tmp >>= (32 - width);
29042: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29043: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29044: { uae_u32 mask = 1 << (width-1);
29045: while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
29046: m68k_dreg(regs, (extra >> 12) & 7) = offset;
29047: }}}}m68k_incpc(6);
29048: return 12;
29049: }
29050: unsigned long REGPARAM2 CPUFUNC(op_edfb_0)(uae_u32 opcode) /* BFFFO */
29051: {
29052: uae_u32 dstreg = 3;
29053: OpcodeFamily = 93; CurrentInstrCycles = 14;
29054: {{ uae_s16 extra = get_iword(2);
29055: {m68k_incpc(4);
29056: { uaecptr tmppc = m68k_getpc();
29057: uaecptr dsta = get_disp_ea_020(tmppc, next_iword());
29058: BusCyclePenalty += 2;
29059: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29060: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29061: uae_u32 tmp,bf0,bf1;
29062: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29063: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29064: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29065: tmp >>= (32 - width);
29066: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29067: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29068: { uae_u32 mask = 1 << (width-1);
29069: while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
29070: m68k_dreg(regs, (extra >> 12) & 7) = offset;
29071: }}}}}return 14;
29072: }
29073: unsigned long REGPARAM2 CPUFUNC(op_eec0_0)(uae_u32 opcode) /* BFSET */
29074: {
29075: uae_u32 dstreg = opcode & 7;
29076: OpcodeFamily = 94; CurrentInstrCycles = 8;
29077: {{ uae_s16 extra = get_iword(2);
29078: {{ uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29079: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29080: uae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);
29081: tmp >>= (32 - width);
29082: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29083: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29084: tmp = 0xffffffff;
29085: tmp <<= (32 - width);
29086: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :
29087: (0xffffffff << (32 - (offset & 0x1f))))) |
29088: (tmp >> (offset & 0x1f)) |
29089: (((offset & 0x1f) + width) >= 32 ? 0 :
29090: (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));
29091: }}}}m68k_incpc(4);
29092: return 8;
29093: }
29094: unsigned long REGPARAM2 CPUFUNC(op_eed0_0)(uae_u32 opcode) /* BFSET */
29095: {
29096: uae_u32 dstreg = opcode & 7;
29097: OpcodeFamily = 94; CurrentInstrCycles = 8;
29098: {{ uae_s16 extra = get_iword(2);
29099: { uaecptr dsta = m68k_areg(regs, dstreg);
29100: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29101: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29102: uae_u32 tmp,bf0,bf1;
29103: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29104: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29105: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29106: tmp >>= (32 - width);
29107: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29108: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29109: tmp = 0xffffffff;
29110: tmp <<= (32 - width);
29111: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29112: (tmp >> (offset & 7)) |
29113: (((offset & 7) + width) >= 32 ? 0 :
29114: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29115: put_long(dsta,bf0 );
29116: if (((offset & 7) + width) > 32) {
29117: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29118: (tmp << (8 - (offset & 7)));
29119: put_byte(dsta+4,bf1);
29120: }
29121: }}}}m68k_incpc(4);
29122: return 8;
29123: }
29124: unsigned long REGPARAM2 CPUFUNC(op_eee8_0)(uae_u32 opcode) /* BFSET */
29125: {
29126: uae_u32 dstreg = opcode & 7;
29127: OpcodeFamily = 94; CurrentInstrCycles = 12;
29128: {{ uae_s16 extra = get_iword(2);
29129: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
29130: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29131: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29132: uae_u32 tmp,bf0,bf1;
29133: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29134: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29135: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29136: tmp >>= (32 - width);
29137: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29138: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29139: tmp = 0xffffffff;
29140: tmp <<= (32 - width);
29141: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29142: (tmp >> (offset & 7)) |
29143: (((offset & 7) + width) >= 32 ? 0 :
29144: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29145: put_long(dsta,bf0 );
29146: if (((offset & 7) + width) > 32) {
29147: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29148: (tmp << (8 - (offset & 7)));
29149: put_byte(dsta+4,bf1);
29150: }
29151: }}}}m68k_incpc(6);
29152: return 12;
29153: }
29154: unsigned long REGPARAM2 CPUFUNC(op_eef0_0)(uae_u32 opcode) /* BFSET */
29155: {
29156: uae_u32 dstreg = opcode & 7;
29157: OpcodeFamily = 94; CurrentInstrCycles = 14;
29158: {{ uae_s16 extra = get_iword(2);
29159: {m68k_incpc(4);
29160: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
29161: BusCyclePenalty += 2;
29162: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29163: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29164: uae_u32 tmp,bf0,bf1;
29165: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29166: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29167: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29168: tmp >>= (32 - width);
29169: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29170: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29171: tmp = 0xffffffff;
29172: tmp <<= (32 - width);
29173: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29174: (tmp >> (offset & 7)) |
29175: (((offset & 7) + width) >= 32 ? 0 :
29176: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29177: put_long(dsta,bf0 );
29178: if (((offset & 7) + width) > 32) {
29179: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29180: (tmp << (8 - (offset & 7)));
29181: put_byte(dsta+4,bf1);
29182: }
29183: }}}}}return 14;
29184: }
29185: unsigned long REGPARAM2 CPUFUNC(op_eef8_0)(uae_u32 opcode) /* BFSET */
29186: {
29187: OpcodeFamily = 94; CurrentInstrCycles = 12;
29188: {{ uae_s16 extra = get_iword(2);
29189: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
29190: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29191: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29192: uae_u32 tmp,bf0,bf1;
29193: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29194: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29195: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29196: tmp >>= (32 - width);
29197: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29198: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29199: tmp = 0xffffffff;
29200: tmp <<= (32 - width);
29201: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29202: (tmp >> (offset & 7)) |
29203: (((offset & 7) + width) >= 32 ? 0 :
29204: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29205: put_long(dsta,bf0 );
29206: if (((offset & 7) + width) > 32) {
29207: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29208: (tmp << (8 - (offset & 7)));
29209: put_byte(dsta+4,bf1);
29210: }
29211: }}}}m68k_incpc(6);
29212: return 12;
29213: }
29214: unsigned long REGPARAM2 CPUFUNC(op_eef9_0)(uae_u32 opcode) /* BFSET */
29215: {
29216: OpcodeFamily = 94; CurrentInstrCycles = 16;
29217: {{ uae_s16 extra = get_iword(2);
29218: { uaecptr dsta = get_ilong(4);
29219: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29220: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29221: uae_u32 tmp,bf0,bf1;
29222: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29223: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29224: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29225: tmp >>= (32 - width);
29226: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29227: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29228: tmp = 0xffffffff;
29229: tmp <<= (32 - width);
29230: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29231: (tmp >> (offset & 7)) |
29232: (((offset & 7) + width) >= 32 ? 0 :
29233: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29234: put_long(dsta,bf0 );
29235: if (((offset & 7) + width) > 32) {
29236: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29237: (tmp << (8 - (offset & 7)));
29238: put_byte(dsta+4,bf1);
29239: }
29240: }}}}m68k_incpc(8);
29241: return 16;
29242: }
29243: unsigned long REGPARAM2 CPUFUNC(op_efc0_0)(uae_u32 opcode) /* BFINS */
29244: {
29245: uae_u32 dstreg = opcode & 7;
29246: OpcodeFamily = 95; CurrentInstrCycles = 8;
29247: {{ uae_s16 extra = get_iword(2);
29248: {{ uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29249: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29250: uae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);
29251: tmp >>= (32 - width);
29252: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29253: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29254: tmp = m68k_dreg(regs, (extra >> 12) & 7);
29255: SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
29256: SET_ZFLG (tmp == 0);
29257: tmp <<= (32 - width);
29258: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :
29259: (0xffffffff << (32 - (offset & 0x1f))))) |
29260: (tmp >> (offset & 0x1f)) |
29261: (((offset & 0x1f) + width) >= 32 ? 0 :
29262: (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));
29263: }}}}m68k_incpc(4);
29264: return 8;
29265: }
29266: unsigned long REGPARAM2 CPUFUNC(op_efd0_0)(uae_u32 opcode) /* BFINS */
29267: {
29268: uae_u32 dstreg = opcode & 7;
29269: OpcodeFamily = 95; CurrentInstrCycles = 8;
29270: {{ uae_s16 extra = get_iword(2);
29271: { uaecptr dsta = m68k_areg(regs, dstreg);
29272: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29273: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29274: uae_u32 tmp,bf0,bf1;
29275: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29276: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29277: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29278: tmp >>= (32 - width);
29279: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29280: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29281: tmp = m68k_dreg(regs, (extra >> 12) & 7);
29282: SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
29283: SET_ZFLG (tmp == 0);
29284: tmp <<= (32 - width);
29285: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29286: (tmp >> (offset & 7)) |
29287: (((offset & 7) + width) >= 32 ? 0 :
29288: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29289: put_long(dsta,bf0 );
29290: if (((offset & 7) + width) > 32) {
29291: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29292: (tmp << (8 - (offset & 7)));
29293: put_byte(dsta+4,bf1);
29294: }
29295: }}}}m68k_incpc(4);
29296: return 8;
29297: }
29298: unsigned long REGPARAM2 CPUFUNC(op_efe8_0)(uae_u32 opcode) /* BFINS */
29299: {
29300: uae_u32 dstreg = opcode & 7;
29301: OpcodeFamily = 95; CurrentInstrCycles = 12;
29302: {{ uae_s16 extra = get_iword(2);
29303: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
29304: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29305: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29306: uae_u32 tmp,bf0,bf1;
29307: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29308: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29309: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29310: tmp >>= (32 - width);
29311: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29312: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29313: tmp = m68k_dreg(regs, (extra >> 12) & 7);
29314: SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
29315: SET_ZFLG (tmp == 0);
29316: tmp <<= (32 - width);
29317: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29318: (tmp >> (offset & 7)) |
29319: (((offset & 7) + width) >= 32 ? 0 :
29320: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29321: put_long(dsta,bf0 );
29322: if (((offset & 7) + width) > 32) {
29323: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29324: (tmp << (8 - (offset & 7)));
29325: put_byte(dsta+4,bf1);
29326: }
29327: }}}}m68k_incpc(6);
29328: return 12;
29329: }
29330: unsigned long REGPARAM2 CPUFUNC(op_eff0_0)(uae_u32 opcode) /* BFINS */
29331: {
29332: uae_u32 dstreg = opcode & 7;
29333: OpcodeFamily = 95; CurrentInstrCycles = 14;
29334: {{ uae_s16 extra = get_iword(2);
29335: {m68k_incpc(4);
29336: { uaecptr dsta = get_disp_ea_020(m68k_areg(regs, dstreg), next_iword());
29337: BusCyclePenalty += 2;
29338: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29339: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29340: uae_u32 tmp,bf0,bf1;
29341: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29342: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29343: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29344: tmp >>= (32 - width);
29345: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29346: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29347: tmp = m68k_dreg(regs, (extra >> 12) & 7);
29348: SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
29349: SET_ZFLG (tmp == 0);
29350: tmp <<= (32 - width);
29351: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29352: (tmp >> (offset & 7)) |
29353: (((offset & 7) + width) >= 32 ? 0 :
29354: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29355: put_long(dsta,bf0 );
29356: if (((offset & 7) + width) > 32) {
29357: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29358: (tmp << (8 - (offset & 7)));
29359: put_byte(dsta+4,bf1);
29360: }
29361: }}}}}return 14;
29362: }
29363: unsigned long REGPARAM2 CPUFUNC(op_eff8_0)(uae_u32 opcode) /* BFINS */
29364: {
29365: OpcodeFamily = 95; CurrentInstrCycles = 12;
29366: {{ uae_s16 extra = get_iword(2);
29367: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
29368: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29369: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29370: uae_u32 tmp,bf0,bf1;
29371: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29372: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29373: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29374: tmp >>= (32 - width);
29375: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29376: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29377: tmp = m68k_dreg(regs, (extra >> 12) & 7);
29378: SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
29379: SET_ZFLG (tmp == 0);
29380: tmp <<= (32 - width);
29381: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29382: (tmp >> (offset & 7)) |
29383: (((offset & 7) + width) >= 32 ? 0 :
29384: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29385: put_long(dsta,bf0 );
29386: if (((offset & 7) + width) > 32) {
29387: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29388: (tmp << (8 - (offset & 7)));
29389: put_byte(dsta+4,bf1);
29390: }
29391: }}}}m68k_incpc(6);
29392: return 12;
29393: }
29394: unsigned long REGPARAM2 CPUFUNC(op_eff9_0)(uae_u32 opcode) /* BFINS */
29395: {
29396: OpcodeFamily = 95; CurrentInstrCycles = 16;
29397: {{ uae_s16 extra = get_iword(2);
29398: { uaecptr dsta = get_ilong(4);
29399: { uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
29400: int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
29401: uae_u32 tmp,bf0,bf1;
29402: dsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);
29403: bf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;
29404: tmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));
29405: tmp >>= (32 - width);
29406: SET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);
29407: SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
29408: tmp = m68k_dreg(regs, (extra >> 12) & 7);
29409: SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
29410: SET_ZFLG (tmp == 0);
29411: tmp <<= (32 - width);
29412: bf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |
29413: (tmp >> (offset & 7)) |
29414: (((offset & 7) + width) >= 32 ? 0 :
29415: (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));
29416: put_long(dsta,bf0 );
29417: if (((offset & 7) + width) > 32) {
29418: bf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |
29419: (tmp << (8 - (offset & 7)));
29420: put_byte(dsta+4,bf1);
29421: }
29422: }}}}m68k_incpc(8);
29423: return 16;
29424: }
29425: unsigned long REGPARAM2 CPUFUNC(op_f200_0)(uae_u32 opcode) /* FPP */
29426: {
29427: uae_u32 dstreg = opcode & 7;
29428: OpcodeFamily = 104; CurrentInstrCycles = 8;
29429: {{ uae_s16 extra = get_iword(2);
29430: m68k_incpc(4);
29431: fpp_opp(opcode,extra);
29432: }}return 8;
29433: }
29434: unsigned long REGPARAM2 CPUFUNC(op_f208_0)(uae_u32 opcode) /* FPP */
29435: {
29436: uae_u32 dstreg = opcode & 7;
29437: OpcodeFamily = 104; CurrentInstrCycles = 8;
29438: {{ uae_s16 extra = get_iword(2);
29439: m68k_incpc(4);
29440: fpp_opp(opcode,extra);
29441: }}return 8;
29442: }
29443: unsigned long REGPARAM2 CPUFUNC(op_f210_0)(uae_u32 opcode) /* FPP */
29444: {
29445: uae_u32 dstreg = opcode & 7;
29446: OpcodeFamily = 104; CurrentInstrCycles = 8;
29447: {{ uae_s16 extra = get_iword(2);
29448: m68k_incpc(4);
29449: fpp_opp(opcode,extra);
29450: }}return 8;
29451: }
29452: unsigned long REGPARAM2 CPUFUNC(op_f218_0)(uae_u32 opcode) /* FPP */
29453: {
29454: uae_u32 dstreg = opcode & 7;
29455: OpcodeFamily = 104; CurrentInstrCycles = 8;
29456: {{ uae_s16 extra = get_iword(2);
29457: m68k_incpc(4);
29458: fpp_opp(opcode,extra);
29459: }}return 8;
29460: }
29461: unsigned long REGPARAM2 CPUFUNC(op_f220_0)(uae_u32 opcode) /* FPP */
29462: {
29463: uae_u32 dstreg = opcode & 7;
29464: OpcodeFamily = 104; CurrentInstrCycles = 8;
29465: {{ uae_s16 extra = get_iword(2);
29466: m68k_incpc(4);
29467: fpp_opp(opcode,extra);
29468: }}return 8;
29469: }
29470: unsigned long REGPARAM2 CPUFUNC(op_f228_0)(uae_u32 opcode) /* FPP */
29471: {
29472: uae_u32 dstreg = opcode & 7;
29473: OpcodeFamily = 104; CurrentInstrCycles = 8;
29474: {{ uae_s16 extra = get_iword(2);
29475: m68k_incpc(4);
29476: fpp_opp(opcode,extra);
29477: }}return 8;
29478: }
29479: unsigned long REGPARAM2 CPUFUNC(op_f230_0)(uae_u32 opcode) /* FPP */
29480: {
29481: uae_u32 dstreg = opcode & 7;
29482: OpcodeFamily = 104; CurrentInstrCycles = 8;
29483: {{ uae_s16 extra = get_iword(2);
29484: m68k_incpc(4);
29485: fpp_opp(opcode,extra);
29486: }}return 8;
29487: }
29488: unsigned long REGPARAM2 CPUFUNC(op_f238_0)(uae_u32 opcode) /* FPP */
29489: {
29490: OpcodeFamily = 104; CurrentInstrCycles = 8;
29491: {{ uae_s16 extra = get_iword(2);
29492: m68k_incpc(4);
29493: fpp_opp(opcode,extra);
29494: }}return 8;
29495: }
29496: unsigned long REGPARAM2 CPUFUNC(op_f239_0)(uae_u32 opcode) /* FPP */
29497: {
29498: OpcodeFamily = 104; CurrentInstrCycles = 8;
29499: {{ uae_s16 extra = get_iword(2);
29500: m68k_incpc(4);
29501: fpp_opp(opcode,extra);
29502: }}return 8;
29503: }
29504: unsigned long REGPARAM2 CPUFUNC(op_f23a_0)(uae_u32 opcode) /* FPP */
29505: {
29506: uae_u32 dstreg = 2;
29507: OpcodeFamily = 104; CurrentInstrCycles = 8;
29508: {{ uae_s16 extra = get_iword(2);
29509: m68k_incpc(4);
29510: fpp_opp(opcode,extra);
29511: }}return 8;
29512: }
29513: unsigned long REGPARAM2 CPUFUNC(op_f23b_0)(uae_u32 opcode) /* FPP */
29514: {
29515: uae_u32 dstreg = 3;
29516: OpcodeFamily = 104; CurrentInstrCycles = 8;
29517: {{ uae_s16 extra = get_iword(2);
29518: m68k_incpc(4);
29519: fpp_opp(opcode,extra);
29520: }}return 8;
29521: }
29522: unsigned long REGPARAM2 CPUFUNC(op_f23c_0)(uae_u32 opcode) /* FPP */
29523: {
29524: OpcodeFamily = 104; CurrentInstrCycles = 8;
29525: {{ uae_s16 extra = get_iword(2);
29526: m68k_incpc(4);
29527: fpp_opp(opcode,extra);
29528: }}return 8;
29529: }
29530: unsigned long REGPARAM2 CPUFUNC(op_f240_0)(uae_u32 opcode) /* FScc */
29531: {
29532: uae_u32 dstreg = opcode & 7;
29533: OpcodeFamily = 106; CurrentInstrCycles = 8;
29534: {{ uae_s16 extra = get_iword(2);
29535: m68k_incpc(4);
29536: fscc_opp(opcode,extra);
29537: }}return 8;
29538: }
29539: unsigned long REGPARAM2 CPUFUNC(op_f248_0)(uae_u32 opcode) /* FDBcc */
29540: {
29541: uae_u32 dstreg = opcode & 7;
29542: OpcodeFamily = 105; CurrentInstrCycles = 8;
29543: {{ uae_s16 extra = get_iword(2);
29544: m68k_incpc(4);
29545: fdbcc_opp(opcode,extra);
29546: }}return 8;
29547: }
29548: unsigned long REGPARAM2 CPUFUNC(op_f250_0)(uae_u32 opcode) /* FScc */
29549: {
29550: uae_u32 dstreg = opcode & 7;
29551: OpcodeFamily = 106; CurrentInstrCycles = 8;
29552: {{ uae_s16 extra = get_iword(2);
29553: m68k_incpc(4);
29554: fscc_opp(opcode,extra);
29555: }}return 8;
29556: }
29557: unsigned long REGPARAM2 CPUFUNC(op_f258_0)(uae_u32 opcode) /* FScc */
29558: {
29559: uae_u32 dstreg = opcode & 7;
29560: OpcodeFamily = 106; CurrentInstrCycles = 8;
29561: {{ uae_s16 extra = get_iword(2);
29562: m68k_incpc(4);
29563: fscc_opp(opcode,extra);
29564: }}return 8;
29565: }
29566: unsigned long REGPARAM2 CPUFUNC(op_f260_0)(uae_u32 opcode) /* FScc */
29567: {
29568: uae_u32 dstreg = opcode & 7;
29569: OpcodeFamily = 106; CurrentInstrCycles = 8;
29570: {{ uae_s16 extra = get_iword(2);
29571: m68k_incpc(4);
29572: fscc_opp(opcode,extra);
29573: }}return 8;
29574: }
29575: unsigned long REGPARAM2 CPUFUNC(op_f268_0)(uae_u32 opcode) /* FScc */
29576: {
29577: uae_u32 dstreg = opcode & 7;
29578: OpcodeFamily = 106; CurrentInstrCycles = 8;
29579: {{ uae_s16 extra = get_iword(2);
29580: m68k_incpc(4);
29581: fscc_opp(opcode,extra);
29582: }}return 8;
29583: }
29584: unsigned long REGPARAM2 CPUFUNC(op_f270_0)(uae_u32 opcode) /* FScc */
29585: {
29586: uae_u32 dstreg = opcode & 7;
29587: OpcodeFamily = 106; CurrentInstrCycles = 8;
29588: {{ uae_s16 extra = get_iword(2);
29589: m68k_incpc(4);
29590: fscc_opp(opcode,extra);
29591: }}return 8;
29592: }
29593: unsigned long REGPARAM2 CPUFUNC(op_f278_0)(uae_u32 opcode) /* FScc */
29594: {
29595: OpcodeFamily = 106; CurrentInstrCycles = 8;
29596: {{ uae_s16 extra = get_iword(2);
29597: m68k_incpc(4);
29598: fscc_opp(opcode,extra);
29599: }}return 8;
29600: }
29601: unsigned long REGPARAM2 CPUFUNC(op_f279_0)(uae_u32 opcode) /* FScc */
29602: {
29603: OpcodeFamily = 106; CurrentInstrCycles = 8;
29604: {{ uae_s16 extra = get_iword(2);
29605: m68k_incpc(4);
29606: fscc_opp(opcode,extra);
29607: }}return 8;
29608: }
29609: unsigned long REGPARAM2 CPUFUNC(op_f27a_0)(uae_u32 opcode) /* FTRAPcc */
29610: {
29611: OpcodeFamily = 107; CurrentInstrCycles = 8;
29612: {m68k_incpc(2);
29613: { uaecptr oldpc = m68k_getpc();
29614: { uae_s16 dummy = get_iword(0);
29615: m68k_incpc(2);
29616: ftrapcc_opp(opcode,oldpc);
29617: }}}return 8;
29618: }
29619: unsigned long REGPARAM2 CPUFUNC(op_f27b_0)(uae_u32 opcode) /* FTRAPcc */
29620: {
29621: OpcodeFamily = 107; CurrentInstrCycles = 12;
29622: {m68k_incpc(2);
29623: { uaecptr oldpc = m68k_getpc();
29624: { uae_s32 dummy = get_ilong(0);
29625: m68k_incpc(4);
29626: ftrapcc_opp(opcode,oldpc);
29627: }}}return 12;
29628: }
29629: unsigned long REGPARAM2 CPUFUNC(op_f27c_0)(uae_u32 opcode) /* FTRAPcc */
29630: {
29631: OpcodeFamily = 107; CurrentInstrCycles = 4;
29632: {m68k_incpc(2);
29633: { uaecptr oldpc = m68k_getpc();
29634: ftrapcc_opp(opcode,oldpc);
29635: }}return 4;
29636: }
29637: unsigned long REGPARAM2 CPUFUNC(op_f280_0)(uae_u32 opcode) /* FBcc */
29638: {
29639: uae_u32 srcreg = (opcode & 63);
29640: OpcodeFamily = 108; CurrentInstrCycles = 8;
29641: {m68k_incpc(2);
29642: { uaecptr pc = m68k_getpc();
29643: { uae_s16 extra = get_iword(0);
29644: m68k_incpc(2);
29645: fbcc_opp(opcode,pc,extra);
29646: }}}return 8;
29647: }
29648: unsigned long REGPARAM2 CPUFUNC(op_f2c0_0)(uae_u32 opcode) /* FBcc */
29649: {
29650: uae_u32 srcreg = (opcode & 63);
29651: OpcodeFamily = 108; CurrentInstrCycles = 12;
29652: {m68k_incpc(2);
29653: { uaecptr pc = m68k_getpc();
29654: { uae_s32 extra = get_ilong(0);
29655: m68k_incpc(4);
29656: fbcc_opp(opcode,pc,extra);
29657: }}}return 12;
29658: }
29659: unsigned long REGPARAM2 CPUFUNC(op_f310_0)(uae_u32 opcode) /* FSAVE */
29660: {
29661: uae_u32 srcreg = (opcode & 7);
29662: OpcodeFamily = 109; CurrentInstrCycles = 4;
29663: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1835; }
29664: {m68k_incpc(2);
29665: fsave_opp(opcode);
29666: }}endlabel1835: ;
29667: return 4;
29668: }
29669: unsigned long REGPARAM2 CPUFUNC(op_f320_0)(uae_u32 opcode) /* FSAVE */
29670: {
29671: uae_u32 srcreg = (opcode & 7);
29672: OpcodeFamily = 109; CurrentInstrCycles = 4;
29673: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1836; }
29674: {m68k_incpc(2);
29675: fsave_opp(opcode);
29676: }}endlabel1836: ;
29677: return 4;
29678: }
29679: unsigned long REGPARAM2 CPUFUNC(op_f328_0)(uae_u32 opcode) /* FSAVE */
29680: {
29681: uae_u32 srcreg = (opcode & 7);
29682: OpcodeFamily = 109; CurrentInstrCycles = 4;
29683: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1837; }
29684: {m68k_incpc(2);
29685: fsave_opp(opcode);
29686: }}endlabel1837: ;
29687: return 4;
29688: }
29689: unsigned long REGPARAM2 CPUFUNC(op_f330_0)(uae_u32 opcode) /* FSAVE */
29690: {
29691: uae_u32 srcreg = (opcode & 7);
29692: OpcodeFamily = 109; CurrentInstrCycles = 4;
29693: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1838; }
29694: {m68k_incpc(2);
29695: fsave_opp(opcode);
29696: }}endlabel1838: ;
29697: return 4;
29698: }
29699: unsigned long REGPARAM2 CPUFUNC(op_f338_0)(uae_u32 opcode) /* FSAVE */
29700: {
29701: OpcodeFamily = 109; CurrentInstrCycles = 4;
29702: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1839; }
29703: {m68k_incpc(2);
29704: fsave_opp(opcode);
29705: }}endlabel1839: ;
29706: return 4;
29707: }
29708: unsigned long REGPARAM2 CPUFUNC(op_f339_0)(uae_u32 opcode) /* FSAVE */
29709: {
29710: OpcodeFamily = 109; CurrentInstrCycles = 4;
29711: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1840; }
29712: {m68k_incpc(2);
29713: fsave_opp(opcode);
29714: }}endlabel1840: ;
29715: return 4;
29716: }
29717: unsigned long REGPARAM2 CPUFUNC(op_f350_0)(uae_u32 opcode) /* FRESTORE */
29718: {
29719: uae_u32 srcreg = (opcode & 7);
29720: OpcodeFamily = 110; CurrentInstrCycles = 4;
29721: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1841; }
29722: {m68k_incpc(2);
29723: frestore_opp(opcode);
29724: }}endlabel1841: ;
29725: return 4;
29726: }
29727: unsigned long REGPARAM2 CPUFUNC(op_f358_0)(uae_u32 opcode) /* FRESTORE */
29728: {
29729: uae_u32 srcreg = (opcode & 7);
29730: OpcodeFamily = 110; CurrentInstrCycles = 4;
29731: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1842; }
29732: {m68k_incpc(2);
29733: frestore_opp(opcode);
29734: }}endlabel1842: ;
29735: return 4;
29736: }
29737: unsigned long REGPARAM2 CPUFUNC(op_f368_0)(uae_u32 opcode) /* FRESTORE */
29738: {
29739: uae_u32 srcreg = (opcode & 7);
29740: OpcodeFamily = 110; CurrentInstrCycles = 4;
29741: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1843; }
29742: {m68k_incpc(2);
29743: frestore_opp(opcode);
29744: }}endlabel1843: ;
29745: return 4;
29746: }
29747: unsigned long REGPARAM2 CPUFUNC(op_f370_0)(uae_u32 opcode) /* FRESTORE */
29748: {
29749: uae_u32 srcreg = (opcode & 7);
29750: OpcodeFamily = 110; CurrentInstrCycles = 4;
29751: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1844; }
29752: {m68k_incpc(2);
29753: frestore_opp(opcode);
29754: }}endlabel1844: ;
29755: return 4;
29756: }
29757: unsigned long REGPARAM2 CPUFUNC(op_f378_0)(uae_u32 opcode) /* FRESTORE */
29758: {
29759: OpcodeFamily = 110; CurrentInstrCycles = 4;
29760: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1845; }
29761: {m68k_incpc(2);
29762: frestore_opp(opcode);
29763: }}endlabel1845: ;
29764: return 4;
29765: }
29766: unsigned long REGPARAM2 CPUFUNC(op_f379_0)(uae_u32 opcode) /* FRESTORE */
29767: {
29768: OpcodeFamily = 110; CurrentInstrCycles = 4;
29769: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1846; }
29770: {m68k_incpc(2);
29771: frestore_opp(opcode);
29772: }}endlabel1846: ;
29773: return 4;
29774: }
29775: unsigned long REGPARAM2 CPUFUNC(op_f37a_0)(uae_u32 opcode) /* FRESTORE */
29776: {
29777: OpcodeFamily = 110; CurrentInstrCycles = 4;
29778: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1847; }
29779: {m68k_incpc(2);
29780: frestore_opp(opcode);
29781: }}endlabel1847: ;
29782: return 4;
29783: }
29784: unsigned long REGPARAM2 CPUFUNC(op_f37b_0)(uae_u32 opcode) /* FRESTORE */
29785: {
29786: OpcodeFamily = 110; CurrentInstrCycles = 4;
29787: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1848; }
29788: {m68k_incpc(2);
29789: frestore_opp(opcode);
29790: }}endlabel1848: ;
29791: return 4;
29792: }
29793: unsigned long REGPARAM2 CPUFUNC(op_f408_0)(uae_u32 opcode) /* CINVL */
29794: {
29795: uae_u32 srcreg = ((opcode >> 6) & 3);
29796: uae_u32 dstreg = opcode & 7;
29797: OpcodeFamily = 111; CurrentInstrCycles = 4;
29798: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1849; }
29799: {}}m68k_incpc(2);
29800: endlabel1849: ;
29801: return 4;
29802: }
29803: unsigned long REGPARAM2 CPUFUNC(op_f410_0)(uae_u32 opcode) /* CINVP */
29804: {
29805: uae_u32 srcreg = ((opcode >> 6) & 3);
29806: uae_u32 dstreg = opcode & 7;
29807: OpcodeFamily = 112; CurrentInstrCycles = 4;
29808: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1850; }
29809: {}}m68k_incpc(2);
29810: endlabel1850: ;
29811: return 4;
29812: }
29813: unsigned long REGPARAM2 CPUFUNC(op_f418_0)(uae_u32 opcode) /* CINVA */
29814: {
29815: uae_u32 srcreg = ((opcode >> 6) & 3);
29816: OpcodeFamily = 113; CurrentInstrCycles = 4;
29817: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1851; }
29818: {}}m68k_incpc(2);
29819: endlabel1851: ;
29820: return 4;
29821: }
29822: unsigned long REGPARAM2 CPUFUNC(op_f419_0)(uae_u32 opcode) /* CINVA */
29823: {
29824: uae_u32 srcreg = ((opcode >> 6) & 3);
29825: OpcodeFamily = 113; CurrentInstrCycles = 4;
29826: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1852; }
29827: {}}m68k_incpc(2);
29828: endlabel1852: ;
29829: return 4;
29830: }
29831: unsigned long REGPARAM2 CPUFUNC(op_f41a_0)(uae_u32 opcode) /* CINVA */
29832: {
29833: uae_u32 srcreg = ((opcode >> 6) & 3);
29834: OpcodeFamily = 113; CurrentInstrCycles = 4;
29835: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1853; }
29836: {}}m68k_incpc(2);
29837: endlabel1853: ;
29838: return 4;
29839: }
29840: unsigned long REGPARAM2 CPUFUNC(op_f41b_0)(uae_u32 opcode) /* CINVA */
29841: {
29842: uae_u32 srcreg = ((opcode >> 6) & 3);
29843: OpcodeFamily = 113; CurrentInstrCycles = 4;
29844: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1854; }
29845: {}}m68k_incpc(2);
29846: endlabel1854: ;
29847: return 4;
29848: }
29849: unsigned long REGPARAM2 CPUFUNC(op_f41c_0)(uae_u32 opcode) /* CINVA */
29850: {
29851: uae_u32 srcreg = ((opcode >> 6) & 3);
29852: OpcodeFamily = 113; CurrentInstrCycles = 4;
29853: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1855; }
29854: {}}m68k_incpc(2);
29855: endlabel1855: ;
29856: return 4;
29857: }
29858: unsigned long REGPARAM2 CPUFUNC(op_f41d_0)(uae_u32 opcode) /* CINVA */
29859: {
29860: uae_u32 srcreg = ((opcode >> 6) & 3);
29861: OpcodeFamily = 113; CurrentInstrCycles = 4;
29862: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1856; }
29863: {}}m68k_incpc(2);
29864: endlabel1856: ;
29865: return 4;
29866: }
29867: unsigned long REGPARAM2 CPUFUNC(op_f41e_0)(uae_u32 opcode) /* CINVA */
29868: {
29869: uae_u32 srcreg = ((opcode >> 6) & 3);
29870: OpcodeFamily = 113; CurrentInstrCycles = 4;
29871: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1857; }
29872: {}}m68k_incpc(2);
29873: endlabel1857: ;
29874: return 4;
29875: }
29876: unsigned long REGPARAM2 CPUFUNC(op_f41f_0)(uae_u32 opcode) /* CINVA */
29877: {
29878: uae_u32 srcreg = ((opcode >> 6) & 3);
29879: OpcodeFamily = 113; CurrentInstrCycles = 4;
29880: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1858; }
29881: {}}m68k_incpc(2);
29882: endlabel1858: ;
29883: return 4;
29884: }
29885: unsigned long REGPARAM2 CPUFUNC(op_f428_0)(uae_u32 opcode) /* CPUSHL */
29886: {
29887: uae_u32 srcreg = ((opcode >> 6) & 3);
29888: uae_u32 dstreg = opcode & 7;
29889: OpcodeFamily = 114; CurrentInstrCycles = 4;
29890: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1859; }
29891: {}}m68k_incpc(2);
29892: endlabel1859: ;
29893: return 4;
29894: }
29895: unsigned long REGPARAM2 CPUFUNC(op_f430_0)(uae_u32 opcode) /* CPUSHP */
29896: {
29897: uae_u32 srcreg = ((opcode >> 6) & 3);
29898: uae_u32 dstreg = opcode & 7;
29899: OpcodeFamily = 115; CurrentInstrCycles = 4;
29900: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1860; }
29901: {}}m68k_incpc(2);
29902: endlabel1860: ;
29903: return 4;
29904: }
29905: unsigned long REGPARAM2 CPUFUNC(op_f438_0)(uae_u32 opcode) /* CPUSHA */
29906: {
29907: uae_u32 srcreg = ((opcode >> 6) & 3);
29908: OpcodeFamily = 116; CurrentInstrCycles = 4;
29909: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1861; }
29910: {}}m68k_incpc(2);
29911: endlabel1861: ;
29912: return 4;
29913: }
29914: unsigned long REGPARAM2 CPUFUNC(op_f439_0)(uae_u32 opcode) /* CPUSHA */
29915: {
29916: uae_u32 srcreg = ((opcode >> 6) & 3);
29917: OpcodeFamily = 116; CurrentInstrCycles = 4;
29918: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1862; }
29919: {}}m68k_incpc(2);
29920: endlabel1862: ;
29921: return 4;
29922: }
29923: unsigned long REGPARAM2 CPUFUNC(op_f43a_0)(uae_u32 opcode) /* CPUSHA */
29924: {
29925: uae_u32 srcreg = ((opcode >> 6) & 3);
29926: OpcodeFamily = 116; CurrentInstrCycles = 4;
29927: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1863; }
29928: {}}m68k_incpc(2);
29929: endlabel1863: ;
29930: return 4;
29931: }
29932: unsigned long REGPARAM2 CPUFUNC(op_f43b_0)(uae_u32 opcode) /* CPUSHA */
29933: {
29934: uae_u32 srcreg = ((opcode >> 6) & 3);
29935: OpcodeFamily = 116; CurrentInstrCycles = 4;
29936: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1864; }
29937: {}}m68k_incpc(2);
29938: endlabel1864: ;
29939: return 4;
29940: }
29941: unsigned long REGPARAM2 CPUFUNC(op_f43c_0)(uae_u32 opcode) /* CPUSHA */
29942: {
29943: uae_u32 srcreg = ((opcode >> 6) & 3);
29944: OpcodeFamily = 116; CurrentInstrCycles = 4;
29945: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1865; }
29946: {}}m68k_incpc(2);
29947: endlabel1865: ;
29948: return 4;
29949: }
29950: unsigned long REGPARAM2 CPUFUNC(op_f43d_0)(uae_u32 opcode) /* CPUSHA */
29951: {
29952: uae_u32 srcreg = ((opcode >> 6) & 3);
29953: OpcodeFamily = 116; CurrentInstrCycles = 4;
29954: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1866; }
29955: {}}m68k_incpc(2);
29956: endlabel1866: ;
29957: return 4;
29958: }
29959: unsigned long REGPARAM2 CPUFUNC(op_f43e_0)(uae_u32 opcode) /* CPUSHA */
29960: {
29961: uae_u32 srcreg = ((opcode >> 6) & 3);
29962: OpcodeFamily = 116; CurrentInstrCycles = 4;
29963: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1867; }
29964: {}}m68k_incpc(2);
29965: endlabel1867: ;
29966: return 4;
29967: }
29968: unsigned long REGPARAM2 CPUFUNC(op_f43f_0)(uae_u32 opcode) /* CPUSHA */
29969: {
29970: uae_u32 srcreg = ((opcode >> 6) & 3);
29971: OpcodeFamily = 116; CurrentInstrCycles = 4;
29972: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1868; }
29973: {}}m68k_incpc(2);
29974: endlabel1868: ;
29975: return 4;
29976: }
29977: unsigned long REGPARAM2 CPUFUNC(op_f500_0)(uae_u32 opcode) /* MMUOP */
29978: {
29979: uae_u32 srcreg = (uae_s32)(uae_s8)((opcode >> 3) & 255);
29980: uae_u32 dstreg = opcode & 7;
29981: OpcodeFamily = 118; CurrentInstrCycles = 4;
29982: {{ uae_u32 extra = srcreg;
29983: m68k_incpc(2);
29984: mmu_op(opcode,extra);
29985: }}return 4;
29986: }
29987: unsigned long REGPARAM2 CPUFUNC(op_f600_0)(uae_u32 opcode) /* MOVE16 */
29988: {
29989: uae_u32 srcreg = (opcode & 7);
29990: OpcodeFamily = 117; CurrentInstrCycles = 12;
29991: {{ uaecptr memsa = m68k_areg(regs, srcreg);
29992: { uaecptr memda = get_ilong(2);
29993: memsa &= ~15;
29994: memda &= ~15;
29995: put_long(memda, get_long(memsa));
29996: put_long(memda+4, get_long(memsa+4));
29997: put_long(memda+8, get_long(memsa+8));
29998: put_long(memda+12, get_long(memsa+12));
29999: m68k_areg(regs, srcreg) += 16;
30000: }}}m68k_incpc(6);
30001: return 12;
30002: }
30003: unsigned long REGPARAM2 CPUFUNC(op_f608_0)(uae_u32 opcode) /* MOVE16 */
30004: {
30005: uae_u32 dstreg = opcode & 7;
30006: OpcodeFamily = 117; CurrentInstrCycles = 12;
30007: {{ uaecptr memsa = get_ilong(2);
30008: { uaecptr memda = m68k_areg(regs, dstreg);
30009: memsa &= ~15;
30010: memda &= ~15;
30011: put_long(memda, get_long(memsa));
30012: put_long(memda+4, get_long(memsa+4));
30013: put_long(memda+8, get_long(memsa+8));
30014: put_long(memda+12, get_long(memsa+12));
30015: m68k_areg(regs, dstreg) += 16;
30016: }}}m68k_incpc(6);
30017: return 12;
30018: }
30019: unsigned long REGPARAM2 CPUFUNC(op_f610_0)(uae_u32 opcode) /* MOVE16 */
30020: {
30021: uae_u32 srcreg = (opcode & 7);
30022: OpcodeFamily = 117; CurrentInstrCycles = 12;
30023: {{ uaecptr memsa = m68k_areg(regs, srcreg);
30024: { uaecptr memda = get_ilong(2);
30025: memsa &= ~15;
30026: memda &= ~15;
30027: put_long(memda, get_long(memsa));
30028: put_long(memda+4, get_long(memsa+4));
30029: put_long(memda+8, get_long(memsa+8));
30030: put_long(memda+12, get_long(memsa+12));
30031: }}}m68k_incpc(6);
30032: return 12;
30033: }
30034: unsigned long REGPARAM2 CPUFUNC(op_f618_0)(uae_u32 opcode) /* MOVE16 */
30035: {
30036: uae_u32 dstreg = opcode & 7;
30037: OpcodeFamily = 117; CurrentInstrCycles = 12;
30038: {{ uaecptr memsa = get_ilong(2);
30039: { uaecptr memda = m68k_areg(regs, dstreg);
30040: memsa &= ~15;
30041: memda &= ~15;
30042: put_long(memda, get_long(memsa));
30043: put_long(memda+4, get_long(memsa+4));
30044: put_long(memda+8, get_long(memsa+8));
30045: put_long(memda+12, get_long(memsa+12));
30046: }}}m68k_incpc(6);
30047: return 12;
30048: }
30049: unsigned long REGPARAM2 CPUFUNC(op_f620_0)(uae_u32 opcode) /* MOVE16 */
30050: {
30051: uae_u32 srcreg = (opcode & 7);
30052: uae_u32 dstreg = 0;
30053: OpcodeFamily = 117; CurrentInstrCycles = 8;
30054: { uaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;
30055: dstreg = (get_iword(2) >> 12) & 7;
30056: memd = m68k_areg(regs, dstreg) & ~15;
30057: put_long(memd, get_long(mems));
30058: put_long(memd+4, get_long(mems+4));
30059: put_long(memd+8, get_long(mems+8));
30060: put_long(memd+12, get_long(mems+12));
30061: if (srcreg != dstreg)
30062: m68k_areg(regs, srcreg) += 16;
30063: m68k_areg(regs, dstreg) += 16;
30064: }m68k_incpc(4);
30065: return 8;
30066: }
30067: #endif
30068:
30069:
30070: #if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
30071: #define PART_1 1
30072: #define PART_2 1
30073: #define PART_3 1
30074: #define PART_4 1
30075: #define PART_5 1
30076: #define PART_6 1
30077: #define PART_7 1
30078: #define PART_8 1
30079: #endif
30080:
30081: #ifdef PART_1
30082: #endif
30083:
30084: #ifdef PART_2
30085: #endif
30086:
30087: #ifdef PART_3
30088: #endif
30089:
30090: #ifdef PART_4
30091: #endif
30092:
30093: #ifdef PART_5
30094: #endif
30095:
30096: #ifdef PART_6
30097: #endif
30098:
30099: #ifdef PART_7
30100: #endif
30101:
30102: #ifdef PART_8
30103: #endif
30104:
30105:
30106: #if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
30107: #define PART_1 1
30108: #define PART_2 1
30109: #define PART_3 1
30110: #define PART_4 1
30111: #define PART_5 1
30112: #define PART_6 1
30113: #define PART_7 1
30114: #define PART_8 1
30115: #endif
30116:
30117: #ifdef PART_1
30118: #endif
30119:
30120: #ifdef PART_2
30121: #endif
30122:
30123: #ifdef PART_3
30124: #endif
30125:
30126: #ifdef PART_4
30127: #endif
30128:
30129: #ifdef PART_5
30130: #endif
30131:
30132: #ifdef PART_6
30133: #endif
30134:
30135: #ifdef PART_7
30136: #endif
30137:
30138: #ifdef PART_8
30139: #endif
30140:
30141:
30142: #if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
30143: #define PART_1 1
30144: #define PART_2 1
30145: #define PART_3 1
30146: #define PART_4 1
30147: #define PART_5 1
30148: #define PART_6 1
30149: #define PART_7 1
30150: #define PART_8 1
30151: #endif
30152:
30153: #ifdef PART_1
30154: unsigned long REGPARAM2 CPUFUNC(op_30_3)(uae_u32 opcode) /* OR */
30155: {
30156: uae_u32 dstreg = opcode & 7;
30157: OpcodeFamily = 1; CurrentInstrCycles = 22;
30158: {{ uae_s8 src = get_ibyte(2);
30159: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30160: BusCyclePenalty += 2;
30161: { uae_s8 dst = get_byte(dsta);
30162: src |= dst;
30163: CLEAR_CZNV;
30164: SET_ZFLG (((uae_s8)(src)) == 0);
30165: SET_NFLG (((uae_s8)(src)) < 0);
30166: put_byte(dsta,src);
30167: }}}}m68k_incpc(6);
30168: return 22;
30169: }
30170: unsigned long REGPARAM2 CPUFUNC(op_70_3)(uae_u32 opcode) /* OR */
30171: {
30172: uae_u32 dstreg = opcode & 7;
30173: OpcodeFamily = 1; CurrentInstrCycles = 22;
30174: {{ uae_s16 src = get_iword(2);
30175: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30176: BusCyclePenalty += 2;
30177: { uae_s16 dst = get_word(dsta);
30178: src |= dst;
30179: CLEAR_CZNV;
30180: SET_ZFLG (((uae_s16)(src)) == 0);
30181: SET_NFLG (((uae_s16)(src)) < 0);
30182: put_word(dsta,src);
30183: }}}}m68k_incpc(6);
30184: return 22;
30185: }
30186: unsigned long REGPARAM2 CPUFUNC(op_b0_3)(uae_u32 opcode) /* OR */
30187: {
30188: uae_u32 dstreg = opcode & 7;
30189: OpcodeFamily = 1; CurrentInstrCycles = 34;
30190: {{ uae_s32 src = get_ilong(2);
30191: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
30192: BusCyclePenalty += 2;
30193: { uae_s32 dst = get_long(dsta);
30194: src |= dst;
30195: CLEAR_CZNV;
30196: SET_ZFLG (((uae_s32)(src)) == 0);
30197: SET_NFLG (((uae_s32)(src)) < 0);
30198: put_long(dsta,src);
30199: }}}}m68k_incpc(8);
30200: return 34;
30201: }
30202: unsigned long REGPARAM2 CPUFUNC(op_130_3)(uae_u32 opcode) /* BTST */
30203: {
30204: uae_u32 srcreg = ((opcode >> 9) & 7);
30205: uae_u32 dstreg = opcode & 7;
30206: OpcodeFamily = 21; CurrentInstrCycles = 14;
30207: {{ uae_s8 src = m68k_dreg(regs, srcreg);
30208: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
30209: BusCyclePenalty += 2;
30210: { uae_s8 dst = get_byte(dsta);
30211: src &= 7;
30212: SET_ZFLG (1 ^ ((dst >> src) & 1));
30213: }}}}m68k_incpc(4);
30214: return 14;
30215: }
30216: unsigned long REGPARAM2 CPUFUNC(op_13b_3)(uae_u32 opcode) /* BTST */
30217: {
30218: uae_u32 srcreg = ((opcode >> 9) & 7);
30219: uae_u32 dstreg = 3;
30220: OpcodeFamily = 21; CurrentInstrCycles = 14;
30221: {{ uae_s8 src = m68k_dreg(regs, srcreg);
30222: { uaecptr tmppc = m68k_getpc() + 2;
30223: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(2));
30224: BusCyclePenalty += 2;
30225: { uae_s8 dst = get_byte(dsta);
30226: src &= 7;
30227: SET_ZFLG (1 ^ ((dst >> src) & 1));
30228: }}}}m68k_incpc(4);
30229: return 14;
30230: }
30231: unsigned long REGPARAM2 CPUFUNC(op_170_3)(uae_u32 opcode) /* BCHG */
30232: {
30233: uae_u32 srcreg = ((opcode >> 9) & 7);
30234: uae_u32 dstreg = opcode & 7;
30235: OpcodeFamily = 22; CurrentInstrCycles = 18;
30236: {{ uae_s8 src = m68k_dreg(regs, srcreg);
30237: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
30238: BusCyclePenalty += 2;
30239: { uae_s8 dst = get_byte(dsta);
30240: src &= 7;
30241: dst ^= (1 << src);
30242: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
30243: put_byte(dsta,dst);
30244: }}}}m68k_incpc(4);
30245: return 18;
30246: }
30247: unsigned long REGPARAM2 CPUFUNC(op_17b_3)(uae_u32 opcode) /* BCHG */
30248: {
30249: uae_u32 srcreg = ((opcode >> 9) & 7);
30250: uae_u32 dstreg = 3;
30251: OpcodeFamily = 22; CurrentInstrCycles = 18;
30252: {{ uae_s8 src = m68k_dreg(regs, srcreg);
30253: { uaecptr tmppc = m68k_getpc() + 2;
30254: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(2));
30255: BusCyclePenalty += 2;
30256: { uae_s8 dst = get_byte(dsta);
30257: src &= 7;
30258: dst ^= (1 << src);
30259: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
30260: put_byte(dsta,dst);
30261: }}}}m68k_incpc(4);
30262: return 18;
30263: }
30264: unsigned long REGPARAM2 CPUFUNC(op_1b0_3)(uae_u32 opcode) /* BCLR */
30265: {
30266: uae_u32 srcreg = ((opcode >> 9) & 7);
30267: uae_u32 dstreg = opcode & 7;
30268: OpcodeFamily = 23; CurrentInstrCycles = 18;
30269: {{ uae_s8 src = m68k_dreg(regs, srcreg);
30270: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
30271: BusCyclePenalty += 2;
30272: { uae_s8 dst = get_byte(dsta);
30273: src &= 7;
30274: SET_ZFLG (1 ^ ((dst >> src) & 1));
30275: dst &= ~(1 << src);
30276: put_byte(dsta,dst);
30277: }}}}m68k_incpc(4);
30278: return 18;
30279: }
30280: unsigned long REGPARAM2 CPUFUNC(op_1bb_3)(uae_u32 opcode) /* BCLR */
30281: {
30282: uae_u32 srcreg = ((opcode >> 9) & 7);
30283: uae_u32 dstreg = 3;
30284: OpcodeFamily = 23; CurrentInstrCycles = 18;
30285: {{ uae_s8 src = m68k_dreg(regs, srcreg);
30286: { uaecptr tmppc = m68k_getpc() + 2;
30287: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(2));
30288: BusCyclePenalty += 2;
30289: { uae_s8 dst = get_byte(dsta);
30290: src &= 7;
30291: SET_ZFLG (1 ^ ((dst >> src) & 1));
30292: dst &= ~(1 << src);
30293: put_byte(dsta,dst);
30294: }}}}m68k_incpc(4);
30295: return 18;
30296: }
30297: unsigned long REGPARAM2 CPUFUNC(op_1f0_3)(uae_u32 opcode) /* BSET */
30298: {
30299: uae_u32 srcreg = ((opcode >> 9) & 7);
30300: uae_u32 dstreg = opcode & 7;
30301: OpcodeFamily = 24; CurrentInstrCycles = 18;
30302: {{ uae_s8 src = m68k_dreg(regs, srcreg);
30303: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
30304: BusCyclePenalty += 2;
30305: { uae_s8 dst = get_byte(dsta);
30306: src &= 7;
30307: SET_ZFLG (1 ^ ((dst >> src) & 1));
30308: dst |= (1 << src);
30309: put_byte(dsta,dst);
30310: }}}}m68k_incpc(4);
30311: return 18;
30312: }
30313: unsigned long REGPARAM2 CPUFUNC(op_1fb_3)(uae_u32 opcode) /* BSET */
30314: {
30315: uae_u32 srcreg = ((opcode >> 9) & 7);
30316: uae_u32 dstreg = 3;
30317: OpcodeFamily = 24; CurrentInstrCycles = 18;
30318: {{ uae_s8 src = m68k_dreg(regs, srcreg);
30319: { uaecptr tmppc = m68k_getpc() + 2;
30320: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(2));
30321: BusCyclePenalty += 2;
30322: { uae_s8 dst = get_byte(dsta);
30323: src &= 7;
30324: SET_ZFLG (1 ^ ((dst >> src) & 1));
30325: dst |= (1 << src);
30326: put_byte(dsta,dst);
30327: }}}}m68k_incpc(4);
30328: return 18;
30329: }
30330: unsigned long REGPARAM2 CPUFUNC(op_230_3)(uae_u32 opcode) /* AND */
30331: {
30332: uae_u32 dstreg = opcode & 7;
30333: OpcodeFamily = 2; CurrentInstrCycles = 22;
30334: {{ uae_s8 src = get_ibyte(2);
30335: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30336: BusCyclePenalty += 2;
30337: { uae_s8 dst = get_byte(dsta);
30338: src &= dst;
30339: CLEAR_CZNV;
30340: SET_ZFLG (((uae_s8)(src)) == 0);
30341: SET_NFLG (((uae_s8)(src)) < 0);
30342: put_byte(dsta,src);
30343: }}}}m68k_incpc(6);
30344: return 22;
30345: }
30346: unsigned long REGPARAM2 CPUFUNC(op_270_3)(uae_u32 opcode) /* AND */
30347: {
30348: uae_u32 dstreg = opcode & 7;
30349: OpcodeFamily = 2; CurrentInstrCycles = 22;
30350: {{ uae_s16 src = get_iword(2);
30351: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30352: BusCyclePenalty += 2;
30353: { uae_s16 dst = get_word(dsta);
30354: src &= dst;
30355: CLEAR_CZNV;
30356: SET_ZFLG (((uae_s16)(src)) == 0);
30357: SET_NFLG (((uae_s16)(src)) < 0);
30358: put_word(dsta,src);
30359: }}}}m68k_incpc(6);
30360: return 22;
30361: }
30362: unsigned long REGPARAM2 CPUFUNC(op_2b0_3)(uae_u32 opcode) /* AND */
30363: {
30364: uae_u32 dstreg = opcode & 7;
30365: OpcodeFamily = 2; CurrentInstrCycles = 34;
30366: {{ uae_s32 src = get_ilong(2);
30367: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
30368: BusCyclePenalty += 2;
30369: { uae_s32 dst = get_long(dsta);
30370: src &= dst;
30371: CLEAR_CZNV;
30372: SET_ZFLG (((uae_s32)(src)) == 0);
30373: SET_NFLG (((uae_s32)(src)) < 0);
30374: put_long(dsta,src);
30375: }}}}m68k_incpc(8);
30376: return 34;
30377: }
30378: unsigned long REGPARAM2 CPUFUNC(op_430_3)(uae_u32 opcode) /* SUB */
30379: {
30380: uae_u32 dstreg = opcode & 7;
30381: OpcodeFamily = 7; CurrentInstrCycles = 22;
30382: {{ uae_s8 src = get_ibyte(2);
30383: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30384: BusCyclePenalty += 2;
30385: { uae_s8 dst = get_byte(dsta);
30386: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
30387: { int flgs = ((uae_s8)(src)) < 0;
30388: int flgo = ((uae_s8)(dst)) < 0;
30389: int flgn = ((uae_s8)(newv)) < 0;
30390: SET_ZFLG (((uae_s8)(newv)) == 0);
30391: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
30392: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
30393: COPY_CARRY;
30394: SET_NFLG (flgn != 0);
30395: put_byte(dsta,newv);
30396: }}}}}}}m68k_incpc(6);
30397: return 22;
30398: }
30399: unsigned long REGPARAM2 CPUFUNC(op_470_3)(uae_u32 opcode) /* SUB */
30400: {
30401: uae_u32 dstreg = opcode & 7;
30402: OpcodeFamily = 7; CurrentInstrCycles = 22;
30403: {{ uae_s16 src = get_iword(2);
30404: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30405: BusCyclePenalty += 2;
30406: { uae_s16 dst = get_word(dsta);
30407: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
30408: { int flgs = ((uae_s16)(src)) < 0;
30409: int flgo = ((uae_s16)(dst)) < 0;
30410: int flgn = ((uae_s16)(newv)) < 0;
30411: SET_ZFLG (((uae_s16)(newv)) == 0);
30412: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
30413: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
30414: COPY_CARRY;
30415: SET_NFLG (flgn != 0);
30416: put_word(dsta,newv);
30417: }}}}}}}m68k_incpc(6);
30418: return 22;
30419: }
30420: unsigned long REGPARAM2 CPUFUNC(op_4b0_3)(uae_u32 opcode) /* SUB */
30421: {
30422: uae_u32 dstreg = opcode & 7;
30423: OpcodeFamily = 7; CurrentInstrCycles = 34;
30424: {{ uae_s32 src = get_ilong(2);
30425: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
30426: BusCyclePenalty += 2;
30427: { uae_s32 dst = get_long(dsta);
30428: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
30429: { int flgs = ((uae_s32)(src)) < 0;
30430: int flgo = ((uae_s32)(dst)) < 0;
30431: int flgn = ((uae_s32)(newv)) < 0;
30432: SET_ZFLG (((uae_s32)(newv)) == 0);
30433: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
30434: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
30435: COPY_CARRY;
30436: SET_NFLG (flgn != 0);
30437: put_long(dsta,newv);
30438: }}}}}}}m68k_incpc(8);
30439: return 34;
30440: }
30441: unsigned long REGPARAM2 CPUFUNC(op_630_3)(uae_u32 opcode) /* ADD */
30442: {
30443: uae_u32 dstreg = opcode & 7;
30444: OpcodeFamily = 11; CurrentInstrCycles = 22;
30445: {{ uae_s8 src = get_ibyte(2);
30446: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30447: BusCyclePenalty += 2;
30448: { uae_s8 dst = get_byte(dsta);
30449: { refill_prefetch (m68k_getpc(), 2);
30450: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
30451: { int flgs = ((uae_s8)(src)) < 0;
30452: int flgo = ((uae_s8)(dst)) < 0;
30453: int flgn = ((uae_s8)(newv)) < 0;
30454: SET_ZFLG (((uae_s8)(newv)) == 0);
30455: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
30456: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
30457: COPY_CARRY;
30458: SET_NFLG (flgn != 0);
30459: put_byte(dsta,newv);
30460: }}}}}}}m68k_incpc(6);
30461: return 22;
30462: }
30463: unsigned long REGPARAM2 CPUFUNC(op_670_3)(uae_u32 opcode) /* ADD */
30464: {
30465: uae_u32 dstreg = opcode & 7;
30466: OpcodeFamily = 11; CurrentInstrCycles = 22;
30467: {{ uae_s16 src = get_iword(2);
30468: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30469: BusCyclePenalty += 2;
30470: { uae_s16 dst = get_word(dsta);
30471: { refill_prefetch (m68k_getpc(), 2);
30472: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
30473: { int flgs = ((uae_s16)(src)) < 0;
30474: int flgo = ((uae_s16)(dst)) < 0;
30475: int flgn = ((uae_s16)(newv)) < 0;
30476: SET_ZFLG (((uae_s16)(newv)) == 0);
30477: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
30478: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
30479: COPY_CARRY;
30480: SET_NFLG (flgn != 0);
30481: put_word(dsta,newv);
30482: }}}}}}}m68k_incpc(6);
30483: return 22;
30484: }
30485: unsigned long REGPARAM2 CPUFUNC(op_6b0_3)(uae_u32 opcode) /* ADD */
30486: {
30487: uae_u32 dstreg = opcode & 7;
30488: OpcodeFamily = 11; CurrentInstrCycles = 34;
30489: {{ uae_s32 src = get_ilong(2);
30490: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
30491: BusCyclePenalty += 2;
30492: { uae_s32 dst = get_long(dsta);
30493: { refill_prefetch (m68k_getpc(), 2);
30494: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
30495: { int flgs = ((uae_s32)(src)) < 0;
30496: int flgo = ((uae_s32)(dst)) < 0;
30497: int flgn = ((uae_s32)(newv)) < 0;
30498: SET_ZFLG (((uae_s32)(newv)) == 0);
30499: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
30500: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
30501: COPY_CARRY;
30502: SET_NFLG (flgn != 0);
30503: put_long(dsta,newv);
30504: }}}}}}}m68k_incpc(8);
30505: return 34;
30506: }
30507: unsigned long REGPARAM2 CPUFUNC(op_830_3)(uae_u32 opcode) /* BTST */
30508: {
30509: uae_u32 dstreg = opcode & 7;
30510: OpcodeFamily = 21; CurrentInstrCycles = 18;
30511: {{ uae_s16 src = get_iword(2);
30512: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30513: BusCyclePenalty += 2;
30514: { uae_s8 dst = get_byte(dsta);
30515: src &= 7;
30516: SET_ZFLG (1 ^ ((dst >> src) & 1));
30517: }}}}m68k_incpc(6);
30518: return 18;
30519: }
30520: unsigned long REGPARAM2 CPUFUNC(op_83b_3)(uae_u32 opcode) /* BTST */
30521: {
30522: uae_u32 dstreg = 3;
30523: OpcodeFamily = 21; CurrentInstrCycles = 18;
30524: {{ uae_s16 src = get_iword(2);
30525: { uaecptr tmppc = m68k_getpc() + 4;
30526: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(4));
30527: BusCyclePenalty += 2;
30528: { uae_s8 dst = get_byte(dsta);
30529: src &= 7;
30530: SET_ZFLG (1 ^ ((dst >> src) & 1));
30531: }}}}m68k_incpc(6);
30532: return 18;
30533: }
30534: unsigned long REGPARAM2 CPUFUNC(op_870_3)(uae_u32 opcode) /* BCHG */
30535: {
30536: uae_u32 dstreg = opcode & 7;
30537: OpcodeFamily = 22; CurrentInstrCycles = 22;
30538: {{ uae_s16 src = get_iword(2);
30539: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30540: BusCyclePenalty += 2;
30541: { uae_s8 dst = get_byte(dsta);
30542: src &= 7;
30543: dst ^= (1 << src);
30544: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
30545: put_byte(dsta,dst);
30546: }}}}m68k_incpc(6);
30547: return 22;
30548: }
30549: unsigned long REGPARAM2 CPUFUNC(op_87b_3)(uae_u32 opcode) /* BCHG */
30550: {
30551: uae_u32 dstreg = 3;
30552: OpcodeFamily = 22; CurrentInstrCycles = 22;
30553: {{ uae_s16 src = get_iword(2);
30554: { uaecptr tmppc = m68k_getpc() + 4;
30555: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(4));
30556: BusCyclePenalty += 2;
30557: { uae_s8 dst = get_byte(dsta);
30558: src &= 7;
30559: dst ^= (1 << src);
30560: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
30561: put_byte(dsta,dst);
30562: }}}}m68k_incpc(6);
30563: return 22;
30564: }
30565: unsigned long REGPARAM2 CPUFUNC(op_8b0_3)(uae_u32 opcode) /* BCLR */
30566: {
30567: uae_u32 dstreg = opcode & 7;
30568: OpcodeFamily = 23; CurrentInstrCycles = 22;
30569: {{ uae_s16 src = get_iword(2);
30570: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30571: BusCyclePenalty += 2;
30572: { uae_s8 dst = get_byte(dsta);
30573: src &= 7;
30574: SET_ZFLG (1 ^ ((dst >> src) & 1));
30575: dst &= ~(1 << src);
30576: put_byte(dsta,dst);
30577: }}}}m68k_incpc(6);
30578: return 22;
30579: }
30580: unsigned long REGPARAM2 CPUFUNC(op_8bb_3)(uae_u32 opcode) /* BCLR */
30581: {
30582: uae_u32 dstreg = 3;
30583: OpcodeFamily = 23; CurrentInstrCycles = 22;
30584: {{ uae_s16 src = get_iword(2);
30585: { uaecptr tmppc = m68k_getpc() + 4;
30586: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(4));
30587: BusCyclePenalty += 2;
30588: { uae_s8 dst = get_byte(dsta);
30589: src &= 7;
30590: SET_ZFLG (1 ^ ((dst >> src) & 1));
30591: dst &= ~(1 << src);
30592: put_byte(dsta,dst);
30593: }}}}m68k_incpc(6);
30594: return 22;
30595: }
30596: unsigned long REGPARAM2 CPUFUNC(op_8f0_3)(uae_u32 opcode) /* BSET */
30597: {
30598: uae_u32 dstreg = opcode & 7;
30599: OpcodeFamily = 24; CurrentInstrCycles = 22;
30600: {{ uae_s16 src = get_iword(2);
30601: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30602: BusCyclePenalty += 2;
30603: { uae_s8 dst = get_byte(dsta);
30604: src &= 7;
30605: SET_ZFLG (1 ^ ((dst >> src) & 1));
30606: dst |= (1 << src);
30607: put_byte(dsta,dst);
30608: }}}}m68k_incpc(6);
30609: return 22;
30610: }
30611: unsigned long REGPARAM2 CPUFUNC(op_8fb_3)(uae_u32 opcode) /* BSET */
30612: {
30613: uae_u32 dstreg = 3;
30614: OpcodeFamily = 24; CurrentInstrCycles = 22;
30615: {{ uae_s16 src = get_iword(2);
30616: { uaecptr tmppc = m68k_getpc() + 4;
30617: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(4));
30618: BusCyclePenalty += 2;
30619: { uae_s8 dst = get_byte(dsta);
30620: src &= 7;
30621: SET_ZFLG (1 ^ ((dst >> src) & 1));
30622: dst |= (1 << src);
30623: put_byte(dsta,dst);
30624: }}}}m68k_incpc(6);
30625: return 22;
30626: }
30627: unsigned long REGPARAM2 CPUFUNC(op_a30_3)(uae_u32 opcode) /* EOR */
30628: {
30629: uae_u32 dstreg = opcode & 7;
30630: OpcodeFamily = 3; CurrentInstrCycles = 22;
30631: {{ uae_s8 src = get_ibyte(2);
30632: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30633: BusCyclePenalty += 2;
30634: { uae_s8 dst = get_byte(dsta);
30635: src ^= dst;
30636: CLEAR_CZNV;
30637: SET_ZFLG (((uae_s8)(src)) == 0);
30638: SET_NFLG (((uae_s8)(src)) < 0);
30639: put_byte(dsta,src);
30640: }}}}m68k_incpc(6);
30641: return 22;
30642: }
30643: unsigned long REGPARAM2 CPUFUNC(op_a70_3)(uae_u32 opcode) /* EOR */
30644: {
30645: uae_u32 dstreg = opcode & 7;
30646: OpcodeFamily = 3; CurrentInstrCycles = 22;
30647: {{ uae_s16 src = get_iword(2);
30648: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30649: BusCyclePenalty += 2;
30650: { uae_s16 dst = get_word(dsta);
30651: src ^= dst;
30652: CLEAR_CZNV;
30653: SET_ZFLG (((uae_s16)(src)) == 0);
30654: SET_NFLG (((uae_s16)(src)) < 0);
30655: put_word(dsta,src);
30656: }}}}m68k_incpc(6);
30657: return 22;
30658: }
30659: #endif
30660:
30661: #ifdef PART_2
30662: unsigned long REGPARAM2 CPUFUNC(op_ab0_3)(uae_u32 opcode) /* EOR */
30663: {
30664: uae_u32 dstreg = opcode & 7;
30665: OpcodeFamily = 3; CurrentInstrCycles = 34;
30666: {{ uae_s32 src = get_ilong(2);
30667: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
30668: BusCyclePenalty += 2;
30669: { uae_s32 dst = get_long(dsta);
30670: src ^= dst;
30671: CLEAR_CZNV;
30672: SET_ZFLG (((uae_s32)(src)) == 0);
30673: SET_NFLG (((uae_s32)(src)) < 0);
30674: put_long(dsta,src);
30675: }}}}m68k_incpc(8);
30676: return 34;
30677: }
30678: unsigned long REGPARAM2 CPUFUNC(op_c30_3)(uae_u32 opcode) /* CMP */
30679: {
30680: uae_u32 dstreg = opcode & 7;
30681: OpcodeFamily = 25; CurrentInstrCycles = 18;
30682: {{ uae_s8 src = get_ibyte(2);
30683: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30684: BusCyclePenalty += 2;
30685: { uae_s8 dst = get_byte(dsta);
30686: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
30687: { int flgs = ((uae_s8)(src)) < 0;
30688: int flgo = ((uae_s8)(dst)) < 0;
30689: int flgn = ((uae_s8)(newv)) < 0;
30690: SET_ZFLG (((uae_s8)(newv)) == 0);
30691: SET_VFLG ((flgs != flgo) && (flgn != flgo));
30692: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
30693: SET_NFLG (flgn != 0);
30694: }}}}}}}m68k_incpc(6);
30695: return 18;
30696: }
30697: unsigned long REGPARAM2 CPUFUNC(op_c3b_3)(uae_u32 opcode) /* CMP */
30698: {
30699: uae_u32 dstreg = 3;
30700: OpcodeFamily = 25; CurrentInstrCycles = 18;
30701: {{ uae_s8 src = get_ibyte(2);
30702: { uaecptr tmppc = m68k_getpc() + 4;
30703: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(4));
30704: BusCyclePenalty += 2;
30705: { uae_s8 dst = get_byte(dsta);
30706: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
30707: { int flgs = ((uae_s8)(src)) < 0;
30708: int flgo = ((uae_s8)(dst)) < 0;
30709: int flgn = ((uae_s8)(newv)) < 0;
30710: SET_ZFLG (((uae_s8)(newv)) == 0);
30711: SET_VFLG ((flgs != flgo) && (flgn != flgo));
30712: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
30713: SET_NFLG (flgn != 0);
30714: }}}}}}}m68k_incpc(6);
30715: return 18;
30716: }
30717: unsigned long REGPARAM2 CPUFUNC(op_c70_3)(uae_u32 opcode) /* CMP */
30718: {
30719: uae_u32 dstreg = opcode & 7;
30720: OpcodeFamily = 25; CurrentInstrCycles = 18;
30721: {{ uae_s16 src = get_iword(2);
30722: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
30723: BusCyclePenalty += 2;
30724: { uae_s16 dst = get_word(dsta);
30725: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
30726: { int flgs = ((uae_s16)(src)) < 0;
30727: int flgo = ((uae_s16)(dst)) < 0;
30728: int flgn = ((uae_s16)(newv)) < 0;
30729: SET_ZFLG (((uae_s16)(newv)) == 0);
30730: SET_VFLG ((flgs != flgo) && (flgn != flgo));
30731: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
30732: SET_NFLG (flgn != 0);
30733: }}}}}}}m68k_incpc(6);
30734: return 18;
30735: }
30736: unsigned long REGPARAM2 CPUFUNC(op_c7b_3)(uae_u32 opcode) /* CMP */
30737: {
30738: uae_u32 dstreg = 3;
30739: OpcodeFamily = 25; CurrentInstrCycles = 18;
30740: {{ uae_s16 src = get_iword(2);
30741: { uaecptr tmppc = m68k_getpc() + 4;
30742: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(4));
30743: BusCyclePenalty += 2;
30744: { uae_s16 dst = get_word(dsta);
30745: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
30746: { int flgs = ((uae_s16)(src)) < 0;
30747: int flgo = ((uae_s16)(dst)) < 0;
30748: int flgn = ((uae_s16)(newv)) < 0;
30749: SET_ZFLG (((uae_s16)(newv)) == 0);
30750: SET_VFLG ((flgs != flgo) && (flgn != flgo));
30751: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
30752: SET_NFLG (flgn != 0);
30753: }}}}}}}m68k_incpc(6);
30754: return 18;
30755: }
30756: unsigned long REGPARAM2 CPUFUNC(op_cb0_3)(uae_u32 opcode) /* CMP */
30757: {
30758: uae_u32 dstreg = opcode & 7;
30759: OpcodeFamily = 25; CurrentInstrCycles = 26;
30760: {{ uae_s32 src = get_ilong(2);
30761: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
30762: BusCyclePenalty += 2;
30763: { uae_s32 dst = get_long(dsta);
30764: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
30765: { int flgs = ((uae_s32)(src)) < 0;
30766: int flgo = ((uae_s32)(dst)) < 0;
30767: int flgn = ((uae_s32)(newv)) < 0;
30768: SET_ZFLG (((uae_s32)(newv)) == 0);
30769: SET_VFLG ((flgs != flgo) && (flgn != flgo));
30770: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
30771: SET_NFLG (flgn != 0);
30772: }}}}}}}m68k_incpc(8);
30773: return 26;
30774: }
30775: unsigned long REGPARAM2 CPUFUNC(op_cbb_3)(uae_u32 opcode) /* CMP */
30776: {
30777: uae_u32 dstreg = 3;
30778: OpcodeFamily = 25; CurrentInstrCycles = 26;
30779: {{ uae_s32 src = get_ilong(2);
30780: { uaecptr tmppc = m68k_getpc() + 6;
30781: uaecptr dsta = get_disp_ea_000(tmppc, get_iword(6));
30782: BusCyclePenalty += 2;
30783: { uae_s32 dst = get_long(dsta);
30784: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
30785: { int flgs = ((uae_s32)(src)) < 0;
30786: int flgo = ((uae_s32)(dst)) < 0;
30787: int flgn = ((uae_s32)(newv)) < 0;
30788: SET_ZFLG (((uae_s32)(newv)) == 0);
30789: SET_VFLG ((flgs != flgo) && (flgn != flgo));
30790: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
30791: SET_NFLG (flgn != 0);
30792: }}}}}}}m68k_incpc(8);
30793: return 26;
30794: }
30795: unsigned long REGPARAM2 CPUFUNC(op_1030_3)(uae_u32 opcode) /* MOVE */
30796: {
30797: uae_u32 srcreg = (opcode & 7);
30798: uae_u32 dstreg = (opcode >> 9) & 7;
30799: OpcodeFamily = 30; CurrentInstrCycles = 14;
30800: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
30801: BusCyclePenalty += 2;
30802: { uae_s8 src = get_byte(srca);
30803: { CLEAR_CZNV;
30804: SET_ZFLG (((uae_s8)(src)) == 0);
30805: SET_NFLG (((uae_s8)(src)) < 0);
30806: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
30807: }}}}m68k_incpc(4);
30808: return 14;
30809: }
30810: unsigned long REGPARAM2 CPUFUNC(op_103b_3)(uae_u32 opcode) /* MOVE */
30811: {
30812: uae_u32 dstreg = (opcode >> 9) & 7;
30813: OpcodeFamily = 30; CurrentInstrCycles = 14;
30814: {{ uaecptr tmppc = m68k_getpc() + 2;
30815: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
30816: BusCyclePenalty += 2;
30817: { uae_s8 src = get_byte(srca);
30818: { CLEAR_CZNV;
30819: SET_ZFLG (((uae_s8)(src)) == 0);
30820: SET_NFLG (((uae_s8)(src)) < 0);
30821: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
30822: }}}}m68k_incpc(4);
30823: return 14;
30824: }
30825: unsigned long REGPARAM2 CPUFUNC(op_10b0_3)(uae_u32 opcode) /* MOVE */
30826: {
30827: uae_u32 srcreg = (opcode & 7);
30828: uae_u32 dstreg = (opcode >> 9) & 7;
30829: OpcodeFamily = 30; CurrentInstrCycles = 18;
30830: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
30831: BusCyclePenalty += 2;
30832: { uae_s8 src = get_byte(srca);
30833: { uaecptr dsta = m68k_areg(regs, dstreg);
30834: CLEAR_CZNV;
30835: SET_ZFLG (((uae_s8)(src)) == 0);
30836: SET_NFLG (((uae_s8)(src)) < 0);
30837: put_byte(dsta,src);
30838: }}}}m68k_incpc(4);
30839: return 18;
30840: }
30841: unsigned long REGPARAM2 CPUFUNC(op_10bb_3)(uae_u32 opcode) /* MOVE */
30842: {
30843: uae_u32 dstreg = (opcode >> 9) & 7;
30844: OpcodeFamily = 30; CurrentInstrCycles = 18;
30845: {{ uaecptr tmppc = m68k_getpc() + 2;
30846: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
30847: BusCyclePenalty += 2;
30848: { uae_s8 src = get_byte(srca);
30849: { uaecptr dsta = m68k_areg(regs, dstreg);
30850: CLEAR_CZNV;
30851: SET_ZFLG (((uae_s8)(src)) == 0);
30852: SET_NFLG (((uae_s8)(src)) < 0);
30853: put_byte(dsta,src);
30854: }}}}m68k_incpc(4);
30855: return 18;
30856: }
30857: unsigned long REGPARAM2 CPUFUNC(op_10f0_3)(uae_u32 opcode) /* MOVE */
30858: {
30859: uae_u32 srcreg = (opcode & 7);
30860: uae_u32 dstreg = (opcode >> 9) & 7;
30861: OpcodeFamily = 30; CurrentInstrCycles = 18;
30862: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
30863: BusCyclePenalty += 2;
30864: { uae_s8 src = get_byte(srca);
30865: { uaecptr dsta = m68k_areg(regs, dstreg);
30866: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
30867: CLEAR_CZNV;
30868: SET_ZFLG (((uae_s8)(src)) == 0);
30869: SET_NFLG (((uae_s8)(src)) < 0);
30870: put_byte(dsta,src);
30871: }}}}m68k_incpc(4);
30872: return 18;
30873: }
30874: unsigned long REGPARAM2 CPUFUNC(op_10fb_3)(uae_u32 opcode) /* MOVE */
30875: {
30876: uae_u32 dstreg = (opcode >> 9) & 7;
30877: OpcodeFamily = 30; CurrentInstrCycles = 18;
30878: {{ uaecptr tmppc = m68k_getpc() + 2;
30879: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
30880: BusCyclePenalty += 2;
30881: { uae_s8 src = get_byte(srca);
30882: { uaecptr dsta = m68k_areg(regs, dstreg);
30883: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
30884: CLEAR_CZNV;
30885: SET_ZFLG (((uae_s8)(src)) == 0);
30886: SET_NFLG (((uae_s8)(src)) < 0);
30887: put_byte(dsta,src);
30888: }}}}m68k_incpc(4);
30889: return 18;
30890: }
30891: unsigned long REGPARAM2 CPUFUNC(op_1130_3)(uae_u32 opcode) /* MOVE */
30892: {
30893: uae_u32 srcreg = (opcode & 7);
30894: uae_u32 dstreg = (opcode >> 9) & 7;
30895: OpcodeFamily = 30; CurrentInstrCycles = 18;
30896: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
30897: BusCyclePenalty += 2;
30898: { uae_s8 src = get_byte(srca);
30899: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
30900: m68k_areg (regs, dstreg) = dsta;
30901: CLEAR_CZNV;
30902: SET_ZFLG (((uae_s8)(src)) == 0);
30903: SET_NFLG (((uae_s8)(src)) < 0);
30904: put_byte(dsta,src);
30905: }}}}m68k_incpc(4);
30906: return 18;
30907: }
30908: unsigned long REGPARAM2 CPUFUNC(op_113b_3)(uae_u32 opcode) /* MOVE */
30909: {
30910: uae_u32 dstreg = (opcode >> 9) & 7;
30911: OpcodeFamily = 30; CurrentInstrCycles = 18;
30912: {{ uaecptr tmppc = m68k_getpc() + 2;
30913: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
30914: BusCyclePenalty += 2;
30915: { uae_s8 src = get_byte(srca);
30916: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
30917: m68k_areg (regs, dstreg) = dsta;
30918: CLEAR_CZNV;
30919: SET_ZFLG (((uae_s8)(src)) == 0);
30920: SET_NFLG (((uae_s8)(src)) < 0);
30921: put_byte(dsta,src);
30922: }}}}m68k_incpc(4);
30923: return 18;
30924: }
30925: unsigned long REGPARAM2 CPUFUNC(op_1170_3)(uae_u32 opcode) /* MOVE */
30926: {
30927: uae_u32 srcreg = (opcode & 7);
30928: uae_u32 dstreg = (opcode >> 9) & 7;
30929: OpcodeFamily = 30; CurrentInstrCycles = 22;
30930: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
30931: BusCyclePenalty += 2;
30932: { uae_s8 src = get_byte(srca);
30933: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
30934: CLEAR_CZNV;
30935: SET_ZFLG (((uae_s8)(src)) == 0);
30936: SET_NFLG (((uae_s8)(src)) < 0);
30937: put_byte(dsta,src);
30938: }}}}m68k_incpc(6);
30939: return 22;
30940: }
30941: unsigned long REGPARAM2 CPUFUNC(op_117b_3)(uae_u32 opcode) /* MOVE */
30942: {
30943: uae_u32 dstreg = (opcode >> 9) & 7;
30944: OpcodeFamily = 30; CurrentInstrCycles = 22;
30945: {{ uaecptr tmppc = m68k_getpc() + 2;
30946: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
30947: BusCyclePenalty += 2;
30948: { uae_s8 src = get_byte(srca);
30949: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
30950: CLEAR_CZNV;
30951: SET_ZFLG (((uae_s8)(src)) == 0);
30952: SET_NFLG (((uae_s8)(src)) < 0);
30953: put_byte(dsta,src);
30954: }}}}m68k_incpc(6);
30955: return 22;
30956: }
30957: unsigned long REGPARAM2 CPUFUNC(op_1180_3)(uae_u32 opcode) /* MOVE */
30958: {
30959: uae_u32 srcreg = (opcode & 7);
30960: uae_u32 dstreg = (opcode >> 9) & 7;
30961: OpcodeFamily = 30; CurrentInstrCycles = 14;
30962: {{ uae_s8 src = m68k_dreg(regs, srcreg);
30963: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
30964: BusCyclePenalty += 2;
30965: CLEAR_CZNV;
30966: SET_ZFLG (((uae_s8)(src)) == 0);
30967: SET_NFLG (((uae_s8)(src)) < 0);
30968: put_byte(dsta,src);
30969: }}}m68k_incpc(4);
30970: return 14;
30971: }
30972: unsigned long REGPARAM2 CPUFUNC(op_1188_3)(uae_u32 opcode) /* MOVE */
30973: {
30974: uae_u32 srcreg = (opcode & 7);
30975: uae_u32 dstreg = (opcode >> 9) & 7;
30976: OpcodeFamily = 30; CurrentInstrCycles = 14;
30977: {{ uae_s8 src = m68k_areg(regs, srcreg);
30978: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
30979: BusCyclePenalty += 2;
30980: CLEAR_CZNV;
30981: SET_ZFLG (((uae_s8)(src)) == 0);
30982: SET_NFLG (((uae_s8)(src)) < 0);
30983: put_byte(dsta,src);
30984: }}}m68k_incpc(4);
30985: return 14;
30986: }
30987: unsigned long REGPARAM2 CPUFUNC(op_1190_3)(uae_u32 opcode) /* MOVE */
30988: {
30989: uae_u32 srcreg = (opcode & 7);
30990: uae_u32 dstreg = (opcode >> 9) & 7;
30991: OpcodeFamily = 30; CurrentInstrCycles = 18;
30992: {{ uaecptr srca = m68k_areg(regs, srcreg);
30993: { uae_s8 src = get_byte(srca);
30994: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
30995: BusCyclePenalty += 2;
30996: CLEAR_CZNV;
30997: SET_ZFLG (((uae_s8)(src)) == 0);
30998: SET_NFLG (((uae_s8)(src)) < 0);
30999: put_byte(dsta,src);
31000: }}}}m68k_incpc(4);
31001: return 18;
31002: }
31003: unsigned long REGPARAM2 CPUFUNC(op_1198_3)(uae_u32 opcode) /* MOVE */
31004: {
31005: uae_u32 srcreg = (opcode & 7);
31006: uae_u32 dstreg = (opcode >> 9) & 7;
31007: OpcodeFamily = 30; CurrentInstrCycles = 18;
31008: {{ uaecptr srca = m68k_areg(regs, srcreg);
31009: { uae_s8 src = get_byte(srca);
31010: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
31011: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31012: BusCyclePenalty += 2;
31013: CLEAR_CZNV;
31014: SET_ZFLG (((uae_s8)(src)) == 0);
31015: SET_NFLG (((uae_s8)(src)) < 0);
31016: put_byte(dsta,src);
31017: }}}}m68k_incpc(4);
31018: return 18;
31019: }
31020: unsigned long REGPARAM2 CPUFUNC(op_11a0_3)(uae_u32 opcode) /* MOVE */
31021: {
31022: uae_u32 srcreg = (opcode & 7);
31023: uae_u32 dstreg = (opcode >> 9) & 7;
31024: OpcodeFamily = 30; CurrentInstrCycles = 20;
31025: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
31026: { uae_s8 src = get_byte(srca);
31027: m68k_areg (regs, srcreg) = srca;
31028: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31029: BusCyclePenalty += 2;
31030: CLEAR_CZNV;
31031: SET_ZFLG (((uae_s8)(src)) == 0);
31032: SET_NFLG (((uae_s8)(src)) < 0);
31033: put_byte(dsta,src);
31034: }}}}m68k_incpc(4);
31035: return 20;
31036: }
31037: unsigned long REGPARAM2 CPUFUNC(op_11a8_3)(uae_u32 opcode) /* MOVE */
31038: {
31039: uae_u32 srcreg = (opcode & 7);
31040: uae_u32 dstreg = (opcode >> 9) & 7;
31041: OpcodeFamily = 30; CurrentInstrCycles = 22;
31042: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
31043: { uae_s8 src = get_byte(srca);
31044: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31045: BusCyclePenalty += 2;
31046: CLEAR_CZNV;
31047: SET_ZFLG (((uae_s8)(src)) == 0);
31048: SET_NFLG (((uae_s8)(src)) < 0);
31049: put_byte(dsta,src);
31050: }}}}m68k_incpc(6);
31051: return 22;
31052: }
31053: unsigned long REGPARAM2 CPUFUNC(op_11b0_3)(uae_u32 opcode) /* MOVE */
31054: {
31055: uae_u32 srcreg = (opcode & 7);
31056: uae_u32 dstreg = (opcode >> 9) & 7;
31057: OpcodeFamily = 30; CurrentInstrCycles = 24;
31058: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31059: BusCyclePenalty += 2;
31060: { uae_s8 src = get_byte(srca);
31061: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31062: BusCyclePenalty += 2;
31063: CLEAR_CZNV;
31064: SET_ZFLG (((uae_s8)(src)) == 0);
31065: SET_NFLG (((uae_s8)(src)) < 0);
31066: put_byte(dsta,src);
31067: }}}}m68k_incpc(6);
31068: return 24;
31069: }
31070: unsigned long REGPARAM2 CPUFUNC(op_11b8_3)(uae_u32 opcode) /* MOVE */
31071: {
31072: uae_u32 dstreg = (opcode >> 9) & 7;
31073: OpcodeFamily = 30; CurrentInstrCycles = 22;
31074: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
31075: { uae_s8 src = get_byte(srca);
31076: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31077: BusCyclePenalty += 2;
31078: CLEAR_CZNV;
31079: SET_ZFLG (((uae_s8)(src)) == 0);
31080: SET_NFLG (((uae_s8)(src)) < 0);
31081: put_byte(dsta,src);
31082: }}}}m68k_incpc(6);
31083: return 22;
31084: }
31085: unsigned long REGPARAM2 CPUFUNC(op_11b9_3)(uae_u32 opcode) /* MOVE */
31086: {
31087: uae_u32 dstreg = (opcode >> 9) & 7;
31088: OpcodeFamily = 30; CurrentInstrCycles = 26;
31089: {{ uaecptr srca = get_ilong(2);
31090: { uae_s8 src = get_byte(srca);
31091: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
31092: BusCyclePenalty += 2;
31093: CLEAR_CZNV;
31094: SET_ZFLG (((uae_s8)(src)) == 0);
31095: SET_NFLG (((uae_s8)(src)) < 0);
31096: put_byte(dsta,src);
31097: }}}}m68k_incpc(8);
31098: return 26;
31099: }
31100: unsigned long REGPARAM2 CPUFUNC(op_11ba_3)(uae_u32 opcode) /* MOVE */
31101: {
31102: uae_u32 dstreg = (opcode >> 9) & 7;
31103: OpcodeFamily = 30; CurrentInstrCycles = 22;
31104: {{ uaecptr srca = m68k_getpc () + 2;
31105: srca += (uae_s32)(uae_s16)get_iword(2);
31106: { uae_s8 src = get_byte(srca);
31107: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31108: BusCyclePenalty += 2;
31109: CLEAR_CZNV;
31110: SET_ZFLG (((uae_s8)(src)) == 0);
31111: SET_NFLG (((uae_s8)(src)) < 0);
31112: put_byte(dsta,src);
31113: }}}}m68k_incpc(6);
31114: return 22;
31115: }
31116: unsigned long REGPARAM2 CPUFUNC(op_11bb_3)(uae_u32 opcode) /* MOVE */
31117: {
31118: uae_u32 dstreg = (opcode >> 9) & 7;
31119: OpcodeFamily = 30; CurrentInstrCycles = 24;
31120: {{ uaecptr tmppc = m68k_getpc() + 2;
31121: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31122: BusCyclePenalty += 2;
31123: { uae_s8 src = get_byte(srca);
31124: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31125: BusCyclePenalty += 2;
31126: CLEAR_CZNV;
31127: SET_ZFLG (((uae_s8)(src)) == 0);
31128: SET_NFLG (((uae_s8)(src)) < 0);
31129: put_byte(dsta,src);
31130: }}}}m68k_incpc(6);
31131: return 24;
31132: }
31133: unsigned long REGPARAM2 CPUFUNC(op_11bc_3)(uae_u32 opcode) /* MOVE */
31134: {
31135: uae_u32 dstreg = (opcode >> 9) & 7;
31136: OpcodeFamily = 30; CurrentInstrCycles = 18;
31137: {{ uae_s8 src = get_ibyte(2);
31138: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31139: BusCyclePenalty += 2;
31140: CLEAR_CZNV;
31141: SET_ZFLG (((uae_s8)(src)) == 0);
31142: SET_NFLG (((uae_s8)(src)) < 0);
31143: put_byte(dsta,src);
31144: }}}m68k_incpc(6);
31145: return 18;
31146: }
31147: unsigned long REGPARAM2 CPUFUNC(op_11f0_3)(uae_u32 opcode) /* MOVE */
31148: {
31149: uae_u32 srcreg = (opcode & 7);
31150: OpcodeFamily = 30; CurrentInstrCycles = 22;
31151: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31152: BusCyclePenalty += 2;
31153: { uae_s8 src = get_byte(srca);
31154: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
31155: CLEAR_CZNV;
31156: SET_ZFLG (((uae_s8)(src)) == 0);
31157: SET_NFLG (((uae_s8)(src)) < 0);
31158: put_byte(dsta,src);
31159: }}}}m68k_incpc(6);
31160: return 22;
31161: }
31162: unsigned long REGPARAM2 CPUFUNC(op_11fb_3)(uae_u32 opcode) /* MOVE */
31163: {
31164: OpcodeFamily = 30; CurrentInstrCycles = 22;
31165: {{ uaecptr tmppc = m68k_getpc() + 2;
31166: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31167: BusCyclePenalty += 2;
31168: { uae_s8 src = get_byte(srca);
31169: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
31170: CLEAR_CZNV;
31171: SET_ZFLG (((uae_s8)(src)) == 0);
31172: SET_NFLG (((uae_s8)(src)) < 0);
31173: put_byte(dsta,src);
31174: }}}}m68k_incpc(6);
31175: return 22;
31176: }
31177: unsigned long REGPARAM2 CPUFUNC(op_13f0_3)(uae_u32 opcode) /* MOVE */
31178: {
31179: uae_u32 srcreg = (opcode & 7);
31180: OpcodeFamily = 30; CurrentInstrCycles = 26;
31181: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31182: BusCyclePenalty += 2;
31183: { uae_s8 src = get_byte(srca);
31184: { uaecptr dsta = get_ilong(4);
31185: CLEAR_CZNV;
31186: SET_ZFLG (((uae_s8)(src)) == 0);
31187: SET_NFLG (((uae_s8)(src)) < 0);
31188: put_byte(dsta,src);
31189: }}}}m68k_incpc(8);
31190: return 26;
31191: }
31192: unsigned long REGPARAM2 CPUFUNC(op_13fb_3)(uae_u32 opcode) /* MOVE */
31193: {
31194: OpcodeFamily = 30; CurrentInstrCycles = 26;
31195: {{ uaecptr tmppc = m68k_getpc() + 2;
31196: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31197: BusCyclePenalty += 2;
31198: { uae_s8 src = get_byte(srca);
31199: { uaecptr dsta = get_ilong(4);
31200: CLEAR_CZNV;
31201: SET_ZFLG (((uae_s8)(src)) == 0);
31202: SET_NFLG (((uae_s8)(src)) < 0);
31203: put_byte(dsta,src);
31204: }}}}m68k_incpc(8);
31205: return 26;
31206: }
31207: unsigned long REGPARAM2 CPUFUNC(op_2030_3)(uae_u32 opcode) /* MOVE */
31208: {
31209: uae_u32 srcreg = (opcode & 7);
31210: uae_u32 dstreg = (opcode >> 9) & 7;
31211: OpcodeFamily = 30; CurrentInstrCycles = 18;
31212: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31213: BusCyclePenalty += 2;
31214: { uae_s32 src = get_long(srca);
31215: { CLEAR_CZNV;
31216: SET_ZFLG (((uae_s32)(src)) == 0);
31217: SET_NFLG (((uae_s32)(src)) < 0);
31218: m68k_dreg(regs, dstreg) = (src);
31219: }}}}m68k_incpc(4);
31220: return 18;
31221: }
31222: unsigned long REGPARAM2 CPUFUNC(op_203b_3)(uae_u32 opcode) /* MOVE */
31223: {
31224: uae_u32 dstreg = (opcode >> 9) & 7;
31225: OpcodeFamily = 30; CurrentInstrCycles = 18;
31226: {{ uaecptr tmppc = m68k_getpc() + 2;
31227: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31228: BusCyclePenalty += 2;
31229: { uae_s32 src = get_long(srca);
31230: { CLEAR_CZNV;
31231: SET_ZFLG (((uae_s32)(src)) == 0);
31232: SET_NFLG (((uae_s32)(src)) < 0);
31233: m68k_dreg(regs, dstreg) = (src);
31234: }}}}m68k_incpc(4);
31235: return 18;
31236: }
31237: unsigned long REGPARAM2 CPUFUNC(op_2070_3)(uae_u32 opcode) /* MOVEA */
31238: {
31239: uae_u32 srcreg = (opcode & 7);
31240: uae_u32 dstreg = (opcode >> 9) & 7;
31241: OpcodeFamily = 31; CurrentInstrCycles = 18;
31242: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31243: BusCyclePenalty += 2;
31244: { uae_s32 src = get_long(srca);
31245: { uae_u32 val = src;
31246: m68k_areg(regs, dstreg) = (val);
31247: }}}}m68k_incpc(4);
31248: return 18;
31249: }
31250: unsigned long REGPARAM2 CPUFUNC(op_207b_3)(uae_u32 opcode) /* MOVEA */
31251: {
31252: uae_u32 dstreg = (opcode >> 9) & 7;
31253: OpcodeFamily = 31; CurrentInstrCycles = 18;
31254: {{ uaecptr tmppc = m68k_getpc() + 2;
31255: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31256: BusCyclePenalty += 2;
31257: { uae_s32 src = get_long(srca);
31258: { uae_u32 val = src;
31259: m68k_areg(regs, dstreg) = (val);
31260: }}}}m68k_incpc(4);
31261: return 18;
31262: }
31263: unsigned long REGPARAM2 CPUFUNC(op_20b0_3)(uae_u32 opcode) /* MOVE */
31264: {
31265: uae_u32 srcreg = (opcode & 7);
31266: uae_u32 dstreg = (opcode >> 9) & 7;
31267: OpcodeFamily = 30; CurrentInstrCycles = 26;
31268: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31269: BusCyclePenalty += 2;
31270: { uae_s32 src = get_long(srca);
31271: { uaecptr dsta = m68k_areg(regs, dstreg);
31272: CLEAR_CZNV;
31273: SET_ZFLG (((uae_s32)(src)) == 0);
31274: SET_NFLG (((uae_s32)(src)) < 0);
31275: put_long(dsta,src);
31276: }}}}m68k_incpc(4);
31277: return 26;
31278: }
31279: unsigned long REGPARAM2 CPUFUNC(op_20bb_3)(uae_u32 opcode) /* MOVE */
31280: {
31281: uae_u32 dstreg = (opcode >> 9) & 7;
31282: OpcodeFamily = 30; CurrentInstrCycles = 26;
31283: {{ uaecptr tmppc = m68k_getpc() + 2;
31284: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31285: BusCyclePenalty += 2;
31286: { uae_s32 src = get_long(srca);
31287: { uaecptr dsta = m68k_areg(regs, dstreg);
31288: CLEAR_CZNV;
31289: SET_ZFLG (((uae_s32)(src)) == 0);
31290: SET_NFLG (((uae_s32)(src)) < 0);
31291: put_long(dsta,src);
31292: }}}}m68k_incpc(4);
31293: return 26;
31294: }
31295: unsigned long REGPARAM2 CPUFUNC(op_20f0_3)(uae_u32 opcode) /* MOVE */
31296: {
31297: uae_u32 srcreg = (opcode & 7);
31298: uae_u32 dstreg = (opcode >> 9) & 7;
31299: OpcodeFamily = 30; CurrentInstrCycles = 26;
31300: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31301: BusCyclePenalty += 2;
31302: { uae_s32 src = get_long(srca);
31303: { uaecptr dsta = m68k_areg(regs, dstreg);
31304: m68k_areg(regs, dstreg) += 4;
31305: CLEAR_CZNV;
31306: SET_ZFLG (((uae_s32)(src)) == 0);
31307: SET_NFLG (((uae_s32)(src)) < 0);
31308: put_long(dsta,src);
31309: }}}}m68k_incpc(4);
31310: return 26;
31311: }
31312: unsigned long REGPARAM2 CPUFUNC(op_20fb_3)(uae_u32 opcode) /* MOVE */
31313: {
31314: uae_u32 dstreg = (opcode >> 9) & 7;
31315: OpcodeFamily = 30; CurrentInstrCycles = 26;
31316: {{ uaecptr tmppc = m68k_getpc() + 2;
31317: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31318: BusCyclePenalty += 2;
31319: { uae_s32 src = get_long(srca);
31320: { uaecptr dsta = m68k_areg(regs, dstreg);
31321: m68k_areg(regs, dstreg) += 4;
31322: CLEAR_CZNV;
31323: SET_ZFLG (((uae_s32)(src)) == 0);
31324: SET_NFLG (((uae_s32)(src)) < 0);
31325: put_long(dsta,src);
31326: }}}}m68k_incpc(4);
31327: return 26;
31328: }
31329: unsigned long REGPARAM2 CPUFUNC(op_2130_3)(uae_u32 opcode) /* MOVE */
31330: {
31331: uae_u32 srcreg = (opcode & 7);
31332: uae_u32 dstreg = (opcode >> 9) & 7;
31333: OpcodeFamily = 30; CurrentInstrCycles = 26;
31334: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31335: BusCyclePenalty += 2;
31336: { uae_s32 src = get_long(srca);
31337: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
31338: m68k_areg (regs, dstreg) = dsta;
31339: CLEAR_CZNV;
31340: SET_ZFLG (((uae_s32)(src)) == 0);
31341: SET_NFLG (((uae_s32)(src)) < 0);
31342: put_long(dsta,src);
31343: }}}}m68k_incpc(4);
31344: return 26;
31345: }
31346: #endif
31347:
31348: #ifdef PART_3
31349: unsigned long REGPARAM2 CPUFUNC(op_213b_3)(uae_u32 opcode) /* MOVE */
31350: {
31351: uae_u32 dstreg = (opcode >> 9) & 7;
31352: OpcodeFamily = 30; CurrentInstrCycles = 26;
31353: {{ uaecptr tmppc = m68k_getpc() + 2;
31354: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31355: BusCyclePenalty += 2;
31356: { uae_s32 src = get_long(srca);
31357: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
31358: m68k_areg (regs, dstreg) = dsta;
31359: CLEAR_CZNV;
31360: SET_ZFLG (((uae_s32)(src)) == 0);
31361: SET_NFLG (((uae_s32)(src)) < 0);
31362: put_long(dsta,src);
31363: }}}}m68k_incpc(4);
31364: return 26;
31365: }
31366: unsigned long REGPARAM2 CPUFUNC(op_2170_3)(uae_u32 opcode) /* MOVE */
31367: {
31368: uae_u32 srcreg = (opcode & 7);
31369: uae_u32 dstreg = (opcode >> 9) & 7;
31370: OpcodeFamily = 30; CurrentInstrCycles = 30;
31371: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31372: BusCyclePenalty += 2;
31373: { uae_s32 src = get_long(srca);
31374: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
31375: CLEAR_CZNV;
31376: SET_ZFLG (((uae_s32)(src)) == 0);
31377: SET_NFLG (((uae_s32)(src)) < 0);
31378: put_long(dsta,src);
31379: }}}}m68k_incpc(6);
31380: return 30;
31381: }
31382: unsigned long REGPARAM2 CPUFUNC(op_217b_3)(uae_u32 opcode) /* MOVE */
31383: {
31384: uae_u32 dstreg = (opcode >> 9) & 7;
31385: OpcodeFamily = 30; CurrentInstrCycles = 30;
31386: {{ uaecptr tmppc = m68k_getpc() + 2;
31387: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31388: BusCyclePenalty += 2;
31389: { uae_s32 src = get_long(srca);
31390: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
31391: CLEAR_CZNV;
31392: SET_ZFLG (((uae_s32)(src)) == 0);
31393: SET_NFLG (((uae_s32)(src)) < 0);
31394: put_long(dsta,src);
31395: }}}}m68k_incpc(6);
31396: return 30;
31397: }
31398: unsigned long REGPARAM2 CPUFUNC(op_2180_3)(uae_u32 opcode) /* MOVE */
31399: {
31400: uae_u32 srcreg = (opcode & 7);
31401: uae_u32 dstreg = (opcode >> 9) & 7;
31402: OpcodeFamily = 30; CurrentInstrCycles = 18;
31403: {{ uae_s32 src = m68k_dreg(regs, srcreg);
31404: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31405: BusCyclePenalty += 2;
31406: CLEAR_CZNV;
31407: SET_ZFLG (((uae_s32)(src)) == 0);
31408: SET_NFLG (((uae_s32)(src)) < 0);
31409: put_long(dsta,src);
31410: }}}m68k_incpc(4);
31411: return 18;
31412: }
31413: unsigned long REGPARAM2 CPUFUNC(op_2188_3)(uae_u32 opcode) /* MOVE */
31414: {
31415: uae_u32 srcreg = (opcode & 7);
31416: uae_u32 dstreg = (opcode >> 9) & 7;
31417: OpcodeFamily = 30; CurrentInstrCycles = 18;
31418: {{ uae_s32 src = m68k_areg(regs, srcreg);
31419: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31420: BusCyclePenalty += 2;
31421: CLEAR_CZNV;
31422: SET_ZFLG (((uae_s32)(src)) == 0);
31423: SET_NFLG (((uae_s32)(src)) < 0);
31424: put_long(dsta,src);
31425: }}}m68k_incpc(4);
31426: return 18;
31427: }
31428: unsigned long REGPARAM2 CPUFUNC(op_2190_3)(uae_u32 opcode) /* MOVE */
31429: {
31430: uae_u32 srcreg = (opcode & 7);
31431: uae_u32 dstreg = (opcode >> 9) & 7;
31432: OpcodeFamily = 30; CurrentInstrCycles = 26;
31433: {{ uaecptr srca = m68k_areg(regs, srcreg);
31434: { uae_s32 src = get_long(srca);
31435: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31436: BusCyclePenalty += 2;
31437: CLEAR_CZNV;
31438: SET_ZFLG (((uae_s32)(src)) == 0);
31439: SET_NFLG (((uae_s32)(src)) < 0);
31440: put_long(dsta,src);
31441: }}}}m68k_incpc(4);
31442: return 26;
31443: }
31444: unsigned long REGPARAM2 CPUFUNC(op_2198_3)(uae_u32 opcode) /* MOVE */
31445: {
31446: uae_u32 srcreg = (opcode & 7);
31447: uae_u32 dstreg = (opcode >> 9) & 7;
31448: OpcodeFamily = 30; CurrentInstrCycles = 26;
31449: {{ uaecptr srca = m68k_areg(regs, srcreg);
31450: { uae_s32 src = get_long(srca);
31451: m68k_areg(regs, srcreg) += 4;
31452: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31453: BusCyclePenalty += 2;
31454: CLEAR_CZNV;
31455: SET_ZFLG (((uae_s32)(src)) == 0);
31456: SET_NFLG (((uae_s32)(src)) < 0);
31457: put_long(dsta,src);
31458: }}}}m68k_incpc(4);
31459: return 26;
31460: }
31461: unsigned long REGPARAM2 CPUFUNC(op_21a0_3)(uae_u32 opcode) /* MOVE */
31462: {
31463: uae_u32 srcreg = (opcode & 7);
31464: uae_u32 dstreg = (opcode >> 9) & 7;
31465: OpcodeFamily = 30; CurrentInstrCycles = 28;
31466: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
31467: { uae_s32 src = get_long(srca);
31468: m68k_areg (regs, srcreg) = srca;
31469: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31470: BusCyclePenalty += 2;
31471: CLEAR_CZNV;
31472: SET_ZFLG (((uae_s32)(src)) == 0);
31473: SET_NFLG (((uae_s32)(src)) < 0);
31474: put_long(dsta,src);
31475: }}}}m68k_incpc(4);
31476: return 28;
31477: }
31478: unsigned long REGPARAM2 CPUFUNC(op_21a8_3)(uae_u32 opcode) /* MOVE */
31479: {
31480: uae_u32 srcreg = (opcode & 7);
31481: uae_u32 dstreg = (opcode >> 9) & 7;
31482: OpcodeFamily = 30; CurrentInstrCycles = 30;
31483: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
31484: { uae_s32 src = get_long(srca);
31485: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31486: BusCyclePenalty += 2;
31487: CLEAR_CZNV;
31488: SET_ZFLG (((uae_s32)(src)) == 0);
31489: SET_NFLG (((uae_s32)(src)) < 0);
31490: put_long(dsta,src);
31491: }}}}m68k_incpc(6);
31492: return 30;
31493: }
31494: unsigned long REGPARAM2 CPUFUNC(op_21b0_3)(uae_u32 opcode) /* MOVE */
31495: {
31496: uae_u32 srcreg = (opcode & 7);
31497: uae_u32 dstreg = (opcode >> 9) & 7;
31498: OpcodeFamily = 30; CurrentInstrCycles = 32;
31499: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31500: BusCyclePenalty += 2;
31501: { uae_s32 src = get_long(srca);
31502: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31503: BusCyclePenalty += 2;
31504: CLEAR_CZNV;
31505: SET_ZFLG (((uae_s32)(src)) == 0);
31506: SET_NFLG (((uae_s32)(src)) < 0);
31507: put_long(dsta,src);
31508: }}}}m68k_incpc(6);
31509: return 32;
31510: }
31511: unsigned long REGPARAM2 CPUFUNC(op_21b8_3)(uae_u32 opcode) /* MOVE */
31512: {
31513: uae_u32 dstreg = (opcode >> 9) & 7;
31514: OpcodeFamily = 30; CurrentInstrCycles = 30;
31515: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
31516: { uae_s32 src = get_long(srca);
31517: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31518: BusCyclePenalty += 2;
31519: CLEAR_CZNV;
31520: SET_ZFLG (((uae_s32)(src)) == 0);
31521: SET_NFLG (((uae_s32)(src)) < 0);
31522: put_long(dsta,src);
31523: }}}}m68k_incpc(6);
31524: return 30;
31525: }
31526: unsigned long REGPARAM2 CPUFUNC(op_21b9_3)(uae_u32 opcode) /* MOVE */
31527: {
31528: uae_u32 dstreg = (opcode >> 9) & 7;
31529: OpcodeFamily = 30; CurrentInstrCycles = 34;
31530: {{ uaecptr srca = get_ilong(2);
31531: { uae_s32 src = get_long(srca);
31532: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
31533: BusCyclePenalty += 2;
31534: CLEAR_CZNV;
31535: SET_ZFLG (((uae_s32)(src)) == 0);
31536: SET_NFLG (((uae_s32)(src)) < 0);
31537: put_long(dsta,src);
31538: }}}}m68k_incpc(8);
31539: return 34;
31540: }
31541: unsigned long REGPARAM2 CPUFUNC(op_21ba_3)(uae_u32 opcode) /* MOVE */
31542: {
31543: uae_u32 dstreg = (opcode >> 9) & 7;
31544: OpcodeFamily = 30; CurrentInstrCycles = 30;
31545: {{ uaecptr srca = m68k_getpc () + 2;
31546: srca += (uae_s32)(uae_s16)get_iword(2);
31547: { uae_s32 src = get_long(srca);
31548: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31549: BusCyclePenalty += 2;
31550: CLEAR_CZNV;
31551: SET_ZFLG (((uae_s32)(src)) == 0);
31552: SET_NFLG (((uae_s32)(src)) < 0);
31553: put_long(dsta,src);
31554: }}}}m68k_incpc(6);
31555: return 30;
31556: }
31557: unsigned long REGPARAM2 CPUFUNC(op_21bb_3)(uae_u32 opcode) /* MOVE */
31558: {
31559: uae_u32 dstreg = (opcode >> 9) & 7;
31560: OpcodeFamily = 30; CurrentInstrCycles = 32;
31561: {{ uaecptr tmppc = m68k_getpc() + 2;
31562: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31563: BusCyclePenalty += 2;
31564: { uae_s32 src = get_long(srca);
31565: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31566: BusCyclePenalty += 2;
31567: CLEAR_CZNV;
31568: SET_ZFLG (((uae_s32)(src)) == 0);
31569: SET_NFLG (((uae_s32)(src)) < 0);
31570: put_long(dsta,src);
31571: }}}}m68k_incpc(6);
31572: return 32;
31573: }
31574: unsigned long REGPARAM2 CPUFUNC(op_21bc_3)(uae_u32 opcode) /* MOVE */
31575: {
31576: uae_u32 dstreg = (opcode >> 9) & 7;
31577: OpcodeFamily = 30; CurrentInstrCycles = 26;
31578: {{ uae_s32 src = get_ilong(2);
31579: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
31580: BusCyclePenalty += 2;
31581: CLEAR_CZNV;
31582: SET_ZFLG (((uae_s32)(src)) == 0);
31583: SET_NFLG (((uae_s32)(src)) < 0);
31584: put_long(dsta,src);
31585: }}}m68k_incpc(8);
31586: return 26;
31587: }
31588: unsigned long REGPARAM2 CPUFUNC(op_21f0_3)(uae_u32 opcode) /* MOVE */
31589: {
31590: uae_u32 srcreg = (opcode & 7);
31591: OpcodeFamily = 30; CurrentInstrCycles = 30;
31592: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31593: BusCyclePenalty += 2;
31594: { uae_s32 src = get_long(srca);
31595: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
31596: CLEAR_CZNV;
31597: SET_ZFLG (((uae_s32)(src)) == 0);
31598: SET_NFLG (((uae_s32)(src)) < 0);
31599: put_long(dsta,src);
31600: }}}}m68k_incpc(6);
31601: return 30;
31602: }
31603: unsigned long REGPARAM2 CPUFUNC(op_21fb_3)(uae_u32 opcode) /* MOVE */
31604: {
31605: OpcodeFamily = 30; CurrentInstrCycles = 30;
31606: {{ uaecptr tmppc = m68k_getpc() + 2;
31607: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31608: BusCyclePenalty += 2;
31609: { uae_s32 src = get_long(srca);
31610: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
31611: CLEAR_CZNV;
31612: SET_ZFLG (((uae_s32)(src)) == 0);
31613: SET_NFLG (((uae_s32)(src)) < 0);
31614: put_long(dsta,src);
31615: }}}}m68k_incpc(6);
31616: return 30;
31617: }
31618: unsigned long REGPARAM2 CPUFUNC(op_23f0_3)(uae_u32 opcode) /* MOVE */
31619: {
31620: uae_u32 srcreg = (opcode & 7);
31621: OpcodeFamily = 30; CurrentInstrCycles = 34;
31622: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31623: BusCyclePenalty += 2;
31624: { uae_s32 src = get_long(srca);
31625: { uaecptr dsta = get_ilong(4);
31626: CLEAR_CZNV;
31627: SET_ZFLG (((uae_s32)(src)) == 0);
31628: SET_NFLG (((uae_s32)(src)) < 0);
31629: put_long(dsta,src);
31630: }}}}m68k_incpc(8);
31631: return 34;
31632: }
31633: unsigned long REGPARAM2 CPUFUNC(op_23fb_3)(uae_u32 opcode) /* MOVE */
31634: {
31635: OpcodeFamily = 30; CurrentInstrCycles = 34;
31636: {{ uaecptr tmppc = m68k_getpc() + 2;
31637: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31638: BusCyclePenalty += 2;
31639: { uae_s32 src = get_long(srca);
31640: { uaecptr dsta = get_ilong(4);
31641: CLEAR_CZNV;
31642: SET_ZFLG (((uae_s32)(src)) == 0);
31643: SET_NFLG (((uae_s32)(src)) < 0);
31644: put_long(dsta,src);
31645: }}}}m68k_incpc(8);
31646: return 34;
31647: }
31648: unsigned long REGPARAM2 CPUFUNC(op_3030_3)(uae_u32 opcode) /* MOVE */
31649: {
31650: uae_u32 srcreg = (opcode & 7);
31651: uae_u32 dstreg = (opcode >> 9) & 7;
31652: OpcodeFamily = 30; CurrentInstrCycles = 14;
31653: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31654: BusCyclePenalty += 2;
31655: { uae_s16 src = get_word(srca);
31656: { CLEAR_CZNV;
31657: SET_ZFLG (((uae_s16)(src)) == 0);
31658: SET_NFLG (((uae_s16)(src)) < 0);
31659: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
31660: }}}}m68k_incpc(4);
31661: return 14;
31662: }
31663: unsigned long REGPARAM2 CPUFUNC(op_303b_3)(uae_u32 opcode) /* MOVE */
31664: {
31665: uae_u32 dstreg = (opcode >> 9) & 7;
31666: OpcodeFamily = 30; CurrentInstrCycles = 14;
31667: {{ uaecptr tmppc = m68k_getpc() + 2;
31668: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31669: BusCyclePenalty += 2;
31670: { uae_s16 src = get_word(srca);
31671: { CLEAR_CZNV;
31672: SET_ZFLG (((uae_s16)(src)) == 0);
31673: SET_NFLG (((uae_s16)(src)) < 0);
31674: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
31675: }}}}m68k_incpc(4);
31676: return 14;
31677: }
31678: unsigned long REGPARAM2 CPUFUNC(op_3070_3)(uae_u32 opcode) /* MOVEA */
31679: {
31680: uae_u32 srcreg = (opcode & 7);
31681: uae_u32 dstreg = (opcode >> 9) & 7;
31682: OpcodeFamily = 31; CurrentInstrCycles = 14;
31683: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31684: BusCyclePenalty += 2;
31685: { uae_s16 src = get_word(srca);
31686: { uae_u32 val = (uae_s32)(uae_s16)src;
31687: m68k_areg(regs, dstreg) = (val);
31688: }}}}m68k_incpc(4);
31689: return 14;
31690: }
31691: unsigned long REGPARAM2 CPUFUNC(op_307b_3)(uae_u32 opcode) /* MOVEA */
31692: {
31693: uae_u32 dstreg = (opcode >> 9) & 7;
31694: OpcodeFamily = 31; CurrentInstrCycles = 14;
31695: {{ uaecptr tmppc = m68k_getpc() + 2;
31696: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31697: BusCyclePenalty += 2;
31698: { uae_s16 src = get_word(srca);
31699: { uae_u32 val = (uae_s32)(uae_s16)src;
31700: m68k_areg(regs, dstreg) = (val);
31701: }}}}m68k_incpc(4);
31702: return 14;
31703: }
31704: unsigned long REGPARAM2 CPUFUNC(op_30b0_3)(uae_u32 opcode) /* MOVE */
31705: {
31706: uae_u32 srcreg = (opcode & 7);
31707: uae_u32 dstreg = (opcode >> 9) & 7;
31708: OpcodeFamily = 30; CurrentInstrCycles = 18;
31709: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31710: BusCyclePenalty += 2;
31711: { uae_s16 src = get_word(srca);
31712: { uaecptr dsta = m68k_areg(regs, dstreg);
31713: CLEAR_CZNV;
31714: SET_ZFLG (((uae_s16)(src)) == 0);
31715: SET_NFLG (((uae_s16)(src)) < 0);
31716: put_word(dsta,src);
31717: }}}}m68k_incpc(4);
31718: return 18;
31719: }
31720: unsigned long REGPARAM2 CPUFUNC(op_30bb_3)(uae_u32 opcode) /* MOVE */
31721: {
31722: uae_u32 dstreg = (opcode >> 9) & 7;
31723: OpcodeFamily = 30; CurrentInstrCycles = 18;
31724: {{ uaecptr tmppc = m68k_getpc() + 2;
31725: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31726: BusCyclePenalty += 2;
31727: { uae_s16 src = get_word(srca);
31728: { uaecptr dsta = m68k_areg(regs, dstreg);
31729: CLEAR_CZNV;
31730: SET_ZFLG (((uae_s16)(src)) == 0);
31731: SET_NFLG (((uae_s16)(src)) < 0);
31732: put_word(dsta,src);
31733: }}}}m68k_incpc(4);
31734: return 18;
31735: }
31736: unsigned long REGPARAM2 CPUFUNC(op_30f0_3)(uae_u32 opcode) /* MOVE */
31737: {
31738: uae_u32 srcreg = (opcode & 7);
31739: uae_u32 dstreg = (opcode >> 9) & 7;
31740: OpcodeFamily = 30; CurrentInstrCycles = 18;
31741: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31742: BusCyclePenalty += 2;
31743: { uae_s16 src = get_word(srca);
31744: { uaecptr dsta = m68k_areg(regs, dstreg);
31745: m68k_areg(regs, dstreg) += 2;
31746: CLEAR_CZNV;
31747: SET_ZFLG (((uae_s16)(src)) == 0);
31748: SET_NFLG (((uae_s16)(src)) < 0);
31749: put_word(dsta,src);
31750: }}}}m68k_incpc(4);
31751: return 18;
31752: }
31753: unsigned long REGPARAM2 CPUFUNC(op_30fb_3)(uae_u32 opcode) /* MOVE */
31754: {
31755: uae_u32 dstreg = (opcode >> 9) & 7;
31756: OpcodeFamily = 30; CurrentInstrCycles = 18;
31757: {{ uaecptr tmppc = m68k_getpc() + 2;
31758: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31759: BusCyclePenalty += 2;
31760: { uae_s16 src = get_word(srca);
31761: { uaecptr dsta = m68k_areg(regs, dstreg);
31762: m68k_areg(regs, dstreg) += 2;
31763: CLEAR_CZNV;
31764: SET_ZFLG (((uae_s16)(src)) == 0);
31765: SET_NFLG (((uae_s16)(src)) < 0);
31766: put_word(dsta,src);
31767: }}}}m68k_incpc(4);
31768: return 18;
31769: }
31770: unsigned long REGPARAM2 CPUFUNC(op_3130_3)(uae_u32 opcode) /* MOVE */
31771: {
31772: uae_u32 srcreg = (opcode & 7);
31773: uae_u32 dstreg = (opcode >> 9) & 7;
31774: OpcodeFamily = 30; CurrentInstrCycles = 18;
31775: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31776: BusCyclePenalty += 2;
31777: { uae_s16 src = get_word(srca);
31778: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
31779: m68k_areg (regs, dstreg) = dsta;
31780: CLEAR_CZNV;
31781: SET_ZFLG (((uae_s16)(src)) == 0);
31782: SET_NFLG (((uae_s16)(src)) < 0);
31783: put_word(dsta,src);
31784: }}}}m68k_incpc(4);
31785: return 18;
31786: }
31787: unsigned long REGPARAM2 CPUFUNC(op_313b_3)(uae_u32 opcode) /* MOVE */
31788: {
31789: uae_u32 dstreg = (opcode >> 9) & 7;
31790: OpcodeFamily = 30; CurrentInstrCycles = 18;
31791: {{ uaecptr tmppc = m68k_getpc() + 2;
31792: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31793: BusCyclePenalty += 2;
31794: { uae_s16 src = get_word(srca);
31795: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
31796: m68k_areg (regs, dstreg) = dsta;
31797: CLEAR_CZNV;
31798: SET_ZFLG (((uae_s16)(src)) == 0);
31799: SET_NFLG (((uae_s16)(src)) < 0);
31800: put_word(dsta,src);
31801: }}}}m68k_incpc(4);
31802: return 18;
31803: }
31804: unsigned long REGPARAM2 CPUFUNC(op_3170_3)(uae_u32 opcode) /* MOVE */
31805: {
31806: uae_u32 srcreg = (opcode & 7);
31807: uae_u32 dstreg = (opcode >> 9) & 7;
31808: OpcodeFamily = 30; CurrentInstrCycles = 22;
31809: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31810: BusCyclePenalty += 2;
31811: { uae_s16 src = get_word(srca);
31812: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
31813: CLEAR_CZNV;
31814: SET_ZFLG (((uae_s16)(src)) == 0);
31815: SET_NFLG (((uae_s16)(src)) < 0);
31816: put_word(dsta,src);
31817: }}}}m68k_incpc(6);
31818: return 22;
31819: }
31820: unsigned long REGPARAM2 CPUFUNC(op_317b_3)(uae_u32 opcode) /* MOVE */
31821: {
31822: uae_u32 dstreg = (opcode >> 9) & 7;
31823: OpcodeFamily = 30; CurrentInstrCycles = 22;
31824: {{ uaecptr tmppc = m68k_getpc() + 2;
31825: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
31826: BusCyclePenalty += 2;
31827: { uae_s16 src = get_word(srca);
31828: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword(4);
31829: CLEAR_CZNV;
31830: SET_ZFLG (((uae_s16)(src)) == 0);
31831: SET_NFLG (((uae_s16)(src)) < 0);
31832: put_word(dsta,src);
31833: }}}}m68k_incpc(6);
31834: return 22;
31835: }
31836: unsigned long REGPARAM2 CPUFUNC(op_3180_3)(uae_u32 opcode) /* MOVE */
31837: {
31838: uae_u32 srcreg = (opcode & 7);
31839: uae_u32 dstreg = (opcode >> 9) & 7;
31840: OpcodeFamily = 30; CurrentInstrCycles = 14;
31841: {{ uae_s16 src = m68k_dreg(regs, srcreg);
31842: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31843: BusCyclePenalty += 2;
31844: CLEAR_CZNV;
31845: SET_ZFLG (((uae_s16)(src)) == 0);
31846: SET_NFLG (((uae_s16)(src)) < 0);
31847: put_word(dsta,src);
31848: }}}m68k_incpc(4);
31849: return 14;
31850: }
31851: unsigned long REGPARAM2 CPUFUNC(op_3188_3)(uae_u32 opcode) /* MOVE */
31852: {
31853: uae_u32 srcreg = (opcode & 7);
31854: uae_u32 dstreg = (opcode >> 9) & 7;
31855: OpcodeFamily = 30; CurrentInstrCycles = 14;
31856: {{ uae_s16 src = m68k_areg(regs, srcreg);
31857: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31858: BusCyclePenalty += 2;
31859: CLEAR_CZNV;
31860: SET_ZFLG (((uae_s16)(src)) == 0);
31861: SET_NFLG (((uae_s16)(src)) < 0);
31862: put_word(dsta,src);
31863: }}}m68k_incpc(4);
31864: return 14;
31865: }
31866: unsigned long REGPARAM2 CPUFUNC(op_3190_3)(uae_u32 opcode) /* MOVE */
31867: {
31868: uae_u32 srcreg = (opcode & 7);
31869: uae_u32 dstreg = (opcode >> 9) & 7;
31870: OpcodeFamily = 30; CurrentInstrCycles = 18;
31871: {{ uaecptr srca = m68k_areg(regs, srcreg);
31872: { uae_s16 src = get_word(srca);
31873: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31874: BusCyclePenalty += 2;
31875: CLEAR_CZNV;
31876: SET_ZFLG (((uae_s16)(src)) == 0);
31877: SET_NFLG (((uae_s16)(src)) < 0);
31878: put_word(dsta,src);
31879: }}}}m68k_incpc(4);
31880: return 18;
31881: }
31882: unsigned long REGPARAM2 CPUFUNC(op_3198_3)(uae_u32 opcode) /* MOVE */
31883: {
31884: uae_u32 srcreg = (opcode & 7);
31885: uae_u32 dstreg = (opcode >> 9) & 7;
31886: OpcodeFamily = 30; CurrentInstrCycles = 18;
31887: {{ uaecptr srca = m68k_areg(regs, srcreg);
31888: { uae_s16 src = get_word(srca);
31889: m68k_areg(regs, srcreg) += 2;
31890: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31891: BusCyclePenalty += 2;
31892: CLEAR_CZNV;
31893: SET_ZFLG (((uae_s16)(src)) == 0);
31894: SET_NFLG (((uae_s16)(src)) < 0);
31895: put_word(dsta,src);
31896: }}}}m68k_incpc(4);
31897: return 18;
31898: }
31899: unsigned long REGPARAM2 CPUFUNC(op_31a0_3)(uae_u32 opcode) /* MOVE */
31900: {
31901: uae_u32 srcreg = (opcode & 7);
31902: uae_u32 dstreg = (opcode >> 9) & 7;
31903: OpcodeFamily = 30; CurrentInstrCycles = 20;
31904: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
31905: { uae_s16 src = get_word(srca);
31906: m68k_areg (regs, srcreg) = srca;
31907: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
31908: BusCyclePenalty += 2;
31909: CLEAR_CZNV;
31910: SET_ZFLG (((uae_s16)(src)) == 0);
31911: SET_NFLG (((uae_s16)(src)) < 0);
31912: put_word(dsta,src);
31913: }}}}m68k_incpc(4);
31914: return 20;
31915: }
31916: unsigned long REGPARAM2 CPUFUNC(op_31a8_3)(uae_u32 opcode) /* MOVE */
31917: {
31918: uae_u32 srcreg = (opcode & 7);
31919: uae_u32 dstreg = (opcode >> 9) & 7;
31920: OpcodeFamily = 30; CurrentInstrCycles = 22;
31921: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
31922: { uae_s16 src = get_word(srca);
31923: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31924: BusCyclePenalty += 2;
31925: CLEAR_CZNV;
31926: SET_ZFLG (((uae_s16)(src)) == 0);
31927: SET_NFLG (((uae_s16)(src)) < 0);
31928: put_word(dsta,src);
31929: }}}}m68k_incpc(6);
31930: return 22;
31931: }
31932: unsigned long REGPARAM2 CPUFUNC(op_31b0_3)(uae_u32 opcode) /* MOVE */
31933: {
31934: uae_u32 srcreg = (opcode & 7);
31935: uae_u32 dstreg = (opcode >> 9) & 7;
31936: OpcodeFamily = 30; CurrentInstrCycles = 24;
31937: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
31938: BusCyclePenalty += 2;
31939: { uae_s16 src = get_word(srca);
31940: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31941: BusCyclePenalty += 2;
31942: CLEAR_CZNV;
31943: SET_ZFLG (((uae_s16)(src)) == 0);
31944: SET_NFLG (((uae_s16)(src)) < 0);
31945: put_word(dsta,src);
31946: }}}}m68k_incpc(6);
31947: return 24;
31948: }
31949: unsigned long REGPARAM2 CPUFUNC(op_31b8_3)(uae_u32 opcode) /* MOVE */
31950: {
31951: uae_u32 dstreg = (opcode >> 9) & 7;
31952: OpcodeFamily = 30; CurrentInstrCycles = 22;
31953: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
31954: { uae_s16 src = get_word(srca);
31955: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31956: BusCyclePenalty += 2;
31957: CLEAR_CZNV;
31958: SET_ZFLG (((uae_s16)(src)) == 0);
31959: SET_NFLG (((uae_s16)(src)) < 0);
31960: put_word(dsta,src);
31961: }}}}m68k_incpc(6);
31962: return 22;
31963: }
31964: unsigned long REGPARAM2 CPUFUNC(op_31b9_3)(uae_u32 opcode) /* MOVE */
31965: {
31966: uae_u32 dstreg = (opcode >> 9) & 7;
31967: OpcodeFamily = 30; CurrentInstrCycles = 26;
31968: {{ uaecptr srca = get_ilong(2);
31969: { uae_s16 src = get_word(srca);
31970: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
31971: BusCyclePenalty += 2;
31972: CLEAR_CZNV;
31973: SET_ZFLG (((uae_s16)(src)) == 0);
31974: SET_NFLG (((uae_s16)(src)) < 0);
31975: put_word(dsta,src);
31976: }}}}m68k_incpc(8);
31977: return 26;
31978: }
31979: unsigned long REGPARAM2 CPUFUNC(op_31ba_3)(uae_u32 opcode) /* MOVE */
31980: {
31981: uae_u32 dstreg = (opcode >> 9) & 7;
31982: OpcodeFamily = 30; CurrentInstrCycles = 22;
31983: {{ uaecptr srca = m68k_getpc () + 2;
31984: srca += (uae_s32)(uae_s16)get_iword(2);
31985: { uae_s16 src = get_word(srca);
31986: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
31987: BusCyclePenalty += 2;
31988: CLEAR_CZNV;
31989: SET_ZFLG (((uae_s16)(src)) == 0);
31990: SET_NFLG (((uae_s16)(src)) < 0);
31991: put_word(dsta,src);
31992: }}}}m68k_incpc(6);
31993: return 22;
31994: }
31995: unsigned long REGPARAM2 CPUFUNC(op_31bb_3)(uae_u32 opcode) /* MOVE */
31996: {
31997: uae_u32 dstreg = (opcode >> 9) & 7;
31998: OpcodeFamily = 30; CurrentInstrCycles = 24;
31999: {{ uaecptr tmppc = m68k_getpc() + 2;
32000: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32001: BusCyclePenalty += 2;
32002: { uae_s16 src = get_word(srca);
32003: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
32004: BusCyclePenalty += 2;
32005: CLEAR_CZNV;
32006: SET_ZFLG (((uae_s16)(src)) == 0);
32007: SET_NFLG (((uae_s16)(src)) < 0);
32008: put_word(dsta,src);
32009: }}}}m68k_incpc(6);
32010: return 24;
32011: }
32012: unsigned long REGPARAM2 CPUFUNC(op_31bc_3)(uae_u32 opcode) /* MOVE */
32013: {
32014: uae_u32 dstreg = (opcode >> 9) & 7;
32015: OpcodeFamily = 30; CurrentInstrCycles = 18;
32016: {{ uae_s16 src = get_iword(2);
32017: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
32018: BusCyclePenalty += 2;
32019: CLEAR_CZNV;
32020: SET_ZFLG (((uae_s16)(src)) == 0);
32021: SET_NFLG (((uae_s16)(src)) < 0);
32022: put_word(dsta,src);
32023: }}}m68k_incpc(6);
32024: return 18;
32025: }
32026: unsigned long REGPARAM2 CPUFUNC(op_31f0_3)(uae_u32 opcode) /* MOVE */
32027: {
32028: uae_u32 srcreg = (opcode & 7);
32029: OpcodeFamily = 30; CurrentInstrCycles = 22;
32030: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32031: BusCyclePenalty += 2;
32032: { uae_s16 src = get_word(srca);
32033: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
32034: CLEAR_CZNV;
32035: SET_ZFLG (((uae_s16)(src)) == 0);
32036: SET_NFLG (((uae_s16)(src)) < 0);
32037: put_word(dsta,src);
32038: }}}}m68k_incpc(6);
32039: return 22;
32040: }
32041: unsigned long REGPARAM2 CPUFUNC(op_31fb_3)(uae_u32 opcode) /* MOVE */
32042: {
32043: OpcodeFamily = 30; CurrentInstrCycles = 22;
32044: {{ uaecptr tmppc = m68k_getpc() + 2;
32045: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32046: BusCyclePenalty += 2;
32047: { uae_s16 src = get_word(srca);
32048: { uaecptr dsta = (uae_s32)(uae_s16)get_iword(4);
32049: CLEAR_CZNV;
32050: SET_ZFLG (((uae_s16)(src)) == 0);
32051: SET_NFLG (((uae_s16)(src)) < 0);
32052: put_word(dsta,src);
32053: }}}}m68k_incpc(6);
32054: return 22;
32055: }
32056: unsigned long REGPARAM2 CPUFUNC(op_33f0_3)(uae_u32 opcode) /* MOVE */
32057: {
32058: uae_u32 srcreg = (opcode & 7);
32059: OpcodeFamily = 30; CurrentInstrCycles = 26;
32060: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32061: BusCyclePenalty += 2;
32062: { uae_s16 src = get_word(srca);
32063: { uaecptr dsta = get_ilong(4);
32064: CLEAR_CZNV;
32065: SET_ZFLG (((uae_s16)(src)) == 0);
32066: SET_NFLG (((uae_s16)(src)) < 0);
32067: put_word(dsta,src);
32068: }}}}m68k_incpc(8);
32069: return 26;
32070: }
32071: unsigned long REGPARAM2 CPUFUNC(op_33fb_3)(uae_u32 opcode) /* MOVE */
32072: {
32073: OpcodeFamily = 30; CurrentInstrCycles = 26;
32074: {{ uaecptr tmppc = m68k_getpc() + 2;
32075: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32076: BusCyclePenalty += 2;
32077: { uae_s16 src = get_word(srca);
32078: { uaecptr dsta = get_ilong(4);
32079: CLEAR_CZNV;
32080: SET_ZFLG (((uae_s16)(src)) == 0);
32081: SET_NFLG (((uae_s16)(src)) < 0);
32082: put_word(dsta,src);
32083: }}}}m68k_incpc(8);
32084: return 26;
32085: }
32086: unsigned long REGPARAM2 CPUFUNC(op_4030_3)(uae_u32 opcode) /* NEGX */
32087: {
32088: uae_u32 srcreg = (opcode & 7);
32089: OpcodeFamily = 16; CurrentInstrCycles = 18;
32090: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32091: BusCyclePenalty += 2;
32092: { uae_s8 src = get_byte(srca);
32093: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
32094: { int flgs = ((uae_s8)(src)) < 0;
32095: int flgo = ((uae_s8)(0)) < 0;
32096: int flgn = ((uae_s8)(newv)) < 0;
32097: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
32098: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
32099: COPY_CARRY;
32100: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
32101: SET_NFLG (((uae_s8)(newv)) < 0);
32102: put_byte(srca,newv);
32103: }}}}}m68k_incpc(4);
32104: return 18;
32105: }
32106: unsigned long REGPARAM2 CPUFUNC(op_4070_3)(uae_u32 opcode) /* NEGX */
32107: {
32108: uae_u32 srcreg = (opcode & 7);
32109: OpcodeFamily = 16; CurrentInstrCycles = 18;
32110: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32111: BusCyclePenalty += 2;
32112: { uae_s16 src = get_word(srca);
32113: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
32114: { int flgs = ((uae_s16)(src)) < 0;
32115: int flgo = ((uae_s16)(0)) < 0;
32116: int flgn = ((uae_s16)(newv)) < 0;
32117: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
32118: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
32119: COPY_CARRY;
32120: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
32121: SET_NFLG (((uae_s16)(newv)) < 0);
32122: put_word(srca,newv);
32123: }}}}}m68k_incpc(4);
32124: return 18;
32125: }
32126: unsigned long REGPARAM2 CPUFUNC(op_40b0_3)(uae_u32 opcode) /* NEGX */
32127: {
32128: uae_u32 srcreg = (opcode & 7);
32129: OpcodeFamily = 16; CurrentInstrCycles = 26;
32130: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32131: BusCyclePenalty += 2;
32132: { uae_s32 src = get_long(srca);
32133: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
32134: { int flgs = ((uae_s32)(src)) < 0;
32135: int flgo = ((uae_s32)(0)) < 0;
32136: int flgn = ((uae_s32)(newv)) < 0;
32137: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
32138: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
32139: COPY_CARRY;
32140: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
32141: SET_NFLG (((uae_s32)(newv)) < 0);
32142: put_long(srca,newv);
32143: }}}}}m68k_incpc(4);
32144: return 26;
32145: }
32146: unsigned long REGPARAM2 CPUFUNC(op_40f0_3)(uae_u32 opcode) /* MVSR2 */
32147: {
32148: uae_u32 srcreg = (opcode & 7);
32149: OpcodeFamily = 32; CurrentInstrCycles = 18;
32150: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1997; }
32151: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32152: BusCyclePenalty += 2;
32153: MakeSR();
32154: put_word(srca,regs.sr);
32155: }}}m68k_incpc(4);
32156: endlabel1997: ;
32157: return 18;
32158: }
32159: unsigned long REGPARAM2 CPUFUNC(op_41b0_3)(uae_u32 opcode) /* CHK */
32160: {
32161: uae_u32 srcreg = (opcode & 7);
32162: uae_u32 dstreg = (opcode >> 9) & 7;
32163: OpcodeFamily = 80; CurrentInstrCycles = 20;
32164: { uaecptr oldpc = m68k_getpc();
32165: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32166: BusCyclePenalty += 2;
32167: { uae_s16 src = get_word(srca);
32168: { uae_s16 dst = m68k_dreg(regs, dstreg);
32169: m68k_incpc(4);
32170: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel1998; }
32171: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel1998; }
32172: }}}}endlabel1998: ;
32173: return 20;
32174: }
32175: unsigned long REGPARAM2 CPUFUNC(op_41bb_3)(uae_u32 opcode) /* CHK */
32176: {
32177: uae_u32 dstreg = (opcode >> 9) & 7;
32178: OpcodeFamily = 80; CurrentInstrCycles = 20;
32179: { uaecptr oldpc = m68k_getpc();
32180: { uaecptr tmppc = m68k_getpc() + 2;
32181: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32182: BusCyclePenalty += 2;
32183: { uae_s16 src = get_word(srca);
32184: { uae_s16 dst = m68k_dreg(regs, dstreg);
32185: m68k_incpc(4);
32186: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel1999; }
32187: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel1999; }
32188: }}}}endlabel1999: ;
32189: return 20;
32190: }
32191: unsigned long REGPARAM2 CPUFUNC(op_41f0_3)(uae_u32 opcode) /* LEA */
32192: {
32193: uae_u32 srcreg = (opcode & 7);
32194: uae_u32 dstreg = (opcode >> 9) & 7;
32195: OpcodeFamily = 56; CurrentInstrCycles = 14;
32196: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32197: BusCyclePenalty += 2;
32198: { m68k_areg(regs, dstreg) = (srca);
32199: }}}m68k_incpc(4);
32200: return 14;
32201: }
32202: unsigned long REGPARAM2 CPUFUNC(op_41fb_3)(uae_u32 opcode) /* LEA */
32203: {
32204: uae_u32 dstreg = (opcode >> 9) & 7;
32205: OpcodeFamily = 56; CurrentInstrCycles = 14;
32206: {{ uaecptr tmppc = m68k_getpc() + 2;
32207: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32208: BusCyclePenalty += 2;
32209: { m68k_areg(regs, dstreg) = (srca);
32210: }}}m68k_incpc(4);
32211: return 14;
32212: }
32213: unsigned long REGPARAM2 CPUFUNC(op_4230_3)(uae_u32 opcode) /* CLR */
32214: {
32215: uae_u32 srcreg = (opcode & 7);
32216: OpcodeFamily = 18; CurrentInstrCycles = 18;
32217: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32218: BusCyclePenalty += 2;
32219: uae_s8 src = get_byte(srca);
32220: CLEAR_CZNV;
32221: SET_ZFLG (((uae_s8)(0)) == 0);
32222: SET_NFLG (((uae_s8)(0)) < 0);
32223: put_byte(srca,0);
32224: }}m68k_incpc(4);
32225: return 18;
32226: }
32227: #endif
32228:
32229: #ifdef PART_4
32230: unsigned long REGPARAM2 CPUFUNC(op_4270_3)(uae_u32 opcode) /* CLR */
32231: {
32232: uae_u32 srcreg = (opcode & 7);
32233: OpcodeFamily = 18; CurrentInstrCycles = 18;
32234: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32235: BusCyclePenalty += 2;
32236: uae_s16 src = get_word(srca);
32237: CLEAR_CZNV;
32238: SET_ZFLG (((uae_s16)(0)) == 0);
32239: SET_NFLG (((uae_s16)(0)) < 0);
32240: put_word(srca,0);
32241: }}m68k_incpc(4);
32242: return 18;
32243: }
32244: unsigned long REGPARAM2 CPUFUNC(op_42b0_3)(uae_u32 opcode) /* CLR */
32245: {
32246: uae_u32 srcreg = (opcode & 7);
32247: OpcodeFamily = 18; CurrentInstrCycles = 26;
32248: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32249: BusCyclePenalty += 2;
32250: uae_s32 src = get_long(srca);
32251: CLEAR_CZNV;
32252: SET_ZFLG (((uae_s32)(0)) == 0);
32253: SET_NFLG (((uae_s32)(0)) < 0);
32254: put_long(srca,0);
32255: }}m68k_incpc(4);
32256: return 26;
32257: }
32258: unsigned long REGPARAM2 CPUFUNC(op_42f0_3)(uae_u32 opcode) /* MVSR2 */
32259: {
32260: uae_u32 srcreg = (opcode & 7);
32261: OpcodeFamily = 32; CurrentInstrCycles = 18;
32262: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32263: BusCyclePenalty += 2;
32264: MakeSR();
32265: put_word(srca,regs.sr & 0xff);
32266: }}m68k_incpc(4);
32267: return 18;
32268: }
32269: unsigned long REGPARAM2 CPUFUNC(op_4430_3)(uae_u32 opcode) /* NEG */
32270: {
32271: uae_u32 srcreg = (opcode & 7);
32272: OpcodeFamily = 15; CurrentInstrCycles = 18;
32273: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32274: BusCyclePenalty += 2;
32275: { uae_s8 src = get_byte(srca);
32276: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
32277: { int flgs = ((uae_s8)(src)) < 0;
32278: int flgo = ((uae_s8)(0)) < 0;
32279: int flgn = ((uae_s8)(dst)) < 0;
32280: SET_ZFLG (((uae_s8)(dst)) == 0);
32281: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
32282: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
32283: COPY_CARRY;
32284: SET_NFLG (flgn != 0);
32285: put_byte(srca,dst);
32286: }}}}}}m68k_incpc(4);
32287: return 18;
32288: }
32289: unsigned long REGPARAM2 CPUFUNC(op_4470_3)(uae_u32 opcode) /* NEG */
32290: {
32291: uae_u32 srcreg = (opcode & 7);
32292: OpcodeFamily = 15; CurrentInstrCycles = 18;
32293: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32294: BusCyclePenalty += 2;
32295: { uae_s16 src = get_word(srca);
32296: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
32297: { int flgs = ((uae_s16)(src)) < 0;
32298: int flgo = ((uae_s16)(0)) < 0;
32299: int flgn = ((uae_s16)(dst)) < 0;
32300: SET_ZFLG (((uae_s16)(dst)) == 0);
32301: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
32302: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
32303: COPY_CARRY;
32304: SET_NFLG (flgn != 0);
32305: put_word(srca,dst);
32306: }}}}}}m68k_incpc(4);
32307: return 18;
32308: }
32309: unsigned long REGPARAM2 CPUFUNC(op_44b0_3)(uae_u32 opcode) /* NEG */
32310: {
32311: uae_u32 srcreg = (opcode & 7);
32312: OpcodeFamily = 15; CurrentInstrCycles = 26;
32313: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32314: BusCyclePenalty += 2;
32315: { uae_s32 src = get_long(srca);
32316: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
32317: { int flgs = ((uae_s32)(src)) < 0;
32318: int flgo = ((uae_s32)(0)) < 0;
32319: int flgn = ((uae_s32)(dst)) < 0;
32320: SET_ZFLG (((uae_s32)(dst)) == 0);
32321: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
32322: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
32323: COPY_CARRY;
32324: SET_NFLG (flgn != 0);
32325: put_long(srca,dst);
32326: }}}}}}m68k_incpc(4);
32327: return 26;
32328: }
32329: unsigned long REGPARAM2 CPUFUNC(op_44f0_3)(uae_u32 opcode) /* MV2SR */
32330: {
32331: uae_u32 srcreg = (opcode & 7);
32332: OpcodeFamily = 33; CurrentInstrCycles = 22;
32333: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32334: BusCyclePenalty += 2;
32335: { uae_s16 src = get_word(srca);
32336: MakeSR();
32337: regs.sr &= 0xFF00;
32338: regs.sr |= src & 0xFF;
32339: MakeFromSR();
32340: }}}m68k_incpc(4);
32341: return 22;
32342: }
32343: unsigned long REGPARAM2 CPUFUNC(op_44fb_3)(uae_u32 opcode) /* MV2SR */
32344: {
32345: OpcodeFamily = 33; CurrentInstrCycles = 22;
32346: {{ uaecptr tmppc = m68k_getpc() + 2;
32347: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32348: BusCyclePenalty += 2;
32349: { uae_s16 src = get_word(srca);
32350: MakeSR();
32351: regs.sr &= 0xFF00;
32352: regs.sr |= src & 0xFF;
32353: MakeFromSR();
32354: }}}m68k_incpc(4);
32355: return 22;
32356: }
32357: unsigned long REGPARAM2 CPUFUNC(op_4630_3)(uae_u32 opcode) /* NOT */
32358: {
32359: uae_u32 srcreg = (opcode & 7);
32360: OpcodeFamily = 19; CurrentInstrCycles = 18;
32361: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32362: BusCyclePenalty += 2;
32363: { uae_s8 src = get_byte(srca);
32364: { uae_u32 dst = ~src;
32365: CLEAR_CZNV;
32366: SET_ZFLG (((uae_s8)(dst)) == 0);
32367: SET_NFLG (((uae_s8)(dst)) < 0);
32368: put_byte(srca,dst);
32369: }}}}m68k_incpc(4);
32370: return 18;
32371: }
32372: unsigned long REGPARAM2 CPUFUNC(op_4670_3)(uae_u32 opcode) /* NOT */
32373: {
32374: uae_u32 srcreg = (opcode & 7);
32375: OpcodeFamily = 19; CurrentInstrCycles = 18;
32376: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32377: BusCyclePenalty += 2;
32378: { uae_s16 src = get_word(srca);
32379: { uae_u32 dst = ~src;
32380: CLEAR_CZNV;
32381: SET_ZFLG (((uae_s16)(dst)) == 0);
32382: SET_NFLG (((uae_s16)(dst)) < 0);
32383: put_word(srca,dst);
32384: }}}}m68k_incpc(4);
32385: return 18;
32386: }
32387: unsigned long REGPARAM2 CPUFUNC(op_46b0_3)(uae_u32 opcode) /* NOT */
32388: {
32389: uae_u32 srcreg = (opcode & 7);
32390: OpcodeFamily = 19; CurrentInstrCycles = 26;
32391: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32392: BusCyclePenalty += 2;
32393: { uae_s32 src = get_long(srca);
32394: { uae_u32 dst = ~src;
32395: CLEAR_CZNV;
32396: SET_ZFLG (((uae_s32)(dst)) == 0);
32397: SET_NFLG (((uae_s32)(dst)) < 0);
32398: put_long(srca,dst);
32399: }}}}m68k_incpc(4);
32400: return 26;
32401: }
32402: unsigned long REGPARAM2 CPUFUNC(op_46f0_3)(uae_u32 opcode) /* MV2SR */
32403: {
32404: uae_u32 srcreg = (opcode & 7);
32405: OpcodeFamily = 33; CurrentInstrCycles = 22;
32406: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2014; }
32407: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32408: BusCyclePenalty += 2;
32409: { uae_s16 src = get_word(srca);
32410: regs.sr = src;
32411: MakeFromSR();
32412: }}}}m68k_incpc(4);
32413: endlabel2014: ;
32414: return 22;
32415: }
32416: unsigned long REGPARAM2 CPUFUNC(op_46fb_3)(uae_u32 opcode) /* MV2SR */
32417: {
32418: OpcodeFamily = 33; CurrentInstrCycles = 22;
32419: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2015; }
32420: {{ uaecptr tmppc = m68k_getpc() + 2;
32421: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32422: BusCyclePenalty += 2;
32423: { uae_s16 src = get_word(srca);
32424: regs.sr = src;
32425: MakeFromSR();
32426: }}}}m68k_incpc(4);
32427: endlabel2015: ;
32428: return 22;
32429: }
32430: unsigned long REGPARAM2 CPUFUNC(op_4830_3)(uae_u32 opcode) /* NBCD */
32431: {
32432: uae_u32 srcreg = (opcode & 7);
32433: OpcodeFamily = 17; CurrentInstrCycles = 18;
32434: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32435: BusCyclePenalty += 2;
32436: { uae_s8 src = get_byte(srca);
32437: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
32438: uae_u16 newv_hi = - (src & 0xF0);
32439: uae_u16 newv;
32440: int cflg;
32441: if (newv_lo > 9) { newv_lo -= 6; }
32442: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
32443: if (cflg) newv -= 0x60;
32444: SET_CFLG (cflg);
32445: COPY_CARRY;
32446: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
32447: SET_NFLG (((uae_s8)(newv)) < 0);
32448: put_byte(srca,newv);
32449: }}}}m68k_incpc(4);
32450: return 18;
32451: }
32452: unsigned long REGPARAM2 CPUFUNC(op_4870_3)(uae_u32 opcode) /* PEA */
32453: {
32454: uae_u32 srcreg = (opcode & 7);
32455: OpcodeFamily = 57; CurrentInstrCycles = 22;
32456: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32457: BusCyclePenalty += 2;
32458: { uaecptr dsta = m68k_areg(regs, 7) - 4;
32459: m68k_areg (regs, 7) = dsta;
32460: put_long(dsta,srca);
32461: }}}m68k_incpc(4);
32462: return 22;
32463: }
32464: unsigned long REGPARAM2 CPUFUNC(op_487b_3)(uae_u32 opcode) /* PEA */
32465: {
32466: OpcodeFamily = 57; CurrentInstrCycles = 22;
32467: {{ uaecptr tmppc = m68k_getpc() + 2;
32468: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32469: BusCyclePenalty += 2;
32470: { uaecptr dsta = m68k_areg(regs, 7) - 4;
32471: m68k_areg (regs, 7) = dsta;
32472: put_long(dsta,srca);
32473: }}}m68k_incpc(4);
32474: return 22;
32475: }
32476: unsigned long REGPARAM2 CPUFUNC(op_48b0_3)(uae_u32 opcode) /* MVMLE */
32477: {
32478: uae_u32 dstreg = opcode & 7;
32479: unsigned int retcycles = 0;
32480: OpcodeFamily = 38; CurrentInstrCycles = 14;
32481: { uae_u16 mask = get_iword(2);
32482: retcycles = 0;
32483: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
32484: BusCyclePenalty += 2;
32485: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
32486: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
32487: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
32488: }}}m68k_incpc(6);
32489: return (14+retcycles);
32490: }
32491: unsigned long REGPARAM2 CPUFUNC(op_48f0_3)(uae_u32 opcode) /* MVMLE */
32492: {
32493: uae_u32 dstreg = opcode & 7;
32494: unsigned int retcycles = 0;
32495: OpcodeFamily = 38; CurrentInstrCycles = 14;
32496: { uae_u16 mask = get_iword(2);
32497: retcycles = 0;
32498: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
32499: BusCyclePenalty += 2;
32500: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
32501: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
32502: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
32503: }}}m68k_incpc(6);
32504: return (14+retcycles);
32505: }
32506: unsigned long REGPARAM2 CPUFUNC(op_4a30_3)(uae_u32 opcode) /* TST */
32507: {
32508: uae_u32 srcreg = (opcode & 7);
32509: OpcodeFamily = 20; CurrentInstrCycles = 14;
32510: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32511: BusCyclePenalty += 2;
32512: { uae_s8 src = get_byte(srca);
32513: CLEAR_CZNV;
32514: SET_ZFLG (((uae_s8)(src)) == 0);
32515: SET_NFLG (((uae_s8)(src)) < 0);
32516: }}}m68k_incpc(4);
32517: return 14;
32518: }
32519: unsigned long REGPARAM2 CPUFUNC(op_4a3b_3)(uae_u32 opcode) /* TST */
32520: {
32521: OpcodeFamily = 20; CurrentInstrCycles = 14;
32522: {{ uaecptr tmppc = m68k_getpc() + 2;
32523: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32524: BusCyclePenalty += 2;
32525: { uae_s8 src = get_byte(srca);
32526: CLEAR_CZNV;
32527: SET_ZFLG (((uae_s8)(src)) == 0);
32528: SET_NFLG (((uae_s8)(src)) < 0);
32529: }}}m68k_incpc(4);
32530: return 14;
32531: }
32532: unsigned long REGPARAM2 CPUFUNC(op_4a70_3)(uae_u32 opcode) /* TST */
32533: {
32534: uae_u32 srcreg = (opcode & 7);
32535: OpcodeFamily = 20; CurrentInstrCycles = 14;
32536: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32537: BusCyclePenalty += 2;
32538: { uae_s16 src = get_word(srca);
32539: CLEAR_CZNV;
32540: SET_ZFLG (((uae_s16)(src)) == 0);
32541: SET_NFLG (((uae_s16)(src)) < 0);
32542: }}}m68k_incpc(4);
32543: return 14;
32544: }
32545: unsigned long REGPARAM2 CPUFUNC(op_4a7b_3)(uae_u32 opcode) /* TST */
32546: {
32547: OpcodeFamily = 20; CurrentInstrCycles = 14;
32548: {{ uaecptr tmppc = m68k_getpc() + 2;
32549: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32550: BusCyclePenalty += 2;
32551: { uae_s16 src = get_word(srca);
32552: CLEAR_CZNV;
32553: SET_ZFLG (((uae_s16)(src)) == 0);
32554: SET_NFLG (((uae_s16)(src)) < 0);
32555: }}}m68k_incpc(4);
32556: return 14;
32557: }
32558: unsigned long REGPARAM2 CPUFUNC(op_4ab0_3)(uae_u32 opcode) /* TST */
32559: {
32560: uae_u32 srcreg = (opcode & 7);
32561: OpcodeFamily = 20; CurrentInstrCycles = 18;
32562: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32563: BusCyclePenalty += 2;
32564: { uae_s32 src = get_long(srca);
32565: CLEAR_CZNV;
32566: SET_ZFLG (((uae_s32)(src)) == 0);
32567: SET_NFLG (((uae_s32)(src)) < 0);
32568: }}}m68k_incpc(4);
32569: return 18;
32570: }
32571: unsigned long REGPARAM2 CPUFUNC(op_4abb_3)(uae_u32 opcode) /* TST */
32572: {
32573: OpcodeFamily = 20; CurrentInstrCycles = 18;
32574: {{ uaecptr tmppc = m68k_getpc() + 2;
32575: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32576: BusCyclePenalty += 2;
32577: { uae_s32 src = get_long(srca);
32578: CLEAR_CZNV;
32579: SET_ZFLG (((uae_s32)(src)) == 0);
32580: SET_NFLG (((uae_s32)(src)) < 0);
32581: }}}m68k_incpc(4);
32582: return 18;
32583: }
32584: unsigned long REGPARAM2 CPUFUNC(op_4af0_3)(uae_u32 opcode) /* TAS */
32585: {
32586: uae_u32 srcreg = (opcode & 7);
32587: OpcodeFamily = 98; CurrentInstrCycles = 20;
32588: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32589: BusCyclePenalty += 2;
32590: { uae_s8 src = get_byte(srca);
32591: CLEAR_CZNV;
32592: SET_ZFLG (((uae_s8)(src)) == 0);
32593: SET_NFLG (((uae_s8)(src)) < 0);
32594: src |= 0x80;
32595: put_byte(srca,src);
32596: }}}m68k_incpc(4);
32597: return 20;
32598: }
32599: unsigned long REGPARAM2 CPUFUNC(op_4cb0_3)(uae_u32 opcode) /* MVMEL */
32600: {
32601: uae_u32 dstreg = opcode & 7;
32602: unsigned int retcycles = 0;
32603: OpcodeFamily = 37; CurrentInstrCycles = 18;
32604: { uae_u16 mask = get_iword(2);
32605: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
32606: retcycles = 0;
32607: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
32608: BusCyclePenalty += 2;
32609: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
32610: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
32611: }}}m68k_incpc(6);
32612: return (18+retcycles);
32613: }
32614: unsigned long REGPARAM2 CPUFUNC(op_4cbb_3)(uae_u32 opcode) /* MVMEL */
32615: {
32616: uae_u32 dstreg = 3;
32617: unsigned int retcycles = 0;
32618: OpcodeFamily = 37; CurrentInstrCycles = 18;
32619: { uae_u16 mask = get_iword(2);
32620: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
32621: retcycles = 0;
32622: { uaecptr tmppc = m68k_getpc() + 4;
32623: uaecptr srca = get_disp_ea_000(tmppc, get_iword(4));
32624: BusCyclePenalty += 2;
32625: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
32626: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
32627: }}}m68k_incpc(6);
32628: return (18+retcycles);
32629: }
32630: unsigned long REGPARAM2 CPUFUNC(op_4cf0_3)(uae_u32 opcode) /* MVMEL */
32631: {
32632: uae_u32 dstreg = opcode & 7;
32633: unsigned int retcycles = 0;
32634: OpcodeFamily = 37; CurrentInstrCycles = 18;
32635: { uae_u16 mask = get_iword(2);
32636: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
32637: retcycles = 0;
32638: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
32639: BusCyclePenalty += 2;
32640: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
32641: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
32642: }}}m68k_incpc(6);
32643: return (18+retcycles);
32644: }
32645: unsigned long REGPARAM2 CPUFUNC(op_4cfb_3)(uae_u32 opcode) /* MVMEL */
32646: {
32647: uae_u32 dstreg = 3;
32648: unsigned int retcycles = 0;
32649: OpcodeFamily = 37; CurrentInstrCycles = 18;
32650: { uae_u16 mask = get_iword(2);
32651: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
32652: retcycles = 0;
32653: { uaecptr tmppc = m68k_getpc() + 4;
32654: uaecptr srca = get_disp_ea_000(tmppc, get_iword(4));
32655: BusCyclePenalty += 2;
32656: { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
32657: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
32658: }}}m68k_incpc(6);
32659: return (18+retcycles);
32660: }
32661: unsigned long REGPARAM2 CPUFUNC(op_4eb0_3)(uae_u32 opcode) /* JSR */
32662: {
32663: uae_u32 srcreg = (opcode & 7);
32664: OpcodeFamily = 52; CurrentInstrCycles = 22;
32665: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32666: BusCyclePenalty += 2;
32667: m68k_do_jsr(m68k_getpc() + 4, srca);
32668: }}return 22;
32669: }
32670: unsigned long REGPARAM2 CPUFUNC(op_4ebb_3)(uae_u32 opcode) /* JSR */
32671: {
32672: OpcodeFamily = 52; CurrentInstrCycles = 22;
32673: {{ uaecptr tmppc = m68k_getpc() + 2;
32674: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32675: BusCyclePenalty += 2;
32676: m68k_do_jsr(m68k_getpc() + 4, srca);
32677: }}return 22;
32678: }
32679: unsigned long REGPARAM2 CPUFUNC(op_4ef0_3)(uae_u32 opcode) /* JMP */
32680: {
32681: uae_u32 srcreg = (opcode & 7);
32682: OpcodeFamily = 53; CurrentInstrCycles = 14;
32683: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32684: BusCyclePenalty += 2;
32685: m68k_setpc(srca);
32686: }}return 14;
32687: }
32688: unsigned long REGPARAM2 CPUFUNC(op_4efb_3)(uae_u32 opcode) /* JMP */
32689: {
32690: OpcodeFamily = 53; CurrentInstrCycles = 14;
32691: {{ uaecptr tmppc = m68k_getpc() + 2;
32692: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
32693: BusCyclePenalty += 2;
32694: m68k_setpc(srca);
32695: }}return 14;
32696: }
32697: #endif
32698:
32699: #ifdef PART_5
32700: unsigned long REGPARAM2 CPUFUNC(op_5030_3)(uae_u32 opcode) /* ADD */
32701: {
32702: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
32703: uae_u32 dstreg = opcode & 7;
32704: OpcodeFamily = 11; CurrentInstrCycles = 18;
32705: {{ uae_u32 src = srcreg;
32706: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
32707: BusCyclePenalty += 2;
32708: { uae_s8 dst = get_byte(dsta);
32709: { refill_prefetch (m68k_getpc(), 2);
32710: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
32711: { int flgs = ((uae_s8)(src)) < 0;
32712: int flgo = ((uae_s8)(dst)) < 0;
32713: int flgn = ((uae_s8)(newv)) < 0;
32714: SET_ZFLG (((uae_s8)(newv)) == 0);
32715: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
32716: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
32717: COPY_CARRY;
32718: SET_NFLG (flgn != 0);
32719: put_byte(dsta,newv);
32720: }}}}}}}m68k_incpc(4);
32721: return 18;
32722: }
32723: unsigned long REGPARAM2 CPUFUNC(op_5070_3)(uae_u32 opcode) /* ADD */
32724: {
32725: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
32726: uae_u32 dstreg = opcode & 7;
32727: OpcodeFamily = 11; CurrentInstrCycles = 18;
32728: {{ uae_u32 src = srcreg;
32729: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
32730: BusCyclePenalty += 2;
32731: { uae_s16 dst = get_word(dsta);
32732: { refill_prefetch (m68k_getpc(), 2);
32733: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
32734: { int flgs = ((uae_s16)(src)) < 0;
32735: int flgo = ((uae_s16)(dst)) < 0;
32736: int flgn = ((uae_s16)(newv)) < 0;
32737: SET_ZFLG (((uae_s16)(newv)) == 0);
32738: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
32739: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
32740: COPY_CARRY;
32741: SET_NFLG (flgn != 0);
32742: put_word(dsta,newv);
32743: }}}}}}}m68k_incpc(4);
32744: return 18;
32745: }
32746: unsigned long REGPARAM2 CPUFUNC(op_50b0_3)(uae_u32 opcode) /* ADD */
32747: {
32748: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
32749: uae_u32 dstreg = opcode & 7;
32750: OpcodeFamily = 11; CurrentInstrCycles = 26;
32751: {{ uae_u32 src = srcreg;
32752: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
32753: BusCyclePenalty += 2;
32754: { uae_s32 dst = get_long(dsta);
32755: { refill_prefetch (m68k_getpc(), 2);
32756: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
32757: { int flgs = ((uae_s32)(src)) < 0;
32758: int flgo = ((uae_s32)(dst)) < 0;
32759: int flgn = ((uae_s32)(newv)) < 0;
32760: SET_ZFLG (((uae_s32)(newv)) == 0);
32761: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
32762: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
32763: COPY_CARRY;
32764: SET_NFLG (flgn != 0);
32765: put_long(dsta,newv);
32766: }}}}}}}m68k_incpc(4);
32767: return 26;
32768: }
32769: unsigned long REGPARAM2 CPUFUNC(op_50f0_3)(uae_u32 opcode) /* Scc */
32770: {
32771: uae_u32 srcreg = (opcode & 7);
32772: OpcodeFamily = 59; CurrentInstrCycles = 18;
32773: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32774: BusCyclePenalty += 2;
32775: { int val = cctrue(0) ? 0xff : 0;
32776: put_byte(srca,val);
32777: }}}m68k_incpc(4);
32778: return 18;
32779: }
32780: unsigned long REGPARAM2 CPUFUNC(op_5130_3)(uae_u32 opcode) /* SUB */
32781: {
32782: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
32783: uae_u32 dstreg = opcode & 7;
32784: OpcodeFamily = 7; CurrentInstrCycles = 18;
32785: {{ uae_u32 src = srcreg;
32786: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
32787: BusCyclePenalty += 2;
32788: { uae_s8 dst = get_byte(dsta);
32789: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
32790: { int flgs = ((uae_s8)(src)) < 0;
32791: int flgo = ((uae_s8)(dst)) < 0;
32792: int flgn = ((uae_s8)(newv)) < 0;
32793: SET_ZFLG (((uae_s8)(newv)) == 0);
32794: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
32795: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
32796: COPY_CARRY;
32797: SET_NFLG (flgn != 0);
32798: put_byte(dsta,newv);
32799: }}}}}}}m68k_incpc(4);
32800: return 18;
32801: }
32802: unsigned long REGPARAM2 CPUFUNC(op_5170_3)(uae_u32 opcode) /* SUB */
32803: {
32804: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
32805: uae_u32 dstreg = opcode & 7;
32806: OpcodeFamily = 7; CurrentInstrCycles = 18;
32807: {{ uae_u32 src = srcreg;
32808: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
32809: BusCyclePenalty += 2;
32810: { uae_s16 dst = get_word(dsta);
32811: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
32812: { int flgs = ((uae_s16)(src)) < 0;
32813: int flgo = ((uae_s16)(dst)) < 0;
32814: int flgn = ((uae_s16)(newv)) < 0;
32815: SET_ZFLG (((uae_s16)(newv)) == 0);
32816: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
32817: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
32818: COPY_CARRY;
32819: SET_NFLG (flgn != 0);
32820: put_word(dsta,newv);
32821: }}}}}}}m68k_incpc(4);
32822: return 18;
32823: }
32824: unsigned long REGPARAM2 CPUFUNC(op_51b0_3)(uae_u32 opcode) /* SUB */
32825: {
32826: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
32827: uae_u32 dstreg = opcode & 7;
32828: OpcodeFamily = 7; CurrentInstrCycles = 26;
32829: {{ uae_u32 src = srcreg;
32830: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
32831: BusCyclePenalty += 2;
32832: { uae_s32 dst = get_long(dsta);
32833: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
32834: { int flgs = ((uae_s32)(src)) < 0;
32835: int flgo = ((uae_s32)(dst)) < 0;
32836: int flgn = ((uae_s32)(newv)) < 0;
32837: SET_ZFLG (((uae_s32)(newv)) == 0);
32838: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
32839: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
32840: COPY_CARRY;
32841: SET_NFLG (flgn != 0);
32842: put_long(dsta,newv);
32843: }}}}}}}m68k_incpc(4);
32844: return 26;
32845: }
32846: unsigned long REGPARAM2 CPUFUNC(op_51f0_3)(uae_u32 opcode) /* Scc */
32847: {
32848: uae_u32 srcreg = (opcode & 7);
32849: OpcodeFamily = 59; CurrentInstrCycles = 18;
32850: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32851: BusCyclePenalty += 2;
32852: { int val = cctrue(1) ? 0xff : 0;
32853: put_byte(srca,val);
32854: }}}m68k_incpc(4);
32855: return 18;
32856: }
32857: unsigned long REGPARAM2 CPUFUNC(op_52f0_3)(uae_u32 opcode) /* Scc */
32858: {
32859: uae_u32 srcreg = (opcode & 7);
32860: OpcodeFamily = 59; CurrentInstrCycles = 18;
32861: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32862: BusCyclePenalty += 2;
32863: { int val = cctrue(2) ? 0xff : 0;
32864: put_byte(srca,val);
32865: }}}m68k_incpc(4);
32866: return 18;
32867: }
32868: unsigned long REGPARAM2 CPUFUNC(op_53f0_3)(uae_u32 opcode) /* Scc */
32869: {
32870: uae_u32 srcreg = (opcode & 7);
32871: OpcodeFamily = 59; CurrentInstrCycles = 18;
32872: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32873: BusCyclePenalty += 2;
32874: { int val = cctrue(3) ? 0xff : 0;
32875: put_byte(srca,val);
32876: }}}m68k_incpc(4);
32877: return 18;
32878: }
32879: unsigned long REGPARAM2 CPUFUNC(op_54f0_3)(uae_u32 opcode) /* Scc */
32880: {
32881: uae_u32 srcreg = (opcode & 7);
32882: OpcodeFamily = 59; CurrentInstrCycles = 18;
32883: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32884: BusCyclePenalty += 2;
32885: { int val = cctrue(4) ? 0xff : 0;
32886: put_byte(srca,val);
32887: }}}m68k_incpc(4);
32888: return 18;
32889: }
32890: unsigned long REGPARAM2 CPUFUNC(op_55f0_3)(uae_u32 opcode) /* Scc */
32891: {
32892: uae_u32 srcreg = (opcode & 7);
32893: OpcodeFamily = 59; CurrentInstrCycles = 18;
32894: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32895: BusCyclePenalty += 2;
32896: { int val = cctrue(5) ? 0xff : 0;
32897: put_byte(srca,val);
32898: }}}m68k_incpc(4);
32899: return 18;
32900: }
32901: unsigned long REGPARAM2 CPUFUNC(op_56f0_3)(uae_u32 opcode) /* Scc */
32902: {
32903: uae_u32 srcreg = (opcode & 7);
32904: OpcodeFamily = 59; CurrentInstrCycles = 18;
32905: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32906: BusCyclePenalty += 2;
32907: { int val = cctrue(6) ? 0xff : 0;
32908: put_byte(srca,val);
32909: }}}m68k_incpc(4);
32910: return 18;
32911: }
32912: unsigned long REGPARAM2 CPUFUNC(op_57f0_3)(uae_u32 opcode) /* Scc */
32913: {
32914: uae_u32 srcreg = (opcode & 7);
32915: OpcodeFamily = 59; CurrentInstrCycles = 18;
32916: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32917: BusCyclePenalty += 2;
32918: { int val = cctrue(7) ? 0xff : 0;
32919: put_byte(srca,val);
32920: }}}m68k_incpc(4);
32921: return 18;
32922: }
32923: unsigned long REGPARAM2 CPUFUNC(op_58f0_3)(uae_u32 opcode) /* Scc */
32924: {
32925: uae_u32 srcreg = (opcode & 7);
32926: OpcodeFamily = 59; CurrentInstrCycles = 18;
32927: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32928: BusCyclePenalty += 2;
32929: { int val = cctrue(8) ? 0xff : 0;
32930: put_byte(srca,val);
32931: }}}m68k_incpc(4);
32932: return 18;
32933: }
32934: unsigned long REGPARAM2 CPUFUNC(op_59f0_3)(uae_u32 opcode) /* Scc */
32935: {
32936: uae_u32 srcreg = (opcode & 7);
32937: OpcodeFamily = 59; CurrentInstrCycles = 18;
32938: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32939: BusCyclePenalty += 2;
32940: { int val = cctrue(9) ? 0xff : 0;
32941: put_byte(srca,val);
32942: }}}m68k_incpc(4);
32943: return 18;
32944: }
32945: unsigned long REGPARAM2 CPUFUNC(op_5af0_3)(uae_u32 opcode) /* Scc */
32946: {
32947: uae_u32 srcreg = (opcode & 7);
32948: OpcodeFamily = 59; CurrentInstrCycles = 18;
32949: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32950: BusCyclePenalty += 2;
32951: { int val = cctrue(10) ? 0xff : 0;
32952: put_byte(srca,val);
32953: }}}m68k_incpc(4);
32954: return 18;
32955: }
32956: unsigned long REGPARAM2 CPUFUNC(op_5bf0_3)(uae_u32 opcode) /* Scc */
32957: {
32958: uae_u32 srcreg = (opcode & 7);
32959: OpcodeFamily = 59; CurrentInstrCycles = 18;
32960: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32961: BusCyclePenalty += 2;
32962: { int val = cctrue(11) ? 0xff : 0;
32963: put_byte(srca,val);
32964: }}}m68k_incpc(4);
32965: return 18;
32966: }
32967: unsigned long REGPARAM2 CPUFUNC(op_5cf0_3)(uae_u32 opcode) /* Scc */
32968: {
32969: uae_u32 srcreg = (opcode & 7);
32970: OpcodeFamily = 59; CurrentInstrCycles = 18;
32971: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32972: BusCyclePenalty += 2;
32973: { int val = cctrue(12) ? 0xff : 0;
32974: put_byte(srca,val);
32975: }}}m68k_incpc(4);
32976: return 18;
32977: }
32978: unsigned long REGPARAM2 CPUFUNC(op_5df0_3)(uae_u32 opcode) /* Scc */
32979: {
32980: uae_u32 srcreg = (opcode & 7);
32981: OpcodeFamily = 59; CurrentInstrCycles = 18;
32982: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32983: BusCyclePenalty += 2;
32984: { int val = cctrue(13) ? 0xff : 0;
32985: put_byte(srca,val);
32986: }}}m68k_incpc(4);
32987: return 18;
32988: }
32989: unsigned long REGPARAM2 CPUFUNC(op_5ef0_3)(uae_u32 opcode) /* Scc */
32990: {
32991: uae_u32 srcreg = (opcode & 7);
32992: OpcodeFamily = 59; CurrentInstrCycles = 18;
32993: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
32994: BusCyclePenalty += 2;
32995: { int val = cctrue(14) ? 0xff : 0;
32996: put_byte(srca,val);
32997: }}}m68k_incpc(4);
32998: return 18;
32999: }
33000: #endif
33001:
33002: #ifdef PART_6
33003: unsigned long REGPARAM2 CPUFUNC(op_5ff0_3)(uae_u32 opcode) /* Scc */
33004: {
33005: uae_u32 srcreg = (opcode & 7);
33006: OpcodeFamily = 59; CurrentInstrCycles = 18;
33007: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33008: BusCyclePenalty += 2;
33009: { int val = cctrue(15) ? 0xff : 0;
33010: put_byte(srca,val);
33011: }}}m68k_incpc(4);
33012: return 18;
33013: }
33014: unsigned long REGPARAM2 CPUFUNC(op_60ff_3)(uae_u32 opcode) /* Bcc */
33015: {
33016: OpcodeFamily = 55; CurrentInstrCycles = 12;
33017: { m68k_incpc(2);
33018: if (!cctrue(0)) goto endlabel2058;
33019: last_addr_for_exception_3 = m68k_getpc() + 2;
33020: last_fault_for_exception_3 = m68k_getpc() + 1;
33021: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2058;
33022: { uae_s32 src = get_ilong(2);
33023: if (!cctrue(0)) goto didnt_jump;
33024: m68k_incpc ((uae_s32)src + 2);
33025: return 10;
33026: didnt_jump:;
33027: }}m68k_incpc(6);
33028: endlabel2058: ;
33029: return 12;
33030: }
33031: unsigned long REGPARAM2 CPUFUNC(op_62ff_3)(uae_u32 opcode) /* Bcc */
33032: {
33033: OpcodeFamily = 55; CurrentInstrCycles = 12;
33034: { m68k_incpc(2);
33035: if (!cctrue(2)) goto endlabel2059;
33036: last_addr_for_exception_3 = m68k_getpc() + 2;
33037: last_fault_for_exception_3 = m68k_getpc() + 1;
33038: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2059;
33039: { uae_s32 src = get_ilong(2);
33040: if (!cctrue(2)) goto didnt_jump;
33041: m68k_incpc ((uae_s32)src + 2);
33042: return 10;
33043: didnt_jump:;
33044: }}m68k_incpc(6);
33045: endlabel2059: ;
33046: return 12;
33047: }
33048: unsigned long REGPARAM2 CPUFUNC(op_63ff_3)(uae_u32 opcode) /* Bcc */
33049: {
33050: OpcodeFamily = 55; CurrentInstrCycles = 12;
33051: { m68k_incpc(2);
33052: if (!cctrue(3)) goto endlabel2060;
33053: last_addr_for_exception_3 = m68k_getpc() + 2;
33054: last_fault_for_exception_3 = m68k_getpc() + 1;
33055: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2060;
33056: { uae_s32 src = get_ilong(2);
33057: if (!cctrue(3)) goto didnt_jump;
33058: m68k_incpc ((uae_s32)src + 2);
33059: return 10;
33060: didnt_jump:;
33061: }}m68k_incpc(6);
33062: endlabel2060: ;
33063: return 12;
33064: }
33065: unsigned long REGPARAM2 CPUFUNC(op_64ff_3)(uae_u32 opcode) /* Bcc */
33066: {
33067: OpcodeFamily = 55; CurrentInstrCycles = 12;
33068: { m68k_incpc(2);
33069: if (!cctrue(4)) goto endlabel2061;
33070: last_addr_for_exception_3 = m68k_getpc() + 2;
33071: last_fault_for_exception_3 = m68k_getpc() + 1;
33072: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2061;
33073: { uae_s32 src = get_ilong(2);
33074: if (!cctrue(4)) goto didnt_jump;
33075: m68k_incpc ((uae_s32)src + 2);
33076: return 10;
33077: didnt_jump:;
33078: }}m68k_incpc(6);
33079: endlabel2061: ;
33080: return 12;
33081: }
33082: unsigned long REGPARAM2 CPUFUNC(op_65ff_3)(uae_u32 opcode) /* Bcc */
33083: {
33084: OpcodeFamily = 55; CurrentInstrCycles = 12;
33085: { m68k_incpc(2);
33086: if (!cctrue(5)) goto endlabel2062;
33087: last_addr_for_exception_3 = m68k_getpc() + 2;
33088: last_fault_for_exception_3 = m68k_getpc() + 1;
33089: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2062;
33090: { uae_s32 src = get_ilong(2);
33091: if (!cctrue(5)) goto didnt_jump;
33092: m68k_incpc ((uae_s32)src + 2);
33093: return 10;
33094: didnt_jump:;
33095: }}m68k_incpc(6);
33096: endlabel2062: ;
33097: return 12;
33098: }
33099: unsigned long REGPARAM2 CPUFUNC(op_66ff_3)(uae_u32 opcode) /* Bcc */
33100: {
33101: OpcodeFamily = 55; CurrentInstrCycles = 12;
33102: { m68k_incpc(2);
33103: if (!cctrue(6)) goto endlabel2063;
33104: last_addr_for_exception_3 = m68k_getpc() + 2;
33105: last_fault_for_exception_3 = m68k_getpc() + 1;
33106: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2063;
33107: { uae_s32 src = get_ilong(2);
33108: if (!cctrue(6)) goto didnt_jump;
33109: m68k_incpc ((uae_s32)src + 2);
33110: return 10;
33111: didnt_jump:;
33112: }}m68k_incpc(6);
33113: endlabel2063: ;
33114: return 12;
33115: }
33116: unsigned long REGPARAM2 CPUFUNC(op_67ff_3)(uae_u32 opcode) /* Bcc */
33117: {
33118: OpcodeFamily = 55; CurrentInstrCycles = 12;
33119: { m68k_incpc(2);
33120: if (!cctrue(7)) goto endlabel2064;
33121: last_addr_for_exception_3 = m68k_getpc() + 2;
33122: last_fault_for_exception_3 = m68k_getpc() + 1;
33123: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2064;
33124: { uae_s32 src = get_ilong(2);
33125: if (!cctrue(7)) goto didnt_jump;
33126: m68k_incpc ((uae_s32)src + 2);
33127: return 10;
33128: didnt_jump:;
33129: }}m68k_incpc(6);
33130: endlabel2064: ;
33131: return 12;
33132: }
33133: unsigned long REGPARAM2 CPUFUNC(op_68ff_3)(uae_u32 opcode) /* Bcc */
33134: {
33135: OpcodeFamily = 55; CurrentInstrCycles = 12;
33136: { m68k_incpc(2);
33137: if (!cctrue(8)) goto endlabel2065;
33138: last_addr_for_exception_3 = m68k_getpc() + 2;
33139: last_fault_for_exception_3 = m68k_getpc() + 1;
33140: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2065;
33141: { uae_s32 src = get_ilong(2);
33142: if (!cctrue(8)) goto didnt_jump;
33143: m68k_incpc ((uae_s32)src + 2);
33144: return 10;
33145: didnt_jump:;
33146: }}m68k_incpc(6);
33147: endlabel2065: ;
33148: return 12;
33149: }
33150: unsigned long REGPARAM2 CPUFUNC(op_69ff_3)(uae_u32 opcode) /* Bcc */
33151: {
33152: OpcodeFamily = 55; CurrentInstrCycles = 12;
33153: { m68k_incpc(2);
33154: if (!cctrue(9)) goto endlabel2066;
33155: last_addr_for_exception_3 = m68k_getpc() + 2;
33156: last_fault_for_exception_3 = m68k_getpc() + 1;
33157: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2066;
33158: { uae_s32 src = get_ilong(2);
33159: if (!cctrue(9)) goto didnt_jump;
33160: m68k_incpc ((uae_s32)src + 2);
33161: return 10;
33162: didnt_jump:;
33163: }}m68k_incpc(6);
33164: endlabel2066: ;
33165: return 12;
33166: }
33167: unsigned long REGPARAM2 CPUFUNC(op_6aff_3)(uae_u32 opcode) /* Bcc */
33168: {
33169: OpcodeFamily = 55; CurrentInstrCycles = 12;
33170: { m68k_incpc(2);
33171: if (!cctrue(10)) goto endlabel2067;
33172: last_addr_for_exception_3 = m68k_getpc() + 2;
33173: last_fault_for_exception_3 = m68k_getpc() + 1;
33174: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2067;
33175: { uae_s32 src = get_ilong(2);
33176: if (!cctrue(10)) goto didnt_jump;
33177: m68k_incpc ((uae_s32)src + 2);
33178: return 10;
33179: didnt_jump:;
33180: }}m68k_incpc(6);
33181: endlabel2067: ;
33182: return 12;
33183: }
33184: unsigned long REGPARAM2 CPUFUNC(op_6bff_3)(uae_u32 opcode) /* Bcc */
33185: {
33186: OpcodeFamily = 55; CurrentInstrCycles = 12;
33187: { m68k_incpc(2);
33188: if (!cctrue(11)) goto endlabel2068;
33189: last_addr_for_exception_3 = m68k_getpc() + 2;
33190: last_fault_for_exception_3 = m68k_getpc() + 1;
33191: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2068;
33192: { uae_s32 src = get_ilong(2);
33193: if (!cctrue(11)) goto didnt_jump;
33194: m68k_incpc ((uae_s32)src + 2);
33195: return 10;
33196: didnt_jump:;
33197: }}m68k_incpc(6);
33198: endlabel2068: ;
33199: return 12;
33200: }
33201: unsigned long REGPARAM2 CPUFUNC(op_6cff_3)(uae_u32 opcode) /* Bcc */
33202: {
33203: OpcodeFamily = 55; CurrentInstrCycles = 12;
33204: { m68k_incpc(2);
33205: if (!cctrue(12)) goto endlabel2069;
33206: last_addr_for_exception_3 = m68k_getpc() + 2;
33207: last_fault_for_exception_3 = m68k_getpc() + 1;
33208: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2069;
33209: { uae_s32 src = get_ilong(2);
33210: if (!cctrue(12)) goto didnt_jump;
33211: m68k_incpc ((uae_s32)src + 2);
33212: return 10;
33213: didnt_jump:;
33214: }}m68k_incpc(6);
33215: endlabel2069: ;
33216: return 12;
33217: }
33218: unsigned long REGPARAM2 CPUFUNC(op_6dff_3)(uae_u32 opcode) /* Bcc */
33219: {
33220: OpcodeFamily = 55; CurrentInstrCycles = 12;
33221: { m68k_incpc(2);
33222: if (!cctrue(13)) goto endlabel2070;
33223: last_addr_for_exception_3 = m68k_getpc() + 2;
33224: last_fault_for_exception_3 = m68k_getpc() + 1;
33225: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2070;
33226: { uae_s32 src = get_ilong(2);
33227: if (!cctrue(13)) goto didnt_jump;
33228: m68k_incpc ((uae_s32)src + 2);
33229: return 10;
33230: didnt_jump:;
33231: }}m68k_incpc(6);
33232: endlabel2070: ;
33233: return 12;
33234: }
33235: unsigned long REGPARAM2 CPUFUNC(op_6eff_3)(uae_u32 opcode) /* Bcc */
33236: {
33237: OpcodeFamily = 55; CurrentInstrCycles = 12;
33238: { m68k_incpc(2);
33239: if (!cctrue(14)) goto endlabel2071;
33240: last_addr_for_exception_3 = m68k_getpc() + 2;
33241: last_fault_for_exception_3 = m68k_getpc() + 1;
33242: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2071;
33243: { uae_s32 src = get_ilong(2);
33244: if (!cctrue(14)) goto didnt_jump;
33245: m68k_incpc ((uae_s32)src + 2);
33246: return 10;
33247: didnt_jump:;
33248: }}m68k_incpc(6);
33249: endlabel2071: ;
33250: return 12;
33251: }
33252: unsigned long REGPARAM2 CPUFUNC(op_6fff_3)(uae_u32 opcode) /* Bcc */
33253: {
33254: OpcodeFamily = 55; CurrentInstrCycles = 12;
33255: { m68k_incpc(2);
33256: if (!cctrue(15)) goto endlabel2072;
33257: last_addr_for_exception_3 = m68k_getpc() + 2;
33258: last_fault_for_exception_3 = m68k_getpc() + 1;
33259: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2072;
33260: { uae_s32 src = get_ilong(2);
33261: if (!cctrue(15)) goto didnt_jump;
33262: m68k_incpc ((uae_s32)src + 2);
33263: return 10;
33264: didnt_jump:;
33265: }}m68k_incpc(6);
33266: endlabel2072: ;
33267: return 12;
33268: }
33269: unsigned long REGPARAM2 CPUFUNC(op_8030_3)(uae_u32 opcode) /* OR */
33270: {
33271: uae_u32 srcreg = (opcode & 7);
33272: uae_u32 dstreg = (opcode >> 9) & 7;
33273: OpcodeFamily = 1; CurrentInstrCycles = 14;
33274: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33275: BusCyclePenalty += 2;
33276: { uae_s8 src = get_byte(srca);
33277: { uae_s8 dst = m68k_dreg(regs, dstreg);
33278: src |= dst;
33279: CLEAR_CZNV;
33280: SET_ZFLG (((uae_s8)(src)) == 0);
33281: SET_NFLG (((uae_s8)(src)) < 0);
33282: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
33283: }}}}m68k_incpc(4);
33284: return 14;
33285: }
33286: unsigned long REGPARAM2 CPUFUNC(op_803b_3)(uae_u32 opcode) /* OR */
33287: {
33288: uae_u32 dstreg = (opcode >> 9) & 7;
33289: OpcodeFamily = 1; CurrentInstrCycles = 14;
33290: {{ uaecptr tmppc = m68k_getpc() + 2;
33291: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33292: BusCyclePenalty += 2;
33293: { uae_s8 src = get_byte(srca);
33294: { uae_s8 dst = m68k_dreg(regs, dstreg);
33295: src |= dst;
33296: CLEAR_CZNV;
33297: SET_ZFLG (((uae_s8)(src)) == 0);
33298: SET_NFLG (((uae_s8)(src)) < 0);
33299: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
33300: }}}}m68k_incpc(4);
33301: return 14;
33302: }
33303: unsigned long REGPARAM2 CPUFUNC(op_8070_3)(uae_u32 opcode) /* OR */
33304: {
33305: uae_u32 srcreg = (opcode & 7);
33306: uae_u32 dstreg = (opcode >> 9) & 7;
33307: OpcodeFamily = 1; CurrentInstrCycles = 14;
33308: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33309: BusCyclePenalty += 2;
33310: { uae_s16 src = get_word(srca);
33311: { uae_s16 dst = m68k_dreg(regs, dstreg);
33312: src |= dst;
33313: CLEAR_CZNV;
33314: SET_ZFLG (((uae_s16)(src)) == 0);
33315: SET_NFLG (((uae_s16)(src)) < 0);
33316: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
33317: }}}}m68k_incpc(4);
33318: return 14;
33319: }
33320: unsigned long REGPARAM2 CPUFUNC(op_807b_3)(uae_u32 opcode) /* OR */
33321: {
33322: uae_u32 dstreg = (opcode >> 9) & 7;
33323: OpcodeFamily = 1; CurrentInstrCycles = 14;
33324: {{ uaecptr tmppc = m68k_getpc() + 2;
33325: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33326: BusCyclePenalty += 2;
33327: { uae_s16 src = get_word(srca);
33328: { uae_s16 dst = m68k_dreg(regs, dstreg);
33329: src |= dst;
33330: CLEAR_CZNV;
33331: SET_ZFLG (((uae_s16)(src)) == 0);
33332: SET_NFLG (((uae_s16)(src)) < 0);
33333: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
33334: }}}}m68k_incpc(4);
33335: return 14;
33336: }
33337: unsigned long REGPARAM2 CPUFUNC(op_80b0_3)(uae_u32 opcode) /* OR */
33338: {
33339: uae_u32 srcreg = (opcode & 7);
33340: uae_u32 dstreg = (opcode >> 9) & 7;
33341: OpcodeFamily = 1; CurrentInstrCycles = 20;
33342: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33343: BusCyclePenalty += 2;
33344: { uae_s32 src = get_long(srca);
33345: { uae_s32 dst = m68k_dreg(regs, dstreg);
33346: src |= dst;
33347: CLEAR_CZNV;
33348: SET_ZFLG (((uae_s32)(src)) == 0);
33349: SET_NFLG (((uae_s32)(src)) < 0);
33350: m68k_dreg(regs, dstreg) = (src);
33351: }}}}m68k_incpc(4);
33352: return 20;
33353: }
33354: unsigned long REGPARAM2 CPUFUNC(op_80bb_3)(uae_u32 opcode) /* OR */
33355: {
33356: uae_u32 dstreg = (opcode >> 9) & 7;
33357: OpcodeFamily = 1; CurrentInstrCycles = 20;
33358: {{ uaecptr tmppc = m68k_getpc() + 2;
33359: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33360: BusCyclePenalty += 2;
33361: { uae_s32 src = get_long(srca);
33362: { uae_s32 dst = m68k_dreg(regs, dstreg);
33363: src |= dst;
33364: CLEAR_CZNV;
33365: SET_ZFLG (((uae_s32)(src)) == 0);
33366: SET_NFLG (((uae_s32)(src)) < 0);
33367: m68k_dreg(regs, dstreg) = (src);
33368: }}}}m68k_incpc(4);
33369: return 20;
33370: }
33371: unsigned long REGPARAM2 CPUFUNC(op_80f0_3)(uae_u32 opcode) /* DIVU */
33372: {
33373: uae_u32 srcreg = (opcode & 7);
33374: uae_u32 dstreg = (opcode >> 9) & 7;
33375: unsigned int retcycles = 0;
33376: OpcodeFamily = 60; CurrentInstrCycles = 14;
33377: { uaecptr oldpc = m68k_getpc();
33378: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33379: BusCyclePenalty += 2;
33380: { uae_s16 src = get_word(srca);
33381: { uae_s32 dst = m68k_dreg(regs, dstreg);
33382: m68k_incpc(4);
33383: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2079; } else {
33384: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
33385: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
33386: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
33387: {
33388: CLEAR_CZNV;
33389: SET_ZFLG (((uae_s16)(newv)) == 0);
33390: SET_NFLG (((uae_s16)(newv)) < 0);
33391: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
33392: m68k_dreg(regs, dstreg) = (newv);
33393: }
33394: }
33395: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
33396: }}}}endlabel2079: ;
33397: return (14+retcycles);
33398: }
33399: unsigned long REGPARAM2 CPUFUNC(op_80fb_3)(uae_u32 opcode) /* DIVU */
33400: {
33401: uae_u32 dstreg = (opcode >> 9) & 7;
33402: unsigned int retcycles = 0;
33403: OpcodeFamily = 60; CurrentInstrCycles = 14;
33404: { uaecptr oldpc = m68k_getpc();
33405: { uaecptr tmppc = m68k_getpc() + 2;
33406: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33407: BusCyclePenalty += 2;
33408: { uae_s16 src = get_word(srca);
33409: { uae_s32 dst = m68k_dreg(regs, dstreg);
33410: m68k_incpc(4);
33411: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2080; } else {
33412: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
33413: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
33414: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
33415: {
33416: CLEAR_CZNV;
33417: SET_ZFLG (((uae_s16)(newv)) == 0);
33418: SET_NFLG (((uae_s16)(newv)) < 0);
33419: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
33420: m68k_dreg(regs, dstreg) = (newv);
33421: }
33422: }
33423: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
33424: }}}}endlabel2080: ;
33425: return (14+retcycles);
33426: }
33427: unsigned long REGPARAM2 CPUFUNC(op_8130_3)(uae_u32 opcode) /* OR */
33428: {
33429: uae_u32 srcreg = ((opcode >> 9) & 7);
33430: uae_u32 dstreg = opcode & 7;
33431: OpcodeFamily = 1; CurrentInstrCycles = 18;
33432: {{ uae_s8 src = m68k_dreg(regs, srcreg);
33433: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
33434: BusCyclePenalty += 2;
33435: { uae_s8 dst = get_byte(dsta);
33436: src |= dst;
33437: CLEAR_CZNV;
33438: SET_ZFLG (((uae_s8)(src)) == 0);
33439: SET_NFLG (((uae_s8)(src)) < 0);
33440: put_byte(dsta,src);
33441: }}}}m68k_incpc(4);
33442: return 18;
33443: }
33444: unsigned long REGPARAM2 CPUFUNC(op_8170_3)(uae_u32 opcode) /* OR */
33445: {
33446: uae_u32 srcreg = ((opcode >> 9) & 7);
33447: uae_u32 dstreg = opcode & 7;
33448: OpcodeFamily = 1; CurrentInstrCycles = 18;
33449: {{ uae_s16 src = m68k_dreg(regs, srcreg);
33450: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
33451: BusCyclePenalty += 2;
33452: { uae_s16 dst = get_word(dsta);
33453: src |= dst;
33454: CLEAR_CZNV;
33455: SET_ZFLG (((uae_s16)(src)) == 0);
33456: SET_NFLG (((uae_s16)(src)) < 0);
33457: put_word(dsta,src);
33458: }}}}m68k_incpc(4);
33459: return 18;
33460: }
33461: unsigned long REGPARAM2 CPUFUNC(op_81b0_3)(uae_u32 opcode) /* OR */
33462: {
33463: uae_u32 srcreg = ((opcode >> 9) & 7);
33464: uae_u32 dstreg = opcode & 7;
33465: OpcodeFamily = 1; CurrentInstrCycles = 26;
33466: {{ uae_s32 src = m68k_dreg(regs, srcreg);
33467: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
33468: BusCyclePenalty += 2;
33469: { uae_s32 dst = get_long(dsta);
33470: src |= dst;
33471: CLEAR_CZNV;
33472: SET_ZFLG (((uae_s32)(src)) == 0);
33473: SET_NFLG (((uae_s32)(src)) < 0);
33474: put_long(dsta,src);
33475: }}}}m68k_incpc(4);
33476: return 26;
33477: }
33478: unsigned long REGPARAM2 CPUFUNC(op_81f0_3)(uae_u32 opcode) /* DIVS */
33479: {
33480: uae_u32 srcreg = (opcode & 7);
33481: uae_u32 dstreg = (opcode >> 9) & 7;
33482: unsigned int retcycles = 0;
33483: OpcodeFamily = 61; CurrentInstrCycles = 14;
33484: { uaecptr oldpc = m68k_getpc();
33485: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33486: BusCyclePenalty += 2;
33487: { uae_s16 src = get_word(srca);
33488: { uae_s32 dst = m68k_dreg(regs, dstreg);
33489: m68k_incpc(4);
33490: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2084; } else {
33491: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
33492: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
33493: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
33494: {
33495: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
33496: CLEAR_CZNV;
33497: SET_ZFLG (((uae_s16)(newv)) == 0);
33498: SET_NFLG (((uae_s16)(newv)) < 0);
33499: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
33500: m68k_dreg(regs, dstreg) = (newv);
33501: }
33502: }
33503: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
33504: }}}}endlabel2084: ;
33505: return (14+retcycles);
33506: }
33507: unsigned long REGPARAM2 CPUFUNC(op_81fb_3)(uae_u32 opcode) /* DIVS */
33508: {
33509: uae_u32 dstreg = (opcode >> 9) & 7;
33510: unsigned int retcycles = 0;
33511: OpcodeFamily = 61; CurrentInstrCycles = 14;
33512: { uaecptr oldpc = m68k_getpc();
33513: { uaecptr tmppc = m68k_getpc() + 2;
33514: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33515: BusCyclePenalty += 2;
33516: { uae_s16 src = get_word(srca);
33517: { uae_s32 dst = m68k_dreg(regs, dstreg);
33518: m68k_incpc(4);
33519: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2085; } else {
33520: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
33521: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
33522: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
33523: {
33524: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
33525: CLEAR_CZNV;
33526: SET_ZFLG (((uae_s16)(newv)) == 0);
33527: SET_NFLG (((uae_s16)(newv)) < 0);
33528: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
33529: m68k_dreg(regs, dstreg) = (newv);
33530: }
33531: }
33532: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
33533: }}}}endlabel2085: ;
33534: return (14+retcycles);
33535: }
33536: unsigned long REGPARAM2 CPUFUNC(op_9030_3)(uae_u32 opcode) /* SUB */
33537: {
33538: uae_u32 srcreg = (opcode & 7);
33539: uae_u32 dstreg = (opcode >> 9) & 7;
33540: OpcodeFamily = 7; CurrentInstrCycles = 14;
33541: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33542: BusCyclePenalty += 2;
33543: { uae_s8 src = get_byte(srca);
33544: { uae_s8 dst = m68k_dreg(regs, dstreg);
33545: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
33546: { int flgs = ((uae_s8)(src)) < 0;
33547: int flgo = ((uae_s8)(dst)) < 0;
33548: int flgn = ((uae_s8)(newv)) < 0;
33549: SET_ZFLG (((uae_s8)(newv)) == 0);
33550: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
33551: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
33552: COPY_CARRY;
33553: SET_NFLG (flgn != 0);
33554: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
33555: }}}}}}}m68k_incpc(4);
33556: return 14;
33557: }
33558: unsigned long REGPARAM2 CPUFUNC(op_903b_3)(uae_u32 opcode) /* SUB */
33559: {
33560: uae_u32 dstreg = (opcode >> 9) & 7;
33561: OpcodeFamily = 7; CurrentInstrCycles = 14;
33562: {{ uaecptr tmppc = m68k_getpc() + 2;
33563: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33564: BusCyclePenalty += 2;
33565: { uae_s8 src = get_byte(srca);
33566: { uae_s8 dst = m68k_dreg(regs, dstreg);
33567: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
33568: { int flgs = ((uae_s8)(src)) < 0;
33569: int flgo = ((uae_s8)(dst)) < 0;
33570: int flgn = ((uae_s8)(newv)) < 0;
33571: SET_ZFLG (((uae_s8)(newv)) == 0);
33572: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
33573: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
33574: COPY_CARRY;
33575: SET_NFLG (flgn != 0);
33576: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
33577: }}}}}}}m68k_incpc(4);
33578: return 14;
33579: }
33580: unsigned long REGPARAM2 CPUFUNC(op_9070_3)(uae_u32 opcode) /* SUB */
33581: {
33582: uae_u32 srcreg = (opcode & 7);
33583: uae_u32 dstreg = (opcode >> 9) & 7;
33584: OpcodeFamily = 7; CurrentInstrCycles = 14;
33585: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33586: BusCyclePenalty += 2;
33587: { uae_s16 src = get_word(srca);
33588: { uae_s16 dst = m68k_dreg(regs, dstreg);
33589: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
33590: { int flgs = ((uae_s16)(src)) < 0;
33591: int flgo = ((uae_s16)(dst)) < 0;
33592: int flgn = ((uae_s16)(newv)) < 0;
33593: SET_ZFLG (((uae_s16)(newv)) == 0);
33594: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
33595: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
33596: COPY_CARRY;
33597: SET_NFLG (flgn != 0);
33598: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
33599: }}}}}}}m68k_incpc(4);
33600: return 14;
33601: }
33602: unsigned long REGPARAM2 CPUFUNC(op_907b_3)(uae_u32 opcode) /* SUB */
33603: {
33604: uae_u32 dstreg = (opcode >> 9) & 7;
33605: OpcodeFamily = 7; CurrentInstrCycles = 14;
33606: {{ uaecptr tmppc = m68k_getpc() + 2;
33607: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33608: BusCyclePenalty += 2;
33609: { uae_s16 src = get_word(srca);
33610: { uae_s16 dst = m68k_dreg(regs, dstreg);
33611: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
33612: { int flgs = ((uae_s16)(src)) < 0;
33613: int flgo = ((uae_s16)(dst)) < 0;
33614: int flgn = ((uae_s16)(newv)) < 0;
33615: SET_ZFLG (((uae_s16)(newv)) == 0);
33616: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
33617: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
33618: COPY_CARRY;
33619: SET_NFLG (flgn != 0);
33620: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
33621: }}}}}}}m68k_incpc(4);
33622: return 14;
33623: }
33624: unsigned long REGPARAM2 CPUFUNC(op_90b0_3)(uae_u32 opcode) /* SUB */
33625: {
33626: uae_u32 srcreg = (opcode & 7);
33627: uae_u32 dstreg = (opcode >> 9) & 7;
33628: OpcodeFamily = 7; CurrentInstrCycles = 20;
33629: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33630: BusCyclePenalty += 2;
33631: { uae_s32 src = get_long(srca);
33632: { uae_s32 dst = m68k_dreg(regs, dstreg);
33633: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
33634: { int flgs = ((uae_s32)(src)) < 0;
33635: int flgo = ((uae_s32)(dst)) < 0;
33636: int flgn = ((uae_s32)(newv)) < 0;
33637: SET_ZFLG (((uae_s32)(newv)) == 0);
33638: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
33639: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
33640: COPY_CARRY;
33641: SET_NFLG (flgn != 0);
33642: m68k_dreg(regs, dstreg) = (newv);
33643: }}}}}}}m68k_incpc(4);
33644: return 20;
33645: }
33646: unsigned long REGPARAM2 CPUFUNC(op_90bb_3)(uae_u32 opcode) /* SUB */
33647: {
33648: uae_u32 dstreg = (opcode >> 9) & 7;
33649: OpcodeFamily = 7; CurrentInstrCycles = 20;
33650: {{ uaecptr tmppc = m68k_getpc() + 2;
33651: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33652: BusCyclePenalty += 2;
33653: { uae_s32 src = get_long(srca);
33654: { uae_s32 dst = m68k_dreg(regs, dstreg);
33655: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
33656: { int flgs = ((uae_s32)(src)) < 0;
33657: int flgo = ((uae_s32)(dst)) < 0;
33658: int flgn = ((uae_s32)(newv)) < 0;
33659: SET_ZFLG (((uae_s32)(newv)) == 0);
33660: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
33661: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
33662: COPY_CARRY;
33663: SET_NFLG (flgn != 0);
33664: m68k_dreg(regs, dstreg) = (newv);
33665: }}}}}}}m68k_incpc(4);
33666: return 20;
33667: }
33668: unsigned long REGPARAM2 CPUFUNC(op_90f0_3)(uae_u32 opcode) /* SUBA */
33669: {
33670: uae_u32 srcreg = (opcode & 7);
33671: uae_u32 dstreg = (opcode >> 9) & 7;
33672: OpcodeFamily = 8; CurrentInstrCycles = 18;
33673: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33674: BusCyclePenalty += 2;
33675: { uae_s16 src = get_word(srca);
33676: { uae_s32 dst = m68k_areg(regs, dstreg);
33677: { uae_u32 newv = dst - src;
33678: m68k_areg(regs, dstreg) = (newv);
33679: }}}}}m68k_incpc(4);
33680: return 18;
33681: }
33682: unsigned long REGPARAM2 CPUFUNC(op_90fb_3)(uae_u32 opcode) /* SUBA */
33683: {
33684: uae_u32 dstreg = (opcode >> 9) & 7;
33685: OpcodeFamily = 8; CurrentInstrCycles = 18;
33686: {{ uaecptr tmppc = m68k_getpc() + 2;
33687: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33688: BusCyclePenalty += 2;
33689: { uae_s16 src = get_word(srca);
33690: { uae_s32 dst = m68k_areg(regs, dstreg);
33691: { uae_u32 newv = dst - src;
33692: m68k_areg(regs, dstreg) = (newv);
33693: }}}}}m68k_incpc(4);
33694: return 18;
33695: }
33696: unsigned long REGPARAM2 CPUFUNC(op_9130_3)(uae_u32 opcode) /* SUB */
33697: {
33698: uae_u32 srcreg = ((opcode >> 9) & 7);
33699: uae_u32 dstreg = opcode & 7;
33700: OpcodeFamily = 7; CurrentInstrCycles = 18;
33701: {{ uae_s8 src = m68k_dreg(regs, srcreg);
33702: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
33703: BusCyclePenalty += 2;
33704: { uae_s8 dst = get_byte(dsta);
33705: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
33706: { int flgs = ((uae_s8)(src)) < 0;
33707: int flgo = ((uae_s8)(dst)) < 0;
33708: int flgn = ((uae_s8)(newv)) < 0;
33709: SET_ZFLG (((uae_s8)(newv)) == 0);
33710: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
33711: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
33712: COPY_CARRY;
33713: SET_NFLG (flgn != 0);
33714: put_byte(dsta,newv);
33715: }}}}}}}m68k_incpc(4);
33716: return 18;
33717: }
33718: unsigned long REGPARAM2 CPUFUNC(op_9170_3)(uae_u32 opcode) /* SUB */
33719: {
33720: uae_u32 srcreg = ((opcode >> 9) & 7);
33721: uae_u32 dstreg = opcode & 7;
33722: OpcodeFamily = 7; CurrentInstrCycles = 18;
33723: {{ uae_s16 src = m68k_dreg(regs, srcreg);
33724: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
33725: BusCyclePenalty += 2;
33726: { uae_s16 dst = get_word(dsta);
33727: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
33728: { int flgs = ((uae_s16)(src)) < 0;
33729: int flgo = ((uae_s16)(dst)) < 0;
33730: int flgn = ((uae_s16)(newv)) < 0;
33731: SET_ZFLG (((uae_s16)(newv)) == 0);
33732: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
33733: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
33734: COPY_CARRY;
33735: SET_NFLG (flgn != 0);
33736: put_word(dsta,newv);
33737: }}}}}}}m68k_incpc(4);
33738: return 18;
33739: }
33740: unsigned long REGPARAM2 CPUFUNC(op_91b0_3)(uae_u32 opcode) /* SUB */
33741: {
33742: uae_u32 srcreg = ((opcode >> 9) & 7);
33743: uae_u32 dstreg = opcode & 7;
33744: OpcodeFamily = 7; CurrentInstrCycles = 26;
33745: {{ uae_s32 src = m68k_dreg(regs, srcreg);
33746: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
33747: BusCyclePenalty += 2;
33748: { uae_s32 dst = get_long(dsta);
33749: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
33750: { int flgs = ((uae_s32)(src)) < 0;
33751: int flgo = ((uae_s32)(dst)) < 0;
33752: int flgn = ((uae_s32)(newv)) < 0;
33753: SET_ZFLG (((uae_s32)(newv)) == 0);
33754: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
33755: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
33756: COPY_CARRY;
33757: SET_NFLG (flgn != 0);
33758: put_long(dsta,newv);
33759: }}}}}}}m68k_incpc(4);
33760: return 26;
33761: }
33762: unsigned long REGPARAM2 CPUFUNC(op_91f0_3)(uae_u32 opcode) /* SUBA */
33763: {
33764: uae_u32 srcreg = (opcode & 7);
33765: uae_u32 dstreg = (opcode >> 9) & 7;
33766: OpcodeFamily = 8; CurrentInstrCycles = 20;
33767: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33768: BusCyclePenalty += 2;
33769: { uae_s32 src = get_long(srca);
33770: { uae_s32 dst = m68k_areg(regs, dstreg);
33771: { uae_u32 newv = dst - src;
33772: m68k_areg(regs, dstreg) = (newv);
33773: }}}}}m68k_incpc(4);
33774: return 20;
33775: }
33776: unsigned long REGPARAM2 CPUFUNC(op_91fb_3)(uae_u32 opcode) /* SUBA */
33777: {
33778: uae_u32 dstreg = (opcode >> 9) & 7;
33779: OpcodeFamily = 8; CurrentInstrCycles = 20;
33780: {{ uaecptr tmppc = m68k_getpc() + 2;
33781: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33782: BusCyclePenalty += 2;
33783: { uae_s32 src = get_long(srca);
33784: { uae_s32 dst = m68k_areg(regs, dstreg);
33785: { uae_u32 newv = dst - src;
33786: m68k_areg(regs, dstreg) = (newv);
33787: }}}}}m68k_incpc(4);
33788: return 20;
33789: }
33790: unsigned long REGPARAM2 CPUFUNC(op_b030_3)(uae_u32 opcode) /* CMP */
33791: {
33792: uae_u32 srcreg = (opcode & 7);
33793: uae_u32 dstreg = (opcode >> 9) & 7;
33794: OpcodeFamily = 25; CurrentInstrCycles = 14;
33795: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33796: BusCyclePenalty += 2;
33797: { uae_s8 src = get_byte(srca);
33798: { uae_s8 dst = m68k_dreg(regs, dstreg);
33799: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
33800: { int flgs = ((uae_s8)(src)) < 0;
33801: int flgo = ((uae_s8)(dst)) < 0;
33802: int flgn = ((uae_s8)(newv)) < 0;
33803: SET_ZFLG (((uae_s8)(newv)) == 0);
33804: SET_VFLG ((flgs != flgo) && (flgn != flgo));
33805: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
33806: SET_NFLG (flgn != 0);
33807: }}}}}}}m68k_incpc(4);
33808: return 14;
33809: }
33810: unsigned long REGPARAM2 CPUFUNC(op_b03b_3)(uae_u32 opcode) /* CMP */
33811: {
33812: uae_u32 dstreg = (opcode >> 9) & 7;
33813: OpcodeFamily = 25; CurrentInstrCycles = 14;
33814: {{ uaecptr tmppc = m68k_getpc() + 2;
33815: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33816: BusCyclePenalty += 2;
33817: { uae_s8 src = get_byte(srca);
33818: { uae_s8 dst = m68k_dreg(regs, dstreg);
33819: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
33820: { int flgs = ((uae_s8)(src)) < 0;
33821: int flgo = ((uae_s8)(dst)) < 0;
33822: int flgn = ((uae_s8)(newv)) < 0;
33823: SET_ZFLG (((uae_s8)(newv)) == 0);
33824: SET_VFLG ((flgs != flgo) && (flgn != flgo));
33825: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
33826: SET_NFLG (flgn != 0);
33827: }}}}}}}m68k_incpc(4);
33828: return 14;
33829: }
33830: #endif
33831:
33832: #ifdef PART_7
33833: unsigned long REGPARAM2 CPUFUNC(op_b070_3)(uae_u32 opcode) /* CMP */
33834: {
33835: uae_u32 srcreg = (opcode & 7);
33836: uae_u32 dstreg = (opcode >> 9) & 7;
33837: OpcodeFamily = 25; CurrentInstrCycles = 14;
33838: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33839: BusCyclePenalty += 2;
33840: { uae_s16 src = get_word(srca);
33841: { uae_s16 dst = m68k_dreg(regs, dstreg);
33842: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
33843: { int flgs = ((uae_s16)(src)) < 0;
33844: int flgo = ((uae_s16)(dst)) < 0;
33845: int flgn = ((uae_s16)(newv)) < 0;
33846: SET_ZFLG (((uae_s16)(newv)) == 0);
33847: SET_VFLG ((flgs != flgo) && (flgn != flgo));
33848: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
33849: SET_NFLG (flgn != 0);
33850: }}}}}}}m68k_incpc(4);
33851: return 14;
33852: }
33853: unsigned long REGPARAM2 CPUFUNC(op_b07b_3)(uae_u32 opcode) /* CMP */
33854: {
33855: uae_u32 dstreg = (opcode >> 9) & 7;
33856: OpcodeFamily = 25; CurrentInstrCycles = 14;
33857: {{ uaecptr tmppc = m68k_getpc() + 2;
33858: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33859: BusCyclePenalty += 2;
33860: { uae_s16 src = get_word(srca);
33861: { uae_s16 dst = m68k_dreg(regs, dstreg);
33862: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
33863: { int flgs = ((uae_s16)(src)) < 0;
33864: int flgo = ((uae_s16)(dst)) < 0;
33865: int flgn = ((uae_s16)(newv)) < 0;
33866: SET_ZFLG (((uae_s16)(newv)) == 0);
33867: SET_VFLG ((flgs != flgo) && (flgn != flgo));
33868: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
33869: SET_NFLG (flgn != 0);
33870: }}}}}}}m68k_incpc(4);
33871: return 14;
33872: }
33873: unsigned long REGPARAM2 CPUFUNC(op_b0b0_3)(uae_u32 opcode) /* CMP */
33874: {
33875: uae_u32 srcreg = (opcode & 7);
33876: uae_u32 dstreg = (opcode >> 9) & 7;
33877: OpcodeFamily = 25; CurrentInstrCycles = 20;
33878: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33879: BusCyclePenalty += 2;
33880: { uae_s32 src = get_long(srca);
33881: { uae_s32 dst = m68k_dreg(regs, dstreg);
33882: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
33883: { int flgs = ((uae_s32)(src)) < 0;
33884: int flgo = ((uae_s32)(dst)) < 0;
33885: int flgn = ((uae_s32)(newv)) < 0;
33886: SET_ZFLG (((uae_s32)(newv)) == 0);
33887: SET_VFLG ((flgs != flgo) && (flgn != flgo));
33888: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
33889: SET_NFLG (flgn != 0);
33890: }}}}}}}m68k_incpc(4);
33891: return 20;
33892: }
33893: unsigned long REGPARAM2 CPUFUNC(op_b0bb_3)(uae_u32 opcode) /* CMP */
33894: {
33895: uae_u32 dstreg = (opcode >> 9) & 7;
33896: OpcodeFamily = 25; CurrentInstrCycles = 20;
33897: {{ uaecptr tmppc = m68k_getpc() + 2;
33898: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33899: BusCyclePenalty += 2;
33900: { uae_s32 src = get_long(srca);
33901: { uae_s32 dst = m68k_dreg(regs, dstreg);
33902: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
33903: { int flgs = ((uae_s32)(src)) < 0;
33904: int flgo = ((uae_s32)(dst)) < 0;
33905: int flgn = ((uae_s32)(newv)) < 0;
33906: SET_ZFLG (((uae_s32)(newv)) == 0);
33907: SET_VFLG ((flgs != flgo) && (flgn != flgo));
33908: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
33909: SET_NFLG (flgn != 0);
33910: }}}}}}}m68k_incpc(4);
33911: return 20;
33912: }
33913: unsigned long REGPARAM2 CPUFUNC(op_b0f0_3)(uae_u32 opcode) /* CMPA */
33914: {
33915: uae_u32 srcreg = (opcode & 7);
33916: uae_u32 dstreg = (opcode >> 9) & 7;
33917: OpcodeFamily = 27; CurrentInstrCycles = 16;
33918: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
33919: BusCyclePenalty += 2;
33920: { uae_s16 src = get_word(srca);
33921: { uae_s32 dst = m68k_areg(regs, dstreg);
33922: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
33923: { int flgs = ((uae_s32)(src)) < 0;
33924: int flgo = ((uae_s32)(dst)) < 0;
33925: int flgn = ((uae_s32)(newv)) < 0;
33926: SET_ZFLG (((uae_s32)(newv)) == 0);
33927: SET_VFLG ((flgs != flgo) && (flgn != flgo));
33928: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
33929: SET_NFLG (flgn != 0);
33930: }}}}}}}m68k_incpc(4);
33931: return 16;
33932: }
33933: unsigned long REGPARAM2 CPUFUNC(op_b0fb_3)(uae_u32 opcode) /* CMPA */
33934: {
33935: uae_u32 dstreg = (opcode >> 9) & 7;
33936: OpcodeFamily = 27; CurrentInstrCycles = 16;
33937: {{ uaecptr tmppc = m68k_getpc() + 2;
33938: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
33939: BusCyclePenalty += 2;
33940: { uae_s16 src = get_word(srca);
33941: { uae_s32 dst = m68k_areg(regs, dstreg);
33942: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
33943: { int flgs = ((uae_s32)(src)) < 0;
33944: int flgo = ((uae_s32)(dst)) < 0;
33945: int flgn = ((uae_s32)(newv)) < 0;
33946: SET_ZFLG (((uae_s32)(newv)) == 0);
33947: SET_VFLG ((flgs != flgo) && (flgn != flgo));
33948: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
33949: SET_NFLG (flgn != 0);
33950: }}}}}}}m68k_incpc(4);
33951: return 16;
33952: }
33953: unsigned long REGPARAM2 CPUFUNC(op_b130_3)(uae_u32 opcode) /* EOR */
33954: {
33955: uae_u32 srcreg = ((opcode >> 9) & 7);
33956: uae_u32 dstreg = opcode & 7;
33957: OpcodeFamily = 3; CurrentInstrCycles = 18;
33958: {{ uae_s8 src = m68k_dreg(regs, srcreg);
33959: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
33960: BusCyclePenalty += 2;
33961: { uae_s8 dst = get_byte(dsta);
33962: src ^= dst;
33963: CLEAR_CZNV;
33964: SET_ZFLG (((uae_s8)(src)) == 0);
33965: SET_NFLG (((uae_s8)(src)) < 0);
33966: put_byte(dsta,src);
33967: }}}}m68k_incpc(4);
33968: return 18;
33969: }
33970: unsigned long REGPARAM2 CPUFUNC(op_b170_3)(uae_u32 opcode) /* EOR */
33971: {
33972: uae_u32 srcreg = ((opcode >> 9) & 7);
33973: uae_u32 dstreg = opcode & 7;
33974: OpcodeFamily = 3; CurrentInstrCycles = 18;
33975: {{ uae_s16 src = m68k_dreg(regs, srcreg);
33976: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
33977: BusCyclePenalty += 2;
33978: { uae_s16 dst = get_word(dsta);
33979: src ^= dst;
33980: CLEAR_CZNV;
33981: SET_ZFLG (((uae_s16)(src)) == 0);
33982: SET_NFLG (((uae_s16)(src)) < 0);
33983: put_word(dsta,src);
33984: }}}}m68k_incpc(4);
33985: return 18;
33986: }
33987: unsigned long REGPARAM2 CPUFUNC(op_b1b0_3)(uae_u32 opcode) /* EOR */
33988: {
33989: uae_u32 srcreg = ((opcode >> 9) & 7);
33990: uae_u32 dstreg = opcode & 7;
33991: OpcodeFamily = 3; CurrentInstrCycles = 26;
33992: {{ uae_s32 src = m68k_dreg(regs, srcreg);
33993: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
33994: BusCyclePenalty += 2;
33995: { uae_s32 dst = get_long(dsta);
33996: src ^= dst;
33997: CLEAR_CZNV;
33998: SET_ZFLG (((uae_s32)(src)) == 0);
33999: SET_NFLG (((uae_s32)(src)) < 0);
34000: put_long(dsta,src);
34001: }}}}m68k_incpc(4);
34002: return 26;
34003: }
34004: unsigned long REGPARAM2 CPUFUNC(op_b1f0_3)(uae_u32 opcode) /* CMPA */
34005: {
34006: uae_u32 srcreg = (opcode & 7);
34007: uae_u32 dstreg = (opcode >> 9) & 7;
34008: OpcodeFamily = 27; CurrentInstrCycles = 20;
34009: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34010: BusCyclePenalty += 2;
34011: { uae_s32 src = get_long(srca);
34012: { uae_s32 dst = m68k_areg(regs, dstreg);
34013: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
34014: { int flgs = ((uae_s32)(src)) < 0;
34015: int flgo = ((uae_s32)(dst)) < 0;
34016: int flgn = ((uae_s32)(newv)) < 0;
34017: SET_ZFLG (((uae_s32)(newv)) == 0);
34018: SET_VFLG ((flgs != flgo) && (flgn != flgo));
34019: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
34020: SET_NFLG (flgn != 0);
34021: }}}}}}}m68k_incpc(4);
34022: return 20;
34023: }
34024: unsigned long REGPARAM2 CPUFUNC(op_b1fb_3)(uae_u32 opcode) /* CMPA */
34025: {
34026: uae_u32 dstreg = (opcode >> 9) & 7;
34027: OpcodeFamily = 27; CurrentInstrCycles = 20;
34028: {{ uaecptr tmppc = m68k_getpc() + 2;
34029: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34030: BusCyclePenalty += 2;
34031: { uae_s32 src = get_long(srca);
34032: { uae_s32 dst = m68k_areg(regs, dstreg);
34033: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
34034: { int flgs = ((uae_s32)(src)) < 0;
34035: int flgo = ((uae_s32)(dst)) < 0;
34036: int flgn = ((uae_s32)(newv)) < 0;
34037: SET_ZFLG (((uae_s32)(newv)) == 0);
34038: SET_VFLG ((flgs != flgo) && (flgn != flgo));
34039: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
34040: SET_NFLG (flgn != 0);
34041: }}}}}}}m68k_incpc(4);
34042: return 20;
34043: }
34044: unsigned long REGPARAM2 CPUFUNC(op_c030_3)(uae_u32 opcode) /* AND */
34045: {
34046: uae_u32 srcreg = (opcode & 7);
34047: uae_u32 dstreg = (opcode >> 9) & 7;
34048: OpcodeFamily = 2; CurrentInstrCycles = 14;
34049: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34050: BusCyclePenalty += 2;
34051: { uae_s8 src = get_byte(srca);
34052: { uae_s8 dst = m68k_dreg(regs, dstreg);
34053: src &= dst;
34054: CLEAR_CZNV;
34055: SET_ZFLG (((uae_s8)(src)) == 0);
34056: SET_NFLG (((uae_s8)(src)) < 0);
34057: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
34058: }}}}m68k_incpc(4);
34059: return 14;
34060: }
34061: unsigned long REGPARAM2 CPUFUNC(op_c03b_3)(uae_u32 opcode) /* AND */
34062: {
34063: uae_u32 dstreg = (opcode >> 9) & 7;
34064: OpcodeFamily = 2; CurrentInstrCycles = 14;
34065: {{ uaecptr tmppc = m68k_getpc() + 2;
34066: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34067: BusCyclePenalty += 2;
34068: { uae_s8 src = get_byte(srca);
34069: { uae_s8 dst = m68k_dreg(regs, dstreg);
34070: src &= dst;
34071: CLEAR_CZNV;
34072: SET_ZFLG (((uae_s8)(src)) == 0);
34073: SET_NFLG (((uae_s8)(src)) < 0);
34074: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
34075: }}}}m68k_incpc(4);
34076: return 14;
34077: }
34078: unsigned long REGPARAM2 CPUFUNC(op_c070_3)(uae_u32 opcode) /* AND */
34079: {
34080: uae_u32 srcreg = (opcode & 7);
34081: uae_u32 dstreg = (opcode >> 9) & 7;
34082: OpcodeFamily = 2; CurrentInstrCycles = 14;
34083: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34084: BusCyclePenalty += 2;
34085: { uae_s16 src = get_word(srca);
34086: { uae_s16 dst = m68k_dreg(regs, dstreg);
34087: src &= dst;
34088: CLEAR_CZNV;
34089: SET_ZFLG (((uae_s16)(src)) == 0);
34090: SET_NFLG (((uae_s16)(src)) < 0);
34091: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
34092: }}}}m68k_incpc(4);
34093: return 14;
34094: }
34095: unsigned long REGPARAM2 CPUFUNC(op_c07b_3)(uae_u32 opcode) /* AND */
34096: {
34097: uae_u32 dstreg = (opcode >> 9) & 7;
34098: OpcodeFamily = 2; CurrentInstrCycles = 14;
34099: {{ uaecptr tmppc = m68k_getpc() + 2;
34100: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34101: BusCyclePenalty += 2;
34102: { uae_s16 src = get_word(srca);
34103: { uae_s16 dst = m68k_dreg(regs, dstreg);
34104: src &= dst;
34105: CLEAR_CZNV;
34106: SET_ZFLG (((uae_s16)(src)) == 0);
34107: SET_NFLG (((uae_s16)(src)) < 0);
34108: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
34109: }}}}m68k_incpc(4);
34110: return 14;
34111: }
34112: unsigned long REGPARAM2 CPUFUNC(op_c0b0_3)(uae_u32 opcode) /* AND */
34113: {
34114: uae_u32 srcreg = (opcode & 7);
34115: uae_u32 dstreg = (opcode >> 9) & 7;
34116: OpcodeFamily = 2; CurrentInstrCycles = 20;
34117: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34118: BusCyclePenalty += 2;
34119: { uae_s32 src = get_long(srca);
34120: { uae_s32 dst = m68k_dreg(regs, dstreg);
34121: src &= dst;
34122: CLEAR_CZNV;
34123: SET_ZFLG (((uae_s32)(src)) == 0);
34124: SET_NFLG (((uae_s32)(src)) < 0);
34125: m68k_dreg(regs, dstreg) = (src);
34126: }}}}m68k_incpc(4);
34127: return 20;
34128: }
34129: unsigned long REGPARAM2 CPUFUNC(op_c0bb_3)(uae_u32 opcode) /* AND */
34130: {
34131: uae_u32 dstreg = (opcode >> 9) & 7;
34132: OpcodeFamily = 2; CurrentInstrCycles = 20;
34133: {{ uaecptr tmppc = m68k_getpc() + 2;
34134: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34135: BusCyclePenalty += 2;
34136: { uae_s32 src = get_long(srca);
34137: { uae_s32 dst = m68k_dreg(regs, dstreg);
34138: src &= dst;
34139: CLEAR_CZNV;
34140: SET_ZFLG (((uae_s32)(src)) == 0);
34141: SET_NFLG (((uae_s32)(src)) < 0);
34142: m68k_dreg(regs, dstreg) = (src);
34143: }}}}m68k_incpc(4);
34144: return 20;
34145: }
34146: unsigned long REGPARAM2 CPUFUNC(op_c0f0_3)(uae_u32 opcode) /* MULU */
34147: {
34148: uae_u32 srcreg = (opcode & 7);
34149: uae_u32 dstreg = (opcode >> 9) & 7;
34150: unsigned int retcycles = 0;
34151: OpcodeFamily = 62; CurrentInstrCycles = 48;
34152: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34153: BusCyclePenalty += 2;
34154: { uae_s16 src = get_word(srca);
34155: { uae_s16 dst = m68k_dreg(regs, dstreg);
34156: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
34157: CLEAR_CZNV;
34158: SET_ZFLG (((uae_s32)(newv)) == 0);
34159: SET_NFLG (((uae_s32)(newv)) < 0);
34160: m68k_dreg(regs, dstreg) = (newv);
34161: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
34162: }}}}}m68k_incpc(4);
34163: return (48+retcycles*2);
34164: }
34165: unsigned long REGPARAM2 CPUFUNC(op_c0fb_3)(uae_u32 opcode) /* MULU */
34166: {
34167: uae_u32 dstreg = (opcode >> 9) & 7;
34168: unsigned int retcycles = 0;
34169: OpcodeFamily = 62; CurrentInstrCycles = 48;
34170: {{ uaecptr tmppc = m68k_getpc() + 2;
34171: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34172: BusCyclePenalty += 2;
34173: { uae_s16 src = get_word(srca);
34174: { uae_s16 dst = m68k_dreg(regs, dstreg);
34175: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
34176: CLEAR_CZNV;
34177: SET_ZFLG (((uae_s32)(newv)) == 0);
34178: SET_NFLG (((uae_s32)(newv)) < 0);
34179: m68k_dreg(regs, dstreg) = (newv);
34180: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
34181: }}}}}m68k_incpc(4);
34182: return (48+retcycles*2);
34183: }
34184: unsigned long REGPARAM2 CPUFUNC(op_c130_3)(uae_u32 opcode) /* AND */
34185: {
34186: uae_u32 srcreg = ((opcode >> 9) & 7);
34187: uae_u32 dstreg = opcode & 7;
34188: OpcodeFamily = 2; CurrentInstrCycles = 18;
34189: {{ uae_s8 src = m68k_dreg(regs, srcreg);
34190: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
34191: BusCyclePenalty += 2;
34192: { uae_s8 dst = get_byte(dsta);
34193: src &= dst;
34194: CLEAR_CZNV;
34195: SET_ZFLG (((uae_s8)(src)) == 0);
34196: SET_NFLG (((uae_s8)(src)) < 0);
34197: put_byte(dsta,src);
34198: }}}}m68k_incpc(4);
34199: return 18;
34200: }
34201: unsigned long REGPARAM2 CPUFUNC(op_c170_3)(uae_u32 opcode) /* AND */
34202: {
34203: uae_u32 srcreg = ((opcode >> 9) & 7);
34204: uae_u32 dstreg = opcode & 7;
34205: OpcodeFamily = 2; CurrentInstrCycles = 18;
34206: {{ uae_s16 src = m68k_dreg(regs, srcreg);
34207: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
34208: BusCyclePenalty += 2;
34209: { uae_s16 dst = get_word(dsta);
34210: src &= dst;
34211: CLEAR_CZNV;
34212: SET_ZFLG (((uae_s16)(src)) == 0);
34213: SET_NFLG (((uae_s16)(src)) < 0);
34214: put_word(dsta,src);
34215: }}}}m68k_incpc(4);
34216: return 18;
34217: }
34218: unsigned long REGPARAM2 CPUFUNC(op_c1b0_3)(uae_u32 opcode) /* AND */
34219: {
34220: uae_u32 srcreg = ((opcode >> 9) & 7);
34221: uae_u32 dstreg = opcode & 7;
34222: OpcodeFamily = 2; CurrentInstrCycles = 26;
34223: {{ uae_s32 src = m68k_dreg(regs, srcreg);
34224: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
34225: BusCyclePenalty += 2;
34226: { uae_s32 dst = get_long(dsta);
34227: src &= dst;
34228: CLEAR_CZNV;
34229: SET_ZFLG (((uae_s32)(src)) == 0);
34230: SET_NFLG (((uae_s32)(src)) < 0);
34231: put_long(dsta,src);
34232: }}}}m68k_incpc(4);
34233: return 26;
34234: }
34235: unsigned long REGPARAM2 CPUFUNC(op_c1f0_3)(uae_u32 opcode) /* MULS */
34236: {
34237: uae_u32 srcreg = (opcode & 7);
34238: uae_u32 dstreg = (opcode >> 9) & 7;
34239: unsigned int retcycles = 0;
34240: OpcodeFamily = 63; CurrentInstrCycles = 48;
34241: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34242: BusCyclePenalty += 2;
34243: { uae_s16 src = get_word(srca);
34244: { uae_s16 dst = m68k_dreg(regs, dstreg);
34245: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
34246: uae_u32 src2;
34247: CLEAR_CZNV;
34248: SET_ZFLG (((uae_s32)(newv)) == 0);
34249: SET_NFLG (((uae_s32)(newv)) < 0);
34250: m68k_dreg(regs, dstreg) = (newv);
34251: src2 = ((uae_u32)src) << 1;
34252: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
34253: }}}}}m68k_incpc(4);
34254: return (48+retcycles*2);
34255: }
34256: unsigned long REGPARAM2 CPUFUNC(op_c1fb_3)(uae_u32 opcode) /* MULS */
34257: {
34258: uae_u32 dstreg = (opcode >> 9) & 7;
34259: unsigned int retcycles = 0;
34260: OpcodeFamily = 63; CurrentInstrCycles = 48;
34261: {{ uaecptr tmppc = m68k_getpc() + 2;
34262: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34263: BusCyclePenalty += 2;
34264: { uae_s16 src = get_word(srca);
34265: { uae_s16 dst = m68k_dreg(regs, dstreg);
34266: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
34267: uae_u32 src2;
34268: CLEAR_CZNV;
34269: SET_ZFLG (((uae_s32)(newv)) == 0);
34270: SET_NFLG (((uae_s32)(newv)) < 0);
34271: m68k_dreg(regs, dstreg) = (newv);
34272: src2 = ((uae_u32)src) << 1;
34273: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
34274: }}}}}m68k_incpc(4);
34275: return (48+retcycles*2);
34276: }
34277: unsigned long REGPARAM2 CPUFUNC(op_d030_3)(uae_u32 opcode) /* ADD */
34278: {
34279: uae_u32 srcreg = (opcode & 7);
34280: uae_u32 dstreg = (opcode >> 9) & 7;
34281: OpcodeFamily = 11; CurrentInstrCycles = 14;
34282: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34283: BusCyclePenalty += 2;
34284: { uae_s8 src = get_byte(srca);
34285: { uae_s8 dst = m68k_dreg(regs, dstreg);
34286: { refill_prefetch (m68k_getpc(), 2);
34287: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
34288: { int flgs = ((uae_s8)(src)) < 0;
34289: int flgo = ((uae_s8)(dst)) < 0;
34290: int flgn = ((uae_s8)(newv)) < 0;
34291: SET_ZFLG (((uae_s8)(newv)) == 0);
34292: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
34293: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
34294: COPY_CARRY;
34295: SET_NFLG (flgn != 0);
34296: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
34297: }}}}}}}m68k_incpc(4);
34298: return 14;
34299: }
34300: unsigned long REGPARAM2 CPUFUNC(op_d03b_3)(uae_u32 opcode) /* ADD */
34301: {
34302: uae_u32 dstreg = (opcode >> 9) & 7;
34303: OpcodeFamily = 11; CurrentInstrCycles = 14;
34304: {{ uaecptr tmppc = m68k_getpc() + 2;
34305: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34306: BusCyclePenalty += 2;
34307: { uae_s8 src = get_byte(srca);
34308: { uae_s8 dst = m68k_dreg(regs, dstreg);
34309: { refill_prefetch (m68k_getpc(), 2);
34310: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
34311: { int flgs = ((uae_s8)(src)) < 0;
34312: int flgo = ((uae_s8)(dst)) < 0;
34313: int flgn = ((uae_s8)(newv)) < 0;
34314: SET_ZFLG (((uae_s8)(newv)) == 0);
34315: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
34316: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
34317: COPY_CARRY;
34318: SET_NFLG (flgn != 0);
34319: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
34320: }}}}}}}m68k_incpc(4);
34321: return 14;
34322: }
34323: unsigned long REGPARAM2 CPUFUNC(op_d070_3)(uae_u32 opcode) /* ADD */
34324: {
34325: uae_u32 srcreg = (opcode & 7);
34326: uae_u32 dstreg = (opcode >> 9) & 7;
34327: OpcodeFamily = 11; CurrentInstrCycles = 14;
34328: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34329: BusCyclePenalty += 2;
34330: { uae_s16 src = get_word(srca);
34331: { uae_s16 dst = m68k_dreg(regs, dstreg);
34332: { refill_prefetch (m68k_getpc(), 2);
34333: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
34334: { int flgs = ((uae_s16)(src)) < 0;
34335: int flgo = ((uae_s16)(dst)) < 0;
34336: int flgn = ((uae_s16)(newv)) < 0;
34337: SET_ZFLG (((uae_s16)(newv)) == 0);
34338: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
34339: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
34340: COPY_CARRY;
34341: SET_NFLG (flgn != 0);
34342: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
34343: }}}}}}}m68k_incpc(4);
34344: return 14;
34345: }
34346: unsigned long REGPARAM2 CPUFUNC(op_d07b_3)(uae_u32 opcode) /* ADD */
34347: {
34348: uae_u32 dstreg = (opcode >> 9) & 7;
34349: OpcodeFamily = 11; CurrentInstrCycles = 14;
34350: {{ uaecptr tmppc = m68k_getpc() + 2;
34351: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34352: BusCyclePenalty += 2;
34353: { uae_s16 src = get_word(srca);
34354: { uae_s16 dst = m68k_dreg(regs, dstreg);
34355: { refill_prefetch (m68k_getpc(), 2);
34356: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
34357: { int flgs = ((uae_s16)(src)) < 0;
34358: int flgo = ((uae_s16)(dst)) < 0;
34359: int flgn = ((uae_s16)(newv)) < 0;
34360: SET_ZFLG (((uae_s16)(newv)) == 0);
34361: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
34362: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
34363: COPY_CARRY;
34364: SET_NFLG (flgn != 0);
34365: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
34366: }}}}}}}m68k_incpc(4);
34367: return 14;
34368: }
34369: unsigned long REGPARAM2 CPUFUNC(op_d0b0_3)(uae_u32 opcode) /* ADD */
34370: {
34371: uae_u32 srcreg = (opcode & 7);
34372: uae_u32 dstreg = (opcode >> 9) & 7;
34373: OpcodeFamily = 11; CurrentInstrCycles = 20;
34374: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34375: BusCyclePenalty += 2;
34376: { uae_s32 src = get_long(srca);
34377: { uae_s32 dst = m68k_dreg(regs, dstreg);
34378: { refill_prefetch (m68k_getpc(), 2);
34379: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
34380: { int flgs = ((uae_s32)(src)) < 0;
34381: int flgo = ((uae_s32)(dst)) < 0;
34382: int flgn = ((uae_s32)(newv)) < 0;
34383: SET_ZFLG (((uae_s32)(newv)) == 0);
34384: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
34385: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
34386: COPY_CARRY;
34387: SET_NFLG (flgn != 0);
34388: m68k_dreg(regs, dstreg) = (newv);
34389: }}}}}}}m68k_incpc(4);
34390: return 20;
34391: }
34392: unsigned long REGPARAM2 CPUFUNC(op_d0bb_3)(uae_u32 opcode) /* ADD */
34393: {
34394: uae_u32 dstreg = (opcode >> 9) & 7;
34395: OpcodeFamily = 11; CurrentInstrCycles = 20;
34396: {{ uaecptr tmppc = m68k_getpc() + 2;
34397: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34398: BusCyclePenalty += 2;
34399: { uae_s32 src = get_long(srca);
34400: { uae_s32 dst = m68k_dreg(regs, dstreg);
34401: { refill_prefetch (m68k_getpc(), 2);
34402: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
34403: { int flgs = ((uae_s32)(src)) < 0;
34404: int flgo = ((uae_s32)(dst)) < 0;
34405: int flgn = ((uae_s32)(newv)) < 0;
34406: SET_ZFLG (((uae_s32)(newv)) == 0);
34407: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
34408: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
34409: COPY_CARRY;
34410: SET_NFLG (flgn != 0);
34411: m68k_dreg(regs, dstreg) = (newv);
34412: }}}}}}}m68k_incpc(4);
34413: return 20;
34414: }
34415: unsigned long REGPARAM2 CPUFUNC(op_d0f0_3)(uae_u32 opcode) /* ADDA */
34416: {
34417: uae_u32 srcreg = (opcode & 7);
34418: uae_u32 dstreg = (opcode >> 9) & 7;
34419: OpcodeFamily = 12; CurrentInstrCycles = 18;
34420: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34421: BusCyclePenalty += 2;
34422: { uae_s16 src = get_word(srca);
34423: { uae_s32 dst = m68k_areg(regs, dstreg);
34424: { uae_u32 newv = dst + src;
34425: m68k_areg(regs, dstreg) = (newv);
34426: }}}}}m68k_incpc(4);
34427: return 18;
34428: }
34429: unsigned long REGPARAM2 CPUFUNC(op_d0fb_3)(uae_u32 opcode) /* ADDA */
34430: {
34431: uae_u32 dstreg = (opcode >> 9) & 7;
34432: OpcodeFamily = 12; CurrentInstrCycles = 18;
34433: {{ uaecptr tmppc = m68k_getpc() + 2;
34434: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34435: BusCyclePenalty += 2;
34436: { uae_s16 src = get_word(srca);
34437: { uae_s32 dst = m68k_areg(regs, dstreg);
34438: { uae_u32 newv = dst + src;
34439: m68k_areg(regs, dstreg) = (newv);
34440: }}}}}m68k_incpc(4);
34441: return 18;
34442: }
34443: unsigned long REGPARAM2 CPUFUNC(op_d130_3)(uae_u32 opcode) /* ADD */
34444: {
34445: uae_u32 srcreg = ((opcode >> 9) & 7);
34446: uae_u32 dstreg = opcode & 7;
34447: OpcodeFamily = 11; CurrentInstrCycles = 18;
34448: {{ uae_s8 src = m68k_dreg(regs, srcreg);
34449: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
34450: BusCyclePenalty += 2;
34451: { uae_s8 dst = get_byte(dsta);
34452: { refill_prefetch (m68k_getpc(), 2);
34453: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
34454: { int flgs = ((uae_s8)(src)) < 0;
34455: int flgo = ((uae_s8)(dst)) < 0;
34456: int flgn = ((uae_s8)(newv)) < 0;
34457: SET_ZFLG (((uae_s8)(newv)) == 0);
34458: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
34459: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
34460: COPY_CARRY;
34461: SET_NFLG (flgn != 0);
34462: put_byte(dsta,newv);
34463: }}}}}}}m68k_incpc(4);
34464: return 18;
34465: }
34466: unsigned long REGPARAM2 CPUFUNC(op_d170_3)(uae_u32 opcode) /* ADD */
34467: {
34468: uae_u32 srcreg = ((opcode >> 9) & 7);
34469: uae_u32 dstreg = opcode & 7;
34470: OpcodeFamily = 11; CurrentInstrCycles = 18;
34471: {{ uae_s16 src = m68k_dreg(regs, srcreg);
34472: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
34473: BusCyclePenalty += 2;
34474: { uae_s16 dst = get_word(dsta);
34475: { refill_prefetch (m68k_getpc(), 2);
34476: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
34477: { int flgs = ((uae_s16)(src)) < 0;
34478: int flgo = ((uae_s16)(dst)) < 0;
34479: int flgn = ((uae_s16)(newv)) < 0;
34480: SET_ZFLG (((uae_s16)(newv)) == 0);
34481: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
34482: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
34483: COPY_CARRY;
34484: SET_NFLG (flgn != 0);
34485: put_word(dsta,newv);
34486: }}}}}}}m68k_incpc(4);
34487: return 18;
34488: }
34489: unsigned long REGPARAM2 CPUFUNC(op_d1b0_3)(uae_u32 opcode) /* ADD */
34490: {
34491: uae_u32 srcreg = ((opcode >> 9) & 7);
34492: uae_u32 dstreg = opcode & 7;
34493: OpcodeFamily = 11; CurrentInstrCycles = 26;
34494: {{ uae_s32 src = m68k_dreg(regs, srcreg);
34495: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
34496: BusCyclePenalty += 2;
34497: { uae_s32 dst = get_long(dsta);
34498: { refill_prefetch (m68k_getpc(), 2);
34499: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
34500: { int flgs = ((uae_s32)(src)) < 0;
34501: int flgo = ((uae_s32)(dst)) < 0;
34502: int flgn = ((uae_s32)(newv)) < 0;
34503: SET_ZFLG (((uae_s32)(newv)) == 0);
34504: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
34505: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
34506: COPY_CARRY;
34507: SET_NFLG (flgn != 0);
34508: put_long(dsta,newv);
34509: }}}}}}}m68k_incpc(4);
34510: return 26;
34511: }
34512: #endif
34513:
34514: #ifdef PART_8
34515: unsigned long REGPARAM2 CPUFUNC(op_d1f0_3)(uae_u32 opcode) /* ADDA */
34516: {
34517: uae_u32 srcreg = (opcode & 7);
34518: uae_u32 dstreg = (opcode >> 9) & 7;
34519: OpcodeFamily = 12; CurrentInstrCycles = 20;
34520: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34521: BusCyclePenalty += 2;
34522: { uae_s32 src = get_long(srca);
34523: { uae_s32 dst = m68k_areg(regs, dstreg);
34524: { uae_u32 newv = dst + src;
34525: m68k_areg(regs, dstreg) = (newv);
34526: }}}}}m68k_incpc(4);
34527: return 20;
34528: }
34529: unsigned long REGPARAM2 CPUFUNC(op_d1fb_3)(uae_u32 opcode) /* ADDA */
34530: {
34531: uae_u32 dstreg = (opcode >> 9) & 7;
34532: OpcodeFamily = 12; CurrentInstrCycles = 20;
34533: {{ uaecptr tmppc = m68k_getpc() + 2;
34534: uaecptr srca = get_disp_ea_000(tmppc, get_iword(2));
34535: BusCyclePenalty += 2;
34536: { uae_s32 src = get_long(srca);
34537: { uae_s32 dst = m68k_areg(regs, dstreg);
34538: { uae_u32 newv = dst + src;
34539: m68k_areg(regs, dstreg) = (newv);
34540: }}}}}m68k_incpc(4);
34541: return 20;
34542: }
34543: unsigned long REGPARAM2 CPUFUNC(op_e0f0_3)(uae_u32 opcode) /* ASRW */
34544: {
34545: uae_u32 srcreg = (opcode & 7);
34546: OpcodeFamily = 72; CurrentInstrCycles = 18;
34547: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34548: BusCyclePenalty += 2;
34549: { uae_s16 data = get_word(dataa);
34550: { uae_u32 val = (uae_u16)data;
34551: uae_u32 sign = 0x8000 & val;
34552: uae_u32 cflg = val & 1;
34553: val = (val >> 1) | sign;
34554: CLEAR_CZNV;
34555: SET_ZFLG (((uae_s16)(val)) == 0);
34556: SET_NFLG (((uae_s16)(val)) < 0);
34557: SET_CFLG (cflg);
34558: COPY_CARRY;
34559: put_word(dataa,val);
34560: }}}}m68k_incpc(4);
34561: return 18;
34562: }
34563: unsigned long REGPARAM2 CPUFUNC(op_e1f0_3)(uae_u32 opcode) /* ASLW */
34564: {
34565: uae_u32 srcreg = (opcode & 7);
34566: OpcodeFamily = 73; CurrentInstrCycles = 18;
34567: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34568: BusCyclePenalty += 2;
34569: { uae_s16 data = get_word(dataa);
34570: { uae_u32 val = (uae_u16)data;
34571: uae_u32 sign = 0x8000 & val;
34572: uae_u32 sign2;
34573: val <<= 1;
34574: CLEAR_CZNV;
34575: SET_ZFLG (((uae_s16)(val)) == 0);
34576: SET_NFLG (((uae_s16)(val)) < 0);
34577: sign2 = 0x8000 & val;
34578: SET_CFLG (sign != 0);
34579: COPY_CARRY;
34580: SET_VFLG (GET_VFLG | (sign2 != sign));
34581: put_word(dataa,val);
34582: }}}}m68k_incpc(4);
34583: return 18;
34584: }
34585: unsigned long REGPARAM2 CPUFUNC(op_e2f0_3)(uae_u32 opcode) /* LSRW */
34586: {
34587: uae_u32 srcreg = (opcode & 7);
34588: OpcodeFamily = 74; CurrentInstrCycles = 18;
34589: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34590: BusCyclePenalty += 2;
34591: { uae_s16 data = get_word(dataa);
34592: { uae_u32 val = (uae_u16)data;
34593: uae_u32 carry = val & 1;
34594: val >>= 1;
34595: CLEAR_CZNV;
34596: SET_ZFLG (((uae_s16)(val)) == 0);
34597: SET_NFLG (((uae_s16)(val)) < 0);
34598: SET_CFLG (carry);
34599: COPY_CARRY;
34600: put_word(dataa,val);
34601: }}}}m68k_incpc(4);
34602: return 18;
34603: }
34604: unsigned long REGPARAM2 CPUFUNC(op_e3f0_3)(uae_u32 opcode) /* LSLW */
34605: {
34606: uae_u32 srcreg = (opcode & 7);
34607: OpcodeFamily = 75; CurrentInstrCycles = 18;
34608: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34609: BusCyclePenalty += 2;
34610: { uae_s16 data = get_word(dataa);
34611: { uae_u16 val = data;
34612: uae_u32 carry = val & 0x8000;
34613: val <<= 1;
34614: CLEAR_CZNV;
34615: SET_ZFLG (((uae_s16)(val)) == 0);
34616: SET_NFLG (((uae_s16)(val)) < 0);
34617: SET_CFLG (carry >> 15);
34618: COPY_CARRY;
34619: put_word(dataa,val);
34620: }}}}m68k_incpc(4);
34621: return 18;
34622: }
34623: unsigned long REGPARAM2 CPUFUNC(op_e4f0_3)(uae_u32 opcode) /* ROXRW */
34624: {
34625: uae_u32 srcreg = (opcode & 7);
34626: OpcodeFamily = 79; CurrentInstrCycles = 18;
34627: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34628: BusCyclePenalty += 2;
34629: { uae_s16 data = get_word(dataa);
34630: { uae_u16 val = data;
34631: uae_u32 carry = val & 1;
34632: val >>= 1;
34633: if (GET_XFLG) val |= 0x8000;
34634: CLEAR_CZNV;
34635: SET_ZFLG (((uae_s16)(val)) == 0);
34636: SET_NFLG (((uae_s16)(val)) < 0);
34637: SET_CFLG (carry);
34638: COPY_CARRY;
34639: put_word(dataa,val);
34640: }}}}m68k_incpc(4);
34641: return 18;
34642: }
34643: unsigned long REGPARAM2 CPUFUNC(op_e5f0_3)(uae_u32 opcode) /* ROXLW */
34644: {
34645: uae_u32 srcreg = (opcode & 7);
34646: OpcodeFamily = 78; CurrentInstrCycles = 18;
34647: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34648: BusCyclePenalty += 2;
34649: { uae_s16 data = get_word(dataa);
34650: { uae_u16 val = data;
34651: uae_u32 carry = val & 0x8000;
34652: val <<= 1;
34653: if (GET_XFLG) val |= 1;
34654: CLEAR_CZNV;
34655: SET_ZFLG (((uae_s16)(val)) == 0);
34656: SET_NFLG (((uae_s16)(val)) < 0);
34657: SET_CFLG (carry >> 15);
34658: COPY_CARRY;
34659: put_word(dataa,val);
34660: }}}}m68k_incpc(4);
34661: return 18;
34662: }
34663: unsigned long REGPARAM2 CPUFUNC(op_e6f0_3)(uae_u32 opcode) /* RORW */
34664: {
34665: uae_u32 srcreg = (opcode & 7);
34666: OpcodeFamily = 77; CurrentInstrCycles = 18;
34667: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34668: BusCyclePenalty += 2;
34669: { uae_s16 data = get_word(dataa);
34670: { uae_u16 val = data;
34671: uae_u32 carry = val & 1;
34672: val >>= 1;
34673: if (carry) val |= 0x8000;
34674: CLEAR_CZNV;
34675: SET_ZFLG (((uae_s16)(val)) == 0);
34676: SET_NFLG (((uae_s16)(val)) < 0);
34677: SET_CFLG (carry);
34678: put_word(dataa,val);
34679: }}}}m68k_incpc(4);
34680: return 18;
34681: }
34682: unsigned long REGPARAM2 CPUFUNC(op_e7f0_3)(uae_u32 opcode) /* ROLW */
34683: {
34684: uae_u32 srcreg = (opcode & 7);
34685: OpcodeFamily = 76; CurrentInstrCycles = 18;
34686: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34687: BusCyclePenalty += 2;
34688: { uae_s16 data = get_word(dataa);
34689: { uae_u16 val = data;
34690: uae_u32 carry = val & 0x8000;
34691: val <<= 1;
34692: if (carry) val |= 1;
34693: CLEAR_CZNV;
34694: SET_ZFLG (((uae_s16)(val)) == 0);
34695: SET_NFLG (((uae_s16)(val)) < 0);
34696: SET_CFLG (carry >> 15);
34697: put_word(dataa,val);
34698: }}}}m68k_incpc(4);
34699: return 18;
34700: }
34701: #endif
34702:
34703:
34704: #if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
34705: #define PART_1 1
34706: #define PART_2 1
34707: #define PART_3 1
34708: #define PART_4 1
34709: #define PART_5 1
34710: #define PART_6 1
34711: #define PART_7 1
34712: #define PART_8 1
34713: #endif
34714:
34715: #ifdef PART_1
34716: #endif
34717:
34718: #ifdef PART_2
34719: #endif
34720:
34721: #ifdef PART_3
34722: unsigned long REGPARAM2 CPUFUNC(op_40c0_4)(uae_u32 opcode) /* MVSR2 */
34723: {
34724: uae_u32 srcreg = (opcode & 7);
34725: OpcodeFamily = 32; CurrentInstrCycles = 6;
34726: {{ MakeSR();
34727: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
34728: }}m68k_incpc(2);
34729: return 6;
34730: }
34731: unsigned long REGPARAM2 CPUFUNC(op_40d0_4)(uae_u32 opcode) /* MVSR2 */
34732: {
34733: uae_u32 srcreg = (opcode & 7);
34734: OpcodeFamily = 32; CurrentInstrCycles = 12;
34735: {{ uaecptr srca = m68k_areg(regs, srcreg);
34736: MakeSR();
34737: put_word(srca,regs.sr);
34738: }}m68k_incpc(2);
34739: return 12;
34740: }
34741: unsigned long REGPARAM2 CPUFUNC(op_40d8_4)(uae_u32 opcode) /* MVSR2 */
34742: {
34743: uae_u32 srcreg = (opcode & 7);
34744: OpcodeFamily = 32; CurrentInstrCycles = 12;
34745: {{ uaecptr srca = m68k_areg(regs, srcreg);
34746: m68k_areg(regs, srcreg) += 2;
34747: MakeSR();
34748: put_word(srca,regs.sr);
34749: }}m68k_incpc(2);
34750: return 12;
34751: }
34752: unsigned long REGPARAM2 CPUFUNC(op_40e0_4)(uae_u32 opcode) /* MVSR2 */
34753: {
34754: uae_u32 srcreg = (opcode & 7);
34755: OpcodeFamily = 32; CurrentInstrCycles = 14;
34756: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
34757: m68k_areg (regs, srcreg) = srca;
34758: MakeSR();
34759: put_word(srca,regs.sr);
34760: }}m68k_incpc(2);
34761: return 14;
34762: }
34763: unsigned long REGPARAM2 CPUFUNC(op_40e8_4)(uae_u32 opcode) /* MVSR2 */
34764: {
34765: uae_u32 srcreg = (opcode & 7);
34766: OpcodeFamily = 32; CurrentInstrCycles = 16;
34767: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword(2);
34768: MakeSR();
34769: put_word(srca,regs.sr);
34770: }}m68k_incpc(4);
34771: return 16;
34772: }
34773: unsigned long REGPARAM2 CPUFUNC(op_40f0_4)(uae_u32 opcode) /* MVSR2 */
34774: {
34775: uae_u32 srcreg = (opcode & 7);
34776: OpcodeFamily = 32; CurrentInstrCycles = 18;
34777: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
34778: BusCyclePenalty += 2;
34779: MakeSR();
34780: put_word(srca,regs.sr);
34781: }}m68k_incpc(4);
34782: return 18;
34783: }
34784: unsigned long REGPARAM2 CPUFUNC(op_40f8_4)(uae_u32 opcode) /* MVSR2 */
34785: {
34786: OpcodeFamily = 32; CurrentInstrCycles = 16;
34787: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword(2);
34788: MakeSR();
34789: put_word(srca,regs.sr);
34790: }}m68k_incpc(4);
34791: return 16;
34792: }
34793: unsigned long REGPARAM2 CPUFUNC(op_40f9_4)(uae_u32 opcode) /* MVSR2 */
34794: {
34795: OpcodeFamily = 32; CurrentInstrCycles = 20;
34796: {{ uaecptr srca = get_ilong(2);
34797: MakeSR();
34798: put_word(srca,regs.sr);
34799: }}m68k_incpc(6);
34800: return 20;
34801: }
34802: #endif
34803:
34804: #ifdef PART_4
34805: unsigned long REGPARAM2 CPUFUNC(op_4e73_4)(uae_u32 opcode) /* RTE */
34806: {
34807: OpcodeFamily = 45; CurrentInstrCycles = 20;
34808: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2154; }
34809: {{ uaecptr sra = m68k_areg(regs, 7);
34810: { uae_s16 sr = get_word(sra);
34811: m68k_areg(regs, 7) += 2;
34812: { uaecptr pca = m68k_areg(regs, 7);
34813: { uae_s32 pc = get_long(pca);
34814: m68k_areg(regs, 7) += 4;
34815: regs.sr = sr; m68k_setpc_rte(pc);
34816: MakeFromSR();
34817: }}}}}}endlabel2154: ;
34818: return 20;
34819: }
34820: #endif
34821:
34822: #ifdef PART_5
34823: #endif
34824:
34825: #ifdef PART_6
34826: #endif
34827:
34828: #ifdef PART_7
34829: #endif
34830:
34831: #ifdef PART_8
34832: #endif
34833:
34834:
34835: #if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
34836: #define PART_1 1
34837: #define PART_2 1
34838: #define PART_3 1
34839: #define PART_4 1
34840: #define PART_5 1
34841: #define PART_6 1
34842: #define PART_7 1
34843: #define PART_8 1
34844: #endif
34845:
34846: #ifdef PART_1
34847: unsigned long REGPARAM2 CPUFUNC(op_0_5)(uae_u32 opcode) /* OR */
34848: {
34849: uae_u32 dstreg = opcode & 7;
34850: OpcodeFamily = 1; CurrentInstrCycles = 8;
34851: {{ uae_s8 src = get_ibyte_prefetch(2);
34852: { uae_s8 dst = m68k_dreg(regs, dstreg);
34853: src |= dst;
34854: CLEAR_CZNV;
34855: SET_ZFLG (((uae_s8)(src)) == 0);
34856: SET_NFLG (((uae_s8)(src)) < 0);
34857: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
34858: }}}m68k_incpc(4);
34859: fill_prefetch_0 ();
34860: return 8;
34861: }
34862: unsigned long REGPARAM2 CPUFUNC(op_10_5)(uae_u32 opcode) /* OR */
34863: {
34864: uae_u32 dstreg = opcode & 7;
34865: OpcodeFamily = 1; CurrentInstrCycles = 16;
34866: {{ uae_s8 src = get_ibyte_prefetch(2);
34867: { uaecptr dsta = m68k_areg(regs, dstreg);
34868: { uae_s8 dst = get_byte(dsta);
34869: src |= dst;
34870: CLEAR_CZNV;
34871: SET_ZFLG (((uae_s8)(src)) == 0);
34872: SET_NFLG (((uae_s8)(src)) < 0);
34873: m68k_incpc(4);
34874: fill_prefetch_0 ();
34875: put_byte(dsta,src);
34876: }}}}return 16;
34877: }
34878: unsigned long REGPARAM2 CPUFUNC(op_18_5)(uae_u32 opcode) /* OR */
34879: {
34880: uae_u32 dstreg = opcode & 7;
34881: OpcodeFamily = 1; CurrentInstrCycles = 16;
34882: {{ uae_s8 src = get_ibyte_prefetch(2);
34883: { uaecptr dsta = m68k_areg(regs, dstreg);
34884: { uae_s8 dst = get_byte(dsta);
34885: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
34886: src |= dst;
34887: CLEAR_CZNV;
34888: SET_ZFLG (((uae_s8)(src)) == 0);
34889: SET_NFLG (((uae_s8)(src)) < 0);
34890: m68k_incpc(4);
34891: fill_prefetch_0 ();
34892: put_byte(dsta,src);
34893: }}}}return 16;
34894: }
34895: unsigned long REGPARAM2 CPUFUNC(op_20_5)(uae_u32 opcode) /* OR */
34896: {
34897: uae_u32 dstreg = opcode & 7;
34898: OpcodeFamily = 1; CurrentInstrCycles = 18;
34899: {{ uae_s8 src = get_ibyte_prefetch(2);
34900: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
34901: { uae_s8 dst = get_byte(dsta);
34902: m68k_areg (regs, dstreg) = dsta;
34903: src |= dst;
34904: CLEAR_CZNV;
34905: SET_ZFLG (((uae_s8)(src)) == 0);
34906: SET_NFLG (((uae_s8)(src)) < 0);
34907: m68k_incpc(4);
34908: fill_prefetch_0 ();
34909: put_byte(dsta,src);
34910: }}}}return 18;
34911: }
34912: unsigned long REGPARAM2 CPUFUNC(op_28_5)(uae_u32 opcode) /* OR */
34913: {
34914: uae_u32 dstreg = opcode & 7;
34915: OpcodeFamily = 1; CurrentInstrCycles = 20;
34916: {{ uae_s8 src = get_ibyte_prefetch(2);
34917: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
34918: { uae_s8 dst = get_byte(dsta);
34919: src |= dst;
34920: CLEAR_CZNV;
34921: SET_ZFLG (((uae_s8)(src)) == 0);
34922: SET_NFLG (((uae_s8)(src)) < 0);
34923: m68k_incpc(6);
34924: fill_prefetch_0 ();
34925: put_byte(dsta,src);
34926: }}}}return 20;
34927: }
34928: unsigned long REGPARAM2 CPUFUNC(op_30_5)(uae_u32 opcode) /* OR */
34929: {
34930: uae_u32 dstreg = opcode & 7;
34931: OpcodeFamily = 1; CurrentInstrCycles = 22;
34932: {{ uae_s8 src = get_ibyte_prefetch(2);
34933: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
34934: BusCyclePenalty += 2;
34935: { uae_s8 dst = get_byte(dsta);
34936: src |= dst;
34937: CLEAR_CZNV;
34938: SET_ZFLG (((uae_s8)(src)) == 0);
34939: SET_NFLG (((uae_s8)(src)) < 0);
34940: m68k_incpc(6);
34941: fill_prefetch_0 ();
34942: put_byte(dsta,src);
34943: }}}}return 22;
34944: }
34945: unsigned long REGPARAM2 CPUFUNC(op_38_5)(uae_u32 opcode) /* OR */
34946: {
34947: OpcodeFamily = 1; CurrentInstrCycles = 20;
34948: {{ uae_s8 src = get_ibyte_prefetch(2);
34949: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
34950: { uae_s8 dst = get_byte(dsta);
34951: src |= dst;
34952: CLEAR_CZNV;
34953: SET_ZFLG (((uae_s8)(src)) == 0);
34954: SET_NFLG (((uae_s8)(src)) < 0);
34955: m68k_incpc(6);
34956: fill_prefetch_0 ();
34957: put_byte(dsta,src);
34958: }}}}return 20;
34959: }
34960: unsigned long REGPARAM2 CPUFUNC(op_39_5)(uae_u32 opcode) /* OR */
34961: {
34962: OpcodeFamily = 1; CurrentInstrCycles = 24;
34963: {{ uae_s8 src = get_ibyte_prefetch(2);
34964: { uaecptr dsta = get_ilong_prefetch(4);
34965: { uae_s8 dst = get_byte(dsta);
34966: src |= dst;
34967: CLEAR_CZNV;
34968: SET_ZFLG (((uae_s8)(src)) == 0);
34969: SET_NFLG (((uae_s8)(src)) < 0);
34970: m68k_incpc(8);
34971: fill_prefetch_0 ();
34972: put_byte(dsta,src);
34973: }}}}return 24;
34974: }
34975: unsigned long REGPARAM2 CPUFUNC(op_3c_5)(uae_u32 opcode) /* ORSR */
34976: {
34977: OpcodeFamily = 4; CurrentInstrCycles = 20;
34978: { MakeSR();
34979: { uae_s16 src = get_iword_prefetch(2);
34980: src &= 0xFF;
34981: regs.sr |= src;
34982: MakeFromSR();
34983: }}m68k_incpc(4);
34984: fill_prefetch_0 ();
34985: return 20;
34986: }
34987: unsigned long REGPARAM2 CPUFUNC(op_40_5)(uae_u32 opcode) /* OR */
34988: {
34989: uae_u32 dstreg = opcode & 7;
34990: OpcodeFamily = 1; CurrentInstrCycles = 8;
34991: {{ uae_s16 src = get_iword_prefetch(2);
34992: { uae_s16 dst = m68k_dreg(regs, dstreg);
34993: src |= dst;
34994: CLEAR_CZNV;
34995: SET_ZFLG (((uae_s16)(src)) == 0);
34996: SET_NFLG (((uae_s16)(src)) < 0);
34997: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
34998: }}}m68k_incpc(4);
34999: fill_prefetch_0 ();
35000: return 8;
35001: }
35002: unsigned long REGPARAM2 CPUFUNC(op_50_5)(uae_u32 opcode) /* OR */
35003: {
35004: uae_u32 dstreg = opcode & 7;
35005: OpcodeFamily = 1; CurrentInstrCycles = 16;
35006: {{ uae_s16 src = get_iword_prefetch(2);
35007: { uaecptr dsta = m68k_areg(regs, dstreg);
35008: if ((dsta & 1) != 0) {
35009: last_fault_for_exception_3 = dsta;
35010: last_op_for_exception_3 = opcode;
35011: last_addr_for_exception_3 = m68k_getpc() + 4;
35012: Exception(3, 0, M68000_EXC_SRC_CPU);
35013: goto endlabel2165;
35014: }
35015: {{ uae_s16 dst = get_word(dsta);
35016: src |= dst;
35017: CLEAR_CZNV;
35018: SET_ZFLG (((uae_s16)(src)) == 0);
35019: SET_NFLG (((uae_s16)(src)) < 0);
35020: m68k_incpc(4);
35021: fill_prefetch_0 ();
35022: put_word(dsta,src);
35023: }}}}}endlabel2165: ;
35024: return 16;
35025: }
35026: unsigned long REGPARAM2 CPUFUNC(op_58_5)(uae_u32 opcode) /* OR */
35027: {
35028: uae_u32 dstreg = opcode & 7;
35029: OpcodeFamily = 1; CurrentInstrCycles = 16;
35030: {{ uae_s16 src = get_iword_prefetch(2);
35031: { uaecptr dsta = m68k_areg(regs, dstreg);
35032: if ((dsta & 1) != 0) {
35033: last_fault_for_exception_3 = dsta;
35034: last_op_for_exception_3 = opcode;
35035: last_addr_for_exception_3 = m68k_getpc() + 4;
35036: Exception(3, 0, M68000_EXC_SRC_CPU);
35037: goto endlabel2166;
35038: }
35039: {{ uae_s16 dst = get_word(dsta);
35040: m68k_areg(regs, dstreg) += 2;
35041: src |= dst;
35042: CLEAR_CZNV;
35043: SET_ZFLG (((uae_s16)(src)) == 0);
35044: SET_NFLG (((uae_s16)(src)) < 0);
35045: m68k_incpc(4);
35046: fill_prefetch_0 ();
35047: put_word(dsta,src);
35048: }}}}}endlabel2166: ;
35049: return 16;
35050: }
35051: unsigned long REGPARAM2 CPUFUNC(op_60_5)(uae_u32 opcode) /* OR */
35052: {
35053: uae_u32 dstreg = opcode & 7;
35054: OpcodeFamily = 1; CurrentInstrCycles = 18;
35055: {{ uae_s16 src = get_iword_prefetch(2);
35056: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
35057: if ((dsta & 1) != 0) {
35058: last_fault_for_exception_3 = dsta;
35059: last_op_for_exception_3 = opcode;
35060: last_addr_for_exception_3 = m68k_getpc() + 4;
35061: Exception(3, 0, M68000_EXC_SRC_CPU);
35062: goto endlabel2167;
35063: }
35064: {{ uae_s16 dst = get_word(dsta);
35065: m68k_areg (regs, dstreg) = dsta;
35066: src |= dst;
35067: CLEAR_CZNV;
35068: SET_ZFLG (((uae_s16)(src)) == 0);
35069: SET_NFLG (((uae_s16)(src)) < 0);
35070: m68k_incpc(4);
35071: fill_prefetch_0 ();
35072: put_word(dsta,src);
35073: }}}}}endlabel2167: ;
35074: return 18;
35075: }
35076: unsigned long REGPARAM2 CPUFUNC(op_68_5)(uae_u32 opcode) /* OR */
35077: {
35078: uae_u32 dstreg = opcode & 7;
35079: OpcodeFamily = 1; CurrentInstrCycles = 20;
35080: {{ uae_s16 src = get_iword_prefetch(2);
35081: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
35082: if ((dsta & 1) != 0) {
35083: last_fault_for_exception_3 = dsta;
35084: last_op_for_exception_3 = opcode;
35085: last_addr_for_exception_3 = m68k_getpc() + 6;
35086: Exception(3, 0, M68000_EXC_SRC_CPU);
35087: goto endlabel2168;
35088: }
35089: {{ uae_s16 dst = get_word(dsta);
35090: src |= dst;
35091: CLEAR_CZNV;
35092: SET_ZFLG (((uae_s16)(src)) == 0);
35093: SET_NFLG (((uae_s16)(src)) < 0);
35094: m68k_incpc(6);
35095: fill_prefetch_0 ();
35096: put_word(dsta,src);
35097: }}}}}endlabel2168: ;
35098: return 20;
35099: }
35100: unsigned long REGPARAM2 CPUFUNC(op_70_5)(uae_u32 opcode) /* OR */
35101: {
35102: uae_u32 dstreg = opcode & 7;
35103: OpcodeFamily = 1; CurrentInstrCycles = 22;
35104: {{ uae_s16 src = get_iword_prefetch(2);
35105: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
35106: BusCyclePenalty += 2;
35107: if ((dsta & 1) != 0) {
35108: last_fault_for_exception_3 = dsta;
35109: last_op_for_exception_3 = opcode;
35110: last_addr_for_exception_3 = m68k_getpc() + 6;
35111: Exception(3, 0, M68000_EXC_SRC_CPU);
35112: goto endlabel2169;
35113: }
35114: {{ uae_s16 dst = get_word(dsta);
35115: src |= dst;
35116: CLEAR_CZNV;
35117: SET_ZFLG (((uae_s16)(src)) == 0);
35118: SET_NFLG (((uae_s16)(src)) < 0);
35119: m68k_incpc(6);
35120: fill_prefetch_0 ();
35121: put_word(dsta,src);
35122: }}}}}endlabel2169: ;
35123: return 22;
35124: }
35125: unsigned long REGPARAM2 CPUFUNC(op_78_5)(uae_u32 opcode) /* OR */
35126: {
35127: OpcodeFamily = 1; CurrentInstrCycles = 20;
35128: {{ uae_s16 src = get_iword_prefetch(2);
35129: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
35130: if ((dsta & 1) != 0) {
35131: last_fault_for_exception_3 = dsta;
35132: last_op_for_exception_3 = opcode;
35133: last_addr_for_exception_3 = m68k_getpc() + 6;
35134: Exception(3, 0, M68000_EXC_SRC_CPU);
35135: goto endlabel2170;
35136: }
35137: {{ uae_s16 dst = get_word(dsta);
35138: src |= dst;
35139: CLEAR_CZNV;
35140: SET_ZFLG (((uae_s16)(src)) == 0);
35141: SET_NFLG (((uae_s16)(src)) < 0);
35142: m68k_incpc(6);
35143: fill_prefetch_0 ();
35144: put_word(dsta,src);
35145: }}}}}endlabel2170: ;
35146: return 20;
35147: }
35148: unsigned long REGPARAM2 CPUFUNC(op_79_5)(uae_u32 opcode) /* OR */
35149: {
35150: OpcodeFamily = 1; CurrentInstrCycles = 24;
35151: {{ uae_s16 src = get_iword_prefetch(2);
35152: { uaecptr dsta = get_ilong_prefetch(4);
35153: if ((dsta & 1) != 0) {
35154: last_fault_for_exception_3 = dsta;
35155: last_op_for_exception_3 = opcode;
35156: last_addr_for_exception_3 = m68k_getpc() + 8;
35157: Exception(3, 0, M68000_EXC_SRC_CPU);
35158: goto endlabel2171;
35159: }
35160: {{ uae_s16 dst = get_word(dsta);
35161: src |= dst;
35162: CLEAR_CZNV;
35163: SET_ZFLG (((uae_s16)(src)) == 0);
35164: SET_NFLG (((uae_s16)(src)) < 0);
35165: m68k_incpc(8);
35166: fill_prefetch_0 ();
35167: put_word(dsta,src);
35168: }}}}}endlabel2171: ;
35169: return 24;
35170: }
35171: unsigned long REGPARAM2 CPUFUNC(op_7c_5)(uae_u32 opcode) /* ORSR */
35172: {
35173: OpcodeFamily = 4; CurrentInstrCycles = 20;
35174: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2172; }
35175: { MakeSR();
35176: { uae_s16 src = get_iword_prefetch(2);
35177: regs.sr |= src;
35178: MakeFromSR();
35179: }}}m68k_incpc(4);
35180: fill_prefetch_0 ();
35181: endlabel2172: ;
35182: return 20;
35183: }
35184: unsigned long REGPARAM2 CPUFUNC(op_80_5)(uae_u32 opcode) /* OR */
35185: {
35186: uae_u32 dstreg = opcode & 7;
35187: OpcodeFamily = 1; CurrentInstrCycles = 16;
35188: {{ uae_s32 src = get_ilong_prefetch(2);
35189: { uae_s32 dst = m68k_dreg(regs, dstreg);
35190: src |= dst;
35191: CLEAR_CZNV;
35192: SET_ZFLG (((uae_s32)(src)) == 0);
35193: SET_NFLG (((uae_s32)(src)) < 0);
35194: m68k_dreg(regs, dstreg) = (src);
35195: }}}m68k_incpc(6);
35196: fill_prefetch_0 ();
35197: return 16;
35198: }
35199: unsigned long REGPARAM2 CPUFUNC(op_90_5)(uae_u32 opcode) /* OR */
35200: {
35201: uae_u32 dstreg = opcode & 7;
35202: OpcodeFamily = 1; CurrentInstrCycles = 28;
35203: {{ uae_s32 src = get_ilong_prefetch(2);
35204: { uaecptr dsta = m68k_areg(regs, dstreg);
35205: if ((dsta & 1) != 0) {
35206: last_fault_for_exception_3 = dsta;
35207: last_op_for_exception_3 = opcode;
35208: last_addr_for_exception_3 = m68k_getpc() + 6;
35209: Exception(3, 0, M68000_EXC_SRC_CPU);
35210: goto endlabel2174;
35211: }
35212: {{ uae_s32 dst = get_long(dsta);
35213: src |= dst;
35214: CLEAR_CZNV;
35215: SET_ZFLG (((uae_s32)(src)) == 0);
35216: SET_NFLG (((uae_s32)(src)) < 0);
35217: m68k_incpc(6);
35218: fill_prefetch_0 ();
35219: put_long(dsta,src);
35220: }}}}}endlabel2174: ;
35221: return 28;
35222: }
35223: unsigned long REGPARAM2 CPUFUNC(op_98_5)(uae_u32 opcode) /* OR */
35224: {
35225: uae_u32 dstreg = opcode & 7;
35226: OpcodeFamily = 1; CurrentInstrCycles = 28;
35227: {{ uae_s32 src = get_ilong_prefetch(2);
35228: { uaecptr dsta = m68k_areg(regs, dstreg);
35229: if ((dsta & 1) != 0) {
35230: last_fault_for_exception_3 = dsta;
35231: last_op_for_exception_3 = opcode;
35232: last_addr_for_exception_3 = m68k_getpc() + 6;
35233: Exception(3, 0, M68000_EXC_SRC_CPU);
35234: goto endlabel2175;
35235: }
35236: {{ uae_s32 dst = get_long(dsta);
35237: m68k_areg(regs, dstreg) += 4;
35238: src |= dst;
35239: CLEAR_CZNV;
35240: SET_ZFLG (((uae_s32)(src)) == 0);
35241: SET_NFLG (((uae_s32)(src)) < 0);
35242: m68k_incpc(6);
35243: fill_prefetch_0 ();
35244: put_long(dsta,src);
35245: }}}}}endlabel2175: ;
35246: return 28;
35247: }
35248: unsigned long REGPARAM2 CPUFUNC(op_a0_5)(uae_u32 opcode) /* OR */
35249: {
35250: uae_u32 dstreg = opcode & 7;
35251: OpcodeFamily = 1; CurrentInstrCycles = 30;
35252: {{ uae_s32 src = get_ilong_prefetch(2);
35253: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
35254: if ((dsta & 1) != 0) {
35255: last_fault_for_exception_3 = dsta;
35256: last_op_for_exception_3 = opcode;
35257: last_addr_for_exception_3 = m68k_getpc() + 6;
35258: Exception(3, 0, M68000_EXC_SRC_CPU);
35259: goto endlabel2176;
35260: }
35261: {{ uae_s32 dst = get_long(dsta);
35262: m68k_areg (regs, dstreg) = dsta;
35263: src |= dst;
35264: CLEAR_CZNV;
35265: SET_ZFLG (((uae_s32)(src)) == 0);
35266: SET_NFLG (((uae_s32)(src)) < 0);
35267: m68k_incpc(6);
35268: fill_prefetch_0 ();
35269: put_long(dsta,src);
35270: }}}}}endlabel2176: ;
35271: return 30;
35272: }
35273: unsigned long REGPARAM2 CPUFUNC(op_a8_5)(uae_u32 opcode) /* OR */
35274: {
35275: uae_u32 dstreg = opcode & 7;
35276: OpcodeFamily = 1; CurrentInstrCycles = 32;
35277: {{ uae_s32 src = get_ilong_prefetch(2);
35278: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
35279: if ((dsta & 1) != 0) {
35280: last_fault_for_exception_3 = dsta;
35281: last_op_for_exception_3 = opcode;
35282: last_addr_for_exception_3 = m68k_getpc() + 8;
35283: Exception(3, 0, M68000_EXC_SRC_CPU);
35284: goto endlabel2177;
35285: }
35286: {{ uae_s32 dst = get_long(dsta);
35287: src |= dst;
35288: CLEAR_CZNV;
35289: SET_ZFLG (((uae_s32)(src)) == 0);
35290: SET_NFLG (((uae_s32)(src)) < 0);
35291: m68k_incpc(8);
35292: fill_prefetch_0 ();
35293: put_long(dsta,src);
35294: }}}}}endlabel2177: ;
35295: return 32;
35296: }
35297: unsigned long REGPARAM2 CPUFUNC(op_b0_5)(uae_u32 opcode) /* OR */
35298: {
35299: uae_u32 dstreg = opcode & 7;
35300: OpcodeFamily = 1; CurrentInstrCycles = 34;
35301: {{ uae_s32 src = get_ilong_prefetch(2);
35302: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
35303: BusCyclePenalty += 2;
35304: if ((dsta & 1) != 0) {
35305: last_fault_for_exception_3 = dsta;
35306: last_op_for_exception_3 = opcode;
35307: last_addr_for_exception_3 = m68k_getpc() + 8;
35308: Exception(3, 0, M68000_EXC_SRC_CPU);
35309: goto endlabel2178;
35310: }
35311: {{ uae_s32 dst = get_long(dsta);
35312: src |= dst;
35313: CLEAR_CZNV;
35314: SET_ZFLG (((uae_s32)(src)) == 0);
35315: SET_NFLG (((uae_s32)(src)) < 0);
35316: m68k_incpc(8);
35317: fill_prefetch_0 ();
35318: put_long(dsta,src);
35319: }}}}}endlabel2178: ;
35320: return 34;
35321: }
35322: unsigned long REGPARAM2 CPUFUNC(op_b8_5)(uae_u32 opcode) /* OR */
35323: {
35324: OpcodeFamily = 1; CurrentInstrCycles = 32;
35325: {{ uae_s32 src = get_ilong_prefetch(2);
35326: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
35327: if ((dsta & 1) != 0) {
35328: last_fault_for_exception_3 = dsta;
35329: last_op_for_exception_3 = opcode;
35330: last_addr_for_exception_3 = m68k_getpc() + 8;
35331: Exception(3, 0, M68000_EXC_SRC_CPU);
35332: goto endlabel2179;
35333: }
35334: {{ uae_s32 dst = get_long(dsta);
35335: src |= dst;
35336: CLEAR_CZNV;
35337: SET_ZFLG (((uae_s32)(src)) == 0);
35338: SET_NFLG (((uae_s32)(src)) < 0);
35339: m68k_incpc(8);
35340: fill_prefetch_0 ();
35341: put_long(dsta,src);
35342: }}}}}endlabel2179: ;
35343: return 32;
35344: }
35345: unsigned long REGPARAM2 CPUFUNC(op_b9_5)(uae_u32 opcode) /* OR */
35346: {
35347: OpcodeFamily = 1; CurrentInstrCycles = 36;
35348: {{ uae_s32 src = get_ilong_prefetch(2);
35349: { uaecptr dsta = get_ilong_prefetch(6);
35350: if ((dsta & 1) != 0) {
35351: last_fault_for_exception_3 = dsta;
35352: last_op_for_exception_3 = opcode;
35353: last_addr_for_exception_3 = m68k_getpc() + 10;
35354: Exception(3, 0, M68000_EXC_SRC_CPU);
35355: goto endlabel2180;
35356: }
35357: {{ uae_s32 dst = get_long(dsta);
35358: src |= dst;
35359: CLEAR_CZNV;
35360: SET_ZFLG (((uae_s32)(src)) == 0);
35361: SET_NFLG (((uae_s32)(src)) < 0);
35362: m68k_incpc(10);
35363: fill_prefetch_0 ();
35364: put_long(dsta,src);
35365: }}}}}endlabel2180: ;
35366: return 36;
35367: }
35368: unsigned long REGPARAM2 CPUFUNC(op_100_5)(uae_u32 opcode) /* BTST */
35369: {
35370: uae_u32 srcreg = ((opcode >> 9) & 7);
35371: uae_u32 dstreg = opcode & 7;
35372: OpcodeFamily = 21; CurrentInstrCycles = 6;
35373: {{ uae_s32 src = m68k_dreg(regs, srcreg);
35374: { uae_s32 dst = m68k_dreg(regs, dstreg);
35375: src &= 31;
35376: SET_ZFLG (1 ^ ((dst >> src) & 1));
35377: }}}m68k_incpc(2);
35378: fill_prefetch_2 ();
35379: return 6;
35380: }
35381: unsigned long REGPARAM2 CPUFUNC(op_108_5)(uae_u32 opcode) /* MVPMR */
35382: {
35383: uae_u32 srcreg = (opcode & 7);
35384: uae_u32 dstreg = (opcode >> 9) & 7;
35385: OpcodeFamily = 29; CurrentInstrCycles = 16;
35386: { uaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
35387: { uae_u16 val = (get_byte(memp) << 8) + get_byte(memp + 2);
35388: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
35389: }}m68k_incpc(4);
35390: fill_prefetch_0 ();
35391: return 16;
35392: }
35393: unsigned long REGPARAM2 CPUFUNC(op_110_5)(uae_u32 opcode) /* BTST */
35394: {
35395: uae_u32 srcreg = ((opcode >> 9) & 7);
35396: uae_u32 dstreg = opcode & 7;
35397: OpcodeFamily = 21; CurrentInstrCycles = 8;
35398: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35399: { uaecptr dsta = m68k_areg(regs, dstreg);
35400: { uae_s8 dst = get_byte(dsta);
35401: src &= 7;
35402: SET_ZFLG (1 ^ ((dst >> src) & 1));
35403: }}}}m68k_incpc(2);
35404: fill_prefetch_2 ();
35405: return 8;
35406: }
35407: unsigned long REGPARAM2 CPUFUNC(op_118_5)(uae_u32 opcode) /* BTST */
35408: {
35409: uae_u32 srcreg = ((opcode >> 9) & 7);
35410: uae_u32 dstreg = opcode & 7;
35411: OpcodeFamily = 21; CurrentInstrCycles = 8;
35412: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35413: { uaecptr dsta = m68k_areg(regs, dstreg);
35414: { uae_s8 dst = get_byte(dsta);
35415: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
35416: src &= 7;
35417: SET_ZFLG (1 ^ ((dst >> src) & 1));
35418: }}}}m68k_incpc(2);
35419: fill_prefetch_2 ();
35420: return 8;
35421: }
35422: unsigned long REGPARAM2 CPUFUNC(op_120_5)(uae_u32 opcode) /* BTST */
35423: {
35424: uae_u32 srcreg = ((opcode >> 9) & 7);
35425: uae_u32 dstreg = opcode & 7;
35426: OpcodeFamily = 21; CurrentInstrCycles = 10;
35427: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35428: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
35429: { uae_s8 dst = get_byte(dsta);
35430: m68k_areg (regs, dstreg) = dsta;
35431: src &= 7;
35432: SET_ZFLG (1 ^ ((dst >> src) & 1));
35433: }}}}m68k_incpc(2);
35434: fill_prefetch_2 ();
35435: return 10;
35436: }
35437: unsigned long REGPARAM2 CPUFUNC(op_128_5)(uae_u32 opcode) /* BTST */
35438: {
35439: uae_u32 srcreg = ((opcode >> 9) & 7);
35440: uae_u32 dstreg = opcode & 7;
35441: OpcodeFamily = 21; CurrentInstrCycles = 12;
35442: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35443: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
35444: { uae_s8 dst = get_byte(dsta);
35445: src &= 7;
35446: SET_ZFLG (1 ^ ((dst >> src) & 1));
35447: }}}}m68k_incpc(4);
35448: fill_prefetch_0 ();
35449: return 12;
35450: }
35451: unsigned long REGPARAM2 CPUFUNC(op_130_5)(uae_u32 opcode) /* BTST */
35452: {
35453: uae_u32 srcreg = ((opcode >> 9) & 7);
35454: uae_u32 dstreg = opcode & 7;
35455: OpcodeFamily = 21; CurrentInstrCycles = 14;
35456: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35457: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
35458: BusCyclePenalty += 2;
35459: { uae_s8 dst = get_byte(dsta);
35460: src &= 7;
35461: SET_ZFLG (1 ^ ((dst >> src) & 1));
35462: }}}}m68k_incpc(4);
35463: fill_prefetch_0 ();
35464: return 14;
35465: }
35466: unsigned long REGPARAM2 CPUFUNC(op_138_5)(uae_u32 opcode) /* BTST */
35467: {
35468: uae_u32 srcreg = ((opcode >> 9) & 7);
35469: OpcodeFamily = 21; CurrentInstrCycles = 12;
35470: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35471: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
35472: { uae_s8 dst = get_byte(dsta);
35473: src &= 7;
35474: SET_ZFLG (1 ^ ((dst >> src) & 1));
35475: }}}}m68k_incpc(4);
35476: fill_prefetch_0 ();
35477: return 12;
35478: }
35479: unsigned long REGPARAM2 CPUFUNC(op_139_5)(uae_u32 opcode) /* BTST */
35480: {
35481: uae_u32 srcreg = ((opcode >> 9) & 7);
35482: OpcodeFamily = 21; CurrentInstrCycles = 16;
35483: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35484: { uaecptr dsta = get_ilong_prefetch(2);
35485: { uae_s8 dst = get_byte(dsta);
35486: src &= 7;
35487: SET_ZFLG (1 ^ ((dst >> src) & 1));
35488: }}}}m68k_incpc(6);
35489: fill_prefetch_0 ();
35490: return 16;
35491: }
35492: unsigned long REGPARAM2 CPUFUNC(op_13a_5)(uae_u32 opcode) /* BTST */
35493: {
35494: uae_u32 srcreg = ((opcode >> 9) & 7);
35495: uae_u32 dstreg = 2;
35496: OpcodeFamily = 21; CurrentInstrCycles = 12;
35497: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35498: { uaecptr dsta = m68k_getpc () + 2;
35499: dsta += (uae_s32)(uae_s16)get_iword_prefetch(2);
35500: { uae_s8 dst = get_byte(dsta);
35501: src &= 7;
35502: SET_ZFLG (1 ^ ((dst >> src) & 1));
35503: }}}}m68k_incpc(4);
35504: fill_prefetch_0 ();
35505: return 12;
35506: }
35507: unsigned long REGPARAM2 CPUFUNC(op_13b_5)(uae_u32 opcode) /* BTST */
35508: {
35509: uae_u32 srcreg = ((opcode >> 9) & 7);
35510: uae_u32 dstreg = 3;
35511: OpcodeFamily = 21; CurrentInstrCycles = 14;
35512: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35513: { uaecptr tmppc = m68k_getpc() + 2;
35514: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2));
35515: BusCyclePenalty += 2;
35516: { uae_s8 dst = get_byte(dsta);
35517: src &= 7;
35518: SET_ZFLG (1 ^ ((dst >> src) & 1));
35519: }}}}m68k_incpc(4);
35520: fill_prefetch_0 ();
35521: return 14;
35522: }
35523: unsigned long REGPARAM2 CPUFUNC(op_13c_5)(uae_u32 opcode) /* BTST */
35524: {
35525: uae_u32 srcreg = ((opcode >> 9) & 7);
35526: OpcodeFamily = 21; CurrentInstrCycles = 8;
35527: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35528: { uae_s8 dst = get_ibyte_prefetch(2);
35529: src &= 7;
35530: SET_ZFLG (1 ^ ((dst >> src) & 1));
35531: }}}m68k_incpc(4);
35532: fill_prefetch_0 ();
35533: return 8;
35534: }
35535: unsigned long REGPARAM2 CPUFUNC(op_140_5)(uae_u32 opcode) /* BCHG */
35536: {
35537: uae_u32 srcreg = ((opcode >> 9) & 7);
35538: uae_u32 dstreg = opcode & 7;
35539: OpcodeFamily = 22; CurrentInstrCycles = 8;
35540: {{ uae_s32 src = m68k_dreg(regs, srcreg);
35541: { uae_s32 dst = m68k_dreg(regs, dstreg);
35542: src &= 31;
35543: dst ^= (1 << src);
35544: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35545: m68k_dreg(regs, dstreg) = (dst);
35546: }}}m68k_incpc(2);
35547: fill_prefetch_2 ();
35548: return 8;
35549: }
35550: unsigned long REGPARAM2 CPUFUNC(op_148_5)(uae_u32 opcode) /* MVPMR */
35551: {
35552: uae_u32 srcreg = (opcode & 7);
35553: uae_u32 dstreg = (opcode >> 9) & 7;
35554: OpcodeFamily = 29; CurrentInstrCycles = 24;
35555: { uaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
35556: { uae_u32 val = (get_byte(memp) << 24) + (get_byte(memp + 2) << 16)
35557: + (get_byte(memp + 4) << 8) + get_byte(memp + 6);
35558: m68k_dreg(regs, dstreg) = (val);
35559: }}m68k_incpc(4);
35560: fill_prefetch_0 ();
35561: return 24;
35562: }
35563: unsigned long REGPARAM2 CPUFUNC(op_150_5)(uae_u32 opcode) /* BCHG */
35564: {
35565: uae_u32 srcreg = ((opcode >> 9) & 7);
35566: uae_u32 dstreg = opcode & 7;
35567: OpcodeFamily = 22; CurrentInstrCycles = 12;
35568: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35569: { uaecptr dsta = m68k_areg(regs, dstreg);
35570: { uae_s8 dst = get_byte(dsta);
35571: src &= 7;
35572: dst ^= (1 << src);
35573: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35574: m68k_incpc(2);
35575: fill_prefetch_2 ();
35576: put_byte(dsta,dst);
35577: }}}}return 12;
35578: }
35579: unsigned long REGPARAM2 CPUFUNC(op_158_5)(uae_u32 opcode) /* BCHG */
35580: {
35581: uae_u32 srcreg = ((opcode >> 9) & 7);
35582: uae_u32 dstreg = opcode & 7;
35583: OpcodeFamily = 22; CurrentInstrCycles = 12;
35584: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35585: { uaecptr dsta = m68k_areg(regs, dstreg);
35586: { uae_s8 dst = get_byte(dsta);
35587: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
35588: src &= 7;
35589: dst ^= (1 << src);
35590: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35591: m68k_incpc(2);
35592: fill_prefetch_2 ();
35593: put_byte(dsta,dst);
35594: }}}}return 12;
35595: }
35596: unsigned long REGPARAM2 CPUFUNC(op_160_5)(uae_u32 opcode) /* BCHG */
35597: {
35598: uae_u32 srcreg = ((opcode >> 9) & 7);
35599: uae_u32 dstreg = opcode & 7;
35600: OpcodeFamily = 22; CurrentInstrCycles = 14;
35601: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35602: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
35603: { uae_s8 dst = get_byte(dsta);
35604: m68k_areg (regs, dstreg) = dsta;
35605: src &= 7;
35606: dst ^= (1 << src);
35607: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35608: m68k_incpc(2);
35609: fill_prefetch_2 ();
35610: put_byte(dsta,dst);
35611: }}}}return 14;
35612: }
35613: unsigned long REGPARAM2 CPUFUNC(op_168_5)(uae_u32 opcode) /* BCHG */
35614: {
35615: uae_u32 srcreg = ((opcode >> 9) & 7);
35616: uae_u32 dstreg = opcode & 7;
35617: OpcodeFamily = 22; CurrentInstrCycles = 16;
35618: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35619: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
35620: { uae_s8 dst = get_byte(dsta);
35621: src &= 7;
35622: dst ^= (1 << src);
35623: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35624: m68k_incpc(4);
35625: fill_prefetch_0 ();
35626: put_byte(dsta,dst);
35627: }}}}return 16;
35628: }
35629: unsigned long REGPARAM2 CPUFUNC(op_170_5)(uae_u32 opcode) /* BCHG */
35630: {
35631: uae_u32 srcreg = ((opcode >> 9) & 7);
35632: uae_u32 dstreg = opcode & 7;
35633: OpcodeFamily = 22; CurrentInstrCycles = 18;
35634: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35635: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
35636: BusCyclePenalty += 2;
35637: { uae_s8 dst = get_byte(dsta);
35638: src &= 7;
35639: dst ^= (1 << src);
35640: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35641: m68k_incpc(4);
35642: fill_prefetch_0 ();
35643: put_byte(dsta,dst);
35644: }}}}return 18;
35645: }
35646: unsigned long REGPARAM2 CPUFUNC(op_178_5)(uae_u32 opcode) /* BCHG */
35647: {
35648: uae_u32 srcreg = ((opcode >> 9) & 7);
35649: OpcodeFamily = 22; CurrentInstrCycles = 16;
35650: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35651: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
35652: { uae_s8 dst = get_byte(dsta);
35653: src &= 7;
35654: dst ^= (1 << src);
35655: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35656: m68k_incpc(4);
35657: fill_prefetch_0 ();
35658: put_byte(dsta,dst);
35659: }}}}return 16;
35660: }
35661: unsigned long REGPARAM2 CPUFUNC(op_179_5)(uae_u32 opcode) /* BCHG */
35662: {
35663: uae_u32 srcreg = ((opcode >> 9) & 7);
35664: OpcodeFamily = 22; CurrentInstrCycles = 20;
35665: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35666: { uaecptr dsta = get_ilong_prefetch(2);
35667: { uae_s8 dst = get_byte(dsta);
35668: src &= 7;
35669: dst ^= (1 << src);
35670: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35671: m68k_incpc(6);
35672: fill_prefetch_0 ();
35673: put_byte(dsta,dst);
35674: }}}}return 20;
35675: }
35676: unsigned long REGPARAM2 CPUFUNC(op_17a_5)(uae_u32 opcode) /* BCHG */
35677: {
35678: uae_u32 srcreg = ((opcode >> 9) & 7);
35679: uae_u32 dstreg = 2;
35680: OpcodeFamily = 22; CurrentInstrCycles = 16;
35681: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35682: { uaecptr dsta = m68k_getpc () + 2;
35683: dsta += (uae_s32)(uae_s16)get_iword_prefetch(2);
35684: { uae_s8 dst = get_byte(dsta);
35685: src &= 7;
35686: dst ^= (1 << src);
35687: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35688: m68k_incpc(4);
35689: fill_prefetch_0 ();
35690: put_byte(dsta,dst);
35691: }}}}return 16;
35692: }
35693: unsigned long REGPARAM2 CPUFUNC(op_17b_5)(uae_u32 opcode) /* BCHG */
35694: {
35695: uae_u32 srcreg = ((opcode >> 9) & 7);
35696: uae_u32 dstreg = 3;
35697: OpcodeFamily = 22; CurrentInstrCycles = 18;
35698: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35699: { uaecptr tmppc = m68k_getpc() + 2;
35700: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2));
35701: BusCyclePenalty += 2;
35702: { uae_s8 dst = get_byte(dsta);
35703: src &= 7;
35704: dst ^= (1 << src);
35705: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
35706: m68k_incpc(4);
35707: fill_prefetch_0 ();
35708: put_byte(dsta,dst);
35709: }}}}return 18;
35710: }
35711: unsigned long REGPARAM2 CPUFUNC(op_180_5)(uae_u32 opcode) /* BCLR */
35712: {
35713: uae_u32 srcreg = ((opcode >> 9) & 7);
35714: uae_u32 dstreg = opcode & 7;
35715: OpcodeFamily = 23; CurrentInstrCycles = 10;
35716: {{ uae_s32 src = m68k_dreg(regs, srcreg);
35717: { uae_s32 dst = m68k_dreg(regs, dstreg);
35718: src &= 31;
35719: SET_ZFLG (1 ^ ((dst >> src) & 1));
35720: dst &= ~(1 << src);
35721: m68k_dreg(regs, dstreg) = (dst);
35722: if ( src < 16 ) { m68k_incpc(2); return 8; }
35723: }}}m68k_incpc(2);
35724: fill_prefetch_2 ();
35725: return 10;
35726: }
35727: unsigned long REGPARAM2 CPUFUNC(op_188_5)(uae_u32 opcode) /* MVPRM */
35728: {
35729: uae_u32 srcreg = ((opcode >> 9) & 7);
35730: uae_u32 dstreg = opcode & 7;
35731: OpcodeFamily = 28; CurrentInstrCycles = 16;
35732: {{ uae_s16 src = m68k_dreg(regs, srcreg);
35733: uaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
35734: put_byte(memp, src >> 8); put_byte(memp + 2, src);
35735: }}m68k_incpc(4);
35736: fill_prefetch_0 ();
35737: return 16;
35738: }
35739: unsigned long REGPARAM2 CPUFUNC(op_190_5)(uae_u32 opcode) /* BCLR */
35740: {
35741: uae_u32 srcreg = ((opcode >> 9) & 7);
35742: uae_u32 dstreg = opcode & 7;
35743: OpcodeFamily = 23; CurrentInstrCycles = 12;
35744: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35745: { uaecptr dsta = m68k_areg(regs, dstreg);
35746: { uae_s8 dst = get_byte(dsta);
35747: src &= 7;
35748: SET_ZFLG (1 ^ ((dst >> src) & 1));
35749: dst &= ~(1 << src);
35750: m68k_incpc(2);
35751: fill_prefetch_2 ();
35752: put_byte(dsta,dst);
35753: }}}}return 12;
35754: }
35755: unsigned long REGPARAM2 CPUFUNC(op_198_5)(uae_u32 opcode) /* BCLR */
35756: {
35757: uae_u32 srcreg = ((opcode >> 9) & 7);
35758: uae_u32 dstreg = opcode & 7;
35759: OpcodeFamily = 23; CurrentInstrCycles = 12;
35760: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35761: { uaecptr dsta = m68k_areg(regs, dstreg);
35762: { uae_s8 dst = get_byte(dsta);
35763: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
35764: src &= 7;
35765: SET_ZFLG (1 ^ ((dst >> src) & 1));
35766: dst &= ~(1 << src);
35767: m68k_incpc(2);
35768: fill_prefetch_2 ();
35769: put_byte(dsta,dst);
35770: }}}}return 12;
35771: }
35772: unsigned long REGPARAM2 CPUFUNC(op_1a0_5)(uae_u32 opcode) /* BCLR */
35773: {
35774: uae_u32 srcreg = ((opcode >> 9) & 7);
35775: uae_u32 dstreg = opcode & 7;
35776: OpcodeFamily = 23; CurrentInstrCycles = 14;
35777: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35778: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
35779: { uae_s8 dst = get_byte(dsta);
35780: m68k_areg (regs, dstreg) = dsta;
35781: src &= 7;
35782: SET_ZFLG (1 ^ ((dst >> src) & 1));
35783: dst &= ~(1 << src);
35784: m68k_incpc(2);
35785: fill_prefetch_2 ();
35786: put_byte(dsta,dst);
35787: }}}}return 14;
35788: }
35789: unsigned long REGPARAM2 CPUFUNC(op_1a8_5)(uae_u32 opcode) /* BCLR */
35790: {
35791: uae_u32 srcreg = ((opcode >> 9) & 7);
35792: uae_u32 dstreg = opcode & 7;
35793: OpcodeFamily = 23; CurrentInstrCycles = 16;
35794: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35795: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
35796: { uae_s8 dst = get_byte(dsta);
35797: src &= 7;
35798: SET_ZFLG (1 ^ ((dst >> src) & 1));
35799: dst &= ~(1 << src);
35800: m68k_incpc(4);
35801: fill_prefetch_0 ();
35802: put_byte(dsta,dst);
35803: }}}}return 16;
35804: }
35805: unsigned long REGPARAM2 CPUFUNC(op_1b0_5)(uae_u32 opcode) /* BCLR */
35806: {
35807: uae_u32 srcreg = ((opcode >> 9) & 7);
35808: uae_u32 dstreg = opcode & 7;
35809: OpcodeFamily = 23; CurrentInstrCycles = 18;
35810: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35811: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
35812: BusCyclePenalty += 2;
35813: { uae_s8 dst = get_byte(dsta);
35814: src &= 7;
35815: SET_ZFLG (1 ^ ((dst >> src) & 1));
35816: dst &= ~(1 << src);
35817: m68k_incpc(4);
35818: fill_prefetch_0 ();
35819: put_byte(dsta,dst);
35820: }}}}return 18;
35821: }
35822: unsigned long REGPARAM2 CPUFUNC(op_1b8_5)(uae_u32 opcode) /* BCLR */
35823: {
35824: uae_u32 srcreg = ((opcode >> 9) & 7);
35825: OpcodeFamily = 23; CurrentInstrCycles = 16;
35826: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35827: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
35828: { uae_s8 dst = get_byte(dsta);
35829: src &= 7;
35830: SET_ZFLG (1 ^ ((dst >> src) & 1));
35831: dst &= ~(1 << src);
35832: m68k_incpc(4);
35833: fill_prefetch_0 ();
35834: put_byte(dsta,dst);
35835: }}}}return 16;
35836: }
35837: unsigned long REGPARAM2 CPUFUNC(op_1b9_5)(uae_u32 opcode) /* BCLR */
35838: {
35839: uae_u32 srcreg = ((opcode >> 9) & 7);
35840: OpcodeFamily = 23; CurrentInstrCycles = 20;
35841: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35842: { uaecptr dsta = get_ilong_prefetch(2);
35843: { uae_s8 dst = get_byte(dsta);
35844: src &= 7;
35845: SET_ZFLG (1 ^ ((dst >> src) & 1));
35846: dst &= ~(1 << src);
35847: m68k_incpc(6);
35848: fill_prefetch_0 ();
35849: put_byte(dsta,dst);
35850: }}}}return 20;
35851: }
35852: unsigned long REGPARAM2 CPUFUNC(op_1ba_5)(uae_u32 opcode) /* BCLR */
35853: {
35854: uae_u32 srcreg = ((opcode >> 9) & 7);
35855: uae_u32 dstreg = 2;
35856: OpcodeFamily = 23; CurrentInstrCycles = 16;
35857: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35858: { uaecptr dsta = m68k_getpc () + 2;
35859: dsta += (uae_s32)(uae_s16)get_iword_prefetch(2);
35860: { uae_s8 dst = get_byte(dsta);
35861: src &= 7;
35862: SET_ZFLG (1 ^ ((dst >> src) & 1));
35863: dst &= ~(1 << src);
35864: m68k_incpc(4);
35865: fill_prefetch_0 ();
35866: put_byte(dsta,dst);
35867: }}}}return 16;
35868: }
35869: unsigned long REGPARAM2 CPUFUNC(op_1bb_5)(uae_u32 opcode) /* BCLR */
35870: {
35871: uae_u32 srcreg = ((opcode >> 9) & 7);
35872: uae_u32 dstreg = 3;
35873: OpcodeFamily = 23; CurrentInstrCycles = 18;
35874: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35875: { uaecptr tmppc = m68k_getpc() + 2;
35876: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2));
35877: BusCyclePenalty += 2;
35878: { uae_s8 dst = get_byte(dsta);
35879: src &= 7;
35880: SET_ZFLG (1 ^ ((dst >> src) & 1));
35881: dst &= ~(1 << src);
35882: m68k_incpc(4);
35883: fill_prefetch_0 ();
35884: put_byte(dsta,dst);
35885: }}}}return 18;
35886: }
35887: unsigned long REGPARAM2 CPUFUNC(op_1c0_5)(uae_u32 opcode) /* BSET */
35888: {
35889: uae_u32 srcreg = ((opcode >> 9) & 7);
35890: uae_u32 dstreg = opcode & 7;
35891: OpcodeFamily = 24; CurrentInstrCycles = 8;
35892: {{ uae_s32 src = m68k_dreg(regs, srcreg);
35893: { uae_s32 dst = m68k_dreg(regs, dstreg);
35894: src &= 31;
35895: SET_ZFLG (1 ^ ((dst >> src) & 1));
35896: dst |= (1 << src);
35897: m68k_dreg(regs, dstreg) = (dst);
35898: }}}m68k_incpc(2);
35899: fill_prefetch_2 ();
35900: return 8;
35901: }
35902: unsigned long REGPARAM2 CPUFUNC(op_1c8_5)(uae_u32 opcode) /* MVPRM */
35903: {
35904: uae_u32 srcreg = ((opcode >> 9) & 7);
35905: uae_u32 dstreg = opcode & 7;
35906: OpcodeFamily = 28; CurrentInstrCycles = 24;
35907: {{ uae_s32 src = m68k_dreg(regs, srcreg);
35908: uaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
35909: put_byte(memp, src >> 24); put_byte(memp + 2, src >> 16);
35910: put_byte(memp + 4, src >> 8); put_byte(memp + 6, src);
35911: }}m68k_incpc(4);
35912: fill_prefetch_0 ();
35913: return 24;
35914: }
35915: unsigned long REGPARAM2 CPUFUNC(op_1d0_5)(uae_u32 opcode) /* BSET */
35916: {
35917: uae_u32 srcreg = ((opcode >> 9) & 7);
35918: uae_u32 dstreg = opcode & 7;
35919: OpcodeFamily = 24; CurrentInstrCycles = 12;
35920: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35921: { uaecptr dsta = m68k_areg(regs, dstreg);
35922: { uae_s8 dst = get_byte(dsta);
35923: src &= 7;
35924: SET_ZFLG (1 ^ ((dst >> src) & 1));
35925: dst |= (1 << src);
35926: m68k_incpc(2);
35927: fill_prefetch_2 ();
35928: put_byte(dsta,dst);
35929: }}}}return 12;
35930: }
35931: unsigned long REGPARAM2 CPUFUNC(op_1d8_5)(uae_u32 opcode) /* BSET */
35932: {
35933: uae_u32 srcreg = ((opcode >> 9) & 7);
35934: uae_u32 dstreg = opcode & 7;
35935: OpcodeFamily = 24; CurrentInstrCycles = 12;
35936: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35937: { uaecptr dsta = m68k_areg(regs, dstreg);
35938: { uae_s8 dst = get_byte(dsta);
35939: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
35940: src &= 7;
35941: SET_ZFLG (1 ^ ((dst >> src) & 1));
35942: dst |= (1 << src);
35943: m68k_incpc(2);
35944: fill_prefetch_2 ();
35945: put_byte(dsta,dst);
35946: }}}}return 12;
35947: }
35948: unsigned long REGPARAM2 CPUFUNC(op_1e0_5)(uae_u32 opcode) /* BSET */
35949: {
35950: uae_u32 srcreg = ((opcode >> 9) & 7);
35951: uae_u32 dstreg = opcode & 7;
35952: OpcodeFamily = 24; CurrentInstrCycles = 14;
35953: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35954: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
35955: { uae_s8 dst = get_byte(dsta);
35956: m68k_areg (regs, dstreg) = dsta;
35957: src &= 7;
35958: SET_ZFLG (1 ^ ((dst >> src) & 1));
35959: dst |= (1 << src);
35960: m68k_incpc(2);
35961: fill_prefetch_2 ();
35962: put_byte(dsta,dst);
35963: }}}}return 14;
35964: }
35965: unsigned long REGPARAM2 CPUFUNC(op_1e8_5)(uae_u32 opcode) /* BSET */
35966: {
35967: uae_u32 srcreg = ((opcode >> 9) & 7);
35968: uae_u32 dstreg = opcode & 7;
35969: OpcodeFamily = 24; CurrentInstrCycles = 16;
35970: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35971: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
35972: { uae_s8 dst = get_byte(dsta);
35973: src &= 7;
35974: SET_ZFLG (1 ^ ((dst >> src) & 1));
35975: dst |= (1 << src);
35976: m68k_incpc(4);
35977: fill_prefetch_0 ();
35978: put_byte(dsta,dst);
35979: }}}}return 16;
35980: }
35981: unsigned long REGPARAM2 CPUFUNC(op_1f0_5)(uae_u32 opcode) /* BSET */
35982: {
35983: uae_u32 srcreg = ((opcode >> 9) & 7);
35984: uae_u32 dstreg = opcode & 7;
35985: OpcodeFamily = 24; CurrentInstrCycles = 18;
35986: {{ uae_s8 src = m68k_dreg(regs, srcreg);
35987: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
35988: BusCyclePenalty += 2;
35989: { uae_s8 dst = get_byte(dsta);
35990: src &= 7;
35991: SET_ZFLG (1 ^ ((dst >> src) & 1));
35992: dst |= (1 << src);
35993: m68k_incpc(4);
35994: fill_prefetch_0 ();
35995: put_byte(dsta,dst);
35996: }}}}return 18;
35997: }
35998: unsigned long REGPARAM2 CPUFUNC(op_1f8_5)(uae_u32 opcode) /* BSET */
35999: {
36000: uae_u32 srcreg = ((opcode >> 9) & 7);
36001: OpcodeFamily = 24; CurrentInstrCycles = 16;
36002: {{ uae_s8 src = m68k_dreg(regs, srcreg);
36003: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
36004: { uae_s8 dst = get_byte(dsta);
36005: src &= 7;
36006: SET_ZFLG (1 ^ ((dst >> src) & 1));
36007: dst |= (1 << src);
36008: m68k_incpc(4);
36009: fill_prefetch_0 ();
36010: put_byte(dsta,dst);
36011: }}}}return 16;
36012: }
36013: unsigned long REGPARAM2 CPUFUNC(op_1f9_5)(uae_u32 opcode) /* BSET */
36014: {
36015: uae_u32 srcreg = ((opcode >> 9) & 7);
36016: OpcodeFamily = 24; CurrentInstrCycles = 20;
36017: {{ uae_s8 src = m68k_dreg(regs, srcreg);
36018: { uaecptr dsta = get_ilong_prefetch(2);
36019: { uae_s8 dst = get_byte(dsta);
36020: src &= 7;
36021: SET_ZFLG (1 ^ ((dst >> src) & 1));
36022: dst |= (1 << src);
36023: m68k_incpc(6);
36024: fill_prefetch_0 ();
36025: put_byte(dsta,dst);
36026: }}}}return 20;
36027: }
36028: unsigned long REGPARAM2 CPUFUNC(op_1fa_5)(uae_u32 opcode) /* BSET */
36029: {
36030: uae_u32 srcreg = ((opcode >> 9) & 7);
36031: uae_u32 dstreg = 2;
36032: OpcodeFamily = 24; CurrentInstrCycles = 16;
36033: {{ uae_s8 src = m68k_dreg(regs, srcreg);
36034: { uaecptr dsta = m68k_getpc () + 2;
36035: dsta += (uae_s32)(uae_s16)get_iword_prefetch(2);
36036: { uae_s8 dst = get_byte(dsta);
36037: src &= 7;
36038: SET_ZFLG (1 ^ ((dst >> src) & 1));
36039: dst |= (1 << src);
36040: m68k_incpc(4);
36041: fill_prefetch_0 ();
36042: put_byte(dsta,dst);
36043: }}}}return 16;
36044: }
36045: unsigned long REGPARAM2 CPUFUNC(op_1fb_5)(uae_u32 opcode) /* BSET */
36046: {
36047: uae_u32 srcreg = ((opcode >> 9) & 7);
36048: uae_u32 dstreg = 3;
36049: OpcodeFamily = 24; CurrentInstrCycles = 18;
36050: {{ uae_s8 src = m68k_dreg(regs, srcreg);
36051: { uaecptr tmppc = m68k_getpc() + 2;
36052: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2));
36053: BusCyclePenalty += 2;
36054: { uae_s8 dst = get_byte(dsta);
36055: src &= 7;
36056: SET_ZFLG (1 ^ ((dst >> src) & 1));
36057: dst |= (1 << src);
36058: m68k_incpc(4);
36059: fill_prefetch_0 ();
36060: put_byte(dsta,dst);
36061: }}}}return 18;
36062: }
36063: unsigned long REGPARAM2 CPUFUNC(op_200_5)(uae_u32 opcode) /* AND */
36064: {
36065: uae_u32 dstreg = opcode & 7;
36066: OpcodeFamily = 2; CurrentInstrCycles = 8;
36067: {{ uae_s8 src = get_ibyte_prefetch(2);
36068: { uae_s8 dst = m68k_dreg(regs, dstreg);
36069: src &= dst;
36070: CLEAR_CZNV;
36071: SET_ZFLG (((uae_s8)(src)) == 0);
36072: SET_NFLG (((uae_s8)(src)) < 0);
36073: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
36074: }}}m68k_incpc(4);
36075: fill_prefetch_0 ();
36076: return 8;
36077: }
36078: unsigned long REGPARAM2 CPUFUNC(op_210_5)(uae_u32 opcode) /* AND */
36079: {
36080: uae_u32 dstreg = opcode & 7;
36081: OpcodeFamily = 2; CurrentInstrCycles = 16;
36082: {{ uae_s8 src = get_ibyte_prefetch(2);
36083: { uaecptr dsta = m68k_areg(regs, dstreg);
36084: { uae_s8 dst = get_byte(dsta);
36085: src &= dst;
36086: CLEAR_CZNV;
36087: SET_ZFLG (((uae_s8)(src)) == 0);
36088: SET_NFLG (((uae_s8)(src)) < 0);
36089: m68k_incpc(4);
36090: fill_prefetch_0 ();
36091: put_byte(dsta,src);
36092: }}}}return 16;
36093: }
36094: unsigned long REGPARAM2 CPUFUNC(op_218_5)(uae_u32 opcode) /* AND */
36095: {
36096: uae_u32 dstreg = opcode & 7;
36097: OpcodeFamily = 2; CurrentInstrCycles = 16;
36098: {{ uae_s8 src = get_ibyte_prefetch(2);
36099: { uaecptr dsta = m68k_areg(regs, dstreg);
36100: { uae_s8 dst = get_byte(dsta);
36101: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
36102: src &= dst;
36103: CLEAR_CZNV;
36104: SET_ZFLG (((uae_s8)(src)) == 0);
36105: SET_NFLG (((uae_s8)(src)) < 0);
36106: m68k_incpc(4);
36107: fill_prefetch_0 ();
36108: put_byte(dsta,src);
36109: }}}}return 16;
36110: }
36111: unsigned long REGPARAM2 CPUFUNC(op_220_5)(uae_u32 opcode) /* AND */
36112: {
36113: uae_u32 dstreg = opcode & 7;
36114: OpcodeFamily = 2; CurrentInstrCycles = 18;
36115: {{ uae_s8 src = get_ibyte_prefetch(2);
36116: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
36117: { uae_s8 dst = get_byte(dsta);
36118: m68k_areg (regs, dstreg) = dsta;
36119: src &= dst;
36120: CLEAR_CZNV;
36121: SET_ZFLG (((uae_s8)(src)) == 0);
36122: SET_NFLG (((uae_s8)(src)) < 0);
36123: m68k_incpc(4);
36124: fill_prefetch_0 ();
36125: put_byte(dsta,src);
36126: }}}}return 18;
36127: }
36128: unsigned long REGPARAM2 CPUFUNC(op_228_5)(uae_u32 opcode) /* AND */
36129: {
36130: uae_u32 dstreg = opcode & 7;
36131: OpcodeFamily = 2; CurrentInstrCycles = 20;
36132: {{ uae_s8 src = get_ibyte_prefetch(2);
36133: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
36134: { uae_s8 dst = get_byte(dsta);
36135: src &= dst;
36136: CLEAR_CZNV;
36137: SET_ZFLG (((uae_s8)(src)) == 0);
36138: SET_NFLG (((uae_s8)(src)) < 0);
36139: m68k_incpc(6);
36140: fill_prefetch_0 ();
36141: put_byte(dsta,src);
36142: }}}}return 20;
36143: }
36144: unsigned long REGPARAM2 CPUFUNC(op_230_5)(uae_u32 opcode) /* AND */
36145: {
36146: uae_u32 dstreg = opcode & 7;
36147: OpcodeFamily = 2; CurrentInstrCycles = 22;
36148: {{ uae_s8 src = get_ibyte_prefetch(2);
36149: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
36150: BusCyclePenalty += 2;
36151: { uae_s8 dst = get_byte(dsta);
36152: src &= dst;
36153: CLEAR_CZNV;
36154: SET_ZFLG (((uae_s8)(src)) == 0);
36155: SET_NFLG (((uae_s8)(src)) < 0);
36156: m68k_incpc(6);
36157: fill_prefetch_0 ();
36158: put_byte(dsta,src);
36159: }}}}return 22;
36160: }
36161: unsigned long REGPARAM2 CPUFUNC(op_238_5)(uae_u32 opcode) /* AND */
36162: {
36163: OpcodeFamily = 2; CurrentInstrCycles = 20;
36164: {{ uae_s8 src = get_ibyte_prefetch(2);
36165: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
36166: { uae_s8 dst = get_byte(dsta);
36167: src &= dst;
36168: CLEAR_CZNV;
36169: SET_ZFLG (((uae_s8)(src)) == 0);
36170: SET_NFLG (((uae_s8)(src)) < 0);
36171: m68k_incpc(6);
36172: fill_prefetch_0 ();
36173: put_byte(dsta,src);
36174: }}}}return 20;
36175: }
36176: unsigned long REGPARAM2 CPUFUNC(op_239_5)(uae_u32 opcode) /* AND */
36177: {
36178: OpcodeFamily = 2; CurrentInstrCycles = 24;
36179: {{ uae_s8 src = get_ibyte_prefetch(2);
36180: { uaecptr dsta = get_ilong_prefetch(4);
36181: { uae_s8 dst = get_byte(dsta);
36182: src &= dst;
36183: CLEAR_CZNV;
36184: SET_ZFLG (((uae_s8)(src)) == 0);
36185: SET_NFLG (((uae_s8)(src)) < 0);
36186: m68k_incpc(8);
36187: fill_prefetch_0 ();
36188: put_byte(dsta,src);
36189: }}}}return 24;
36190: }
36191: unsigned long REGPARAM2 CPUFUNC(op_23c_5)(uae_u32 opcode) /* ANDSR */
36192: {
36193: OpcodeFamily = 5; CurrentInstrCycles = 20;
36194: { MakeSR();
36195: { uae_s16 src = get_iword_prefetch(2);
36196: src |= 0xFF00;
36197: regs.sr &= src;
36198: MakeFromSR();
36199: }}m68k_incpc(4);
36200: fill_prefetch_0 ();
36201: return 20;
36202: }
36203: unsigned long REGPARAM2 CPUFUNC(op_240_5)(uae_u32 opcode) /* AND */
36204: {
36205: uae_u32 dstreg = opcode & 7;
36206: OpcodeFamily = 2; CurrentInstrCycles = 8;
36207: {{ uae_s16 src = get_iword_prefetch(2);
36208: { uae_s16 dst = m68k_dreg(regs, dstreg);
36209: src &= dst;
36210: CLEAR_CZNV;
36211: SET_ZFLG (((uae_s16)(src)) == 0);
36212: SET_NFLG (((uae_s16)(src)) < 0);
36213: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
36214: }}}m68k_incpc(4);
36215: fill_prefetch_0 ();
36216: return 8;
36217: }
36218: unsigned long REGPARAM2 CPUFUNC(op_250_5)(uae_u32 opcode) /* AND */
36219: {
36220: uae_u32 dstreg = opcode & 7;
36221: OpcodeFamily = 2; CurrentInstrCycles = 16;
36222: {{ uae_s16 src = get_iword_prefetch(2);
36223: { uaecptr dsta = m68k_areg(regs, dstreg);
36224: if ((dsta & 1) != 0) {
36225: last_fault_for_exception_3 = dsta;
36226: last_op_for_exception_3 = opcode;
36227: last_addr_for_exception_3 = m68k_getpc() + 4;
36228: Exception(3, 0, M68000_EXC_SRC_CPU);
36229: goto endlabel2236;
36230: }
36231: {{ uae_s16 dst = get_word(dsta);
36232: src &= dst;
36233: CLEAR_CZNV;
36234: SET_ZFLG (((uae_s16)(src)) == 0);
36235: SET_NFLG (((uae_s16)(src)) < 0);
36236: m68k_incpc(4);
36237: fill_prefetch_0 ();
36238: put_word(dsta,src);
36239: }}}}}endlabel2236: ;
36240: return 16;
36241: }
36242: unsigned long REGPARAM2 CPUFUNC(op_258_5)(uae_u32 opcode) /* AND */
36243: {
36244: uae_u32 dstreg = opcode & 7;
36245: OpcodeFamily = 2; CurrentInstrCycles = 16;
36246: {{ uae_s16 src = get_iword_prefetch(2);
36247: { uaecptr dsta = m68k_areg(regs, dstreg);
36248: if ((dsta & 1) != 0) {
36249: last_fault_for_exception_3 = dsta;
36250: last_op_for_exception_3 = opcode;
36251: last_addr_for_exception_3 = m68k_getpc() + 4;
36252: Exception(3, 0, M68000_EXC_SRC_CPU);
36253: goto endlabel2237;
36254: }
36255: {{ uae_s16 dst = get_word(dsta);
36256: m68k_areg(regs, dstreg) += 2;
36257: src &= dst;
36258: CLEAR_CZNV;
36259: SET_ZFLG (((uae_s16)(src)) == 0);
36260: SET_NFLG (((uae_s16)(src)) < 0);
36261: m68k_incpc(4);
36262: fill_prefetch_0 ();
36263: put_word(dsta,src);
36264: }}}}}endlabel2237: ;
36265: return 16;
36266: }
36267: unsigned long REGPARAM2 CPUFUNC(op_260_5)(uae_u32 opcode) /* AND */
36268: {
36269: uae_u32 dstreg = opcode & 7;
36270: OpcodeFamily = 2; CurrentInstrCycles = 18;
36271: {{ uae_s16 src = get_iword_prefetch(2);
36272: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
36273: if ((dsta & 1) != 0) {
36274: last_fault_for_exception_3 = dsta;
36275: last_op_for_exception_3 = opcode;
36276: last_addr_for_exception_3 = m68k_getpc() + 4;
36277: Exception(3, 0, M68000_EXC_SRC_CPU);
36278: goto endlabel2238;
36279: }
36280: {{ uae_s16 dst = get_word(dsta);
36281: m68k_areg (regs, dstreg) = dsta;
36282: src &= dst;
36283: CLEAR_CZNV;
36284: SET_ZFLG (((uae_s16)(src)) == 0);
36285: SET_NFLG (((uae_s16)(src)) < 0);
36286: m68k_incpc(4);
36287: fill_prefetch_0 ();
36288: put_word(dsta,src);
36289: }}}}}endlabel2238: ;
36290: return 18;
36291: }
36292: unsigned long REGPARAM2 CPUFUNC(op_268_5)(uae_u32 opcode) /* AND */
36293: {
36294: uae_u32 dstreg = opcode & 7;
36295: OpcodeFamily = 2; CurrentInstrCycles = 20;
36296: {{ uae_s16 src = get_iword_prefetch(2);
36297: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
36298: if ((dsta & 1) != 0) {
36299: last_fault_for_exception_3 = dsta;
36300: last_op_for_exception_3 = opcode;
36301: last_addr_for_exception_3 = m68k_getpc() + 6;
36302: Exception(3, 0, M68000_EXC_SRC_CPU);
36303: goto endlabel2239;
36304: }
36305: {{ uae_s16 dst = get_word(dsta);
36306: src &= dst;
36307: CLEAR_CZNV;
36308: SET_ZFLG (((uae_s16)(src)) == 0);
36309: SET_NFLG (((uae_s16)(src)) < 0);
36310: m68k_incpc(6);
36311: fill_prefetch_0 ();
36312: put_word(dsta,src);
36313: }}}}}endlabel2239: ;
36314: return 20;
36315: }
36316: unsigned long REGPARAM2 CPUFUNC(op_270_5)(uae_u32 opcode) /* AND */
36317: {
36318: uae_u32 dstreg = opcode & 7;
36319: OpcodeFamily = 2; CurrentInstrCycles = 22;
36320: {{ uae_s16 src = get_iword_prefetch(2);
36321: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
36322: BusCyclePenalty += 2;
36323: if ((dsta & 1) != 0) {
36324: last_fault_for_exception_3 = dsta;
36325: last_op_for_exception_3 = opcode;
36326: last_addr_for_exception_3 = m68k_getpc() + 6;
36327: Exception(3, 0, M68000_EXC_SRC_CPU);
36328: goto endlabel2240;
36329: }
36330: {{ uae_s16 dst = get_word(dsta);
36331: src &= dst;
36332: CLEAR_CZNV;
36333: SET_ZFLG (((uae_s16)(src)) == 0);
36334: SET_NFLG (((uae_s16)(src)) < 0);
36335: m68k_incpc(6);
36336: fill_prefetch_0 ();
36337: put_word(dsta,src);
36338: }}}}}endlabel2240: ;
36339: return 22;
36340: }
36341: unsigned long REGPARAM2 CPUFUNC(op_278_5)(uae_u32 opcode) /* AND */
36342: {
36343: OpcodeFamily = 2; CurrentInstrCycles = 20;
36344: {{ uae_s16 src = get_iword_prefetch(2);
36345: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
36346: if ((dsta & 1) != 0) {
36347: last_fault_for_exception_3 = dsta;
36348: last_op_for_exception_3 = opcode;
36349: last_addr_for_exception_3 = m68k_getpc() + 6;
36350: Exception(3, 0, M68000_EXC_SRC_CPU);
36351: goto endlabel2241;
36352: }
36353: {{ uae_s16 dst = get_word(dsta);
36354: src &= dst;
36355: CLEAR_CZNV;
36356: SET_ZFLG (((uae_s16)(src)) == 0);
36357: SET_NFLG (((uae_s16)(src)) < 0);
36358: m68k_incpc(6);
36359: fill_prefetch_0 ();
36360: put_word(dsta,src);
36361: }}}}}endlabel2241: ;
36362: return 20;
36363: }
36364: unsigned long REGPARAM2 CPUFUNC(op_279_5)(uae_u32 opcode) /* AND */
36365: {
36366: OpcodeFamily = 2; CurrentInstrCycles = 24;
36367: {{ uae_s16 src = get_iword_prefetch(2);
36368: { uaecptr dsta = get_ilong_prefetch(4);
36369: if ((dsta & 1) != 0) {
36370: last_fault_for_exception_3 = dsta;
36371: last_op_for_exception_3 = opcode;
36372: last_addr_for_exception_3 = m68k_getpc() + 8;
36373: Exception(3, 0, M68000_EXC_SRC_CPU);
36374: goto endlabel2242;
36375: }
36376: {{ uae_s16 dst = get_word(dsta);
36377: src &= dst;
36378: CLEAR_CZNV;
36379: SET_ZFLG (((uae_s16)(src)) == 0);
36380: SET_NFLG (((uae_s16)(src)) < 0);
36381: m68k_incpc(8);
36382: fill_prefetch_0 ();
36383: put_word(dsta,src);
36384: }}}}}endlabel2242: ;
36385: return 24;
36386: }
36387: unsigned long REGPARAM2 CPUFUNC(op_27c_5)(uae_u32 opcode) /* ANDSR */
36388: {
36389: OpcodeFamily = 5; CurrentInstrCycles = 20;
36390: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2243; }
36391: { MakeSR();
36392: { uae_s16 src = get_iword_prefetch(2);
36393: regs.sr &= src;
36394: MakeFromSR();
36395: }}}m68k_incpc(4);
36396: fill_prefetch_0 ();
36397: endlabel2243: ;
36398: return 20;
36399: }
36400: unsigned long REGPARAM2 CPUFUNC(op_280_5)(uae_u32 opcode) /* AND */
36401: {
36402: uae_u32 dstreg = opcode & 7;
36403: OpcodeFamily = 2; CurrentInstrCycles = 16;
36404: {{ uae_s32 src = get_ilong_prefetch(2);
36405: { uae_s32 dst = m68k_dreg(regs, dstreg);
36406: src &= dst;
36407: CLEAR_CZNV;
36408: SET_ZFLG (((uae_s32)(src)) == 0);
36409: SET_NFLG (((uae_s32)(src)) < 0);
36410: m68k_dreg(regs, dstreg) = (src);
36411: }}}m68k_incpc(6);
36412: fill_prefetch_0 ();
36413: return 16;
36414: }
36415: unsigned long REGPARAM2 CPUFUNC(op_290_5)(uae_u32 opcode) /* AND */
36416: {
36417: uae_u32 dstreg = opcode & 7;
36418: OpcodeFamily = 2; CurrentInstrCycles = 28;
36419: {{ uae_s32 src = get_ilong_prefetch(2);
36420: { uaecptr dsta = m68k_areg(regs, dstreg);
36421: if ((dsta & 1) != 0) {
36422: last_fault_for_exception_3 = dsta;
36423: last_op_for_exception_3 = opcode;
36424: last_addr_for_exception_3 = m68k_getpc() + 6;
36425: Exception(3, 0, M68000_EXC_SRC_CPU);
36426: goto endlabel2245;
36427: }
36428: {{ uae_s32 dst = get_long(dsta);
36429: src &= dst;
36430: CLEAR_CZNV;
36431: SET_ZFLG (((uae_s32)(src)) == 0);
36432: SET_NFLG (((uae_s32)(src)) < 0);
36433: m68k_incpc(6);
36434: fill_prefetch_0 ();
36435: put_long(dsta,src);
36436: }}}}}endlabel2245: ;
36437: return 28;
36438: }
36439: unsigned long REGPARAM2 CPUFUNC(op_298_5)(uae_u32 opcode) /* AND */
36440: {
36441: uae_u32 dstreg = opcode & 7;
36442: OpcodeFamily = 2; CurrentInstrCycles = 28;
36443: {{ uae_s32 src = get_ilong_prefetch(2);
36444: { uaecptr dsta = m68k_areg(regs, dstreg);
36445: if ((dsta & 1) != 0) {
36446: last_fault_for_exception_3 = dsta;
36447: last_op_for_exception_3 = opcode;
36448: last_addr_for_exception_3 = m68k_getpc() + 6;
36449: Exception(3, 0, M68000_EXC_SRC_CPU);
36450: goto endlabel2246;
36451: }
36452: {{ uae_s32 dst = get_long(dsta);
36453: m68k_areg(regs, dstreg) += 4;
36454: src &= dst;
36455: CLEAR_CZNV;
36456: SET_ZFLG (((uae_s32)(src)) == 0);
36457: SET_NFLG (((uae_s32)(src)) < 0);
36458: m68k_incpc(6);
36459: fill_prefetch_0 ();
36460: put_long(dsta,src);
36461: }}}}}endlabel2246: ;
36462: return 28;
36463: }
36464: unsigned long REGPARAM2 CPUFUNC(op_2a0_5)(uae_u32 opcode) /* AND */
36465: {
36466: uae_u32 dstreg = opcode & 7;
36467: OpcodeFamily = 2; CurrentInstrCycles = 30;
36468: {{ uae_s32 src = get_ilong_prefetch(2);
36469: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
36470: if ((dsta & 1) != 0) {
36471: last_fault_for_exception_3 = dsta;
36472: last_op_for_exception_3 = opcode;
36473: last_addr_for_exception_3 = m68k_getpc() + 6;
36474: Exception(3, 0, M68000_EXC_SRC_CPU);
36475: goto endlabel2247;
36476: }
36477: {{ uae_s32 dst = get_long(dsta);
36478: m68k_areg (regs, dstreg) = dsta;
36479: src &= dst;
36480: CLEAR_CZNV;
36481: SET_ZFLG (((uae_s32)(src)) == 0);
36482: SET_NFLG (((uae_s32)(src)) < 0);
36483: m68k_incpc(6);
36484: fill_prefetch_0 ();
36485: put_long(dsta,src);
36486: }}}}}endlabel2247: ;
36487: return 30;
36488: }
36489: unsigned long REGPARAM2 CPUFUNC(op_2a8_5)(uae_u32 opcode) /* AND */
36490: {
36491: uae_u32 dstreg = opcode & 7;
36492: OpcodeFamily = 2; CurrentInstrCycles = 32;
36493: {{ uae_s32 src = get_ilong_prefetch(2);
36494: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
36495: if ((dsta & 1) != 0) {
36496: last_fault_for_exception_3 = dsta;
36497: last_op_for_exception_3 = opcode;
36498: last_addr_for_exception_3 = m68k_getpc() + 8;
36499: Exception(3, 0, M68000_EXC_SRC_CPU);
36500: goto endlabel2248;
36501: }
36502: {{ uae_s32 dst = get_long(dsta);
36503: src &= dst;
36504: CLEAR_CZNV;
36505: SET_ZFLG (((uae_s32)(src)) == 0);
36506: SET_NFLG (((uae_s32)(src)) < 0);
36507: m68k_incpc(8);
36508: fill_prefetch_0 ();
36509: put_long(dsta,src);
36510: }}}}}endlabel2248: ;
36511: return 32;
36512: }
36513: unsigned long REGPARAM2 CPUFUNC(op_2b0_5)(uae_u32 opcode) /* AND */
36514: {
36515: uae_u32 dstreg = opcode & 7;
36516: OpcodeFamily = 2; CurrentInstrCycles = 34;
36517: {{ uae_s32 src = get_ilong_prefetch(2);
36518: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
36519: BusCyclePenalty += 2;
36520: if ((dsta & 1) != 0) {
36521: last_fault_for_exception_3 = dsta;
36522: last_op_for_exception_3 = opcode;
36523: last_addr_for_exception_3 = m68k_getpc() + 8;
36524: Exception(3, 0, M68000_EXC_SRC_CPU);
36525: goto endlabel2249;
36526: }
36527: {{ uae_s32 dst = get_long(dsta);
36528: src &= dst;
36529: CLEAR_CZNV;
36530: SET_ZFLG (((uae_s32)(src)) == 0);
36531: SET_NFLG (((uae_s32)(src)) < 0);
36532: m68k_incpc(8);
36533: fill_prefetch_0 ();
36534: put_long(dsta,src);
36535: }}}}}endlabel2249: ;
36536: return 34;
36537: }
36538: unsigned long REGPARAM2 CPUFUNC(op_2b8_5)(uae_u32 opcode) /* AND */
36539: {
36540: OpcodeFamily = 2; CurrentInstrCycles = 32;
36541: {{ uae_s32 src = get_ilong_prefetch(2);
36542: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
36543: if ((dsta & 1) != 0) {
36544: last_fault_for_exception_3 = dsta;
36545: last_op_for_exception_3 = opcode;
36546: last_addr_for_exception_3 = m68k_getpc() + 8;
36547: Exception(3, 0, M68000_EXC_SRC_CPU);
36548: goto endlabel2250;
36549: }
36550: {{ uae_s32 dst = get_long(dsta);
36551: src &= dst;
36552: CLEAR_CZNV;
36553: SET_ZFLG (((uae_s32)(src)) == 0);
36554: SET_NFLG (((uae_s32)(src)) < 0);
36555: m68k_incpc(8);
36556: fill_prefetch_0 ();
36557: put_long(dsta,src);
36558: }}}}}endlabel2250: ;
36559: return 32;
36560: }
36561: unsigned long REGPARAM2 CPUFUNC(op_2b9_5)(uae_u32 opcode) /* AND */
36562: {
36563: OpcodeFamily = 2; CurrentInstrCycles = 36;
36564: {{ uae_s32 src = get_ilong_prefetch(2);
36565: { uaecptr dsta = get_ilong_prefetch(6);
36566: if ((dsta & 1) != 0) {
36567: last_fault_for_exception_3 = dsta;
36568: last_op_for_exception_3 = opcode;
36569: last_addr_for_exception_3 = m68k_getpc() + 10;
36570: Exception(3, 0, M68000_EXC_SRC_CPU);
36571: goto endlabel2251;
36572: }
36573: {{ uae_s32 dst = get_long(dsta);
36574: src &= dst;
36575: CLEAR_CZNV;
36576: SET_ZFLG (((uae_s32)(src)) == 0);
36577: SET_NFLG (((uae_s32)(src)) < 0);
36578: m68k_incpc(10);
36579: fill_prefetch_0 ();
36580: put_long(dsta,src);
36581: }}}}}endlabel2251: ;
36582: return 36;
36583: }
36584: unsigned long REGPARAM2 CPUFUNC(op_400_5)(uae_u32 opcode) /* SUB */
36585: {
36586: uae_u32 dstreg = opcode & 7;
36587: OpcodeFamily = 7; CurrentInstrCycles = 8;
36588: {{ uae_s8 src = get_ibyte_prefetch(2);
36589: { uae_s8 dst = m68k_dreg(regs, dstreg);
36590: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
36591: { int flgs = ((uae_s8)(src)) < 0;
36592: int flgo = ((uae_s8)(dst)) < 0;
36593: int flgn = ((uae_s8)(newv)) < 0;
36594: SET_ZFLG (((uae_s8)(newv)) == 0);
36595: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36596: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
36597: COPY_CARRY;
36598: SET_NFLG (flgn != 0);
36599: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
36600: }}}}}}m68k_incpc(4);
36601: fill_prefetch_0 ();
36602: return 8;
36603: }
36604: unsigned long REGPARAM2 CPUFUNC(op_410_5)(uae_u32 opcode) /* SUB */
36605: {
36606: uae_u32 dstreg = opcode & 7;
36607: OpcodeFamily = 7; CurrentInstrCycles = 16;
36608: {{ uae_s8 src = get_ibyte_prefetch(2);
36609: { uaecptr dsta = m68k_areg(regs, dstreg);
36610: { uae_s8 dst = get_byte(dsta);
36611: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
36612: { int flgs = ((uae_s8)(src)) < 0;
36613: int flgo = ((uae_s8)(dst)) < 0;
36614: int flgn = ((uae_s8)(newv)) < 0;
36615: SET_ZFLG (((uae_s8)(newv)) == 0);
36616: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36617: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
36618: COPY_CARRY;
36619: SET_NFLG (flgn != 0);
36620: m68k_incpc(4);
36621: fill_prefetch_0 ();
36622: put_byte(dsta,newv);
36623: }}}}}}}return 16;
36624: }
36625: unsigned long REGPARAM2 CPUFUNC(op_418_5)(uae_u32 opcode) /* SUB */
36626: {
36627: uae_u32 dstreg = opcode & 7;
36628: OpcodeFamily = 7; CurrentInstrCycles = 16;
36629: {{ uae_s8 src = get_ibyte_prefetch(2);
36630: { uaecptr dsta = m68k_areg(regs, dstreg);
36631: { uae_s8 dst = get_byte(dsta);
36632: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
36633: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
36634: { int flgs = ((uae_s8)(src)) < 0;
36635: int flgo = ((uae_s8)(dst)) < 0;
36636: int flgn = ((uae_s8)(newv)) < 0;
36637: SET_ZFLG (((uae_s8)(newv)) == 0);
36638: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36639: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
36640: COPY_CARRY;
36641: SET_NFLG (flgn != 0);
36642: m68k_incpc(4);
36643: fill_prefetch_0 ();
36644: put_byte(dsta,newv);
36645: }}}}}}}return 16;
36646: }
36647: unsigned long REGPARAM2 CPUFUNC(op_420_5)(uae_u32 opcode) /* SUB */
36648: {
36649: uae_u32 dstreg = opcode & 7;
36650: OpcodeFamily = 7; CurrentInstrCycles = 18;
36651: {{ uae_s8 src = get_ibyte_prefetch(2);
36652: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
36653: { uae_s8 dst = get_byte(dsta);
36654: m68k_areg (regs, dstreg) = dsta;
36655: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
36656: { int flgs = ((uae_s8)(src)) < 0;
36657: int flgo = ((uae_s8)(dst)) < 0;
36658: int flgn = ((uae_s8)(newv)) < 0;
36659: SET_ZFLG (((uae_s8)(newv)) == 0);
36660: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36661: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
36662: COPY_CARRY;
36663: SET_NFLG (flgn != 0);
36664: m68k_incpc(4);
36665: fill_prefetch_0 ();
36666: put_byte(dsta,newv);
36667: }}}}}}}return 18;
36668: }
36669: unsigned long REGPARAM2 CPUFUNC(op_428_5)(uae_u32 opcode) /* SUB */
36670: {
36671: uae_u32 dstreg = opcode & 7;
36672: OpcodeFamily = 7; CurrentInstrCycles = 20;
36673: {{ uae_s8 src = get_ibyte_prefetch(2);
36674: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
36675: { uae_s8 dst = get_byte(dsta);
36676: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
36677: { int flgs = ((uae_s8)(src)) < 0;
36678: int flgo = ((uae_s8)(dst)) < 0;
36679: int flgn = ((uae_s8)(newv)) < 0;
36680: SET_ZFLG (((uae_s8)(newv)) == 0);
36681: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36682: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
36683: COPY_CARRY;
36684: SET_NFLG (flgn != 0);
36685: m68k_incpc(6);
36686: fill_prefetch_0 ();
36687: put_byte(dsta,newv);
36688: }}}}}}}return 20;
36689: }
36690: unsigned long REGPARAM2 CPUFUNC(op_430_5)(uae_u32 opcode) /* SUB */
36691: {
36692: uae_u32 dstreg = opcode & 7;
36693: OpcodeFamily = 7; CurrentInstrCycles = 22;
36694: {{ uae_s8 src = get_ibyte_prefetch(2);
36695: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
36696: BusCyclePenalty += 2;
36697: { uae_s8 dst = get_byte(dsta);
36698: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
36699: { int flgs = ((uae_s8)(src)) < 0;
36700: int flgo = ((uae_s8)(dst)) < 0;
36701: int flgn = ((uae_s8)(newv)) < 0;
36702: SET_ZFLG (((uae_s8)(newv)) == 0);
36703: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36704: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
36705: COPY_CARRY;
36706: SET_NFLG (flgn != 0);
36707: m68k_incpc(6);
36708: fill_prefetch_0 ();
36709: put_byte(dsta,newv);
36710: }}}}}}}return 22;
36711: }
36712: unsigned long REGPARAM2 CPUFUNC(op_438_5)(uae_u32 opcode) /* SUB */
36713: {
36714: OpcodeFamily = 7; CurrentInstrCycles = 20;
36715: {{ uae_s8 src = get_ibyte_prefetch(2);
36716: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
36717: { uae_s8 dst = get_byte(dsta);
36718: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
36719: { int flgs = ((uae_s8)(src)) < 0;
36720: int flgo = ((uae_s8)(dst)) < 0;
36721: int flgn = ((uae_s8)(newv)) < 0;
36722: SET_ZFLG (((uae_s8)(newv)) == 0);
36723: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36724: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
36725: COPY_CARRY;
36726: SET_NFLG (flgn != 0);
36727: m68k_incpc(6);
36728: fill_prefetch_0 ();
36729: put_byte(dsta,newv);
36730: }}}}}}}return 20;
36731: }
36732: unsigned long REGPARAM2 CPUFUNC(op_439_5)(uae_u32 opcode) /* SUB */
36733: {
36734: OpcodeFamily = 7; CurrentInstrCycles = 24;
36735: {{ uae_s8 src = get_ibyte_prefetch(2);
36736: { uaecptr dsta = get_ilong_prefetch(4);
36737: { uae_s8 dst = get_byte(dsta);
36738: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
36739: { int flgs = ((uae_s8)(src)) < 0;
36740: int flgo = ((uae_s8)(dst)) < 0;
36741: int flgn = ((uae_s8)(newv)) < 0;
36742: SET_ZFLG (((uae_s8)(newv)) == 0);
36743: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36744: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
36745: COPY_CARRY;
36746: SET_NFLG (flgn != 0);
36747: m68k_incpc(8);
36748: fill_prefetch_0 ();
36749: put_byte(dsta,newv);
36750: }}}}}}}return 24;
36751: }
36752: unsigned long REGPARAM2 CPUFUNC(op_440_5)(uae_u32 opcode) /* SUB */
36753: {
36754: uae_u32 dstreg = opcode & 7;
36755: OpcodeFamily = 7; CurrentInstrCycles = 8;
36756: {{ uae_s16 src = get_iword_prefetch(2);
36757: { uae_s16 dst = m68k_dreg(regs, dstreg);
36758: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
36759: { int flgs = ((uae_s16)(src)) < 0;
36760: int flgo = ((uae_s16)(dst)) < 0;
36761: int flgn = ((uae_s16)(newv)) < 0;
36762: SET_ZFLG (((uae_s16)(newv)) == 0);
36763: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36764: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
36765: COPY_CARRY;
36766: SET_NFLG (flgn != 0);
36767: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
36768: }}}}}}m68k_incpc(4);
36769: fill_prefetch_0 ();
36770: return 8;
36771: }
36772: unsigned long REGPARAM2 CPUFUNC(op_450_5)(uae_u32 opcode) /* SUB */
36773: {
36774: uae_u32 dstreg = opcode & 7;
36775: OpcodeFamily = 7; CurrentInstrCycles = 16;
36776: {{ uae_s16 src = get_iword_prefetch(2);
36777: { uaecptr dsta = m68k_areg(regs, dstreg);
36778: if ((dsta & 1) != 0) {
36779: last_fault_for_exception_3 = dsta;
36780: last_op_for_exception_3 = opcode;
36781: last_addr_for_exception_3 = m68k_getpc() + 4;
36782: Exception(3, 0, M68000_EXC_SRC_CPU);
36783: goto endlabel2261;
36784: }
36785: {{ uae_s16 dst = get_word(dsta);
36786: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
36787: { int flgs = ((uae_s16)(src)) < 0;
36788: int flgo = ((uae_s16)(dst)) < 0;
36789: int flgn = ((uae_s16)(newv)) < 0;
36790: SET_ZFLG (((uae_s16)(newv)) == 0);
36791: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36792: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
36793: COPY_CARRY;
36794: SET_NFLG (flgn != 0);
36795: m68k_incpc(4);
36796: fill_prefetch_0 ();
36797: put_word(dsta,newv);
36798: }}}}}}}}endlabel2261: ;
36799: return 16;
36800: }
36801: unsigned long REGPARAM2 CPUFUNC(op_458_5)(uae_u32 opcode) /* SUB */
36802: {
36803: uae_u32 dstreg = opcode & 7;
36804: OpcodeFamily = 7; CurrentInstrCycles = 16;
36805: {{ uae_s16 src = get_iword_prefetch(2);
36806: { uaecptr dsta = m68k_areg(regs, dstreg);
36807: if ((dsta & 1) != 0) {
36808: last_fault_for_exception_3 = dsta;
36809: last_op_for_exception_3 = opcode;
36810: last_addr_for_exception_3 = m68k_getpc() + 4;
36811: Exception(3, 0, M68000_EXC_SRC_CPU);
36812: goto endlabel2262;
36813: }
36814: {{ uae_s16 dst = get_word(dsta);
36815: m68k_areg(regs, dstreg) += 2;
36816: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
36817: { int flgs = ((uae_s16)(src)) < 0;
36818: int flgo = ((uae_s16)(dst)) < 0;
36819: int flgn = ((uae_s16)(newv)) < 0;
36820: SET_ZFLG (((uae_s16)(newv)) == 0);
36821: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36822: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
36823: COPY_CARRY;
36824: SET_NFLG (flgn != 0);
36825: m68k_incpc(4);
36826: fill_prefetch_0 ();
36827: put_word(dsta,newv);
36828: }}}}}}}}endlabel2262: ;
36829: return 16;
36830: }
36831: unsigned long REGPARAM2 CPUFUNC(op_460_5)(uae_u32 opcode) /* SUB */
36832: {
36833: uae_u32 dstreg = opcode & 7;
36834: OpcodeFamily = 7; CurrentInstrCycles = 18;
36835: {{ uae_s16 src = get_iword_prefetch(2);
36836: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
36837: if ((dsta & 1) != 0) {
36838: last_fault_for_exception_3 = dsta;
36839: last_op_for_exception_3 = opcode;
36840: last_addr_for_exception_3 = m68k_getpc() + 4;
36841: Exception(3, 0, M68000_EXC_SRC_CPU);
36842: goto endlabel2263;
36843: }
36844: {{ uae_s16 dst = get_word(dsta);
36845: m68k_areg (regs, dstreg) = dsta;
36846: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
36847: { int flgs = ((uae_s16)(src)) < 0;
36848: int flgo = ((uae_s16)(dst)) < 0;
36849: int flgn = ((uae_s16)(newv)) < 0;
36850: SET_ZFLG (((uae_s16)(newv)) == 0);
36851: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36852: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
36853: COPY_CARRY;
36854: SET_NFLG (flgn != 0);
36855: m68k_incpc(4);
36856: fill_prefetch_0 ();
36857: put_word(dsta,newv);
36858: }}}}}}}}endlabel2263: ;
36859: return 18;
36860: }
36861: unsigned long REGPARAM2 CPUFUNC(op_468_5)(uae_u32 opcode) /* SUB */
36862: {
36863: uae_u32 dstreg = opcode & 7;
36864: OpcodeFamily = 7; CurrentInstrCycles = 20;
36865: {{ uae_s16 src = get_iword_prefetch(2);
36866: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
36867: if ((dsta & 1) != 0) {
36868: last_fault_for_exception_3 = dsta;
36869: last_op_for_exception_3 = opcode;
36870: last_addr_for_exception_3 = m68k_getpc() + 6;
36871: Exception(3, 0, M68000_EXC_SRC_CPU);
36872: goto endlabel2264;
36873: }
36874: {{ uae_s16 dst = get_word(dsta);
36875: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
36876: { int flgs = ((uae_s16)(src)) < 0;
36877: int flgo = ((uae_s16)(dst)) < 0;
36878: int flgn = ((uae_s16)(newv)) < 0;
36879: SET_ZFLG (((uae_s16)(newv)) == 0);
36880: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36881: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
36882: COPY_CARRY;
36883: SET_NFLG (flgn != 0);
36884: m68k_incpc(6);
36885: fill_prefetch_0 ();
36886: put_word(dsta,newv);
36887: }}}}}}}}endlabel2264: ;
36888: return 20;
36889: }
36890: unsigned long REGPARAM2 CPUFUNC(op_470_5)(uae_u32 opcode) /* SUB */
36891: {
36892: uae_u32 dstreg = opcode & 7;
36893: OpcodeFamily = 7; CurrentInstrCycles = 22;
36894: {{ uae_s16 src = get_iword_prefetch(2);
36895: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
36896: BusCyclePenalty += 2;
36897: if ((dsta & 1) != 0) {
36898: last_fault_for_exception_3 = dsta;
36899: last_op_for_exception_3 = opcode;
36900: last_addr_for_exception_3 = m68k_getpc() + 6;
36901: Exception(3, 0, M68000_EXC_SRC_CPU);
36902: goto endlabel2265;
36903: }
36904: {{ uae_s16 dst = get_word(dsta);
36905: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
36906: { int flgs = ((uae_s16)(src)) < 0;
36907: int flgo = ((uae_s16)(dst)) < 0;
36908: int flgn = ((uae_s16)(newv)) < 0;
36909: SET_ZFLG (((uae_s16)(newv)) == 0);
36910: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36911: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
36912: COPY_CARRY;
36913: SET_NFLG (flgn != 0);
36914: m68k_incpc(6);
36915: fill_prefetch_0 ();
36916: put_word(dsta,newv);
36917: }}}}}}}}endlabel2265: ;
36918: return 22;
36919: }
36920: unsigned long REGPARAM2 CPUFUNC(op_478_5)(uae_u32 opcode) /* SUB */
36921: {
36922: OpcodeFamily = 7; CurrentInstrCycles = 20;
36923: {{ uae_s16 src = get_iword_prefetch(2);
36924: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
36925: if ((dsta & 1) != 0) {
36926: last_fault_for_exception_3 = dsta;
36927: last_op_for_exception_3 = opcode;
36928: last_addr_for_exception_3 = m68k_getpc() + 6;
36929: Exception(3, 0, M68000_EXC_SRC_CPU);
36930: goto endlabel2266;
36931: }
36932: {{ uae_s16 dst = get_word(dsta);
36933: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
36934: { int flgs = ((uae_s16)(src)) < 0;
36935: int flgo = ((uae_s16)(dst)) < 0;
36936: int flgn = ((uae_s16)(newv)) < 0;
36937: SET_ZFLG (((uae_s16)(newv)) == 0);
36938: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36939: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
36940: COPY_CARRY;
36941: SET_NFLG (flgn != 0);
36942: m68k_incpc(6);
36943: fill_prefetch_0 ();
36944: put_word(dsta,newv);
36945: }}}}}}}}endlabel2266: ;
36946: return 20;
36947: }
36948: unsigned long REGPARAM2 CPUFUNC(op_479_5)(uae_u32 opcode) /* SUB */
36949: {
36950: OpcodeFamily = 7; CurrentInstrCycles = 24;
36951: {{ uae_s16 src = get_iword_prefetch(2);
36952: { uaecptr dsta = get_ilong_prefetch(4);
36953: if ((dsta & 1) != 0) {
36954: last_fault_for_exception_3 = dsta;
36955: last_op_for_exception_3 = opcode;
36956: last_addr_for_exception_3 = m68k_getpc() + 8;
36957: Exception(3, 0, M68000_EXC_SRC_CPU);
36958: goto endlabel2267;
36959: }
36960: {{ uae_s16 dst = get_word(dsta);
36961: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
36962: { int flgs = ((uae_s16)(src)) < 0;
36963: int flgo = ((uae_s16)(dst)) < 0;
36964: int flgn = ((uae_s16)(newv)) < 0;
36965: SET_ZFLG (((uae_s16)(newv)) == 0);
36966: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36967: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
36968: COPY_CARRY;
36969: SET_NFLG (flgn != 0);
36970: m68k_incpc(8);
36971: fill_prefetch_0 ();
36972: put_word(dsta,newv);
36973: }}}}}}}}endlabel2267: ;
36974: return 24;
36975: }
36976: unsigned long REGPARAM2 CPUFUNC(op_480_5)(uae_u32 opcode) /* SUB */
36977: {
36978: uae_u32 dstreg = opcode & 7;
36979: OpcodeFamily = 7; CurrentInstrCycles = 16;
36980: {{ uae_s32 src = get_ilong_prefetch(2);
36981: { uae_s32 dst = m68k_dreg(regs, dstreg);
36982: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
36983: { int flgs = ((uae_s32)(src)) < 0;
36984: int flgo = ((uae_s32)(dst)) < 0;
36985: int flgn = ((uae_s32)(newv)) < 0;
36986: SET_ZFLG (((uae_s32)(newv)) == 0);
36987: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
36988: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
36989: COPY_CARRY;
36990: SET_NFLG (flgn != 0);
36991: m68k_dreg(regs, dstreg) = (newv);
36992: }}}}}}m68k_incpc(6);
36993: fill_prefetch_0 ();
36994: return 16;
36995: }
36996: unsigned long REGPARAM2 CPUFUNC(op_490_5)(uae_u32 opcode) /* SUB */
36997: {
36998: uae_u32 dstreg = opcode & 7;
36999: OpcodeFamily = 7; CurrentInstrCycles = 28;
37000: {{ uae_s32 src = get_ilong_prefetch(2);
37001: { uaecptr dsta = m68k_areg(regs, dstreg);
37002: if ((dsta & 1) != 0) {
37003: last_fault_for_exception_3 = dsta;
37004: last_op_for_exception_3 = opcode;
37005: last_addr_for_exception_3 = m68k_getpc() + 6;
37006: Exception(3, 0, M68000_EXC_SRC_CPU);
37007: goto endlabel2269;
37008: }
37009: {{ uae_s32 dst = get_long(dsta);
37010: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
37011: { int flgs = ((uae_s32)(src)) < 0;
37012: int flgo = ((uae_s32)(dst)) < 0;
37013: int flgn = ((uae_s32)(newv)) < 0;
37014: SET_ZFLG (((uae_s32)(newv)) == 0);
37015: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
37016: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
37017: COPY_CARRY;
37018: SET_NFLG (flgn != 0);
37019: m68k_incpc(6);
37020: fill_prefetch_0 ();
37021: put_long(dsta,newv);
37022: }}}}}}}}endlabel2269: ;
37023: return 28;
37024: }
37025: unsigned long REGPARAM2 CPUFUNC(op_498_5)(uae_u32 opcode) /* SUB */
37026: {
37027: uae_u32 dstreg = opcode & 7;
37028: OpcodeFamily = 7; CurrentInstrCycles = 28;
37029: {{ uae_s32 src = get_ilong_prefetch(2);
37030: { uaecptr dsta = m68k_areg(regs, dstreg);
37031: if ((dsta & 1) != 0) {
37032: last_fault_for_exception_3 = dsta;
37033: last_op_for_exception_3 = opcode;
37034: last_addr_for_exception_3 = m68k_getpc() + 6;
37035: Exception(3, 0, M68000_EXC_SRC_CPU);
37036: goto endlabel2270;
37037: }
37038: {{ uae_s32 dst = get_long(dsta);
37039: m68k_areg(regs, dstreg) += 4;
37040: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
37041: { int flgs = ((uae_s32)(src)) < 0;
37042: int flgo = ((uae_s32)(dst)) < 0;
37043: int flgn = ((uae_s32)(newv)) < 0;
37044: SET_ZFLG (((uae_s32)(newv)) == 0);
37045: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
37046: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
37047: COPY_CARRY;
37048: SET_NFLG (flgn != 0);
37049: m68k_incpc(6);
37050: fill_prefetch_0 ();
37051: put_long(dsta,newv);
37052: }}}}}}}}endlabel2270: ;
37053: return 28;
37054: }
37055: unsigned long REGPARAM2 CPUFUNC(op_4a0_5)(uae_u32 opcode) /* SUB */
37056: {
37057: uae_u32 dstreg = opcode & 7;
37058: OpcodeFamily = 7; CurrentInstrCycles = 30;
37059: {{ uae_s32 src = get_ilong_prefetch(2);
37060: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
37061: if ((dsta & 1) != 0) {
37062: last_fault_for_exception_3 = dsta;
37063: last_op_for_exception_3 = opcode;
37064: last_addr_for_exception_3 = m68k_getpc() + 6;
37065: Exception(3, 0, M68000_EXC_SRC_CPU);
37066: goto endlabel2271;
37067: }
37068: {{ uae_s32 dst = get_long(dsta);
37069: m68k_areg (regs, dstreg) = dsta;
37070: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
37071: { int flgs = ((uae_s32)(src)) < 0;
37072: int flgo = ((uae_s32)(dst)) < 0;
37073: int flgn = ((uae_s32)(newv)) < 0;
37074: SET_ZFLG (((uae_s32)(newv)) == 0);
37075: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
37076: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
37077: COPY_CARRY;
37078: SET_NFLG (flgn != 0);
37079: m68k_incpc(6);
37080: fill_prefetch_0 ();
37081: put_long(dsta,newv);
37082: }}}}}}}}endlabel2271: ;
37083: return 30;
37084: }
37085: unsigned long REGPARAM2 CPUFUNC(op_4a8_5)(uae_u32 opcode) /* SUB */
37086: {
37087: uae_u32 dstreg = opcode & 7;
37088: OpcodeFamily = 7; CurrentInstrCycles = 32;
37089: {{ uae_s32 src = get_ilong_prefetch(2);
37090: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
37091: if ((dsta & 1) != 0) {
37092: last_fault_for_exception_3 = dsta;
37093: last_op_for_exception_3 = opcode;
37094: last_addr_for_exception_3 = m68k_getpc() + 8;
37095: Exception(3, 0, M68000_EXC_SRC_CPU);
37096: goto endlabel2272;
37097: }
37098: {{ uae_s32 dst = get_long(dsta);
37099: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
37100: { int flgs = ((uae_s32)(src)) < 0;
37101: int flgo = ((uae_s32)(dst)) < 0;
37102: int flgn = ((uae_s32)(newv)) < 0;
37103: SET_ZFLG (((uae_s32)(newv)) == 0);
37104: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
37105: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
37106: COPY_CARRY;
37107: SET_NFLG (flgn != 0);
37108: m68k_incpc(8);
37109: fill_prefetch_0 ();
37110: put_long(dsta,newv);
37111: }}}}}}}}endlabel2272: ;
37112: return 32;
37113: }
37114: unsigned long REGPARAM2 CPUFUNC(op_4b0_5)(uae_u32 opcode) /* SUB */
37115: {
37116: uae_u32 dstreg = opcode & 7;
37117: OpcodeFamily = 7; CurrentInstrCycles = 34;
37118: {{ uae_s32 src = get_ilong_prefetch(2);
37119: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
37120: BusCyclePenalty += 2;
37121: if ((dsta & 1) != 0) {
37122: last_fault_for_exception_3 = dsta;
37123: last_op_for_exception_3 = opcode;
37124: last_addr_for_exception_3 = m68k_getpc() + 8;
37125: Exception(3, 0, M68000_EXC_SRC_CPU);
37126: goto endlabel2273;
37127: }
37128: {{ uae_s32 dst = get_long(dsta);
37129: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
37130: { int flgs = ((uae_s32)(src)) < 0;
37131: int flgo = ((uae_s32)(dst)) < 0;
37132: int flgn = ((uae_s32)(newv)) < 0;
37133: SET_ZFLG (((uae_s32)(newv)) == 0);
37134: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
37135: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
37136: COPY_CARRY;
37137: SET_NFLG (flgn != 0);
37138: m68k_incpc(8);
37139: fill_prefetch_0 ();
37140: put_long(dsta,newv);
37141: }}}}}}}}endlabel2273: ;
37142: return 34;
37143: }
37144: unsigned long REGPARAM2 CPUFUNC(op_4b8_5)(uae_u32 opcode) /* SUB */
37145: {
37146: OpcodeFamily = 7; CurrentInstrCycles = 32;
37147: {{ uae_s32 src = get_ilong_prefetch(2);
37148: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
37149: if ((dsta & 1) != 0) {
37150: last_fault_for_exception_3 = dsta;
37151: last_op_for_exception_3 = opcode;
37152: last_addr_for_exception_3 = m68k_getpc() + 8;
37153: Exception(3, 0, M68000_EXC_SRC_CPU);
37154: goto endlabel2274;
37155: }
37156: {{ uae_s32 dst = get_long(dsta);
37157: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
37158: { int flgs = ((uae_s32)(src)) < 0;
37159: int flgo = ((uae_s32)(dst)) < 0;
37160: int flgn = ((uae_s32)(newv)) < 0;
37161: SET_ZFLG (((uae_s32)(newv)) == 0);
37162: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
37163: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
37164: COPY_CARRY;
37165: SET_NFLG (flgn != 0);
37166: m68k_incpc(8);
37167: fill_prefetch_0 ();
37168: put_long(dsta,newv);
37169: }}}}}}}}endlabel2274: ;
37170: return 32;
37171: }
37172: unsigned long REGPARAM2 CPUFUNC(op_4b9_5)(uae_u32 opcode) /* SUB */
37173: {
37174: OpcodeFamily = 7; CurrentInstrCycles = 36;
37175: {{ uae_s32 src = get_ilong_prefetch(2);
37176: { uaecptr dsta = get_ilong_prefetch(6);
37177: if ((dsta & 1) != 0) {
37178: last_fault_for_exception_3 = dsta;
37179: last_op_for_exception_3 = opcode;
37180: last_addr_for_exception_3 = m68k_getpc() + 10;
37181: Exception(3, 0, M68000_EXC_SRC_CPU);
37182: goto endlabel2275;
37183: }
37184: {{ uae_s32 dst = get_long(dsta);
37185: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
37186: { int flgs = ((uae_s32)(src)) < 0;
37187: int flgo = ((uae_s32)(dst)) < 0;
37188: int flgn = ((uae_s32)(newv)) < 0;
37189: SET_ZFLG (((uae_s32)(newv)) == 0);
37190: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
37191: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
37192: COPY_CARRY;
37193: SET_NFLG (flgn != 0);
37194: m68k_incpc(10);
37195: fill_prefetch_0 ();
37196: put_long(dsta,newv);
37197: }}}}}}}}endlabel2275: ;
37198: return 36;
37199: }
37200: unsigned long REGPARAM2 CPUFUNC(op_600_5)(uae_u32 opcode) /* ADD */
37201: {
37202: uae_u32 dstreg = opcode & 7;
37203: OpcodeFamily = 11; CurrentInstrCycles = 8;
37204: {{ uae_s8 src = get_ibyte_prefetch(2);
37205: { uae_s8 dst = m68k_dreg(regs, dstreg);
37206: { refill_prefetch (m68k_getpc(), 2);
37207: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
37208: { int flgs = ((uae_s8)(src)) < 0;
37209: int flgo = ((uae_s8)(dst)) < 0;
37210: int flgn = ((uae_s8)(newv)) < 0;
37211: SET_ZFLG (((uae_s8)(newv)) == 0);
37212: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37213: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
37214: COPY_CARRY;
37215: SET_NFLG (flgn != 0);
37216: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
37217: }}}}}}m68k_incpc(4);
37218: fill_prefetch_0 ();
37219: return 8;
37220: }
37221: unsigned long REGPARAM2 CPUFUNC(op_610_5)(uae_u32 opcode) /* ADD */
37222: {
37223: uae_u32 dstreg = opcode & 7;
37224: OpcodeFamily = 11; CurrentInstrCycles = 16;
37225: {{ uae_s8 src = get_ibyte_prefetch(2);
37226: { uaecptr dsta = m68k_areg(regs, dstreg);
37227: { uae_s8 dst = get_byte(dsta);
37228: { refill_prefetch (m68k_getpc(), 2);
37229: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
37230: { int flgs = ((uae_s8)(src)) < 0;
37231: int flgo = ((uae_s8)(dst)) < 0;
37232: int flgn = ((uae_s8)(newv)) < 0;
37233: SET_ZFLG (((uae_s8)(newv)) == 0);
37234: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37235: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
37236: COPY_CARRY;
37237: SET_NFLG (flgn != 0);
37238: m68k_incpc(4);
37239: fill_prefetch_0 ();
37240: put_byte(dsta,newv);
37241: }}}}}}}return 16;
37242: }
37243: unsigned long REGPARAM2 CPUFUNC(op_618_5)(uae_u32 opcode) /* ADD */
37244: {
37245: uae_u32 dstreg = opcode & 7;
37246: OpcodeFamily = 11; CurrentInstrCycles = 16;
37247: {{ uae_s8 src = get_ibyte_prefetch(2);
37248: { uaecptr dsta = m68k_areg(regs, dstreg);
37249: { uae_s8 dst = get_byte(dsta);
37250: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
37251: { refill_prefetch (m68k_getpc(), 2);
37252: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
37253: { int flgs = ((uae_s8)(src)) < 0;
37254: int flgo = ((uae_s8)(dst)) < 0;
37255: int flgn = ((uae_s8)(newv)) < 0;
37256: SET_ZFLG (((uae_s8)(newv)) == 0);
37257: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37258: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
37259: COPY_CARRY;
37260: SET_NFLG (flgn != 0);
37261: m68k_incpc(4);
37262: fill_prefetch_0 ();
37263: put_byte(dsta,newv);
37264: }}}}}}}return 16;
37265: }
37266: unsigned long REGPARAM2 CPUFUNC(op_620_5)(uae_u32 opcode) /* ADD */
37267: {
37268: uae_u32 dstreg = opcode & 7;
37269: OpcodeFamily = 11; CurrentInstrCycles = 18;
37270: {{ uae_s8 src = get_ibyte_prefetch(2);
37271: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
37272: { uae_s8 dst = get_byte(dsta);
37273: m68k_areg (regs, dstreg) = dsta;
37274: { refill_prefetch (m68k_getpc(), 2);
37275: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
37276: { int flgs = ((uae_s8)(src)) < 0;
37277: int flgo = ((uae_s8)(dst)) < 0;
37278: int flgn = ((uae_s8)(newv)) < 0;
37279: SET_ZFLG (((uae_s8)(newv)) == 0);
37280: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37281: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
37282: COPY_CARRY;
37283: SET_NFLG (flgn != 0);
37284: m68k_incpc(4);
37285: fill_prefetch_0 ();
37286: put_byte(dsta,newv);
37287: }}}}}}}return 18;
37288: }
37289: unsigned long REGPARAM2 CPUFUNC(op_628_5)(uae_u32 opcode) /* ADD */
37290: {
37291: uae_u32 dstreg = opcode & 7;
37292: OpcodeFamily = 11; CurrentInstrCycles = 20;
37293: {{ uae_s8 src = get_ibyte_prefetch(2);
37294: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
37295: { uae_s8 dst = get_byte(dsta);
37296: { refill_prefetch (m68k_getpc(), 2);
37297: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
37298: { int flgs = ((uae_s8)(src)) < 0;
37299: int flgo = ((uae_s8)(dst)) < 0;
37300: int flgn = ((uae_s8)(newv)) < 0;
37301: SET_ZFLG (((uae_s8)(newv)) == 0);
37302: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37303: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
37304: COPY_CARRY;
37305: SET_NFLG (flgn != 0);
37306: m68k_incpc(6);
37307: fill_prefetch_0 ();
37308: put_byte(dsta,newv);
37309: }}}}}}}return 20;
37310: }
37311: unsigned long REGPARAM2 CPUFUNC(op_630_5)(uae_u32 opcode) /* ADD */
37312: {
37313: uae_u32 dstreg = opcode & 7;
37314: OpcodeFamily = 11; CurrentInstrCycles = 22;
37315: {{ uae_s8 src = get_ibyte_prefetch(2);
37316: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
37317: BusCyclePenalty += 2;
37318: { uae_s8 dst = get_byte(dsta);
37319: { refill_prefetch (m68k_getpc(), 2);
37320: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
37321: { int flgs = ((uae_s8)(src)) < 0;
37322: int flgo = ((uae_s8)(dst)) < 0;
37323: int flgn = ((uae_s8)(newv)) < 0;
37324: SET_ZFLG (((uae_s8)(newv)) == 0);
37325: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37326: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
37327: COPY_CARRY;
37328: SET_NFLG (flgn != 0);
37329: m68k_incpc(6);
37330: fill_prefetch_0 ();
37331: put_byte(dsta,newv);
37332: }}}}}}}return 22;
37333: }
37334: unsigned long REGPARAM2 CPUFUNC(op_638_5)(uae_u32 opcode) /* ADD */
37335: {
37336: OpcodeFamily = 11; CurrentInstrCycles = 20;
37337: {{ uae_s8 src = get_ibyte_prefetch(2);
37338: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
37339: { uae_s8 dst = get_byte(dsta);
37340: { refill_prefetch (m68k_getpc(), 2);
37341: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
37342: { int flgs = ((uae_s8)(src)) < 0;
37343: int flgo = ((uae_s8)(dst)) < 0;
37344: int flgn = ((uae_s8)(newv)) < 0;
37345: SET_ZFLG (((uae_s8)(newv)) == 0);
37346: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37347: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
37348: COPY_CARRY;
37349: SET_NFLG (flgn != 0);
37350: m68k_incpc(6);
37351: fill_prefetch_0 ();
37352: put_byte(dsta,newv);
37353: }}}}}}}return 20;
37354: }
37355: unsigned long REGPARAM2 CPUFUNC(op_639_5)(uae_u32 opcode) /* ADD */
37356: {
37357: OpcodeFamily = 11; CurrentInstrCycles = 24;
37358: {{ uae_s8 src = get_ibyte_prefetch(2);
37359: { uaecptr dsta = get_ilong_prefetch(4);
37360: { uae_s8 dst = get_byte(dsta);
37361: { refill_prefetch (m68k_getpc(), 2);
37362: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
37363: { int flgs = ((uae_s8)(src)) < 0;
37364: int flgo = ((uae_s8)(dst)) < 0;
37365: int flgn = ((uae_s8)(newv)) < 0;
37366: SET_ZFLG (((uae_s8)(newv)) == 0);
37367: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37368: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
37369: COPY_CARRY;
37370: SET_NFLG (flgn != 0);
37371: m68k_incpc(8);
37372: fill_prefetch_0 ();
37373: put_byte(dsta,newv);
37374: }}}}}}}return 24;
37375: }
37376: unsigned long REGPARAM2 CPUFUNC(op_640_5)(uae_u32 opcode) /* ADD */
37377: {
37378: uae_u32 dstreg = opcode & 7;
37379: OpcodeFamily = 11; CurrentInstrCycles = 8;
37380: {{ uae_s16 src = get_iword_prefetch(2);
37381: { uae_s16 dst = m68k_dreg(regs, dstreg);
37382: { refill_prefetch (m68k_getpc(), 2);
37383: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
37384: { int flgs = ((uae_s16)(src)) < 0;
37385: int flgo = ((uae_s16)(dst)) < 0;
37386: int flgn = ((uae_s16)(newv)) < 0;
37387: SET_ZFLG (((uae_s16)(newv)) == 0);
37388: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37389: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
37390: COPY_CARRY;
37391: SET_NFLG (flgn != 0);
37392: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
37393: }}}}}}m68k_incpc(4);
37394: fill_prefetch_0 ();
37395: return 8;
37396: }
37397: unsigned long REGPARAM2 CPUFUNC(op_650_5)(uae_u32 opcode) /* ADD */
37398: {
37399: uae_u32 dstreg = opcode & 7;
37400: OpcodeFamily = 11; CurrentInstrCycles = 16;
37401: {{ uae_s16 src = get_iword_prefetch(2);
37402: { uaecptr dsta = m68k_areg(regs, dstreg);
37403: if ((dsta & 1) != 0) {
37404: last_fault_for_exception_3 = dsta;
37405: last_op_for_exception_3 = opcode;
37406: last_addr_for_exception_3 = m68k_getpc() + 4;
37407: Exception(3, 0, M68000_EXC_SRC_CPU);
37408: goto endlabel2285;
37409: }
37410: {{ uae_s16 dst = get_word(dsta);
37411: { refill_prefetch (m68k_getpc(), 2);
37412: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
37413: { int flgs = ((uae_s16)(src)) < 0;
37414: int flgo = ((uae_s16)(dst)) < 0;
37415: int flgn = ((uae_s16)(newv)) < 0;
37416: SET_ZFLG (((uae_s16)(newv)) == 0);
37417: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37418: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
37419: COPY_CARRY;
37420: SET_NFLG (flgn != 0);
37421: m68k_incpc(4);
37422: fill_prefetch_0 ();
37423: put_word(dsta,newv);
37424: }}}}}}}}endlabel2285: ;
37425: return 16;
37426: }
37427: unsigned long REGPARAM2 CPUFUNC(op_658_5)(uae_u32 opcode) /* ADD */
37428: {
37429: uae_u32 dstreg = opcode & 7;
37430: OpcodeFamily = 11; CurrentInstrCycles = 16;
37431: {{ uae_s16 src = get_iword_prefetch(2);
37432: { uaecptr dsta = m68k_areg(regs, dstreg);
37433: if ((dsta & 1) != 0) {
37434: last_fault_for_exception_3 = dsta;
37435: last_op_for_exception_3 = opcode;
37436: last_addr_for_exception_3 = m68k_getpc() + 4;
37437: Exception(3, 0, M68000_EXC_SRC_CPU);
37438: goto endlabel2286;
37439: }
37440: {{ uae_s16 dst = get_word(dsta);
37441: m68k_areg(regs, dstreg) += 2;
37442: { refill_prefetch (m68k_getpc(), 2);
37443: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
37444: { int flgs = ((uae_s16)(src)) < 0;
37445: int flgo = ((uae_s16)(dst)) < 0;
37446: int flgn = ((uae_s16)(newv)) < 0;
37447: SET_ZFLG (((uae_s16)(newv)) == 0);
37448: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37449: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
37450: COPY_CARRY;
37451: SET_NFLG (flgn != 0);
37452: m68k_incpc(4);
37453: fill_prefetch_0 ();
37454: put_word(dsta,newv);
37455: }}}}}}}}endlabel2286: ;
37456: return 16;
37457: }
37458: unsigned long REGPARAM2 CPUFUNC(op_660_5)(uae_u32 opcode) /* ADD */
37459: {
37460: uae_u32 dstreg = opcode & 7;
37461: OpcodeFamily = 11; CurrentInstrCycles = 18;
37462: {{ uae_s16 src = get_iword_prefetch(2);
37463: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
37464: if ((dsta & 1) != 0) {
37465: last_fault_for_exception_3 = dsta;
37466: last_op_for_exception_3 = opcode;
37467: last_addr_for_exception_3 = m68k_getpc() + 4;
37468: Exception(3, 0, M68000_EXC_SRC_CPU);
37469: goto endlabel2287;
37470: }
37471: {{ uae_s16 dst = get_word(dsta);
37472: m68k_areg (regs, dstreg) = dsta;
37473: { refill_prefetch (m68k_getpc(), 2);
37474: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
37475: { int flgs = ((uae_s16)(src)) < 0;
37476: int flgo = ((uae_s16)(dst)) < 0;
37477: int flgn = ((uae_s16)(newv)) < 0;
37478: SET_ZFLG (((uae_s16)(newv)) == 0);
37479: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37480: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
37481: COPY_CARRY;
37482: SET_NFLG (flgn != 0);
37483: m68k_incpc(4);
37484: fill_prefetch_0 ();
37485: put_word(dsta,newv);
37486: }}}}}}}}endlabel2287: ;
37487: return 18;
37488: }
37489: unsigned long REGPARAM2 CPUFUNC(op_668_5)(uae_u32 opcode) /* ADD */
37490: {
37491: uae_u32 dstreg = opcode & 7;
37492: OpcodeFamily = 11; CurrentInstrCycles = 20;
37493: {{ uae_s16 src = get_iword_prefetch(2);
37494: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
37495: if ((dsta & 1) != 0) {
37496: last_fault_for_exception_3 = dsta;
37497: last_op_for_exception_3 = opcode;
37498: last_addr_for_exception_3 = m68k_getpc() + 6;
37499: Exception(3, 0, M68000_EXC_SRC_CPU);
37500: goto endlabel2288;
37501: }
37502: {{ uae_s16 dst = get_word(dsta);
37503: { refill_prefetch (m68k_getpc(), 2);
37504: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
37505: { int flgs = ((uae_s16)(src)) < 0;
37506: int flgo = ((uae_s16)(dst)) < 0;
37507: int flgn = ((uae_s16)(newv)) < 0;
37508: SET_ZFLG (((uae_s16)(newv)) == 0);
37509: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37510: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
37511: COPY_CARRY;
37512: SET_NFLG (flgn != 0);
37513: m68k_incpc(6);
37514: fill_prefetch_0 ();
37515: put_word(dsta,newv);
37516: }}}}}}}}endlabel2288: ;
37517: return 20;
37518: }
37519: unsigned long REGPARAM2 CPUFUNC(op_670_5)(uae_u32 opcode) /* ADD */
37520: {
37521: uae_u32 dstreg = opcode & 7;
37522: OpcodeFamily = 11; CurrentInstrCycles = 22;
37523: {{ uae_s16 src = get_iword_prefetch(2);
37524: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
37525: BusCyclePenalty += 2;
37526: if ((dsta & 1) != 0) {
37527: last_fault_for_exception_3 = dsta;
37528: last_op_for_exception_3 = opcode;
37529: last_addr_for_exception_3 = m68k_getpc() + 6;
37530: Exception(3, 0, M68000_EXC_SRC_CPU);
37531: goto endlabel2289;
37532: }
37533: {{ uae_s16 dst = get_word(dsta);
37534: { refill_prefetch (m68k_getpc(), 2);
37535: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
37536: { int flgs = ((uae_s16)(src)) < 0;
37537: int flgo = ((uae_s16)(dst)) < 0;
37538: int flgn = ((uae_s16)(newv)) < 0;
37539: SET_ZFLG (((uae_s16)(newv)) == 0);
37540: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37541: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
37542: COPY_CARRY;
37543: SET_NFLG (flgn != 0);
37544: m68k_incpc(6);
37545: fill_prefetch_0 ();
37546: put_word(dsta,newv);
37547: }}}}}}}}endlabel2289: ;
37548: return 22;
37549: }
37550: unsigned long REGPARAM2 CPUFUNC(op_678_5)(uae_u32 opcode) /* ADD */
37551: {
37552: OpcodeFamily = 11; CurrentInstrCycles = 20;
37553: {{ uae_s16 src = get_iword_prefetch(2);
37554: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
37555: if ((dsta & 1) != 0) {
37556: last_fault_for_exception_3 = dsta;
37557: last_op_for_exception_3 = opcode;
37558: last_addr_for_exception_3 = m68k_getpc() + 6;
37559: Exception(3, 0, M68000_EXC_SRC_CPU);
37560: goto endlabel2290;
37561: }
37562: {{ uae_s16 dst = get_word(dsta);
37563: { refill_prefetch (m68k_getpc(), 2);
37564: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
37565: { int flgs = ((uae_s16)(src)) < 0;
37566: int flgo = ((uae_s16)(dst)) < 0;
37567: int flgn = ((uae_s16)(newv)) < 0;
37568: SET_ZFLG (((uae_s16)(newv)) == 0);
37569: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37570: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
37571: COPY_CARRY;
37572: SET_NFLG (flgn != 0);
37573: m68k_incpc(6);
37574: fill_prefetch_0 ();
37575: put_word(dsta,newv);
37576: }}}}}}}}endlabel2290: ;
37577: return 20;
37578: }
37579: unsigned long REGPARAM2 CPUFUNC(op_679_5)(uae_u32 opcode) /* ADD */
37580: {
37581: OpcodeFamily = 11; CurrentInstrCycles = 24;
37582: {{ uae_s16 src = get_iword_prefetch(2);
37583: { uaecptr dsta = get_ilong_prefetch(4);
37584: if ((dsta & 1) != 0) {
37585: last_fault_for_exception_3 = dsta;
37586: last_op_for_exception_3 = opcode;
37587: last_addr_for_exception_3 = m68k_getpc() + 8;
37588: Exception(3, 0, M68000_EXC_SRC_CPU);
37589: goto endlabel2291;
37590: }
37591: {{ uae_s16 dst = get_word(dsta);
37592: { refill_prefetch (m68k_getpc(), 2);
37593: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
37594: { int flgs = ((uae_s16)(src)) < 0;
37595: int flgo = ((uae_s16)(dst)) < 0;
37596: int flgn = ((uae_s16)(newv)) < 0;
37597: SET_ZFLG (((uae_s16)(newv)) == 0);
37598: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37599: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
37600: COPY_CARRY;
37601: SET_NFLG (flgn != 0);
37602: m68k_incpc(8);
37603: fill_prefetch_0 ();
37604: put_word(dsta,newv);
37605: }}}}}}}}endlabel2291: ;
37606: return 24;
37607: }
37608: unsigned long REGPARAM2 CPUFUNC(op_680_5)(uae_u32 opcode) /* ADD */
37609: {
37610: uae_u32 dstreg = opcode & 7;
37611: OpcodeFamily = 11; CurrentInstrCycles = 16;
37612: {{ uae_s32 src = get_ilong_prefetch(2);
37613: { uae_s32 dst = m68k_dreg(regs, dstreg);
37614: { refill_prefetch (m68k_getpc(), 2);
37615: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
37616: { int flgs = ((uae_s32)(src)) < 0;
37617: int flgo = ((uae_s32)(dst)) < 0;
37618: int flgn = ((uae_s32)(newv)) < 0;
37619: SET_ZFLG (((uae_s32)(newv)) == 0);
37620: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37621: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
37622: COPY_CARRY;
37623: SET_NFLG (flgn != 0);
37624: m68k_dreg(regs, dstreg) = (newv);
37625: }}}}}}m68k_incpc(6);
37626: fill_prefetch_0 ();
37627: return 16;
37628: }
37629: unsigned long REGPARAM2 CPUFUNC(op_690_5)(uae_u32 opcode) /* ADD */
37630: {
37631: uae_u32 dstreg = opcode & 7;
37632: OpcodeFamily = 11; CurrentInstrCycles = 28;
37633: {{ uae_s32 src = get_ilong_prefetch(2);
37634: { uaecptr dsta = m68k_areg(regs, dstreg);
37635: if ((dsta & 1) != 0) {
37636: last_fault_for_exception_3 = dsta;
37637: last_op_for_exception_3 = opcode;
37638: last_addr_for_exception_3 = m68k_getpc() + 6;
37639: Exception(3, 0, M68000_EXC_SRC_CPU);
37640: goto endlabel2293;
37641: }
37642: {{ uae_s32 dst = get_long(dsta);
37643: { refill_prefetch (m68k_getpc(), 2);
37644: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
37645: { int flgs = ((uae_s32)(src)) < 0;
37646: int flgo = ((uae_s32)(dst)) < 0;
37647: int flgn = ((uae_s32)(newv)) < 0;
37648: SET_ZFLG (((uae_s32)(newv)) == 0);
37649: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37650: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
37651: COPY_CARRY;
37652: SET_NFLG (flgn != 0);
37653: m68k_incpc(6);
37654: fill_prefetch_0 ();
37655: put_long(dsta,newv);
37656: }}}}}}}}endlabel2293: ;
37657: return 28;
37658: }
37659: unsigned long REGPARAM2 CPUFUNC(op_698_5)(uae_u32 opcode) /* ADD */
37660: {
37661: uae_u32 dstreg = opcode & 7;
37662: OpcodeFamily = 11; CurrentInstrCycles = 28;
37663: {{ uae_s32 src = get_ilong_prefetch(2);
37664: { uaecptr dsta = m68k_areg(regs, dstreg);
37665: if ((dsta & 1) != 0) {
37666: last_fault_for_exception_3 = dsta;
37667: last_op_for_exception_3 = opcode;
37668: last_addr_for_exception_3 = m68k_getpc() + 6;
37669: Exception(3, 0, M68000_EXC_SRC_CPU);
37670: goto endlabel2294;
37671: }
37672: {{ uae_s32 dst = get_long(dsta);
37673: m68k_areg(regs, dstreg) += 4;
37674: { refill_prefetch (m68k_getpc(), 2);
37675: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
37676: { int flgs = ((uae_s32)(src)) < 0;
37677: int flgo = ((uae_s32)(dst)) < 0;
37678: int flgn = ((uae_s32)(newv)) < 0;
37679: SET_ZFLG (((uae_s32)(newv)) == 0);
37680: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37681: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
37682: COPY_CARRY;
37683: SET_NFLG (flgn != 0);
37684: m68k_incpc(6);
37685: fill_prefetch_0 ();
37686: put_long(dsta,newv);
37687: }}}}}}}}endlabel2294: ;
37688: return 28;
37689: }
37690: unsigned long REGPARAM2 CPUFUNC(op_6a0_5)(uae_u32 opcode) /* ADD */
37691: {
37692: uae_u32 dstreg = opcode & 7;
37693: OpcodeFamily = 11; CurrentInstrCycles = 30;
37694: {{ uae_s32 src = get_ilong_prefetch(2);
37695: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
37696: if ((dsta & 1) != 0) {
37697: last_fault_for_exception_3 = dsta;
37698: last_op_for_exception_3 = opcode;
37699: last_addr_for_exception_3 = m68k_getpc() + 6;
37700: Exception(3, 0, M68000_EXC_SRC_CPU);
37701: goto endlabel2295;
37702: }
37703: {{ uae_s32 dst = get_long(dsta);
37704: m68k_areg (regs, dstreg) = dsta;
37705: { refill_prefetch (m68k_getpc(), 2);
37706: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
37707: { int flgs = ((uae_s32)(src)) < 0;
37708: int flgo = ((uae_s32)(dst)) < 0;
37709: int flgn = ((uae_s32)(newv)) < 0;
37710: SET_ZFLG (((uae_s32)(newv)) == 0);
37711: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37712: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
37713: COPY_CARRY;
37714: SET_NFLG (flgn != 0);
37715: m68k_incpc(6);
37716: fill_prefetch_0 ();
37717: put_long(dsta,newv);
37718: }}}}}}}}endlabel2295: ;
37719: return 30;
37720: }
37721: unsigned long REGPARAM2 CPUFUNC(op_6a8_5)(uae_u32 opcode) /* ADD */
37722: {
37723: uae_u32 dstreg = opcode & 7;
37724: OpcodeFamily = 11; CurrentInstrCycles = 32;
37725: {{ uae_s32 src = get_ilong_prefetch(2);
37726: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
37727: if ((dsta & 1) != 0) {
37728: last_fault_for_exception_3 = dsta;
37729: last_op_for_exception_3 = opcode;
37730: last_addr_for_exception_3 = m68k_getpc() + 8;
37731: Exception(3, 0, M68000_EXC_SRC_CPU);
37732: goto endlabel2296;
37733: }
37734: {{ uae_s32 dst = get_long(dsta);
37735: { refill_prefetch (m68k_getpc(), 2);
37736: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
37737: { int flgs = ((uae_s32)(src)) < 0;
37738: int flgo = ((uae_s32)(dst)) < 0;
37739: int flgn = ((uae_s32)(newv)) < 0;
37740: SET_ZFLG (((uae_s32)(newv)) == 0);
37741: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37742: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
37743: COPY_CARRY;
37744: SET_NFLG (flgn != 0);
37745: m68k_incpc(8);
37746: fill_prefetch_0 ();
37747: put_long(dsta,newv);
37748: }}}}}}}}endlabel2296: ;
37749: return 32;
37750: }
37751: unsigned long REGPARAM2 CPUFUNC(op_6b0_5)(uae_u32 opcode) /* ADD */
37752: {
37753: uae_u32 dstreg = opcode & 7;
37754: OpcodeFamily = 11; CurrentInstrCycles = 34;
37755: {{ uae_s32 src = get_ilong_prefetch(2);
37756: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
37757: BusCyclePenalty += 2;
37758: if ((dsta & 1) != 0) {
37759: last_fault_for_exception_3 = dsta;
37760: last_op_for_exception_3 = opcode;
37761: last_addr_for_exception_3 = m68k_getpc() + 8;
37762: Exception(3, 0, M68000_EXC_SRC_CPU);
37763: goto endlabel2297;
37764: }
37765: {{ uae_s32 dst = get_long(dsta);
37766: { refill_prefetch (m68k_getpc(), 2);
37767: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
37768: { int flgs = ((uae_s32)(src)) < 0;
37769: int flgo = ((uae_s32)(dst)) < 0;
37770: int flgn = ((uae_s32)(newv)) < 0;
37771: SET_ZFLG (((uae_s32)(newv)) == 0);
37772: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37773: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
37774: COPY_CARRY;
37775: SET_NFLG (flgn != 0);
37776: m68k_incpc(8);
37777: fill_prefetch_0 ();
37778: put_long(dsta,newv);
37779: }}}}}}}}endlabel2297: ;
37780: return 34;
37781: }
37782: unsigned long REGPARAM2 CPUFUNC(op_6b8_5)(uae_u32 opcode) /* ADD */
37783: {
37784: OpcodeFamily = 11; CurrentInstrCycles = 32;
37785: {{ uae_s32 src = get_ilong_prefetch(2);
37786: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
37787: if ((dsta & 1) != 0) {
37788: last_fault_for_exception_3 = dsta;
37789: last_op_for_exception_3 = opcode;
37790: last_addr_for_exception_3 = m68k_getpc() + 8;
37791: Exception(3, 0, M68000_EXC_SRC_CPU);
37792: goto endlabel2298;
37793: }
37794: {{ uae_s32 dst = get_long(dsta);
37795: { refill_prefetch (m68k_getpc(), 2);
37796: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
37797: { int flgs = ((uae_s32)(src)) < 0;
37798: int flgo = ((uae_s32)(dst)) < 0;
37799: int flgn = ((uae_s32)(newv)) < 0;
37800: SET_ZFLG (((uae_s32)(newv)) == 0);
37801: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37802: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
37803: COPY_CARRY;
37804: SET_NFLG (flgn != 0);
37805: m68k_incpc(8);
37806: fill_prefetch_0 ();
37807: put_long(dsta,newv);
37808: }}}}}}}}endlabel2298: ;
37809: return 32;
37810: }
37811: unsigned long REGPARAM2 CPUFUNC(op_6b9_5)(uae_u32 opcode) /* ADD */
37812: {
37813: OpcodeFamily = 11; CurrentInstrCycles = 36;
37814: {{ uae_s32 src = get_ilong_prefetch(2);
37815: { uaecptr dsta = get_ilong_prefetch(6);
37816: if ((dsta & 1) != 0) {
37817: last_fault_for_exception_3 = dsta;
37818: last_op_for_exception_3 = opcode;
37819: last_addr_for_exception_3 = m68k_getpc() + 10;
37820: Exception(3, 0, M68000_EXC_SRC_CPU);
37821: goto endlabel2299;
37822: }
37823: {{ uae_s32 dst = get_long(dsta);
37824: { refill_prefetch (m68k_getpc(), 2);
37825: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
37826: { int flgs = ((uae_s32)(src)) < 0;
37827: int flgo = ((uae_s32)(dst)) < 0;
37828: int flgn = ((uae_s32)(newv)) < 0;
37829: SET_ZFLG (((uae_s32)(newv)) == 0);
37830: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
37831: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
37832: COPY_CARRY;
37833: SET_NFLG (flgn != 0);
37834: m68k_incpc(10);
37835: fill_prefetch_0 ();
37836: put_long(dsta,newv);
37837: }}}}}}}}endlabel2299: ;
37838: return 36;
37839: }
37840: unsigned long REGPARAM2 CPUFUNC(op_800_5)(uae_u32 opcode) /* BTST */
37841: {
37842: uae_u32 dstreg = opcode & 7;
37843: OpcodeFamily = 21; CurrentInstrCycles = 10;
37844: {{ uae_s16 src = get_iword_prefetch(2);
37845: { uae_s32 dst = m68k_dreg(regs, dstreg);
37846: src &= 31;
37847: SET_ZFLG (1 ^ ((dst >> src) & 1));
37848: }}}m68k_incpc(4);
37849: fill_prefetch_0 ();
37850: return 10;
37851: }
37852: unsigned long REGPARAM2 CPUFUNC(op_810_5)(uae_u32 opcode) /* BTST */
37853: {
37854: uae_u32 dstreg = opcode & 7;
37855: OpcodeFamily = 21; CurrentInstrCycles = 12;
37856: {{ uae_s16 src = get_iword_prefetch(2);
37857: { uaecptr dsta = m68k_areg(regs, dstreg);
37858: { uae_s8 dst = get_byte(dsta);
37859: src &= 7;
37860: SET_ZFLG (1 ^ ((dst >> src) & 1));
37861: }}}}m68k_incpc(4);
37862: fill_prefetch_0 ();
37863: return 12;
37864: }
37865: unsigned long REGPARAM2 CPUFUNC(op_818_5)(uae_u32 opcode) /* BTST */
37866: {
37867: uae_u32 dstreg = opcode & 7;
37868: OpcodeFamily = 21; CurrentInstrCycles = 12;
37869: {{ uae_s16 src = get_iword_prefetch(2);
37870: { uaecptr dsta = m68k_areg(regs, dstreg);
37871: { uae_s8 dst = get_byte(dsta);
37872: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
37873: src &= 7;
37874: SET_ZFLG (1 ^ ((dst >> src) & 1));
37875: }}}}m68k_incpc(4);
37876: fill_prefetch_0 ();
37877: return 12;
37878: }
37879: unsigned long REGPARAM2 CPUFUNC(op_820_5)(uae_u32 opcode) /* BTST */
37880: {
37881: uae_u32 dstreg = opcode & 7;
37882: OpcodeFamily = 21; CurrentInstrCycles = 14;
37883: {{ uae_s16 src = get_iword_prefetch(2);
37884: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
37885: { uae_s8 dst = get_byte(dsta);
37886: m68k_areg (regs, dstreg) = dsta;
37887: src &= 7;
37888: SET_ZFLG (1 ^ ((dst >> src) & 1));
37889: }}}}m68k_incpc(4);
37890: fill_prefetch_0 ();
37891: return 14;
37892: }
37893: unsigned long REGPARAM2 CPUFUNC(op_828_5)(uae_u32 opcode) /* BTST */
37894: {
37895: uae_u32 dstreg = opcode & 7;
37896: OpcodeFamily = 21; CurrentInstrCycles = 16;
37897: {{ uae_s16 src = get_iword_prefetch(2);
37898: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
37899: { uae_s8 dst = get_byte(dsta);
37900: src &= 7;
37901: SET_ZFLG (1 ^ ((dst >> src) & 1));
37902: }}}}m68k_incpc(6);
37903: fill_prefetch_0 ();
37904: return 16;
37905: }
37906: unsigned long REGPARAM2 CPUFUNC(op_830_5)(uae_u32 opcode) /* BTST */
37907: {
37908: uae_u32 dstreg = opcode & 7;
37909: OpcodeFamily = 21; CurrentInstrCycles = 18;
37910: {{ uae_s16 src = get_iword_prefetch(2);
37911: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
37912: BusCyclePenalty += 2;
37913: { uae_s8 dst = get_byte(dsta);
37914: src &= 7;
37915: SET_ZFLG (1 ^ ((dst >> src) & 1));
37916: }}}}m68k_incpc(6);
37917: fill_prefetch_0 ();
37918: return 18;
37919: }
37920: unsigned long REGPARAM2 CPUFUNC(op_838_5)(uae_u32 opcode) /* BTST */
37921: {
37922: OpcodeFamily = 21; CurrentInstrCycles = 16;
37923: {{ uae_s16 src = get_iword_prefetch(2);
37924: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
37925: { uae_s8 dst = get_byte(dsta);
37926: src &= 7;
37927: SET_ZFLG (1 ^ ((dst >> src) & 1));
37928: }}}}m68k_incpc(6);
37929: fill_prefetch_0 ();
37930: return 16;
37931: }
37932: unsigned long REGPARAM2 CPUFUNC(op_839_5)(uae_u32 opcode) /* BTST */
37933: {
37934: OpcodeFamily = 21; CurrentInstrCycles = 20;
37935: {{ uae_s16 src = get_iword_prefetch(2);
37936: { uaecptr dsta = get_ilong_prefetch(4);
37937: { uae_s8 dst = get_byte(dsta);
37938: src &= 7;
37939: SET_ZFLG (1 ^ ((dst >> src) & 1));
37940: }}}}m68k_incpc(8);
37941: fill_prefetch_0 ();
37942: return 20;
37943: }
37944: unsigned long REGPARAM2 CPUFUNC(op_83a_5)(uae_u32 opcode) /* BTST */
37945: {
37946: uae_u32 dstreg = 2;
37947: OpcodeFamily = 21; CurrentInstrCycles = 16;
37948: {{ uae_s16 src = get_iword_prefetch(2);
37949: { uaecptr dsta = m68k_getpc () + 4;
37950: dsta += (uae_s32)(uae_s16)get_iword_prefetch(4);
37951: { uae_s8 dst = get_byte(dsta);
37952: src &= 7;
37953: SET_ZFLG (1 ^ ((dst >> src) & 1));
37954: }}}}m68k_incpc(6);
37955: fill_prefetch_0 ();
37956: return 16;
37957: }
37958: unsigned long REGPARAM2 CPUFUNC(op_83b_5)(uae_u32 opcode) /* BTST */
37959: {
37960: uae_u32 dstreg = 3;
37961: OpcodeFamily = 21; CurrentInstrCycles = 18;
37962: {{ uae_s16 src = get_iword_prefetch(2);
37963: { uaecptr tmppc = m68k_getpc() + 4;
37964: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4));
37965: BusCyclePenalty += 2;
37966: { uae_s8 dst = get_byte(dsta);
37967: src &= 7;
37968: SET_ZFLG (1 ^ ((dst >> src) & 1));
37969: }}}}m68k_incpc(6);
37970: fill_prefetch_0 ();
37971: return 18;
37972: }
37973: unsigned long REGPARAM2 CPUFUNC(op_83c_5)(uae_u32 opcode) /* BTST */
37974: {
37975: OpcodeFamily = 21; CurrentInstrCycles = 12;
37976: {{ uae_s16 src = get_iword_prefetch(2);
37977: { uae_s8 dst = get_ibyte_prefetch(4);
37978: src &= 7;
37979: SET_ZFLG (1 ^ ((dst >> src) & 1));
37980: }}}m68k_incpc(6);
37981: fill_prefetch_0 ();
37982: return 12;
37983: }
37984: unsigned long REGPARAM2 CPUFUNC(op_840_5)(uae_u32 opcode) /* BCHG */
37985: {
37986: uae_u32 dstreg = opcode & 7;
37987: OpcodeFamily = 22; CurrentInstrCycles = 12;
37988: {{ uae_s16 src = get_iword_prefetch(2);
37989: { uae_s32 dst = m68k_dreg(regs, dstreg);
37990: src &= 31;
37991: dst ^= (1 << src);
37992: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
37993: m68k_dreg(regs, dstreg) = (dst);
37994: }}}m68k_incpc(4);
37995: fill_prefetch_0 ();
37996: return 12;
37997: }
37998: unsigned long REGPARAM2 CPUFUNC(op_850_5)(uae_u32 opcode) /* BCHG */
37999: {
38000: uae_u32 dstreg = opcode & 7;
38001: OpcodeFamily = 22; CurrentInstrCycles = 16;
38002: {{ uae_s16 src = get_iword_prefetch(2);
38003: { uaecptr dsta = m68k_areg(regs, dstreg);
38004: { uae_s8 dst = get_byte(dsta);
38005: src &= 7;
38006: dst ^= (1 << src);
38007: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
38008: m68k_incpc(4);
38009: fill_prefetch_0 ();
38010: put_byte(dsta,dst);
38011: }}}}return 16;
38012: }
38013: unsigned long REGPARAM2 CPUFUNC(op_858_5)(uae_u32 opcode) /* BCHG */
38014: {
38015: uae_u32 dstreg = opcode & 7;
38016: OpcodeFamily = 22; CurrentInstrCycles = 16;
38017: {{ uae_s16 src = get_iword_prefetch(2);
38018: { uaecptr dsta = m68k_areg(regs, dstreg);
38019: { uae_s8 dst = get_byte(dsta);
38020: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
38021: src &= 7;
38022: dst ^= (1 << src);
38023: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
38024: m68k_incpc(4);
38025: fill_prefetch_0 ();
38026: put_byte(dsta,dst);
38027: }}}}return 16;
38028: }
38029: unsigned long REGPARAM2 CPUFUNC(op_860_5)(uae_u32 opcode) /* BCHG */
38030: {
38031: uae_u32 dstreg = opcode & 7;
38032: OpcodeFamily = 22; CurrentInstrCycles = 18;
38033: {{ uae_s16 src = get_iword_prefetch(2);
38034: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
38035: { uae_s8 dst = get_byte(dsta);
38036: m68k_areg (regs, dstreg) = dsta;
38037: src &= 7;
38038: dst ^= (1 << src);
38039: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
38040: m68k_incpc(4);
38041: fill_prefetch_0 ();
38042: put_byte(dsta,dst);
38043: }}}}return 18;
38044: }
38045: unsigned long REGPARAM2 CPUFUNC(op_868_5)(uae_u32 opcode) /* BCHG */
38046: {
38047: uae_u32 dstreg = opcode & 7;
38048: OpcodeFamily = 22; CurrentInstrCycles = 20;
38049: {{ uae_s16 src = get_iword_prefetch(2);
38050: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
38051: { uae_s8 dst = get_byte(dsta);
38052: src &= 7;
38053: dst ^= (1 << src);
38054: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
38055: m68k_incpc(6);
38056: fill_prefetch_0 ();
38057: put_byte(dsta,dst);
38058: }}}}return 20;
38059: }
38060: unsigned long REGPARAM2 CPUFUNC(op_870_5)(uae_u32 opcode) /* BCHG */
38061: {
38062: uae_u32 dstreg = opcode & 7;
38063: OpcodeFamily = 22; CurrentInstrCycles = 22;
38064: {{ uae_s16 src = get_iword_prefetch(2);
38065: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
38066: BusCyclePenalty += 2;
38067: { uae_s8 dst = get_byte(dsta);
38068: src &= 7;
38069: dst ^= (1 << src);
38070: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
38071: m68k_incpc(6);
38072: fill_prefetch_0 ();
38073: put_byte(dsta,dst);
38074: }}}}return 22;
38075: }
38076: unsigned long REGPARAM2 CPUFUNC(op_878_5)(uae_u32 opcode) /* BCHG */
38077: {
38078: OpcodeFamily = 22; CurrentInstrCycles = 20;
38079: {{ uae_s16 src = get_iword_prefetch(2);
38080: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
38081: { uae_s8 dst = get_byte(dsta);
38082: src &= 7;
38083: dst ^= (1 << src);
38084: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
38085: m68k_incpc(6);
38086: fill_prefetch_0 ();
38087: put_byte(dsta,dst);
38088: }}}}return 20;
38089: }
38090: unsigned long REGPARAM2 CPUFUNC(op_879_5)(uae_u32 opcode) /* BCHG */
38091: {
38092: OpcodeFamily = 22; CurrentInstrCycles = 24;
38093: {{ uae_s16 src = get_iword_prefetch(2);
38094: { uaecptr dsta = get_ilong_prefetch(4);
38095: { uae_s8 dst = get_byte(dsta);
38096: src &= 7;
38097: dst ^= (1 << src);
38098: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
38099: m68k_incpc(8);
38100: fill_prefetch_0 ();
38101: put_byte(dsta,dst);
38102: }}}}return 24;
38103: }
38104: unsigned long REGPARAM2 CPUFUNC(op_87a_5)(uae_u32 opcode) /* BCHG */
38105: {
38106: uae_u32 dstreg = 2;
38107: OpcodeFamily = 22; CurrentInstrCycles = 20;
38108: {{ uae_s16 src = get_iword_prefetch(2);
38109: { uaecptr dsta = m68k_getpc () + 4;
38110: dsta += (uae_s32)(uae_s16)get_iword_prefetch(4);
38111: { uae_s8 dst = get_byte(dsta);
38112: src &= 7;
38113: dst ^= (1 << src);
38114: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
38115: m68k_incpc(6);
38116: fill_prefetch_0 ();
38117: put_byte(dsta,dst);
38118: }}}}return 20;
38119: }
38120: unsigned long REGPARAM2 CPUFUNC(op_87b_5)(uae_u32 opcode) /* BCHG */
38121: {
38122: uae_u32 dstreg = 3;
38123: OpcodeFamily = 22; CurrentInstrCycles = 22;
38124: {{ uae_s16 src = get_iword_prefetch(2);
38125: { uaecptr tmppc = m68k_getpc() + 4;
38126: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4));
38127: BusCyclePenalty += 2;
38128: { uae_s8 dst = get_byte(dsta);
38129: src &= 7;
38130: dst ^= (1 << src);
38131: SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
38132: m68k_incpc(6);
38133: fill_prefetch_0 ();
38134: put_byte(dsta,dst);
38135: }}}}return 22;
38136: }
38137: unsigned long REGPARAM2 CPUFUNC(op_880_5)(uae_u32 opcode) /* BCLR */
38138: {
38139: uae_u32 dstreg = opcode & 7;
38140: OpcodeFamily = 23; CurrentInstrCycles = 14;
38141: {{ uae_s16 src = get_iword_prefetch(2);
38142: { uae_s32 dst = m68k_dreg(regs, dstreg);
38143: src &= 31;
38144: SET_ZFLG (1 ^ ((dst >> src) & 1));
38145: dst &= ~(1 << src);
38146: m68k_dreg(regs, dstreg) = (dst);
38147: if ( src < 16 ) { m68k_incpc(4); return 12; }
38148: }}}m68k_incpc(4);
38149: fill_prefetch_0 ();
38150: return 14;
38151: }
38152: unsigned long REGPARAM2 CPUFUNC(op_890_5)(uae_u32 opcode) /* BCLR */
38153: {
38154: uae_u32 dstreg = opcode & 7;
38155: OpcodeFamily = 23; CurrentInstrCycles = 16;
38156: {{ uae_s16 src = get_iword_prefetch(2);
38157: { uaecptr dsta = m68k_areg(regs, dstreg);
38158: { uae_s8 dst = get_byte(dsta);
38159: src &= 7;
38160: SET_ZFLG (1 ^ ((dst >> src) & 1));
38161: dst &= ~(1 << src);
38162: m68k_incpc(4);
38163: fill_prefetch_0 ();
38164: put_byte(dsta,dst);
38165: }}}}return 16;
38166: }
38167: unsigned long REGPARAM2 CPUFUNC(op_898_5)(uae_u32 opcode) /* BCLR */
38168: {
38169: uae_u32 dstreg = opcode & 7;
38170: OpcodeFamily = 23; CurrentInstrCycles = 16;
38171: {{ uae_s16 src = get_iword_prefetch(2);
38172: { uaecptr dsta = m68k_areg(regs, dstreg);
38173: { uae_s8 dst = get_byte(dsta);
38174: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
38175: src &= 7;
38176: SET_ZFLG (1 ^ ((dst >> src) & 1));
38177: dst &= ~(1 << src);
38178: m68k_incpc(4);
38179: fill_prefetch_0 ();
38180: put_byte(dsta,dst);
38181: }}}}return 16;
38182: }
38183: unsigned long REGPARAM2 CPUFUNC(op_8a0_5)(uae_u32 opcode) /* BCLR */
38184: {
38185: uae_u32 dstreg = opcode & 7;
38186: OpcodeFamily = 23; CurrentInstrCycles = 18;
38187: {{ uae_s16 src = get_iword_prefetch(2);
38188: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
38189: { uae_s8 dst = get_byte(dsta);
38190: m68k_areg (regs, dstreg) = dsta;
38191: src &= 7;
38192: SET_ZFLG (1 ^ ((dst >> src) & 1));
38193: dst &= ~(1 << src);
38194: m68k_incpc(4);
38195: fill_prefetch_0 ();
38196: put_byte(dsta,dst);
38197: }}}}return 18;
38198: }
38199: unsigned long REGPARAM2 CPUFUNC(op_8a8_5)(uae_u32 opcode) /* BCLR */
38200: {
38201: uae_u32 dstreg = opcode & 7;
38202: OpcodeFamily = 23; CurrentInstrCycles = 20;
38203: {{ uae_s16 src = get_iword_prefetch(2);
38204: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
38205: { uae_s8 dst = get_byte(dsta);
38206: src &= 7;
38207: SET_ZFLG (1 ^ ((dst >> src) & 1));
38208: dst &= ~(1 << src);
38209: m68k_incpc(6);
38210: fill_prefetch_0 ();
38211: put_byte(dsta,dst);
38212: }}}}return 20;
38213: }
38214: unsigned long REGPARAM2 CPUFUNC(op_8b0_5)(uae_u32 opcode) /* BCLR */
38215: {
38216: uae_u32 dstreg = opcode & 7;
38217: OpcodeFamily = 23; CurrentInstrCycles = 22;
38218: {{ uae_s16 src = get_iword_prefetch(2);
38219: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
38220: BusCyclePenalty += 2;
38221: { uae_s8 dst = get_byte(dsta);
38222: src &= 7;
38223: SET_ZFLG (1 ^ ((dst >> src) & 1));
38224: dst &= ~(1 << src);
38225: m68k_incpc(6);
38226: fill_prefetch_0 ();
38227: put_byte(dsta,dst);
38228: }}}}return 22;
38229: }
38230: unsigned long REGPARAM2 CPUFUNC(op_8b8_5)(uae_u32 opcode) /* BCLR */
38231: {
38232: OpcodeFamily = 23; CurrentInstrCycles = 20;
38233: {{ uae_s16 src = get_iword_prefetch(2);
38234: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
38235: { uae_s8 dst = get_byte(dsta);
38236: src &= 7;
38237: SET_ZFLG (1 ^ ((dst >> src) & 1));
38238: dst &= ~(1 << src);
38239: m68k_incpc(6);
38240: fill_prefetch_0 ();
38241: put_byte(dsta,dst);
38242: }}}}return 20;
38243: }
38244: unsigned long REGPARAM2 CPUFUNC(op_8b9_5)(uae_u32 opcode) /* BCLR */
38245: {
38246: OpcodeFamily = 23; CurrentInstrCycles = 24;
38247: {{ uae_s16 src = get_iword_prefetch(2);
38248: { uaecptr dsta = get_ilong_prefetch(4);
38249: { uae_s8 dst = get_byte(dsta);
38250: src &= 7;
38251: SET_ZFLG (1 ^ ((dst >> src) & 1));
38252: dst &= ~(1 << src);
38253: m68k_incpc(8);
38254: fill_prefetch_0 ();
38255: put_byte(dsta,dst);
38256: }}}}return 24;
38257: }
38258: unsigned long REGPARAM2 CPUFUNC(op_8ba_5)(uae_u32 opcode) /* BCLR */
38259: {
38260: uae_u32 dstreg = 2;
38261: OpcodeFamily = 23; CurrentInstrCycles = 20;
38262: {{ uae_s16 src = get_iword_prefetch(2);
38263: { uaecptr dsta = m68k_getpc () + 4;
38264: dsta += (uae_s32)(uae_s16)get_iword_prefetch(4);
38265: { uae_s8 dst = get_byte(dsta);
38266: src &= 7;
38267: SET_ZFLG (1 ^ ((dst >> src) & 1));
38268: dst &= ~(1 << src);
38269: m68k_incpc(6);
38270: fill_prefetch_0 ();
38271: put_byte(dsta,dst);
38272: }}}}return 20;
38273: }
38274: unsigned long REGPARAM2 CPUFUNC(op_8bb_5)(uae_u32 opcode) /* BCLR */
38275: {
38276: uae_u32 dstreg = 3;
38277: OpcodeFamily = 23; CurrentInstrCycles = 22;
38278: {{ uae_s16 src = get_iword_prefetch(2);
38279: { uaecptr tmppc = m68k_getpc() + 4;
38280: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4));
38281: BusCyclePenalty += 2;
38282: { uae_s8 dst = get_byte(dsta);
38283: src &= 7;
38284: SET_ZFLG (1 ^ ((dst >> src) & 1));
38285: dst &= ~(1 << src);
38286: m68k_incpc(6);
38287: fill_prefetch_0 ();
38288: put_byte(dsta,dst);
38289: }}}}return 22;
38290: }
38291: unsigned long REGPARAM2 CPUFUNC(op_8c0_5)(uae_u32 opcode) /* BSET */
38292: {
38293: uae_u32 dstreg = opcode & 7;
38294: OpcodeFamily = 24; CurrentInstrCycles = 12;
38295: {{ uae_s16 src = get_iword_prefetch(2);
38296: { uae_s32 dst = m68k_dreg(regs, dstreg);
38297: src &= 31;
38298: SET_ZFLG (1 ^ ((dst >> src) & 1));
38299: dst |= (1 << src);
38300: m68k_dreg(regs, dstreg) = (dst);
38301: }}}m68k_incpc(4);
38302: fill_prefetch_0 ();
38303: return 12;
38304: }
38305: unsigned long REGPARAM2 CPUFUNC(op_8d0_5)(uae_u32 opcode) /* BSET */
38306: {
38307: uae_u32 dstreg = opcode & 7;
38308: OpcodeFamily = 24; CurrentInstrCycles = 16;
38309: {{ uae_s16 src = get_iword_prefetch(2);
38310: { uaecptr dsta = m68k_areg(regs, dstreg);
38311: { uae_s8 dst = get_byte(dsta);
38312: src &= 7;
38313: SET_ZFLG (1 ^ ((dst >> src) & 1));
38314: dst |= (1 << src);
38315: m68k_incpc(4);
38316: fill_prefetch_0 ();
38317: put_byte(dsta,dst);
38318: }}}}return 16;
38319: }
38320: unsigned long REGPARAM2 CPUFUNC(op_8d8_5)(uae_u32 opcode) /* BSET */
38321: {
38322: uae_u32 dstreg = opcode & 7;
38323: OpcodeFamily = 24; CurrentInstrCycles = 16;
38324: {{ uae_s16 src = get_iword_prefetch(2);
38325: { uaecptr dsta = m68k_areg(regs, dstreg);
38326: { uae_s8 dst = get_byte(dsta);
38327: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
38328: src &= 7;
38329: SET_ZFLG (1 ^ ((dst >> src) & 1));
38330: dst |= (1 << src);
38331: m68k_incpc(4);
38332: fill_prefetch_0 ();
38333: put_byte(dsta,dst);
38334: }}}}return 16;
38335: }
38336: unsigned long REGPARAM2 CPUFUNC(op_8e0_5)(uae_u32 opcode) /* BSET */
38337: {
38338: uae_u32 dstreg = opcode & 7;
38339: OpcodeFamily = 24; CurrentInstrCycles = 18;
38340: {{ uae_s16 src = get_iword_prefetch(2);
38341: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
38342: { uae_s8 dst = get_byte(dsta);
38343: m68k_areg (regs, dstreg) = dsta;
38344: src &= 7;
38345: SET_ZFLG (1 ^ ((dst >> src) & 1));
38346: dst |= (1 << src);
38347: m68k_incpc(4);
38348: fill_prefetch_0 ();
38349: put_byte(dsta,dst);
38350: }}}}return 18;
38351: }
38352: unsigned long REGPARAM2 CPUFUNC(op_8e8_5)(uae_u32 opcode) /* BSET */
38353: {
38354: uae_u32 dstreg = opcode & 7;
38355: OpcodeFamily = 24; CurrentInstrCycles = 20;
38356: {{ uae_s16 src = get_iword_prefetch(2);
38357: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
38358: { uae_s8 dst = get_byte(dsta);
38359: src &= 7;
38360: SET_ZFLG (1 ^ ((dst >> src) & 1));
38361: dst |= (1 << src);
38362: m68k_incpc(6);
38363: fill_prefetch_0 ();
38364: put_byte(dsta,dst);
38365: }}}}return 20;
38366: }
38367: unsigned long REGPARAM2 CPUFUNC(op_8f0_5)(uae_u32 opcode) /* BSET */
38368: {
38369: uae_u32 dstreg = opcode & 7;
38370: OpcodeFamily = 24; CurrentInstrCycles = 22;
38371: {{ uae_s16 src = get_iword_prefetch(2);
38372: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
38373: BusCyclePenalty += 2;
38374: { uae_s8 dst = get_byte(dsta);
38375: src &= 7;
38376: SET_ZFLG (1 ^ ((dst >> src) & 1));
38377: dst |= (1 << src);
38378: m68k_incpc(6);
38379: fill_prefetch_0 ();
38380: put_byte(dsta,dst);
38381: }}}}return 22;
38382: }
38383: unsigned long REGPARAM2 CPUFUNC(op_8f8_5)(uae_u32 opcode) /* BSET */
38384: {
38385: OpcodeFamily = 24; CurrentInstrCycles = 20;
38386: {{ uae_s16 src = get_iword_prefetch(2);
38387: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
38388: { uae_s8 dst = get_byte(dsta);
38389: src &= 7;
38390: SET_ZFLG (1 ^ ((dst >> src) & 1));
38391: dst |= (1 << src);
38392: m68k_incpc(6);
38393: fill_prefetch_0 ();
38394: put_byte(dsta,dst);
38395: }}}}return 20;
38396: }
38397: unsigned long REGPARAM2 CPUFUNC(op_8f9_5)(uae_u32 opcode) /* BSET */
38398: {
38399: OpcodeFamily = 24; CurrentInstrCycles = 24;
38400: {{ uae_s16 src = get_iword_prefetch(2);
38401: { uaecptr dsta = get_ilong_prefetch(4);
38402: { uae_s8 dst = get_byte(dsta);
38403: src &= 7;
38404: SET_ZFLG (1 ^ ((dst >> src) & 1));
38405: dst |= (1 << src);
38406: m68k_incpc(8);
38407: fill_prefetch_0 ();
38408: put_byte(dsta,dst);
38409: }}}}return 24;
38410: }
38411: unsigned long REGPARAM2 CPUFUNC(op_8fa_5)(uae_u32 opcode) /* BSET */
38412: {
38413: uae_u32 dstreg = 2;
38414: OpcodeFamily = 24; CurrentInstrCycles = 20;
38415: {{ uae_s16 src = get_iword_prefetch(2);
38416: { uaecptr dsta = m68k_getpc () + 4;
38417: dsta += (uae_s32)(uae_s16)get_iword_prefetch(4);
38418: { uae_s8 dst = get_byte(dsta);
38419: src &= 7;
38420: SET_ZFLG (1 ^ ((dst >> src) & 1));
38421: dst |= (1 << src);
38422: m68k_incpc(6);
38423: fill_prefetch_0 ();
38424: put_byte(dsta,dst);
38425: }}}}return 20;
38426: }
38427: unsigned long REGPARAM2 CPUFUNC(op_8fb_5)(uae_u32 opcode) /* BSET */
38428: {
38429: uae_u32 dstreg = 3;
38430: OpcodeFamily = 24; CurrentInstrCycles = 22;
38431: {{ uae_s16 src = get_iword_prefetch(2);
38432: { uaecptr tmppc = m68k_getpc() + 4;
38433: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4));
38434: BusCyclePenalty += 2;
38435: { uae_s8 dst = get_byte(dsta);
38436: src &= 7;
38437: SET_ZFLG (1 ^ ((dst >> src) & 1));
38438: dst |= (1 << src);
38439: m68k_incpc(6);
38440: fill_prefetch_0 ();
38441: put_byte(dsta,dst);
38442: }}}}return 22;
38443: }
38444: unsigned long REGPARAM2 CPUFUNC(op_a00_5)(uae_u32 opcode) /* EOR */
38445: {
38446: uae_u32 dstreg = opcode & 7;
38447: OpcodeFamily = 3; CurrentInstrCycles = 8;
38448: {{ uae_s8 src = get_ibyte_prefetch(2);
38449: { uae_s8 dst = m68k_dreg(regs, dstreg);
38450: src ^= dst;
38451: CLEAR_CZNV;
38452: SET_ZFLG (((uae_s8)(src)) == 0);
38453: SET_NFLG (((uae_s8)(src)) < 0);
38454: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
38455: }}}m68k_incpc(4);
38456: fill_prefetch_0 ();
38457: return 8;
38458: }
38459: unsigned long REGPARAM2 CPUFUNC(op_a10_5)(uae_u32 opcode) /* EOR */
38460: {
38461: uae_u32 dstreg = opcode & 7;
38462: OpcodeFamily = 3; CurrentInstrCycles = 16;
38463: {{ uae_s8 src = get_ibyte_prefetch(2);
38464: { uaecptr dsta = m68k_areg(regs, dstreg);
38465: { uae_s8 dst = get_byte(dsta);
38466: src ^= dst;
38467: CLEAR_CZNV;
38468: SET_ZFLG (((uae_s8)(src)) == 0);
38469: SET_NFLG (((uae_s8)(src)) < 0);
38470: m68k_incpc(4);
38471: fill_prefetch_0 ();
38472: put_byte(dsta,src);
38473: }}}}return 16;
38474: }
38475: unsigned long REGPARAM2 CPUFUNC(op_a18_5)(uae_u32 opcode) /* EOR */
38476: {
38477: uae_u32 dstreg = opcode & 7;
38478: OpcodeFamily = 3; CurrentInstrCycles = 16;
38479: {{ uae_s8 src = get_ibyte_prefetch(2);
38480: { uaecptr dsta = m68k_areg(regs, dstreg);
38481: { uae_s8 dst = get_byte(dsta);
38482: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
38483: src ^= dst;
38484: CLEAR_CZNV;
38485: SET_ZFLG (((uae_s8)(src)) == 0);
38486: SET_NFLG (((uae_s8)(src)) < 0);
38487: m68k_incpc(4);
38488: fill_prefetch_0 ();
38489: put_byte(dsta,src);
38490: }}}}return 16;
38491: }
38492: unsigned long REGPARAM2 CPUFUNC(op_a20_5)(uae_u32 opcode) /* EOR */
38493: {
38494: uae_u32 dstreg = opcode & 7;
38495: OpcodeFamily = 3; CurrentInstrCycles = 18;
38496: {{ uae_s8 src = get_ibyte_prefetch(2);
38497: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
38498: { uae_s8 dst = get_byte(dsta);
38499: m68k_areg (regs, dstreg) = dsta;
38500: src ^= dst;
38501: CLEAR_CZNV;
38502: SET_ZFLG (((uae_s8)(src)) == 0);
38503: SET_NFLG (((uae_s8)(src)) < 0);
38504: m68k_incpc(4);
38505: fill_prefetch_0 ();
38506: put_byte(dsta,src);
38507: }}}}return 18;
38508: }
38509: unsigned long REGPARAM2 CPUFUNC(op_a28_5)(uae_u32 opcode) /* EOR */
38510: {
38511: uae_u32 dstreg = opcode & 7;
38512: OpcodeFamily = 3; CurrentInstrCycles = 20;
38513: {{ uae_s8 src = get_ibyte_prefetch(2);
38514: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
38515: { uae_s8 dst = get_byte(dsta);
38516: src ^= dst;
38517: CLEAR_CZNV;
38518: SET_ZFLG (((uae_s8)(src)) == 0);
38519: SET_NFLG (((uae_s8)(src)) < 0);
38520: m68k_incpc(6);
38521: fill_prefetch_0 ();
38522: put_byte(dsta,src);
38523: }}}}return 20;
38524: }
38525: unsigned long REGPARAM2 CPUFUNC(op_a30_5)(uae_u32 opcode) /* EOR */
38526: {
38527: uae_u32 dstreg = opcode & 7;
38528: OpcodeFamily = 3; CurrentInstrCycles = 22;
38529: {{ uae_s8 src = get_ibyte_prefetch(2);
38530: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
38531: BusCyclePenalty += 2;
38532: { uae_s8 dst = get_byte(dsta);
38533: src ^= dst;
38534: CLEAR_CZNV;
38535: SET_ZFLG (((uae_s8)(src)) == 0);
38536: SET_NFLG (((uae_s8)(src)) < 0);
38537: m68k_incpc(6);
38538: fill_prefetch_0 ();
38539: put_byte(dsta,src);
38540: }}}}return 22;
38541: }
38542: unsigned long REGPARAM2 CPUFUNC(op_a38_5)(uae_u32 opcode) /* EOR */
38543: {
38544: OpcodeFamily = 3; CurrentInstrCycles = 20;
38545: {{ uae_s8 src = get_ibyte_prefetch(2);
38546: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
38547: { uae_s8 dst = get_byte(dsta);
38548: src ^= dst;
38549: CLEAR_CZNV;
38550: SET_ZFLG (((uae_s8)(src)) == 0);
38551: SET_NFLG (((uae_s8)(src)) < 0);
38552: m68k_incpc(6);
38553: fill_prefetch_0 ();
38554: put_byte(dsta,src);
38555: }}}}return 20;
38556: }
38557: unsigned long REGPARAM2 CPUFUNC(op_a39_5)(uae_u32 opcode) /* EOR */
38558: {
38559: OpcodeFamily = 3; CurrentInstrCycles = 24;
38560: {{ uae_s8 src = get_ibyte_prefetch(2);
38561: { uaecptr dsta = get_ilong_prefetch(4);
38562: { uae_s8 dst = get_byte(dsta);
38563: src ^= dst;
38564: CLEAR_CZNV;
38565: SET_ZFLG (((uae_s8)(src)) == 0);
38566: SET_NFLG (((uae_s8)(src)) < 0);
38567: m68k_incpc(8);
38568: fill_prefetch_0 ();
38569: put_byte(dsta,src);
38570: }}}}return 24;
38571: }
38572: unsigned long REGPARAM2 CPUFUNC(op_a3c_5)(uae_u32 opcode) /* EORSR */
38573: {
38574: OpcodeFamily = 6; CurrentInstrCycles = 20;
38575: { MakeSR();
38576: { uae_s16 src = get_iword_prefetch(2);
38577: src &= 0xFF;
38578: regs.sr ^= src;
38579: MakeFromSR();
38580: }}m68k_incpc(4);
38581: fill_prefetch_0 ();
38582: return 20;
38583: }
38584: unsigned long REGPARAM2 CPUFUNC(op_a40_5)(uae_u32 opcode) /* EOR */
38585: {
38586: uae_u32 dstreg = opcode & 7;
38587: OpcodeFamily = 3; CurrentInstrCycles = 8;
38588: {{ uae_s16 src = get_iword_prefetch(2);
38589: { uae_s16 dst = m68k_dreg(regs, dstreg);
38590: src ^= dst;
38591: CLEAR_CZNV;
38592: SET_ZFLG (((uae_s16)(src)) == 0);
38593: SET_NFLG (((uae_s16)(src)) < 0);
38594: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
38595: }}}m68k_incpc(4);
38596: fill_prefetch_0 ();
38597: return 8;
38598: }
38599: unsigned long REGPARAM2 CPUFUNC(op_a50_5)(uae_u32 opcode) /* EOR */
38600: {
38601: uae_u32 dstreg = opcode & 7;
38602: OpcodeFamily = 3; CurrentInstrCycles = 16;
38603: {{ uae_s16 src = get_iword_prefetch(2);
38604: { uaecptr dsta = m68k_areg(regs, dstreg);
38605: if ((dsta & 1) != 0) {
38606: last_fault_for_exception_3 = dsta;
38607: last_op_for_exception_3 = opcode;
38608: last_addr_for_exception_3 = m68k_getpc() + 4;
38609: Exception(3, 0, M68000_EXC_SRC_CPU);
38610: goto endlabel2351;
38611: }
38612: {{ uae_s16 dst = get_word(dsta);
38613: src ^= dst;
38614: CLEAR_CZNV;
38615: SET_ZFLG (((uae_s16)(src)) == 0);
38616: SET_NFLG (((uae_s16)(src)) < 0);
38617: m68k_incpc(4);
38618: fill_prefetch_0 ();
38619: put_word(dsta,src);
38620: }}}}}endlabel2351: ;
38621: return 16;
38622: }
38623: unsigned long REGPARAM2 CPUFUNC(op_a58_5)(uae_u32 opcode) /* EOR */
38624: {
38625: uae_u32 dstreg = opcode & 7;
38626: OpcodeFamily = 3; CurrentInstrCycles = 16;
38627: {{ uae_s16 src = get_iword_prefetch(2);
38628: { uaecptr dsta = m68k_areg(regs, dstreg);
38629: if ((dsta & 1) != 0) {
38630: last_fault_for_exception_3 = dsta;
38631: last_op_for_exception_3 = opcode;
38632: last_addr_for_exception_3 = m68k_getpc() + 4;
38633: Exception(3, 0, M68000_EXC_SRC_CPU);
38634: goto endlabel2352;
38635: }
38636: {{ uae_s16 dst = get_word(dsta);
38637: m68k_areg(regs, dstreg) += 2;
38638: src ^= dst;
38639: CLEAR_CZNV;
38640: SET_ZFLG (((uae_s16)(src)) == 0);
38641: SET_NFLG (((uae_s16)(src)) < 0);
38642: m68k_incpc(4);
38643: fill_prefetch_0 ();
38644: put_word(dsta,src);
38645: }}}}}endlabel2352: ;
38646: return 16;
38647: }
38648: unsigned long REGPARAM2 CPUFUNC(op_a60_5)(uae_u32 opcode) /* EOR */
38649: {
38650: uae_u32 dstreg = opcode & 7;
38651: OpcodeFamily = 3; CurrentInstrCycles = 18;
38652: {{ uae_s16 src = get_iword_prefetch(2);
38653: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
38654: if ((dsta & 1) != 0) {
38655: last_fault_for_exception_3 = dsta;
38656: last_op_for_exception_3 = opcode;
38657: last_addr_for_exception_3 = m68k_getpc() + 4;
38658: Exception(3, 0, M68000_EXC_SRC_CPU);
38659: goto endlabel2353;
38660: }
38661: {{ uae_s16 dst = get_word(dsta);
38662: m68k_areg (regs, dstreg) = dsta;
38663: src ^= dst;
38664: CLEAR_CZNV;
38665: SET_ZFLG (((uae_s16)(src)) == 0);
38666: SET_NFLG (((uae_s16)(src)) < 0);
38667: m68k_incpc(4);
38668: fill_prefetch_0 ();
38669: put_word(dsta,src);
38670: }}}}}endlabel2353: ;
38671: return 18;
38672: }
38673: unsigned long REGPARAM2 CPUFUNC(op_a68_5)(uae_u32 opcode) /* EOR */
38674: {
38675: uae_u32 dstreg = opcode & 7;
38676: OpcodeFamily = 3; CurrentInstrCycles = 20;
38677: {{ uae_s16 src = get_iword_prefetch(2);
38678: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
38679: if ((dsta & 1) != 0) {
38680: last_fault_for_exception_3 = dsta;
38681: last_op_for_exception_3 = opcode;
38682: last_addr_for_exception_3 = m68k_getpc() + 6;
38683: Exception(3, 0, M68000_EXC_SRC_CPU);
38684: goto endlabel2354;
38685: }
38686: {{ uae_s16 dst = get_word(dsta);
38687: src ^= dst;
38688: CLEAR_CZNV;
38689: SET_ZFLG (((uae_s16)(src)) == 0);
38690: SET_NFLG (((uae_s16)(src)) < 0);
38691: m68k_incpc(6);
38692: fill_prefetch_0 ();
38693: put_word(dsta,src);
38694: }}}}}endlabel2354: ;
38695: return 20;
38696: }
38697: unsigned long REGPARAM2 CPUFUNC(op_a70_5)(uae_u32 opcode) /* EOR */
38698: {
38699: uae_u32 dstreg = opcode & 7;
38700: OpcodeFamily = 3; CurrentInstrCycles = 22;
38701: {{ uae_s16 src = get_iword_prefetch(2);
38702: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
38703: BusCyclePenalty += 2;
38704: if ((dsta & 1) != 0) {
38705: last_fault_for_exception_3 = dsta;
38706: last_op_for_exception_3 = opcode;
38707: last_addr_for_exception_3 = m68k_getpc() + 6;
38708: Exception(3, 0, M68000_EXC_SRC_CPU);
38709: goto endlabel2355;
38710: }
38711: {{ uae_s16 dst = get_word(dsta);
38712: src ^= dst;
38713: CLEAR_CZNV;
38714: SET_ZFLG (((uae_s16)(src)) == 0);
38715: SET_NFLG (((uae_s16)(src)) < 0);
38716: m68k_incpc(6);
38717: fill_prefetch_0 ();
38718: put_word(dsta,src);
38719: }}}}}endlabel2355: ;
38720: return 22;
38721: }
38722: unsigned long REGPARAM2 CPUFUNC(op_a78_5)(uae_u32 opcode) /* EOR */
38723: {
38724: OpcodeFamily = 3; CurrentInstrCycles = 20;
38725: {{ uae_s16 src = get_iword_prefetch(2);
38726: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
38727: if ((dsta & 1) != 0) {
38728: last_fault_for_exception_3 = dsta;
38729: last_op_for_exception_3 = opcode;
38730: last_addr_for_exception_3 = m68k_getpc() + 6;
38731: Exception(3, 0, M68000_EXC_SRC_CPU);
38732: goto endlabel2356;
38733: }
38734: {{ uae_s16 dst = get_word(dsta);
38735: src ^= dst;
38736: CLEAR_CZNV;
38737: SET_ZFLG (((uae_s16)(src)) == 0);
38738: SET_NFLG (((uae_s16)(src)) < 0);
38739: m68k_incpc(6);
38740: fill_prefetch_0 ();
38741: put_word(dsta,src);
38742: }}}}}endlabel2356: ;
38743: return 20;
38744: }
38745: unsigned long REGPARAM2 CPUFUNC(op_a79_5)(uae_u32 opcode) /* EOR */
38746: {
38747: OpcodeFamily = 3; CurrentInstrCycles = 24;
38748: {{ uae_s16 src = get_iword_prefetch(2);
38749: { uaecptr dsta = get_ilong_prefetch(4);
38750: if ((dsta & 1) != 0) {
38751: last_fault_for_exception_3 = dsta;
38752: last_op_for_exception_3 = opcode;
38753: last_addr_for_exception_3 = m68k_getpc() + 8;
38754: Exception(3, 0, M68000_EXC_SRC_CPU);
38755: goto endlabel2357;
38756: }
38757: {{ uae_s16 dst = get_word(dsta);
38758: src ^= dst;
38759: CLEAR_CZNV;
38760: SET_ZFLG (((uae_s16)(src)) == 0);
38761: SET_NFLG (((uae_s16)(src)) < 0);
38762: m68k_incpc(8);
38763: fill_prefetch_0 ();
38764: put_word(dsta,src);
38765: }}}}}endlabel2357: ;
38766: return 24;
38767: }
38768: unsigned long REGPARAM2 CPUFUNC(op_a7c_5)(uae_u32 opcode) /* EORSR */
38769: {
38770: OpcodeFamily = 6; CurrentInstrCycles = 20;
38771: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2358; }
38772: { MakeSR();
38773: { uae_s16 src = get_iword_prefetch(2);
38774: regs.sr ^= src;
38775: MakeFromSR();
38776: }}}m68k_incpc(4);
38777: fill_prefetch_0 ();
38778: endlabel2358: ;
38779: return 20;
38780: }
38781: #endif
38782:
38783: #ifdef PART_2
38784: unsigned long REGPARAM2 CPUFUNC(op_a80_5)(uae_u32 opcode) /* EOR */
38785: {
38786: uae_u32 dstreg = opcode & 7;
38787: OpcodeFamily = 3; CurrentInstrCycles = 16;
38788: {{ uae_s32 src = get_ilong_prefetch(2);
38789: { uae_s32 dst = m68k_dreg(regs, dstreg);
38790: src ^= dst;
38791: CLEAR_CZNV;
38792: SET_ZFLG (((uae_s32)(src)) == 0);
38793: SET_NFLG (((uae_s32)(src)) < 0);
38794: m68k_dreg(regs, dstreg) = (src);
38795: }}}m68k_incpc(6);
38796: fill_prefetch_0 ();
38797: return 16;
38798: }
38799: unsigned long REGPARAM2 CPUFUNC(op_a90_5)(uae_u32 opcode) /* EOR */
38800: {
38801: uae_u32 dstreg = opcode & 7;
38802: OpcodeFamily = 3; CurrentInstrCycles = 28;
38803: {{ uae_s32 src = get_ilong_prefetch(2);
38804: { uaecptr dsta = m68k_areg(regs, dstreg);
38805: if ((dsta & 1) != 0) {
38806: last_fault_for_exception_3 = dsta;
38807: last_op_for_exception_3 = opcode;
38808: last_addr_for_exception_3 = m68k_getpc() + 6;
38809: Exception(3, 0, M68000_EXC_SRC_CPU);
38810: goto endlabel2360;
38811: }
38812: {{ uae_s32 dst = get_long(dsta);
38813: src ^= dst;
38814: CLEAR_CZNV;
38815: SET_ZFLG (((uae_s32)(src)) == 0);
38816: SET_NFLG (((uae_s32)(src)) < 0);
38817: m68k_incpc(6);
38818: fill_prefetch_0 ();
38819: put_long(dsta,src);
38820: }}}}}endlabel2360: ;
38821: return 28;
38822: }
38823: unsigned long REGPARAM2 CPUFUNC(op_a98_5)(uae_u32 opcode) /* EOR */
38824: {
38825: uae_u32 dstreg = opcode & 7;
38826: OpcodeFamily = 3; CurrentInstrCycles = 28;
38827: {{ uae_s32 src = get_ilong_prefetch(2);
38828: { uaecptr dsta = m68k_areg(regs, dstreg);
38829: if ((dsta & 1) != 0) {
38830: last_fault_for_exception_3 = dsta;
38831: last_op_for_exception_3 = opcode;
38832: last_addr_for_exception_3 = m68k_getpc() + 6;
38833: Exception(3, 0, M68000_EXC_SRC_CPU);
38834: goto endlabel2361;
38835: }
38836: {{ uae_s32 dst = get_long(dsta);
38837: m68k_areg(regs, dstreg) += 4;
38838: src ^= dst;
38839: CLEAR_CZNV;
38840: SET_ZFLG (((uae_s32)(src)) == 0);
38841: SET_NFLG (((uae_s32)(src)) < 0);
38842: m68k_incpc(6);
38843: fill_prefetch_0 ();
38844: put_long(dsta,src);
38845: }}}}}endlabel2361: ;
38846: return 28;
38847: }
38848: unsigned long REGPARAM2 CPUFUNC(op_aa0_5)(uae_u32 opcode) /* EOR */
38849: {
38850: uae_u32 dstreg = opcode & 7;
38851: OpcodeFamily = 3; CurrentInstrCycles = 30;
38852: {{ uae_s32 src = get_ilong_prefetch(2);
38853: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
38854: if ((dsta & 1) != 0) {
38855: last_fault_for_exception_3 = dsta;
38856: last_op_for_exception_3 = opcode;
38857: last_addr_for_exception_3 = m68k_getpc() + 6;
38858: Exception(3, 0, M68000_EXC_SRC_CPU);
38859: goto endlabel2362;
38860: }
38861: {{ uae_s32 dst = get_long(dsta);
38862: m68k_areg (regs, dstreg) = dsta;
38863: src ^= dst;
38864: CLEAR_CZNV;
38865: SET_ZFLG (((uae_s32)(src)) == 0);
38866: SET_NFLG (((uae_s32)(src)) < 0);
38867: m68k_incpc(6);
38868: fill_prefetch_0 ();
38869: put_long(dsta,src);
38870: }}}}}endlabel2362: ;
38871: return 30;
38872: }
38873: unsigned long REGPARAM2 CPUFUNC(op_aa8_5)(uae_u32 opcode) /* EOR */
38874: {
38875: uae_u32 dstreg = opcode & 7;
38876: OpcodeFamily = 3; CurrentInstrCycles = 32;
38877: {{ uae_s32 src = get_ilong_prefetch(2);
38878: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
38879: if ((dsta & 1) != 0) {
38880: last_fault_for_exception_3 = dsta;
38881: last_op_for_exception_3 = opcode;
38882: last_addr_for_exception_3 = m68k_getpc() + 8;
38883: Exception(3, 0, M68000_EXC_SRC_CPU);
38884: goto endlabel2363;
38885: }
38886: {{ uae_s32 dst = get_long(dsta);
38887: src ^= dst;
38888: CLEAR_CZNV;
38889: SET_ZFLG (((uae_s32)(src)) == 0);
38890: SET_NFLG (((uae_s32)(src)) < 0);
38891: m68k_incpc(8);
38892: fill_prefetch_0 ();
38893: put_long(dsta,src);
38894: }}}}}endlabel2363: ;
38895: return 32;
38896: }
38897: unsigned long REGPARAM2 CPUFUNC(op_ab0_5)(uae_u32 opcode) /* EOR */
38898: {
38899: uae_u32 dstreg = opcode & 7;
38900: OpcodeFamily = 3; CurrentInstrCycles = 34;
38901: {{ uae_s32 src = get_ilong_prefetch(2);
38902: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
38903: BusCyclePenalty += 2;
38904: if ((dsta & 1) != 0) {
38905: last_fault_for_exception_3 = dsta;
38906: last_op_for_exception_3 = opcode;
38907: last_addr_for_exception_3 = m68k_getpc() + 8;
38908: Exception(3, 0, M68000_EXC_SRC_CPU);
38909: goto endlabel2364;
38910: }
38911: {{ uae_s32 dst = get_long(dsta);
38912: src ^= dst;
38913: CLEAR_CZNV;
38914: SET_ZFLG (((uae_s32)(src)) == 0);
38915: SET_NFLG (((uae_s32)(src)) < 0);
38916: m68k_incpc(8);
38917: fill_prefetch_0 ();
38918: put_long(dsta,src);
38919: }}}}}endlabel2364: ;
38920: return 34;
38921: }
38922: unsigned long REGPARAM2 CPUFUNC(op_ab8_5)(uae_u32 opcode) /* EOR */
38923: {
38924: OpcodeFamily = 3; CurrentInstrCycles = 32;
38925: {{ uae_s32 src = get_ilong_prefetch(2);
38926: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
38927: if ((dsta & 1) != 0) {
38928: last_fault_for_exception_3 = dsta;
38929: last_op_for_exception_3 = opcode;
38930: last_addr_for_exception_3 = m68k_getpc() + 8;
38931: Exception(3, 0, M68000_EXC_SRC_CPU);
38932: goto endlabel2365;
38933: }
38934: {{ uae_s32 dst = get_long(dsta);
38935: src ^= dst;
38936: CLEAR_CZNV;
38937: SET_ZFLG (((uae_s32)(src)) == 0);
38938: SET_NFLG (((uae_s32)(src)) < 0);
38939: m68k_incpc(8);
38940: fill_prefetch_0 ();
38941: put_long(dsta,src);
38942: }}}}}endlabel2365: ;
38943: return 32;
38944: }
38945: unsigned long REGPARAM2 CPUFUNC(op_ab9_5)(uae_u32 opcode) /* EOR */
38946: {
38947: OpcodeFamily = 3; CurrentInstrCycles = 36;
38948: {{ uae_s32 src = get_ilong_prefetch(2);
38949: { uaecptr dsta = get_ilong_prefetch(6);
38950: if ((dsta & 1) != 0) {
38951: last_fault_for_exception_3 = dsta;
38952: last_op_for_exception_3 = opcode;
38953: last_addr_for_exception_3 = m68k_getpc() + 10;
38954: Exception(3, 0, M68000_EXC_SRC_CPU);
38955: goto endlabel2366;
38956: }
38957: {{ uae_s32 dst = get_long(dsta);
38958: src ^= dst;
38959: CLEAR_CZNV;
38960: SET_ZFLG (((uae_s32)(src)) == 0);
38961: SET_NFLG (((uae_s32)(src)) < 0);
38962: m68k_incpc(10);
38963: fill_prefetch_0 ();
38964: put_long(dsta,src);
38965: }}}}}endlabel2366: ;
38966: return 36;
38967: }
38968: unsigned long REGPARAM2 CPUFUNC(op_c00_5)(uae_u32 opcode) /* CMP */
38969: {
38970: uae_u32 dstreg = opcode & 7;
38971: OpcodeFamily = 25; CurrentInstrCycles = 8;
38972: {{ uae_s8 src = get_ibyte_prefetch(2);
38973: { uae_s8 dst = m68k_dreg(regs, dstreg);
38974: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
38975: { int flgs = ((uae_s8)(src)) < 0;
38976: int flgo = ((uae_s8)(dst)) < 0;
38977: int flgn = ((uae_s8)(newv)) < 0;
38978: SET_ZFLG (((uae_s8)(newv)) == 0);
38979: SET_VFLG ((flgs != flgo) && (flgn != flgo));
38980: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
38981: SET_NFLG (flgn != 0);
38982: }}}}}}m68k_incpc(4);
38983: fill_prefetch_0 ();
38984: return 8;
38985: }
38986: unsigned long REGPARAM2 CPUFUNC(op_c10_5)(uae_u32 opcode) /* CMP */
38987: {
38988: uae_u32 dstreg = opcode & 7;
38989: OpcodeFamily = 25; CurrentInstrCycles = 12;
38990: {{ uae_s8 src = get_ibyte_prefetch(2);
38991: { uaecptr dsta = m68k_areg(regs, dstreg);
38992: { uae_s8 dst = get_byte(dsta);
38993: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
38994: { int flgs = ((uae_s8)(src)) < 0;
38995: int flgo = ((uae_s8)(dst)) < 0;
38996: int flgn = ((uae_s8)(newv)) < 0;
38997: SET_ZFLG (((uae_s8)(newv)) == 0);
38998: SET_VFLG ((flgs != flgo) && (flgn != flgo));
38999: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
39000: SET_NFLG (flgn != 0);
39001: }}}}}}}m68k_incpc(4);
39002: fill_prefetch_0 ();
39003: return 12;
39004: }
39005: unsigned long REGPARAM2 CPUFUNC(op_c18_5)(uae_u32 opcode) /* CMP */
39006: {
39007: uae_u32 dstreg = opcode & 7;
39008: OpcodeFamily = 25; CurrentInstrCycles = 12;
39009: {{ uae_s8 src = get_ibyte_prefetch(2);
39010: { uaecptr dsta = m68k_areg(regs, dstreg);
39011: { uae_s8 dst = get_byte(dsta);
39012: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
39013: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
39014: { int flgs = ((uae_s8)(src)) < 0;
39015: int flgo = ((uae_s8)(dst)) < 0;
39016: int flgn = ((uae_s8)(newv)) < 0;
39017: SET_ZFLG (((uae_s8)(newv)) == 0);
39018: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39019: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
39020: SET_NFLG (flgn != 0);
39021: }}}}}}}m68k_incpc(4);
39022: fill_prefetch_0 ();
39023: return 12;
39024: }
39025: unsigned long REGPARAM2 CPUFUNC(op_c20_5)(uae_u32 opcode) /* CMP */
39026: {
39027: uae_u32 dstreg = opcode & 7;
39028: OpcodeFamily = 25; CurrentInstrCycles = 14;
39029: {{ uae_s8 src = get_ibyte_prefetch(2);
39030: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
39031: { uae_s8 dst = get_byte(dsta);
39032: m68k_areg (regs, dstreg) = dsta;
39033: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
39034: { int flgs = ((uae_s8)(src)) < 0;
39035: int flgo = ((uae_s8)(dst)) < 0;
39036: int flgn = ((uae_s8)(newv)) < 0;
39037: SET_ZFLG (((uae_s8)(newv)) == 0);
39038: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39039: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
39040: SET_NFLG (flgn != 0);
39041: }}}}}}}m68k_incpc(4);
39042: fill_prefetch_0 ();
39043: return 14;
39044: }
39045: unsigned long REGPARAM2 CPUFUNC(op_c28_5)(uae_u32 opcode) /* CMP */
39046: {
39047: uae_u32 dstreg = opcode & 7;
39048: OpcodeFamily = 25; CurrentInstrCycles = 16;
39049: {{ uae_s8 src = get_ibyte_prefetch(2);
39050: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
39051: { uae_s8 dst = get_byte(dsta);
39052: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
39053: { int flgs = ((uae_s8)(src)) < 0;
39054: int flgo = ((uae_s8)(dst)) < 0;
39055: int flgn = ((uae_s8)(newv)) < 0;
39056: SET_ZFLG (((uae_s8)(newv)) == 0);
39057: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39058: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
39059: SET_NFLG (flgn != 0);
39060: }}}}}}}m68k_incpc(6);
39061: fill_prefetch_0 ();
39062: return 16;
39063: }
39064: unsigned long REGPARAM2 CPUFUNC(op_c30_5)(uae_u32 opcode) /* CMP */
39065: {
39066: uae_u32 dstreg = opcode & 7;
39067: OpcodeFamily = 25; CurrentInstrCycles = 18;
39068: {{ uae_s8 src = get_ibyte_prefetch(2);
39069: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
39070: BusCyclePenalty += 2;
39071: { uae_s8 dst = get_byte(dsta);
39072: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
39073: { int flgs = ((uae_s8)(src)) < 0;
39074: int flgo = ((uae_s8)(dst)) < 0;
39075: int flgn = ((uae_s8)(newv)) < 0;
39076: SET_ZFLG (((uae_s8)(newv)) == 0);
39077: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39078: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
39079: SET_NFLG (flgn != 0);
39080: }}}}}}}m68k_incpc(6);
39081: fill_prefetch_0 ();
39082: return 18;
39083: }
39084: unsigned long REGPARAM2 CPUFUNC(op_c38_5)(uae_u32 opcode) /* CMP */
39085: {
39086: OpcodeFamily = 25; CurrentInstrCycles = 16;
39087: {{ uae_s8 src = get_ibyte_prefetch(2);
39088: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
39089: { uae_s8 dst = get_byte(dsta);
39090: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
39091: { int flgs = ((uae_s8)(src)) < 0;
39092: int flgo = ((uae_s8)(dst)) < 0;
39093: int flgn = ((uae_s8)(newv)) < 0;
39094: SET_ZFLG (((uae_s8)(newv)) == 0);
39095: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39096: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
39097: SET_NFLG (flgn != 0);
39098: }}}}}}}m68k_incpc(6);
39099: fill_prefetch_0 ();
39100: return 16;
39101: }
39102: unsigned long REGPARAM2 CPUFUNC(op_c39_5)(uae_u32 opcode) /* CMP */
39103: {
39104: OpcodeFamily = 25; CurrentInstrCycles = 20;
39105: {{ uae_s8 src = get_ibyte_prefetch(2);
39106: { uaecptr dsta = get_ilong_prefetch(4);
39107: { uae_s8 dst = get_byte(dsta);
39108: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
39109: { int flgs = ((uae_s8)(src)) < 0;
39110: int flgo = ((uae_s8)(dst)) < 0;
39111: int flgn = ((uae_s8)(newv)) < 0;
39112: SET_ZFLG (((uae_s8)(newv)) == 0);
39113: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39114: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
39115: SET_NFLG (flgn != 0);
39116: }}}}}}}m68k_incpc(8);
39117: fill_prefetch_0 ();
39118: return 20;
39119: }
39120: unsigned long REGPARAM2 CPUFUNC(op_c3a_5)(uae_u32 opcode) /* CMP */
39121: {
39122: uae_u32 dstreg = 2;
39123: OpcodeFamily = 25; CurrentInstrCycles = 16;
39124: {{ uae_s8 src = get_ibyte_prefetch(2);
39125: { uaecptr dsta = m68k_getpc () + 4;
39126: dsta += (uae_s32)(uae_s16)get_iword_prefetch(4);
39127: { uae_s8 dst = get_byte(dsta);
39128: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
39129: { int flgs = ((uae_s8)(src)) < 0;
39130: int flgo = ((uae_s8)(dst)) < 0;
39131: int flgn = ((uae_s8)(newv)) < 0;
39132: SET_ZFLG (((uae_s8)(newv)) == 0);
39133: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39134: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
39135: SET_NFLG (flgn != 0);
39136: }}}}}}}m68k_incpc(6);
39137: fill_prefetch_0 ();
39138: return 16;
39139: }
39140: unsigned long REGPARAM2 CPUFUNC(op_c3b_5)(uae_u32 opcode) /* CMP */
39141: {
39142: uae_u32 dstreg = 3;
39143: OpcodeFamily = 25; CurrentInstrCycles = 18;
39144: {{ uae_s8 src = get_ibyte_prefetch(2);
39145: { uaecptr tmppc = m68k_getpc() + 4;
39146: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4));
39147: BusCyclePenalty += 2;
39148: { uae_s8 dst = get_byte(dsta);
39149: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
39150: { int flgs = ((uae_s8)(src)) < 0;
39151: int flgo = ((uae_s8)(dst)) < 0;
39152: int flgn = ((uae_s8)(newv)) < 0;
39153: SET_ZFLG (((uae_s8)(newv)) == 0);
39154: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39155: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
39156: SET_NFLG (flgn != 0);
39157: }}}}}}}m68k_incpc(6);
39158: fill_prefetch_0 ();
39159: return 18;
39160: }
39161: unsigned long REGPARAM2 CPUFUNC(op_c40_5)(uae_u32 opcode) /* CMP */
39162: {
39163: uae_u32 dstreg = opcode & 7;
39164: OpcodeFamily = 25; CurrentInstrCycles = 8;
39165: {{ uae_s16 src = get_iword_prefetch(2);
39166: { uae_s16 dst = m68k_dreg(regs, dstreg);
39167: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39168: { int flgs = ((uae_s16)(src)) < 0;
39169: int flgo = ((uae_s16)(dst)) < 0;
39170: int flgn = ((uae_s16)(newv)) < 0;
39171: SET_ZFLG (((uae_s16)(newv)) == 0);
39172: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39173: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39174: SET_NFLG (flgn != 0);
39175: }}}}}}m68k_incpc(4);
39176: fill_prefetch_0 ();
39177: return 8;
39178: }
39179: unsigned long REGPARAM2 CPUFUNC(op_c50_5)(uae_u32 opcode) /* CMP */
39180: {
39181: uae_u32 dstreg = opcode & 7;
39182: OpcodeFamily = 25; CurrentInstrCycles = 12;
39183: {{ uae_s16 src = get_iword_prefetch(2);
39184: { uaecptr dsta = m68k_areg(regs, dstreg);
39185: if ((dsta & 1) != 0) {
39186: last_fault_for_exception_3 = dsta;
39187: last_op_for_exception_3 = opcode;
39188: last_addr_for_exception_3 = m68k_getpc() + 4;
39189: Exception(3, 0, M68000_EXC_SRC_CPU);
39190: goto endlabel2378;
39191: }
39192: {{ uae_s16 dst = get_word(dsta);
39193: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39194: { int flgs = ((uae_s16)(src)) < 0;
39195: int flgo = ((uae_s16)(dst)) < 0;
39196: int flgn = ((uae_s16)(newv)) < 0;
39197: SET_ZFLG (((uae_s16)(newv)) == 0);
39198: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39199: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39200: SET_NFLG (flgn != 0);
39201: }}}}}}}}m68k_incpc(4);
39202: fill_prefetch_0 ();
39203: endlabel2378: ;
39204: return 12;
39205: }
39206: unsigned long REGPARAM2 CPUFUNC(op_c58_5)(uae_u32 opcode) /* CMP */
39207: {
39208: uae_u32 dstreg = opcode & 7;
39209: OpcodeFamily = 25; CurrentInstrCycles = 12;
39210: {{ uae_s16 src = get_iword_prefetch(2);
39211: { uaecptr dsta = m68k_areg(regs, dstreg);
39212: if ((dsta & 1) != 0) {
39213: last_fault_for_exception_3 = dsta;
39214: last_op_for_exception_3 = opcode;
39215: last_addr_for_exception_3 = m68k_getpc() + 4;
39216: Exception(3, 0, M68000_EXC_SRC_CPU);
39217: goto endlabel2379;
39218: }
39219: {{ uae_s16 dst = get_word(dsta);
39220: m68k_areg(regs, dstreg) += 2;
39221: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39222: { int flgs = ((uae_s16)(src)) < 0;
39223: int flgo = ((uae_s16)(dst)) < 0;
39224: int flgn = ((uae_s16)(newv)) < 0;
39225: SET_ZFLG (((uae_s16)(newv)) == 0);
39226: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39227: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39228: SET_NFLG (flgn != 0);
39229: }}}}}}}}m68k_incpc(4);
39230: fill_prefetch_0 ();
39231: endlabel2379: ;
39232: return 12;
39233: }
39234: unsigned long REGPARAM2 CPUFUNC(op_c60_5)(uae_u32 opcode) /* CMP */
39235: {
39236: uae_u32 dstreg = opcode & 7;
39237: OpcodeFamily = 25; CurrentInstrCycles = 14;
39238: {{ uae_s16 src = get_iword_prefetch(2);
39239: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
39240: if ((dsta & 1) != 0) {
39241: last_fault_for_exception_3 = dsta;
39242: last_op_for_exception_3 = opcode;
39243: last_addr_for_exception_3 = m68k_getpc() + 4;
39244: Exception(3, 0, M68000_EXC_SRC_CPU);
39245: goto endlabel2380;
39246: }
39247: {{ uae_s16 dst = get_word(dsta);
39248: m68k_areg (regs, dstreg) = dsta;
39249: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39250: { int flgs = ((uae_s16)(src)) < 0;
39251: int flgo = ((uae_s16)(dst)) < 0;
39252: int flgn = ((uae_s16)(newv)) < 0;
39253: SET_ZFLG (((uae_s16)(newv)) == 0);
39254: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39255: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39256: SET_NFLG (flgn != 0);
39257: }}}}}}}}m68k_incpc(4);
39258: fill_prefetch_0 ();
39259: endlabel2380: ;
39260: return 14;
39261: }
39262: unsigned long REGPARAM2 CPUFUNC(op_c68_5)(uae_u32 opcode) /* CMP */
39263: {
39264: uae_u32 dstreg = opcode & 7;
39265: OpcodeFamily = 25; CurrentInstrCycles = 16;
39266: {{ uae_s16 src = get_iword_prefetch(2);
39267: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
39268: if ((dsta & 1) != 0) {
39269: last_fault_for_exception_3 = dsta;
39270: last_op_for_exception_3 = opcode;
39271: last_addr_for_exception_3 = m68k_getpc() + 6;
39272: Exception(3, 0, M68000_EXC_SRC_CPU);
39273: goto endlabel2381;
39274: }
39275: {{ uae_s16 dst = get_word(dsta);
39276: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39277: { int flgs = ((uae_s16)(src)) < 0;
39278: int flgo = ((uae_s16)(dst)) < 0;
39279: int flgn = ((uae_s16)(newv)) < 0;
39280: SET_ZFLG (((uae_s16)(newv)) == 0);
39281: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39282: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39283: SET_NFLG (flgn != 0);
39284: }}}}}}}}m68k_incpc(6);
39285: fill_prefetch_0 ();
39286: endlabel2381: ;
39287: return 16;
39288: }
39289: unsigned long REGPARAM2 CPUFUNC(op_c70_5)(uae_u32 opcode) /* CMP */
39290: {
39291: uae_u32 dstreg = opcode & 7;
39292: OpcodeFamily = 25; CurrentInstrCycles = 18;
39293: {{ uae_s16 src = get_iword_prefetch(2);
39294: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
39295: BusCyclePenalty += 2;
39296: if ((dsta & 1) != 0) {
39297: last_fault_for_exception_3 = dsta;
39298: last_op_for_exception_3 = opcode;
39299: last_addr_for_exception_3 = m68k_getpc() + 6;
39300: Exception(3, 0, M68000_EXC_SRC_CPU);
39301: goto endlabel2382;
39302: }
39303: {{ uae_s16 dst = get_word(dsta);
39304: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39305: { int flgs = ((uae_s16)(src)) < 0;
39306: int flgo = ((uae_s16)(dst)) < 0;
39307: int flgn = ((uae_s16)(newv)) < 0;
39308: SET_ZFLG (((uae_s16)(newv)) == 0);
39309: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39310: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39311: SET_NFLG (flgn != 0);
39312: }}}}}}}}m68k_incpc(6);
39313: fill_prefetch_0 ();
39314: endlabel2382: ;
39315: return 18;
39316: }
39317: unsigned long REGPARAM2 CPUFUNC(op_c78_5)(uae_u32 opcode) /* CMP */
39318: {
39319: OpcodeFamily = 25; CurrentInstrCycles = 16;
39320: {{ uae_s16 src = get_iword_prefetch(2);
39321: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
39322: if ((dsta & 1) != 0) {
39323: last_fault_for_exception_3 = dsta;
39324: last_op_for_exception_3 = opcode;
39325: last_addr_for_exception_3 = m68k_getpc() + 6;
39326: Exception(3, 0, M68000_EXC_SRC_CPU);
39327: goto endlabel2383;
39328: }
39329: {{ uae_s16 dst = get_word(dsta);
39330: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39331: { int flgs = ((uae_s16)(src)) < 0;
39332: int flgo = ((uae_s16)(dst)) < 0;
39333: int flgn = ((uae_s16)(newv)) < 0;
39334: SET_ZFLG (((uae_s16)(newv)) == 0);
39335: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39336: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39337: SET_NFLG (flgn != 0);
39338: }}}}}}}}m68k_incpc(6);
39339: fill_prefetch_0 ();
39340: endlabel2383: ;
39341: return 16;
39342: }
39343: unsigned long REGPARAM2 CPUFUNC(op_c79_5)(uae_u32 opcode) /* CMP */
39344: {
39345: OpcodeFamily = 25; CurrentInstrCycles = 20;
39346: {{ uae_s16 src = get_iword_prefetch(2);
39347: { uaecptr dsta = get_ilong_prefetch(4);
39348: if ((dsta & 1) != 0) {
39349: last_fault_for_exception_3 = dsta;
39350: last_op_for_exception_3 = opcode;
39351: last_addr_for_exception_3 = m68k_getpc() + 8;
39352: Exception(3, 0, M68000_EXC_SRC_CPU);
39353: goto endlabel2384;
39354: }
39355: {{ uae_s16 dst = get_word(dsta);
39356: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39357: { int flgs = ((uae_s16)(src)) < 0;
39358: int flgo = ((uae_s16)(dst)) < 0;
39359: int flgn = ((uae_s16)(newv)) < 0;
39360: SET_ZFLG (((uae_s16)(newv)) == 0);
39361: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39362: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39363: SET_NFLG (flgn != 0);
39364: }}}}}}}}m68k_incpc(8);
39365: fill_prefetch_0 ();
39366: endlabel2384: ;
39367: return 20;
39368: }
39369: unsigned long REGPARAM2 CPUFUNC(op_c7a_5)(uae_u32 opcode) /* CMP */
39370: {
39371: uae_u32 dstreg = 2;
39372: OpcodeFamily = 25; CurrentInstrCycles = 16;
39373: {{ uae_s16 src = get_iword_prefetch(2);
39374: { uaecptr dsta = m68k_getpc () + 4;
39375: dsta += (uae_s32)(uae_s16)get_iword_prefetch(4);
39376: if ((dsta & 1) != 0) {
39377: last_fault_for_exception_3 = dsta;
39378: last_op_for_exception_3 = opcode;
39379: last_addr_for_exception_3 = m68k_getpc() + 6;
39380: Exception(3, 0, M68000_EXC_SRC_CPU);
39381: goto endlabel2385;
39382: }
39383: {{ uae_s16 dst = get_word(dsta);
39384: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39385: { int flgs = ((uae_s16)(src)) < 0;
39386: int flgo = ((uae_s16)(dst)) < 0;
39387: int flgn = ((uae_s16)(newv)) < 0;
39388: SET_ZFLG (((uae_s16)(newv)) == 0);
39389: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39390: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39391: SET_NFLG (flgn != 0);
39392: }}}}}}}}m68k_incpc(6);
39393: fill_prefetch_0 ();
39394: endlabel2385: ;
39395: return 16;
39396: }
39397: unsigned long REGPARAM2 CPUFUNC(op_c7b_5)(uae_u32 opcode) /* CMP */
39398: {
39399: uae_u32 dstreg = 3;
39400: OpcodeFamily = 25; CurrentInstrCycles = 18;
39401: {{ uae_s16 src = get_iword_prefetch(2);
39402: { uaecptr tmppc = m68k_getpc() + 4;
39403: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4));
39404: BusCyclePenalty += 2;
39405: if ((dsta & 1) != 0) {
39406: last_fault_for_exception_3 = dsta;
39407: last_op_for_exception_3 = opcode;
39408: last_addr_for_exception_3 = m68k_getpc() + 6;
39409: Exception(3, 0, M68000_EXC_SRC_CPU);
39410: goto endlabel2386;
39411: }
39412: {{ uae_s16 dst = get_word(dsta);
39413: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
39414: { int flgs = ((uae_s16)(src)) < 0;
39415: int flgo = ((uae_s16)(dst)) < 0;
39416: int flgn = ((uae_s16)(newv)) < 0;
39417: SET_ZFLG (((uae_s16)(newv)) == 0);
39418: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39419: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
39420: SET_NFLG (flgn != 0);
39421: }}}}}}}}m68k_incpc(6);
39422: fill_prefetch_0 ();
39423: endlabel2386: ;
39424: return 18;
39425: }
39426: unsigned long REGPARAM2 CPUFUNC(op_c80_5)(uae_u32 opcode) /* CMP */
39427: {
39428: uae_u32 dstreg = opcode & 7;
39429: OpcodeFamily = 25; CurrentInstrCycles = 14;
39430: {{ uae_s32 src = get_ilong_prefetch(2);
39431: { uae_s32 dst = m68k_dreg(regs, dstreg);
39432: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39433: { int flgs = ((uae_s32)(src)) < 0;
39434: int flgo = ((uae_s32)(dst)) < 0;
39435: int flgn = ((uae_s32)(newv)) < 0;
39436: SET_ZFLG (((uae_s32)(newv)) == 0);
39437: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39438: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39439: SET_NFLG (flgn != 0);
39440: }}}}}}m68k_incpc(6);
39441: fill_prefetch_0 ();
39442: return 14;
39443: }
39444: unsigned long REGPARAM2 CPUFUNC(op_c90_5)(uae_u32 opcode) /* CMP */
39445: {
39446: uae_u32 dstreg = opcode & 7;
39447: OpcodeFamily = 25; CurrentInstrCycles = 20;
39448: {{ uae_s32 src = get_ilong_prefetch(2);
39449: { uaecptr dsta = m68k_areg(regs, dstreg);
39450: if ((dsta & 1) != 0) {
39451: last_fault_for_exception_3 = dsta;
39452: last_op_for_exception_3 = opcode;
39453: last_addr_for_exception_3 = m68k_getpc() + 6;
39454: Exception(3, 0, M68000_EXC_SRC_CPU);
39455: goto endlabel2388;
39456: }
39457: {{ uae_s32 dst = get_long(dsta);
39458: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39459: { int flgs = ((uae_s32)(src)) < 0;
39460: int flgo = ((uae_s32)(dst)) < 0;
39461: int flgn = ((uae_s32)(newv)) < 0;
39462: SET_ZFLG (((uae_s32)(newv)) == 0);
39463: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39464: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39465: SET_NFLG (flgn != 0);
39466: }}}}}}}}m68k_incpc(6);
39467: fill_prefetch_0 ();
39468: endlabel2388: ;
39469: return 20;
39470: }
39471: unsigned long REGPARAM2 CPUFUNC(op_c98_5)(uae_u32 opcode) /* CMP */
39472: {
39473: uae_u32 dstreg = opcode & 7;
39474: OpcodeFamily = 25; CurrentInstrCycles = 20;
39475: {{ uae_s32 src = get_ilong_prefetch(2);
39476: { uaecptr dsta = m68k_areg(regs, dstreg);
39477: if ((dsta & 1) != 0) {
39478: last_fault_for_exception_3 = dsta;
39479: last_op_for_exception_3 = opcode;
39480: last_addr_for_exception_3 = m68k_getpc() + 6;
39481: Exception(3, 0, M68000_EXC_SRC_CPU);
39482: goto endlabel2389;
39483: }
39484: {{ uae_s32 dst = get_long(dsta);
39485: m68k_areg(regs, dstreg) += 4;
39486: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39487: { int flgs = ((uae_s32)(src)) < 0;
39488: int flgo = ((uae_s32)(dst)) < 0;
39489: int flgn = ((uae_s32)(newv)) < 0;
39490: SET_ZFLG (((uae_s32)(newv)) == 0);
39491: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39492: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39493: SET_NFLG (flgn != 0);
39494: }}}}}}}}m68k_incpc(6);
39495: fill_prefetch_0 ();
39496: endlabel2389: ;
39497: return 20;
39498: }
39499: unsigned long REGPARAM2 CPUFUNC(op_ca0_5)(uae_u32 opcode) /* CMP */
39500: {
39501: uae_u32 dstreg = opcode & 7;
39502: OpcodeFamily = 25; CurrentInstrCycles = 22;
39503: {{ uae_s32 src = get_ilong_prefetch(2);
39504: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
39505: if ((dsta & 1) != 0) {
39506: last_fault_for_exception_3 = dsta;
39507: last_op_for_exception_3 = opcode;
39508: last_addr_for_exception_3 = m68k_getpc() + 6;
39509: Exception(3, 0, M68000_EXC_SRC_CPU);
39510: goto endlabel2390;
39511: }
39512: {{ uae_s32 dst = get_long(dsta);
39513: m68k_areg (regs, dstreg) = dsta;
39514: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39515: { int flgs = ((uae_s32)(src)) < 0;
39516: int flgo = ((uae_s32)(dst)) < 0;
39517: int flgn = ((uae_s32)(newv)) < 0;
39518: SET_ZFLG (((uae_s32)(newv)) == 0);
39519: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39520: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39521: SET_NFLG (flgn != 0);
39522: }}}}}}}}m68k_incpc(6);
39523: fill_prefetch_0 ();
39524: endlabel2390: ;
39525: return 22;
39526: }
39527: unsigned long REGPARAM2 CPUFUNC(op_ca8_5)(uae_u32 opcode) /* CMP */
39528: {
39529: uae_u32 dstreg = opcode & 7;
39530: OpcodeFamily = 25; CurrentInstrCycles = 24;
39531: {{ uae_s32 src = get_ilong_prefetch(2);
39532: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
39533: if ((dsta & 1) != 0) {
39534: last_fault_for_exception_3 = dsta;
39535: last_op_for_exception_3 = opcode;
39536: last_addr_for_exception_3 = m68k_getpc() + 8;
39537: Exception(3, 0, M68000_EXC_SRC_CPU);
39538: goto endlabel2391;
39539: }
39540: {{ uae_s32 dst = get_long(dsta);
39541: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39542: { int flgs = ((uae_s32)(src)) < 0;
39543: int flgo = ((uae_s32)(dst)) < 0;
39544: int flgn = ((uae_s32)(newv)) < 0;
39545: SET_ZFLG (((uae_s32)(newv)) == 0);
39546: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39547: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39548: SET_NFLG (flgn != 0);
39549: }}}}}}}}m68k_incpc(8);
39550: fill_prefetch_0 ();
39551: endlabel2391: ;
39552: return 24;
39553: }
39554: unsigned long REGPARAM2 CPUFUNC(op_cb0_5)(uae_u32 opcode) /* CMP */
39555: {
39556: uae_u32 dstreg = opcode & 7;
39557: OpcodeFamily = 25; CurrentInstrCycles = 26;
39558: {{ uae_s32 src = get_ilong_prefetch(2);
39559: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
39560: BusCyclePenalty += 2;
39561: if ((dsta & 1) != 0) {
39562: last_fault_for_exception_3 = dsta;
39563: last_op_for_exception_3 = opcode;
39564: last_addr_for_exception_3 = m68k_getpc() + 8;
39565: Exception(3, 0, M68000_EXC_SRC_CPU);
39566: goto endlabel2392;
39567: }
39568: {{ uae_s32 dst = get_long(dsta);
39569: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39570: { int flgs = ((uae_s32)(src)) < 0;
39571: int flgo = ((uae_s32)(dst)) < 0;
39572: int flgn = ((uae_s32)(newv)) < 0;
39573: SET_ZFLG (((uae_s32)(newv)) == 0);
39574: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39575: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39576: SET_NFLG (flgn != 0);
39577: }}}}}}}}m68k_incpc(8);
39578: fill_prefetch_0 ();
39579: endlabel2392: ;
39580: return 26;
39581: }
39582: unsigned long REGPARAM2 CPUFUNC(op_cb8_5)(uae_u32 opcode) /* CMP */
39583: {
39584: OpcodeFamily = 25; CurrentInstrCycles = 24;
39585: {{ uae_s32 src = get_ilong_prefetch(2);
39586: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
39587: if ((dsta & 1) != 0) {
39588: last_fault_for_exception_3 = dsta;
39589: last_op_for_exception_3 = opcode;
39590: last_addr_for_exception_3 = m68k_getpc() + 8;
39591: Exception(3, 0, M68000_EXC_SRC_CPU);
39592: goto endlabel2393;
39593: }
39594: {{ uae_s32 dst = get_long(dsta);
39595: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39596: { int flgs = ((uae_s32)(src)) < 0;
39597: int flgo = ((uae_s32)(dst)) < 0;
39598: int flgn = ((uae_s32)(newv)) < 0;
39599: SET_ZFLG (((uae_s32)(newv)) == 0);
39600: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39601: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39602: SET_NFLG (flgn != 0);
39603: }}}}}}}}m68k_incpc(8);
39604: fill_prefetch_0 ();
39605: endlabel2393: ;
39606: return 24;
39607: }
39608: unsigned long REGPARAM2 CPUFUNC(op_cb9_5)(uae_u32 opcode) /* CMP */
39609: {
39610: OpcodeFamily = 25; CurrentInstrCycles = 28;
39611: {{ uae_s32 src = get_ilong_prefetch(2);
39612: { uaecptr dsta = get_ilong_prefetch(6);
39613: if ((dsta & 1) != 0) {
39614: last_fault_for_exception_3 = dsta;
39615: last_op_for_exception_3 = opcode;
39616: last_addr_for_exception_3 = m68k_getpc() + 10;
39617: Exception(3, 0, M68000_EXC_SRC_CPU);
39618: goto endlabel2394;
39619: }
39620: {{ uae_s32 dst = get_long(dsta);
39621: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39622: { int flgs = ((uae_s32)(src)) < 0;
39623: int flgo = ((uae_s32)(dst)) < 0;
39624: int flgn = ((uae_s32)(newv)) < 0;
39625: SET_ZFLG (((uae_s32)(newv)) == 0);
39626: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39627: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39628: SET_NFLG (flgn != 0);
39629: }}}}}}}}m68k_incpc(10);
39630: fill_prefetch_0 ();
39631: endlabel2394: ;
39632: return 28;
39633: }
39634: unsigned long REGPARAM2 CPUFUNC(op_cba_5)(uae_u32 opcode) /* CMP */
39635: {
39636: uae_u32 dstreg = 2;
39637: OpcodeFamily = 25; CurrentInstrCycles = 24;
39638: {{ uae_s32 src = get_ilong_prefetch(2);
39639: { uaecptr dsta = m68k_getpc () + 6;
39640: dsta += (uae_s32)(uae_s16)get_iword_prefetch(6);
39641: if ((dsta & 1) != 0) {
39642: last_fault_for_exception_3 = dsta;
39643: last_op_for_exception_3 = opcode;
39644: last_addr_for_exception_3 = m68k_getpc() + 8;
39645: Exception(3, 0, M68000_EXC_SRC_CPU);
39646: goto endlabel2395;
39647: }
39648: {{ uae_s32 dst = get_long(dsta);
39649: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39650: { int flgs = ((uae_s32)(src)) < 0;
39651: int flgo = ((uae_s32)(dst)) < 0;
39652: int flgn = ((uae_s32)(newv)) < 0;
39653: SET_ZFLG (((uae_s32)(newv)) == 0);
39654: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39655: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39656: SET_NFLG (flgn != 0);
39657: }}}}}}}}m68k_incpc(8);
39658: fill_prefetch_0 ();
39659: endlabel2395: ;
39660: return 24;
39661: }
39662: unsigned long REGPARAM2 CPUFUNC(op_cbb_5)(uae_u32 opcode) /* CMP */
39663: {
39664: uae_u32 dstreg = 3;
39665: OpcodeFamily = 25; CurrentInstrCycles = 26;
39666: {{ uae_s32 src = get_ilong_prefetch(2);
39667: { uaecptr tmppc = m68k_getpc() + 6;
39668: uaecptr dsta = get_disp_ea_000(tmppc, get_iword_prefetch(6));
39669: BusCyclePenalty += 2;
39670: if ((dsta & 1) != 0) {
39671: last_fault_for_exception_3 = dsta;
39672: last_op_for_exception_3 = opcode;
39673: last_addr_for_exception_3 = m68k_getpc() + 8;
39674: Exception(3, 0, M68000_EXC_SRC_CPU);
39675: goto endlabel2396;
39676: }
39677: {{ uae_s32 dst = get_long(dsta);
39678: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
39679: { int flgs = ((uae_s32)(src)) < 0;
39680: int flgo = ((uae_s32)(dst)) < 0;
39681: int flgn = ((uae_s32)(newv)) < 0;
39682: SET_ZFLG (((uae_s32)(newv)) == 0);
39683: SET_VFLG ((flgs != flgo) && (flgn != flgo));
39684: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
39685: SET_NFLG (flgn != 0);
39686: }}}}}}}}m68k_incpc(8);
39687: fill_prefetch_0 ();
39688: endlabel2396: ;
39689: return 26;
39690: }
39691: unsigned long REGPARAM2 CPUFUNC(op_1000_5)(uae_u32 opcode) /* MOVE */
39692: {
39693: uae_u32 srcreg = (opcode & 7);
39694: uae_u32 dstreg = (opcode >> 9) & 7;
39695: OpcodeFamily = 30; CurrentInstrCycles = 4;
39696: {{ uae_s8 src = m68k_dreg(regs, srcreg);
39697: { CLEAR_CZNV;
39698: SET_ZFLG (((uae_s8)(src)) == 0);
39699: SET_NFLG (((uae_s8)(src)) < 0);
39700: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39701: }}}m68k_incpc(2);
39702: fill_prefetch_2 ();
39703: return 4;
39704: }
39705: unsigned long REGPARAM2 CPUFUNC(op_1008_5)(uae_u32 opcode) /* MOVE */
39706: {
39707: uae_u32 srcreg = (opcode & 7);
39708: uae_u32 dstreg = (opcode >> 9) & 7;
39709: OpcodeFamily = 30; CurrentInstrCycles = 4;
39710: {{ uae_s8 src = m68k_areg(regs, srcreg);
39711: { CLEAR_CZNV;
39712: SET_ZFLG (((uae_s8)(src)) == 0);
39713: SET_NFLG (((uae_s8)(src)) < 0);
39714: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39715: }}}m68k_incpc(2);
39716: fill_prefetch_2 ();
39717: return 4;
39718: }
39719: unsigned long REGPARAM2 CPUFUNC(op_1010_5)(uae_u32 opcode) /* MOVE */
39720: {
39721: uae_u32 srcreg = (opcode & 7);
39722: uae_u32 dstreg = (opcode >> 9) & 7;
39723: OpcodeFamily = 30; CurrentInstrCycles = 8;
39724: {{ uaecptr srca = m68k_areg(regs, srcreg);
39725: { uae_s8 src = get_byte(srca);
39726: { CLEAR_CZNV;
39727: SET_ZFLG (((uae_s8)(src)) == 0);
39728: SET_NFLG (((uae_s8)(src)) < 0);
39729: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39730: }}}}m68k_incpc(2);
39731: fill_prefetch_2 ();
39732: return 8;
39733: }
39734: unsigned long REGPARAM2 CPUFUNC(op_1018_5)(uae_u32 opcode) /* MOVE */
39735: {
39736: uae_u32 srcreg = (opcode & 7);
39737: uae_u32 dstreg = (opcode >> 9) & 7;
39738: OpcodeFamily = 30; CurrentInstrCycles = 8;
39739: {{ uaecptr srca = m68k_areg(regs, srcreg);
39740: { uae_s8 src = get_byte(srca);
39741: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
39742: { CLEAR_CZNV;
39743: SET_ZFLG (((uae_s8)(src)) == 0);
39744: SET_NFLG (((uae_s8)(src)) < 0);
39745: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39746: }}}}m68k_incpc(2);
39747: fill_prefetch_2 ();
39748: return 8;
39749: }
39750: unsigned long REGPARAM2 CPUFUNC(op_1020_5)(uae_u32 opcode) /* MOVE */
39751: {
39752: uae_u32 srcreg = (opcode & 7);
39753: uae_u32 dstreg = (opcode >> 9) & 7;
39754: OpcodeFamily = 30; CurrentInstrCycles = 10;
39755: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
39756: { uae_s8 src = get_byte(srca);
39757: m68k_areg (regs, srcreg) = srca;
39758: { CLEAR_CZNV;
39759: SET_ZFLG (((uae_s8)(src)) == 0);
39760: SET_NFLG (((uae_s8)(src)) < 0);
39761: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39762: }}}}m68k_incpc(2);
39763: fill_prefetch_2 ();
39764: return 10;
39765: }
39766: unsigned long REGPARAM2 CPUFUNC(op_1028_5)(uae_u32 opcode) /* MOVE */
39767: {
39768: uae_u32 srcreg = (opcode & 7);
39769: uae_u32 dstreg = (opcode >> 9) & 7;
39770: OpcodeFamily = 30; CurrentInstrCycles = 12;
39771: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
39772: { uae_s8 src = get_byte(srca);
39773: { CLEAR_CZNV;
39774: SET_ZFLG (((uae_s8)(src)) == 0);
39775: SET_NFLG (((uae_s8)(src)) < 0);
39776: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39777: }}}}m68k_incpc(4);
39778: fill_prefetch_0 ();
39779: return 12;
39780: }
39781: unsigned long REGPARAM2 CPUFUNC(op_1030_5)(uae_u32 opcode) /* MOVE */
39782: {
39783: uae_u32 srcreg = (opcode & 7);
39784: uae_u32 dstreg = (opcode >> 9) & 7;
39785: OpcodeFamily = 30; CurrentInstrCycles = 14;
39786: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
39787: BusCyclePenalty += 2;
39788: { uae_s8 src = get_byte(srca);
39789: { CLEAR_CZNV;
39790: SET_ZFLG (((uae_s8)(src)) == 0);
39791: SET_NFLG (((uae_s8)(src)) < 0);
39792: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39793: }}}}m68k_incpc(4);
39794: fill_prefetch_0 ();
39795: return 14;
39796: }
39797: unsigned long REGPARAM2 CPUFUNC(op_1038_5)(uae_u32 opcode) /* MOVE */
39798: {
39799: uae_u32 dstreg = (opcode >> 9) & 7;
39800: OpcodeFamily = 30; CurrentInstrCycles = 12;
39801: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
39802: { uae_s8 src = get_byte(srca);
39803: { CLEAR_CZNV;
39804: SET_ZFLG (((uae_s8)(src)) == 0);
39805: SET_NFLG (((uae_s8)(src)) < 0);
39806: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39807: }}}}m68k_incpc(4);
39808: fill_prefetch_0 ();
39809: return 12;
39810: }
39811: unsigned long REGPARAM2 CPUFUNC(op_1039_5)(uae_u32 opcode) /* MOVE */
39812: {
39813: uae_u32 dstreg = (opcode >> 9) & 7;
39814: OpcodeFamily = 30; CurrentInstrCycles = 16;
39815: {{ uaecptr srca = get_ilong_prefetch(2);
39816: { uae_s8 src = get_byte(srca);
39817: { CLEAR_CZNV;
39818: SET_ZFLG (((uae_s8)(src)) == 0);
39819: SET_NFLG (((uae_s8)(src)) < 0);
39820: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39821: }}}}m68k_incpc(6);
39822: fill_prefetch_0 ();
39823: return 16;
39824: }
39825: unsigned long REGPARAM2 CPUFUNC(op_103a_5)(uae_u32 opcode) /* MOVE */
39826: {
39827: uae_u32 dstreg = (opcode >> 9) & 7;
39828: OpcodeFamily = 30; CurrentInstrCycles = 12;
39829: {{ uaecptr srca = m68k_getpc () + 2;
39830: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
39831: { uae_s8 src = get_byte(srca);
39832: { CLEAR_CZNV;
39833: SET_ZFLG (((uae_s8)(src)) == 0);
39834: SET_NFLG (((uae_s8)(src)) < 0);
39835: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39836: }}}}m68k_incpc(4);
39837: fill_prefetch_0 ();
39838: return 12;
39839: }
39840: unsigned long REGPARAM2 CPUFUNC(op_103b_5)(uae_u32 opcode) /* MOVE */
39841: {
39842: uae_u32 dstreg = (opcode >> 9) & 7;
39843: OpcodeFamily = 30; CurrentInstrCycles = 14;
39844: {{ uaecptr tmppc = m68k_getpc() + 2;
39845: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
39846: BusCyclePenalty += 2;
39847: { uae_s8 src = get_byte(srca);
39848: { CLEAR_CZNV;
39849: SET_ZFLG (((uae_s8)(src)) == 0);
39850: SET_NFLG (((uae_s8)(src)) < 0);
39851: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39852: }}}}m68k_incpc(4);
39853: fill_prefetch_0 ();
39854: return 14;
39855: }
39856: unsigned long REGPARAM2 CPUFUNC(op_103c_5)(uae_u32 opcode) /* MOVE */
39857: {
39858: uae_u32 dstreg = (opcode >> 9) & 7;
39859: OpcodeFamily = 30; CurrentInstrCycles = 8;
39860: {{ uae_s8 src = get_ibyte_prefetch(2);
39861: { CLEAR_CZNV;
39862: SET_ZFLG (((uae_s8)(src)) == 0);
39863: SET_NFLG (((uae_s8)(src)) < 0);
39864: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
39865: }}}m68k_incpc(4);
39866: fill_prefetch_0 ();
39867: return 8;
39868: }
39869: unsigned long REGPARAM2 CPUFUNC(op_1080_5)(uae_u32 opcode) /* MOVE */
39870: {
39871: uae_u32 srcreg = (opcode & 7);
39872: uae_u32 dstreg = (opcode >> 9) & 7;
39873: OpcodeFamily = 30; CurrentInstrCycles = 8;
39874: {{ uae_s8 src = m68k_dreg(regs, srcreg);
39875: { uaecptr dsta = m68k_areg(regs, dstreg);
39876: CLEAR_CZNV;
39877: SET_ZFLG (((uae_s8)(src)) == 0);
39878: SET_NFLG (((uae_s8)(src)) < 0);
39879: m68k_incpc(2);
39880: fill_prefetch_2 ();
39881: put_byte(dsta,src);
39882: }}}return 8;
39883: }
39884: unsigned long REGPARAM2 CPUFUNC(op_1088_5)(uae_u32 opcode) /* MOVE */
39885: {
39886: uae_u32 srcreg = (opcode & 7);
39887: uae_u32 dstreg = (opcode >> 9) & 7;
39888: OpcodeFamily = 30; CurrentInstrCycles = 8;
39889: {{ uae_s8 src = m68k_areg(regs, srcreg);
39890: { uaecptr dsta = m68k_areg(regs, dstreg);
39891: CLEAR_CZNV;
39892: SET_ZFLG (((uae_s8)(src)) == 0);
39893: SET_NFLG (((uae_s8)(src)) < 0);
39894: m68k_incpc(2);
39895: fill_prefetch_2 ();
39896: put_byte(dsta,src);
39897: }}}return 8;
39898: }
39899: unsigned long REGPARAM2 CPUFUNC(op_1090_5)(uae_u32 opcode) /* MOVE */
39900: {
39901: uae_u32 srcreg = (opcode & 7);
39902: uae_u32 dstreg = (opcode >> 9) & 7;
39903: OpcodeFamily = 30; CurrentInstrCycles = 12;
39904: {{ uaecptr srca = m68k_areg(regs, srcreg);
39905: { uae_s8 src = get_byte(srca);
39906: { uaecptr dsta = m68k_areg(regs, dstreg);
39907: CLEAR_CZNV;
39908: SET_ZFLG (((uae_s8)(src)) == 0);
39909: SET_NFLG (((uae_s8)(src)) < 0);
39910: m68k_incpc(2);
39911: fill_prefetch_2 ();
39912: put_byte(dsta,src);
39913: }}}}return 12;
39914: }
39915: unsigned long REGPARAM2 CPUFUNC(op_1098_5)(uae_u32 opcode) /* MOVE */
39916: {
39917: uae_u32 srcreg = (opcode & 7);
39918: uae_u32 dstreg = (opcode >> 9) & 7;
39919: OpcodeFamily = 30; CurrentInstrCycles = 12;
39920: {{ uaecptr srca = m68k_areg(regs, srcreg);
39921: { uae_s8 src = get_byte(srca);
39922: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
39923: { uaecptr dsta = m68k_areg(regs, dstreg);
39924: CLEAR_CZNV;
39925: SET_ZFLG (((uae_s8)(src)) == 0);
39926: SET_NFLG (((uae_s8)(src)) < 0);
39927: m68k_incpc(2);
39928: fill_prefetch_2 ();
39929: put_byte(dsta,src);
39930: }}}}return 12;
39931: }
39932: unsigned long REGPARAM2 CPUFUNC(op_10a0_5)(uae_u32 opcode) /* MOVE */
39933: {
39934: uae_u32 srcreg = (opcode & 7);
39935: uae_u32 dstreg = (opcode >> 9) & 7;
39936: OpcodeFamily = 30; CurrentInstrCycles = 14;
39937: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
39938: { uae_s8 src = get_byte(srca);
39939: m68k_areg (regs, srcreg) = srca;
39940: { uaecptr dsta = m68k_areg(regs, dstreg);
39941: CLEAR_CZNV;
39942: SET_ZFLG (((uae_s8)(src)) == 0);
39943: SET_NFLG (((uae_s8)(src)) < 0);
39944: m68k_incpc(2);
39945: fill_prefetch_2 ();
39946: put_byte(dsta,src);
39947: }}}}return 14;
39948: }
39949: unsigned long REGPARAM2 CPUFUNC(op_10a8_5)(uae_u32 opcode) /* MOVE */
39950: {
39951: uae_u32 srcreg = (opcode & 7);
39952: uae_u32 dstreg = (opcode >> 9) & 7;
39953: OpcodeFamily = 30; CurrentInstrCycles = 16;
39954: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
39955: { uae_s8 src = get_byte(srca);
39956: { uaecptr dsta = m68k_areg(regs, dstreg);
39957: CLEAR_CZNV;
39958: SET_ZFLG (((uae_s8)(src)) == 0);
39959: SET_NFLG (((uae_s8)(src)) < 0);
39960: m68k_incpc(4);
39961: fill_prefetch_0 ();
39962: put_byte(dsta,src);
39963: }}}}return 16;
39964: }
39965: unsigned long REGPARAM2 CPUFUNC(op_10b0_5)(uae_u32 opcode) /* MOVE */
39966: {
39967: uae_u32 srcreg = (opcode & 7);
39968: uae_u32 dstreg = (opcode >> 9) & 7;
39969: OpcodeFamily = 30; CurrentInstrCycles = 18;
39970: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
39971: BusCyclePenalty += 2;
39972: { uae_s8 src = get_byte(srca);
39973: { uaecptr dsta = m68k_areg(regs, dstreg);
39974: CLEAR_CZNV;
39975: SET_ZFLG (((uae_s8)(src)) == 0);
39976: SET_NFLG (((uae_s8)(src)) < 0);
39977: m68k_incpc(4);
39978: fill_prefetch_0 ();
39979: put_byte(dsta,src);
39980: }}}}return 18;
39981: }
39982: unsigned long REGPARAM2 CPUFUNC(op_10b8_5)(uae_u32 opcode) /* MOVE */
39983: {
39984: uae_u32 dstreg = (opcode >> 9) & 7;
39985: OpcodeFamily = 30; CurrentInstrCycles = 16;
39986: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
39987: { uae_s8 src = get_byte(srca);
39988: { uaecptr dsta = m68k_areg(regs, dstreg);
39989: CLEAR_CZNV;
39990: SET_ZFLG (((uae_s8)(src)) == 0);
39991: SET_NFLG (((uae_s8)(src)) < 0);
39992: m68k_incpc(4);
39993: fill_prefetch_0 ();
39994: put_byte(dsta,src);
39995: }}}}return 16;
39996: }
39997: unsigned long REGPARAM2 CPUFUNC(op_10b9_5)(uae_u32 opcode) /* MOVE */
39998: {
39999: uae_u32 dstreg = (opcode >> 9) & 7;
40000: OpcodeFamily = 30; CurrentInstrCycles = 20;
40001: {{ uaecptr srca = get_ilong_prefetch(2);
40002: { uae_s8 src = get_byte(srca);
40003: { uaecptr dsta = m68k_areg(regs, dstreg);
40004: CLEAR_CZNV;
40005: SET_ZFLG (((uae_s8)(src)) == 0);
40006: SET_NFLG (((uae_s8)(src)) < 0);
40007: m68k_incpc(6);
40008: fill_prefetch_0 ();
40009: put_byte(dsta,src);
40010: }}}}return 20;
40011: }
40012: unsigned long REGPARAM2 CPUFUNC(op_10ba_5)(uae_u32 opcode) /* MOVE */
40013: {
40014: uae_u32 dstreg = (opcode >> 9) & 7;
40015: OpcodeFamily = 30; CurrentInstrCycles = 16;
40016: {{ uaecptr srca = m68k_getpc () + 2;
40017: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
40018: { uae_s8 src = get_byte(srca);
40019: { uaecptr dsta = m68k_areg(regs, dstreg);
40020: CLEAR_CZNV;
40021: SET_ZFLG (((uae_s8)(src)) == 0);
40022: SET_NFLG (((uae_s8)(src)) < 0);
40023: m68k_incpc(4);
40024: fill_prefetch_0 ();
40025: put_byte(dsta,src);
40026: }}}}return 16;
40027: }
40028: unsigned long REGPARAM2 CPUFUNC(op_10bb_5)(uae_u32 opcode) /* MOVE */
40029: {
40030: uae_u32 dstreg = (opcode >> 9) & 7;
40031: OpcodeFamily = 30; CurrentInstrCycles = 18;
40032: {{ uaecptr tmppc = m68k_getpc() + 2;
40033: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
40034: BusCyclePenalty += 2;
40035: { uae_s8 src = get_byte(srca);
40036: { uaecptr dsta = m68k_areg(regs, dstreg);
40037: CLEAR_CZNV;
40038: SET_ZFLG (((uae_s8)(src)) == 0);
40039: SET_NFLG (((uae_s8)(src)) < 0);
40040: m68k_incpc(4);
40041: fill_prefetch_0 ();
40042: put_byte(dsta,src);
40043: }}}}return 18;
40044: }
40045: unsigned long REGPARAM2 CPUFUNC(op_10bc_5)(uae_u32 opcode) /* MOVE */
40046: {
40047: uae_u32 dstreg = (opcode >> 9) & 7;
40048: OpcodeFamily = 30; CurrentInstrCycles = 12;
40049: {{ uae_s8 src = get_ibyte_prefetch(2);
40050: { uaecptr dsta = m68k_areg(regs, dstreg);
40051: CLEAR_CZNV;
40052: SET_ZFLG (((uae_s8)(src)) == 0);
40053: SET_NFLG (((uae_s8)(src)) < 0);
40054: m68k_incpc(4);
40055: fill_prefetch_0 ();
40056: put_byte(dsta,src);
40057: }}}return 12;
40058: }
40059: unsigned long REGPARAM2 CPUFUNC(op_10c0_5)(uae_u32 opcode) /* MOVE */
40060: {
40061: uae_u32 srcreg = (opcode & 7);
40062: uae_u32 dstreg = (opcode >> 9) & 7;
40063: OpcodeFamily = 30; CurrentInstrCycles = 8;
40064: {{ uae_s8 src = m68k_dreg(regs, srcreg);
40065: { uaecptr dsta = m68k_areg(regs, dstreg);
40066: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40067: CLEAR_CZNV;
40068: SET_ZFLG (((uae_s8)(src)) == 0);
40069: SET_NFLG (((uae_s8)(src)) < 0);
40070: m68k_incpc(2);
40071: fill_prefetch_2 ();
40072: put_byte(dsta,src);
40073: }}}return 8;
40074: }
40075: unsigned long REGPARAM2 CPUFUNC(op_10c8_5)(uae_u32 opcode) /* MOVE */
40076: {
40077: uae_u32 srcreg = (opcode & 7);
40078: uae_u32 dstreg = (opcode >> 9) & 7;
40079: OpcodeFamily = 30; CurrentInstrCycles = 8;
40080: {{ uae_s8 src = m68k_areg(regs, srcreg);
40081: { uaecptr dsta = m68k_areg(regs, dstreg);
40082: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40083: CLEAR_CZNV;
40084: SET_ZFLG (((uae_s8)(src)) == 0);
40085: SET_NFLG (((uae_s8)(src)) < 0);
40086: m68k_incpc(2);
40087: fill_prefetch_2 ();
40088: put_byte(dsta,src);
40089: }}}return 8;
40090: }
40091: unsigned long REGPARAM2 CPUFUNC(op_10d0_5)(uae_u32 opcode) /* MOVE */
40092: {
40093: uae_u32 srcreg = (opcode & 7);
40094: uae_u32 dstreg = (opcode >> 9) & 7;
40095: OpcodeFamily = 30; CurrentInstrCycles = 12;
40096: {{ uaecptr srca = m68k_areg(regs, srcreg);
40097: { uae_s8 src = get_byte(srca);
40098: { uaecptr dsta = m68k_areg(regs, dstreg);
40099: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40100: CLEAR_CZNV;
40101: SET_ZFLG (((uae_s8)(src)) == 0);
40102: SET_NFLG (((uae_s8)(src)) < 0);
40103: m68k_incpc(2);
40104: fill_prefetch_2 ();
40105: put_byte(dsta,src);
40106: }}}}return 12;
40107: }
40108: unsigned long REGPARAM2 CPUFUNC(op_10d8_5)(uae_u32 opcode) /* MOVE */
40109: {
40110: uae_u32 srcreg = (opcode & 7);
40111: uae_u32 dstreg = (opcode >> 9) & 7;
40112: OpcodeFamily = 30; CurrentInstrCycles = 12;
40113: {{ uaecptr srca = m68k_areg(regs, srcreg);
40114: { uae_s8 src = get_byte(srca);
40115: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
40116: { uaecptr dsta = m68k_areg(regs, dstreg);
40117: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40118: CLEAR_CZNV;
40119: SET_ZFLG (((uae_s8)(src)) == 0);
40120: SET_NFLG (((uae_s8)(src)) < 0);
40121: m68k_incpc(2);
40122: fill_prefetch_2 ();
40123: put_byte(dsta,src);
40124: }}}}return 12;
40125: }
40126: unsigned long REGPARAM2 CPUFUNC(op_10e0_5)(uae_u32 opcode) /* MOVE */
40127: {
40128: uae_u32 srcreg = (opcode & 7);
40129: uae_u32 dstreg = (opcode >> 9) & 7;
40130: OpcodeFamily = 30; CurrentInstrCycles = 14;
40131: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
40132: { uae_s8 src = get_byte(srca);
40133: m68k_areg (regs, srcreg) = srca;
40134: { uaecptr dsta = m68k_areg(regs, dstreg);
40135: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40136: CLEAR_CZNV;
40137: SET_ZFLG (((uae_s8)(src)) == 0);
40138: SET_NFLG (((uae_s8)(src)) < 0);
40139: m68k_incpc(2);
40140: fill_prefetch_2 ();
40141: put_byte(dsta,src);
40142: }}}}return 14;
40143: }
40144: unsigned long REGPARAM2 CPUFUNC(op_10e8_5)(uae_u32 opcode) /* MOVE */
40145: {
40146: uae_u32 srcreg = (opcode & 7);
40147: uae_u32 dstreg = (opcode >> 9) & 7;
40148: OpcodeFamily = 30; CurrentInstrCycles = 16;
40149: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40150: { uae_s8 src = get_byte(srca);
40151: { uaecptr dsta = m68k_areg(regs, dstreg);
40152: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40153: CLEAR_CZNV;
40154: SET_ZFLG (((uae_s8)(src)) == 0);
40155: SET_NFLG (((uae_s8)(src)) < 0);
40156: m68k_incpc(4);
40157: fill_prefetch_0 ();
40158: put_byte(dsta,src);
40159: }}}}return 16;
40160: }
40161: unsigned long REGPARAM2 CPUFUNC(op_10f0_5)(uae_u32 opcode) /* MOVE */
40162: {
40163: uae_u32 srcreg = (opcode & 7);
40164: uae_u32 dstreg = (opcode >> 9) & 7;
40165: OpcodeFamily = 30; CurrentInstrCycles = 18;
40166: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
40167: BusCyclePenalty += 2;
40168: { uae_s8 src = get_byte(srca);
40169: { uaecptr dsta = m68k_areg(regs, dstreg);
40170: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40171: CLEAR_CZNV;
40172: SET_ZFLG (((uae_s8)(src)) == 0);
40173: SET_NFLG (((uae_s8)(src)) < 0);
40174: m68k_incpc(4);
40175: fill_prefetch_0 ();
40176: put_byte(dsta,src);
40177: }}}}return 18;
40178: }
40179: unsigned long REGPARAM2 CPUFUNC(op_10f8_5)(uae_u32 opcode) /* MOVE */
40180: {
40181: uae_u32 dstreg = (opcode >> 9) & 7;
40182: OpcodeFamily = 30; CurrentInstrCycles = 16;
40183: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
40184: { uae_s8 src = get_byte(srca);
40185: { uaecptr dsta = m68k_areg(regs, dstreg);
40186: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40187: CLEAR_CZNV;
40188: SET_ZFLG (((uae_s8)(src)) == 0);
40189: SET_NFLG (((uae_s8)(src)) < 0);
40190: m68k_incpc(4);
40191: fill_prefetch_0 ();
40192: put_byte(dsta,src);
40193: }}}}return 16;
40194: }
40195: unsigned long REGPARAM2 CPUFUNC(op_10f9_5)(uae_u32 opcode) /* MOVE */
40196: {
40197: uae_u32 dstreg = (opcode >> 9) & 7;
40198: OpcodeFamily = 30; CurrentInstrCycles = 20;
40199: {{ uaecptr srca = get_ilong_prefetch(2);
40200: { uae_s8 src = get_byte(srca);
40201: { uaecptr dsta = m68k_areg(regs, dstreg);
40202: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40203: CLEAR_CZNV;
40204: SET_ZFLG (((uae_s8)(src)) == 0);
40205: SET_NFLG (((uae_s8)(src)) < 0);
40206: m68k_incpc(6);
40207: fill_prefetch_0 ();
40208: put_byte(dsta,src);
40209: }}}}return 20;
40210: }
40211: unsigned long REGPARAM2 CPUFUNC(op_10fa_5)(uae_u32 opcode) /* MOVE */
40212: {
40213: uae_u32 dstreg = (opcode >> 9) & 7;
40214: OpcodeFamily = 30; CurrentInstrCycles = 16;
40215: {{ uaecptr srca = m68k_getpc () + 2;
40216: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
40217: { uae_s8 src = get_byte(srca);
40218: { uaecptr dsta = m68k_areg(regs, dstreg);
40219: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40220: CLEAR_CZNV;
40221: SET_ZFLG (((uae_s8)(src)) == 0);
40222: SET_NFLG (((uae_s8)(src)) < 0);
40223: m68k_incpc(4);
40224: fill_prefetch_0 ();
40225: put_byte(dsta,src);
40226: }}}}return 16;
40227: }
40228: unsigned long REGPARAM2 CPUFUNC(op_10fb_5)(uae_u32 opcode) /* MOVE */
40229: {
40230: uae_u32 dstreg = (opcode >> 9) & 7;
40231: OpcodeFamily = 30; CurrentInstrCycles = 18;
40232: {{ uaecptr tmppc = m68k_getpc() + 2;
40233: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
40234: BusCyclePenalty += 2;
40235: { uae_s8 src = get_byte(srca);
40236: { uaecptr dsta = m68k_areg(regs, dstreg);
40237: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40238: CLEAR_CZNV;
40239: SET_ZFLG (((uae_s8)(src)) == 0);
40240: SET_NFLG (((uae_s8)(src)) < 0);
40241: m68k_incpc(4);
40242: fill_prefetch_0 ();
40243: put_byte(dsta,src);
40244: }}}}return 18;
40245: }
40246: unsigned long REGPARAM2 CPUFUNC(op_10fc_5)(uae_u32 opcode) /* MOVE */
40247: {
40248: uae_u32 dstreg = (opcode >> 9) & 7;
40249: OpcodeFamily = 30; CurrentInstrCycles = 12;
40250: {{ uae_s8 src = get_ibyte_prefetch(2);
40251: { uaecptr dsta = m68k_areg(regs, dstreg);
40252: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
40253: CLEAR_CZNV;
40254: SET_ZFLG (((uae_s8)(src)) == 0);
40255: SET_NFLG (((uae_s8)(src)) < 0);
40256: m68k_incpc(4);
40257: fill_prefetch_0 ();
40258: put_byte(dsta,src);
40259: }}}return 12;
40260: }
40261: unsigned long REGPARAM2 CPUFUNC(op_1100_5)(uae_u32 opcode) /* MOVE */
40262: {
40263: uae_u32 srcreg = (opcode & 7);
40264: uae_u32 dstreg = (opcode >> 9) & 7;
40265: OpcodeFamily = 30; CurrentInstrCycles = 8;
40266: {{ uae_s8 src = m68k_dreg(regs, srcreg);
40267: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40268: m68k_areg (regs, dstreg) = dsta;
40269: CLEAR_CZNV;
40270: SET_ZFLG (((uae_s8)(src)) == 0);
40271: SET_NFLG (((uae_s8)(src)) < 0);
40272: m68k_incpc(2);
40273: fill_prefetch_2 ();
40274: put_byte(dsta,src);
40275: }}}return 8;
40276: }
40277: unsigned long REGPARAM2 CPUFUNC(op_1108_5)(uae_u32 opcode) /* MOVE */
40278: {
40279: uae_u32 srcreg = (opcode & 7);
40280: uae_u32 dstreg = (opcode >> 9) & 7;
40281: OpcodeFamily = 30; CurrentInstrCycles = 8;
40282: {{ uae_s8 src = m68k_areg(regs, srcreg);
40283: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40284: m68k_areg (regs, dstreg) = dsta;
40285: CLEAR_CZNV;
40286: SET_ZFLG (((uae_s8)(src)) == 0);
40287: SET_NFLG (((uae_s8)(src)) < 0);
40288: m68k_incpc(2);
40289: fill_prefetch_2 ();
40290: put_byte(dsta,src);
40291: }}}return 8;
40292: }
40293: unsigned long REGPARAM2 CPUFUNC(op_1110_5)(uae_u32 opcode) /* MOVE */
40294: {
40295: uae_u32 srcreg = (opcode & 7);
40296: uae_u32 dstreg = (opcode >> 9) & 7;
40297: OpcodeFamily = 30; CurrentInstrCycles = 12;
40298: {{ uaecptr srca = m68k_areg(regs, srcreg);
40299: { uae_s8 src = get_byte(srca);
40300: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40301: m68k_areg (regs, dstreg) = dsta;
40302: CLEAR_CZNV;
40303: SET_ZFLG (((uae_s8)(src)) == 0);
40304: SET_NFLG (((uae_s8)(src)) < 0);
40305: m68k_incpc(2);
40306: fill_prefetch_2 ();
40307: put_byte(dsta,src);
40308: }}}}return 12;
40309: }
40310: unsigned long REGPARAM2 CPUFUNC(op_1118_5)(uae_u32 opcode) /* MOVE */
40311: {
40312: uae_u32 srcreg = (opcode & 7);
40313: uae_u32 dstreg = (opcode >> 9) & 7;
40314: OpcodeFamily = 30; CurrentInstrCycles = 12;
40315: {{ uaecptr srca = m68k_areg(regs, srcreg);
40316: { uae_s8 src = get_byte(srca);
40317: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
40318: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40319: m68k_areg (regs, dstreg) = dsta;
40320: CLEAR_CZNV;
40321: SET_ZFLG (((uae_s8)(src)) == 0);
40322: SET_NFLG (((uae_s8)(src)) < 0);
40323: m68k_incpc(2);
40324: fill_prefetch_2 ();
40325: put_byte(dsta,src);
40326: }}}}return 12;
40327: }
40328: unsigned long REGPARAM2 CPUFUNC(op_1120_5)(uae_u32 opcode) /* MOVE */
40329: {
40330: uae_u32 srcreg = (opcode & 7);
40331: uae_u32 dstreg = (opcode >> 9) & 7;
40332: OpcodeFamily = 30; CurrentInstrCycles = 14;
40333: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
40334: { uae_s8 src = get_byte(srca);
40335: m68k_areg (regs, srcreg) = srca;
40336: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40337: m68k_areg (regs, dstreg) = dsta;
40338: CLEAR_CZNV;
40339: SET_ZFLG (((uae_s8)(src)) == 0);
40340: SET_NFLG (((uae_s8)(src)) < 0);
40341: m68k_incpc(2);
40342: fill_prefetch_2 ();
40343: put_byte(dsta,src);
40344: }}}}return 14;
40345: }
40346: unsigned long REGPARAM2 CPUFUNC(op_1128_5)(uae_u32 opcode) /* MOVE */
40347: {
40348: uae_u32 srcreg = (opcode & 7);
40349: uae_u32 dstreg = (opcode >> 9) & 7;
40350: OpcodeFamily = 30; CurrentInstrCycles = 16;
40351: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40352: { uae_s8 src = get_byte(srca);
40353: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40354: m68k_areg (regs, dstreg) = dsta;
40355: CLEAR_CZNV;
40356: SET_ZFLG (((uae_s8)(src)) == 0);
40357: SET_NFLG (((uae_s8)(src)) < 0);
40358: m68k_incpc(4);
40359: fill_prefetch_0 ();
40360: put_byte(dsta,src);
40361: }}}}return 16;
40362: }
40363: unsigned long REGPARAM2 CPUFUNC(op_1130_5)(uae_u32 opcode) /* MOVE */
40364: {
40365: uae_u32 srcreg = (opcode & 7);
40366: uae_u32 dstreg = (opcode >> 9) & 7;
40367: OpcodeFamily = 30; CurrentInstrCycles = 18;
40368: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
40369: BusCyclePenalty += 2;
40370: { uae_s8 src = get_byte(srca);
40371: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40372: m68k_areg (regs, dstreg) = dsta;
40373: CLEAR_CZNV;
40374: SET_ZFLG (((uae_s8)(src)) == 0);
40375: SET_NFLG (((uae_s8)(src)) < 0);
40376: m68k_incpc(4);
40377: fill_prefetch_0 ();
40378: put_byte(dsta,src);
40379: }}}}return 18;
40380: }
40381: unsigned long REGPARAM2 CPUFUNC(op_1138_5)(uae_u32 opcode) /* MOVE */
40382: {
40383: uae_u32 dstreg = (opcode >> 9) & 7;
40384: OpcodeFamily = 30; CurrentInstrCycles = 16;
40385: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
40386: { uae_s8 src = get_byte(srca);
40387: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40388: m68k_areg (regs, dstreg) = dsta;
40389: CLEAR_CZNV;
40390: SET_ZFLG (((uae_s8)(src)) == 0);
40391: SET_NFLG (((uae_s8)(src)) < 0);
40392: m68k_incpc(4);
40393: fill_prefetch_0 ();
40394: put_byte(dsta,src);
40395: }}}}return 16;
40396: }
40397: unsigned long REGPARAM2 CPUFUNC(op_1139_5)(uae_u32 opcode) /* MOVE */
40398: {
40399: uae_u32 dstreg = (opcode >> 9) & 7;
40400: OpcodeFamily = 30; CurrentInstrCycles = 20;
40401: {{ uaecptr srca = get_ilong_prefetch(2);
40402: { uae_s8 src = get_byte(srca);
40403: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40404: m68k_areg (regs, dstreg) = dsta;
40405: CLEAR_CZNV;
40406: SET_ZFLG (((uae_s8)(src)) == 0);
40407: SET_NFLG (((uae_s8)(src)) < 0);
40408: m68k_incpc(6);
40409: fill_prefetch_0 ();
40410: put_byte(dsta,src);
40411: }}}}return 20;
40412: }
40413: unsigned long REGPARAM2 CPUFUNC(op_113a_5)(uae_u32 opcode) /* MOVE */
40414: {
40415: uae_u32 dstreg = (opcode >> 9) & 7;
40416: OpcodeFamily = 30; CurrentInstrCycles = 16;
40417: {{ uaecptr srca = m68k_getpc () + 2;
40418: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
40419: { uae_s8 src = get_byte(srca);
40420: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40421: m68k_areg (regs, dstreg) = dsta;
40422: CLEAR_CZNV;
40423: SET_ZFLG (((uae_s8)(src)) == 0);
40424: SET_NFLG (((uae_s8)(src)) < 0);
40425: m68k_incpc(4);
40426: fill_prefetch_0 ();
40427: put_byte(dsta,src);
40428: }}}}return 16;
40429: }
40430: unsigned long REGPARAM2 CPUFUNC(op_113b_5)(uae_u32 opcode) /* MOVE */
40431: {
40432: uae_u32 dstreg = (opcode >> 9) & 7;
40433: OpcodeFamily = 30; CurrentInstrCycles = 18;
40434: {{ uaecptr tmppc = m68k_getpc() + 2;
40435: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
40436: BusCyclePenalty += 2;
40437: { uae_s8 src = get_byte(srca);
40438: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40439: m68k_areg (regs, dstreg) = dsta;
40440: CLEAR_CZNV;
40441: SET_ZFLG (((uae_s8)(src)) == 0);
40442: SET_NFLG (((uae_s8)(src)) < 0);
40443: m68k_incpc(4);
40444: fill_prefetch_0 ();
40445: put_byte(dsta,src);
40446: }}}}return 18;
40447: }
40448: unsigned long REGPARAM2 CPUFUNC(op_113c_5)(uae_u32 opcode) /* MOVE */
40449: {
40450: uae_u32 dstreg = (opcode >> 9) & 7;
40451: OpcodeFamily = 30; CurrentInstrCycles = 12;
40452: {{ uae_s8 src = get_ibyte_prefetch(2);
40453: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
40454: m68k_areg (regs, dstreg) = dsta;
40455: CLEAR_CZNV;
40456: SET_ZFLG (((uae_s8)(src)) == 0);
40457: SET_NFLG (((uae_s8)(src)) < 0);
40458: m68k_incpc(4);
40459: fill_prefetch_0 ();
40460: put_byte(dsta,src);
40461: }}}return 12;
40462: }
40463: unsigned long REGPARAM2 CPUFUNC(op_1140_5)(uae_u32 opcode) /* MOVE */
40464: {
40465: uae_u32 srcreg = (opcode & 7);
40466: uae_u32 dstreg = (opcode >> 9) & 7;
40467: OpcodeFamily = 30; CurrentInstrCycles = 12;
40468: {{ uae_s8 src = m68k_dreg(regs, srcreg);
40469: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40470: CLEAR_CZNV;
40471: SET_ZFLG (((uae_s8)(src)) == 0);
40472: SET_NFLG (((uae_s8)(src)) < 0);
40473: m68k_incpc(4);
40474: fill_prefetch_0 ();
40475: put_byte(dsta,src);
40476: }}}return 12;
40477: }
40478: unsigned long REGPARAM2 CPUFUNC(op_1148_5)(uae_u32 opcode) /* MOVE */
40479: {
40480: uae_u32 srcreg = (opcode & 7);
40481: uae_u32 dstreg = (opcode >> 9) & 7;
40482: OpcodeFamily = 30; CurrentInstrCycles = 12;
40483: {{ uae_s8 src = m68k_areg(regs, srcreg);
40484: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40485: CLEAR_CZNV;
40486: SET_ZFLG (((uae_s8)(src)) == 0);
40487: SET_NFLG (((uae_s8)(src)) < 0);
40488: m68k_incpc(4);
40489: fill_prefetch_0 ();
40490: put_byte(dsta,src);
40491: }}}return 12;
40492: }
40493: unsigned long REGPARAM2 CPUFUNC(op_1150_5)(uae_u32 opcode) /* MOVE */
40494: {
40495: uae_u32 srcreg = (opcode & 7);
40496: uae_u32 dstreg = (opcode >> 9) & 7;
40497: OpcodeFamily = 30; CurrentInstrCycles = 16;
40498: {{ uaecptr srca = m68k_areg(regs, srcreg);
40499: { uae_s8 src = get_byte(srca);
40500: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40501: CLEAR_CZNV;
40502: SET_ZFLG (((uae_s8)(src)) == 0);
40503: SET_NFLG (((uae_s8)(src)) < 0);
40504: m68k_incpc(4);
40505: fill_prefetch_0 ();
40506: put_byte(dsta,src);
40507: }}}}return 16;
40508: }
40509: unsigned long REGPARAM2 CPUFUNC(op_1158_5)(uae_u32 opcode) /* MOVE */
40510: {
40511: uae_u32 srcreg = (opcode & 7);
40512: uae_u32 dstreg = (opcode >> 9) & 7;
40513: OpcodeFamily = 30; CurrentInstrCycles = 16;
40514: {{ uaecptr srca = m68k_areg(regs, srcreg);
40515: { uae_s8 src = get_byte(srca);
40516: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
40517: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40518: CLEAR_CZNV;
40519: SET_ZFLG (((uae_s8)(src)) == 0);
40520: SET_NFLG (((uae_s8)(src)) < 0);
40521: m68k_incpc(4);
40522: fill_prefetch_0 ();
40523: put_byte(dsta,src);
40524: }}}}return 16;
40525: }
40526: unsigned long REGPARAM2 CPUFUNC(op_1160_5)(uae_u32 opcode) /* MOVE */
40527: {
40528: uae_u32 srcreg = (opcode & 7);
40529: uae_u32 dstreg = (opcode >> 9) & 7;
40530: OpcodeFamily = 30; CurrentInstrCycles = 18;
40531: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
40532: { uae_s8 src = get_byte(srca);
40533: m68k_areg (regs, srcreg) = srca;
40534: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40535: CLEAR_CZNV;
40536: SET_ZFLG (((uae_s8)(src)) == 0);
40537: SET_NFLG (((uae_s8)(src)) < 0);
40538: m68k_incpc(4);
40539: fill_prefetch_0 ();
40540: put_byte(dsta,src);
40541: }}}}return 18;
40542: }
40543: unsigned long REGPARAM2 CPUFUNC(op_1168_5)(uae_u32 opcode) /* MOVE */
40544: {
40545: uae_u32 srcreg = (opcode & 7);
40546: uae_u32 dstreg = (opcode >> 9) & 7;
40547: OpcodeFamily = 30; CurrentInstrCycles = 20;
40548: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40549: { uae_s8 src = get_byte(srca);
40550: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
40551: CLEAR_CZNV;
40552: SET_ZFLG (((uae_s8)(src)) == 0);
40553: SET_NFLG (((uae_s8)(src)) < 0);
40554: m68k_incpc(6);
40555: fill_prefetch_0 ();
40556: put_byte(dsta,src);
40557: }}}}return 20;
40558: }
40559: unsigned long REGPARAM2 CPUFUNC(op_1170_5)(uae_u32 opcode) /* MOVE */
40560: {
40561: uae_u32 srcreg = (opcode & 7);
40562: uae_u32 dstreg = (opcode >> 9) & 7;
40563: OpcodeFamily = 30; CurrentInstrCycles = 22;
40564: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
40565: BusCyclePenalty += 2;
40566: { uae_s8 src = get_byte(srca);
40567: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
40568: CLEAR_CZNV;
40569: SET_ZFLG (((uae_s8)(src)) == 0);
40570: SET_NFLG (((uae_s8)(src)) < 0);
40571: m68k_incpc(6);
40572: fill_prefetch_0 ();
40573: put_byte(dsta,src);
40574: }}}}return 22;
40575: }
40576: unsigned long REGPARAM2 CPUFUNC(op_1178_5)(uae_u32 opcode) /* MOVE */
40577: {
40578: uae_u32 dstreg = (opcode >> 9) & 7;
40579: OpcodeFamily = 30; CurrentInstrCycles = 20;
40580: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
40581: { uae_s8 src = get_byte(srca);
40582: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
40583: CLEAR_CZNV;
40584: SET_ZFLG (((uae_s8)(src)) == 0);
40585: SET_NFLG (((uae_s8)(src)) < 0);
40586: m68k_incpc(6);
40587: fill_prefetch_0 ();
40588: put_byte(dsta,src);
40589: }}}}return 20;
40590: }
40591: unsigned long REGPARAM2 CPUFUNC(op_1179_5)(uae_u32 opcode) /* MOVE */
40592: {
40593: uae_u32 dstreg = (opcode >> 9) & 7;
40594: OpcodeFamily = 30; CurrentInstrCycles = 24;
40595: {{ uaecptr srca = get_ilong_prefetch(2);
40596: { uae_s8 src = get_byte(srca);
40597: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
40598: CLEAR_CZNV;
40599: SET_ZFLG (((uae_s8)(src)) == 0);
40600: SET_NFLG (((uae_s8)(src)) < 0);
40601: m68k_incpc(8);
40602: fill_prefetch_0 ();
40603: put_byte(dsta,src);
40604: }}}}return 24;
40605: }
40606: unsigned long REGPARAM2 CPUFUNC(op_117a_5)(uae_u32 opcode) /* MOVE */
40607: {
40608: uae_u32 dstreg = (opcode >> 9) & 7;
40609: OpcodeFamily = 30; CurrentInstrCycles = 20;
40610: {{ uaecptr srca = m68k_getpc () + 2;
40611: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
40612: { uae_s8 src = get_byte(srca);
40613: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
40614: CLEAR_CZNV;
40615: SET_ZFLG (((uae_s8)(src)) == 0);
40616: SET_NFLG (((uae_s8)(src)) < 0);
40617: m68k_incpc(6);
40618: fill_prefetch_0 ();
40619: put_byte(dsta,src);
40620: }}}}return 20;
40621: }
40622: unsigned long REGPARAM2 CPUFUNC(op_117b_5)(uae_u32 opcode) /* MOVE */
40623: {
40624: uae_u32 dstreg = (opcode >> 9) & 7;
40625: OpcodeFamily = 30; CurrentInstrCycles = 22;
40626: {{ uaecptr tmppc = m68k_getpc() + 2;
40627: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
40628: BusCyclePenalty += 2;
40629: { uae_s8 src = get_byte(srca);
40630: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
40631: CLEAR_CZNV;
40632: SET_ZFLG (((uae_s8)(src)) == 0);
40633: SET_NFLG (((uae_s8)(src)) < 0);
40634: m68k_incpc(6);
40635: fill_prefetch_0 ();
40636: put_byte(dsta,src);
40637: }}}}return 22;
40638: }
40639: unsigned long REGPARAM2 CPUFUNC(op_117c_5)(uae_u32 opcode) /* MOVE */
40640: {
40641: uae_u32 dstreg = (opcode >> 9) & 7;
40642: OpcodeFamily = 30; CurrentInstrCycles = 16;
40643: {{ uae_s8 src = get_ibyte_prefetch(2);
40644: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
40645: CLEAR_CZNV;
40646: SET_ZFLG (((uae_s8)(src)) == 0);
40647: SET_NFLG (((uae_s8)(src)) < 0);
40648: m68k_incpc(6);
40649: fill_prefetch_0 ();
40650: put_byte(dsta,src);
40651: }}}return 16;
40652: }
40653: unsigned long REGPARAM2 CPUFUNC(op_1180_5)(uae_u32 opcode) /* MOVE */
40654: {
40655: uae_u32 srcreg = (opcode & 7);
40656: uae_u32 dstreg = (opcode >> 9) & 7;
40657: OpcodeFamily = 30; CurrentInstrCycles = 14;
40658: {{ uae_s8 src = m68k_dreg(regs, srcreg);
40659: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
40660: BusCyclePenalty += 2;
40661: CLEAR_CZNV;
40662: SET_ZFLG (((uae_s8)(src)) == 0);
40663: SET_NFLG (((uae_s8)(src)) < 0);
40664: m68k_incpc(4);
40665: fill_prefetch_0 ();
40666: put_byte(dsta,src);
40667: }}}return 14;
40668: }
40669: unsigned long REGPARAM2 CPUFUNC(op_1188_5)(uae_u32 opcode) /* MOVE */
40670: {
40671: uae_u32 srcreg = (opcode & 7);
40672: uae_u32 dstreg = (opcode >> 9) & 7;
40673: OpcodeFamily = 30; CurrentInstrCycles = 14;
40674: {{ uae_s8 src = m68k_areg(regs, srcreg);
40675: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
40676: BusCyclePenalty += 2;
40677: CLEAR_CZNV;
40678: SET_ZFLG (((uae_s8)(src)) == 0);
40679: SET_NFLG (((uae_s8)(src)) < 0);
40680: m68k_incpc(4);
40681: fill_prefetch_0 ();
40682: put_byte(dsta,src);
40683: }}}return 14;
40684: }
40685: unsigned long REGPARAM2 CPUFUNC(op_1190_5)(uae_u32 opcode) /* MOVE */
40686: {
40687: uae_u32 srcreg = (opcode & 7);
40688: uae_u32 dstreg = (opcode >> 9) & 7;
40689: OpcodeFamily = 30; CurrentInstrCycles = 18;
40690: {{ uaecptr srca = m68k_areg(regs, srcreg);
40691: { uae_s8 src = get_byte(srca);
40692: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
40693: BusCyclePenalty += 2;
40694: CLEAR_CZNV;
40695: SET_ZFLG (((uae_s8)(src)) == 0);
40696: SET_NFLG (((uae_s8)(src)) < 0);
40697: m68k_incpc(4);
40698: fill_prefetch_0 ();
40699: put_byte(dsta,src);
40700: }}}}return 18;
40701: }
40702: unsigned long REGPARAM2 CPUFUNC(op_1198_5)(uae_u32 opcode) /* MOVE */
40703: {
40704: uae_u32 srcreg = (opcode & 7);
40705: uae_u32 dstreg = (opcode >> 9) & 7;
40706: OpcodeFamily = 30; CurrentInstrCycles = 18;
40707: {{ uaecptr srca = m68k_areg(regs, srcreg);
40708: { uae_s8 src = get_byte(srca);
40709: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
40710: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
40711: BusCyclePenalty += 2;
40712: CLEAR_CZNV;
40713: SET_ZFLG (((uae_s8)(src)) == 0);
40714: SET_NFLG (((uae_s8)(src)) < 0);
40715: m68k_incpc(4);
40716: fill_prefetch_0 ();
40717: put_byte(dsta,src);
40718: }}}}return 18;
40719: }
40720: unsigned long REGPARAM2 CPUFUNC(op_11a0_5)(uae_u32 opcode) /* MOVE */
40721: {
40722: uae_u32 srcreg = (opcode & 7);
40723: uae_u32 dstreg = (opcode >> 9) & 7;
40724: OpcodeFamily = 30; CurrentInstrCycles = 20;
40725: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
40726: { uae_s8 src = get_byte(srca);
40727: m68k_areg (regs, srcreg) = srca;
40728: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
40729: BusCyclePenalty += 2;
40730: CLEAR_CZNV;
40731: SET_ZFLG (((uae_s8)(src)) == 0);
40732: SET_NFLG (((uae_s8)(src)) < 0);
40733: m68k_incpc(4);
40734: fill_prefetch_0 ();
40735: put_byte(dsta,src);
40736: }}}}return 20;
40737: }
40738: unsigned long REGPARAM2 CPUFUNC(op_11a8_5)(uae_u32 opcode) /* MOVE */
40739: {
40740: uae_u32 srcreg = (opcode & 7);
40741: uae_u32 dstreg = (opcode >> 9) & 7;
40742: OpcodeFamily = 30; CurrentInstrCycles = 22;
40743: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40744: { uae_s8 src = get_byte(srca);
40745: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
40746: BusCyclePenalty += 2;
40747: CLEAR_CZNV;
40748: SET_ZFLG (((uae_s8)(src)) == 0);
40749: SET_NFLG (((uae_s8)(src)) < 0);
40750: m68k_incpc(6);
40751: fill_prefetch_0 ();
40752: put_byte(dsta,src);
40753: }}}}return 22;
40754: }
40755: unsigned long REGPARAM2 CPUFUNC(op_11b0_5)(uae_u32 opcode) /* MOVE */
40756: {
40757: uae_u32 srcreg = (opcode & 7);
40758: uae_u32 dstreg = (opcode >> 9) & 7;
40759: OpcodeFamily = 30; CurrentInstrCycles = 24;
40760: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
40761: BusCyclePenalty += 2;
40762: { uae_s8 src = get_byte(srca);
40763: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
40764: BusCyclePenalty += 2;
40765: CLEAR_CZNV;
40766: SET_ZFLG (((uae_s8)(src)) == 0);
40767: SET_NFLG (((uae_s8)(src)) < 0);
40768: m68k_incpc(6);
40769: fill_prefetch_0 ();
40770: put_byte(dsta,src);
40771: }}}}return 24;
40772: }
40773: unsigned long REGPARAM2 CPUFUNC(op_11b8_5)(uae_u32 opcode) /* MOVE */
40774: {
40775: uae_u32 dstreg = (opcode >> 9) & 7;
40776: OpcodeFamily = 30; CurrentInstrCycles = 22;
40777: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
40778: { uae_s8 src = get_byte(srca);
40779: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
40780: BusCyclePenalty += 2;
40781: CLEAR_CZNV;
40782: SET_ZFLG (((uae_s8)(src)) == 0);
40783: SET_NFLG (((uae_s8)(src)) < 0);
40784: m68k_incpc(6);
40785: fill_prefetch_0 ();
40786: put_byte(dsta,src);
40787: }}}}return 22;
40788: }
40789: unsigned long REGPARAM2 CPUFUNC(op_11b9_5)(uae_u32 opcode) /* MOVE */
40790: {
40791: uae_u32 dstreg = (opcode >> 9) & 7;
40792: OpcodeFamily = 30; CurrentInstrCycles = 26;
40793: {{ uaecptr srca = get_ilong_prefetch(2);
40794: { uae_s8 src = get_byte(srca);
40795: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
40796: BusCyclePenalty += 2;
40797: CLEAR_CZNV;
40798: SET_ZFLG (((uae_s8)(src)) == 0);
40799: SET_NFLG (((uae_s8)(src)) < 0);
40800: m68k_incpc(8);
40801: fill_prefetch_0 ();
40802: put_byte(dsta,src);
40803: }}}}return 26;
40804: }
40805: unsigned long REGPARAM2 CPUFUNC(op_11ba_5)(uae_u32 opcode) /* MOVE */
40806: {
40807: uae_u32 dstreg = (opcode >> 9) & 7;
40808: OpcodeFamily = 30; CurrentInstrCycles = 22;
40809: {{ uaecptr srca = m68k_getpc () + 2;
40810: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
40811: { uae_s8 src = get_byte(srca);
40812: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
40813: BusCyclePenalty += 2;
40814: CLEAR_CZNV;
40815: SET_ZFLG (((uae_s8)(src)) == 0);
40816: SET_NFLG (((uae_s8)(src)) < 0);
40817: m68k_incpc(6);
40818: fill_prefetch_0 ();
40819: put_byte(dsta,src);
40820: }}}}return 22;
40821: }
40822: unsigned long REGPARAM2 CPUFUNC(op_11bb_5)(uae_u32 opcode) /* MOVE */
40823: {
40824: uae_u32 dstreg = (opcode >> 9) & 7;
40825: OpcodeFamily = 30; CurrentInstrCycles = 24;
40826: {{ uaecptr tmppc = m68k_getpc() + 2;
40827: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
40828: BusCyclePenalty += 2;
40829: { uae_s8 src = get_byte(srca);
40830: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
40831: BusCyclePenalty += 2;
40832: CLEAR_CZNV;
40833: SET_ZFLG (((uae_s8)(src)) == 0);
40834: SET_NFLG (((uae_s8)(src)) < 0);
40835: m68k_incpc(6);
40836: fill_prefetch_0 ();
40837: put_byte(dsta,src);
40838: }}}}return 24;
40839: }
40840: unsigned long REGPARAM2 CPUFUNC(op_11bc_5)(uae_u32 opcode) /* MOVE */
40841: {
40842: uae_u32 dstreg = (opcode >> 9) & 7;
40843: OpcodeFamily = 30; CurrentInstrCycles = 18;
40844: {{ uae_s8 src = get_ibyte_prefetch(2);
40845: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
40846: BusCyclePenalty += 2;
40847: CLEAR_CZNV;
40848: SET_ZFLG (((uae_s8)(src)) == 0);
40849: SET_NFLG (((uae_s8)(src)) < 0);
40850: m68k_incpc(6);
40851: fill_prefetch_0 ();
40852: put_byte(dsta,src);
40853: }}}return 18;
40854: }
40855: unsigned long REGPARAM2 CPUFUNC(op_11c0_5)(uae_u32 opcode) /* MOVE */
40856: {
40857: uae_u32 srcreg = (opcode & 7);
40858: OpcodeFamily = 30; CurrentInstrCycles = 12;
40859: {{ uae_s8 src = m68k_dreg(regs, srcreg);
40860: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
40861: CLEAR_CZNV;
40862: SET_ZFLG (((uae_s8)(src)) == 0);
40863: SET_NFLG (((uae_s8)(src)) < 0);
40864: m68k_incpc(4);
40865: fill_prefetch_0 ();
40866: put_byte(dsta,src);
40867: }}}return 12;
40868: }
40869: unsigned long REGPARAM2 CPUFUNC(op_11c8_5)(uae_u32 opcode) /* MOVE */
40870: {
40871: uae_u32 srcreg = (opcode & 7);
40872: OpcodeFamily = 30; CurrentInstrCycles = 12;
40873: {{ uae_s8 src = m68k_areg(regs, srcreg);
40874: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
40875: CLEAR_CZNV;
40876: SET_ZFLG (((uae_s8)(src)) == 0);
40877: SET_NFLG (((uae_s8)(src)) < 0);
40878: m68k_incpc(4);
40879: fill_prefetch_0 ();
40880: put_byte(dsta,src);
40881: }}}return 12;
40882: }
40883: unsigned long REGPARAM2 CPUFUNC(op_11d0_5)(uae_u32 opcode) /* MOVE */
40884: {
40885: uae_u32 srcreg = (opcode & 7);
40886: OpcodeFamily = 30; CurrentInstrCycles = 16;
40887: {{ uaecptr srca = m68k_areg(regs, srcreg);
40888: { uae_s8 src = get_byte(srca);
40889: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
40890: CLEAR_CZNV;
40891: SET_ZFLG (((uae_s8)(src)) == 0);
40892: SET_NFLG (((uae_s8)(src)) < 0);
40893: m68k_incpc(4);
40894: fill_prefetch_0 ();
40895: put_byte(dsta,src);
40896: }}}}return 16;
40897: }
40898: unsigned long REGPARAM2 CPUFUNC(op_11d8_5)(uae_u32 opcode) /* MOVE */
40899: {
40900: uae_u32 srcreg = (opcode & 7);
40901: OpcodeFamily = 30; CurrentInstrCycles = 16;
40902: {{ uaecptr srca = m68k_areg(regs, srcreg);
40903: { uae_s8 src = get_byte(srca);
40904: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
40905: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
40906: CLEAR_CZNV;
40907: SET_ZFLG (((uae_s8)(src)) == 0);
40908: SET_NFLG (((uae_s8)(src)) < 0);
40909: m68k_incpc(4);
40910: fill_prefetch_0 ();
40911: put_byte(dsta,src);
40912: }}}}return 16;
40913: }
40914: unsigned long REGPARAM2 CPUFUNC(op_11e0_5)(uae_u32 opcode) /* MOVE */
40915: {
40916: uae_u32 srcreg = (opcode & 7);
40917: OpcodeFamily = 30; CurrentInstrCycles = 18;
40918: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
40919: { uae_s8 src = get_byte(srca);
40920: m68k_areg (regs, srcreg) = srca;
40921: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
40922: CLEAR_CZNV;
40923: SET_ZFLG (((uae_s8)(src)) == 0);
40924: SET_NFLG (((uae_s8)(src)) < 0);
40925: m68k_incpc(4);
40926: fill_prefetch_0 ();
40927: put_byte(dsta,src);
40928: }}}}return 18;
40929: }
40930: unsigned long REGPARAM2 CPUFUNC(op_11e8_5)(uae_u32 opcode) /* MOVE */
40931: {
40932: uae_u32 srcreg = (opcode & 7);
40933: OpcodeFamily = 30; CurrentInstrCycles = 20;
40934: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
40935: { uae_s8 src = get_byte(srca);
40936: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
40937: CLEAR_CZNV;
40938: SET_ZFLG (((uae_s8)(src)) == 0);
40939: SET_NFLG (((uae_s8)(src)) < 0);
40940: m68k_incpc(6);
40941: fill_prefetch_0 ();
40942: put_byte(dsta,src);
40943: }}}}return 20;
40944: }
40945: unsigned long REGPARAM2 CPUFUNC(op_11f0_5)(uae_u32 opcode) /* MOVE */
40946: {
40947: uae_u32 srcreg = (opcode & 7);
40948: OpcodeFamily = 30; CurrentInstrCycles = 22;
40949: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
40950: BusCyclePenalty += 2;
40951: { uae_s8 src = get_byte(srca);
40952: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
40953: CLEAR_CZNV;
40954: SET_ZFLG (((uae_s8)(src)) == 0);
40955: SET_NFLG (((uae_s8)(src)) < 0);
40956: m68k_incpc(6);
40957: fill_prefetch_0 ();
40958: put_byte(dsta,src);
40959: }}}}return 22;
40960: }
40961: unsigned long REGPARAM2 CPUFUNC(op_11f8_5)(uae_u32 opcode) /* MOVE */
40962: {
40963: OpcodeFamily = 30; CurrentInstrCycles = 20;
40964: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
40965: { uae_s8 src = get_byte(srca);
40966: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
40967: CLEAR_CZNV;
40968: SET_ZFLG (((uae_s8)(src)) == 0);
40969: SET_NFLG (((uae_s8)(src)) < 0);
40970: m68k_incpc(6);
40971: fill_prefetch_0 ();
40972: put_byte(dsta,src);
40973: }}}}return 20;
40974: }
40975: unsigned long REGPARAM2 CPUFUNC(op_11f9_5)(uae_u32 opcode) /* MOVE */
40976: {
40977: OpcodeFamily = 30; CurrentInstrCycles = 24;
40978: {{ uaecptr srca = get_ilong_prefetch(2);
40979: { uae_s8 src = get_byte(srca);
40980: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
40981: CLEAR_CZNV;
40982: SET_ZFLG (((uae_s8)(src)) == 0);
40983: SET_NFLG (((uae_s8)(src)) < 0);
40984: m68k_incpc(8);
40985: fill_prefetch_0 ();
40986: put_byte(dsta,src);
40987: }}}}return 24;
40988: }
40989: unsigned long REGPARAM2 CPUFUNC(op_11fa_5)(uae_u32 opcode) /* MOVE */
40990: {
40991: OpcodeFamily = 30; CurrentInstrCycles = 20;
40992: {{ uaecptr srca = m68k_getpc () + 2;
40993: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
40994: { uae_s8 src = get_byte(srca);
40995: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
40996: CLEAR_CZNV;
40997: SET_ZFLG (((uae_s8)(src)) == 0);
40998: SET_NFLG (((uae_s8)(src)) < 0);
40999: m68k_incpc(6);
41000: fill_prefetch_0 ();
41001: put_byte(dsta,src);
41002: }}}}return 20;
41003: }
41004: unsigned long REGPARAM2 CPUFUNC(op_11fb_5)(uae_u32 opcode) /* MOVE */
41005: {
41006: OpcodeFamily = 30; CurrentInstrCycles = 22;
41007: {{ uaecptr tmppc = m68k_getpc() + 2;
41008: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
41009: BusCyclePenalty += 2;
41010: { uae_s8 src = get_byte(srca);
41011: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
41012: CLEAR_CZNV;
41013: SET_ZFLG (((uae_s8)(src)) == 0);
41014: SET_NFLG (((uae_s8)(src)) < 0);
41015: m68k_incpc(6);
41016: fill_prefetch_0 ();
41017: put_byte(dsta,src);
41018: }}}}return 22;
41019: }
41020: unsigned long REGPARAM2 CPUFUNC(op_11fc_5)(uae_u32 opcode) /* MOVE */
41021: {
41022: OpcodeFamily = 30; CurrentInstrCycles = 16;
41023: {{ uae_s8 src = get_ibyte_prefetch(2);
41024: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
41025: CLEAR_CZNV;
41026: SET_ZFLG (((uae_s8)(src)) == 0);
41027: SET_NFLG (((uae_s8)(src)) < 0);
41028: m68k_incpc(6);
41029: fill_prefetch_0 ();
41030: put_byte(dsta,src);
41031: }}}return 16;
41032: }
41033: unsigned long REGPARAM2 CPUFUNC(op_13c0_5)(uae_u32 opcode) /* MOVE */
41034: {
41035: uae_u32 srcreg = (opcode & 7);
41036: OpcodeFamily = 30; CurrentInstrCycles = 16;
41037: {{ uae_s8 src = m68k_dreg(regs, srcreg);
41038: { uaecptr dsta = get_ilong_prefetch(2);
41039: CLEAR_CZNV;
41040: SET_ZFLG (((uae_s8)(src)) == 0);
41041: SET_NFLG (((uae_s8)(src)) < 0);
41042: m68k_incpc(6);
41043: fill_prefetch_0 ();
41044: put_byte(dsta,src);
41045: }}}return 16;
41046: }
41047: unsigned long REGPARAM2 CPUFUNC(op_13c8_5)(uae_u32 opcode) /* MOVE */
41048: {
41049: uae_u32 srcreg = (opcode & 7);
41050: OpcodeFamily = 30; CurrentInstrCycles = 16;
41051: {{ uae_s8 src = m68k_areg(regs, srcreg);
41052: { uaecptr dsta = get_ilong_prefetch(2);
41053: CLEAR_CZNV;
41054: SET_ZFLG (((uae_s8)(src)) == 0);
41055: SET_NFLG (((uae_s8)(src)) < 0);
41056: m68k_incpc(6);
41057: fill_prefetch_0 ();
41058: put_byte(dsta,src);
41059: }}}return 16;
41060: }
41061: unsigned long REGPARAM2 CPUFUNC(op_13d0_5)(uae_u32 opcode) /* MOVE */
41062: {
41063: uae_u32 srcreg = (opcode & 7);
41064: OpcodeFamily = 30; CurrentInstrCycles = 20;
41065: {{ uaecptr srca = m68k_areg(regs, srcreg);
41066: { uae_s8 src = get_byte(srca);
41067: { uaecptr dsta = get_ilong_prefetch(2);
41068: CLEAR_CZNV;
41069: SET_ZFLG (((uae_s8)(src)) == 0);
41070: SET_NFLG (((uae_s8)(src)) < 0);
41071: m68k_incpc(6);
41072: fill_prefetch_0 ();
41073: put_byte(dsta,src);
41074: }}}}return 20;
41075: }
41076: unsigned long REGPARAM2 CPUFUNC(op_13d8_5)(uae_u32 opcode) /* MOVE */
41077: {
41078: uae_u32 srcreg = (opcode & 7);
41079: OpcodeFamily = 30; CurrentInstrCycles = 20;
41080: {{ uaecptr srca = m68k_areg(regs, srcreg);
41081: { uae_s8 src = get_byte(srca);
41082: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
41083: { uaecptr dsta = get_ilong_prefetch(2);
41084: CLEAR_CZNV;
41085: SET_ZFLG (((uae_s8)(src)) == 0);
41086: SET_NFLG (((uae_s8)(src)) < 0);
41087: m68k_incpc(6);
41088: fill_prefetch_0 ();
41089: put_byte(dsta,src);
41090: }}}}return 20;
41091: }
41092: unsigned long REGPARAM2 CPUFUNC(op_13e0_5)(uae_u32 opcode) /* MOVE */
41093: {
41094: uae_u32 srcreg = (opcode & 7);
41095: OpcodeFamily = 30; CurrentInstrCycles = 22;
41096: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
41097: { uae_s8 src = get_byte(srca);
41098: m68k_areg (regs, srcreg) = srca;
41099: { uaecptr dsta = get_ilong_prefetch(2);
41100: CLEAR_CZNV;
41101: SET_ZFLG (((uae_s8)(src)) == 0);
41102: SET_NFLG (((uae_s8)(src)) < 0);
41103: m68k_incpc(6);
41104: fill_prefetch_0 ();
41105: put_byte(dsta,src);
41106: }}}}return 22;
41107: }
41108: unsigned long REGPARAM2 CPUFUNC(op_13e8_5)(uae_u32 opcode) /* MOVE */
41109: {
41110: uae_u32 srcreg = (opcode & 7);
41111: OpcodeFamily = 30; CurrentInstrCycles = 24;
41112: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
41113: { uae_s8 src = get_byte(srca);
41114: { uaecptr dsta = get_ilong_prefetch(4);
41115: CLEAR_CZNV;
41116: SET_ZFLG (((uae_s8)(src)) == 0);
41117: SET_NFLG (((uae_s8)(src)) < 0);
41118: m68k_incpc(8);
41119: fill_prefetch_0 ();
41120: put_byte(dsta,src);
41121: }}}}return 24;
41122: }
41123: unsigned long REGPARAM2 CPUFUNC(op_13f0_5)(uae_u32 opcode) /* MOVE */
41124: {
41125: uae_u32 srcreg = (opcode & 7);
41126: OpcodeFamily = 30; CurrentInstrCycles = 26;
41127: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
41128: BusCyclePenalty += 2;
41129: { uae_s8 src = get_byte(srca);
41130: { uaecptr dsta = get_ilong_prefetch(4);
41131: CLEAR_CZNV;
41132: SET_ZFLG (((uae_s8)(src)) == 0);
41133: SET_NFLG (((uae_s8)(src)) < 0);
41134: m68k_incpc(8);
41135: fill_prefetch_0 ();
41136: put_byte(dsta,src);
41137: }}}}return 26;
41138: }
41139: unsigned long REGPARAM2 CPUFUNC(op_13f8_5)(uae_u32 opcode) /* MOVE */
41140: {
41141: OpcodeFamily = 30; CurrentInstrCycles = 24;
41142: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
41143: { uae_s8 src = get_byte(srca);
41144: { uaecptr dsta = get_ilong_prefetch(4);
41145: CLEAR_CZNV;
41146: SET_ZFLG (((uae_s8)(src)) == 0);
41147: SET_NFLG (((uae_s8)(src)) < 0);
41148: m68k_incpc(8);
41149: fill_prefetch_0 ();
41150: put_byte(dsta,src);
41151: }}}}return 24;
41152: }
41153: unsigned long REGPARAM2 CPUFUNC(op_13f9_5)(uae_u32 opcode) /* MOVE */
41154: {
41155: OpcodeFamily = 30; CurrentInstrCycles = 28;
41156: {{ uaecptr srca = get_ilong_prefetch(2);
41157: { uae_s8 src = get_byte(srca);
41158: { uaecptr dsta = get_ilong_prefetch(6);
41159: CLEAR_CZNV;
41160: SET_ZFLG (((uae_s8)(src)) == 0);
41161: SET_NFLG (((uae_s8)(src)) < 0);
41162: m68k_incpc(10);
41163: fill_prefetch_0 ();
41164: put_byte(dsta,src);
41165: }}}}return 28;
41166: }
41167: unsigned long REGPARAM2 CPUFUNC(op_13fa_5)(uae_u32 opcode) /* MOVE */
41168: {
41169: OpcodeFamily = 30; CurrentInstrCycles = 24;
41170: {{ uaecptr srca = m68k_getpc () + 2;
41171: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
41172: { uae_s8 src = get_byte(srca);
41173: { uaecptr dsta = get_ilong_prefetch(4);
41174: CLEAR_CZNV;
41175: SET_ZFLG (((uae_s8)(src)) == 0);
41176: SET_NFLG (((uae_s8)(src)) < 0);
41177: m68k_incpc(8);
41178: fill_prefetch_0 ();
41179: put_byte(dsta,src);
41180: }}}}return 24;
41181: }
41182: unsigned long REGPARAM2 CPUFUNC(op_13fb_5)(uae_u32 opcode) /* MOVE */
41183: {
41184: OpcodeFamily = 30; CurrentInstrCycles = 26;
41185: {{ uaecptr tmppc = m68k_getpc() + 2;
41186: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
41187: BusCyclePenalty += 2;
41188: { uae_s8 src = get_byte(srca);
41189: { uaecptr dsta = get_ilong_prefetch(4);
41190: CLEAR_CZNV;
41191: SET_ZFLG (((uae_s8)(src)) == 0);
41192: SET_NFLG (((uae_s8)(src)) < 0);
41193: m68k_incpc(8);
41194: fill_prefetch_0 ();
41195: put_byte(dsta,src);
41196: }}}}return 26;
41197: }
41198: unsigned long REGPARAM2 CPUFUNC(op_13fc_5)(uae_u32 opcode) /* MOVE */
41199: {
41200: OpcodeFamily = 30; CurrentInstrCycles = 20;
41201: {{ uae_s8 src = get_ibyte_prefetch(2);
41202: { uaecptr dsta = get_ilong_prefetch(4);
41203: CLEAR_CZNV;
41204: SET_ZFLG (((uae_s8)(src)) == 0);
41205: SET_NFLG (((uae_s8)(src)) < 0);
41206: m68k_incpc(8);
41207: fill_prefetch_0 ();
41208: put_byte(dsta,src);
41209: }}}return 20;
41210: }
41211: unsigned long REGPARAM2 CPUFUNC(op_2000_5)(uae_u32 opcode) /* MOVE */
41212: {
41213: uae_u32 srcreg = (opcode & 7);
41214: uae_u32 dstreg = (opcode >> 9) & 7;
41215: OpcodeFamily = 30; CurrentInstrCycles = 4;
41216: {{ uae_s32 src = m68k_dreg(regs, srcreg);
41217: { CLEAR_CZNV;
41218: SET_ZFLG (((uae_s32)(src)) == 0);
41219: SET_NFLG (((uae_s32)(src)) < 0);
41220: m68k_dreg(regs, dstreg) = (src);
41221: }}}m68k_incpc(2);
41222: fill_prefetch_2 ();
41223: return 4;
41224: }
41225: unsigned long REGPARAM2 CPUFUNC(op_2008_5)(uae_u32 opcode) /* MOVE */
41226: {
41227: uae_u32 srcreg = (opcode & 7);
41228: uae_u32 dstreg = (opcode >> 9) & 7;
41229: OpcodeFamily = 30; CurrentInstrCycles = 4;
41230: {{ uae_s32 src = m68k_areg(regs, srcreg);
41231: { CLEAR_CZNV;
41232: SET_ZFLG (((uae_s32)(src)) == 0);
41233: SET_NFLG (((uae_s32)(src)) < 0);
41234: m68k_dreg(regs, dstreg) = (src);
41235: }}}m68k_incpc(2);
41236: fill_prefetch_2 ();
41237: return 4;
41238: }
41239: unsigned long REGPARAM2 CPUFUNC(op_2010_5)(uae_u32 opcode) /* MOVE */
41240: {
41241: uae_u32 srcreg = (opcode & 7);
41242: uae_u32 dstreg = (opcode >> 9) & 7;
41243: OpcodeFamily = 30; CurrentInstrCycles = 12;
41244: {{ uaecptr srca = m68k_areg(regs, srcreg);
41245: if ((srca & 1) != 0) {
41246: last_fault_for_exception_3 = srca;
41247: last_op_for_exception_3 = opcode;
41248: last_addr_for_exception_3 = m68k_getpc() + 2;
41249: Exception(3, 0, M68000_EXC_SRC_CPU);
41250: goto endlabel2495;
41251: }
41252: {{ uae_s32 src = get_long(srca);
41253: { CLEAR_CZNV;
41254: SET_ZFLG (((uae_s32)(src)) == 0);
41255: SET_NFLG (((uae_s32)(src)) < 0);
41256: m68k_dreg(regs, dstreg) = (src);
41257: }}}}}m68k_incpc(2);
41258: fill_prefetch_2 ();
41259: endlabel2495: ;
41260: return 12;
41261: }
41262: unsigned long REGPARAM2 CPUFUNC(op_2018_5)(uae_u32 opcode) /* MOVE */
41263: {
41264: uae_u32 srcreg = (opcode & 7);
41265: uae_u32 dstreg = (opcode >> 9) & 7;
41266: OpcodeFamily = 30; CurrentInstrCycles = 12;
41267: {{ uaecptr srca = m68k_areg(regs, srcreg);
41268: if ((srca & 1) != 0) {
41269: last_fault_for_exception_3 = srca;
41270: last_op_for_exception_3 = opcode;
41271: last_addr_for_exception_3 = m68k_getpc() + 2;
41272: Exception(3, 0, M68000_EXC_SRC_CPU);
41273: goto endlabel2496;
41274: }
41275: {{ uae_s32 src = get_long(srca);
41276: m68k_areg(regs, srcreg) += 4;
41277: { CLEAR_CZNV;
41278: SET_ZFLG (((uae_s32)(src)) == 0);
41279: SET_NFLG (((uae_s32)(src)) < 0);
41280: m68k_dreg(regs, dstreg) = (src);
41281: }}}}}m68k_incpc(2);
41282: fill_prefetch_2 ();
41283: endlabel2496: ;
41284: return 12;
41285: }
41286: unsigned long REGPARAM2 CPUFUNC(op_2020_5)(uae_u32 opcode) /* MOVE */
41287: {
41288: uae_u32 srcreg = (opcode & 7);
41289: uae_u32 dstreg = (opcode >> 9) & 7;
41290: OpcodeFamily = 30; CurrentInstrCycles = 14;
41291: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
41292: if ((srca & 1) != 0) {
41293: last_fault_for_exception_3 = srca;
41294: last_op_for_exception_3 = opcode;
41295: last_addr_for_exception_3 = m68k_getpc() + 2;
41296: Exception(3, 0, M68000_EXC_SRC_CPU);
41297: goto endlabel2497;
41298: }
41299: {{ uae_s32 src = get_long(srca);
41300: m68k_areg (regs, srcreg) = srca;
41301: { CLEAR_CZNV;
41302: SET_ZFLG (((uae_s32)(src)) == 0);
41303: SET_NFLG (((uae_s32)(src)) < 0);
41304: m68k_dreg(regs, dstreg) = (src);
41305: }}}}}m68k_incpc(2);
41306: fill_prefetch_2 ();
41307: endlabel2497: ;
41308: return 14;
41309: }
41310: unsigned long REGPARAM2 CPUFUNC(op_2028_5)(uae_u32 opcode) /* MOVE */
41311: {
41312: uae_u32 srcreg = (opcode & 7);
41313: uae_u32 dstreg = (opcode >> 9) & 7;
41314: OpcodeFamily = 30; CurrentInstrCycles = 16;
41315: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
41316: if ((srca & 1) != 0) {
41317: last_fault_for_exception_3 = srca;
41318: last_op_for_exception_3 = opcode;
41319: last_addr_for_exception_3 = m68k_getpc() + 4;
41320: Exception(3, 0, M68000_EXC_SRC_CPU);
41321: goto endlabel2498;
41322: }
41323: {{ uae_s32 src = get_long(srca);
41324: { CLEAR_CZNV;
41325: SET_ZFLG (((uae_s32)(src)) == 0);
41326: SET_NFLG (((uae_s32)(src)) < 0);
41327: m68k_dreg(regs, dstreg) = (src);
41328: }}}}}m68k_incpc(4);
41329: fill_prefetch_0 ();
41330: endlabel2498: ;
41331: return 16;
41332: }
41333: unsigned long REGPARAM2 CPUFUNC(op_2030_5)(uae_u32 opcode) /* MOVE */
41334: {
41335: uae_u32 srcreg = (opcode & 7);
41336: uae_u32 dstreg = (opcode >> 9) & 7;
41337: OpcodeFamily = 30; CurrentInstrCycles = 18;
41338: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
41339: BusCyclePenalty += 2;
41340: if ((srca & 1) != 0) {
41341: last_fault_for_exception_3 = srca;
41342: last_op_for_exception_3 = opcode;
41343: last_addr_for_exception_3 = m68k_getpc() + 4;
41344: Exception(3, 0, M68000_EXC_SRC_CPU);
41345: goto endlabel2499;
41346: }
41347: {{ uae_s32 src = get_long(srca);
41348: { CLEAR_CZNV;
41349: SET_ZFLG (((uae_s32)(src)) == 0);
41350: SET_NFLG (((uae_s32)(src)) < 0);
41351: m68k_dreg(regs, dstreg) = (src);
41352: }}}}}m68k_incpc(4);
41353: fill_prefetch_0 ();
41354: endlabel2499: ;
41355: return 18;
41356: }
41357: unsigned long REGPARAM2 CPUFUNC(op_2038_5)(uae_u32 opcode) /* MOVE */
41358: {
41359: uae_u32 dstreg = (opcode >> 9) & 7;
41360: OpcodeFamily = 30; CurrentInstrCycles = 16;
41361: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
41362: if ((srca & 1) != 0) {
41363: last_fault_for_exception_3 = srca;
41364: last_op_for_exception_3 = opcode;
41365: last_addr_for_exception_3 = m68k_getpc() + 4;
41366: Exception(3, 0, M68000_EXC_SRC_CPU);
41367: goto endlabel2500;
41368: }
41369: {{ uae_s32 src = get_long(srca);
41370: { CLEAR_CZNV;
41371: SET_ZFLG (((uae_s32)(src)) == 0);
41372: SET_NFLG (((uae_s32)(src)) < 0);
41373: m68k_dreg(regs, dstreg) = (src);
41374: }}}}}m68k_incpc(4);
41375: fill_prefetch_0 ();
41376: endlabel2500: ;
41377: return 16;
41378: }
41379: unsigned long REGPARAM2 CPUFUNC(op_2039_5)(uae_u32 opcode) /* MOVE */
41380: {
41381: uae_u32 dstreg = (opcode >> 9) & 7;
41382: OpcodeFamily = 30; CurrentInstrCycles = 20;
41383: {{ uaecptr srca = get_ilong_prefetch(2);
41384: if ((srca & 1) != 0) {
41385: last_fault_for_exception_3 = srca;
41386: last_op_for_exception_3 = opcode;
41387: last_addr_for_exception_3 = m68k_getpc() + 6;
41388: Exception(3, 0, M68000_EXC_SRC_CPU);
41389: goto endlabel2501;
41390: }
41391: {{ uae_s32 src = get_long(srca);
41392: { CLEAR_CZNV;
41393: SET_ZFLG (((uae_s32)(src)) == 0);
41394: SET_NFLG (((uae_s32)(src)) < 0);
41395: m68k_dreg(regs, dstreg) = (src);
41396: }}}}}m68k_incpc(6);
41397: fill_prefetch_0 ();
41398: endlabel2501: ;
41399: return 20;
41400: }
41401: unsigned long REGPARAM2 CPUFUNC(op_203a_5)(uae_u32 opcode) /* MOVE */
41402: {
41403: uae_u32 dstreg = (opcode >> 9) & 7;
41404: OpcodeFamily = 30; CurrentInstrCycles = 16;
41405: {{ uaecptr srca = m68k_getpc () + 2;
41406: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
41407: if ((srca & 1) != 0) {
41408: last_fault_for_exception_3 = srca;
41409: last_op_for_exception_3 = opcode;
41410: last_addr_for_exception_3 = m68k_getpc() + 4;
41411: Exception(3, 0, M68000_EXC_SRC_CPU);
41412: goto endlabel2502;
41413: }
41414: {{ uae_s32 src = get_long(srca);
41415: { CLEAR_CZNV;
41416: SET_ZFLG (((uae_s32)(src)) == 0);
41417: SET_NFLG (((uae_s32)(src)) < 0);
41418: m68k_dreg(regs, dstreg) = (src);
41419: }}}}}m68k_incpc(4);
41420: fill_prefetch_0 ();
41421: endlabel2502: ;
41422: return 16;
41423: }
41424: unsigned long REGPARAM2 CPUFUNC(op_203b_5)(uae_u32 opcode) /* MOVE */
41425: {
41426: uae_u32 dstreg = (opcode >> 9) & 7;
41427: OpcodeFamily = 30; CurrentInstrCycles = 18;
41428: {{ uaecptr tmppc = m68k_getpc() + 2;
41429: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
41430: BusCyclePenalty += 2;
41431: if ((srca & 1) != 0) {
41432: last_fault_for_exception_3 = srca;
41433: last_op_for_exception_3 = opcode;
41434: last_addr_for_exception_3 = m68k_getpc() + 4;
41435: Exception(3, 0, M68000_EXC_SRC_CPU);
41436: goto endlabel2503;
41437: }
41438: {{ uae_s32 src = get_long(srca);
41439: { CLEAR_CZNV;
41440: SET_ZFLG (((uae_s32)(src)) == 0);
41441: SET_NFLG (((uae_s32)(src)) < 0);
41442: m68k_dreg(regs, dstreg) = (src);
41443: }}}}}m68k_incpc(4);
41444: fill_prefetch_0 ();
41445: endlabel2503: ;
41446: return 18;
41447: }
41448: unsigned long REGPARAM2 CPUFUNC(op_203c_5)(uae_u32 opcode) /* MOVE */
41449: {
41450: uae_u32 dstreg = (opcode >> 9) & 7;
41451: OpcodeFamily = 30; CurrentInstrCycles = 12;
41452: {{ uae_s32 src = get_ilong_prefetch(2);
41453: { CLEAR_CZNV;
41454: SET_ZFLG (((uae_s32)(src)) == 0);
41455: SET_NFLG (((uae_s32)(src)) < 0);
41456: m68k_dreg(regs, dstreg) = (src);
41457: }}}m68k_incpc(6);
41458: fill_prefetch_0 ();
41459: return 12;
41460: }
41461: unsigned long REGPARAM2 CPUFUNC(op_2040_5)(uae_u32 opcode) /* MOVEA */
41462: {
41463: uae_u32 srcreg = (opcode & 7);
41464: uae_u32 dstreg = (opcode >> 9) & 7;
41465: OpcodeFamily = 31; CurrentInstrCycles = 4;
41466: {{ uae_s32 src = m68k_dreg(regs, srcreg);
41467: { uae_u32 val = src;
41468: m68k_areg(regs, dstreg) = (val);
41469: }}}m68k_incpc(2);
41470: fill_prefetch_2 ();
41471: return 4;
41472: }
41473: unsigned long REGPARAM2 CPUFUNC(op_2048_5)(uae_u32 opcode) /* MOVEA */
41474: {
41475: uae_u32 srcreg = (opcode & 7);
41476: uae_u32 dstreg = (opcode >> 9) & 7;
41477: OpcodeFamily = 31; CurrentInstrCycles = 4;
41478: {{ uae_s32 src = m68k_areg(regs, srcreg);
41479: { uae_u32 val = src;
41480: m68k_areg(regs, dstreg) = (val);
41481: }}}m68k_incpc(2);
41482: fill_prefetch_2 ();
41483: return 4;
41484: }
41485: unsigned long REGPARAM2 CPUFUNC(op_2050_5)(uae_u32 opcode) /* MOVEA */
41486: {
41487: uae_u32 srcreg = (opcode & 7);
41488: uae_u32 dstreg = (opcode >> 9) & 7;
41489: OpcodeFamily = 31; CurrentInstrCycles = 12;
41490: {{ uaecptr srca = m68k_areg(regs, srcreg);
41491: if ((srca & 1) != 0) {
41492: last_fault_for_exception_3 = srca;
41493: last_op_for_exception_3 = opcode;
41494: last_addr_for_exception_3 = m68k_getpc() + 2;
41495: Exception(3, 0, M68000_EXC_SRC_CPU);
41496: goto endlabel2507;
41497: }
41498: {{ uae_s32 src = get_long(srca);
41499: { uae_u32 val = src;
41500: m68k_areg(regs, dstreg) = (val);
41501: }}}}}m68k_incpc(2);
41502: fill_prefetch_2 ();
41503: endlabel2507: ;
41504: return 12;
41505: }
41506: unsigned long REGPARAM2 CPUFUNC(op_2058_5)(uae_u32 opcode) /* MOVEA */
41507: {
41508: uae_u32 srcreg = (opcode & 7);
41509: uae_u32 dstreg = (opcode >> 9) & 7;
41510: OpcodeFamily = 31; CurrentInstrCycles = 12;
41511: {{ uaecptr srca = m68k_areg(regs, srcreg);
41512: if ((srca & 1) != 0) {
41513: last_fault_for_exception_3 = srca;
41514: last_op_for_exception_3 = opcode;
41515: last_addr_for_exception_3 = m68k_getpc() + 2;
41516: Exception(3, 0, M68000_EXC_SRC_CPU);
41517: goto endlabel2508;
41518: }
41519: {{ uae_s32 src = get_long(srca);
41520: m68k_areg(regs, srcreg) += 4;
41521: { uae_u32 val = src;
41522: m68k_areg(regs, dstreg) = (val);
41523: }}}}}m68k_incpc(2);
41524: fill_prefetch_2 ();
41525: endlabel2508: ;
41526: return 12;
41527: }
41528: unsigned long REGPARAM2 CPUFUNC(op_2060_5)(uae_u32 opcode) /* MOVEA */
41529: {
41530: uae_u32 srcreg = (opcode & 7);
41531: uae_u32 dstreg = (opcode >> 9) & 7;
41532: OpcodeFamily = 31; CurrentInstrCycles = 14;
41533: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
41534: if ((srca & 1) != 0) {
41535: last_fault_for_exception_3 = srca;
41536: last_op_for_exception_3 = opcode;
41537: last_addr_for_exception_3 = m68k_getpc() + 2;
41538: Exception(3, 0, M68000_EXC_SRC_CPU);
41539: goto endlabel2509;
41540: }
41541: {{ uae_s32 src = get_long(srca);
41542: m68k_areg (regs, srcreg) = srca;
41543: { uae_u32 val = src;
41544: m68k_areg(regs, dstreg) = (val);
41545: }}}}}m68k_incpc(2);
41546: fill_prefetch_2 ();
41547: endlabel2509: ;
41548: return 14;
41549: }
41550: unsigned long REGPARAM2 CPUFUNC(op_2068_5)(uae_u32 opcode) /* MOVEA */
41551: {
41552: uae_u32 srcreg = (opcode & 7);
41553: uae_u32 dstreg = (opcode >> 9) & 7;
41554: OpcodeFamily = 31; CurrentInstrCycles = 16;
41555: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
41556: if ((srca & 1) != 0) {
41557: last_fault_for_exception_3 = srca;
41558: last_op_for_exception_3 = opcode;
41559: last_addr_for_exception_3 = m68k_getpc() + 4;
41560: Exception(3, 0, M68000_EXC_SRC_CPU);
41561: goto endlabel2510;
41562: }
41563: {{ uae_s32 src = get_long(srca);
41564: { uae_u32 val = src;
41565: m68k_areg(regs, dstreg) = (val);
41566: }}}}}m68k_incpc(4);
41567: fill_prefetch_0 ();
41568: endlabel2510: ;
41569: return 16;
41570: }
41571: unsigned long REGPARAM2 CPUFUNC(op_2070_5)(uae_u32 opcode) /* MOVEA */
41572: {
41573: uae_u32 srcreg = (opcode & 7);
41574: uae_u32 dstreg = (opcode >> 9) & 7;
41575: OpcodeFamily = 31; CurrentInstrCycles = 18;
41576: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
41577: BusCyclePenalty += 2;
41578: if ((srca & 1) != 0) {
41579: last_fault_for_exception_3 = srca;
41580: last_op_for_exception_3 = opcode;
41581: last_addr_for_exception_3 = m68k_getpc() + 4;
41582: Exception(3, 0, M68000_EXC_SRC_CPU);
41583: goto endlabel2511;
41584: }
41585: {{ uae_s32 src = get_long(srca);
41586: { uae_u32 val = src;
41587: m68k_areg(regs, dstreg) = (val);
41588: }}}}}m68k_incpc(4);
41589: fill_prefetch_0 ();
41590: endlabel2511: ;
41591: return 18;
41592: }
41593: unsigned long REGPARAM2 CPUFUNC(op_2078_5)(uae_u32 opcode) /* MOVEA */
41594: {
41595: uae_u32 dstreg = (opcode >> 9) & 7;
41596: OpcodeFamily = 31; CurrentInstrCycles = 16;
41597: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
41598: if ((srca & 1) != 0) {
41599: last_fault_for_exception_3 = srca;
41600: last_op_for_exception_3 = opcode;
41601: last_addr_for_exception_3 = m68k_getpc() + 4;
41602: Exception(3, 0, M68000_EXC_SRC_CPU);
41603: goto endlabel2512;
41604: }
41605: {{ uae_s32 src = get_long(srca);
41606: { uae_u32 val = src;
41607: m68k_areg(regs, dstreg) = (val);
41608: }}}}}m68k_incpc(4);
41609: fill_prefetch_0 ();
41610: endlabel2512: ;
41611: return 16;
41612: }
41613: unsigned long REGPARAM2 CPUFUNC(op_2079_5)(uae_u32 opcode) /* MOVEA */
41614: {
41615: uae_u32 dstreg = (opcode >> 9) & 7;
41616: OpcodeFamily = 31; CurrentInstrCycles = 20;
41617: {{ uaecptr srca = get_ilong_prefetch(2);
41618: if ((srca & 1) != 0) {
41619: last_fault_for_exception_3 = srca;
41620: last_op_for_exception_3 = opcode;
41621: last_addr_for_exception_3 = m68k_getpc() + 6;
41622: Exception(3, 0, M68000_EXC_SRC_CPU);
41623: goto endlabel2513;
41624: }
41625: {{ uae_s32 src = get_long(srca);
41626: { uae_u32 val = src;
41627: m68k_areg(regs, dstreg) = (val);
41628: }}}}}m68k_incpc(6);
41629: fill_prefetch_0 ();
41630: endlabel2513: ;
41631: return 20;
41632: }
41633: unsigned long REGPARAM2 CPUFUNC(op_207a_5)(uae_u32 opcode) /* MOVEA */
41634: {
41635: uae_u32 dstreg = (opcode >> 9) & 7;
41636: OpcodeFamily = 31; CurrentInstrCycles = 16;
41637: {{ uaecptr srca = m68k_getpc () + 2;
41638: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
41639: if ((srca & 1) != 0) {
41640: last_fault_for_exception_3 = srca;
41641: last_op_for_exception_3 = opcode;
41642: last_addr_for_exception_3 = m68k_getpc() + 4;
41643: Exception(3, 0, M68000_EXC_SRC_CPU);
41644: goto endlabel2514;
41645: }
41646: {{ uae_s32 src = get_long(srca);
41647: { uae_u32 val = src;
41648: m68k_areg(regs, dstreg) = (val);
41649: }}}}}m68k_incpc(4);
41650: fill_prefetch_0 ();
41651: endlabel2514: ;
41652: return 16;
41653: }
41654: unsigned long REGPARAM2 CPUFUNC(op_207b_5)(uae_u32 opcode) /* MOVEA */
41655: {
41656: uae_u32 dstreg = (opcode >> 9) & 7;
41657: OpcodeFamily = 31; CurrentInstrCycles = 18;
41658: {{ uaecptr tmppc = m68k_getpc() + 2;
41659: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
41660: BusCyclePenalty += 2;
41661: if ((srca & 1) != 0) {
41662: last_fault_for_exception_3 = srca;
41663: last_op_for_exception_3 = opcode;
41664: last_addr_for_exception_3 = m68k_getpc() + 4;
41665: Exception(3, 0, M68000_EXC_SRC_CPU);
41666: goto endlabel2515;
41667: }
41668: {{ uae_s32 src = get_long(srca);
41669: { uae_u32 val = src;
41670: m68k_areg(regs, dstreg) = (val);
41671: }}}}}m68k_incpc(4);
41672: fill_prefetch_0 ();
41673: endlabel2515: ;
41674: return 18;
41675: }
41676: unsigned long REGPARAM2 CPUFUNC(op_207c_5)(uae_u32 opcode) /* MOVEA */
41677: {
41678: uae_u32 dstreg = (opcode >> 9) & 7;
41679: OpcodeFamily = 31; CurrentInstrCycles = 12;
41680: {{ uae_s32 src = get_ilong_prefetch(2);
41681: { uae_u32 val = src;
41682: m68k_areg(regs, dstreg) = (val);
41683: }}}m68k_incpc(6);
41684: fill_prefetch_0 ();
41685: return 12;
41686: }
41687: unsigned long REGPARAM2 CPUFUNC(op_2080_5)(uae_u32 opcode) /* MOVE */
41688: {
41689: uae_u32 srcreg = (opcode & 7);
41690: uae_u32 dstreg = (opcode >> 9) & 7;
41691: OpcodeFamily = 30; CurrentInstrCycles = 12;
41692: {{ uae_s32 src = m68k_dreg(regs, srcreg);
41693: { uaecptr dsta = m68k_areg(regs, dstreg);
41694: if ((dsta & 1) != 0) {
41695: last_fault_for_exception_3 = dsta;
41696: last_op_for_exception_3 = opcode;
41697: last_addr_for_exception_3 = m68k_getpc() + 2;
41698: Exception(3, 0, M68000_EXC_SRC_CPU);
41699: goto endlabel2517;
41700: }
41701: { CLEAR_CZNV;
41702: SET_ZFLG (((uae_s32)(src)) == 0);
41703: SET_NFLG (((uae_s32)(src)) < 0);
41704: m68k_incpc(2);
41705: fill_prefetch_2 ();
41706: put_long(dsta,src);
41707: }}}}endlabel2517: ;
41708: return 12;
41709: }
41710: unsigned long REGPARAM2 CPUFUNC(op_2088_5)(uae_u32 opcode) /* MOVE */
41711: {
41712: uae_u32 srcreg = (opcode & 7);
41713: uae_u32 dstreg = (opcode >> 9) & 7;
41714: OpcodeFamily = 30; CurrentInstrCycles = 12;
41715: {{ uae_s32 src = m68k_areg(regs, srcreg);
41716: { uaecptr dsta = m68k_areg(regs, dstreg);
41717: if ((dsta & 1) != 0) {
41718: last_fault_for_exception_3 = dsta;
41719: last_op_for_exception_3 = opcode;
41720: last_addr_for_exception_3 = m68k_getpc() + 2;
41721: Exception(3, 0, M68000_EXC_SRC_CPU);
41722: goto endlabel2518;
41723: }
41724: { CLEAR_CZNV;
41725: SET_ZFLG (((uae_s32)(src)) == 0);
41726: SET_NFLG (((uae_s32)(src)) < 0);
41727: m68k_incpc(2);
41728: fill_prefetch_2 ();
41729: put_long(dsta,src);
41730: }}}}endlabel2518: ;
41731: return 12;
41732: }
41733: unsigned long REGPARAM2 CPUFUNC(op_2090_5)(uae_u32 opcode) /* MOVE */
41734: {
41735: uae_u32 srcreg = (opcode & 7);
41736: uae_u32 dstreg = (opcode >> 9) & 7;
41737: OpcodeFamily = 30; CurrentInstrCycles = 20;
41738: {{ uaecptr srca = m68k_areg(regs, srcreg);
41739: if ((srca & 1) != 0) {
41740: last_fault_for_exception_3 = srca;
41741: last_op_for_exception_3 = opcode;
41742: last_addr_for_exception_3 = m68k_getpc() + 2;
41743: Exception(3, 0, M68000_EXC_SRC_CPU);
41744: goto endlabel2519;
41745: }
41746: {{ uae_s32 src = get_long(srca);
41747: { uaecptr dsta = m68k_areg(regs, dstreg);
41748: if ((dsta & 1) != 0) {
41749: last_fault_for_exception_3 = dsta;
41750: last_op_for_exception_3 = opcode;
41751: last_addr_for_exception_3 = m68k_getpc() + 2;
41752: Exception(3, 0, M68000_EXC_SRC_CPU);
41753: goto endlabel2519;
41754: }
41755: { CLEAR_CZNV;
41756: SET_ZFLG (((uae_s32)(src)) == 0);
41757: SET_NFLG (((uae_s32)(src)) < 0);
41758: m68k_incpc(2);
41759: fill_prefetch_2 ();
41760: put_long(dsta,src);
41761: }}}}}}endlabel2519: ;
41762: return 20;
41763: }
41764: unsigned long REGPARAM2 CPUFUNC(op_2098_5)(uae_u32 opcode) /* MOVE */
41765: {
41766: uae_u32 srcreg = (opcode & 7);
41767: uae_u32 dstreg = (opcode >> 9) & 7;
41768: OpcodeFamily = 30; CurrentInstrCycles = 20;
41769: {{ uaecptr srca = m68k_areg(regs, srcreg);
41770: if ((srca & 1) != 0) {
41771: last_fault_for_exception_3 = srca;
41772: last_op_for_exception_3 = opcode;
41773: last_addr_for_exception_3 = m68k_getpc() + 2;
41774: Exception(3, 0, M68000_EXC_SRC_CPU);
41775: goto endlabel2520;
41776: }
41777: {{ uae_s32 src = get_long(srca);
41778: m68k_areg(regs, srcreg) += 4;
41779: { uaecptr dsta = m68k_areg(regs, dstreg);
41780: if ((dsta & 1) != 0) {
41781: last_fault_for_exception_3 = dsta;
41782: last_op_for_exception_3 = opcode;
41783: last_addr_for_exception_3 = m68k_getpc() + 2;
41784: Exception(3, 0, M68000_EXC_SRC_CPU);
41785: goto endlabel2520;
41786: }
41787: { CLEAR_CZNV;
41788: SET_ZFLG (((uae_s32)(src)) == 0);
41789: SET_NFLG (((uae_s32)(src)) < 0);
41790: m68k_incpc(2);
41791: fill_prefetch_2 ();
41792: put_long(dsta,src);
41793: }}}}}}endlabel2520: ;
41794: return 20;
41795: }
41796: unsigned long REGPARAM2 CPUFUNC(op_20a0_5)(uae_u32 opcode) /* MOVE */
41797: {
41798: uae_u32 srcreg = (opcode & 7);
41799: uae_u32 dstreg = (opcode >> 9) & 7;
41800: OpcodeFamily = 30; CurrentInstrCycles = 22;
41801: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
41802: if ((srca & 1) != 0) {
41803: last_fault_for_exception_3 = srca;
41804: last_op_for_exception_3 = opcode;
41805: last_addr_for_exception_3 = m68k_getpc() + 2;
41806: Exception(3, 0, M68000_EXC_SRC_CPU);
41807: goto endlabel2521;
41808: }
41809: {{ uae_s32 src = get_long(srca);
41810: m68k_areg (regs, srcreg) = srca;
41811: { uaecptr dsta = m68k_areg(regs, dstreg);
41812: if ((dsta & 1) != 0) {
41813: last_fault_for_exception_3 = dsta;
41814: last_op_for_exception_3 = opcode;
41815: last_addr_for_exception_3 = m68k_getpc() + 2;
41816: Exception(3, 0, M68000_EXC_SRC_CPU);
41817: goto endlabel2521;
41818: }
41819: { CLEAR_CZNV;
41820: SET_ZFLG (((uae_s32)(src)) == 0);
41821: SET_NFLG (((uae_s32)(src)) < 0);
41822: m68k_incpc(2);
41823: fill_prefetch_2 ();
41824: put_long(dsta,src);
41825: }}}}}}endlabel2521: ;
41826: return 22;
41827: }
41828: unsigned long REGPARAM2 CPUFUNC(op_20a8_5)(uae_u32 opcode) /* MOVE */
41829: {
41830: uae_u32 srcreg = (opcode & 7);
41831: uae_u32 dstreg = (opcode >> 9) & 7;
41832: OpcodeFamily = 30; CurrentInstrCycles = 24;
41833: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
41834: if ((srca & 1) != 0) {
41835: last_fault_for_exception_3 = srca;
41836: last_op_for_exception_3 = opcode;
41837: last_addr_for_exception_3 = m68k_getpc() + 4;
41838: Exception(3, 0, M68000_EXC_SRC_CPU);
41839: goto endlabel2522;
41840: }
41841: {{ uae_s32 src = get_long(srca);
41842: { uaecptr dsta = m68k_areg(regs, dstreg);
41843: if ((dsta & 1) != 0) {
41844: last_fault_for_exception_3 = dsta;
41845: last_op_for_exception_3 = opcode;
41846: last_addr_for_exception_3 = m68k_getpc() + 4;
41847: Exception(3, 0, M68000_EXC_SRC_CPU);
41848: goto endlabel2522;
41849: }
41850: { CLEAR_CZNV;
41851: SET_ZFLG (((uae_s32)(src)) == 0);
41852: SET_NFLG (((uae_s32)(src)) < 0);
41853: m68k_incpc(4);
41854: fill_prefetch_0 ();
41855: put_long(dsta,src);
41856: }}}}}}endlabel2522: ;
41857: return 24;
41858: }
41859: unsigned long REGPARAM2 CPUFUNC(op_20b0_5)(uae_u32 opcode) /* MOVE */
41860: {
41861: uae_u32 srcreg = (opcode & 7);
41862: uae_u32 dstreg = (opcode >> 9) & 7;
41863: OpcodeFamily = 30; CurrentInstrCycles = 26;
41864: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
41865: BusCyclePenalty += 2;
41866: if ((srca & 1) != 0) {
41867: last_fault_for_exception_3 = srca;
41868: last_op_for_exception_3 = opcode;
41869: last_addr_for_exception_3 = m68k_getpc() + 4;
41870: Exception(3, 0, M68000_EXC_SRC_CPU);
41871: goto endlabel2523;
41872: }
41873: {{ uae_s32 src = get_long(srca);
41874: { uaecptr dsta = m68k_areg(regs, dstreg);
41875: if ((dsta & 1) != 0) {
41876: last_fault_for_exception_3 = dsta;
41877: last_op_for_exception_3 = opcode;
41878: last_addr_for_exception_3 = m68k_getpc() + 4;
41879: Exception(3, 0, M68000_EXC_SRC_CPU);
41880: goto endlabel2523;
41881: }
41882: { CLEAR_CZNV;
41883: SET_ZFLG (((uae_s32)(src)) == 0);
41884: SET_NFLG (((uae_s32)(src)) < 0);
41885: m68k_incpc(4);
41886: fill_prefetch_0 ();
41887: put_long(dsta,src);
41888: }}}}}}endlabel2523: ;
41889: return 26;
41890: }
41891: unsigned long REGPARAM2 CPUFUNC(op_20b8_5)(uae_u32 opcode) /* MOVE */
41892: {
41893: uae_u32 dstreg = (opcode >> 9) & 7;
41894: OpcodeFamily = 30; CurrentInstrCycles = 24;
41895: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
41896: if ((srca & 1) != 0) {
41897: last_fault_for_exception_3 = srca;
41898: last_op_for_exception_3 = opcode;
41899: last_addr_for_exception_3 = m68k_getpc() + 4;
41900: Exception(3, 0, M68000_EXC_SRC_CPU);
41901: goto endlabel2524;
41902: }
41903: {{ uae_s32 src = get_long(srca);
41904: { uaecptr dsta = m68k_areg(regs, dstreg);
41905: if ((dsta & 1) != 0) {
41906: last_fault_for_exception_3 = dsta;
41907: last_op_for_exception_3 = opcode;
41908: last_addr_for_exception_3 = m68k_getpc() + 4;
41909: Exception(3, 0, M68000_EXC_SRC_CPU);
41910: goto endlabel2524;
41911: }
41912: { CLEAR_CZNV;
41913: SET_ZFLG (((uae_s32)(src)) == 0);
41914: SET_NFLG (((uae_s32)(src)) < 0);
41915: m68k_incpc(4);
41916: fill_prefetch_0 ();
41917: put_long(dsta,src);
41918: }}}}}}endlabel2524: ;
41919: return 24;
41920: }
41921: unsigned long REGPARAM2 CPUFUNC(op_20b9_5)(uae_u32 opcode) /* MOVE */
41922: {
41923: uae_u32 dstreg = (opcode >> 9) & 7;
41924: OpcodeFamily = 30; CurrentInstrCycles = 28;
41925: {{ uaecptr srca = get_ilong_prefetch(2);
41926: if ((srca & 1) != 0) {
41927: last_fault_for_exception_3 = srca;
41928: last_op_for_exception_3 = opcode;
41929: last_addr_for_exception_3 = m68k_getpc() + 6;
41930: Exception(3, 0, M68000_EXC_SRC_CPU);
41931: goto endlabel2525;
41932: }
41933: {{ uae_s32 src = get_long(srca);
41934: { uaecptr dsta = m68k_areg(regs, dstreg);
41935: if ((dsta & 1) != 0) {
41936: last_fault_for_exception_3 = dsta;
41937: last_op_for_exception_3 = opcode;
41938: last_addr_for_exception_3 = m68k_getpc() + 6;
41939: Exception(3, 0, M68000_EXC_SRC_CPU);
41940: goto endlabel2525;
41941: }
41942: { CLEAR_CZNV;
41943: SET_ZFLG (((uae_s32)(src)) == 0);
41944: SET_NFLG (((uae_s32)(src)) < 0);
41945: m68k_incpc(6);
41946: fill_prefetch_0 ();
41947: put_long(dsta,src);
41948: }}}}}}endlabel2525: ;
41949: return 28;
41950: }
41951: unsigned long REGPARAM2 CPUFUNC(op_20ba_5)(uae_u32 opcode) /* MOVE */
41952: {
41953: uae_u32 dstreg = (opcode >> 9) & 7;
41954: OpcodeFamily = 30; CurrentInstrCycles = 24;
41955: {{ uaecptr srca = m68k_getpc () + 2;
41956: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
41957: if ((srca & 1) != 0) {
41958: last_fault_for_exception_3 = srca;
41959: last_op_for_exception_3 = opcode;
41960: last_addr_for_exception_3 = m68k_getpc() + 4;
41961: Exception(3, 0, M68000_EXC_SRC_CPU);
41962: goto endlabel2526;
41963: }
41964: {{ uae_s32 src = get_long(srca);
41965: { uaecptr dsta = m68k_areg(regs, dstreg);
41966: if ((dsta & 1) != 0) {
41967: last_fault_for_exception_3 = dsta;
41968: last_op_for_exception_3 = opcode;
41969: last_addr_for_exception_3 = m68k_getpc() + 4;
41970: Exception(3, 0, M68000_EXC_SRC_CPU);
41971: goto endlabel2526;
41972: }
41973: { CLEAR_CZNV;
41974: SET_ZFLG (((uae_s32)(src)) == 0);
41975: SET_NFLG (((uae_s32)(src)) < 0);
41976: m68k_incpc(4);
41977: fill_prefetch_0 ();
41978: put_long(dsta,src);
41979: }}}}}}endlabel2526: ;
41980: return 24;
41981: }
41982: unsigned long REGPARAM2 CPUFUNC(op_20bb_5)(uae_u32 opcode) /* MOVE */
41983: {
41984: uae_u32 dstreg = (opcode >> 9) & 7;
41985: OpcodeFamily = 30; CurrentInstrCycles = 26;
41986: {{ uaecptr tmppc = m68k_getpc() + 2;
41987: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
41988: BusCyclePenalty += 2;
41989: if ((srca & 1) != 0) {
41990: last_fault_for_exception_3 = srca;
41991: last_op_for_exception_3 = opcode;
41992: last_addr_for_exception_3 = m68k_getpc() + 4;
41993: Exception(3, 0, M68000_EXC_SRC_CPU);
41994: goto endlabel2527;
41995: }
41996: {{ uae_s32 src = get_long(srca);
41997: { uaecptr dsta = m68k_areg(regs, dstreg);
41998: if ((dsta & 1) != 0) {
41999: last_fault_for_exception_3 = dsta;
42000: last_op_for_exception_3 = opcode;
42001: last_addr_for_exception_3 = m68k_getpc() + 4;
42002: Exception(3, 0, M68000_EXC_SRC_CPU);
42003: goto endlabel2527;
42004: }
42005: { CLEAR_CZNV;
42006: SET_ZFLG (((uae_s32)(src)) == 0);
42007: SET_NFLG (((uae_s32)(src)) < 0);
42008: m68k_incpc(4);
42009: fill_prefetch_0 ();
42010: put_long(dsta,src);
42011: }}}}}}endlabel2527: ;
42012: return 26;
42013: }
42014: unsigned long REGPARAM2 CPUFUNC(op_20bc_5)(uae_u32 opcode) /* MOVE */
42015: {
42016: uae_u32 dstreg = (opcode >> 9) & 7;
42017: OpcodeFamily = 30; CurrentInstrCycles = 20;
42018: {{ uae_s32 src = get_ilong_prefetch(2);
42019: { uaecptr dsta = m68k_areg(regs, dstreg);
42020: if ((dsta & 1) != 0) {
42021: last_fault_for_exception_3 = dsta;
42022: last_op_for_exception_3 = opcode;
42023: last_addr_for_exception_3 = m68k_getpc() + 6;
42024: Exception(3, 0, M68000_EXC_SRC_CPU);
42025: goto endlabel2528;
42026: }
42027: { CLEAR_CZNV;
42028: SET_ZFLG (((uae_s32)(src)) == 0);
42029: SET_NFLG (((uae_s32)(src)) < 0);
42030: m68k_incpc(6);
42031: fill_prefetch_0 ();
42032: put_long(dsta,src);
42033: }}}}endlabel2528: ;
42034: return 20;
42035: }
42036: unsigned long REGPARAM2 CPUFUNC(op_20c0_5)(uae_u32 opcode) /* MOVE */
42037: {
42038: uae_u32 srcreg = (opcode & 7);
42039: uae_u32 dstreg = (opcode >> 9) & 7;
42040: OpcodeFamily = 30; CurrentInstrCycles = 12;
42041: {{ uae_s32 src = m68k_dreg(regs, srcreg);
42042: { uaecptr dsta = m68k_areg(regs, dstreg);
42043: if ((dsta & 1) != 0) {
42044: last_fault_for_exception_3 = dsta;
42045: last_op_for_exception_3 = opcode;
42046: last_addr_for_exception_3 = m68k_getpc() + 2;
42047: Exception(3, 0, M68000_EXC_SRC_CPU);
42048: goto endlabel2529;
42049: }
42050: { m68k_areg(regs, dstreg) += 4;
42051: CLEAR_CZNV;
42052: SET_ZFLG (((uae_s32)(src)) == 0);
42053: SET_NFLG (((uae_s32)(src)) < 0);
42054: m68k_incpc(2);
42055: fill_prefetch_2 ();
42056: put_long(dsta,src);
42057: }}}}endlabel2529: ;
42058: return 12;
42059: }
42060: unsigned long REGPARAM2 CPUFUNC(op_20c8_5)(uae_u32 opcode) /* MOVE */
42061: {
42062: uae_u32 srcreg = (opcode & 7);
42063: uae_u32 dstreg = (opcode >> 9) & 7;
42064: OpcodeFamily = 30; CurrentInstrCycles = 12;
42065: {{ uae_s32 src = m68k_areg(regs, srcreg);
42066: { uaecptr dsta = m68k_areg(regs, dstreg);
42067: if ((dsta & 1) != 0) {
42068: last_fault_for_exception_3 = dsta;
42069: last_op_for_exception_3 = opcode;
42070: last_addr_for_exception_3 = m68k_getpc() + 2;
42071: Exception(3, 0, M68000_EXC_SRC_CPU);
42072: goto endlabel2530;
42073: }
42074: { m68k_areg(regs, dstreg) += 4;
42075: CLEAR_CZNV;
42076: SET_ZFLG (((uae_s32)(src)) == 0);
42077: SET_NFLG (((uae_s32)(src)) < 0);
42078: m68k_incpc(2);
42079: fill_prefetch_2 ();
42080: put_long(dsta,src);
42081: }}}}endlabel2530: ;
42082: return 12;
42083: }
42084: unsigned long REGPARAM2 CPUFUNC(op_20d0_5)(uae_u32 opcode) /* MOVE */
42085: {
42086: uae_u32 srcreg = (opcode & 7);
42087: uae_u32 dstreg = (opcode >> 9) & 7;
42088: OpcodeFamily = 30; CurrentInstrCycles = 20;
42089: {{ uaecptr srca = m68k_areg(regs, srcreg);
42090: if ((srca & 1) != 0) {
42091: last_fault_for_exception_3 = srca;
42092: last_op_for_exception_3 = opcode;
42093: last_addr_for_exception_3 = m68k_getpc() + 2;
42094: Exception(3, 0, M68000_EXC_SRC_CPU);
42095: goto endlabel2531;
42096: }
42097: {{ uae_s32 src = get_long(srca);
42098: { uaecptr dsta = m68k_areg(regs, dstreg);
42099: if ((dsta & 1) != 0) {
42100: last_fault_for_exception_3 = dsta;
42101: last_op_for_exception_3 = opcode;
42102: last_addr_for_exception_3 = m68k_getpc() + 2;
42103: Exception(3, 0, M68000_EXC_SRC_CPU);
42104: goto endlabel2531;
42105: }
42106: { m68k_areg(regs, dstreg) += 4;
42107: CLEAR_CZNV;
42108: SET_ZFLG (((uae_s32)(src)) == 0);
42109: SET_NFLG (((uae_s32)(src)) < 0);
42110: m68k_incpc(2);
42111: fill_prefetch_2 ();
42112: put_long(dsta,src);
42113: }}}}}}endlabel2531: ;
42114: return 20;
42115: }
42116: unsigned long REGPARAM2 CPUFUNC(op_20d8_5)(uae_u32 opcode) /* MOVE */
42117: {
42118: uae_u32 srcreg = (opcode & 7);
42119: uae_u32 dstreg = (opcode >> 9) & 7;
42120: OpcodeFamily = 30; CurrentInstrCycles = 20;
42121: {{ uaecptr srca = m68k_areg(regs, srcreg);
42122: if ((srca & 1) != 0) {
42123: last_fault_for_exception_3 = srca;
42124: last_op_for_exception_3 = opcode;
42125: last_addr_for_exception_3 = m68k_getpc() + 2;
42126: Exception(3, 0, M68000_EXC_SRC_CPU);
42127: goto endlabel2532;
42128: }
42129: {{ uae_s32 src = get_long(srca);
42130: m68k_areg(regs, srcreg) += 4;
42131: { uaecptr dsta = m68k_areg(regs, dstreg);
42132: if ((dsta & 1) != 0) {
42133: last_fault_for_exception_3 = dsta;
42134: last_op_for_exception_3 = opcode;
42135: last_addr_for_exception_3 = m68k_getpc() + 2;
42136: Exception(3, 0, M68000_EXC_SRC_CPU);
42137: goto endlabel2532;
42138: }
42139: { m68k_areg(regs, dstreg) += 4;
42140: CLEAR_CZNV;
42141: SET_ZFLG (((uae_s32)(src)) == 0);
42142: SET_NFLG (((uae_s32)(src)) < 0);
42143: m68k_incpc(2);
42144: fill_prefetch_2 ();
42145: put_long(dsta,src);
42146: }}}}}}endlabel2532: ;
42147: return 20;
42148: }
42149: unsigned long REGPARAM2 CPUFUNC(op_20e0_5)(uae_u32 opcode) /* MOVE */
42150: {
42151: uae_u32 srcreg = (opcode & 7);
42152: uae_u32 dstreg = (opcode >> 9) & 7;
42153: OpcodeFamily = 30; CurrentInstrCycles = 22;
42154: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
42155: if ((srca & 1) != 0) {
42156: last_fault_for_exception_3 = srca;
42157: last_op_for_exception_3 = opcode;
42158: last_addr_for_exception_3 = m68k_getpc() + 2;
42159: Exception(3, 0, M68000_EXC_SRC_CPU);
42160: goto endlabel2533;
42161: }
42162: {{ uae_s32 src = get_long(srca);
42163: m68k_areg (regs, srcreg) = srca;
42164: { uaecptr dsta = m68k_areg(regs, dstreg);
42165: if ((dsta & 1) != 0) {
42166: last_fault_for_exception_3 = dsta;
42167: last_op_for_exception_3 = opcode;
42168: last_addr_for_exception_3 = m68k_getpc() + 2;
42169: Exception(3, 0, M68000_EXC_SRC_CPU);
42170: goto endlabel2533;
42171: }
42172: { m68k_areg(regs, dstreg) += 4;
42173: CLEAR_CZNV;
42174: SET_ZFLG (((uae_s32)(src)) == 0);
42175: SET_NFLG (((uae_s32)(src)) < 0);
42176: m68k_incpc(2);
42177: fill_prefetch_2 ();
42178: put_long(dsta,src);
42179: }}}}}}endlabel2533: ;
42180: return 22;
42181: }
42182: unsigned long REGPARAM2 CPUFUNC(op_20e8_5)(uae_u32 opcode) /* MOVE */
42183: {
42184: uae_u32 srcreg = (opcode & 7);
42185: uae_u32 dstreg = (opcode >> 9) & 7;
42186: OpcodeFamily = 30; CurrentInstrCycles = 24;
42187: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
42188: if ((srca & 1) != 0) {
42189: last_fault_for_exception_3 = srca;
42190: last_op_for_exception_3 = opcode;
42191: last_addr_for_exception_3 = m68k_getpc() + 4;
42192: Exception(3, 0, M68000_EXC_SRC_CPU);
42193: goto endlabel2534;
42194: }
42195: {{ uae_s32 src = get_long(srca);
42196: { uaecptr dsta = m68k_areg(regs, dstreg);
42197: if ((dsta & 1) != 0) {
42198: last_fault_for_exception_3 = dsta;
42199: last_op_for_exception_3 = opcode;
42200: last_addr_for_exception_3 = m68k_getpc() + 4;
42201: Exception(3, 0, M68000_EXC_SRC_CPU);
42202: goto endlabel2534;
42203: }
42204: { m68k_areg(regs, dstreg) += 4;
42205: CLEAR_CZNV;
42206: SET_ZFLG (((uae_s32)(src)) == 0);
42207: SET_NFLG (((uae_s32)(src)) < 0);
42208: m68k_incpc(4);
42209: fill_prefetch_0 ();
42210: put_long(dsta,src);
42211: }}}}}}endlabel2534: ;
42212: return 24;
42213: }
42214: unsigned long REGPARAM2 CPUFUNC(op_20f0_5)(uae_u32 opcode) /* MOVE */
42215: {
42216: uae_u32 srcreg = (opcode & 7);
42217: uae_u32 dstreg = (opcode >> 9) & 7;
42218: OpcodeFamily = 30; CurrentInstrCycles = 26;
42219: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
42220: BusCyclePenalty += 2;
42221: if ((srca & 1) != 0) {
42222: last_fault_for_exception_3 = srca;
42223: last_op_for_exception_3 = opcode;
42224: last_addr_for_exception_3 = m68k_getpc() + 4;
42225: Exception(3, 0, M68000_EXC_SRC_CPU);
42226: goto endlabel2535;
42227: }
42228: {{ uae_s32 src = get_long(srca);
42229: { uaecptr dsta = m68k_areg(regs, dstreg);
42230: if ((dsta & 1) != 0) {
42231: last_fault_for_exception_3 = dsta;
42232: last_op_for_exception_3 = opcode;
42233: last_addr_for_exception_3 = m68k_getpc() + 4;
42234: Exception(3, 0, M68000_EXC_SRC_CPU);
42235: goto endlabel2535;
42236: }
42237: { m68k_areg(regs, dstreg) += 4;
42238: CLEAR_CZNV;
42239: SET_ZFLG (((uae_s32)(src)) == 0);
42240: SET_NFLG (((uae_s32)(src)) < 0);
42241: m68k_incpc(4);
42242: fill_prefetch_0 ();
42243: put_long(dsta,src);
42244: }}}}}}endlabel2535: ;
42245: return 26;
42246: }
42247: unsigned long REGPARAM2 CPUFUNC(op_20f8_5)(uae_u32 opcode) /* MOVE */
42248: {
42249: uae_u32 dstreg = (opcode >> 9) & 7;
42250: OpcodeFamily = 30; CurrentInstrCycles = 24;
42251: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
42252: if ((srca & 1) != 0) {
42253: last_fault_for_exception_3 = srca;
42254: last_op_for_exception_3 = opcode;
42255: last_addr_for_exception_3 = m68k_getpc() + 4;
42256: Exception(3, 0, M68000_EXC_SRC_CPU);
42257: goto endlabel2536;
42258: }
42259: {{ uae_s32 src = get_long(srca);
42260: { uaecptr dsta = m68k_areg(regs, dstreg);
42261: if ((dsta & 1) != 0) {
42262: last_fault_for_exception_3 = dsta;
42263: last_op_for_exception_3 = opcode;
42264: last_addr_for_exception_3 = m68k_getpc() + 4;
42265: Exception(3, 0, M68000_EXC_SRC_CPU);
42266: goto endlabel2536;
42267: }
42268: { m68k_areg(regs, dstreg) += 4;
42269: CLEAR_CZNV;
42270: SET_ZFLG (((uae_s32)(src)) == 0);
42271: SET_NFLG (((uae_s32)(src)) < 0);
42272: m68k_incpc(4);
42273: fill_prefetch_0 ();
42274: put_long(dsta,src);
42275: }}}}}}endlabel2536: ;
42276: return 24;
42277: }
42278: unsigned long REGPARAM2 CPUFUNC(op_20f9_5)(uae_u32 opcode) /* MOVE */
42279: {
42280: uae_u32 dstreg = (opcode >> 9) & 7;
42281: OpcodeFamily = 30; CurrentInstrCycles = 28;
42282: {{ uaecptr srca = get_ilong_prefetch(2);
42283: if ((srca & 1) != 0) {
42284: last_fault_for_exception_3 = srca;
42285: last_op_for_exception_3 = opcode;
42286: last_addr_for_exception_3 = m68k_getpc() + 6;
42287: Exception(3, 0, M68000_EXC_SRC_CPU);
42288: goto endlabel2537;
42289: }
42290: {{ uae_s32 src = get_long(srca);
42291: { uaecptr dsta = m68k_areg(regs, dstreg);
42292: if ((dsta & 1) != 0) {
42293: last_fault_for_exception_3 = dsta;
42294: last_op_for_exception_3 = opcode;
42295: last_addr_for_exception_3 = m68k_getpc() + 6;
42296: Exception(3, 0, M68000_EXC_SRC_CPU);
42297: goto endlabel2537;
42298: }
42299: { m68k_areg(regs, dstreg) += 4;
42300: CLEAR_CZNV;
42301: SET_ZFLG (((uae_s32)(src)) == 0);
42302: SET_NFLG (((uae_s32)(src)) < 0);
42303: m68k_incpc(6);
42304: fill_prefetch_0 ();
42305: put_long(dsta,src);
42306: }}}}}}endlabel2537: ;
42307: return 28;
42308: }
42309: unsigned long REGPARAM2 CPUFUNC(op_20fa_5)(uae_u32 opcode) /* MOVE */
42310: {
42311: uae_u32 dstreg = (opcode >> 9) & 7;
42312: OpcodeFamily = 30; CurrentInstrCycles = 24;
42313: {{ uaecptr srca = m68k_getpc () + 2;
42314: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
42315: if ((srca & 1) != 0) {
42316: last_fault_for_exception_3 = srca;
42317: last_op_for_exception_3 = opcode;
42318: last_addr_for_exception_3 = m68k_getpc() + 4;
42319: Exception(3, 0, M68000_EXC_SRC_CPU);
42320: goto endlabel2538;
42321: }
42322: {{ uae_s32 src = get_long(srca);
42323: { uaecptr dsta = m68k_areg(regs, dstreg);
42324: if ((dsta & 1) != 0) {
42325: last_fault_for_exception_3 = dsta;
42326: last_op_for_exception_3 = opcode;
42327: last_addr_for_exception_3 = m68k_getpc() + 4;
42328: Exception(3, 0, M68000_EXC_SRC_CPU);
42329: goto endlabel2538;
42330: }
42331: { m68k_areg(regs, dstreg) += 4;
42332: CLEAR_CZNV;
42333: SET_ZFLG (((uae_s32)(src)) == 0);
42334: SET_NFLG (((uae_s32)(src)) < 0);
42335: m68k_incpc(4);
42336: fill_prefetch_0 ();
42337: put_long(dsta,src);
42338: }}}}}}endlabel2538: ;
42339: return 24;
42340: }
42341: unsigned long REGPARAM2 CPUFUNC(op_20fb_5)(uae_u32 opcode) /* MOVE */
42342: {
42343: uae_u32 dstreg = (opcode >> 9) & 7;
42344: OpcodeFamily = 30; CurrentInstrCycles = 26;
42345: {{ uaecptr tmppc = m68k_getpc() + 2;
42346: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
42347: BusCyclePenalty += 2;
42348: if ((srca & 1) != 0) {
42349: last_fault_for_exception_3 = srca;
42350: last_op_for_exception_3 = opcode;
42351: last_addr_for_exception_3 = m68k_getpc() + 4;
42352: Exception(3, 0, M68000_EXC_SRC_CPU);
42353: goto endlabel2539;
42354: }
42355: {{ uae_s32 src = get_long(srca);
42356: { uaecptr dsta = m68k_areg(regs, dstreg);
42357: if ((dsta & 1) != 0) {
42358: last_fault_for_exception_3 = dsta;
42359: last_op_for_exception_3 = opcode;
42360: last_addr_for_exception_3 = m68k_getpc() + 4;
42361: Exception(3, 0, M68000_EXC_SRC_CPU);
42362: goto endlabel2539;
42363: }
42364: { m68k_areg(regs, dstreg) += 4;
42365: CLEAR_CZNV;
42366: SET_ZFLG (((uae_s32)(src)) == 0);
42367: SET_NFLG (((uae_s32)(src)) < 0);
42368: m68k_incpc(4);
42369: fill_prefetch_0 ();
42370: put_long(dsta,src);
42371: }}}}}}endlabel2539: ;
42372: return 26;
42373: }
42374: unsigned long REGPARAM2 CPUFUNC(op_20fc_5)(uae_u32 opcode) /* MOVE */
42375: {
42376: uae_u32 dstreg = (opcode >> 9) & 7;
42377: OpcodeFamily = 30; CurrentInstrCycles = 20;
42378: {{ uae_s32 src = get_ilong_prefetch(2);
42379: { uaecptr dsta = m68k_areg(regs, dstreg);
42380: if ((dsta & 1) != 0) {
42381: last_fault_for_exception_3 = dsta;
42382: last_op_for_exception_3 = opcode;
42383: last_addr_for_exception_3 = m68k_getpc() + 6;
42384: Exception(3, 0, M68000_EXC_SRC_CPU);
42385: goto endlabel2540;
42386: }
42387: { m68k_areg(regs, dstreg) += 4;
42388: CLEAR_CZNV;
42389: SET_ZFLG (((uae_s32)(src)) == 0);
42390: SET_NFLG (((uae_s32)(src)) < 0);
42391: m68k_incpc(6);
42392: fill_prefetch_0 ();
42393: put_long(dsta,src);
42394: }}}}endlabel2540: ;
42395: return 20;
42396: }
42397: unsigned long REGPARAM2 CPUFUNC(op_2100_5)(uae_u32 opcode) /* MOVE */
42398: {
42399: uae_u32 srcreg = (opcode & 7);
42400: uae_u32 dstreg = (opcode >> 9) & 7;
42401: OpcodeFamily = 30; CurrentInstrCycles = 12;
42402: {{ uae_s32 src = m68k_dreg(regs, srcreg);
42403: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42404: if ((dsta & 1) != 0) {
42405: last_fault_for_exception_3 = dsta;
42406: last_op_for_exception_3 = opcode;
42407: last_addr_for_exception_3 = m68k_getpc() + 2;
42408: Exception(3, 0, M68000_EXC_SRC_CPU);
42409: goto endlabel2541;
42410: }
42411: { m68k_areg (regs, dstreg) = dsta;
42412: CLEAR_CZNV;
42413: SET_ZFLG (((uae_s32)(src)) == 0);
42414: SET_NFLG (((uae_s32)(src)) < 0);
42415: m68k_incpc(2);
42416: fill_prefetch_2 ();
42417: put_long(dsta,src);
42418: }}}}endlabel2541: ;
42419: return 12;
42420: }
42421: unsigned long REGPARAM2 CPUFUNC(op_2108_5)(uae_u32 opcode) /* MOVE */
42422: {
42423: uae_u32 srcreg = (opcode & 7);
42424: uae_u32 dstreg = (opcode >> 9) & 7;
42425: OpcodeFamily = 30; CurrentInstrCycles = 12;
42426: {{ uae_s32 src = m68k_areg(regs, srcreg);
42427: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42428: if ((dsta & 1) != 0) {
42429: last_fault_for_exception_3 = dsta;
42430: last_op_for_exception_3 = opcode;
42431: last_addr_for_exception_3 = m68k_getpc() + 2;
42432: Exception(3, 0, M68000_EXC_SRC_CPU);
42433: goto endlabel2542;
42434: }
42435: { m68k_areg (regs, dstreg) = dsta;
42436: CLEAR_CZNV;
42437: SET_ZFLG (((uae_s32)(src)) == 0);
42438: SET_NFLG (((uae_s32)(src)) < 0);
42439: m68k_incpc(2);
42440: fill_prefetch_2 ();
42441: put_long(dsta,src);
42442: }}}}endlabel2542: ;
42443: return 12;
42444: }
42445: unsigned long REGPARAM2 CPUFUNC(op_2110_5)(uae_u32 opcode) /* MOVE */
42446: {
42447: uae_u32 srcreg = (opcode & 7);
42448: uae_u32 dstreg = (opcode >> 9) & 7;
42449: OpcodeFamily = 30; CurrentInstrCycles = 20;
42450: {{ uaecptr srca = m68k_areg(regs, srcreg);
42451: if ((srca & 1) != 0) {
42452: last_fault_for_exception_3 = srca;
42453: last_op_for_exception_3 = opcode;
42454: last_addr_for_exception_3 = m68k_getpc() + 2;
42455: Exception(3, 0, M68000_EXC_SRC_CPU);
42456: goto endlabel2543;
42457: }
42458: {{ uae_s32 src = get_long(srca);
42459: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42460: if ((dsta & 1) != 0) {
42461: last_fault_for_exception_3 = dsta;
42462: last_op_for_exception_3 = opcode;
42463: last_addr_for_exception_3 = m68k_getpc() + 2;
42464: Exception(3, 0, M68000_EXC_SRC_CPU);
42465: goto endlabel2543;
42466: }
42467: { m68k_areg (regs, dstreg) = dsta;
42468: CLEAR_CZNV;
42469: SET_ZFLG (((uae_s32)(src)) == 0);
42470: SET_NFLG (((uae_s32)(src)) < 0);
42471: m68k_incpc(2);
42472: fill_prefetch_2 ();
42473: put_long(dsta,src);
42474: }}}}}}endlabel2543: ;
42475: return 20;
42476: }
42477: unsigned long REGPARAM2 CPUFUNC(op_2118_5)(uae_u32 opcode) /* MOVE */
42478: {
42479: uae_u32 srcreg = (opcode & 7);
42480: uae_u32 dstreg = (opcode >> 9) & 7;
42481: OpcodeFamily = 30; CurrentInstrCycles = 20;
42482: {{ uaecptr srca = m68k_areg(regs, srcreg);
42483: if ((srca & 1) != 0) {
42484: last_fault_for_exception_3 = srca;
42485: last_op_for_exception_3 = opcode;
42486: last_addr_for_exception_3 = m68k_getpc() + 2;
42487: Exception(3, 0, M68000_EXC_SRC_CPU);
42488: goto endlabel2544;
42489: }
42490: {{ uae_s32 src = get_long(srca);
42491: m68k_areg(regs, srcreg) += 4;
42492: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42493: if ((dsta & 1) != 0) {
42494: last_fault_for_exception_3 = dsta;
42495: last_op_for_exception_3 = opcode;
42496: last_addr_for_exception_3 = m68k_getpc() + 2;
42497: Exception(3, 0, M68000_EXC_SRC_CPU);
42498: goto endlabel2544;
42499: }
42500: { m68k_areg (regs, dstreg) = dsta;
42501: CLEAR_CZNV;
42502: SET_ZFLG (((uae_s32)(src)) == 0);
42503: SET_NFLG (((uae_s32)(src)) < 0);
42504: m68k_incpc(2);
42505: fill_prefetch_2 ();
42506: put_long(dsta,src);
42507: }}}}}}endlabel2544: ;
42508: return 20;
42509: }
42510: unsigned long REGPARAM2 CPUFUNC(op_2120_5)(uae_u32 opcode) /* MOVE */
42511: {
42512: uae_u32 srcreg = (opcode & 7);
42513: uae_u32 dstreg = (opcode >> 9) & 7;
42514: OpcodeFamily = 30; CurrentInstrCycles = 22;
42515: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
42516: if ((srca & 1) != 0) {
42517: last_fault_for_exception_3 = srca;
42518: last_op_for_exception_3 = opcode;
42519: last_addr_for_exception_3 = m68k_getpc() + 2;
42520: Exception(3, 0, M68000_EXC_SRC_CPU);
42521: goto endlabel2545;
42522: }
42523: {{ uae_s32 src = get_long(srca);
42524: m68k_areg (regs, srcreg) = srca;
42525: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42526: if ((dsta & 1) != 0) {
42527: last_fault_for_exception_3 = dsta;
42528: last_op_for_exception_3 = opcode;
42529: last_addr_for_exception_3 = m68k_getpc() + 2;
42530: Exception(3, 0, M68000_EXC_SRC_CPU);
42531: goto endlabel2545;
42532: }
42533: { m68k_areg (regs, dstreg) = dsta;
42534: CLEAR_CZNV;
42535: SET_ZFLG (((uae_s32)(src)) == 0);
42536: SET_NFLG (((uae_s32)(src)) < 0);
42537: m68k_incpc(2);
42538: fill_prefetch_2 ();
42539: put_long(dsta,src);
42540: }}}}}}endlabel2545: ;
42541: return 22;
42542: }
42543: unsigned long REGPARAM2 CPUFUNC(op_2128_5)(uae_u32 opcode) /* MOVE */
42544: {
42545: uae_u32 srcreg = (opcode & 7);
42546: uae_u32 dstreg = (opcode >> 9) & 7;
42547: OpcodeFamily = 30; CurrentInstrCycles = 24;
42548: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
42549: if ((srca & 1) != 0) {
42550: last_fault_for_exception_3 = srca;
42551: last_op_for_exception_3 = opcode;
42552: last_addr_for_exception_3 = m68k_getpc() + 4;
42553: Exception(3, 0, M68000_EXC_SRC_CPU);
42554: goto endlabel2546;
42555: }
42556: {{ uae_s32 src = get_long(srca);
42557: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42558: if ((dsta & 1) != 0) {
42559: last_fault_for_exception_3 = dsta;
42560: last_op_for_exception_3 = opcode;
42561: last_addr_for_exception_3 = m68k_getpc() + 4;
42562: Exception(3, 0, M68000_EXC_SRC_CPU);
42563: goto endlabel2546;
42564: }
42565: { m68k_areg (regs, dstreg) = dsta;
42566: CLEAR_CZNV;
42567: SET_ZFLG (((uae_s32)(src)) == 0);
42568: SET_NFLG (((uae_s32)(src)) < 0);
42569: m68k_incpc(4);
42570: fill_prefetch_0 ();
42571: put_long(dsta,src);
42572: }}}}}}endlabel2546: ;
42573: return 24;
42574: }
42575: unsigned long REGPARAM2 CPUFUNC(op_2130_5)(uae_u32 opcode) /* MOVE */
42576: {
42577: uae_u32 srcreg = (opcode & 7);
42578: uae_u32 dstreg = (opcode >> 9) & 7;
42579: OpcodeFamily = 30; CurrentInstrCycles = 26;
42580: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
42581: BusCyclePenalty += 2;
42582: if ((srca & 1) != 0) {
42583: last_fault_for_exception_3 = srca;
42584: last_op_for_exception_3 = opcode;
42585: last_addr_for_exception_3 = m68k_getpc() + 4;
42586: Exception(3, 0, M68000_EXC_SRC_CPU);
42587: goto endlabel2547;
42588: }
42589: {{ uae_s32 src = get_long(srca);
42590: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42591: if ((dsta & 1) != 0) {
42592: last_fault_for_exception_3 = dsta;
42593: last_op_for_exception_3 = opcode;
42594: last_addr_for_exception_3 = m68k_getpc() + 4;
42595: Exception(3, 0, M68000_EXC_SRC_CPU);
42596: goto endlabel2547;
42597: }
42598: { m68k_areg (regs, dstreg) = dsta;
42599: CLEAR_CZNV;
42600: SET_ZFLG (((uae_s32)(src)) == 0);
42601: SET_NFLG (((uae_s32)(src)) < 0);
42602: m68k_incpc(4);
42603: fill_prefetch_0 ();
42604: put_long(dsta,src);
42605: }}}}}}endlabel2547: ;
42606: return 26;
42607: }
42608: unsigned long REGPARAM2 CPUFUNC(op_2138_5)(uae_u32 opcode) /* MOVE */
42609: {
42610: uae_u32 dstreg = (opcode >> 9) & 7;
42611: OpcodeFamily = 30; CurrentInstrCycles = 24;
42612: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
42613: if ((srca & 1) != 0) {
42614: last_fault_for_exception_3 = srca;
42615: last_op_for_exception_3 = opcode;
42616: last_addr_for_exception_3 = m68k_getpc() + 4;
42617: Exception(3, 0, M68000_EXC_SRC_CPU);
42618: goto endlabel2548;
42619: }
42620: {{ uae_s32 src = get_long(srca);
42621: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42622: if ((dsta & 1) != 0) {
42623: last_fault_for_exception_3 = dsta;
42624: last_op_for_exception_3 = opcode;
42625: last_addr_for_exception_3 = m68k_getpc() + 4;
42626: Exception(3, 0, M68000_EXC_SRC_CPU);
42627: goto endlabel2548;
42628: }
42629: { m68k_areg (regs, dstreg) = dsta;
42630: CLEAR_CZNV;
42631: SET_ZFLG (((uae_s32)(src)) == 0);
42632: SET_NFLG (((uae_s32)(src)) < 0);
42633: m68k_incpc(4);
42634: fill_prefetch_0 ();
42635: put_long(dsta,src);
42636: }}}}}}endlabel2548: ;
42637: return 24;
42638: }
42639: #endif
42640:
42641: #ifdef PART_3
42642: unsigned long REGPARAM2 CPUFUNC(op_2139_5)(uae_u32 opcode) /* MOVE */
42643: {
42644: uae_u32 dstreg = (opcode >> 9) & 7;
42645: OpcodeFamily = 30; CurrentInstrCycles = 28;
42646: {{ uaecptr srca = get_ilong_prefetch(2);
42647: if ((srca & 1) != 0) {
42648: last_fault_for_exception_3 = srca;
42649: last_op_for_exception_3 = opcode;
42650: last_addr_for_exception_3 = m68k_getpc() + 6;
42651: Exception(3, 0, M68000_EXC_SRC_CPU);
42652: goto endlabel2549;
42653: }
42654: {{ uae_s32 src = get_long(srca);
42655: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42656: if ((dsta & 1) != 0) {
42657: last_fault_for_exception_3 = dsta;
42658: last_op_for_exception_3 = opcode;
42659: last_addr_for_exception_3 = m68k_getpc() + 6;
42660: Exception(3, 0, M68000_EXC_SRC_CPU);
42661: goto endlabel2549;
42662: }
42663: { m68k_areg (regs, dstreg) = dsta;
42664: CLEAR_CZNV;
42665: SET_ZFLG (((uae_s32)(src)) == 0);
42666: SET_NFLG (((uae_s32)(src)) < 0);
42667: m68k_incpc(6);
42668: fill_prefetch_0 ();
42669: put_long(dsta,src);
42670: }}}}}}endlabel2549: ;
42671: return 28;
42672: }
42673: unsigned long REGPARAM2 CPUFUNC(op_213a_5)(uae_u32 opcode) /* MOVE */
42674: {
42675: uae_u32 dstreg = (opcode >> 9) & 7;
42676: OpcodeFamily = 30; CurrentInstrCycles = 24;
42677: {{ uaecptr srca = m68k_getpc () + 2;
42678: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
42679: if ((srca & 1) != 0) {
42680: last_fault_for_exception_3 = srca;
42681: last_op_for_exception_3 = opcode;
42682: last_addr_for_exception_3 = m68k_getpc() + 4;
42683: Exception(3, 0, M68000_EXC_SRC_CPU);
42684: goto endlabel2550;
42685: }
42686: {{ uae_s32 src = get_long(srca);
42687: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42688: if ((dsta & 1) != 0) {
42689: last_fault_for_exception_3 = dsta;
42690: last_op_for_exception_3 = opcode;
42691: last_addr_for_exception_3 = m68k_getpc() + 4;
42692: Exception(3, 0, M68000_EXC_SRC_CPU);
42693: goto endlabel2550;
42694: }
42695: { m68k_areg (regs, dstreg) = dsta;
42696: CLEAR_CZNV;
42697: SET_ZFLG (((uae_s32)(src)) == 0);
42698: SET_NFLG (((uae_s32)(src)) < 0);
42699: m68k_incpc(4);
42700: fill_prefetch_0 ();
42701: put_long(dsta,src);
42702: }}}}}}endlabel2550: ;
42703: return 24;
42704: }
42705: unsigned long REGPARAM2 CPUFUNC(op_213b_5)(uae_u32 opcode) /* MOVE */
42706: {
42707: uae_u32 dstreg = (opcode >> 9) & 7;
42708: OpcodeFamily = 30; CurrentInstrCycles = 26;
42709: {{ uaecptr tmppc = m68k_getpc() + 2;
42710: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
42711: BusCyclePenalty += 2;
42712: if ((srca & 1) != 0) {
42713: last_fault_for_exception_3 = srca;
42714: last_op_for_exception_3 = opcode;
42715: last_addr_for_exception_3 = m68k_getpc() + 4;
42716: Exception(3, 0, M68000_EXC_SRC_CPU);
42717: goto endlabel2551;
42718: }
42719: {{ uae_s32 src = get_long(srca);
42720: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42721: if ((dsta & 1) != 0) {
42722: last_fault_for_exception_3 = dsta;
42723: last_op_for_exception_3 = opcode;
42724: last_addr_for_exception_3 = m68k_getpc() + 4;
42725: Exception(3, 0, M68000_EXC_SRC_CPU);
42726: goto endlabel2551;
42727: }
42728: { m68k_areg (regs, dstreg) = dsta;
42729: CLEAR_CZNV;
42730: SET_ZFLG (((uae_s32)(src)) == 0);
42731: SET_NFLG (((uae_s32)(src)) < 0);
42732: m68k_incpc(4);
42733: fill_prefetch_0 ();
42734: put_long(dsta,src);
42735: }}}}}}endlabel2551: ;
42736: return 26;
42737: }
42738: unsigned long REGPARAM2 CPUFUNC(op_213c_5)(uae_u32 opcode) /* MOVE */
42739: {
42740: uae_u32 dstreg = (opcode >> 9) & 7;
42741: OpcodeFamily = 30; CurrentInstrCycles = 20;
42742: {{ uae_s32 src = get_ilong_prefetch(2);
42743: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
42744: if ((dsta & 1) != 0) {
42745: last_fault_for_exception_3 = dsta;
42746: last_op_for_exception_3 = opcode;
42747: last_addr_for_exception_3 = m68k_getpc() + 6;
42748: Exception(3, 0, M68000_EXC_SRC_CPU);
42749: goto endlabel2552;
42750: }
42751: { m68k_areg (regs, dstreg) = dsta;
42752: CLEAR_CZNV;
42753: SET_ZFLG (((uae_s32)(src)) == 0);
42754: SET_NFLG (((uae_s32)(src)) < 0);
42755: m68k_incpc(6);
42756: fill_prefetch_0 ();
42757: put_long(dsta,src);
42758: }}}}endlabel2552: ;
42759: return 20;
42760: }
42761: unsigned long REGPARAM2 CPUFUNC(op_2140_5)(uae_u32 opcode) /* MOVE */
42762: {
42763: uae_u32 srcreg = (opcode & 7);
42764: uae_u32 dstreg = (opcode >> 9) & 7;
42765: OpcodeFamily = 30; CurrentInstrCycles = 16;
42766: {{ uae_s32 src = m68k_dreg(regs, srcreg);
42767: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
42768: if ((dsta & 1) != 0) {
42769: last_fault_for_exception_3 = dsta;
42770: last_op_for_exception_3 = opcode;
42771: last_addr_for_exception_3 = m68k_getpc() + 4;
42772: Exception(3, 0, M68000_EXC_SRC_CPU);
42773: goto endlabel2553;
42774: }
42775: { CLEAR_CZNV;
42776: SET_ZFLG (((uae_s32)(src)) == 0);
42777: SET_NFLG (((uae_s32)(src)) < 0);
42778: m68k_incpc(4);
42779: fill_prefetch_0 ();
42780: put_long(dsta,src);
42781: }}}}endlabel2553: ;
42782: return 16;
42783: }
42784: unsigned long REGPARAM2 CPUFUNC(op_2148_5)(uae_u32 opcode) /* MOVE */
42785: {
42786: uae_u32 srcreg = (opcode & 7);
42787: uae_u32 dstreg = (opcode >> 9) & 7;
42788: OpcodeFamily = 30; CurrentInstrCycles = 16;
42789: {{ uae_s32 src = m68k_areg(regs, srcreg);
42790: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
42791: if ((dsta & 1) != 0) {
42792: last_fault_for_exception_3 = dsta;
42793: last_op_for_exception_3 = opcode;
42794: last_addr_for_exception_3 = m68k_getpc() + 4;
42795: Exception(3, 0, M68000_EXC_SRC_CPU);
42796: goto endlabel2554;
42797: }
42798: { CLEAR_CZNV;
42799: SET_ZFLG (((uae_s32)(src)) == 0);
42800: SET_NFLG (((uae_s32)(src)) < 0);
42801: m68k_incpc(4);
42802: fill_prefetch_0 ();
42803: put_long(dsta,src);
42804: }}}}endlabel2554: ;
42805: return 16;
42806: }
42807: unsigned long REGPARAM2 CPUFUNC(op_2150_5)(uae_u32 opcode) /* MOVE */
42808: {
42809: uae_u32 srcreg = (opcode & 7);
42810: uae_u32 dstreg = (opcode >> 9) & 7;
42811: OpcodeFamily = 30; CurrentInstrCycles = 24;
42812: {{ uaecptr srca = m68k_areg(regs, srcreg);
42813: if ((srca & 1) != 0) {
42814: last_fault_for_exception_3 = srca;
42815: last_op_for_exception_3 = opcode;
42816: last_addr_for_exception_3 = m68k_getpc() + 2;
42817: Exception(3, 0, M68000_EXC_SRC_CPU);
42818: goto endlabel2555;
42819: }
42820: {{ uae_s32 src = get_long(srca);
42821: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
42822: if ((dsta & 1) != 0) {
42823: last_fault_for_exception_3 = dsta;
42824: last_op_for_exception_3 = opcode;
42825: last_addr_for_exception_3 = m68k_getpc() + 4;
42826: Exception(3, 0, M68000_EXC_SRC_CPU);
42827: goto endlabel2555;
42828: }
42829: { CLEAR_CZNV;
42830: SET_ZFLG (((uae_s32)(src)) == 0);
42831: SET_NFLG (((uae_s32)(src)) < 0);
42832: m68k_incpc(4);
42833: fill_prefetch_0 ();
42834: put_long(dsta,src);
42835: }}}}}}endlabel2555: ;
42836: return 24;
42837: }
42838: unsigned long REGPARAM2 CPUFUNC(op_2158_5)(uae_u32 opcode) /* MOVE */
42839: {
42840: uae_u32 srcreg = (opcode & 7);
42841: uae_u32 dstreg = (opcode >> 9) & 7;
42842: OpcodeFamily = 30; CurrentInstrCycles = 24;
42843: {{ uaecptr srca = m68k_areg(regs, srcreg);
42844: if ((srca & 1) != 0) {
42845: last_fault_for_exception_3 = srca;
42846: last_op_for_exception_3 = opcode;
42847: last_addr_for_exception_3 = m68k_getpc() + 2;
42848: Exception(3, 0, M68000_EXC_SRC_CPU);
42849: goto endlabel2556;
42850: }
42851: {{ uae_s32 src = get_long(srca);
42852: m68k_areg(regs, srcreg) += 4;
42853: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
42854: if ((dsta & 1) != 0) {
42855: last_fault_for_exception_3 = dsta;
42856: last_op_for_exception_3 = opcode;
42857: last_addr_for_exception_3 = m68k_getpc() + 4;
42858: Exception(3, 0, M68000_EXC_SRC_CPU);
42859: goto endlabel2556;
42860: }
42861: { CLEAR_CZNV;
42862: SET_ZFLG (((uae_s32)(src)) == 0);
42863: SET_NFLG (((uae_s32)(src)) < 0);
42864: m68k_incpc(4);
42865: fill_prefetch_0 ();
42866: put_long(dsta,src);
42867: }}}}}}endlabel2556: ;
42868: return 24;
42869: }
42870: unsigned long REGPARAM2 CPUFUNC(op_2160_5)(uae_u32 opcode) /* MOVE */
42871: {
42872: uae_u32 srcreg = (opcode & 7);
42873: uae_u32 dstreg = (opcode >> 9) & 7;
42874: OpcodeFamily = 30; CurrentInstrCycles = 26;
42875: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
42876: if ((srca & 1) != 0) {
42877: last_fault_for_exception_3 = srca;
42878: last_op_for_exception_3 = opcode;
42879: last_addr_for_exception_3 = m68k_getpc() + 2;
42880: Exception(3, 0, M68000_EXC_SRC_CPU);
42881: goto endlabel2557;
42882: }
42883: {{ uae_s32 src = get_long(srca);
42884: m68k_areg (regs, srcreg) = srca;
42885: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
42886: if ((dsta & 1) != 0) {
42887: last_fault_for_exception_3 = dsta;
42888: last_op_for_exception_3 = opcode;
42889: last_addr_for_exception_3 = m68k_getpc() + 4;
42890: Exception(3, 0, M68000_EXC_SRC_CPU);
42891: goto endlabel2557;
42892: }
42893: { CLEAR_CZNV;
42894: SET_ZFLG (((uae_s32)(src)) == 0);
42895: SET_NFLG (((uae_s32)(src)) < 0);
42896: m68k_incpc(4);
42897: fill_prefetch_0 ();
42898: put_long(dsta,src);
42899: }}}}}}endlabel2557: ;
42900: return 26;
42901: }
42902: unsigned long REGPARAM2 CPUFUNC(op_2168_5)(uae_u32 opcode) /* MOVE */
42903: {
42904: uae_u32 srcreg = (opcode & 7);
42905: uae_u32 dstreg = (opcode >> 9) & 7;
42906: OpcodeFamily = 30; CurrentInstrCycles = 28;
42907: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
42908: if ((srca & 1) != 0) {
42909: last_fault_for_exception_3 = srca;
42910: last_op_for_exception_3 = opcode;
42911: last_addr_for_exception_3 = m68k_getpc() + 4;
42912: Exception(3, 0, M68000_EXC_SRC_CPU);
42913: goto endlabel2558;
42914: }
42915: {{ uae_s32 src = get_long(srca);
42916: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
42917: if ((dsta & 1) != 0) {
42918: last_fault_for_exception_3 = dsta;
42919: last_op_for_exception_3 = opcode;
42920: last_addr_for_exception_3 = m68k_getpc() + 6;
42921: Exception(3, 0, M68000_EXC_SRC_CPU);
42922: goto endlabel2558;
42923: }
42924: { CLEAR_CZNV;
42925: SET_ZFLG (((uae_s32)(src)) == 0);
42926: SET_NFLG (((uae_s32)(src)) < 0);
42927: m68k_incpc(6);
42928: fill_prefetch_0 ();
42929: put_long(dsta,src);
42930: }}}}}}endlabel2558: ;
42931: return 28;
42932: }
42933: unsigned long REGPARAM2 CPUFUNC(op_2170_5)(uae_u32 opcode) /* MOVE */
42934: {
42935: uae_u32 srcreg = (opcode & 7);
42936: uae_u32 dstreg = (opcode >> 9) & 7;
42937: OpcodeFamily = 30; CurrentInstrCycles = 30;
42938: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
42939: BusCyclePenalty += 2;
42940: if ((srca & 1) != 0) {
42941: last_fault_for_exception_3 = srca;
42942: last_op_for_exception_3 = opcode;
42943: last_addr_for_exception_3 = m68k_getpc() + 4;
42944: Exception(3, 0, M68000_EXC_SRC_CPU);
42945: goto endlabel2559;
42946: }
42947: {{ uae_s32 src = get_long(srca);
42948: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
42949: if ((dsta & 1) != 0) {
42950: last_fault_for_exception_3 = dsta;
42951: last_op_for_exception_3 = opcode;
42952: last_addr_for_exception_3 = m68k_getpc() + 6;
42953: Exception(3, 0, M68000_EXC_SRC_CPU);
42954: goto endlabel2559;
42955: }
42956: { CLEAR_CZNV;
42957: SET_ZFLG (((uae_s32)(src)) == 0);
42958: SET_NFLG (((uae_s32)(src)) < 0);
42959: m68k_incpc(6);
42960: fill_prefetch_0 ();
42961: put_long(dsta,src);
42962: }}}}}}endlabel2559: ;
42963: return 30;
42964: }
42965: unsigned long REGPARAM2 CPUFUNC(op_2178_5)(uae_u32 opcode) /* MOVE */
42966: {
42967: uae_u32 dstreg = (opcode >> 9) & 7;
42968: OpcodeFamily = 30; CurrentInstrCycles = 28;
42969: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
42970: if ((srca & 1) != 0) {
42971: last_fault_for_exception_3 = srca;
42972: last_op_for_exception_3 = opcode;
42973: last_addr_for_exception_3 = m68k_getpc() + 4;
42974: Exception(3, 0, M68000_EXC_SRC_CPU);
42975: goto endlabel2560;
42976: }
42977: {{ uae_s32 src = get_long(srca);
42978: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
42979: if ((dsta & 1) != 0) {
42980: last_fault_for_exception_3 = dsta;
42981: last_op_for_exception_3 = opcode;
42982: last_addr_for_exception_3 = m68k_getpc() + 6;
42983: Exception(3, 0, M68000_EXC_SRC_CPU);
42984: goto endlabel2560;
42985: }
42986: { CLEAR_CZNV;
42987: SET_ZFLG (((uae_s32)(src)) == 0);
42988: SET_NFLG (((uae_s32)(src)) < 0);
42989: m68k_incpc(6);
42990: fill_prefetch_0 ();
42991: put_long(dsta,src);
42992: }}}}}}endlabel2560: ;
42993: return 28;
42994: }
42995: unsigned long REGPARAM2 CPUFUNC(op_2179_5)(uae_u32 opcode) /* MOVE */
42996: {
42997: uae_u32 dstreg = (opcode >> 9) & 7;
42998: OpcodeFamily = 30; CurrentInstrCycles = 32;
42999: {{ uaecptr srca = get_ilong_prefetch(2);
43000: if ((srca & 1) != 0) {
43001: last_fault_for_exception_3 = srca;
43002: last_op_for_exception_3 = opcode;
43003: last_addr_for_exception_3 = m68k_getpc() + 6;
43004: Exception(3, 0, M68000_EXC_SRC_CPU);
43005: goto endlabel2561;
43006: }
43007: {{ uae_s32 src = get_long(srca);
43008: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
43009: if ((dsta & 1) != 0) {
43010: last_fault_for_exception_3 = dsta;
43011: last_op_for_exception_3 = opcode;
43012: last_addr_for_exception_3 = m68k_getpc() + 8;
43013: Exception(3, 0, M68000_EXC_SRC_CPU);
43014: goto endlabel2561;
43015: }
43016: { CLEAR_CZNV;
43017: SET_ZFLG (((uae_s32)(src)) == 0);
43018: SET_NFLG (((uae_s32)(src)) < 0);
43019: m68k_incpc(8);
43020: fill_prefetch_0 ();
43021: put_long(dsta,src);
43022: }}}}}}endlabel2561: ;
43023: return 32;
43024: }
43025: unsigned long REGPARAM2 CPUFUNC(op_217a_5)(uae_u32 opcode) /* MOVE */
43026: {
43027: uae_u32 dstreg = (opcode >> 9) & 7;
43028: OpcodeFamily = 30; CurrentInstrCycles = 28;
43029: {{ uaecptr srca = m68k_getpc () + 2;
43030: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
43031: if ((srca & 1) != 0) {
43032: last_fault_for_exception_3 = srca;
43033: last_op_for_exception_3 = opcode;
43034: last_addr_for_exception_3 = m68k_getpc() + 4;
43035: Exception(3, 0, M68000_EXC_SRC_CPU);
43036: goto endlabel2562;
43037: }
43038: {{ uae_s32 src = get_long(srca);
43039: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
43040: if ((dsta & 1) != 0) {
43041: last_fault_for_exception_3 = dsta;
43042: last_op_for_exception_3 = opcode;
43043: last_addr_for_exception_3 = m68k_getpc() + 6;
43044: Exception(3, 0, M68000_EXC_SRC_CPU);
43045: goto endlabel2562;
43046: }
43047: { CLEAR_CZNV;
43048: SET_ZFLG (((uae_s32)(src)) == 0);
43049: SET_NFLG (((uae_s32)(src)) < 0);
43050: m68k_incpc(6);
43051: fill_prefetch_0 ();
43052: put_long(dsta,src);
43053: }}}}}}endlabel2562: ;
43054: return 28;
43055: }
43056: unsigned long REGPARAM2 CPUFUNC(op_217b_5)(uae_u32 opcode) /* MOVE */
43057: {
43058: uae_u32 dstreg = (opcode >> 9) & 7;
43059: OpcodeFamily = 30; CurrentInstrCycles = 30;
43060: {{ uaecptr tmppc = m68k_getpc() + 2;
43061: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
43062: BusCyclePenalty += 2;
43063: if ((srca & 1) != 0) {
43064: last_fault_for_exception_3 = srca;
43065: last_op_for_exception_3 = opcode;
43066: last_addr_for_exception_3 = m68k_getpc() + 4;
43067: Exception(3, 0, M68000_EXC_SRC_CPU);
43068: goto endlabel2563;
43069: }
43070: {{ uae_s32 src = get_long(srca);
43071: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
43072: if ((dsta & 1) != 0) {
43073: last_fault_for_exception_3 = dsta;
43074: last_op_for_exception_3 = opcode;
43075: last_addr_for_exception_3 = m68k_getpc() + 6;
43076: Exception(3, 0, M68000_EXC_SRC_CPU);
43077: goto endlabel2563;
43078: }
43079: { CLEAR_CZNV;
43080: SET_ZFLG (((uae_s32)(src)) == 0);
43081: SET_NFLG (((uae_s32)(src)) < 0);
43082: m68k_incpc(6);
43083: fill_prefetch_0 ();
43084: put_long(dsta,src);
43085: }}}}}}endlabel2563: ;
43086: return 30;
43087: }
43088: unsigned long REGPARAM2 CPUFUNC(op_217c_5)(uae_u32 opcode) /* MOVE */
43089: {
43090: uae_u32 dstreg = (opcode >> 9) & 7;
43091: OpcodeFamily = 30; CurrentInstrCycles = 24;
43092: {{ uae_s32 src = get_ilong_prefetch(2);
43093: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
43094: if ((dsta & 1) != 0) {
43095: last_fault_for_exception_3 = dsta;
43096: last_op_for_exception_3 = opcode;
43097: last_addr_for_exception_3 = m68k_getpc() + 8;
43098: Exception(3, 0, M68000_EXC_SRC_CPU);
43099: goto endlabel2564;
43100: }
43101: { CLEAR_CZNV;
43102: SET_ZFLG (((uae_s32)(src)) == 0);
43103: SET_NFLG (((uae_s32)(src)) < 0);
43104: m68k_incpc(8);
43105: fill_prefetch_0 ();
43106: put_long(dsta,src);
43107: }}}}endlabel2564: ;
43108: return 24;
43109: }
43110: unsigned long REGPARAM2 CPUFUNC(op_2180_5)(uae_u32 opcode) /* MOVE */
43111: {
43112: uae_u32 srcreg = (opcode & 7);
43113: uae_u32 dstreg = (opcode >> 9) & 7;
43114: OpcodeFamily = 30; CurrentInstrCycles = 18;
43115: {{ uae_s32 src = m68k_dreg(regs, srcreg);
43116: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
43117: BusCyclePenalty += 2;
43118: if ((dsta & 1) != 0) {
43119: last_fault_for_exception_3 = dsta;
43120: last_op_for_exception_3 = opcode;
43121: last_addr_for_exception_3 = m68k_getpc() + 4;
43122: Exception(3, 0, M68000_EXC_SRC_CPU);
43123: goto endlabel2565;
43124: }
43125: { CLEAR_CZNV;
43126: SET_ZFLG (((uae_s32)(src)) == 0);
43127: SET_NFLG (((uae_s32)(src)) < 0);
43128: m68k_incpc(4);
43129: fill_prefetch_0 ();
43130: put_long(dsta,src);
43131: }}}}endlabel2565: ;
43132: return 18;
43133: }
43134: unsigned long REGPARAM2 CPUFUNC(op_2188_5)(uae_u32 opcode) /* MOVE */
43135: {
43136: uae_u32 srcreg = (opcode & 7);
43137: uae_u32 dstreg = (opcode >> 9) & 7;
43138: OpcodeFamily = 30; CurrentInstrCycles = 18;
43139: {{ uae_s32 src = m68k_areg(regs, srcreg);
43140: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
43141: BusCyclePenalty += 2;
43142: if ((dsta & 1) != 0) {
43143: last_fault_for_exception_3 = dsta;
43144: last_op_for_exception_3 = opcode;
43145: last_addr_for_exception_3 = m68k_getpc() + 4;
43146: Exception(3, 0, M68000_EXC_SRC_CPU);
43147: goto endlabel2566;
43148: }
43149: { CLEAR_CZNV;
43150: SET_ZFLG (((uae_s32)(src)) == 0);
43151: SET_NFLG (((uae_s32)(src)) < 0);
43152: m68k_incpc(4);
43153: fill_prefetch_0 ();
43154: put_long(dsta,src);
43155: }}}}endlabel2566: ;
43156: return 18;
43157: }
43158: unsigned long REGPARAM2 CPUFUNC(op_2190_5)(uae_u32 opcode) /* MOVE */
43159: {
43160: uae_u32 srcreg = (opcode & 7);
43161: uae_u32 dstreg = (opcode >> 9) & 7;
43162: OpcodeFamily = 30; CurrentInstrCycles = 26;
43163: {{ uaecptr srca = m68k_areg(regs, srcreg);
43164: if ((srca & 1) != 0) {
43165: last_fault_for_exception_3 = srca;
43166: last_op_for_exception_3 = opcode;
43167: last_addr_for_exception_3 = m68k_getpc() + 2;
43168: Exception(3, 0, M68000_EXC_SRC_CPU);
43169: goto endlabel2567;
43170: }
43171: {{ uae_s32 src = get_long(srca);
43172: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
43173: BusCyclePenalty += 2;
43174: if ((dsta & 1) != 0) {
43175: last_fault_for_exception_3 = dsta;
43176: last_op_for_exception_3 = opcode;
43177: last_addr_for_exception_3 = m68k_getpc() + 4;
43178: Exception(3, 0, M68000_EXC_SRC_CPU);
43179: goto endlabel2567;
43180: }
43181: { CLEAR_CZNV;
43182: SET_ZFLG (((uae_s32)(src)) == 0);
43183: SET_NFLG (((uae_s32)(src)) < 0);
43184: m68k_incpc(4);
43185: fill_prefetch_0 ();
43186: put_long(dsta,src);
43187: }}}}}}endlabel2567: ;
43188: return 26;
43189: }
43190: unsigned long REGPARAM2 CPUFUNC(op_2198_5)(uae_u32 opcode) /* MOVE */
43191: {
43192: uae_u32 srcreg = (opcode & 7);
43193: uae_u32 dstreg = (opcode >> 9) & 7;
43194: OpcodeFamily = 30; CurrentInstrCycles = 26;
43195: {{ uaecptr srca = m68k_areg(regs, srcreg);
43196: if ((srca & 1) != 0) {
43197: last_fault_for_exception_3 = srca;
43198: last_op_for_exception_3 = opcode;
43199: last_addr_for_exception_3 = m68k_getpc() + 2;
43200: Exception(3, 0, M68000_EXC_SRC_CPU);
43201: goto endlabel2568;
43202: }
43203: {{ uae_s32 src = get_long(srca);
43204: m68k_areg(regs, srcreg) += 4;
43205: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
43206: BusCyclePenalty += 2;
43207: if ((dsta & 1) != 0) {
43208: last_fault_for_exception_3 = dsta;
43209: last_op_for_exception_3 = opcode;
43210: last_addr_for_exception_3 = m68k_getpc() + 4;
43211: Exception(3, 0, M68000_EXC_SRC_CPU);
43212: goto endlabel2568;
43213: }
43214: { CLEAR_CZNV;
43215: SET_ZFLG (((uae_s32)(src)) == 0);
43216: SET_NFLG (((uae_s32)(src)) < 0);
43217: m68k_incpc(4);
43218: fill_prefetch_0 ();
43219: put_long(dsta,src);
43220: }}}}}}endlabel2568: ;
43221: return 26;
43222: }
43223: unsigned long REGPARAM2 CPUFUNC(op_21a0_5)(uae_u32 opcode) /* MOVE */
43224: {
43225: uae_u32 srcreg = (opcode & 7);
43226: uae_u32 dstreg = (opcode >> 9) & 7;
43227: OpcodeFamily = 30; CurrentInstrCycles = 28;
43228: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
43229: if ((srca & 1) != 0) {
43230: last_fault_for_exception_3 = srca;
43231: last_op_for_exception_3 = opcode;
43232: last_addr_for_exception_3 = m68k_getpc() + 2;
43233: Exception(3, 0, M68000_EXC_SRC_CPU);
43234: goto endlabel2569;
43235: }
43236: {{ uae_s32 src = get_long(srca);
43237: m68k_areg (regs, srcreg) = srca;
43238: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
43239: BusCyclePenalty += 2;
43240: if ((dsta & 1) != 0) {
43241: last_fault_for_exception_3 = dsta;
43242: last_op_for_exception_3 = opcode;
43243: last_addr_for_exception_3 = m68k_getpc() + 4;
43244: Exception(3, 0, M68000_EXC_SRC_CPU);
43245: goto endlabel2569;
43246: }
43247: { CLEAR_CZNV;
43248: SET_ZFLG (((uae_s32)(src)) == 0);
43249: SET_NFLG (((uae_s32)(src)) < 0);
43250: m68k_incpc(4);
43251: fill_prefetch_0 ();
43252: put_long(dsta,src);
43253: }}}}}}endlabel2569: ;
43254: return 28;
43255: }
43256: unsigned long REGPARAM2 CPUFUNC(op_21a8_5)(uae_u32 opcode) /* MOVE */
43257: {
43258: uae_u32 srcreg = (opcode & 7);
43259: uae_u32 dstreg = (opcode >> 9) & 7;
43260: OpcodeFamily = 30; CurrentInstrCycles = 30;
43261: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
43262: if ((srca & 1) != 0) {
43263: last_fault_for_exception_3 = srca;
43264: last_op_for_exception_3 = opcode;
43265: last_addr_for_exception_3 = m68k_getpc() + 4;
43266: Exception(3, 0, M68000_EXC_SRC_CPU);
43267: goto endlabel2570;
43268: }
43269: {{ uae_s32 src = get_long(srca);
43270: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
43271: BusCyclePenalty += 2;
43272: if ((dsta & 1) != 0) {
43273: last_fault_for_exception_3 = dsta;
43274: last_op_for_exception_3 = opcode;
43275: last_addr_for_exception_3 = m68k_getpc() + 6;
43276: Exception(3, 0, M68000_EXC_SRC_CPU);
43277: goto endlabel2570;
43278: }
43279: { CLEAR_CZNV;
43280: SET_ZFLG (((uae_s32)(src)) == 0);
43281: SET_NFLG (((uae_s32)(src)) < 0);
43282: m68k_incpc(6);
43283: fill_prefetch_0 ();
43284: put_long(dsta,src);
43285: }}}}}}endlabel2570: ;
43286: return 30;
43287: }
43288: unsigned long REGPARAM2 CPUFUNC(op_21b0_5)(uae_u32 opcode) /* MOVE */
43289: {
43290: uae_u32 srcreg = (opcode & 7);
43291: uae_u32 dstreg = (opcode >> 9) & 7;
43292: OpcodeFamily = 30; CurrentInstrCycles = 32;
43293: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
43294: BusCyclePenalty += 2;
43295: if ((srca & 1) != 0) {
43296: last_fault_for_exception_3 = srca;
43297: last_op_for_exception_3 = opcode;
43298: last_addr_for_exception_3 = m68k_getpc() + 4;
43299: Exception(3, 0, M68000_EXC_SRC_CPU);
43300: goto endlabel2571;
43301: }
43302: {{ uae_s32 src = get_long(srca);
43303: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
43304: BusCyclePenalty += 2;
43305: if ((dsta & 1) != 0) {
43306: last_fault_for_exception_3 = dsta;
43307: last_op_for_exception_3 = opcode;
43308: last_addr_for_exception_3 = m68k_getpc() + 6;
43309: Exception(3, 0, M68000_EXC_SRC_CPU);
43310: goto endlabel2571;
43311: }
43312: { CLEAR_CZNV;
43313: SET_ZFLG (((uae_s32)(src)) == 0);
43314: SET_NFLG (((uae_s32)(src)) < 0);
43315: m68k_incpc(6);
43316: fill_prefetch_0 ();
43317: put_long(dsta,src);
43318: }}}}}}endlabel2571: ;
43319: return 32;
43320: }
43321: unsigned long REGPARAM2 CPUFUNC(op_21b8_5)(uae_u32 opcode) /* MOVE */
43322: {
43323: uae_u32 dstreg = (opcode >> 9) & 7;
43324: OpcodeFamily = 30; CurrentInstrCycles = 30;
43325: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
43326: if ((srca & 1) != 0) {
43327: last_fault_for_exception_3 = srca;
43328: last_op_for_exception_3 = opcode;
43329: last_addr_for_exception_3 = m68k_getpc() + 4;
43330: Exception(3, 0, M68000_EXC_SRC_CPU);
43331: goto endlabel2572;
43332: }
43333: {{ uae_s32 src = get_long(srca);
43334: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
43335: BusCyclePenalty += 2;
43336: if ((dsta & 1) != 0) {
43337: last_fault_for_exception_3 = dsta;
43338: last_op_for_exception_3 = opcode;
43339: last_addr_for_exception_3 = m68k_getpc() + 6;
43340: Exception(3, 0, M68000_EXC_SRC_CPU);
43341: goto endlabel2572;
43342: }
43343: { CLEAR_CZNV;
43344: SET_ZFLG (((uae_s32)(src)) == 0);
43345: SET_NFLG (((uae_s32)(src)) < 0);
43346: m68k_incpc(6);
43347: fill_prefetch_0 ();
43348: put_long(dsta,src);
43349: }}}}}}endlabel2572: ;
43350: return 30;
43351: }
43352: unsigned long REGPARAM2 CPUFUNC(op_21b9_5)(uae_u32 opcode) /* MOVE */
43353: {
43354: uae_u32 dstreg = (opcode >> 9) & 7;
43355: OpcodeFamily = 30; CurrentInstrCycles = 34;
43356: {{ uaecptr srca = get_ilong_prefetch(2);
43357: if ((srca & 1) != 0) {
43358: last_fault_for_exception_3 = srca;
43359: last_op_for_exception_3 = opcode;
43360: last_addr_for_exception_3 = m68k_getpc() + 6;
43361: Exception(3, 0, M68000_EXC_SRC_CPU);
43362: goto endlabel2573;
43363: }
43364: {{ uae_s32 src = get_long(srca);
43365: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
43366: BusCyclePenalty += 2;
43367: if ((dsta & 1) != 0) {
43368: last_fault_for_exception_3 = dsta;
43369: last_op_for_exception_3 = opcode;
43370: last_addr_for_exception_3 = m68k_getpc() + 8;
43371: Exception(3, 0, M68000_EXC_SRC_CPU);
43372: goto endlabel2573;
43373: }
43374: { CLEAR_CZNV;
43375: SET_ZFLG (((uae_s32)(src)) == 0);
43376: SET_NFLG (((uae_s32)(src)) < 0);
43377: m68k_incpc(8);
43378: fill_prefetch_0 ();
43379: put_long(dsta,src);
43380: }}}}}}endlabel2573: ;
43381: return 34;
43382: }
43383: unsigned long REGPARAM2 CPUFUNC(op_21ba_5)(uae_u32 opcode) /* MOVE */
43384: {
43385: uae_u32 dstreg = (opcode >> 9) & 7;
43386: OpcodeFamily = 30; CurrentInstrCycles = 30;
43387: {{ uaecptr srca = m68k_getpc () + 2;
43388: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
43389: if ((srca & 1) != 0) {
43390: last_fault_for_exception_3 = srca;
43391: last_op_for_exception_3 = opcode;
43392: last_addr_for_exception_3 = m68k_getpc() + 4;
43393: Exception(3, 0, M68000_EXC_SRC_CPU);
43394: goto endlabel2574;
43395: }
43396: {{ uae_s32 src = get_long(srca);
43397: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
43398: BusCyclePenalty += 2;
43399: if ((dsta & 1) != 0) {
43400: last_fault_for_exception_3 = dsta;
43401: last_op_for_exception_3 = opcode;
43402: last_addr_for_exception_3 = m68k_getpc() + 6;
43403: Exception(3, 0, M68000_EXC_SRC_CPU);
43404: goto endlabel2574;
43405: }
43406: { CLEAR_CZNV;
43407: SET_ZFLG (((uae_s32)(src)) == 0);
43408: SET_NFLG (((uae_s32)(src)) < 0);
43409: m68k_incpc(6);
43410: fill_prefetch_0 ();
43411: put_long(dsta,src);
43412: }}}}}}endlabel2574: ;
43413: return 30;
43414: }
43415: unsigned long REGPARAM2 CPUFUNC(op_21bb_5)(uae_u32 opcode) /* MOVE */
43416: {
43417: uae_u32 dstreg = (opcode >> 9) & 7;
43418: OpcodeFamily = 30; CurrentInstrCycles = 32;
43419: {{ uaecptr tmppc = m68k_getpc() + 2;
43420: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
43421: BusCyclePenalty += 2;
43422: if ((srca & 1) != 0) {
43423: last_fault_for_exception_3 = srca;
43424: last_op_for_exception_3 = opcode;
43425: last_addr_for_exception_3 = m68k_getpc() + 4;
43426: Exception(3, 0, M68000_EXC_SRC_CPU);
43427: goto endlabel2575;
43428: }
43429: {{ uae_s32 src = get_long(srca);
43430: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
43431: BusCyclePenalty += 2;
43432: if ((dsta & 1) != 0) {
43433: last_fault_for_exception_3 = dsta;
43434: last_op_for_exception_3 = opcode;
43435: last_addr_for_exception_3 = m68k_getpc() + 6;
43436: Exception(3, 0, M68000_EXC_SRC_CPU);
43437: goto endlabel2575;
43438: }
43439: { CLEAR_CZNV;
43440: SET_ZFLG (((uae_s32)(src)) == 0);
43441: SET_NFLG (((uae_s32)(src)) < 0);
43442: m68k_incpc(6);
43443: fill_prefetch_0 ();
43444: put_long(dsta,src);
43445: }}}}}}endlabel2575: ;
43446: return 32;
43447: }
43448: unsigned long REGPARAM2 CPUFUNC(op_21bc_5)(uae_u32 opcode) /* MOVE */
43449: {
43450: uae_u32 dstreg = (opcode >> 9) & 7;
43451: OpcodeFamily = 30; CurrentInstrCycles = 26;
43452: {{ uae_s32 src = get_ilong_prefetch(2);
43453: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
43454: BusCyclePenalty += 2;
43455: if ((dsta & 1) != 0) {
43456: last_fault_for_exception_3 = dsta;
43457: last_op_for_exception_3 = opcode;
43458: last_addr_for_exception_3 = m68k_getpc() + 8;
43459: Exception(3, 0, M68000_EXC_SRC_CPU);
43460: goto endlabel2576;
43461: }
43462: { CLEAR_CZNV;
43463: SET_ZFLG (((uae_s32)(src)) == 0);
43464: SET_NFLG (((uae_s32)(src)) < 0);
43465: m68k_incpc(8);
43466: fill_prefetch_0 ();
43467: put_long(dsta,src);
43468: }}}}endlabel2576: ;
43469: return 26;
43470: }
43471: unsigned long REGPARAM2 CPUFUNC(op_21c0_5)(uae_u32 opcode) /* MOVE */
43472: {
43473: uae_u32 srcreg = (opcode & 7);
43474: OpcodeFamily = 30; CurrentInstrCycles = 16;
43475: {{ uae_s32 src = m68k_dreg(regs, srcreg);
43476: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
43477: if ((dsta & 1) != 0) {
43478: last_fault_for_exception_3 = dsta;
43479: last_op_for_exception_3 = opcode;
43480: last_addr_for_exception_3 = m68k_getpc() + 4;
43481: Exception(3, 0, M68000_EXC_SRC_CPU);
43482: goto endlabel2577;
43483: }
43484: { CLEAR_CZNV;
43485: SET_ZFLG (((uae_s32)(src)) == 0);
43486: SET_NFLG (((uae_s32)(src)) < 0);
43487: m68k_incpc(4);
43488: fill_prefetch_0 ();
43489: put_long(dsta,src);
43490: }}}}endlabel2577: ;
43491: return 16;
43492: }
43493: unsigned long REGPARAM2 CPUFUNC(op_21c8_5)(uae_u32 opcode) /* MOVE */
43494: {
43495: uae_u32 srcreg = (opcode & 7);
43496: OpcodeFamily = 30; CurrentInstrCycles = 16;
43497: {{ uae_s32 src = m68k_areg(regs, srcreg);
43498: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
43499: if ((dsta & 1) != 0) {
43500: last_fault_for_exception_3 = dsta;
43501: last_op_for_exception_3 = opcode;
43502: last_addr_for_exception_3 = m68k_getpc() + 4;
43503: Exception(3, 0, M68000_EXC_SRC_CPU);
43504: goto endlabel2578;
43505: }
43506: { CLEAR_CZNV;
43507: SET_ZFLG (((uae_s32)(src)) == 0);
43508: SET_NFLG (((uae_s32)(src)) < 0);
43509: m68k_incpc(4);
43510: fill_prefetch_0 ();
43511: put_long(dsta,src);
43512: }}}}endlabel2578: ;
43513: return 16;
43514: }
43515: unsigned long REGPARAM2 CPUFUNC(op_21d0_5)(uae_u32 opcode) /* MOVE */
43516: {
43517: uae_u32 srcreg = (opcode & 7);
43518: OpcodeFamily = 30; CurrentInstrCycles = 24;
43519: {{ uaecptr srca = m68k_areg(regs, srcreg);
43520: if ((srca & 1) != 0) {
43521: last_fault_for_exception_3 = srca;
43522: last_op_for_exception_3 = opcode;
43523: last_addr_for_exception_3 = m68k_getpc() + 2;
43524: Exception(3, 0, M68000_EXC_SRC_CPU);
43525: goto endlabel2579;
43526: }
43527: {{ uae_s32 src = get_long(srca);
43528: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
43529: if ((dsta & 1) != 0) {
43530: last_fault_for_exception_3 = dsta;
43531: last_op_for_exception_3 = opcode;
43532: last_addr_for_exception_3 = m68k_getpc() + 4;
43533: Exception(3, 0, M68000_EXC_SRC_CPU);
43534: goto endlabel2579;
43535: }
43536: { CLEAR_CZNV;
43537: SET_ZFLG (((uae_s32)(src)) == 0);
43538: SET_NFLG (((uae_s32)(src)) < 0);
43539: m68k_incpc(4);
43540: fill_prefetch_0 ();
43541: put_long(dsta,src);
43542: }}}}}}endlabel2579: ;
43543: return 24;
43544: }
43545: unsigned long REGPARAM2 CPUFUNC(op_21d8_5)(uae_u32 opcode) /* MOVE */
43546: {
43547: uae_u32 srcreg = (opcode & 7);
43548: OpcodeFamily = 30; CurrentInstrCycles = 24;
43549: {{ uaecptr srca = m68k_areg(regs, srcreg);
43550: if ((srca & 1) != 0) {
43551: last_fault_for_exception_3 = srca;
43552: last_op_for_exception_3 = opcode;
43553: last_addr_for_exception_3 = m68k_getpc() + 2;
43554: Exception(3, 0, M68000_EXC_SRC_CPU);
43555: goto endlabel2580;
43556: }
43557: {{ uae_s32 src = get_long(srca);
43558: m68k_areg(regs, srcreg) += 4;
43559: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
43560: if ((dsta & 1) != 0) {
43561: last_fault_for_exception_3 = dsta;
43562: last_op_for_exception_3 = opcode;
43563: last_addr_for_exception_3 = m68k_getpc() + 4;
43564: Exception(3, 0, M68000_EXC_SRC_CPU);
43565: goto endlabel2580;
43566: }
43567: { CLEAR_CZNV;
43568: SET_ZFLG (((uae_s32)(src)) == 0);
43569: SET_NFLG (((uae_s32)(src)) < 0);
43570: m68k_incpc(4);
43571: fill_prefetch_0 ();
43572: put_long(dsta,src);
43573: }}}}}}endlabel2580: ;
43574: return 24;
43575: }
43576: unsigned long REGPARAM2 CPUFUNC(op_21e0_5)(uae_u32 opcode) /* MOVE */
43577: {
43578: uae_u32 srcreg = (opcode & 7);
43579: OpcodeFamily = 30; CurrentInstrCycles = 26;
43580: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
43581: if ((srca & 1) != 0) {
43582: last_fault_for_exception_3 = srca;
43583: last_op_for_exception_3 = opcode;
43584: last_addr_for_exception_3 = m68k_getpc() + 2;
43585: Exception(3, 0, M68000_EXC_SRC_CPU);
43586: goto endlabel2581;
43587: }
43588: {{ uae_s32 src = get_long(srca);
43589: m68k_areg (regs, srcreg) = srca;
43590: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
43591: if ((dsta & 1) != 0) {
43592: last_fault_for_exception_3 = dsta;
43593: last_op_for_exception_3 = opcode;
43594: last_addr_for_exception_3 = m68k_getpc() + 4;
43595: Exception(3, 0, M68000_EXC_SRC_CPU);
43596: goto endlabel2581;
43597: }
43598: { CLEAR_CZNV;
43599: SET_ZFLG (((uae_s32)(src)) == 0);
43600: SET_NFLG (((uae_s32)(src)) < 0);
43601: m68k_incpc(4);
43602: fill_prefetch_0 ();
43603: put_long(dsta,src);
43604: }}}}}}endlabel2581: ;
43605: return 26;
43606: }
43607: unsigned long REGPARAM2 CPUFUNC(op_21e8_5)(uae_u32 opcode) /* MOVE */
43608: {
43609: uae_u32 srcreg = (opcode & 7);
43610: OpcodeFamily = 30; CurrentInstrCycles = 28;
43611: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
43612: if ((srca & 1) != 0) {
43613: last_fault_for_exception_3 = srca;
43614: last_op_for_exception_3 = opcode;
43615: last_addr_for_exception_3 = m68k_getpc() + 4;
43616: Exception(3, 0, M68000_EXC_SRC_CPU);
43617: goto endlabel2582;
43618: }
43619: {{ uae_s32 src = get_long(srca);
43620: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
43621: if ((dsta & 1) != 0) {
43622: last_fault_for_exception_3 = dsta;
43623: last_op_for_exception_3 = opcode;
43624: last_addr_for_exception_3 = m68k_getpc() + 6;
43625: Exception(3, 0, M68000_EXC_SRC_CPU);
43626: goto endlabel2582;
43627: }
43628: { CLEAR_CZNV;
43629: SET_ZFLG (((uae_s32)(src)) == 0);
43630: SET_NFLG (((uae_s32)(src)) < 0);
43631: m68k_incpc(6);
43632: fill_prefetch_0 ();
43633: put_long(dsta,src);
43634: }}}}}}endlabel2582: ;
43635: return 28;
43636: }
43637: unsigned long REGPARAM2 CPUFUNC(op_21f0_5)(uae_u32 opcode) /* MOVE */
43638: {
43639: uae_u32 srcreg = (opcode & 7);
43640: OpcodeFamily = 30; CurrentInstrCycles = 30;
43641: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
43642: BusCyclePenalty += 2;
43643: if ((srca & 1) != 0) {
43644: last_fault_for_exception_3 = srca;
43645: last_op_for_exception_3 = opcode;
43646: last_addr_for_exception_3 = m68k_getpc() + 4;
43647: Exception(3, 0, M68000_EXC_SRC_CPU);
43648: goto endlabel2583;
43649: }
43650: {{ uae_s32 src = get_long(srca);
43651: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
43652: if ((dsta & 1) != 0) {
43653: last_fault_for_exception_3 = dsta;
43654: last_op_for_exception_3 = opcode;
43655: last_addr_for_exception_3 = m68k_getpc() + 6;
43656: Exception(3, 0, M68000_EXC_SRC_CPU);
43657: goto endlabel2583;
43658: }
43659: { CLEAR_CZNV;
43660: SET_ZFLG (((uae_s32)(src)) == 0);
43661: SET_NFLG (((uae_s32)(src)) < 0);
43662: m68k_incpc(6);
43663: fill_prefetch_0 ();
43664: put_long(dsta,src);
43665: }}}}}}endlabel2583: ;
43666: return 30;
43667: }
43668: unsigned long REGPARAM2 CPUFUNC(op_21f8_5)(uae_u32 opcode) /* MOVE */
43669: {
43670: OpcodeFamily = 30; CurrentInstrCycles = 28;
43671: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
43672: if ((srca & 1) != 0) {
43673: last_fault_for_exception_3 = srca;
43674: last_op_for_exception_3 = opcode;
43675: last_addr_for_exception_3 = m68k_getpc() + 4;
43676: Exception(3, 0, M68000_EXC_SRC_CPU);
43677: goto endlabel2584;
43678: }
43679: {{ uae_s32 src = get_long(srca);
43680: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
43681: if ((dsta & 1) != 0) {
43682: last_fault_for_exception_3 = dsta;
43683: last_op_for_exception_3 = opcode;
43684: last_addr_for_exception_3 = m68k_getpc() + 6;
43685: Exception(3, 0, M68000_EXC_SRC_CPU);
43686: goto endlabel2584;
43687: }
43688: { CLEAR_CZNV;
43689: SET_ZFLG (((uae_s32)(src)) == 0);
43690: SET_NFLG (((uae_s32)(src)) < 0);
43691: m68k_incpc(6);
43692: fill_prefetch_0 ();
43693: put_long(dsta,src);
43694: }}}}}}endlabel2584: ;
43695: return 28;
43696: }
43697: unsigned long REGPARAM2 CPUFUNC(op_21f9_5)(uae_u32 opcode) /* MOVE */
43698: {
43699: OpcodeFamily = 30; CurrentInstrCycles = 32;
43700: {{ uaecptr srca = get_ilong_prefetch(2);
43701: if ((srca & 1) != 0) {
43702: last_fault_for_exception_3 = srca;
43703: last_op_for_exception_3 = opcode;
43704: last_addr_for_exception_3 = m68k_getpc() + 6;
43705: Exception(3, 0, M68000_EXC_SRC_CPU);
43706: goto endlabel2585;
43707: }
43708: {{ uae_s32 src = get_long(srca);
43709: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
43710: if ((dsta & 1) != 0) {
43711: last_fault_for_exception_3 = dsta;
43712: last_op_for_exception_3 = opcode;
43713: last_addr_for_exception_3 = m68k_getpc() + 8;
43714: Exception(3, 0, M68000_EXC_SRC_CPU);
43715: goto endlabel2585;
43716: }
43717: { CLEAR_CZNV;
43718: SET_ZFLG (((uae_s32)(src)) == 0);
43719: SET_NFLG (((uae_s32)(src)) < 0);
43720: m68k_incpc(8);
43721: fill_prefetch_0 ();
43722: put_long(dsta,src);
43723: }}}}}}endlabel2585: ;
43724: return 32;
43725: }
43726: unsigned long REGPARAM2 CPUFUNC(op_21fa_5)(uae_u32 opcode) /* MOVE */
43727: {
43728: OpcodeFamily = 30; CurrentInstrCycles = 28;
43729: {{ uaecptr srca = m68k_getpc () + 2;
43730: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
43731: if ((srca & 1) != 0) {
43732: last_fault_for_exception_3 = srca;
43733: last_op_for_exception_3 = opcode;
43734: last_addr_for_exception_3 = m68k_getpc() + 4;
43735: Exception(3, 0, M68000_EXC_SRC_CPU);
43736: goto endlabel2586;
43737: }
43738: {{ uae_s32 src = get_long(srca);
43739: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
43740: if ((dsta & 1) != 0) {
43741: last_fault_for_exception_3 = dsta;
43742: last_op_for_exception_3 = opcode;
43743: last_addr_for_exception_3 = m68k_getpc() + 6;
43744: Exception(3, 0, M68000_EXC_SRC_CPU);
43745: goto endlabel2586;
43746: }
43747: { CLEAR_CZNV;
43748: SET_ZFLG (((uae_s32)(src)) == 0);
43749: SET_NFLG (((uae_s32)(src)) < 0);
43750: m68k_incpc(6);
43751: fill_prefetch_0 ();
43752: put_long(dsta,src);
43753: }}}}}}endlabel2586: ;
43754: return 28;
43755: }
43756: unsigned long REGPARAM2 CPUFUNC(op_21fb_5)(uae_u32 opcode) /* MOVE */
43757: {
43758: OpcodeFamily = 30; CurrentInstrCycles = 30;
43759: {{ uaecptr tmppc = m68k_getpc() + 2;
43760: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
43761: BusCyclePenalty += 2;
43762: if ((srca & 1) != 0) {
43763: last_fault_for_exception_3 = srca;
43764: last_op_for_exception_3 = opcode;
43765: last_addr_for_exception_3 = m68k_getpc() + 4;
43766: Exception(3, 0, M68000_EXC_SRC_CPU);
43767: goto endlabel2587;
43768: }
43769: {{ uae_s32 src = get_long(srca);
43770: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
43771: if ((dsta & 1) != 0) {
43772: last_fault_for_exception_3 = dsta;
43773: last_op_for_exception_3 = opcode;
43774: last_addr_for_exception_3 = m68k_getpc() + 6;
43775: Exception(3, 0, M68000_EXC_SRC_CPU);
43776: goto endlabel2587;
43777: }
43778: { CLEAR_CZNV;
43779: SET_ZFLG (((uae_s32)(src)) == 0);
43780: SET_NFLG (((uae_s32)(src)) < 0);
43781: m68k_incpc(6);
43782: fill_prefetch_0 ();
43783: put_long(dsta,src);
43784: }}}}}}endlabel2587: ;
43785: return 30;
43786: }
43787: unsigned long REGPARAM2 CPUFUNC(op_21fc_5)(uae_u32 opcode) /* MOVE */
43788: {
43789: OpcodeFamily = 30; CurrentInstrCycles = 24;
43790: {{ uae_s32 src = get_ilong_prefetch(2);
43791: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
43792: if ((dsta & 1) != 0) {
43793: last_fault_for_exception_3 = dsta;
43794: last_op_for_exception_3 = opcode;
43795: last_addr_for_exception_3 = m68k_getpc() + 8;
43796: Exception(3, 0, M68000_EXC_SRC_CPU);
43797: goto endlabel2588;
43798: }
43799: { CLEAR_CZNV;
43800: SET_ZFLG (((uae_s32)(src)) == 0);
43801: SET_NFLG (((uae_s32)(src)) < 0);
43802: m68k_incpc(8);
43803: fill_prefetch_0 ();
43804: put_long(dsta,src);
43805: }}}}endlabel2588: ;
43806: return 24;
43807: }
43808: unsigned long REGPARAM2 CPUFUNC(op_23c0_5)(uae_u32 opcode) /* MOVE */
43809: {
43810: uae_u32 srcreg = (opcode & 7);
43811: OpcodeFamily = 30; CurrentInstrCycles = 20;
43812: {{ uae_s32 src = m68k_dreg(regs, srcreg);
43813: { uaecptr dsta = get_ilong_prefetch(2);
43814: if ((dsta & 1) != 0) {
43815: last_fault_for_exception_3 = dsta;
43816: last_op_for_exception_3 = opcode;
43817: last_addr_for_exception_3 = m68k_getpc() + 6;
43818: Exception(3, 0, M68000_EXC_SRC_CPU);
43819: goto endlabel2589;
43820: }
43821: { CLEAR_CZNV;
43822: SET_ZFLG (((uae_s32)(src)) == 0);
43823: SET_NFLG (((uae_s32)(src)) < 0);
43824: m68k_incpc(6);
43825: fill_prefetch_0 ();
43826: put_long(dsta,src);
43827: }}}}endlabel2589: ;
43828: return 20;
43829: }
43830: unsigned long REGPARAM2 CPUFUNC(op_23c8_5)(uae_u32 opcode) /* MOVE */
43831: {
43832: uae_u32 srcreg = (opcode & 7);
43833: OpcodeFamily = 30; CurrentInstrCycles = 20;
43834: {{ uae_s32 src = m68k_areg(regs, srcreg);
43835: { uaecptr dsta = get_ilong_prefetch(2);
43836: if ((dsta & 1) != 0) {
43837: last_fault_for_exception_3 = dsta;
43838: last_op_for_exception_3 = opcode;
43839: last_addr_for_exception_3 = m68k_getpc() + 6;
43840: Exception(3, 0, M68000_EXC_SRC_CPU);
43841: goto endlabel2590;
43842: }
43843: { CLEAR_CZNV;
43844: SET_ZFLG (((uae_s32)(src)) == 0);
43845: SET_NFLG (((uae_s32)(src)) < 0);
43846: m68k_incpc(6);
43847: fill_prefetch_0 ();
43848: put_long(dsta,src);
43849: }}}}endlabel2590: ;
43850: return 20;
43851: }
43852: unsigned long REGPARAM2 CPUFUNC(op_23d0_5)(uae_u32 opcode) /* MOVE */
43853: {
43854: uae_u32 srcreg = (opcode & 7);
43855: OpcodeFamily = 30; CurrentInstrCycles = 28;
43856: {{ uaecptr srca = m68k_areg(regs, srcreg);
43857: if ((srca & 1) != 0) {
43858: last_fault_for_exception_3 = srca;
43859: last_op_for_exception_3 = opcode;
43860: last_addr_for_exception_3 = m68k_getpc() + 2;
43861: Exception(3, 0, M68000_EXC_SRC_CPU);
43862: goto endlabel2591;
43863: }
43864: {{ uae_s32 src = get_long(srca);
43865: { uaecptr dsta = get_ilong_prefetch(2);
43866: if ((dsta & 1) != 0) {
43867: last_fault_for_exception_3 = dsta;
43868: last_op_for_exception_3 = opcode;
43869: last_addr_for_exception_3 = m68k_getpc() + 6;
43870: Exception(3, 0, M68000_EXC_SRC_CPU);
43871: goto endlabel2591;
43872: }
43873: { CLEAR_CZNV;
43874: SET_ZFLG (((uae_s32)(src)) == 0);
43875: SET_NFLG (((uae_s32)(src)) < 0);
43876: m68k_incpc(6);
43877: fill_prefetch_0 ();
43878: put_long(dsta,src);
43879: }}}}}}endlabel2591: ;
43880: return 28;
43881: }
43882: unsigned long REGPARAM2 CPUFUNC(op_23d8_5)(uae_u32 opcode) /* MOVE */
43883: {
43884: uae_u32 srcreg = (opcode & 7);
43885: OpcodeFamily = 30; CurrentInstrCycles = 28;
43886: {{ uaecptr srca = m68k_areg(regs, srcreg);
43887: if ((srca & 1) != 0) {
43888: last_fault_for_exception_3 = srca;
43889: last_op_for_exception_3 = opcode;
43890: last_addr_for_exception_3 = m68k_getpc() + 2;
43891: Exception(3, 0, M68000_EXC_SRC_CPU);
43892: goto endlabel2592;
43893: }
43894: {{ uae_s32 src = get_long(srca);
43895: m68k_areg(regs, srcreg) += 4;
43896: { uaecptr dsta = get_ilong_prefetch(2);
43897: if ((dsta & 1) != 0) {
43898: last_fault_for_exception_3 = dsta;
43899: last_op_for_exception_3 = opcode;
43900: last_addr_for_exception_3 = m68k_getpc() + 6;
43901: Exception(3, 0, M68000_EXC_SRC_CPU);
43902: goto endlabel2592;
43903: }
43904: { CLEAR_CZNV;
43905: SET_ZFLG (((uae_s32)(src)) == 0);
43906: SET_NFLG (((uae_s32)(src)) < 0);
43907: m68k_incpc(6);
43908: fill_prefetch_0 ();
43909: put_long(dsta,src);
43910: }}}}}}endlabel2592: ;
43911: return 28;
43912: }
43913: unsigned long REGPARAM2 CPUFUNC(op_23e0_5)(uae_u32 opcode) /* MOVE */
43914: {
43915: uae_u32 srcreg = (opcode & 7);
43916: OpcodeFamily = 30; CurrentInstrCycles = 30;
43917: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
43918: if ((srca & 1) != 0) {
43919: last_fault_for_exception_3 = srca;
43920: last_op_for_exception_3 = opcode;
43921: last_addr_for_exception_3 = m68k_getpc() + 2;
43922: Exception(3, 0, M68000_EXC_SRC_CPU);
43923: goto endlabel2593;
43924: }
43925: {{ uae_s32 src = get_long(srca);
43926: m68k_areg (regs, srcreg) = srca;
43927: { uaecptr dsta = get_ilong_prefetch(2);
43928: if ((dsta & 1) != 0) {
43929: last_fault_for_exception_3 = dsta;
43930: last_op_for_exception_3 = opcode;
43931: last_addr_for_exception_3 = m68k_getpc() + 6;
43932: Exception(3, 0, M68000_EXC_SRC_CPU);
43933: goto endlabel2593;
43934: }
43935: { CLEAR_CZNV;
43936: SET_ZFLG (((uae_s32)(src)) == 0);
43937: SET_NFLG (((uae_s32)(src)) < 0);
43938: m68k_incpc(6);
43939: fill_prefetch_0 ();
43940: put_long(dsta,src);
43941: }}}}}}endlabel2593: ;
43942: return 30;
43943: }
43944: unsigned long REGPARAM2 CPUFUNC(op_23e8_5)(uae_u32 opcode) /* MOVE */
43945: {
43946: uae_u32 srcreg = (opcode & 7);
43947: OpcodeFamily = 30; CurrentInstrCycles = 32;
43948: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
43949: if ((srca & 1) != 0) {
43950: last_fault_for_exception_3 = srca;
43951: last_op_for_exception_3 = opcode;
43952: last_addr_for_exception_3 = m68k_getpc() + 4;
43953: Exception(3, 0, M68000_EXC_SRC_CPU);
43954: goto endlabel2594;
43955: }
43956: {{ uae_s32 src = get_long(srca);
43957: { uaecptr dsta = get_ilong_prefetch(4);
43958: if ((dsta & 1) != 0) {
43959: last_fault_for_exception_3 = dsta;
43960: last_op_for_exception_3 = opcode;
43961: last_addr_for_exception_3 = m68k_getpc() + 8;
43962: Exception(3, 0, M68000_EXC_SRC_CPU);
43963: goto endlabel2594;
43964: }
43965: { CLEAR_CZNV;
43966: SET_ZFLG (((uae_s32)(src)) == 0);
43967: SET_NFLG (((uae_s32)(src)) < 0);
43968: m68k_incpc(8);
43969: fill_prefetch_0 ();
43970: put_long(dsta,src);
43971: }}}}}}endlabel2594: ;
43972: return 32;
43973: }
43974: unsigned long REGPARAM2 CPUFUNC(op_23f0_5)(uae_u32 opcode) /* MOVE */
43975: {
43976: uae_u32 srcreg = (opcode & 7);
43977: OpcodeFamily = 30; CurrentInstrCycles = 34;
43978: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
43979: BusCyclePenalty += 2;
43980: if ((srca & 1) != 0) {
43981: last_fault_for_exception_3 = srca;
43982: last_op_for_exception_3 = opcode;
43983: last_addr_for_exception_3 = m68k_getpc() + 4;
43984: Exception(3, 0, M68000_EXC_SRC_CPU);
43985: goto endlabel2595;
43986: }
43987: {{ uae_s32 src = get_long(srca);
43988: { uaecptr dsta = get_ilong_prefetch(4);
43989: if ((dsta & 1) != 0) {
43990: last_fault_for_exception_3 = dsta;
43991: last_op_for_exception_3 = opcode;
43992: last_addr_for_exception_3 = m68k_getpc() + 8;
43993: Exception(3, 0, M68000_EXC_SRC_CPU);
43994: goto endlabel2595;
43995: }
43996: { CLEAR_CZNV;
43997: SET_ZFLG (((uae_s32)(src)) == 0);
43998: SET_NFLG (((uae_s32)(src)) < 0);
43999: m68k_incpc(8);
44000: fill_prefetch_0 ();
44001: put_long(dsta,src);
44002: }}}}}}endlabel2595: ;
44003: return 34;
44004: }
44005: unsigned long REGPARAM2 CPUFUNC(op_23f8_5)(uae_u32 opcode) /* MOVE */
44006: {
44007: OpcodeFamily = 30; CurrentInstrCycles = 32;
44008: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
44009: if ((srca & 1) != 0) {
44010: last_fault_for_exception_3 = srca;
44011: last_op_for_exception_3 = opcode;
44012: last_addr_for_exception_3 = m68k_getpc() + 4;
44013: Exception(3, 0, M68000_EXC_SRC_CPU);
44014: goto endlabel2596;
44015: }
44016: {{ uae_s32 src = get_long(srca);
44017: { uaecptr dsta = get_ilong_prefetch(4);
44018: if ((dsta & 1) != 0) {
44019: last_fault_for_exception_3 = dsta;
44020: last_op_for_exception_3 = opcode;
44021: last_addr_for_exception_3 = m68k_getpc() + 8;
44022: Exception(3, 0, M68000_EXC_SRC_CPU);
44023: goto endlabel2596;
44024: }
44025: { CLEAR_CZNV;
44026: SET_ZFLG (((uae_s32)(src)) == 0);
44027: SET_NFLG (((uae_s32)(src)) < 0);
44028: m68k_incpc(8);
44029: fill_prefetch_0 ();
44030: put_long(dsta,src);
44031: }}}}}}endlabel2596: ;
44032: return 32;
44033: }
44034: unsigned long REGPARAM2 CPUFUNC(op_23f9_5)(uae_u32 opcode) /* MOVE */
44035: {
44036: OpcodeFamily = 30; CurrentInstrCycles = 36;
44037: {{ uaecptr srca = get_ilong_prefetch(2);
44038: if ((srca & 1) != 0) {
44039: last_fault_for_exception_3 = srca;
44040: last_op_for_exception_3 = opcode;
44041: last_addr_for_exception_3 = m68k_getpc() + 6;
44042: Exception(3, 0, M68000_EXC_SRC_CPU);
44043: goto endlabel2597;
44044: }
44045: {{ uae_s32 src = get_long(srca);
44046: { uaecptr dsta = get_ilong_prefetch(6);
44047: if ((dsta & 1) != 0) {
44048: last_fault_for_exception_3 = dsta;
44049: last_op_for_exception_3 = opcode;
44050: last_addr_for_exception_3 = m68k_getpc() + 10;
44051: Exception(3, 0, M68000_EXC_SRC_CPU);
44052: goto endlabel2597;
44053: }
44054: { CLEAR_CZNV;
44055: SET_ZFLG (((uae_s32)(src)) == 0);
44056: SET_NFLG (((uae_s32)(src)) < 0);
44057: m68k_incpc(10);
44058: fill_prefetch_0 ();
44059: put_long(dsta,src);
44060: }}}}}}endlabel2597: ;
44061: return 36;
44062: }
44063: unsigned long REGPARAM2 CPUFUNC(op_23fa_5)(uae_u32 opcode) /* MOVE */
44064: {
44065: OpcodeFamily = 30; CurrentInstrCycles = 32;
44066: {{ uaecptr srca = m68k_getpc () + 2;
44067: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
44068: if ((srca & 1) != 0) {
44069: last_fault_for_exception_3 = srca;
44070: last_op_for_exception_3 = opcode;
44071: last_addr_for_exception_3 = m68k_getpc() + 4;
44072: Exception(3, 0, M68000_EXC_SRC_CPU);
44073: goto endlabel2598;
44074: }
44075: {{ uae_s32 src = get_long(srca);
44076: { uaecptr dsta = get_ilong_prefetch(4);
44077: if ((dsta & 1) != 0) {
44078: last_fault_for_exception_3 = dsta;
44079: last_op_for_exception_3 = opcode;
44080: last_addr_for_exception_3 = m68k_getpc() + 8;
44081: Exception(3, 0, M68000_EXC_SRC_CPU);
44082: goto endlabel2598;
44083: }
44084: { CLEAR_CZNV;
44085: SET_ZFLG (((uae_s32)(src)) == 0);
44086: SET_NFLG (((uae_s32)(src)) < 0);
44087: m68k_incpc(8);
44088: fill_prefetch_0 ();
44089: put_long(dsta,src);
44090: }}}}}}endlabel2598: ;
44091: return 32;
44092: }
44093: unsigned long REGPARAM2 CPUFUNC(op_23fb_5)(uae_u32 opcode) /* MOVE */
44094: {
44095: OpcodeFamily = 30; CurrentInstrCycles = 34;
44096: {{ uaecptr tmppc = m68k_getpc() + 2;
44097: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
44098: BusCyclePenalty += 2;
44099: if ((srca & 1) != 0) {
44100: last_fault_for_exception_3 = srca;
44101: last_op_for_exception_3 = opcode;
44102: last_addr_for_exception_3 = m68k_getpc() + 4;
44103: Exception(3, 0, M68000_EXC_SRC_CPU);
44104: goto endlabel2599;
44105: }
44106: {{ uae_s32 src = get_long(srca);
44107: { uaecptr dsta = get_ilong_prefetch(4);
44108: if ((dsta & 1) != 0) {
44109: last_fault_for_exception_3 = dsta;
44110: last_op_for_exception_3 = opcode;
44111: last_addr_for_exception_3 = m68k_getpc() + 8;
44112: Exception(3, 0, M68000_EXC_SRC_CPU);
44113: goto endlabel2599;
44114: }
44115: { CLEAR_CZNV;
44116: SET_ZFLG (((uae_s32)(src)) == 0);
44117: SET_NFLG (((uae_s32)(src)) < 0);
44118: m68k_incpc(8);
44119: fill_prefetch_0 ();
44120: put_long(dsta,src);
44121: }}}}}}endlabel2599: ;
44122: return 34;
44123: }
44124: unsigned long REGPARAM2 CPUFUNC(op_23fc_5)(uae_u32 opcode) /* MOVE */
44125: {
44126: OpcodeFamily = 30; CurrentInstrCycles = 28;
44127: {{ uae_s32 src = get_ilong_prefetch(2);
44128: { uaecptr dsta = get_ilong_prefetch(6);
44129: if ((dsta & 1) != 0) {
44130: last_fault_for_exception_3 = dsta;
44131: last_op_for_exception_3 = opcode;
44132: last_addr_for_exception_3 = m68k_getpc() + 10;
44133: Exception(3, 0, M68000_EXC_SRC_CPU);
44134: goto endlabel2600;
44135: }
44136: { CLEAR_CZNV;
44137: SET_ZFLG (((uae_s32)(src)) == 0);
44138: SET_NFLG (((uae_s32)(src)) < 0);
44139: m68k_incpc(10);
44140: fill_prefetch_0 ();
44141: put_long(dsta,src);
44142: }}}}endlabel2600: ;
44143: return 28;
44144: }
44145: unsigned long REGPARAM2 CPUFUNC(op_3000_5)(uae_u32 opcode) /* MOVE */
44146: {
44147: uae_u32 srcreg = (opcode & 7);
44148: uae_u32 dstreg = (opcode >> 9) & 7;
44149: OpcodeFamily = 30; CurrentInstrCycles = 4;
44150: {{ uae_s16 src = m68k_dreg(regs, srcreg);
44151: { CLEAR_CZNV;
44152: SET_ZFLG (((uae_s16)(src)) == 0);
44153: SET_NFLG (((uae_s16)(src)) < 0);
44154: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44155: }}}m68k_incpc(2);
44156: fill_prefetch_2 ();
44157: return 4;
44158: }
44159: unsigned long REGPARAM2 CPUFUNC(op_3008_5)(uae_u32 opcode) /* MOVE */
44160: {
44161: uae_u32 srcreg = (opcode & 7);
44162: uae_u32 dstreg = (opcode >> 9) & 7;
44163: OpcodeFamily = 30; CurrentInstrCycles = 4;
44164: {{ uae_s16 src = m68k_areg(regs, srcreg);
44165: { CLEAR_CZNV;
44166: SET_ZFLG (((uae_s16)(src)) == 0);
44167: SET_NFLG (((uae_s16)(src)) < 0);
44168: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44169: }}}m68k_incpc(2);
44170: fill_prefetch_2 ();
44171: return 4;
44172: }
44173: unsigned long REGPARAM2 CPUFUNC(op_3010_5)(uae_u32 opcode) /* MOVE */
44174: {
44175: uae_u32 srcreg = (opcode & 7);
44176: uae_u32 dstreg = (opcode >> 9) & 7;
44177: OpcodeFamily = 30; CurrentInstrCycles = 8;
44178: {{ uaecptr srca = m68k_areg(regs, srcreg);
44179: if ((srca & 1) != 0) {
44180: last_fault_for_exception_3 = srca;
44181: last_op_for_exception_3 = opcode;
44182: last_addr_for_exception_3 = m68k_getpc() + 2;
44183: Exception(3, 0, M68000_EXC_SRC_CPU);
44184: goto endlabel2603;
44185: }
44186: {{ uae_s16 src = get_word(srca);
44187: { CLEAR_CZNV;
44188: SET_ZFLG (((uae_s16)(src)) == 0);
44189: SET_NFLG (((uae_s16)(src)) < 0);
44190: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44191: }}}}}m68k_incpc(2);
44192: fill_prefetch_2 ();
44193: endlabel2603: ;
44194: return 8;
44195: }
44196: unsigned long REGPARAM2 CPUFUNC(op_3018_5)(uae_u32 opcode) /* MOVE */
44197: {
44198: uae_u32 srcreg = (opcode & 7);
44199: uae_u32 dstreg = (opcode >> 9) & 7;
44200: OpcodeFamily = 30; CurrentInstrCycles = 8;
44201: {{ uaecptr srca = m68k_areg(regs, srcreg);
44202: if ((srca & 1) != 0) {
44203: last_fault_for_exception_3 = srca;
44204: last_op_for_exception_3 = opcode;
44205: last_addr_for_exception_3 = m68k_getpc() + 2;
44206: Exception(3, 0, M68000_EXC_SRC_CPU);
44207: goto endlabel2604;
44208: }
44209: {{ uae_s16 src = get_word(srca);
44210: m68k_areg(regs, srcreg) += 2;
44211: { CLEAR_CZNV;
44212: SET_ZFLG (((uae_s16)(src)) == 0);
44213: SET_NFLG (((uae_s16)(src)) < 0);
44214: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44215: }}}}}m68k_incpc(2);
44216: fill_prefetch_2 ();
44217: endlabel2604: ;
44218: return 8;
44219: }
44220: unsigned long REGPARAM2 CPUFUNC(op_3020_5)(uae_u32 opcode) /* MOVE */
44221: {
44222: uae_u32 srcreg = (opcode & 7);
44223: uae_u32 dstreg = (opcode >> 9) & 7;
44224: OpcodeFamily = 30; CurrentInstrCycles = 10;
44225: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
44226: if ((srca & 1) != 0) {
44227: last_fault_for_exception_3 = srca;
44228: last_op_for_exception_3 = opcode;
44229: last_addr_for_exception_3 = m68k_getpc() + 2;
44230: Exception(3, 0, M68000_EXC_SRC_CPU);
44231: goto endlabel2605;
44232: }
44233: {{ uae_s16 src = get_word(srca);
44234: m68k_areg (regs, srcreg) = srca;
44235: { CLEAR_CZNV;
44236: SET_ZFLG (((uae_s16)(src)) == 0);
44237: SET_NFLG (((uae_s16)(src)) < 0);
44238: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44239: }}}}}m68k_incpc(2);
44240: fill_prefetch_2 ();
44241: endlabel2605: ;
44242: return 10;
44243: }
44244: unsigned long REGPARAM2 CPUFUNC(op_3028_5)(uae_u32 opcode) /* MOVE */
44245: {
44246: uae_u32 srcreg = (opcode & 7);
44247: uae_u32 dstreg = (opcode >> 9) & 7;
44248: OpcodeFamily = 30; CurrentInstrCycles = 12;
44249: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
44250: if ((srca & 1) != 0) {
44251: last_fault_for_exception_3 = srca;
44252: last_op_for_exception_3 = opcode;
44253: last_addr_for_exception_3 = m68k_getpc() + 4;
44254: Exception(3, 0, M68000_EXC_SRC_CPU);
44255: goto endlabel2606;
44256: }
44257: {{ uae_s16 src = get_word(srca);
44258: { CLEAR_CZNV;
44259: SET_ZFLG (((uae_s16)(src)) == 0);
44260: SET_NFLG (((uae_s16)(src)) < 0);
44261: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44262: }}}}}m68k_incpc(4);
44263: fill_prefetch_0 ();
44264: endlabel2606: ;
44265: return 12;
44266: }
44267: unsigned long REGPARAM2 CPUFUNC(op_3030_5)(uae_u32 opcode) /* MOVE */
44268: {
44269: uae_u32 srcreg = (opcode & 7);
44270: uae_u32 dstreg = (opcode >> 9) & 7;
44271: OpcodeFamily = 30; CurrentInstrCycles = 14;
44272: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
44273: BusCyclePenalty += 2;
44274: if ((srca & 1) != 0) {
44275: last_fault_for_exception_3 = srca;
44276: last_op_for_exception_3 = opcode;
44277: last_addr_for_exception_3 = m68k_getpc() + 4;
44278: Exception(3, 0, M68000_EXC_SRC_CPU);
44279: goto endlabel2607;
44280: }
44281: {{ uae_s16 src = get_word(srca);
44282: { CLEAR_CZNV;
44283: SET_ZFLG (((uae_s16)(src)) == 0);
44284: SET_NFLG (((uae_s16)(src)) < 0);
44285: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44286: }}}}}m68k_incpc(4);
44287: fill_prefetch_0 ();
44288: endlabel2607: ;
44289: return 14;
44290: }
44291: unsigned long REGPARAM2 CPUFUNC(op_3038_5)(uae_u32 opcode) /* MOVE */
44292: {
44293: uae_u32 dstreg = (opcode >> 9) & 7;
44294: OpcodeFamily = 30; CurrentInstrCycles = 12;
44295: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
44296: if ((srca & 1) != 0) {
44297: last_fault_for_exception_3 = srca;
44298: last_op_for_exception_3 = opcode;
44299: last_addr_for_exception_3 = m68k_getpc() + 4;
44300: Exception(3, 0, M68000_EXC_SRC_CPU);
44301: goto endlabel2608;
44302: }
44303: {{ uae_s16 src = get_word(srca);
44304: { CLEAR_CZNV;
44305: SET_ZFLG (((uae_s16)(src)) == 0);
44306: SET_NFLG (((uae_s16)(src)) < 0);
44307: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44308: }}}}}m68k_incpc(4);
44309: fill_prefetch_0 ();
44310: endlabel2608: ;
44311: return 12;
44312: }
44313: unsigned long REGPARAM2 CPUFUNC(op_3039_5)(uae_u32 opcode) /* MOVE */
44314: {
44315: uae_u32 dstreg = (opcode >> 9) & 7;
44316: OpcodeFamily = 30; CurrentInstrCycles = 16;
44317: {{ uaecptr srca = get_ilong_prefetch(2);
44318: if ((srca & 1) != 0) {
44319: last_fault_for_exception_3 = srca;
44320: last_op_for_exception_3 = opcode;
44321: last_addr_for_exception_3 = m68k_getpc() + 6;
44322: Exception(3, 0, M68000_EXC_SRC_CPU);
44323: goto endlabel2609;
44324: }
44325: {{ uae_s16 src = get_word(srca);
44326: { CLEAR_CZNV;
44327: SET_ZFLG (((uae_s16)(src)) == 0);
44328: SET_NFLG (((uae_s16)(src)) < 0);
44329: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44330: }}}}}m68k_incpc(6);
44331: fill_prefetch_0 ();
44332: endlabel2609: ;
44333: return 16;
44334: }
44335: unsigned long REGPARAM2 CPUFUNC(op_303a_5)(uae_u32 opcode) /* MOVE */
44336: {
44337: uae_u32 dstreg = (opcode >> 9) & 7;
44338: OpcodeFamily = 30; CurrentInstrCycles = 12;
44339: {{ uaecptr srca = m68k_getpc () + 2;
44340: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
44341: if ((srca & 1) != 0) {
44342: last_fault_for_exception_3 = srca;
44343: last_op_for_exception_3 = opcode;
44344: last_addr_for_exception_3 = m68k_getpc() + 4;
44345: Exception(3, 0, M68000_EXC_SRC_CPU);
44346: goto endlabel2610;
44347: }
44348: {{ uae_s16 src = get_word(srca);
44349: { CLEAR_CZNV;
44350: SET_ZFLG (((uae_s16)(src)) == 0);
44351: SET_NFLG (((uae_s16)(src)) < 0);
44352: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44353: }}}}}m68k_incpc(4);
44354: fill_prefetch_0 ();
44355: endlabel2610: ;
44356: return 12;
44357: }
44358: unsigned long REGPARAM2 CPUFUNC(op_303b_5)(uae_u32 opcode) /* MOVE */
44359: {
44360: uae_u32 dstreg = (opcode >> 9) & 7;
44361: OpcodeFamily = 30; CurrentInstrCycles = 14;
44362: {{ uaecptr tmppc = m68k_getpc() + 2;
44363: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
44364: BusCyclePenalty += 2;
44365: if ((srca & 1) != 0) {
44366: last_fault_for_exception_3 = srca;
44367: last_op_for_exception_3 = opcode;
44368: last_addr_for_exception_3 = m68k_getpc() + 4;
44369: Exception(3, 0, M68000_EXC_SRC_CPU);
44370: goto endlabel2611;
44371: }
44372: {{ uae_s16 src = get_word(srca);
44373: { CLEAR_CZNV;
44374: SET_ZFLG (((uae_s16)(src)) == 0);
44375: SET_NFLG (((uae_s16)(src)) < 0);
44376: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44377: }}}}}m68k_incpc(4);
44378: fill_prefetch_0 ();
44379: endlabel2611: ;
44380: return 14;
44381: }
44382: unsigned long REGPARAM2 CPUFUNC(op_303c_5)(uae_u32 opcode) /* MOVE */
44383: {
44384: uae_u32 dstreg = (opcode >> 9) & 7;
44385: OpcodeFamily = 30; CurrentInstrCycles = 8;
44386: {{ uae_s16 src = get_iword_prefetch(2);
44387: { CLEAR_CZNV;
44388: SET_ZFLG (((uae_s16)(src)) == 0);
44389: SET_NFLG (((uae_s16)(src)) < 0);
44390: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
44391: }}}m68k_incpc(4);
44392: fill_prefetch_0 ();
44393: return 8;
44394: }
44395: unsigned long REGPARAM2 CPUFUNC(op_3040_5)(uae_u32 opcode) /* MOVEA */
44396: {
44397: uae_u32 srcreg = (opcode & 7);
44398: uae_u32 dstreg = (opcode >> 9) & 7;
44399: OpcodeFamily = 31; CurrentInstrCycles = 4;
44400: {{ uae_s16 src = m68k_dreg(regs, srcreg);
44401: { uae_u32 val = (uae_s32)(uae_s16)src;
44402: m68k_areg(regs, dstreg) = (val);
44403: }}}m68k_incpc(2);
44404: fill_prefetch_2 ();
44405: return 4;
44406: }
44407: unsigned long REGPARAM2 CPUFUNC(op_3048_5)(uae_u32 opcode) /* MOVEA */
44408: {
44409: uae_u32 srcreg = (opcode & 7);
44410: uae_u32 dstreg = (opcode >> 9) & 7;
44411: OpcodeFamily = 31; CurrentInstrCycles = 4;
44412: {{ uae_s16 src = m68k_areg(regs, srcreg);
44413: { uae_u32 val = (uae_s32)(uae_s16)src;
44414: m68k_areg(regs, dstreg) = (val);
44415: }}}m68k_incpc(2);
44416: fill_prefetch_2 ();
44417: return 4;
44418: }
44419: unsigned long REGPARAM2 CPUFUNC(op_3050_5)(uae_u32 opcode) /* MOVEA */
44420: {
44421: uae_u32 srcreg = (opcode & 7);
44422: uae_u32 dstreg = (opcode >> 9) & 7;
44423: OpcodeFamily = 31; CurrentInstrCycles = 8;
44424: {{ uaecptr srca = m68k_areg(regs, srcreg);
44425: if ((srca & 1) != 0) {
44426: last_fault_for_exception_3 = srca;
44427: last_op_for_exception_3 = opcode;
44428: last_addr_for_exception_3 = m68k_getpc() + 2;
44429: Exception(3, 0, M68000_EXC_SRC_CPU);
44430: goto endlabel2615;
44431: }
44432: {{ uae_s16 src = get_word(srca);
44433: { uae_u32 val = (uae_s32)(uae_s16)src;
44434: m68k_areg(regs, dstreg) = (val);
44435: }}}}}m68k_incpc(2);
44436: fill_prefetch_2 ();
44437: endlabel2615: ;
44438: return 8;
44439: }
44440: unsigned long REGPARAM2 CPUFUNC(op_3058_5)(uae_u32 opcode) /* MOVEA */
44441: {
44442: uae_u32 srcreg = (opcode & 7);
44443: uae_u32 dstreg = (opcode >> 9) & 7;
44444: OpcodeFamily = 31; CurrentInstrCycles = 8;
44445: {{ uaecptr srca = m68k_areg(regs, srcreg);
44446: if ((srca & 1) != 0) {
44447: last_fault_for_exception_3 = srca;
44448: last_op_for_exception_3 = opcode;
44449: last_addr_for_exception_3 = m68k_getpc() + 2;
44450: Exception(3, 0, M68000_EXC_SRC_CPU);
44451: goto endlabel2616;
44452: }
44453: {{ uae_s16 src = get_word(srca);
44454: m68k_areg(regs, srcreg) += 2;
44455: { uae_u32 val = (uae_s32)(uae_s16)src;
44456: m68k_areg(regs, dstreg) = (val);
44457: }}}}}m68k_incpc(2);
44458: fill_prefetch_2 ();
44459: endlabel2616: ;
44460: return 8;
44461: }
44462: unsigned long REGPARAM2 CPUFUNC(op_3060_5)(uae_u32 opcode) /* MOVEA */
44463: {
44464: uae_u32 srcreg = (opcode & 7);
44465: uae_u32 dstreg = (opcode >> 9) & 7;
44466: OpcodeFamily = 31; CurrentInstrCycles = 10;
44467: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
44468: if ((srca & 1) != 0) {
44469: last_fault_for_exception_3 = srca;
44470: last_op_for_exception_3 = opcode;
44471: last_addr_for_exception_3 = m68k_getpc() + 2;
44472: Exception(3, 0, M68000_EXC_SRC_CPU);
44473: goto endlabel2617;
44474: }
44475: {{ uae_s16 src = get_word(srca);
44476: m68k_areg (regs, srcreg) = srca;
44477: { uae_u32 val = (uae_s32)(uae_s16)src;
44478: m68k_areg(regs, dstreg) = (val);
44479: }}}}}m68k_incpc(2);
44480: fill_prefetch_2 ();
44481: endlabel2617: ;
44482: return 10;
44483: }
44484: unsigned long REGPARAM2 CPUFUNC(op_3068_5)(uae_u32 opcode) /* MOVEA */
44485: {
44486: uae_u32 srcreg = (opcode & 7);
44487: uae_u32 dstreg = (opcode >> 9) & 7;
44488: OpcodeFamily = 31; CurrentInstrCycles = 12;
44489: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
44490: if ((srca & 1) != 0) {
44491: last_fault_for_exception_3 = srca;
44492: last_op_for_exception_3 = opcode;
44493: last_addr_for_exception_3 = m68k_getpc() + 4;
44494: Exception(3, 0, M68000_EXC_SRC_CPU);
44495: goto endlabel2618;
44496: }
44497: {{ uae_s16 src = get_word(srca);
44498: { uae_u32 val = (uae_s32)(uae_s16)src;
44499: m68k_areg(regs, dstreg) = (val);
44500: }}}}}m68k_incpc(4);
44501: fill_prefetch_0 ();
44502: endlabel2618: ;
44503: return 12;
44504: }
44505: unsigned long REGPARAM2 CPUFUNC(op_3070_5)(uae_u32 opcode) /* MOVEA */
44506: {
44507: uae_u32 srcreg = (opcode & 7);
44508: uae_u32 dstreg = (opcode >> 9) & 7;
44509: OpcodeFamily = 31; CurrentInstrCycles = 14;
44510: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
44511: BusCyclePenalty += 2;
44512: if ((srca & 1) != 0) {
44513: last_fault_for_exception_3 = srca;
44514: last_op_for_exception_3 = opcode;
44515: last_addr_for_exception_3 = m68k_getpc() + 4;
44516: Exception(3, 0, M68000_EXC_SRC_CPU);
44517: goto endlabel2619;
44518: }
44519: {{ uae_s16 src = get_word(srca);
44520: { uae_u32 val = (uae_s32)(uae_s16)src;
44521: m68k_areg(regs, dstreg) = (val);
44522: }}}}}m68k_incpc(4);
44523: fill_prefetch_0 ();
44524: endlabel2619: ;
44525: return 14;
44526: }
44527: unsigned long REGPARAM2 CPUFUNC(op_3078_5)(uae_u32 opcode) /* MOVEA */
44528: {
44529: uae_u32 dstreg = (opcode >> 9) & 7;
44530: OpcodeFamily = 31; CurrentInstrCycles = 12;
44531: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
44532: if ((srca & 1) != 0) {
44533: last_fault_for_exception_3 = srca;
44534: last_op_for_exception_3 = opcode;
44535: last_addr_for_exception_3 = m68k_getpc() + 4;
44536: Exception(3, 0, M68000_EXC_SRC_CPU);
44537: goto endlabel2620;
44538: }
44539: {{ uae_s16 src = get_word(srca);
44540: { uae_u32 val = (uae_s32)(uae_s16)src;
44541: m68k_areg(regs, dstreg) = (val);
44542: }}}}}m68k_incpc(4);
44543: fill_prefetch_0 ();
44544: endlabel2620: ;
44545: return 12;
44546: }
44547: unsigned long REGPARAM2 CPUFUNC(op_3079_5)(uae_u32 opcode) /* MOVEA */
44548: {
44549: uae_u32 dstreg = (opcode >> 9) & 7;
44550: OpcodeFamily = 31; CurrentInstrCycles = 16;
44551: {{ uaecptr srca = get_ilong_prefetch(2);
44552: if ((srca & 1) != 0) {
44553: last_fault_for_exception_3 = srca;
44554: last_op_for_exception_3 = opcode;
44555: last_addr_for_exception_3 = m68k_getpc() + 6;
44556: Exception(3, 0, M68000_EXC_SRC_CPU);
44557: goto endlabel2621;
44558: }
44559: {{ uae_s16 src = get_word(srca);
44560: { uae_u32 val = (uae_s32)(uae_s16)src;
44561: m68k_areg(regs, dstreg) = (val);
44562: }}}}}m68k_incpc(6);
44563: fill_prefetch_0 ();
44564: endlabel2621: ;
44565: return 16;
44566: }
44567: unsigned long REGPARAM2 CPUFUNC(op_307a_5)(uae_u32 opcode) /* MOVEA */
44568: {
44569: uae_u32 dstreg = (opcode >> 9) & 7;
44570: OpcodeFamily = 31; CurrentInstrCycles = 12;
44571: {{ uaecptr srca = m68k_getpc () + 2;
44572: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
44573: if ((srca & 1) != 0) {
44574: last_fault_for_exception_3 = srca;
44575: last_op_for_exception_3 = opcode;
44576: last_addr_for_exception_3 = m68k_getpc() + 4;
44577: Exception(3, 0, M68000_EXC_SRC_CPU);
44578: goto endlabel2622;
44579: }
44580: {{ uae_s16 src = get_word(srca);
44581: { uae_u32 val = (uae_s32)(uae_s16)src;
44582: m68k_areg(regs, dstreg) = (val);
44583: }}}}}m68k_incpc(4);
44584: fill_prefetch_0 ();
44585: endlabel2622: ;
44586: return 12;
44587: }
44588: unsigned long REGPARAM2 CPUFUNC(op_307b_5)(uae_u32 opcode) /* MOVEA */
44589: {
44590: uae_u32 dstreg = (opcode >> 9) & 7;
44591: OpcodeFamily = 31; CurrentInstrCycles = 14;
44592: {{ uaecptr tmppc = m68k_getpc() + 2;
44593: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
44594: BusCyclePenalty += 2;
44595: if ((srca & 1) != 0) {
44596: last_fault_for_exception_3 = srca;
44597: last_op_for_exception_3 = opcode;
44598: last_addr_for_exception_3 = m68k_getpc() + 4;
44599: Exception(3, 0, M68000_EXC_SRC_CPU);
44600: goto endlabel2623;
44601: }
44602: {{ uae_s16 src = get_word(srca);
44603: { uae_u32 val = (uae_s32)(uae_s16)src;
44604: m68k_areg(regs, dstreg) = (val);
44605: }}}}}m68k_incpc(4);
44606: fill_prefetch_0 ();
44607: endlabel2623: ;
44608: return 14;
44609: }
44610: unsigned long REGPARAM2 CPUFUNC(op_307c_5)(uae_u32 opcode) /* MOVEA */
44611: {
44612: uae_u32 dstreg = (opcode >> 9) & 7;
44613: OpcodeFamily = 31; CurrentInstrCycles = 8;
44614: {{ uae_s16 src = get_iword_prefetch(2);
44615: { uae_u32 val = (uae_s32)(uae_s16)src;
44616: m68k_areg(regs, dstreg) = (val);
44617: }}}m68k_incpc(4);
44618: fill_prefetch_0 ();
44619: return 8;
44620: }
44621: unsigned long REGPARAM2 CPUFUNC(op_3080_5)(uae_u32 opcode) /* MOVE */
44622: {
44623: uae_u32 srcreg = (opcode & 7);
44624: uae_u32 dstreg = (opcode >> 9) & 7;
44625: OpcodeFamily = 30; CurrentInstrCycles = 8;
44626: {{ uae_s16 src = m68k_dreg(regs, srcreg);
44627: { uaecptr dsta = m68k_areg(regs, dstreg);
44628: if ((dsta & 1) != 0) {
44629: last_fault_for_exception_3 = dsta;
44630: last_op_for_exception_3 = opcode;
44631: last_addr_for_exception_3 = m68k_getpc() + 2;
44632: Exception(3, 0, M68000_EXC_SRC_CPU);
44633: goto endlabel2625;
44634: }
44635: { CLEAR_CZNV;
44636: SET_ZFLG (((uae_s16)(src)) == 0);
44637: SET_NFLG (((uae_s16)(src)) < 0);
44638: m68k_incpc(2);
44639: fill_prefetch_2 ();
44640: put_word(dsta,src);
44641: }}}}endlabel2625: ;
44642: return 8;
44643: }
44644: unsigned long REGPARAM2 CPUFUNC(op_3088_5)(uae_u32 opcode) /* MOVE */
44645: {
44646: uae_u32 srcreg = (opcode & 7);
44647: uae_u32 dstreg = (opcode >> 9) & 7;
44648: OpcodeFamily = 30; CurrentInstrCycles = 8;
44649: {{ uae_s16 src = m68k_areg(regs, srcreg);
44650: { uaecptr dsta = m68k_areg(regs, dstreg);
44651: if ((dsta & 1) != 0) {
44652: last_fault_for_exception_3 = dsta;
44653: last_op_for_exception_3 = opcode;
44654: last_addr_for_exception_3 = m68k_getpc() + 2;
44655: Exception(3, 0, M68000_EXC_SRC_CPU);
44656: goto endlabel2626;
44657: }
44658: { CLEAR_CZNV;
44659: SET_ZFLG (((uae_s16)(src)) == 0);
44660: SET_NFLG (((uae_s16)(src)) < 0);
44661: m68k_incpc(2);
44662: fill_prefetch_2 ();
44663: put_word(dsta,src);
44664: }}}}endlabel2626: ;
44665: return 8;
44666: }
44667: unsigned long REGPARAM2 CPUFUNC(op_3090_5)(uae_u32 opcode) /* MOVE */
44668: {
44669: uae_u32 srcreg = (opcode & 7);
44670: uae_u32 dstreg = (opcode >> 9) & 7;
44671: OpcodeFamily = 30; CurrentInstrCycles = 12;
44672: {{ uaecptr srca = m68k_areg(regs, srcreg);
44673: if ((srca & 1) != 0) {
44674: last_fault_for_exception_3 = srca;
44675: last_op_for_exception_3 = opcode;
44676: last_addr_for_exception_3 = m68k_getpc() + 2;
44677: Exception(3, 0, M68000_EXC_SRC_CPU);
44678: goto endlabel2627;
44679: }
44680: {{ uae_s16 src = get_word(srca);
44681: { uaecptr dsta = m68k_areg(regs, dstreg);
44682: if ((dsta & 1) != 0) {
44683: last_fault_for_exception_3 = dsta;
44684: last_op_for_exception_3 = opcode;
44685: last_addr_for_exception_3 = m68k_getpc() + 2;
44686: Exception(3, 0, M68000_EXC_SRC_CPU);
44687: goto endlabel2627;
44688: }
44689: { CLEAR_CZNV;
44690: SET_ZFLG (((uae_s16)(src)) == 0);
44691: SET_NFLG (((uae_s16)(src)) < 0);
44692: m68k_incpc(2);
44693: fill_prefetch_2 ();
44694: put_word(dsta,src);
44695: }}}}}}endlabel2627: ;
44696: return 12;
44697: }
44698: unsigned long REGPARAM2 CPUFUNC(op_3098_5)(uae_u32 opcode) /* MOVE */
44699: {
44700: uae_u32 srcreg = (opcode & 7);
44701: uae_u32 dstreg = (opcode >> 9) & 7;
44702: OpcodeFamily = 30; CurrentInstrCycles = 12;
44703: {{ uaecptr srca = m68k_areg(regs, srcreg);
44704: if ((srca & 1) != 0) {
44705: last_fault_for_exception_3 = srca;
44706: last_op_for_exception_3 = opcode;
44707: last_addr_for_exception_3 = m68k_getpc() + 2;
44708: Exception(3, 0, M68000_EXC_SRC_CPU);
44709: goto endlabel2628;
44710: }
44711: {{ uae_s16 src = get_word(srca);
44712: m68k_areg(regs, srcreg) += 2;
44713: { uaecptr dsta = m68k_areg(regs, dstreg);
44714: if ((dsta & 1) != 0) {
44715: last_fault_for_exception_3 = dsta;
44716: last_op_for_exception_3 = opcode;
44717: last_addr_for_exception_3 = m68k_getpc() + 2;
44718: Exception(3, 0, M68000_EXC_SRC_CPU);
44719: goto endlabel2628;
44720: }
44721: { CLEAR_CZNV;
44722: SET_ZFLG (((uae_s16)(src)) == 0);
44723: SET_NFLG (((uae_s16)(src)) < 0);
44724: m68k_incpc(2);
44725: fill_prefetch_2 ();
44726: put_word(dsta,src);
44727: }}}}}}endlabel2628: ;
44728: return 12;
44729: }
44730: unsigned long REGPARAM2 CPUFUNC(op_30a0_5)(uae_u32 opcode) /* MOVE */
44731: {
44732: uae_u32 srcreg = (opcode & 7);
44733: uae_u32 dstreg = (opcode >> 9) & 7;
44734: OpcodeFamily = 30; CurrentInstrCycles = 14;
44735: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
44736: if ((srca & 1) != 0) {
44737: last_fault_for_exception_3 = srca;
44738: last_op_for_exception_3 = opcode;
44739: last_addr_for_exception_3 = m68k_getpc() + 2;
44740: Exception(3, 0, M68000_EXC_SRC_CPU);
44741: goto endlabel2629;
44742: }
44743: {{ uae_s16 src = get_word(srca);
44744: m68k_areg (regs, srcreg) = srca;
44745: { uaecptr dsta = m68k_areg(regs, dstreg);
44746: if ((dsta & 1) != 0) {
44747: last_fault_for_exception_3 = dsta;
44748: last_op_for_exception_3 = opcode;
44749: last_addr_for_exception_3 = m68k_getpc() + 2;
44750: Exception(3, 0, M68000_EXC_SRC_CPU);
44751: goto endlabel2629;
44752: }
44753: { CLEAR_CZNV;
44754: SET_ZFLG (((uae_s16)(src)) == 0);
44755: SET_NFLG (((uae_s16)(src)) < 0);
44756: m68k_incpc(2);
44757: fill_prefetch_2 ();
44758: put_word(dsta,src);
44759: }}}}}}endlabel2629: ;
44760: return 14;
44761: }
44762: unsigned long REGPARAM2 CPUFUNC(op_30a8_5)(uae_u32 opcode) /* MOVE */
44763: {
44764: uae_u32 srcreg = (opcode & 7);
44765: uae_u32 dstreg = (opcode >> 9) & 7;
44766: OpcodeFamily = 30; CurrentInstrCycles = 16;
44767: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
44768: if ((srca & 1) != 0) {
44769: last_fault_for_exception_3 = srca;
44770: last_op_for_exception_3 = opcode;
44771: last_addr_for_exception_3 = m68k_getpc() + 4;
44772: Exception(3, 0, M68000_EXC_SRC_CPU);
44773: goto endlabel2630;
44774: }
44775: {{ uae_s16 src = get_word(srca);
44776: { uaecptr dsta = m68k_areg(regs, dstreg);
44777: if ((dsta & 1) != 0) {
44778: last_fault_for_exception_3 = dsta;
44779: last_op_for_exception_3 = opcode;
44780: last_addr_for_exception_3 = m68k_getpc() + 4;
44781: Exception(3, 0, M68000_EXC_SRC_CPU);
44782: goto endlabel2630;
44783: }
44784: { CLEAR_CZNV;
44785: SET_ZFLG (((uae_s16)(src)) == 0);
44786: SET_NFLG (((uae_s16)(src)) < 0);
44787: m68k_incpc(4);
44788: fill_prefetch_0 ();
44789: put_word(dsta,src);
44790: }}}}}}endlabel2630: ;
44791: return 16;
44792: }
44793: unsigned long REGPARAM2 CPUFUNC(op_30b0_5)(uae_u32 opcode) /* MOVE */
44794: {
44795: uae_u32 srcreg = (opcode & 7);
44796: uae_u32 dstreg = (opcode >> 9) & 7;
44797: OpcodeFamily = 30; CurrentInstrCycles = 18;
44798: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
44799: BusCyclePenalty += 2;
44800: if ((srca & 1) != 0) {
44801: last_fault_for_exception_3 = srca;
44802: last_op_for_exception_3 = opcode;
44803: last_addr_for_exception_3 = m68k_getpc() + 4;
44804: Exception(3, 0, M68000_EXC_SRC_CPU);
44805: goto endlabel2631;
44806: }
44807: {{ uae_s16 src = get_word(srca);
44808: { uaecptr dsta = m68k_areg(regs, dstreg);
44809: if ((dsta & 1) != 0) {
44810: last_fault_for_exception_3 = dsta;
44811: last_op_for_exception_3 = opcode;
44812: last_addr_for_exception_3 = m68k_getpc() + 4;
44813: Exception(3, 0, M68000_EXC_SRC_CPU);
44814: goto endlabel2631;
44815: }
44816: { CLEAR_CZNV;
44817: SET_ZFLG (((uae_s16)(src)) == 0);
44818: SET_NFLG (((uae_s16)(src)) < 0);
44819: m68k_incpc(4);
44820: fill_prefetch_0 ();
44821: put_word(dsta,src);
44822: }}}}}}endlabel2631: ;
44823: return 18;
44824: }
44825: unsigned long REGPARAM2 CPUFUNC(op_30b8_5)(uae_u32 opcode) /* MOVE */
44826: {
44827: uae_u32 dstreg = (opcode >> 9) & 7;
44828: OpcodeFamily = 30; CurrentInstrCycles = 16;
44829: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
44830: if ((srca & 1) != 0) {
44831: last_fault_for_exception_3 = srca;
44832: last_op_for_exception_3 = opcode;
44833: last_addr_for_exception_3 = m68k_getpc() + 4;
44834: Exception(3, 0, M68000_EXC_SRC_CPU);
44835: goto endlabel2632;
44836: }
44837: {{ uae_s16 src = get_word(srca);
44838: { uaecptr dsta = m68k_areg(regs, dstreg);
44839: if ((dsta & 1) != 0) {
44840: last_fault_for_exception_3 = dsta;
44841: last_op_for_exception_3 = opcode;
44842: last_addr_for_exception_3 = m68k_getpc() + 4;
44843: Exception(3, 0, M68000_EXC_SRC_CPU);
44844: goto endlabel2632;
44845: }
44846: { CLEAR_CZNV;
44847: SET_ZFLG (((uae_s16)(src)) == 0);
44848: SET_NFLG (((uae_s16)(src)) < 0);
44849: m68k_incpc(4);
44850: fill_prefetch_0 ();
44851: put_word(dsta,src);
44852: }}}}}}endlabel2632: ;
44853: return 16;
44854: }
44855: unsigned long REGPARAM2 CPUFUNC(op_30b9_5)(uae_u32 opcode) /* MOVE */
44856: {
44857: uae_u32 dstreg = (opcode >> 9) & 7;
44858: OpcodeFamily = 30; CurrentInstrCycles = 20;
44859: {{ uaecptr srca = get_ilong_prefetch(2);
44860: if ((srca & 1) != 0) {
44861: last_fault_for_exception_3 = srca;
44862: last_op_for_exception_3 = opcode;
44863: last_addr_for_exception_3 = m68k_getpc() + 6;
44864: Exception(3, 0, M68000_EXC_SRC_CPU);
44865: goto endlabel2633;
44866: }
44867: {{ uae_s16 src = get_word(srca);
44868: { uaecptr dsta = m68k_areg(regs, dstreg);
44869: if ((dsta & 1) != 0) {
44870: last_fault_for_exception_3 = dsta;
44871: last_op_for_exception_3 = opcode;
44872: last_addr_for_exception_3 = m68k_getpc() + 6;
44873: Exception(3, 0, M68000_EXC_SRC_CPU);
44874: goto endlabel2633;
44875: }
44876: { CLEAR_CZNV;
44877: SET_ZFLG (((uae_s16)(src)) == 0);
44878: SET_NFLG (((uae_s16)(src)) < 0);
44879: m68k_incpc(6);
44880: fill_prefetch_0 ();
44881: put_word(dsta,src);
44882: }}}}}}endlabel2633: ;
44883: return 20;
44884: }
44885: unsigned long REGPARAM2 CPUFUNC(op_30ba_5)(uae_u32 opcode) /* MOVE */
44886: {
44887: uae_u32 dstreg = (opcode >> 9) & 7;
44888: OpcodeFamily = 30; CurrentInstrCycles = 16;
44889: {{ uaecptr srca = m68k_getpc () + 2;
44890: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
44891: if ((srca & 1) != 0) {
44892: last_fault_for_exception_3 = srca;
44893: last_op_for_exception_3 = opcode;
44894: last_addr_for_exception_3 = m68k_getpc() + 4;
44895: Exception(3, 0, M68000_EXC_SRC_CPU);
44896: goto endlabel2634;
44897: }
44898: {{ uae_s16 src = get_word(srca);
44899: { uaecptr dsta = m68k_areg(regs, dstreg);
44900: if ((dsta & 1) != 0) {
44901: last_fault_for_exception_3 = dsta;
44902: last_op_for_exception_3 = opcode;
44903: last_addr_for_exception_3 = m68k_getpc() + 4;
44904: Exception(3, 0, M68000_EXC_SRC_CPU);
44905: goto endlabel2634;
44906: }
44907: { CLEAR_CZNV;
44908: SET_ZFLG (((uae_s16)(src)) == 0);
44909: SET_NFLG (((uae_s16)(src)) < 0);
44910: m68k_incpc(4);
44911: fill_prefetch_0 ();
44912: put_word(dsta,src);
44913: }}}}}}endlabel2634: ;
44914: return 16;
44915: }
44916: unsigned long REGPARAM2 CPUFUNC(op_30bb_5)(uae_u32 opcode) /* MOVE */
44917: {
44918: uae_u32 dstreg = (opcode >> 9) & 7;
44919: OpcodeFamily = 30; CurrentInstrCycles = 18;
44920: {{ uaecptr tmppc = m68k_getpc() + 2;
44921: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
44922: BusCyclePenalty += 2;
44923: if ((srca & 1) != 0) {
44924: last_fault_for_exception_3 = srca;
44925: last_op_for_exception_3 = opcode;
44926: last_addr_for_exception_3 = m68k_getpc() + 4;
44927: Exception(3, 0, M68000_EXC_SRC_CPU);
44928: goto endlabel2635;
44929: }
44930: {{ uae_s16 src = get_word(srca);
44931: { uaecptr dsta = m68k_areg(regs, dstreg);
44932: if ((dsta & 1) != 0) {
44933: last_fault_for_exception_3 = dsta;
44934: last_op_for_exception_3 = opcode;
44935: last_addr_for_exception_3 = m68k_getpc() + 4;
44936: Exception(3, 0, M68000_EXC_SRC_CPU);
44937: goto endlabel2635;
44938: }
44939: { CLEAR_CZNV;
44940: SET_ZFLG (((uae_s16)(src)) == 0);
44941: SET_NFLG (((uae_s16)(src)) < 0);
44942: m68k_incpc(4);
44943: fill_prefetch_0 ();
44944: put_word(dsta,src);
44945: }}}}}}endlabel2635: ;
44946: return 18;
44947: }
44948: unsigned long REGPARAM2 CPUFUNC(op_30bc_5)(uae_u32 opcode) /* MOVE */
44949: {
44950: uae_u32 dstreg = (opcode >> 9) & 7;
44951: OpcodeFamily = 30; CurrentInstrCycles = 12;
44952: {{ uae_s16 src = get_iword_prefetch(2);
44953: { uaecptr dsta = m68k_areg(regs, dstreg);
44954: if ((dsta & 1) != 0) {
44955: last_fault_for_exception_3 = dsta;
44956: last_op_for_exception_3 = opcode;
44957: last_addr_for_exception_3 = m68k_getpc() + 4;
44958: Exception(3, 0, M68000_EXC_SRC_CPU);
44959: goto endlabel2636;
44960: }
44961: { CLEAR_CZNV;
44962: SET_ZFLG (((uae_s16)(src)) == 0);
44963: SET_NFLG (((uae_s16)(src)) < 0);
44964: m68k_incpc(4);
44965: fill_prefetch_0 ();
44966: put_word(dsta,src);
44967: }}}}endlabel2636: ;
44968: return 12;
44969: }
44970: unsigned long REGPARAM2 CPUFUNC(op_30c0_5)(uae_u32 opcode) /* MOVE */
44971: {
44972: uae_u32 srcreg = (opcode & 7);
44973: uae_u32 dstreg = (opcode >> 9) & 7;
44974: OpcodeFamily = 30; CurrentInstrCycles = 8;
44975: {{ uae_s16 src = m68k_dreg(regs, srcreg);
44976: { uaecptr dsta = m68k_areg(regs, dstreg);
44977: if ((dsta & 1) != 0) {
44978: last_fault_for_exception_3 = dsta;
44979: last_op_for_exception_3 = opcode;
44980: last_addr_for_exception_3 = m68k_getpc() + 2;
44981: Exception(3, 0, M68000_EXC_SRC_CPU);
44982: goto endlabel2637;
44983: }
44984: { m68k_areg(regs, dstreg) += 2;
44985: CLEAR_CZNV;
44986: SET_ZFLG (((uae_s16)(src)) == 0);
44987: SET_NFLG (((uae_s16)(src)) < 0);
44988: m68k_incpc(2);
44989: fill_prefetch_2 ();
44990: put_word(dsta,src);
44991: }}}}endlabel2637: ;
44992: return 8;
44993: }
44994: unsigned long REGPARAM2 CPUFUNC(op_30c8_5)(uae_u32 opcode) /* MOVE */
44995: {
44996: uae_u32 srcreg = (opcode & 7);
44997: uae_u32 dstreg = (opcode >> 9) & 7;
44998: OpcodeFamily = 30; CurrentInstrCycles = 8;
44999: {{ uae_s16 src = m68k_areg(regs, srcreg);
45000: { uaecptr dsta = m68k_areg(regs, dstreg);
45001: if ((dsta & 1) != 0) {
45002: last_fault_for_exception_3 = dsta;
45003: last_op_for_exception_3 = opcode;
45004: last_addr_for_exception_3 = m68k_getpc() + 2;
45005: Exception(3, 0, M68000_EXC_SRC_CPU);
45006: goto endlabel2638;
45007: }
45008: { m68k_areg(regs, dstreg) += 2;
45009: CLEAR_CZNV;
45010: SET_ZFLG (((uae_s16)(src)) == 0);
45011: SET_NFLG (((uae_s16)(src)) < 0);
45012: m68k_incpc(2);
45013: fill_prefetch_2 ();
45014: put_word(dsta,src);
45015: }}}}endlabel2638: ;
45016: return 8;
45017: }
45018: unsigned long REGPARAM2 CPUFUNC(op_30d0_5)(uae_u32 opcode) /* MOVE */
45019: {
45020: uae_u32 srcreg = (opcode & 7);
45021: uae_u32 dstreg = (opcode >> 9) & 7;
45022: OpcodeFamily = 30; CurrentInstrCycles = 12;
45023: {{ uaecptr srca = m68k_areg(regs, srcreg);
45024: if ((srca & 1) != 0) {
45025: last_fault_for_exception_3 = srca;
45026: last_op_for_exception_3 = opcode;
45027: last_addr_for_exception_3 = m68k_getpc() + 2;
45028: Exception(3, 0, M68000_EXC_SRC_CPU);
45029: goto endlabel2639;
45030: }
45031: {{ uae_s16 src = get_word(srca);
45032: { uaecptr dsta = m68k_areg(regs, dstreg);
45033: if ((dsta & 1) != 0) {
45034: last_fault_for_exception_3 = dsta;
45035: last_op_for_exception_3 = opcode;
45036: last_addr_for_exception_3 = m68k_getpc() + 2;
45037: Exception(3, 0, M68000_EXC_SRC_CPU);
45038: goto endlabel2639;
45039: }
45040: { m68k_areg(regs, dstreg) += 2;
45041: CLEAR_CZNV;
45042: SET_ZFLG (((uae_s16)(src)) == 0);
45043: SET_NFLG (((uae_s16)(src)) < 0);
45044: m68k_incpc(2);
45045: fill_prefetch_2 ();
45046: put_word(dsta,src);
45047: }}}}}}endlabel2639: ;
45048: return 12;
45049: }
45050: unsigned long REGPARAM2 CPUFUNC(op_30d8_5)(uae_u32 opcode) /* MOVE */
45051: {
45052: uae_u32 srcreg = (opcode & 7);
45053: uae_u32 dstreg = (opcode >> 9) & 7;
45054: OpcodeFamily = 30; CurrentInstrCycles = 12;
45055: {{ uaecptr srca = m68k_areg(regs, srcreg);
45056: if ((srca & 1) != 0) {
45057: last_fault_for_exception_3 = srca;
45058: last_op_for_exception_3 = opcode;
45059: last_addr_for_exception_3 = m68k_getpc() + 2;
45060: Exception(3, 0, M68000_EXC_SRC_CPU);
45061: goto endlabel2640;
45062: }
45063: {{ uae_s16 src = get_word(srca);
45064: m68k_areg(regs, srcreg) += 2;
45065: { uaecptr dsta = m68k_areg(regs, dstreg);
45066: if ((dsta & 1) != 0) {
45067: last_fault_for_exception_3 = dsta;
45068: last_op_for_exception_3 = opcode;
45069: last_addr_for_exception_3 = m68k_getpc() + 2;
45070: Exception(3, 0, M68000_EXC_SRC_CPU);
45071: goto endlabel2640;
45072: }
45073: { m68k_areg(regs, dstreg) += 2;
45074: CLEAR_CZNV;
45075: SET_ZFLG (((uae_s16)(src)) == 0);
45076: SET_NFLG (((uae_s16)(src)) < 0);
45077: m68k_incpc(2);
45078: fill_prefetch_2 ();
45079: put_word(dsta,src);
45080: }}}}}}endlabel2640: ;
45081: return 12;
45082: }
45083: unsigned long REGPARAM2 CPUFUNC(op_30e0_5)(uae_u32 opcode) /* MOVE */
45084: {
45085: uae_u32 srcreg = (opcode & 7);
45086: uae_u32 dstreg = (opcode >> 9) & 7;
45087: OpcodeFamily = 30; CurrentInstrCycles = 14;
45088: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
45089: if ((srca & 1) != 0) {
45090: last_fault_for_exception_3 = srca;
45091: last_op_for_exception_3 = opcode;
45092: last_addr_for_exception_3 = m68k_getpc() + 2;
45093: Exception(3, 0, M68000_EXC_SRC_CPU);
45094: goto endlabel2641;
45095: }
45096: {{ uae_s16 src = get_word(srca);
45097: m68k_areg (regs, srcreg) = srca;
45098: { uaecptr dsta = m68k_areg(regs, dstreg);
45099: if ((dsta & 1) != 0) {
45100: last_fault_for_exception_3 = dsta;
45101: last_op_for_exception_3 = opcode;
45102: last_addr_for_exception_3 = m68k_getpc() + 2;
45103: Exception(3, 0, M68000_EXC_SRC_CPU);
45104: goto endlabel2641;
45105: }
45106: { m68k_areg(regs, dstreg) += 2;
45107: CLEAR_CZNV;
45108: SET_ZFLG (((uae_s16)(src)) == 0);
45109: SET_NFLG (((uae_s16)(src)) < 0);
45110: m68k_incpc(2);
45111: fill_prefetch_2 ();
45112: put_word(dsta,src);
45113: }}}}}}endlabel2641: ;
45114: return 14;
45115: }
45116: unsigned long REGPARAM2 CPUFUNC(op_30e8_5)(uae_u32 opcode) /* MOVE */
45117: {
45118: uae_u32 srcreg = (opcode & 7);
45119: uae_u32 dstreg = (opcode >> 9) & 7;
45120: OpcodeFamily = 30; CurrentInstrCycles = 16;
45121: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
45122: if ((srca & 1) != 0) {
45123: last_fault_for_exception_3 = srca;
45124: last_op_for_exception_3 = opcode;
45125: last_addr_for_exception_3 = m68k_getpc() + 4;
45126: Exception(3, 0, M68000_EXC_SRC_CPU);
45127: goto endlabel2642;
45128: }
45129: {{ uae_s16 src = get_word(srca);
45130: { uaecptr dsta = m68k_areg(regs, dstreg);
45131: if ((dsta & 1) != 0) {
45132: last_fault_for_exception_3 = dsta;
45133: last_op_for_exception_3 = opcode;
45134: last_addr_for_exception_3 = m68k_getpc() + 4;
45135: Exception(3, 0, M68000_EXC_SRC_CPU);
45136: goto endlabel2642;
45137: }
45138: { m68k_areg(regs, dstreg) += 2;
45139: CLEAR_CZNV;
45140: SET_ZFLG (((uae_s16)(src)) == 0);
45141: SET_NFLG (((uae_s16)(src)) < 0);
45142: m68k_incpc(4);
45143: fill_prefetch_0 ();
45144: put_word(dsta,src);
45145: }}}}}}endlabel2642: ;
45146: return 16;
45147: }
45148: unsigned long REGPARAM2 CPUFUNC(op_30f0_5)(uae_u32 opcode) /* MOVE */
45149: {
45150: uae_u32 srcreg = (opcode & 7);
45151: uae_u32 dstreg = (opcode >> 9) & 7;
45152: OpcodeFamily = 30; CurrentInstrCycles = 18;
45153: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
45154: BusCyclePenalty += 2;
45155: if ((srca & 1) != 0) {
45156: last_fault_for_exception_3 = srca;
45157: last_op_for_exception_3 = opcode;
45158: last_addr_for_exception_3 = m68k_getpc() + 4;
45159: Exception(3, 0, M68000_EXC_SRC_CPU);
45160: goto endlabel2643;
45161: }
45162: {{ uae_s16 src = get_word(srca);
45163: { uaecptr dsta = m68k_areg(regs, dstreg);
45164: if ((dsta & 1) != 0) {
45165: last_fault_for_exception_3 = dsta;
45166: last_op_for_exception_3 = opcode;
45167: last_addr_for_exception_3 = m68k_getpc() + 4;
45168: Exception(3, 0, M68000_EXC_SRC_CPU);
45169: goto endlabel2643;
45170: }
45171: { m68k_areg(regs, dstreg) += 2;
45172: CLEAR_CZNV;
45173: SET_ZFLG (((uae_s16)(src)) == 0);
45174: SET_NFLG (((uae_s16)(src)) < 0);
45175: m68k_incpc(4);
45176: fill_prefetch_0 ();
45177: put_word(dsta,src);
45178: }}}}}}endlabel2643: ;
45179: return 18;
45180: }
45181: unsigned long REGPARAM2 CPUFUNC(op_30f8_5)(uae_u32 opcode) /* MOVE */
45182: {
45183: uae_u32 dstreg = (opcode >> 9) & 7;
45184: OpcodeFamily = 30; CurrentInstrCycles = 16;
45185: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
45186: if ((srca & 1) != 0) {
45187: last_fault_for_exception_3 = srca;
45188: last_op_for_exception_3 = opcode;
45189: last_addr_for_exception_3 = m68k_getpc() + 4;
45190: Exception(3, 0, M68000_EXC_SRC_CPU);
45191: goto endlabel2644;
45192: }
45193: {{ uae_s16 src = get_word(srca);
45194: { uaecptr dsta = m68k_areg(regs, dstreg);
45195: if ((dsta & 1) != 0) {
45196: last_fault_for_exception_3 = dsta;
45197: last_op_for_exception_3 = opcode;
45198: last_addr_for_exception_3 = m68k_getpc() + 4;
45199: Exception(3, 0, M68000_EXC_SRC_CPU);
45200: goto endlabel2644;
45201: }
45202: { m68k_areg(regs, dstreg) += 2;
45203: CLEAR_CZNV;
45204: SET_ZFLG (((uae_s16)(src)) == 0);
45205: SET_NFLG (((uae_s16)(src)) < 0);
45206: m68k_incpc(4);
45207: fill_prefetch_0 ();
45208: put_word(dsta,src);
45209: }}}}}}endlabel2644: ;
45210: return 16;
45211: }
45212: unsigned long REGPARAM2 CPUFUNC(op_30f9_5)(uae_u32 opcode) /* MOVE */
45213: {
45214: uae_u32 dstreg = (opcode >> 9) & 7;
45215: OpcodeFamily = 30; CurrentInstrCycles = 20;
45216: {{ uaecptr srca = get_ilong_prefetch(2);
45217: if ((srca & 1) != 0) {
45218: last_fault_for_exception_3 = srca;
45219: last_op_for_exception_3 = opcode;
45220: last_addr_for_exception_3 = m68k_getpc() + 6;
45221: Exception(3, 0, M68000_EXC_SRC_CPU);
45222: goto endlabel2645;
45223: }
45224: {{ uae_s16 src = get_word(srca);
45225: { uaecptr dsta = m68k_areg(regs, dstreg);
45226: if ((dsta & 1) != 0) {
45227: last_fault_for_exception_3 = dsta;
45228: last_op_for_exception_3 = opcode;
45229: last_addr_for_exception_3 = m68k_getpc() + 6;
45230: Exception(3, 0, M68000_EXC_SRC_CPU);
45231: goto endlabel2645;
45232: }
45233: { m68k_areg(regs, dstreg) += 2;
45234: CLEAR_CZNV;
45235: SET_ZFLG (((uae_s16)(src)) == 0);
45236: SET_NFLG (((uae_s16)(src)) < 0);
45237: m68k_incpc(6);
45238: fill_prefetch_0 ();
45239: put_word(dsta,src);
45240: }}}}}}endlabel2645: ;
45241: return 20;
45242: }
45243: unsigned long REGPARAM2 CPUFUNC(op_30fa_5)(uae_u32 opcode) /* MOVE */
45244: {
45245: uae_u32 dstreg = (opcode >> 9) & 7;
45246: OpcodeFamily = 30; CurrentInstrCycles = 16;
45247: {{ uaecptr srca = m68k_getpc () + 2;
45248: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
45249: if ((srca & 1) != 0) {
45250: last_fault_for_exception_3 = srca;
45251: last_op_for_exception_3 = opcode;
45252: last_addr_for_exception_3 = m68k_getpc() + 4;
45253: Exception(3, 0, M68000_EXC_SRC_CPU);
45254: goto endlabel2646;
45255: }
45256: {{ uae_s16 src = get_word(srca);
45257: { uaecptr dsta = m68k_areg(regs, dstreg);
45258: if ((dsta & 1) != 0) {
45259: last_fault_for_exception_3 = dsta;
45260: last_op_for_exception_3 = opcode;
45261: last_addr_for_exception_3 = m68k_getpc() + 4;
45262: Exception(3, 0, M68000_EXC_SRC_CPU);
45263: goto endlabel2646;
45264: }
45265: { m68k_areg(regs, dstreg) += 2;
45266: CLEAR_CZNV;
45267: SET_ZFLG (((uae_s16)(src)) == 0);
45268: SET_NFLG (((uae_s16)(src)) < 0);
45269: m68k_incpc(4);
45270: fill_prefetch_0 ();
45271: put_word(dsta,src);
45272: }}}}}}endlabel2646: ;
45273: return 16;
45274: }
45275: unsigned long REGPARAM2 CPUFUNC(op_30fb_5)(uae_u32 opcode) /* MOVE */
45276: {
45277: uae_u32 dstreg = (opcode >> 9) & 7;
45278: OpcodeFamily = 30; CurrentInstrCycles = 18;
45279: {{ uaecptr tmppc = m68k_getpc() + 2;
45280: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
45281: BusCyclePenalty += 2;
45282: if ((srca & 1) != 0) {
45283: last_fault_for_exception_3 = srca;
45284: last_op_for_exception_3 = opcode;
45285: last_addr_for_exception_3 = m68k_getpc() + 4;
45286: Exception(3, 0, M68000_EXC_SRC_CPU);
45287: goto endlabel2647;
45288: }
45289: {{ uae_s16 src = get_word(srca);
45290: { uaecptr dsta = m68k_areg(regs, dstreg);
45291: if ((dsta & 1) != 0) {
45292: last_fault_for_exception_3 = dsta;
45293: last_op_for_exception_3 = opcode;
45294: last_addr_for_exception_3 = m68k_getpc() + 4;
45295: Exception(3, 0, M68000_EXC_SRC_CPU);
45296: goto endlabel2647;
45297: }
45298: { m68k_areg(regs, dstreg) += 2;
45299: CLEAR_CZNV;
45300: SET_ZFLG (((uae_s16)(src)) == 0);
45301: SET_NFLG (((uae_s16)(src)) < 0);
45302: m68k_incpc(4);
45303: fill_prefetch_0 ();
45304: put_word(dsta,src);
45305: }}}}}}endlabel2647: ;
45306: return 18;
45307: }
45308: unsigned long REGPARAM2 CPUFUNC(op_30fc_5)(uae_u32 opcode) /* MOVE */
45309: {
45310: uae_u32 dstreg = (opcode >> 9) & 7;
45311: OpcodeFamily = 30; CurrentInstrCycles = 12;
45312: {{ uae_s16 src = get_iword_prefetch(2);
45313: { uaecptr dsta = m68k_areg(regs, dstreg);
45314: if ((dsta & 1) != 0) {
45315: last_fault_for_exception_3 = dsta;
45316: last_op_for_exception_3 = opcode;
45317: last_addr_for_exception_3 = m68k_getpc() + 4;
45318: Exception(3, 0, M68000_EXC_SRC_CPU);
45319: goto endlabel2648;
45320: }
45321: { m68k_areg(regs, dstreg) += 2;
45322: CLEAR_CZNV;
45323: SET_ZFLG (((uae_s16)(src)) == 0);
45324: SET_NFLG (((uae_s16)(src)) < 0);
45325: m68k_incpc(4);
45326: fill_prefetch_0 ();
45327: put_word(dsta,src);
45328: }}}}endlabel2648: ;
45329: return 12;
45330: }
45331: unsigned long REGPARAM2 CPUFUNC(op_3100_5)(uae_u32 opcode) /* MOVE */
45332: {
45333: uae_u32 srcreg = (opcode & 7);
45334: uae_u32 dstreg = (opcode >> 9) & 7;
45335: OpcodeFamily = 30; CurrentInstrCycles = 8;
45336: {{ uae_s16 src = m68k_dreg(regs, srcreg);
45337: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45338: if ((dsta & 1) != 0) {
45339: last_fault_for_exception_3 = dsta;
45340: last_op_for_exception_3 = opcode;
45341: last_addr_for_exception_3 = m68k_getpc() + 2;
45342: Exception(3, 0, M68000_EXC_SRC_CPU);
45343: goto endlabel2649;
45344: }
45345: { m68k_areg (regs, dstreg) = dsta;
45346: CLEAR_CZNV;
45347: SET_ZFLG (((uae_s16)(src)) == 0);
45348: SET_NFLG (((uae_s16)(src)) < 0);
45349: m68k_incpc(2);
45350: fill_prefetch_2 ();
45351: put_word(dsta,src);
45352: }}}}endlabel2649: ;
45353: return 8;
45354: }
45355: unsigned long REGPARAM2 CPUFUNC(op_3108_5)(uae_u32 opcode) /* MOVE */
45356: {
45357: uae_u32 srcreg = (opcode & 7);
45358: uae_u32 dstreg = (opcode >> 9) & 7;
45359: OpcodeFamily = 30; CurrentInstrCycles = 8;
45360: {{ uae_s16 src = m68k_areg(regs, srcreg);
45361: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45362: if ((dsta & 1) != 0) {
45363: last_fault_for_exception_3 = dsta;
45364: last_op_for_exception_3 = opcode;
45365: last_addr_for_exception_3 = m68k_getpc() + 2;
45366: Exception(3, 0, M68000_EXC_SRC_CPU);
45367: goto endlabel2650;
45368: }
45369: { m68k_areg (regs, dstreg) = dsta;
45370: CLEAR_CZNV;
45371: SET_ZFLG (((uae_s16)(src)) == 0);
45372: SET_NFLG (((uae_s16)(src)) < 0);
45373: m68k_incpc(2);
45374: fill_prefetch_2 ();
45375: put_word(dsta,src);
45376: }}}}endlabel2650: ;
45377: return 8;
45378: }
45379: unsigned long REGPARAM2 CPUFUNC(op_3110_5)(uae_u32 opcode) /* MOVE */
45380: {
45381: uae_u32 srcreg = (opcode & 7);
45382: uae_u32 dstreg = (opcode >> 9) & 7;
45383: OpcodeFamily = 30; CurrentInstrCycles = 12;
45384: {{ uaecptr srca = m68k_areg(regs, srcreg);
45385: if ((srca & 1) != 0) {
45386: last_fault_for_exception_3 = srca;
45387: last_op_for_exception_3 = opcode;
45388: last_addr_for_exception_3 = m68k_getpc() + 2;
45389: Exception(3, 0, M68000_EXC_SRC_CPU);
45390: goto endlabel2651;
45391: }
45392: {{ uae_s16 src = get_word(srca);
45393: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45394: if ((dsta & 1) != 0) {
45395: last_fault_for_exception_3 = dsta;
45396: last_op_for_exception_3 = opcode;
45397: last_addr_for_exception_3 = m68k_getpc() + 2;
45398: Exception(3, 0, M68000_EXC_SRC_CPU);
45399: goto endlabel2651;
45400: }
45401: { m68k_areg (regs, dstreg) = dsta;
45402: CLEAR_CZNV;
45403: SET_ZFLG (((uae_s16)(src)) == 0);
45404: SET_NFLG (((uae_s16)(src)) < 0);
45405: m68k_incpc(2);
45406: fill_prefetch_2 ();
45407: put_word(dsta,src);
45408: }}}}}}endlabel2651: ;
45409: return 12;
45410: }
45411: unsigned long REGPARAM2 CPUFUNC(op_3118_5)(uae_u32 opcode) /* MOVE */
45412: {
45413: uae_u32 srcreg = (opcode & 7);
45414: uae_u32 dstreg = (opcode >> 9) & 7;
45415: OpcodeFamily = 30; CurrentInstrCycles = 12;
45416: {{ uaecptr srca = m68k_areg(regs, srcreg);
45417: if ((srca & 1) != 0) {
45418: last_fault_for_exception_3 = srca;
45419: last_op_for_exception_3 = opcode;
45420: last_addr_for_exception_3 = m68k_getpc() + 2;
45421: Exception(3, 0, M68000_EXC_SRC_CPU);
45422: goto endlabel2652;
45423: }
45424: {{ uae_s16 src = get_word(srca);
45425: m68k_areg(regs, srcreg) += 2;
45426: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45427: if ((dsta & 1) != 0) {
45428: last_fault_for_exception_3 = dsta;
45429: last_op_for_exception_3 = opcode;
45430: last_addr_for_exception_3 = m68k_getpc() + 2;
45431: Exception(3, 0, M68000_EXC_SRC_CPU);
45432: goto endlabel2652;
45433: }
45434: { m68k_areg (regs, dstreg) = dsta;
45435: CLEAR_CZNV;
45436: SET_ZFLG (((uae_s16)(src)) == 0);
45437: SET_NFLG (((uae_s16)(src)) < 0);
45438: m68k_incpc(2);
45439: fill_prefetch_2 ();
45440: put_word(dsta,src);
45441: }}}}}}endlabel2652: ;
45442: return 12;
45443: }
45444: unsigned long REGPARAM2 CPUFUNC(op_3120_5)(uae_u32 opcode) /* MOVE */
45445: {
45446: uae_u32 srcreg = (opcode & 7);
45447: uae_u32 dstreg = (opcode >> 9) & 7;
45448: OpcodeFamily = 30; CurrentInstrCycles = 14;
45449: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
45450: if ((srca & 1) != 0) {
45451: last_fault_for_exception_3 = srca;
45452: last_op_for_exception_3 = opcode;
45453: last_addr_for_exception_3 = m68k_getpc() + 2;
45454: Exception(3, 0, M68000_EXC_SRC_CPU);
45455: goto endlabel2653;
45456: }
45457: {{ uae_s16 src = get_word(srca);
45458: m68k_areg (regs, srcreg) = srca;
45459: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45460: if ((dsta & 1) != 0) {
45461: last_fault_for_exception_3 = dsta;
45462: last_op_for_exception_3 = opcode;
45463: last_addr_for_exception_3 = m68k_getpc() + 2;
45464: Exception(3, 0, M68000_EXC_SRC_CPU);
45465: goto endlabel2653;
45466: }
45467: { m68k_areg (regs, dstreg) = dsta;
45468: CLEAR_CZNV;
45469: SET_ZFLG (((uae_s16)(src)) == 0);
45470: SET_NFLG (((uae_s16)(src)) < 0);
45471: m68k_incpc(2);
45472: fill_prefetch_2 ();
45473: put_word(dsta,src);
45474: }}}}}}endlabel2653: ;
45475: return 14;
45476: }
45477: unsigned long REGPARAM2 CPUFUNC(op_3128_5)(uae_u32 opcode) /* MOVE */
45478: {
45479: uae_u32 srcreg = (opcode & 7);
45480: uae_u32 dstreg = (opcode >> 9) & 7;
45481: OpcodeFamily = 30; CurrentInstrCycles = 16;
45482: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
45483: if ((srca & 1) != 0) {
45484: last_fault_for_exception_3 = srca;
45485: last_op_for_exception_3 = opcode;
45486: last_addr_for_exception_3 = m68k_getpc() + 4;
45487: Exception(3, 0, M68000_EXC_SRC_CPU);
45488: goto endlabel2654;
45489: }
45490: {{ uae_s16 src = get_word(srca);
45491: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45492: if ((dsta & 1) != 0) {
45493: last_fault_for_exception_3 = dsta;
45494: last_op_for_exception_3 = opcode;
45495: last_addr_for_exception_3 = m68k_getpc() + 4;
45496: Exception(3, 0, M68000_EXC_SRC_CPU);
45497: goto endlabel2654;
45498: }
45499: { m68k_areg (regs, dstreg) = dsta;
45500: CLEAR_CZNV;
45501: SET_ZFLG (((uae_s16)(src)) == 0);
45502: SET_NFLG (((uae_s16)(src)) < 0);
45503: m68k_incpc(4);
45504: fill_prefetch_0 ();
45505: put_word(dsta,src);
45506: }}}}}}endlabel2654: ;
45507: return 16;
45508: }
45509: unsigned long REGPARAM2 CPUFUNC(op_3130_5)(uae_u32 opcode) /* MOVE */
45510: {
45511: uae_u32 srcreg = (opcode & 7);
45512: uae_u32 dstreg = (opcode >> 9) & 7;
45513: OpcodeFamily = 30; CurrentInstrCycles = 18;
45514: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
45515: BusCyclePenalty += 2;
45516: if ((srca & 1) != 0) {
45517: last_fault_for_exception_3 = srca;
45518: last_op_for_exception_3 = opcode;
45519: last_addr_for_exception_3 = m68k_getpc() + 4;
45520: Exception(3, 0, M68000_EXC_SRC_CPU);
45521: goto endlabel2655;
45522: }
45523: {{ uae_s16 src = get_word(srca);
45524: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45525: if ((dsta & 1) != 0) {
45526: last_fault_for_exception_3 = dsta;
45527: last_op_for_exception_3 = opcode;
45528: last_addr_for_exception_3 = m68k_getpc() + 4;
45529: Exception(3, 0, M68000_EXC_SRC_CPU);
45530: goto endlabel2655;
45531: }
45532: { m68k_areg (regs, dstreg) = dsta;
45533: CLEAR_CZNV;
45534: SET_ZFLG (((uae_s16)(src)) == 0);
45535: SET_NFLG (((uae_s16)(src)) < 0);
45536: m68k_incpc(4);
45537: fill_prefetch_0 ();
45538: put_word(dsta,src);
45539: }}}}}}endlabel2655: ;
45540: return 18;
45541: }
45542: unsigned long REGPARAM2 CPUFUNC(op_3138_5)(uae_u32 opcode) /* MOVE */
45543: {
45544: uae_u32 dstreg = (opcode >> 9) & 7;
45545: OpcodeFamily = 30; CurrentInstrCycles = 16;
45546: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
45547: if ((srca & 1) != 0) {
45548: last_fault_for_exception_3 = srca;
45549: last_op_for_exception_3 = opcode;
45550: last_addr_for_exception_3 = m68k_getpc() + 4;
45551: Exception(3, 0, M68000_EXC_SRC_CPU);
45552: goto endlabel2656;
45553: }
45554: {{ uae_s16 src = get_word(srca);
45555: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45556: if ((dsta & 1) != 0) {
45557: last_fault_for_exception_3 = dsta;
45558: last_op_for_exception_3 = opcode;
45559: last_addr_for_exception_3 = m68k_getpc() + 4;
45560: Exception(3, 0, M68000_EXC_SRC_CPU);
45561: goto endlabel2656;
45562: }
45563: { m68k_areg (regs, dstreg) = dsta;
45564: CLEAR_CZNV;
45565: SET_ZFLG (((uae_s16)(src)) == 0);
45566: SET_NFLG (((uae_s16)(src)) < 0);
45567: m68k_incpc(4);
45568: fill_prefetch_0 ();
45569: put_word(dsta,src);
45570: }}}}}}endlabel2656: ;
45571: return 16;
45572: }
45573: unsigned long REGPARAM2 CPUFUNC(op_3139_5)(uae_u32 opcode) /* MOVE */
45574: {
45575: uae_u32 dstreg = (opcode >> 9) & 7;
45576: OpcodeFamily = 30; CurrentInstrCycles = 20;
45577: {{ uaecptr srca = get_ilong_prefetch(2);
45578: if ((srca & 1) != 0) {
45579: last_fault_for_exception_3 = srca;
45580: last_op_for_exception_3 = opcode;
45581: last_addr_for_exception_3 = m68k_getpc() + 6;
45582: Exception(3, 0, M68000_EXC_SRC_CPU);
45583: goto endlabel2657;
45584: }
45585: {{ uae_s16 src = get_word(srca);
45586: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45587: if ((dsta & 1) != 0) {
45588: last_fault_for_exception_3 = dsta;
45589: last_op_for_exception_3 = opcode;
45590: last_addr_for_exception_3 = m68k_getpc() + 6;
45591: Exception(3, 0, M68000_EXC_SRC_CPU);
45592: goto endlabel2657;
45593: }
45594: { m68k_areg (regs, dstreg) = dsta;
45595: CLEAR_CZNV;
45596: SET_ZFLG (((uae_s16)(src)) == 0);
45597: SET_NFLG (((uae_s16)(src)) < 0);
45598: m68k_incpc(6);
45599: fill_prefetch_0 ();
45600: put_word(dsta,src);
45601: }}}}}}endlabel2657: ;
45602: return 20;
45603: }
45604: unsigned long REGPARAM2 CPUFUNC(op_313a_5)(uae_u32 opcode) /* MOVE */
45605: {
45606: uae_u32 dstreg = (opcode >> 9) & 7;
45607: OpcodeFamily = 30; CurrentInstrCycles = 16;
45608: {{ uaecptr srca = m68k_getpc () + 2;
45609: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
45610: if ((srca & 1) != 0) {
45611: last_fault_for_exception_3 = srca;
45612: last_op_for_exception_3 = opcode;
45613: last_addr_for_exception_3 = m68k_getpc() + 4;
45614: Exception(3, 0, M68000_EXC_SRC_CPU);
45615: goto endlabel2658;
45616: }
45617: {{ uae_s16 src = get_word(srca);
45618: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45619: if ((dsta & 1) != 0) {
45620: last_fault_for_exception_3 = dsta;
45621: last_op_for_exception_3 = opcode;
45622: last_addr_for_exception_3 = m68k_getpc() + 4;
45623: Exception(3, 0, M68000_EXC_SRC_CPU);
45624: goto endlabel2658;
45625: }
45626: { m68k_areg (regs, dstreg) = dsta;
45627: CLEAR_CZNV;
45628: SET_ZFLG (((uae_s16)(src)) == 0);
45629: SET_NFLG (((uae_s16)(src)) < 0);
45630: m68k_incpc(4);
45631: fill_prefetch_0 ();
45632: put_word(dsta,src);
45633: }}}}}}endlabel2658: ;
45634: return 16;
45635: }
45636: unsigned long REGPARAM2 CPUFUNC(op_313b_5)(uae_u32 opcode) /* MOVE */
45637: {
45638: uae_u32 dstreg = (opcode >> 9) & 7;
45639: OpcodeFamily = 30; CurrentInstrCycles = 18;
45640: {{ uaecptr tmppc = m68k_getpc() + 2;
45641: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
45642: BusCyclePenalty += 2;
45643: if ((srca & 1) != 0) {
45644: last_fault_for_exception_3 = srca;
45645: last_op_for_exception_3 = opcode;
45646: last_addr_for_exception_3 = m68k_getpc() + 4;
45647: Exception(3, 0, M68000_EXC_SRC_CPU);
45648: goto endlabel2659;
45649: }
45650: {{ uae_s16 src = get_word(srca);
45651: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45652: if ((dsta & 1) != 0) {
45653: last_fault_for_exception_3 = dsta;
45654: last_op_for_exception_3 = opcode;
45655: last_addr_for_exception_3 = m68k_getpc() + 4;
45656: Exception(3, 0, M68000_EXC_SRC_CPU);
45657: goto endlabel2659;
45658: }
45659: { m68k_areg (regs, dstreg) = dsta;
45660: CLEAR_CZNV;
45661: SET_ZFLG (((uae_s16)(src)) == 0);
45662: SET_NFLG (((uae_s16)(src)) < 0);
45663: m68k_incpc(4);
45664: fill_prefetch_0 ();
45665: put_word(dsta,src);
45666: }}}}}}endlabel2659: ;
45667: return 18;
45668: }
45669: unsigned long REGPARAM2 CPUFUNC(op_313c_5)(uae_u32 opcode) /* MOVE */
45670: {
45671: uae_u32 dstreg = (opcode >> 9) & 7;
45672: OpcodeFamily = 30; CurrentInstrCycles = 12;
45673: {{ uae_s16 src = get_iword_prefetch(2);
45674: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
45675: if ((dsta & 1) != 0) {
45676: last_fault_for_exception_3 = dsta;
45677: last_op_for_exception_3 = opcode;
45678: last_addr_for_exception_3 = m68k_getpc() + 4;
45679: Exception(3, 0, M68000_EXC_SRC_CPU);
45680: goto endlabel2660;
45681: }
45682: { m68k_areg (regs, dstreg) = dsta;
45683: CLEAR_CZNV;
45684: SET_ZFLG (((uae_s16)(src)) == 0);
45685: SET_NFLG (((uae_s16)(src)) < 0);
45686: m68k_incpc(4);
45687: fill_prefetch_0 ();
45688: put_word(dsta,src);
45689: }}}}endlabel2660: ;
45690: return 12;
45691: }
45692: unsigned long REGPARAM2 CPUFUNC(op_3140_5)(uae_u32 opcode) /* MOVE */
45693: {
45694: uae_u32 srcreg = (opcode & 7);
45695: uae_u32 dstreg = (opcode >> 9) & 7;
45696: OpcodeFamily = 30; CurrentInstrCycles = 12;
45697: {{ uae_s16 src = m68k_dreg(regs, srcreg);
45698: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
45699: if ((dsta & 1) != 0) {
45700: last_fault_for_exception_3 = dsta;
45701: last_op_for_exception_3 = opcode;
45702: last_addr_for_exception_3 = m68k_getpc() + 4;
45703: Exception(3, 0, M68000_EXC_SRC_CPU);
45704: goto endlabel2661;
45705: }
45706: { CLEAR_CZNV;
45707: SET_ZFLG (((uae_s16)(src)) == 0);
45708: SET_NFLG (((uae_s16)(src)) < 0);
45709: m68k_incpc(4);
45710: fill_prefetch_0 ();
45711: put_word(dsta,src);
45712: }}}}endlabel2661: ;
45713: return 12;
45714: }
45715: unsigned long REGPARAM2 CPUFUNC(op_3148_5)(uae_u32 opcode) /* MOVE */
45716: {
45717: uae_u32 srcreg = (opcode & 7);
45718: uae_u32 dstreg = (opcode >> 9) & 7;
45719: OpcodeFamily = 30; CurrentInstrCycles = 12;
45720: {{ uae_s16 src = m68k_areg(regs, srcreg);
45721: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
45722: if ((dsta & 1) != 0) {
45723: last_fault_for_exception_3 = dsta;
45724: last_op_for_exception_3 = opcode;
45725: last_addr_for_exception_3 = m68k_getpc() + 4;
45726: Exception(3, 0, M68000_EXC_SRC_CPU);
45727: goto endlabel2662;
45728: }
45729: { CLEAR_CZNV;
45730: SET_ZFLG (((uae_s16)(src)) == 0);
45731: SET_NFLG (((uae_s16)(src)) < 0);
45732: m68k_incpc(4);
45733: fill_prefetch_0 ();
45734: put_word(dsta,src);
45735: }}}}endlabel2662: ;
45736: return 12;
45737: }
45738: unsigned long REGPARAM2 CPUFUNC(op_3150_5)(uae_u32 opcode) /* MOVE */
45739: {
45740: uae_u32 srcreg = (opcode & 7);
45741: uae_u32 dstreg = (opcode >> 9) & 7;
45742: OpcodeFamily = 30; CurrentInstrCycles = 16;
45743: {{ uaecptr srca = m68k_areg(regs, srcreg);
45744: if ((srca & 1) != 0) {
45745: last_fault_for_exception_3 = srca;
45746: last_op_for_exception_3 = opcode;
45747: last_addr_for_exception_3 = m68k_getpc() + 2;
45748: Exception(3, 0, M68000_EXC_SRC_CPU);
45749: goto endlabel2663;
45750: }
45751: {{ uae_s16 src = get_word(srca);
45752: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
45753: if ((dsta & 1) != 0) {
45754: last_fault_for_exception_3 = dsta;
45755: last_op_for_exception_3 = opcode;
45756: last_addr_for_exception_3 = m68k_getpc() + 4;
45757: Exception(3, 0, M68000_EXC_SRC_CPU);
45758: goto endlabel2663;
45759: }
45760: { CLEAR_CZNV;
45761: SET_ZFLG (((uae_s16)(src)) == 0);
45762: SET_NFLG (((uae_s16)(src)) < 0);
45763: m68k_incpc(4);
45764: fill_prefetch_0 ();
45765: put_word(dsta,src);
45766: }}}}}}endlabel2663: ;
45767: return 16;
45768: }
45769: unsigned long REGPARAM2 CPUFUNC(op_3158_5)(uae_u32 opcode) /* MOVE */
45770: {
45771: uae_u32 srcreg = (opcode & 7);
45772: uae_u32 dstreg = (opcode >> 9) & 7;
45773: OpcodeFamily = 30; CurrentInstrCycles = 16;
45774: {{ uaecptr srca = m68k_areg(regs, srcreg);
45775: if ((srca & 1) != 0) {
45776: last_fault_for_exception_3 = srca;
45777: last_op_for_exception_3 = opcode;
45778: last_addr_for_exception_3 = m68k_getpc() + 2;
45779: Exception(3, 0, M68000_EXC_SRC_CPU);
45780: goto endlabel2664;
45781: }
45782: {{ uae_s16 src = get_word(srca);
45783: m68k_areg(regs, srcreg) += 2;
45784: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
45785: if ((dsta & 1) != 0) {
45786: last_fault_for_exception_3 = dsta;
45787: last_op_for_exception_3 = opcode;
45788: last_addr_for_exception_3 = m68k_getpc() + 4;
45789: Exception(3, 0, M68000_EXC_SRC_CPU);
45790: goto endlabel2664;
45791: }
45792: { CLEAR_CZNV;
45793: SET_ZFLG (((uae_s16)(src)) == 0);
45794: SET_NFLG (((uae_s16)(src)) < 0);
45795: m68k_incpc(4);
45796: fill_prefetch_0 ();
45797: put_word(dsta,src);
45798: }}}}}}endlabel2664: ;
45799: return 16;
45800: }
45801: unsigned long REGPARAM2 CPUFUNC(op_3160_5)(uae_u32 opcode) /* MOVE */
45802: {
45803: uae_u32 srcreg = (opcode & 7);
45804: uae_u32 dstreg = (opcode >> 9) & 7;
45805: OpcodeFamily = 30; CurrentInstrCycles = 18;
45806: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
45807: if ((srca & 1) != 0) {
45808: last_fault_for_exception_3 = srca;
45809: last_op_for_exception_3 = opcode;
45810: last_addr_for_exception_3 = m68k_getpc() + 2;
45811: Exception(3, 0, M68000_EXC_SRC_CPU);
45812: goto endlabel2665;
45813: }
45814: {{ uae_s16 src = get_word(srca);
45815: m68k_areg (regs, srcreg) = srca;
45816: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
45817: if ((dsta & 1) != 0) {
45818: last_fault_for_exception_3 = dsta;
45819: last_op_for_exception_3 = opcode;
45820: last_addr_for_exception_3 = m68k_getpc() + 4;
45821: Exception(3, 0, M68000_EXC_SRC_CPU);
45822: goto endlabel2665;
45823: }
45824: { CLEAR_CZNV;
45825: SET_ZFLG (((uae_s16)(src)) == 0);
45826: SET_NFLG (((uae_s16)(src)) < 0);
45827: m68k_incpc(4);
45828: fill_prefetch_0 ();
45829: put_word(dsta,src);
45830: }}}}}}endlabel2665: ;
45831: return 18;
45832: }
45833: unsigned long REGPARAM2 CPUFUNC(op_3168_5)(uae_u32 opcode) /* MOVE */
45834: {
45835: uae_u32 srcreg = (opcode & 7);
45836: uae_u32 dstreg = (opcode >> 9) & 7;
45837: OpcodeFamily = 30; CurrentInstrCycles = 20;
45838: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
45839: if ((srca & 1) != 0) {
45840: last_fault_for_exception_3 = srca;
45841: last_op_for_exception_3 = opcode;
45842: last_addr_for_exception_3 = m68k_getpc() + 4;
45843: Exception(3, 0, M68000_EXC_SRC_CPU);
45844: goto endlabel2666;
45845: }
45846: {{ uae_s16 src = get_word(srca);
45847: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
45848: if ((dsta & 1) != 0) {
45849: last_fault_for_exception_3 = dsta;
45850: last_op_for_exception_3 = opcode;
45851: last_addr_for_exception_3 = m68k_getpc() + 6;
45852: Exception(3, 0, M68000_EXC_SRC_CPU);
45853: goto endlabel2666;
45854: }
45855: { CLEAR_CZNV;
45856: SET_ZFLG (((uae_s16)(src)) == 0);
45857: SET_NFLG (((uae_s16)(src)) < 0);
45858: m68k_incpc(6);
45859: fill_prefetch_0 ();
45860: put_word(dsta,src);
45861: }}}}}}endlabel2666: ;
45862: return 20;
45863: }
45864: unsigned long REGPARAM2 CPUFUNC(op_3170_5)(uae_u32 opcode) /* MOVE */
45865: {
45866: uae_u32 srcreg = (opcode & 7);
45867: uae_u32 dstreg = (opcode >> 9) & 7;
45868: OpcodeFamily = 30; CurrentInstrCycles = 22;
45869: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
45870: BusCyclePenalty += 2;
45871: if ((srca & 1) != 0) {
45872: last_fault_for_exception_3 = srca;
45873: last_op_for_exception_3 = opcode;
45874: last_addr_for_exception_3 = m68k_getpc() + 4;
45875: Exception(3, 0, M68000_EXC_SRC_CPU);
45876: goto endlabel2667;
45877: }
45878: {{ uae_s16 src = get_word(srca);
45879: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
45880: if ((dsta & 1) != 0) {
45881: last_fault_for_exception_3 = dsta;
45882: last_op_for_exception_3 = opcode;
45883: last_addr_for_exception_3 = m68k_getpc() + 6;
45884: Exception(3, 0, M68000_EXC_SRC_CPU);
45885: goto endlabel2667;
45886: }
45887: { CLEAR_CZNV;
45888: SET_ZFLG (((uae_s16)(src)) == 0);
45889: SET_NFLG (((uae_s16)(src)) < 0);
45890: m68k_incpc(6);
45891: fill_prefetch_0 ();
45892: put_word(dsta,src);
45893: }}}}}}endlabel2667: ;
45894: return 22;
45895: }
45896: unsigned long REGPARAM2 CPUFUNC(op_3178_5)(uae_u32 opcode) /* MOVE */
45897: {
45898: uae_u32 dstreg = (opcode >> 9) & 7;
45899: OpcodeFamily = 30; CurrentInstrCycles = 20;
45900: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
45901: if ((srca & 1) != 0) {
45902: last_fault_for_exception_3 = srca;
45903: last_op_for_exception_3 = opcode;
45904: last_addr_for_exception_3 = m68k_getpc() + 4;
45905: Exception(3, 0, M68000_EXC_SRC_CPU);
45906: goto endlabel2668;
45907: }
45908: {{ uae_s16 src = get_word(srca);
45909: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
45910: if ((dsta & 1) != 0) {
45911: last_fault_for_exception_3 = dsta;
45912: last_op_for_exception_3 = opcode;
45913: last_addr_for_exception_3 = m68k_getpc() + 6;
45914: Exception(3, 0, M68000_EXC_SRC_CPU);
45915: goto endlabel2668;
45916: }
45917: { CLEAR_CZNV;
45918: SET_ZFLG (((uae_s16)(src)) == 0);
45919: SET_NFLG (((uae_s16)(src)) < 0);
45920: m68k_incpc(6);
45921: fill_prefetch_0 ();
45922: put_word(dsta,src);
45923: }}}}}}endlabel2668: ;
45924: return 20;
45925: }
45926: unsigned long REGPARAM2 CPUFUNC(op_3179_5)(uae_u32 opcode) /* MOVE */
45927: {
45928: uae_u32 dstreg = (opcode >> 9) & 7;
45929: OpcodeFamily = 30; CurrentInstrCycles = 24;
45930: {{ uaecptr srca = get_ilong_prefetch(2);
45931: if ((srca & 1) != 0) {
45932: last_fault_for_exception_3 = srca;
45933: last_op_for_exception_3 = opcode;
45934: last_addr_for_exception_3 = m68k_getpc() + 6;
45935: Exception(3, 0, M68000_EXC_SRC_CPU);
45936: goto endlabel2669;
45937: }
45938: {{ uae_s16 src = get_word(srca);
45939: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(6);
45940: if ((dsta & 1) != 0) {
45941: last_fault_for_exception_3 = dsta;
45942: last_op_for_exception_3 = opcode;
45943: last_addr_for_exception_3 = m68k_getpc() + 8;
45944: Exception(3, 0, M68000_EXC_SRC_CPU);
45945: goto endlabel2669;
45946: }
45947: { CLEAR_CZNV;
45948: SET_ZFLG (((uae_s16)(src)) == 0);
45949: SET_NFLG (((uae_s16)(src)) < 0);
45950: m68k_incpc(8);
45951: fill_prefetch_0 ();
45952: put_word(dsta,src);
45953: }}}}}}endlabel2669: ;
45954: return 24;
45955: }
45956: unsigned long REGPARAM2 CPUFUNC(op_317a_5)(uae_u32 opcode) /* MOVE */
45957: {
45958: uae_u32 dstreg = (opcode >> 9) & 7;
45959: OpcodeFamily = 30; CurrentInstrCycles = 20;
45960: {{ uaecptr srca = m68k_getpc () + 2;
45961: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
45962: if ((srca & 1) != 0) {
45963: last_fault_for_exception_3 = srca;
45964: last_op_for_exception_3 = opcode;
45965: last_addr_for_exception_3 = m68k_getpc() + 4;
45966: Exception(3, 0, M68000_EXC_SRC_CPU);
45967: goto endlabel2670;
45968: }
45969: {{ uae_s16 src = get_word(srca);
45970: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
45971: if ((dsta & 1) != 0) {
45972: last_fault_for_exception_3 = dsta;
45973: last_op_for_exception_3 = opcode;
45974: last_addr_for_exception_3 = m68k_getpc() + 6;
45975: Exception(3, 0, M68000_EXC_SRC_CPU);
45976: goto endlabel2670;
45977: }
45978: { CLEAR_CZNV;
45979: SET_ZFLG (((uae_s16)(src)) == 0);
45980: SET_NFLG (((uae_s16)(src)) < 0);
45981: m68k_incpc(6);
45982: fill_prefetch_0 ();
45983: put_word(dsta,src);
45984: }}}}}}endlabel2670: ;
45985: return 20;
45986: }
45987: unsigned long REGPARAM2 CPUFUNC(op_317b_5)(uae_u32 opcode) /* MOVE */
45988: {
45989: uae_u32 dstreg = (opcode >> 9) & 7;
45990: OpcodeFamily = 30; CurrentInstrCycles = 22;
45991: {{ uaecptr tmppc = m68k_getpc() + 2;
45992: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
45993: BusCyclePenalty += 2;
45994: if ((srca & 1) != 0) {
45995: last_fault_for_exception_3 = srca;
45996: last_op_for_exception_3 = opcode;
45997: last_addr_for_exception_3 = m68k_getpc() + 4;
45998: Exception(3, 0, M68000_EXC_SRC_CPU);
45999: goto endlabel2671;
46000: }
46001: {{ uae_s16 src = get_word(srca);
46002: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
46003: if ((dsta & 1) != 0) {
46004: last_fault_for_exception_3 = dsta;
46005: last_op_for_exception_3 = opcode;
46006: last_addr_for_exception_3 = m68k_getpc() + 6;
46007: Exception(3, 0, M68000_EXC_SRC_CPU);
46008: goto endlabel2671;
46009: }
46010: { CLEAR_CZNV;
46011: SET_ZFLG (((uae_s16)(src)) == 0);
46012: SET_NFLG (((uae_s16)(src)) < 0);
46013: m68k_incpc(6);
46014: fill_prefetch_0 ();
46015: put_word(dsta,src);
46016: }}}}}}endlabel2671: ;
46017: return 22;
46018: }
46019: unsigned long REGPARAM2 CPUFUNC(op_317c_5)(uae_u32 opcode) /* MOVE */
46020: {
46021: uae_u32 dstreg = (opcode >> 9) & 7;
46022: OpcodeFamily = 30; CurrentInstrCycles = 16;
46023: {{ uae_s16 src = get_iword_prefetch(2);
46024: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
46025: if ((dsta & 1) != 0) {
46026: last_fault_for_exception_3 = dsta;
46027: last_op_for_exception_3 = opcode;
46028: last_addr_for_exception_3 = m68k_getpc() + 6;
46029: Exception(3, 0, M68000_EXC_SRC_CPU);
46030: goto endlabel2672;
46031: }
46032: { CLEAR_CZNV;
46033: SET_ZFLG (((uae_s16)(src)) == 0);
46034: SET_NFLG (((uae_s16)(src)) < 0);
46035: m68k_incpc(6);
46036: fill_prefetch_0 ();
46037: put_word(dsta,src);
46038: }}}}endlabel2672: ;
46039: return 16;
46040: }
46041: unsigned long REGPARAM2 CPUFUNC(op_3180_5)(uae_u32 opcode) /* MOVE */
46042: {
46043: uae_u32 srcreg = (opcode & 7);
46044: uae_u32 dstreg = (opcode >> 9) & 7;
46045: OpcodeFamily = 30; CurrentInstrCycles = 14;
46046: {{ uae_s16 src = m68k_dreg(regs, srcreg);
46047: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
46048: BusCyclePenalty += 2;
46049: if ((dsta & 1) != 0) {
46050: last_fault_for_exception_3 = dsta;
46051: last_op_for_exception_3 = opcode;
46052: last_addr_for_exception_3 = m68k_getpc() + 4;
46053: Exception(3, 0, M68000_EXC_SRC_CPU);
46054: goto endlabel2673;
46055: }
46056: { CLEAR_CZNV;
46057: SET_ZFLG (((uae_s16)(src)) == 0);
46058: SET_NFLG (((uae_s16)(src)) < 0);
46059: m68k_incpc(4);
46060: fill_prefetch_0 ();
46061: put_word(dsta,src);
46062: }}}}endlabel2673: ;
46063: return 14;
46064: }
46065: unsigned long REGPARAM2 CPUFUNC(op_3188_5)(uae_u32 opcode) /* MOVE */
46066: {
46067: uae_u32 srcreg = (opcode & 7);
46068: uae_u32 dstreg = (opcode >> 9) & 7;
46069: OpcodeFamily = 30; CurrentInstrCycles = 14;
46070: {{ uae_s16 src = m68k_areg(regs, srcreg);
46071: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
46072: BusCyclePenalty += 2;
46073: if ((dsta & 1) != 0) {
46074: last_fault_for_exception_3 = dsta;
46075: last_op_for_exception_3 = opcode;
46076: last_addr_for_exception_3 = m68k_getpc() + 4;
46077: Exception(3, 0, M68000_EXC_SRC_CPU);
46078: goto endlabel2674;
46079: }
46080: { CLEAR_CZNV;
46081: SET_ZFLG (((uae_s16)(src)) == 0);
46082: SET_NFLG (((uae_s16)(src)) < 0);
46083: m68k_incpc(4);
46084: fill_prefetch_0 ();
46085: put_word(dsta,src);
46086: }}}}endlabel2674: ;
46087: return 14;
46088: }
46089: unsigned long REGPARAM2 CPUFUNC(op_3190_5)(uae_u32 opcode) /* MOVE */
46090: {
46091: uae_u32 srcreg = (opcode & 7);
46092: uae_u32 dstreg = (opcode >> 9) & 7;
46093: OpcodeFamily = 30; CurrentInstrCycles = 18;
46094: {{ uaecptr srca = m68k_areg(regs, srcreg);
46095: if ((srca & 1) != 0) {
46096: last_fault_for_exception_3 = srca;
46097: last_op_for_exception_3 = opcode;
46098: last_addr_for_exception_3 = m68k_getpc() + 2;
46099: Exception(3, 0, M68000_EXC_SRC_CPU);
46100: goto endlabel2675;
46101: }
46102: {{ uae_s16 src = get_word(srca);
46103: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
46104: BusCyclePenalty += 2;
46105: if ((dsta & 1) != 0) {
46106: last_fault_for_exception_3 = dsta;
46107: last_op_for_exception_3 = opcode;
46108: last_addr_for_exception_3 = m68k_getpc() + 4;
46109: Exception(3, 0, M68000_EXC_SRC_CPU);
46110: goto endlabel2675;
46111: }
46112: { CLEAR_CZNV;
46113: SET_ZFLG (((uae_s16)(src)) == 0);
46114: SET_NFLG (((uae_s16)(src)) < 0);
46115: m68k_incpc(4);
46116: fill_prefetch_0 ();
46117: put_word(dsta,src);
46118: }}}}}}endlabel2675: ;
46119: return 18;
46120: }
46121: unsigned long REGPARAM2 CPUFUNC(op_3198_5)(uae_u32 opcode) /* MOVE */
46122: {
46123: uae_u32 srcreg = (opcode & 7);
46124: uae_u32 dstreg = (opcode >> 9) & 7;
46125: OpcodeFamily = 30; CurrentInstrCycles = 18;
46126: {{ uaecptr srca = m68k_areg(regs, srcreg);
46127: if ((srca & 1) != 0) {
46128: last_fault_for_exception_3 = srca;
46129: last_op_for_exception_3 = opcode;
46130: last_addr_for_exception_3 = m68k_getpc() + 2;
46131: Exception(3, 0, M68000_EXC_SRC_CPU);
46132: goto endlabel2676;
46133: }
46134: {{ uae_s16 src = get_word(srca);
46135: m68k_areg(regs, srcreg) += 2;
46136: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
46137: BusCyclePenalty += 2;
46138: if ((dsta & 1) != 0) {
46139: last_fault_for_exception_3 = dsta;
46140: last_op_for_exception_3 = opcode;
46141: last_addr_for_exception_3 = m68k_getpc() + 4;
46142: Exception(3, 0, M68000_EXC_SRC_CPU);
46143: goto endlabel2676;
46144: }
46145: { CLEAR_CZNV;
46146: SET_ZFLG (((uae_s16)(src)) == 0);
46147: SET_NFLG (((uae_s16)(src)) < 0);
46148: m68k_incpc(4);
46149: fill_prefetch_0 ();
46150: put_word(dsta,src);
46151: }}}}}}endlabel2676: ;
46152: return 18;
46153: }
46154: unsigned long REGPARAM2 CPUFUNC(op_31a0_5)(uae_u32 opcode) /* MOVE */
46155: {
46156: uae_u32 srcreg = (opcode & 7);
46157: uae_u32 dstreg = (opcode >> 9) & 7;
46158: OpcodeFamily = 30; CurrentInstrCycles = 20;
46159: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
46160: if ((srca & 1) != 0) {
46161: last_fault_for_exception_3 = srca;
46162: last_op_for_exception_3 = opcode;
46163: last_addr_for_exception_3 = m68k_getpc() + 2;
46164: Exception(3, 0, M68000_EXC_SRC_CPU);
46165: goto endlabel2677;
46166: }
46167: {{ uae_s16 src = get_word(srca);
46168: m68k_areg (regs, srcreg) = srca;
46169: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
46170: BusCyclePenalty += 2;
46171: if ((dsta & 1) != 0) {
46172: last_fault_for_exception_3 = dsta;
46173: last_op_for_exception_3 = opcode;
46174: last_addr_for_exception_3 = m68k_getpc() + 4;
46175: Exception(3, 0, M68000_EXC_SRC_CPU);
46176: goto endlabel2677;
46177: }
46178: { CLEAR_CZNV;
46179: SET_ZFLG (((uae_s16)(src)) == 0);
46180: SET_NFLG (((uae_s16)(src)) < 0);
46181: m68k_incpc(4);
46182: fill_prefetch_0 ();
46183: put_word(dsta,src);
46184: }}}}}}endlabel2677: ;
46185: return 20;
46186: }
46187: unsigned long REGPARAM2 CPUFUNC(op_31a8_5)(uae_u32 opcode) /* MOVE */
46188: {
46189: uae_u32 srcreg = (opcode & 7);
46190: uae_u32 dstreg = (opcode >> 9) & 7;
46191: OpcodeFamily = 30; CurrentInstrCycles = 22;
46192: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
46193: if ((srca & 1) != 0) {
46194: last_fault_for_exception_3 = srca;
46195: last_op_for_exception_3 = opcode;
46196: last_addr_for_exception_3 = m68k_getpc() + 4;
46197: Exception(3, 0, M68000_EXC_SRC_CPU);
46198: goto endlabel2678;
46199: }
46200: {{ uae_s16 src = get_word(srca);
46201: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
46202: BusCyclePenalty += 2;
46203: if ((dsta & 1) != 0) {
46204: last_fault_for_exception_3 = dsta;
46205: last_op_for_exception_3 = opcode;
46206: last_addr_for_exception_3 = m68k_getpc() + 6;
46207: Exception(3, 0, M68000_EXC_SRC_CPU);
46208: goto endlabel2678;
46209: }
46210: { CLEAR_CZNV;
46211: SET_ZFLG (((uae_s16)(src)) == 0);
46212: SET_NFLG (((uae_s16)(src)) < 0);
46213: m68k_incpc(6);
46214: fill_prefetch_0 ();
46215: put_word(dsta,src);
46216: }}}}}}endlabel2678: ;
46217: return 22;
46218: }
46219: unsigned long REGPARAM2 CPUFUNC(op_31b0_5)(uae_u32 opcode) /* MOVE */
46220: {
46221: uae_u32 srcreg = (opcode & 7);
46222: uae_u32 dstreg = (opcode >> 9) & 7;
46223: OpcodeFamily = 30; CurrentInstrCycles = 24;
46224: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
46225: BusCyclePenalty += 2;
46226: if ((srca & 1) != 0) {
46227: last_fault_for_exception_3 = srca;
46228: last_op_for_exception_3 = opcode;
46229: last_addr_for_exception_3 = m68k_getpc() + 4;
46230: Exception(3, 0, M68000_EXC_SRC_CPU);
46231: goto endlabel2679;
46232: }
46233: {{ uae_s16 src = get_word(srca);
46234: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
46235: BusCyclePenalty += 2;
46236: if ((dsta & 1) != 0) {
46237: last_fault_for_exception_3 = dsta;
46238: last_op_for_exception_3 = opcode;
46239: last_addr_for_exception_3 = m68k_getpc() + 6;
46240: Exception(3, 0, M68000_EXC_SRC_CPU);
46241: goto endlabel2679;
46242: }
46243: { CLEAR_CZNV;
46244: SET_ZFLG (((uae_s16)(src)) == 0);
46245: SET_NFLG (((uae_s16)(src)) < 0);
46246: m68k_incpc(6);
46247: fill_prefetch_0 ();
46248: put_word(dsta,src);
46249: }}}}}}endlabel2679: ;
46250: return 24;
46251: }
46252: unsigned long REGPARAM2 CPUFUNC(op_31b8_5)(uae_u32 opcode) /* MOVE */
46253: {
46254: uae_u32 dstreg = (opcode >> 9) & 7;
46255: OpcodeFamily = 30; CurrentInstrCycles = 22;
46256: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
46257: if ((srca & 1) != 0) {
46258: last_fault_for_exception_3 = srca;
46259: last_op_for_exception_3 = opcode;
46260: last_addr_for_exception_3 = m68k_getpc() + 4;
46261: Exception(3, 0, M68000_EXC_SRC_CPU);
46262: goto endlabel2680;
46263: }
46264: {{ uae_s16 src = get_word(srca);
46265: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
46266: BusCyclePenalty += 2;
46267: if ((dsta & 1) != 0) {
46268: last_fault_for_exception_3 = dsta;
46269: last_op_for_exception_3 = opcode;
46270: last_addr_for_exception_3 = m68k_getpc() + 6;
46271: Exception(3, 0, M68000_EXC_SRC_CPU);
46272: goto endlabel2680;
46273: }
46274: { CLEAR_CZNV;
46275: SET_ZFLG (((uae_s16)(src)) == 0);
46276: SET_NFLG (((uae_s16)(src)) < 0);
46277: m68k_incpc(6);
46278: fill_prefetch_0 ();
46279: put_word(dsta,src);
46280: }}}}}}endlabel2680: ;
46281: return 22;
46282: }
46283: unsigned long REGPARAM2 CPUFUNC(op_31b9_5)(uae_u32 opcode) /* MOVE */
46284: {
46285: uae_u32 dstreg = (opcode >> 9) & 7;
46286: OpcodeFamily = 30; CurrentInstrCycles = 26;
46287: {{ uaecptr srca = get_ilong_prefetch(2);
46288: if ((srca & 1) != 0) {
46289: last_fault_for_exception_3 = srca;
46290: last_op_for_exception_3 = opcode;
46291: last_addr_for_exception_3 = m68k_getpc() + 6;
46292: Exception(3, 0, M68000_EXC_SRC_CPU);
46293: goto endlabel2681;
46294: }
46295: {{ uae_s16 src = get_word(srca);
46296: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6));
46297: BusCyclePenalty += 2;
46298: if ((dsta & 1) != 0) {
46299: last_fault_for_exception_3 = dsta;
46300: last_op_for_exception_3 = opcode;
46301: last_addr_for_exception_3 = m68k_getpc() + 8;
46302: Exception(3, 0, M68000_EXC_SRC_CPU);
46303: goto endlabel2681;
46304: }
46305: { CLEAR_CZNV;
46306: SET_ZFLG (((uae_s16)(src)) == 0);
46307: SET_NFLG (((uae_s16)(src)) < 0);
46308: m68k_incpc(8);
46309: fill_prefetch_0 ();
46310: put_word(dsta,src);
46311: }}}}}}endlabel2681: ;
46312: return 26;
46313: }
46314: unsigned long REGPARAM2 CPUFUNC(op_31ba_5)(uae_u32 opcode) /* MOVE */
46315: {
46316: uae_u32 dstreg = (opcode >> 9) & 7;
46317: OpcodeFamily = 30; CurrentInstrCycles = 22;
46318: {{ uaecptr srca = m68k_getpc () + 2;
46319: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
46320: if ((srca & 1) != 0) {
46321: last_fault_for_exception_3 = srca;
46322: last_op_for_exception_3 = opcode;
46323: last_addr_for_exception_3 = m68k_getpc() + 4;
46324: Exception(3, 0, M68000_EXC_SRC_CPU);
46325: goto endlabel2682;
46326: }
46327: {{ uae_s16 src = get_word(srca);
46328: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
46329: BusCyclePenalty += 2;
46330: if ((dsta & 1) != 0) {
46331: last_fault_for_exception_3 = dsta;
46332: last_op_for_exception_3 = opcode;
46333: last_addr_for_exception_3 = m68k_getpc() + 6;
46334: Exception(3, 0, M68000_EXC_SRC_CPU);
46335: goto endlabel2682;
46336: }
46337: { CLEAR_CZNV;
46338: SET_ZFLG (((uae_s16)(src)) == 0);
46339: SET_NFLG (((uae_s16)(src)) < 0);
46340: m68k_incpc(6);
46341: fill_prefetch_0 ();
46342: put_word(dsta,src);
46343: }}}}}}endlabel2682: ;
46344: return 22;
46345: }
46346: unsigned long REGPARAM2 CPUFUNC(op_31bb_5)(uae_u32 opcode) /* MOVE */
46347: {
46348: uae_u32 dstreg = (opcode >> 9) & 7;
46349: OpcodeFamily = 30; CurrentInstrCycles = 24;
46350: {{ uaecptr tmppc = m68k_getpc() + 2;
46351: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
46352: BusCyclePenalty += 2;
46353: if ((srca & 1) != 0) {
46354: last_fault_for_exception_3 = srca;
46355: last_op_for_exception_3 = opcode;
46356: last_addr_for_exception_3 = m68k_getpc() + 4;
46357: Exception(3, 0, M68000_EXC_SRC_CPU);
46358: goto endlabel2683;
46359: }
46360: {{ uae_s16 src = get_word(srca);
46361: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
46362: BusCyclePenalty += 2;
46363: if ((dsta & 1) != 0) {
46364: last_fault_for_exception_3 = dsta;
46365: last_op_for_exception_3 = opcode;
46366: last_addr_for_exception_3 = m68k_getpc() + 6;
46367: Exception(3, 0, M68000_EXC_SRC_CPU);
46368: goto endlabel2683;
46369: }
46370: { CLEAR_CZNV;
46371: SET_ZFLG (((uae_s16)(src)) == 0);
46372: SET_NFLG (((uae_s16)(src)) < 0);
46373: m68k_incpc(6);
46374: fill_prefetch_0 ();
46375: put_word(dsta,src);
46376: }}}}}}endlabel2683: ;
46377: return 24;
46378: }
46379: unsigned long REGPARAM2 CPUFUNC(op_31bc_5)(uae_u32 opcode) /* MOVE */
46380: {
46381: uae_u32 dstreg = (opcode >> 9) & 7;
46382: OpcodeFamily = 30; CurrentInstrCycles = 18;
46383: {{ uae_s16 src = get_iword_prefetch(2);
46384: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
46385: BusCyclePenalty += 2;
46386: if ((dsta & 1) != 0) {
46387: last_fault_for_exception_3 = dsta;
46388: last_op_for_exception_3 = opcode;
46389: last_addr_for_exception_3 = m68k_getpc() + 6;
46390: Exception(3, 0, M68000_EXC_SRC_CPU);
46391: goto endlabel2684;
46392: }
46393: { CLEAR_CZNV;
46394: SET_ZFLG (((uae_s16)(src)) == 0);
46395: SET_NFLG (((uae_s16)(src)) < 0);
46396: m68k_incpc(6);
46397: fill_prefetch_0 ();
46398: put_word(dsta,src);
46399: }}}}endlabel2684: ;
46400: return 18;
46401: }
46402: unsigned long REGPARAM2 CPUFUNC(op_31c0_5)(uae_u32 opcode) /* MOVE */
46403: {
46404: uae_u32 srcreg = (opcode & 7);
46405: OpcodeFamily = 30; CurrentInstrCycles = 12;
46406: {{ uae_s16 src = m68k_dreg(regs, srcreg);
46407: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
46408: if ((dsta & 1) != 0) {
46409: last_fault_for_exception_3 = dsta;
46410: last_op_for_exception_3 = opcode;
46411: last_addr_for_exception_3 = m68k_getpc() + 4;
46412: Exception(3, 0, M68000_EXC_SRC_CPU);
46413: goto endlabel2685;
46414: }
46415: { CLEAR_CZNV;
46416: SET_ZFLG (((uae_s16)(src)) == 0);
46417: SET_NFLG (((uae_s16)(src)) < 0);
46418: m68k_incpc(4);
46419: fill_prefetch_0 ();
46420: put_word(dsta,src);
46421: }}}}endlabel2685: ;
46422: return 12;
46423: }
46424: unsigned long REGPARAM2 CPUFUNC(op_31c8_5)(uae_u32 opcode) /* MOVE */
46425: {
46426: uae_u32 srcreg = (opcode & 7);
46427: OpcodeFamily = 30; CurrentInstrCycles = 12;
46428: {{ uae_s16 src = m68k_areg(regs, srcreg);
46429: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
46430: if ((dsta & 1) != 0) {
46431: last_fault_for_exception_3 = dsta;
46432: last_op_for_exception_3 = opcode;
46433: last_addr_for_exception_3 = m68k_getpc() + 4;
46434: Exception(3, 0, M68000_EXC_SRC_CPU);
46435: goto endlabel2686;
46436: }
46437: { CLEAR_CZNV;
46438: SET_ZFLG (((uae_s16)(src)) == 0);
46439: SET_NFLG (((uae_s16)(src)) < 0);
46440: m68k_incpc(4);
46441: fill_prefetch_0 ();
46442: put_word(dsta,src);
46443: }}}}endlabel2686: ;
46444: return 12;
46445: }
46446: unsigned long REGPARAM2 CPUFUNC(op_31d0_5)(uae_u32 opcode) /* MOVE */
46447: {
46448: uae_u32 srcreg = (opcode & 7);
46449: OpcodeFamily = 30; CurrentInstrCycles = 16;
46450: {{ uaecptr srca = m68k_areg(regs, srcreg);
46451: if ((srca & 1) != 0) {
46452: last_fault_for_exception_3 = srca;
46453: last_op_for_exception_3 = opcode;
46454: last_addr_for_exception_3 = m68k_getpc() + 2;
46455: Exception(3, 0, M68000_EXC_SRC_CPU);
46456: goto endlabel2687;
46457: }
46458: {{ uae_s16 src = get_word(srca);
46459: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
46460: if ((dsta & 1) != 0) {
46461: last_fault_for_exception_3 = dsta;
46462: last_op_for_exception_3 = opcode;
46463: last_addr_for_exception_3 = m68k_getpc() + 4;
46464: Exception(3, 0, M68000_EXC_SRC_CPU);
46465: goto endlabel2687;
46466: }
46467: { CLEAR_CZNV;
46468: SET_ZFLG (((uae_s16)(src)) == 0);
46469: SET_NFLG (((uae_s16)(src)) < 0);
46470: m68k_incpc(4);
46471: fill_prefetch_0 ();
46472: put_word(dsta,src);
46473: }}}}}}endlabel2687: ;
46474: return 16;
46475: }
46476: unsigned long REGPARAM2 CPUFUNC(op_31d8_5)(uae_u32 opcode) /* MOVE */
46477: {
46478: uae_u32 srcreg = (opcode & 7);
46479: OpcodeFamily = 30; CurrentInstrCycles = 16;
46480: {{ uaecptr srca = m68k_areg(regs, srcreg);
46481: if ((srca & 1) != 0) {
46482: last_fault_for_exception_3 = srca;
46483: last_op_for_exception_3 = opcode;
46484: last_addr_for_exception_3 = m68k_getpc() + 2;
46485: Exception(3, 0, M68000_EXC_SRC_CPU);
46486: goto endlabel2688;
46487: }
46488: {{ uae_s16 src = get_word(srca);
46489: m68k_areg(regs, srcreg) += 2;
46490: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
46491: if ((dsta & 1) != 0) {
46492: last_fault_for_exception_3 = dsta;
46493: last_op_for_exception_3 = opcode;
46494: last_addr_for_exception_3 = m68k_getpc() + 4;
46495: Exception(3, 0, M68000_EXC_SRC_CPU);
46496: goto endlabel2688;
46497: }
46498: { CLEAR_CZNV;
46499: SET_ZFLG (((uae_s16)(src)) == 0);
46500: SET_NFLG (((uae_s16)(src)) < 0);
46501: m68k_incpc(4);
46502: fill_prefetch_0 ();
46503: put_word(dsta,src);
46504: }}}}}}endlabel2688: ;
46505: return 16;
46506: }
46507: unsigned long REGPARAM2 CPUFUNC(op_31e0_5)(uae_u32 opcode) /* MOVE */
46508: {
46509: uae_u32 srcreg = (opcode & 7);
46510: OpcodeFamily = 30; CurrentInstrCycles = 18;
46511: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
46512: if ((srca & 1) != 0) {
46513: last_fault_for_exception_3 = srca;
46514: last_op_for_exception_3 = opcode;
46515: last_addr_for_exception_3 = m68k_getpc() + 2;
46516: Exception(3, 0, M68000_EXC_SRC_CPU);
46517: goto endlabel2689;
46518: }
46519: {{ uae_s16 src = get_word(srca);
46520: m68k_areg (regs, srcreg) = srca;
46521: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
46522: if ((dsta & 1) != 0) {
46523: last_fault_for_exception_3 = dsta;
46524: last_op_for_exception_3 = opcode;
46525: last_addr_for_exception_3 = m68k_getpc() + 4;
46526: Exception(3, 0, M68000_EXC_SRC_CPU);
46527: goto endlabel2689;
46528: }
46529: { CLEAR_CZNV;
46530: SET_ZFLG (((uae_s16)(src)) == 0);
46531: SET_NFLG (((uae_s16)(src)) < 0);
46532: m68k_incpc(4);
46533: fill_prefetch_0 ();
46534: put_word(dsta,src);
46535: }}}}}}endlabel2689: ;
46536: return 18;
46537: }
46538: unsigned long REGPARAM2 CPUFUNC(op_31e8_5)(uae_u32 opcode) /* MOVE */
46539: {
46540: uae_u32 srcreg = (opcode & 7);
46541: OpcodeFamily = 30; CurrentInstrCycles = 20;
46542: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
46543: if ((srca & 1) != 0) {
46544: last_fault_for_exception_3 = srca;
46545: last_op_for_exception_3 = opcode;
46546: last_addr_for_exception_3 = m68k_getpc() + 4;
46547: Exception(3, 0, M68000_EXC_SRC_CPU);
46548: goto endlabel2690;
46549: }
46550: {{ uae_s16 src = get_word(srca);
46551: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
46552: if ((dsta & 1) != 0) {
46553: last_fault_for_exception_3 = dsta;
46554: last_op_for_exception_3 = opcode;
46555: last_addr_for_exception_3 = m68k_getpc() + 6;
46556: Exception(3, 0, M68000_EXC_SRC_CPU);
46557: goto endlabel2690;
46558: }
46559: { CLEAR_CZNV;
46560: SET_ZFLG (((uae_s16)(src)) == 0);
46561: SET_NFLG (((uae_s16)(src)) < 0);
46562: m68k_incpc(6);
46563: fill_prefetch_0 ();
46564: put_word(dsta,src);
46565: }}}}}}endlabel2690: ;
46566: return 20;
46567: }
46568: unsigned long REGPARAM2 CPUFUNC(op_31f0_5)(uae_u32 opcode) /* MOVE */
46569: {
46570: uae_u32 srcreg = (opcode & 7);
46571: OpcodeFamily = 30; CurrentInstrCycles = 22;
46572: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
46573: BusCyclePenalty += 2;
46574: if ((srca & 1) != 0) {
46575: last_fault_for_exception_3 = srca;
46576: last_op_for_exception_3 = opcode;
46577: last_addr_for_exception_3 = m68k_getpc() + 4;
46578: Exception(3, 0, M68000_EXC_SRC_CPU);
46579: goto endlabel2691;
46580: }
46581: {{ uae_s16 src = get_word(srca);
46582: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
46583: if ((dsta & 1) != 0) {
46584: last_fault_for_exception_3 = dsta;
46585: last_op_for_exception_3 = opcode;
46586: last_addr_for_exception_3 = m68k_getpc() + 6;
46587: Exception(3, 0, M68000_EXC_SRC_CPU);
46588: goto endlabel2691;
46589: }
46590: { CLEAR_CZNV;
46591: SET_ZFLG (((uae_s16)(src)) == 0);
46592: SET_NFLG (((uae_s16)(src)) < 0);
46593: m68k_incpc(6);
46594: fill_prefetch_0 ();
46595: put_word(dsta,src);
46596: }}}}}}endlabel2691: ;
46597: return 22;
46598: }
46599: unsigned long REGPARAM2 CPUFUNC(op_31f8_5)(uae_u32 opcode) /* MOVE */
46600: {
46601: OpcodeFamily = 30; CurrentInstrCycles = 20;
46602: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
46603: if ((srca & 1) != 0) {
46604: last_fault_for_exception_3 = srca;
46605: last_op_for_exception_3 = opcode;
46606: last_addr_for_exception_3 = m68k_getpc() + 4;
46607: Exception(3, 0, M68000_EXC_SRC_CPU);
46608: goto endlabel2692;
46609: }
46610: {{ uae_s16 src = get_word(srca);
46611: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
46612: if ((dsta & 1) != 0) {
46613: last_fault_for_exception_3 = dsta;
46614: last_op_for_exception_3 = opcode;
46615: last_addr_for_exception_3 = m68k_getpc() + 6;
46616: Exception(3, 0, M68000_EXC_SRC_CPU);
46617: goto endlabel2692;
46618: }
46619: { CLEAR_CZNV;
46620: SET_ZFLG (((uae_s16)(src)) == 0);
46621: SET_NFLG (((uae_s16)(src)) < 0);
46622: m68k_incpc(6);
46623: fill_prefetch_0 ();
46624: put_word(dsta,src);
46625: }}}}}}endlabel2692: ;
46626: return 20;
46627: }
46628: unsigned long REGPARAM2 CPUFUNC(op_31f9_5)(uae_u32 opcode) /* MOVE */
46629: {
46630: OpcodeFamily = 30; CurrentInstrCycles = 24;
46631: {{ uaecptr srca = get_ilong_prefetch(2);
46632: if ((srca & 1) != 0) {
46633: last_fault_for_exception_3 = srca;
46634: last_op_for_exception_3 = opcode;
46635: last_addr_for_exception_3 = m68k_getpc() + 6;
46636: Exception(3, 0, M68000_EXC_SRC_CPU);
46637: goto endlabel2693;
46638: }
46639: {{ uae_s16 src = get_word(srca);
46640: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(6);
46641: if ((dsta & 1) != 0) {
46642: last_fault_for_exception_3 = dsta;
46643: last_op_for_exception_3 = opcode;
46644: last_addr_for_exception_3 = m68k_getpc() + 8;
46645: Exception(3, 0, M68000_EXC_SRC_CPU);
46646: goto endlabel2693;
46647: }
46648: { CLEAR_CZNV;
46649: SET_ZFLG (((uae_s16)(src)) == 0);
46650: SET_NFLG (((uae_s16)(src)) < 0);
46651: m68k_incpc(8);
46652: fill_prefetch_0 ();
46653: put_word(dsta,src);
46654: }}}}}}endlabel2693: ;
46655: return 24;
46656: }
46657: unsigned long REGPARAM2 CPUFUNC(op_31fa_5)(uae_u32 opcode) /* MOVE */
46658: {
46659: OpcodeFamily = 30; CurrentInstrCycles = 20;
46660: {{ uaecptr srca = m68k_getpc () + 2;
46661: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
46662: if ((srca & 1) != 0) {
46663: last_fault_for_exception_3 = srca;
46664: last_op_for_exception_3 = opcode;
46665: last_addr_for_exception_3 = m68k_getpc() + 4;
46666: Exception(3, 0, M68000_EXC_SRC_CPU);
46667: goto endlabel2694;
46668: }
46669: {{ uae_s16 src = get_word(srca);
46670: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
46671: if ((dsta & 1) != 0) {
46672: last_fault_for_exception_3 = dsta;
46673: last_op_for_exception_3 = opcode;
46674: last_addr_for_exception_3 = m68k_getpc() + 6;
46675: Exception(3, 0, M68000_EXC_SRC_CPU);
46676: goto endlabel2694;
46677: }
46678: { CLEAR_CZNV;
46679: SET_ZFLG (((uae_s16)(src)) == 0);
46680: SET_NFLG (((uae_s16)(src)) < 0);
46681: m68k_incpc(6);
46682: fill_prefetch_0 ();
46683: put_word(dsta,src);
46684: }}}}}}endlabel2694: ;
46685: return 20;
46686: }
46687: unsigned long REGPARAM2 CPUFUNC(op_31fb_5)(uae_u32 opcode) /* MOVE */
46688: {
46689: OpcodeFamily = 30; CurrentInstrCycles = 22;
46690: {{ uaecptr tmppc = m68k_getpc() + 2;
46691: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
46692: BusCyclePenalty += 2;
46693: if ((srca & 1) != 0) {
46694: last_fault_for_exception_3 = srca;
46695: last_op_for_exception_3 = opcode;
46696: last_addr_for_exception_3 = m68k_getpc() + 4;
46697: Exception(3, 0, M68000_EXC_SRC_CPU);
46698: goto endlabel2695;
46699: }
46700: {{ uae_s16 src = get_word(srca);
46701: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
46702: if ((dsta & 1) != 0) {
46703: last_fault_for_exception_3 = dsta;
46704: last_op_for_exception_3 = opcode;
46705: last_addr_for_exception_3 = m68k_getpc() + 6;
46706: Exception(3, 0, M68000_EXC_SRC_CPU);
46707: goto endlabel2695;
46708: }
46709: { CLEAR_CZNV;
46710: SET_ZFLG (((uae_s16)(src)) == 0);
46711: SET_NFLG (((uae_s16)(src)) < 0);
46712: m68k_incpc(6);
46713: fill_prefetch_0 ();
46714: put_word(dsta,src);
46715: }}}}}}endlabel2695: ;
46716: return 22;
46717: }
46718: unsigned long REGPARAM2 CPUFUNC(op_31fc_5)(uae_u32 opcode) /* MOVE */
46719: {
46720: OpcodeFamily = 30; CurrentInstrCycles = 16;
46721: {{ uae_s16 src = get_iword_prefetch(2);
46722: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(4);
46723: if ((dsta & 1) != 0) {
46724: last_fault_for_exception_3 = dsta;
46725: last_op_for_exception_3 = opcode;
46726: last_addr_for_exception_3 = m68k_getpc() + 6;
46727: Exception(3, 0, M68000_EXC_SRC_CPU);
46728: goto endlabel2696;
46729: }
46730: { CLEAR_CZNV;
46731: SET_ZFLG (((uae_s16)(src)) == 0);
46732: SET_NFLG (((uae_s16)(src)) < 0);
46733: m68k_incpc(6);
46734: fill_prefetch_0 ();
46735: put_word(dsta,src);
46736: }}}}endlabel2696: ;
46737: return 16;
46738: }
46739: unsigned long REGPARAM2 CPUFUNC(op_33c0_5)(uae_u32 opcode) /* MOVE */
46740: {
46741: uae_u32 srcreg = (opcode & 7);
46742: OpcodeFamily = 30; CurrentInstrCycles = 16;
46743: {{ uae_s16 src = m68k_dreg(regs, srcreg);
46744: { uaecptr dsta = get_ilong_prefetch(2);
46745: if ((dsta & 1) != 0) {
46746: last_fault_for_exception_3 = dsta;
46747: last_op_for_exception_3 = opcode;
46748: last_addr_for_exception_3 = m68k_getpc() + 6;
46749: Exception(3, 0, M68000_EXC_SRC_CPU);
46750: goto endlabel2697;
46751: }
46752: { CLEAR_CZNV;
46753: SET_ZFLG (((uae_s16)(src)) == 0);
46754: SET_NFLG (((uae_s16)(src)) < 0);
46755: m68k_incpc(6);
46756: fill_prefetch_0 ();
46757: put_word(dsta,src);
46758: }}}}endlabel2697: ;
46759: return 16;
46760: }
46761: unsigned long REGPARAM2 CPUFUNC(op_33c8_5)(uae_u32 opcode) /* MOVE */
46762: {
46763: uae_u32 srcreg = (opcode & 7);
46764: OpcodeFamily = 30; CurrentInstrCycles = 16;
46765: {{ uae_s16 src = m68k_areg(regs, srcreg);
46766: { uaecptr dsta = get_ilong_prefetch(2);
46767: if ((dsta & 1) != 0) {
46768: last_fault_for_exception_3 = dsta;
46769: last_op_for_exception_3 = opcode;
46770: last_addr_for_exception_3 = m68k_getpc() + 6;
46771: Exception(3, 0, M68000_EXC_SRC_CPU);
46772: goto endlabel2698;
46773: }
46774: { CLEAR_CZNV;
46775: SET_ZFLG (((uae_s16)(src)) == 0);
46776: SET_NFLG (((uae_s16)(src)) < 0);
46777: m68k_incpc(6);
46778: fill_prefetch_0 ();
46779: put_word(dsta,src);
46780: }}}}endlabel2698: ;
46781: return 16;
46782: }
46783: unsigned long REGPARAM2 CPUFUNC(op_33d0_5)(uae_u32 opcode) /* MOVE */
46784: {
46785: uae_u32 srcreg = (opcode & 7);
46786: OpcodeFamily = 30; CurrentInstrCycles = 20;
46787: {{ uaecptr srca = m68k_areg(regs, srcreg);
46788: if ((srca & 1) != 0) {
46789: last_fault_for_exception_3 = srca;
46790: last_op_for_exception_3 = opcode;
46791: last_addr_for_exception_3 = m68k_getpc() + 2;
46792: Exception(3, 0, M68000_EXC_SRC_CPU);
46793: goto endlabel2699;
46794: }
46795: {{ uae_s16 src = get_word(srca);
46796: { uaecptr dsta = get_ilong_prefetch(2);
46797: if ((dsta & 1) != 0) {
46798: last_fault_for_exception_3 = dsta;
46799: last_op_for_exception_3 = opcode;
46800: last_addr_for_exception_3 = m68k_getpc() + 6;
46801: Exception(3, 0, M68000_EXC_SRC_CPU);
46802: goto endlabel2699;
46803: }
46804: { CLEAR_CZNV;
46805: SET_ZFLG (((uae_s16)(src)) == 0);
46806: SET_NFLG (((uae_s16)(src)) < 0);
46807: m68k_incpc(6);
46808: fill_prefetch_0 ();
46809: put_word(dsta,src);
46810: }}}}}}endlabel2699: ;
46811: return 20;
46812: }
46813: unsigned long REGPARAM2 CPUFUNC(op_33d8_5)(uae_u32 opcode) /* MOVE */
46814: {
46815: uae_u32 srcreg = (opcode & 7);
46816: OpcodeFamily = 30; CurrentInstrCycles = 20;
46817: {{ uaecptr srca = m68k_areg(regs, srcreg);
46818: if ((srca & 1) != 0) {
46819: last_fault_for_exception_3 = srca;
46820: last_op_for_exception_3 = opcode;
46821: last_addr_for_exception_3 = m68k_getpc() + 2;
46822: Exception(3, 0, M68000_EXC_SRC_CPU);
46823: goto endlabel2700;
46824: }
46825: {{ uae_s16 src = get_word(srca);
46826: m68k_areg(regs, srcreg) += 2;
46827: { uaecptr dsta = get_ilong_prefetch(2);
46828: if ((dsta & 1) != 0) {
46829: last_fault_for_exception_3 = dsta;
46830: last_op_for_exception_3 = opcode;
46831: last_addr_for_exception_3 = m68k_getpc() + 6;
46832: Exception(3, 0, M68000_EXC_SRC_CPU);
46833: goto endlabel2700;
46834: }
46835: { CLEAR_CZNV;
46836: SET_ZFLG (((uae_s16)(src)) == 0);
46837: SET_NFLG (((uae_s16)(src)) < 0);
46838: m68k_incpc(6);
46839: fill_prefetch_0 ();
46840: put_word(dsta,src);
46841: }}}}}}endlabel2700: ;
46842: return 20;
46843: }
46844: unsigned long REGPARAM2 CPUFUNC(op_33e0_5)(uae_u32 opcode) /* MOVE */
46845: {
46846: uae_u32 srcreg = (opcode & 7);
46847: OpcodeFamily = 30; CurrentInstrCycles = 22;
46848: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
46849: if ((srca & 1) != 0) {
46850: last_fault_for_exception_3 = srca;
46851: last_op_for_exception_3 = opcode;
46852: last_addr_for_exception_3 = m68k_getpc() + 2;
46853: Exception(3, 0, M68000_EXC_SRC_CPU);
46854: goto endlabel2701;
46855: }
46856: {{ uae_s16 src = get_word(srca);
46857: m68k_areg (regs, srcreg) = srca;
46858: { uaecptr dsta = get_ilong_prefetch(2);
46859: if ((dsta & 1) != 0) {
46860: last_fault_for_exception_3 = dsta;
46861: last_op_for_exception_3 = opcode;
46862: last_addr_for_exception_3 = m68k_getpc() + 6;
46863: Exception(3, 0, M68000_EXC_SRC_CPU);
46864: goto endlabel2701;
46865: }
46866: { CLEAR_CZNV;
46867: SET_ZFLG (((uae_s16)(src)) == 0);
46868: SET_NFLG (((uae_s16)(src)) < 0);
46869: m68k_incpc(6);
46870: fill_prefetch_0 ();
46871: put_word(dsta,src);
46872: }}}}}}endlabel2701: ;
46873: return 22;
46874: }
46875: unsigned long REGPARAM2 CPUFUNC(op_33e8_5)(uae_u32 opcode) /* MOVE */
46876: {
46877: uae_u32 srcreg = (opcode & 7);
46878: OpcodeFamily = 30; CurrentInstrCycles = 24;
46879: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
46880: if ((srca & 1) != 0) {
46881: last_fault_for_exception_3 = srca;
46882: last_op_for_exception_3 = opcode;
46883: last_addr_for_exception_3 = m68k_getpc() + 4;
46884: Exception(3, 0, M68000_EXC_SRC_CPU);
46885: goto endlabel2702;
46886: }
46887: {{ uae_s16 src = get_word(srca);
46888: { uaecptr dsta = get_ilong_prefetch(4);
46889: if ((dsta & 1) != 0) {
46890: last_fault_for_exception_3 = dsta;
46891: last_op_for_exception_3 = opcode;
46892: last_addr_for_exception_3 = m68k_getpc() + 8;
46893: Exception(3, 0, M68000_EXC_SRC_CPU);
46894: goto endlabel2702;
46895: }
46896: { CLEAR_CZNV;
46897: SET_ZFLG (((uae_s16)(src)) == 0);
46898: SET_NFLG (((uae_s16)(src)) < 0);
46899: m68k_incpc(8);
46900: fill_prefetch_0 ();
46901: put_word(dsta,src);
46902: }}}}}}endlabel2702: ;
46903: return 24;
46904: }
46905: unsigned long REGPARAM2 CPUFUNC(op_33f0_5)(uae_u32 opcode) /* MOVE */
46906: {
46907: uae_u32 srcreg = (opcode & 7);
46908: OpcodeFamily = 30; CurrentInstrCycles = 26;
46909: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
46910: BusCyclePenalty += 2;
46911: if ((srca & 1) != 0) {
46912: last_fault_for_exception_3 = srca;
46913: last_op_for_exception_3 = opcode;
46914: last_addr_for_exception_3 = m68k_getpc() + 4;
46915: Exception(3, 0, M68000_EXC_SRC_CPU);
46916: goto endlabel2703;
46917: }
46918: {{ uae_s16 src = get_word(srca);
46919: { uaecptr dsta = get_ilong_prefetch(4);
46920: if ((dsta & 1) != 0) {
46921: last_fault_for_exception_3 = dsta;
46922: last_op_for_exception_3 = opcode;
46923: last_addr_for_exception_3 = m68k_getpc() + 8;
46924: Exception(3, 0, M68000_EXC_SRC_CPU);
46925: goto endlabel2703;
46926: }
46927: { CLEAR_CZNV;
46928: SET_ZFLG (((uae_s16)(src)) == 0);
46929: SET_NFLG (((uae_s16)(src)) < 0);
46930: m68k_incpc(8);
46931: fill_prefetch_0 ();
46932: put_word(dsta,src);
46933: }}}}}}endlabel2703: ;
46934: return 26;
46935: }
46936: unsigned long REGPARAM2 CPUFUNC(op_33f8_5)(uae_u32 opcode) /* MOVE */
46937: {
46938: OpcodeFamily = 30; CurrentInstrCycles = 24;
46939: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
46940: if ((srca & 1) != 0) {
46941: last_fault_for_exception_3 = srca;
46942: last_op_for_exception_3 = opcode;
46943: last_addr_for_exception_3 = m68k_getpc() + 4;
46944: Exception(3, 0, M68000_EXC_SRC_CPU);
46945: goto endlabel2704;
46946: }
46947: {{ uae_s16 src = get_word(srca);
46948: { uaecptr dsta = get_ilong_prefetch(4);
46949: if ((dsta & 1) != 0) {
46950: last_fault_for_exception_3 = dsta;
46951: last_op_for_exception_3 = opcode;
46952: last_addr_for_exception_3 = m68k_getpc() + 8;
46953: Exception(3, 0, M68000_EXC_SRC_CPU);
46954: goto endlabel2704;
46955: }
46956: { CLEAR_CZNV;
46957: SET_ZFLG (((uae_s16)(src)) == 0);
46958: SET_NFLG (((uae_s16)(src)) < 0);
46959: m68k_incpc(8);
46960: fill_prefetch_0 ();
46961: put_word(dsta,src);
46962: }}}}}}endlabel2704: ;
46963: return 24;
46964: }
46965: unsigned long REGPARAM2 CPUFUNC(op_33f9_5)(uae_u32 opcode) /* MOVE */
46966: {
46967: OpcodeFamily = 30; CurrentInstrCycles = 28;
46968: {{ uaecptr srca = get_ilong_prefetch(2);
46969: if ((srca & 1) != 0) {
46970: last_fault_for_exception_3 = srca;
46971: last_op_for_exception_3 = opcode;
46972: last_addr_for_exception_3 = m68k_getpc() + 6;
46973: Exception(3, 0, M68000_EXC_SRC_CPU);
46974: goto endlabel2705;
46975: }
46976: {{ uae_s16 src = get_word(srca);
46977: { uaecptr dsta = get_ilong_prefetch(6);
46978: if ((dsta & 1) != 0) {
46979: last_fault_for_exception_3 = dsta;
46980: last_op_for_exception_3 = opcode;
46981: last_addr_for_exception_3 = m68k_getpc() + 10;
46982: Exception(3, 0, M68000_EXC_SRC_CPU);
46983: goto endlabel2705;
46984: }
46985: { CLEAR_CZNV;
46986: SET_ZFLG (((uae_s16)(src)) == 0);
46987: SET_NFLG (((uae_s16)(src)) < 0);
46988: m68k_incpc(10);
46989: fill_prefetch_0 ();
46990: put_word(dsta,src);
46991: }}}}}}endlabel2705: ;
46992: return 28;
46993: }
46994: unsigned long REGPARAM2 CPUFUNC(op_33fa_5)(uae_u32 opcode) /* MOVE */
46995: {
46996: OpcodeFamily = 30; CurrentInstrCycles = 24;
46997: {{ uaecptr srca = m68k_getpc () + 2;
46998: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
46999: if ((srca & 1) != 0) {
47000: last_fault_for_exception_3 = srca;
47001: last_op_for_exception_3 = opcode;
47002: last_addr_for_exception_3 = m68k_getpc() + 4;
47003: Exception(3, 0, M68000_EXC_SRC_CPU);
47004: goto endlabel2706;
47005: }
47006: {{ uae_s16 src = get_word(srca);
47007: { uaecptr dsta = get_ilong_prefetch(4);
47008: if ((dsta & 1) != 0) {
47009: last_fault_for_exception_3 = dsta;
47010: last_op_for_exception_3 = opcode;
47011: last_addr_for_exception_3 = m68k_getpc() + 8;
47012: Exception(3, 0, M68000_EXC_SRC_CPU);
47013: goto endlabel2706;
47014: }
47015: { CLEAR_CZNV;
47016: SET_ZFLG (((uae_s16)(src)) == 0);
47017: SET_NFLG (((uae_s16)(src)) < 0);
47018: m68k_incpc(8);
47019: fill_prefetch_0 ();
47020: put_word(dsta,src);
47021: }}}}}}endlabel2706: ;
47022: return 24;
47023: }
47024: unsigned long REGPARAM2 CPUFUNC(op_33fb_5)(uae_u32 opcode) /* MOVE */
47025: {
47026: OpcodeFamily = 30; CurrentInstrCycles = 26;
47027: {{ uaecptr tmppc = m68k_getpc() + 2;
47028: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
47029: BusCyclePenalty += 2;
47030: if ((srca & 1) != 0) {
47031: last_fault_for_exception_3 = srca;
47032: last_op_for_exception_3 = opcode;
47033: last_addr_for_exception_3 = m68k_getpc() + 4;
47034: Exception(3, 0, M68000_EXC_SRC_CPU);
47035: goto endlabel2707;
47036: }
47037: {{ uae_s16 src = get_word(srca);
47038: { uaecptr dsta = get_ilong_prefetch(4);
47039: if ((dsta & 1) != 0) {
47040: last_fault_for_exception_3 = dsta;
47041: last_op_for_exception_3 = opcode;
47042: last_addr_for_exception_3 = m68k_getpc() + 8;
47043: Exception(3, 0, M68000_EXC_SRC_CPU);
47044: goto endlabel2707;
47045: }
47046: { CLEAR_CZNV;
47047: SET_ZFLG (((uae_s16)(src)) == 0);
47048: SET_NFLG (((uae_s16)(src)) < 0);
47049: m68k_incpc(8);
47050: fill_prefetch_0 ();
47051: put_word(dsta,src);
47052: }}}}}}endlabel2707: ;
47053: return 26;
47054: }
47055: unsigned long REGPARAM2 CPUFUNC(op_33fc_5)(uae_u32 opcode) /* MOVE */
47056: {
47057: OpcodeFamily = 30; CurrentInstrCycles = 20;
47058: {{ uae_s16 src = get_iword_prefetch(2);
47059: { uaecptr dsta = get_ilong_prefetch(4);
47060: if ((dsta & 1) != 0) {
47061: last_fault_for_exception_3 = dsta;
47062: last_op_for_exception_3 = opcode;
47063: last_addr_for_exception_3 = m68k_getpc() + 8;
47064: Exception(3, 0, M68000_EXC_SRC_CPU);
47065: goto endlabel2708;
47066: }
47067: { CLEAR_CZNV;
47068: SET_ZFLG (((uae_s16)(src)) == 0);
47069: SET_NFLG (((uae_s16)(src)) < 0);
47070: m68k_incpc(8);
47071: fill_prefetch_0 ();
47072: put_word(dsta,src);
47073: }}}}endlabel2708: ;
47074: return 20;
47075: }
47076: unsigned long REGPARAM2 CPUFUNC(op_4000_5)(uae_u32 opcode) /* NEGX */
47077: {
47078: uae_u32 srcreg = (opcode & 7);
47079: OpcodeFamily = 16; CurrentInstrCycles = 4;
47080: {{ uae_s8 src = m68k_dreg(regs, srcreg);
47081: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47082: { int flgs = ((uae_s8)(src)) < 0;
47083: int flgo = ((uae_s8)(0)) < 0;
47084: int flgn = ((uae_s8)(newv)) < 0;
47085: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47086: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47087: COPY_CARRY;
47088: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
47089: SET_NFLG (((uae_s8)(newv)) < 0);
47090: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
47091: }}}}m68k_incpc(2);
47092: fill_prefetch_2 ();
47093: return 4;
47094: }
47095: unsigned long REGPARAM2 CPUFUNC(op_4010_5)(uae_u32 opcode) /* NEGX */
47096: {
47097: uae_u32 srcreg = (opcode & 7);
47098: OpcodeFamily = 16; CurrentInstrCycles = 12;
47099: {{ uaecptr srca = m68k_areg(regs, srcreg);
47100: { uae_s8 src = get_byte(srca);
47101: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47102: { int flgs = ((uae_s8)(src)) < 0;
47103: int flgo = ((uae_s8)(0)) < 0;
47104: int flgn = ((uae_s8)(newv)) < 0;
47105: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47106: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47107: COPY_CARRY;
47108: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
47109: SET_NFLG (((uae_s8)(newv)) < 0);
47110: m68k_incpc(2);
47111: fill_prefetch_2 ();
47112: put_byte(srca,newv);
47113: }}}}}return 12;
47114: }
47115: unsigned long REGPARAM2 CPUFUNC(op_4018_5)(uae_u32 opcode) /* NEGX */
47116: {
47117: uae_u32 srcreg = (opcode & 7);
47118: OpcodeFamily = 16; CurrentInstrCycles = 12;
47119: {{ uaecptr srca = m68k_areg(regs, srcreg);
47120: { uae_s8 src = get_byte(srca);
47121: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
47122: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47123: { int flgs = ((uae_s8)(src)) < 0;
47124: int flgo = ((uae_s8)(0)) < 0;
47125: int flgn = ((uae_s8)(newv)) < 0;
47126: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47127: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47128: COPY_CARRY;
47129: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
47130: SET_NFLG (((uae_s8)(newv)) < 0);
47131: m68k_incpc(2);
47132: fill_prefetch_2 ();
47133: put_byte(srca,newv);
47134: }}}}}return 12;
47135: }
47136: unsigned long REGPARAM2 CPUFUNC(op_4020_5)(uae_u32 opcode) /* NEGX */
47137: {
47138: uae_u32 srcreg = (opcode & 7);
47139: OpcodeFamily = 16; CurrentInstrCycles = 14;
47140: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
47141: { uae_s8 src = get_byte(srca);
47142: m68k_areg (regs, srcreg) = srca;
47143: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47144: { int flgs = ((uae_s8)(src)) < 0;
47145: int flgo = ((uae_s8)(0)) < 0;
47146: int flgn = ((uae_s8)(newv)) < 0;
47147: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47148: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47149: COPY_CARRY;
47150: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
47151: SET_NFLG (((uae_s8)(newv)) < 0);
47152: m68k_incpc(2);
47153: fill_prefetch_2 ();
47154: put_byte(srca,newv);
47155: }}}}}return 14;
47156: }
47157: unsigned long REGPARAM2 CPUFUNC(op_4028_5)(uae_u32 opcode) /* NEGX */
47158: {
47159: uae_u32 srcreg = (opcode & 7);
47160: OpcodeFamily = 16; CurrentInstrCycles = 16;
47161: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
47162: { uae_s8 src = get_byte(srca);
47163: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47164: { int flgs = ((uae_s8)(src)) < 0;
47165: int flgo = ((uae_s8)(0)) < 0;
47166: int flgn = ((uae_s8)(newv)) < 0;
47167: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47168: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47169: COPY_CARRY;
47170: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
47171: SET_NFLG (((uae_s8)(newv)) < 0);
47172: m68k_incpc(4);
47173: fill_prefetch_0 ();
47174: put_byte(srca,newv);
47175: }}}}}return 16;
47176: }
47177: unsigned long REGPARAM2 CPUFUNC(op_4030_5)(uae_u32 opcode) /* NEGX */
47178: {
47179: uae_u32 srcreg = (opcode & 7);
47180: OpcodeFamily = 16; CurrentInstrCycles = 18;
47181: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
47182: BusCyclePenalty += 2;
47183: { uae_s8 src = get_byte(srca);
47184: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47185: { int flgs = ((uae_s8)(src)) < 0;
47186: int flgo = ((uae_s8)(0)) < 0;
47187: int flgn = ((uae_s8)(newv)) < 0;
47188: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47189: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47190: COPY_CARRY;
47191: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
47192: SET_NFLG (((uae_s8)(newv)) < 0);
47193: m68k_incpc(4);
47194: fill_prefetch_0 ();
47195: put_byte(srca,newv);
47196: }}}}}return 18;
47197: }
47198: unsigned long REGPARAM2 CPUFUNC(op_4038_5)(uae_u32 opcode) /* NEGX */
47199: {
47200: OpcodeFamily = 16; CurrentInstrCycles = 16;
47201: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
47202: { uae_s8 src = get_byte(srca);
47203: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47204: { int flgs = ((uae_s8)(src)) < 0;
47205: int flgo = ((uae_s8)(0)) < 0;
47206: int flgn = ((uae_s8)(newv)) < 0;
47207: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47208: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47209: COPY_CARRY;
47210: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
47211: SET_NFLG (((uae_s8)(newv)) < 0);
47212: m68k_incpc(4);
47213: fill_prefetch_0 ();
47214: put_byte(srca,newv);
47215: }}}}}return 16;
47216: }
47217: unsigned long REGPARAM2 CPUFUNC(op_4039_5)(uae_u32 opcode) /* NEGX */
47218: {
47219: OpcodeFamily = 16; CurrentInstrCycles = 20;
47220: {{ uaecptr srca = get_ilong_prefetch(2);
47221: { uae_s8 src = get_byte(srca);
47222: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47223: { int flgs = ((uae_s8)(src)) < 0;
47224: int flgo = ((uae_s8)(0)) < 0;
47225: int flgn = ((uae_s8)(newv)) < 0;
47226: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47227: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47228: COPY_CARRY;
47229: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
47230: SET_NFLG (((uae_s8)(newv)) < 0);
47231: m68k_incpc(6);
47232: fill_prefetch_0 ();
47233: put_byte(srca,newv);
47234: }}}}}return 20;
47235: }
47236: unsigned long REGPARAM2 CPUFUNC(op_4040_5)(uae_u32 opcode) /* NEGX */
47237: {
47238: uae_u32 srcreg = (opcode & 7);
47239: OpcodeFamily = 16; CurrentInstrCycles = 4;
47240: {{ uae_s16 src = m68k_dreg(regs, srcreg);
47241: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47242: { int flgs = ((uae_s16)(src)) < 0;
47243: int flgo = ((uae_s16)(0)) < 0;
47244: int flgn = ((uae_s16)(newv)) < 0;
47245: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47246: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47247: COPY_CARRY;
47248: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
47249: SET_NFLG (((uae_s16)(newv)) < 0);
47250: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
47251: }}}}m68k_incpc(2);
47252: fill_prefetch_2 ();
47253: return 4;
47254: }
47255: unsigned long REGPARAM2 CPUFUNC(op_4050_5)(uae_u32 opcode) /* NEGX */
47256: {
47257: uae_u32 srcreg = (opcode & 7);
47258: OpcodeFamily = 16; CurrentInstrCycles = 12;
47259: {{ uaecptr srca = m68k_areg(regs, srcreg);
47260: if ((srca & 1) != 0) {
47261: last_fault_for_exception_3 = srca;
47262: last_op_for_exception_3 = opcode;
47263: last_addr_for_exception_3 = m68k_getpc() + 2;
47264: Exception(3, 0, M68000_EXC_SRC_CPU);
47265: goto endlabel2718;
47266: }
47267: {{ uae_s16 src = get_word(srca);
47268: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47269: { int flgs = ((uae_s16)(src)) < 0;
47270: int flgo = ((uae_s16)(0)) < 0;
47271: int flgn = ((uae_s16)(newv)) < 0;
47272: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47273: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47274: COPY_CARRY;
47275: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
47276: SET_NFLG (((uae_s16)(newv)) < 0);
47277: m68k_incpc(2);
47278: fill_prefetch_2 ();
47279: put_word(srca,newv);
47280: }}}}}}endlabel2718: ;
47281: return 12;
47282: }
47283: unsigned long REGPARAM2 CPUFUNC(op_4058_5)(uae_u32 opcode) /* NEGX */
47284: {
47285: uae_u32 srcreg = (opcode & 7);
47286: OpcodeFamily = 16; CurrentInstrCycles = 12;
47287: {{ uaecptr srca = m68k_areg(regs, srcreg);
47288: if ((srca & 1) != 0) {
47289: last_fault_for_exception_3 = srca;
47290: last_op_for_exception_3 = opcode;
47291: last_addr_for_exception_3 = m68k_getpc() + 2;
47292: Exception(3, 0, M68000_EXC_SRC_CPU);
47293: goto endlabel2719;
47294: }
47295: {{ uae_s16 src = get_word(srca);
47296: m68k_areg(regs, srcreg) += 2;
47297: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47298: { int flgs = ((uae_s16)(src)) < 0;
47299: int flgo = ((uae_s16)(0)) < 0;
47300: int flgn = ((uae_s16)(newv)) < 0;
47301: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47302: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47303: COPY_CARRY;
47304: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
47305: SET_NFLG (((uae_s16)(newv)) < 0);
47306: m68k_incpc(2);
47307: fill_prefetch_2 ();
47308: put_word(srca,newv);
47309: }}}}}}endlabel2719: ;
47310: return 12;
47311: }
47312: unsigned long REGPARAM2 CPUFUNC(op_4060_5)(uae_u32 opcode) /* NEGX */
47313: {
47314: uae_u32 srcreg = (opcode & 7);
47315: OpcodeFamily = 16; CurrentInstrCycles = 14;
47316: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
47317: if ((srca & 1) != 0) {
47318: last_fault_for_exception_3 = srca;
47319: last_op_for_exception_3 = opcode;
47320: last_addr_for_exception_3 = m68k_getpc() + 2;
47321: Exception(3, 0, M68000_EXC_SRC_CPU);
47322: goto endlabel2720;
47323: }
47324: {{ uae_s16 src = get_word(srca);
47325: m68k_areg (regs, srcreg) = srca;
47326: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47327: { int flgs = ((uae_s16)(src)) < 0;
47328: int flgo = ((uae_s16)(0)) < 0;
47329: int flgn = ((uae_s16)(newv)) < 0;
47330: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47331: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47332: COPY_CARRY;
47333: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
47334: SET_NFLG (((uae_s16)(newv)) < 0);
47335: m68k_incpc(2);
47336: fill_prefetch_2 ();
47337: put_word(srca,newv);
47338: }}}}}}endlabel2720: ;
47339: return 14;
47340: }
47341: unsigned long REGPARAM2 CPUFUNC(op_4068_5)(uae_u32 opcode) /* NEGX */
47342: {
47343: uae_u32 srcreg = (opcode & 7);
47344: OpcodeFamily = 16; CurrentInstrCycles = 16;
47345: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
47346: if ((srca & 1) != 0) {
47347: last_fault_for_exception_3 = srca;
47348: last_op_for_exception_3 = opcode;
47349: last_addr_for_exception_3 = m68k_getpc() + 4;
47350: Exception(3, 0, M68000_EXC_SRC_CPU);
47351: goto endlabel2721;
47352: }
47353: {{ uae_s16 src = get_word(srca);
47354: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47355: { int flgs = ((uae_s16)(src)) < 0;
47356: int flgo = ((uae_s16)(0)) < 0;
47357: int flgn = ((uae_s16)(newv)) < 0;
47358: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47359: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47360: COPY_CARRY;
47361: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
47362: SET_NFLG (((uae_s16)(newv)) < 0);
47363: m68k_incpc(4);
47364: fill_prefetch_0 ();
47365: put_word(srca,newv);
47366: }}}}}}endlabel2721: ;
47367: return 16;
47368: }
47369: unsigned long REGPARAM2 CPUFUNC(op_4070_5)(uae_u32 opcode) /* NEGX */
47370: {
47371: uae_u32 srcreg = (opcode & 7);
47372: OpcodeFamily = 16; CurrentInstrCycles = 18;
47373: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
47374: BusCyclePenalty += 2;
47375: if ((srca & 1) != 0) {
47376: last_fault_for_exception_3 = srca;
47377: last_op_for_exception_3 = opcode;
47378: last_addr_for_exception_3 = m68k_getpc() + 4;
47379: Exception(3, 0, M68000_EXC_SRC_CPU);
47380: goto endlabel2722;
47381: }
47382: {{ uae_s16 src = get_word(srca);
47383: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47384: { int flgs = ((uae_s16)(src)) < 0;
47385: int flgo = ((uae_s16)(0)) < 0;
47386: int flgn = ((uae_s16)(newv)) < 0;
47387: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47388: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47389: COPY_CARRY;
47390: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
47391: SET_NFLG (((uae_s16)(newv)) < 0);
47392: m68k_incpc(4);
47393: fill_prefetch_0 ();
47394: put_word(srca,newv);
47395: }}}}}}endlabel2722: ;
47396: return 18;
47397: }
47398: unsigned long REGPARAM2 CPUFUNC(op_4078_5)(uae_u32 opcode) /* NEGX */
47399: {
47400: OpcodeFamily = 16; CurrentInstrCycles = 16;
47401: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
47402: if ((srca & 1) != 0) {
47403: last_fault_for_exception_3 = srca;
47404: last_op_for_exception_3 = opcode;
47405: last_addr_for_exception_3 = m68k_getpc() + 4;
47406: Exception(3, 0, M68000_EXC_SRC_CPU);
47407: goto endlabel2723;
47408: }
47409: {{ uae_s16 src = get_word(srca);
47410: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47411: { int flgs = ((uae_s16)(src)) < 0;
47412: int flgo = ((uae_s16)(0)) < 0;
47413: int flgn = ((uae_s16)(newv)) < 0;
47414: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47415: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47416: COPY_CARRY;
47417: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
47418: SET_NFLG (((uae_s16)(newv)) < 0);
47419: m68k_incpc(4);
47420: fill_prefetch_0 ();
47421: put_word(srca,newv);
47422: }}}}}}endlabel2723: ;
47423: return 16;
47424: }
47425: unsigned long REGPARAM2 CPUFUNC(op_4079_5)(uae_u32 opcode) /* NEGX */
47426: {
47427: OpcodeFamily = 16; CurrentInstrCycles = 20;
47428: {{ uaecptr srca = get_ilong_prefetch(2);
47429: if ((srca & 1) != 0) {
47430: last_fault_for_exception_3 = srca;
47431: last_op_for_exception_3 = opcode;
47432: last_addr_for_exception_3 = m68k_getpc() + 6;
47433: Exception(3, 0, M68000_EXC_SRC_CPU);
47434: goto endlabel2724;
47435: }
47436: {{ uae_s16 src = get_word(srca);
47437: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47438: { int flgs = ((uae_s16)(src)) < 0;
47439: int flgo = ((uae_s16)(0)) < 0;
47440: int flgn = ((uae_s16)(newv)) < 0;
47441: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47442: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47443: COPY_CARRY;
47444: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
47445: SET_NFLG (((uae_s16)(newv)) < 0);
47446: m68k_incpc(6);
47447: fill_prefetch_0 ();
47448: put_word(srca,newv);
47449: }}}}}}endlabel2724: ;
47450: return 20;
47451: }
47452: unsigned long REGPARAM2 CPUFUNC(op_4080_5)(uae_u32 opcode) /* NEGX */
47453: {
47454: uae_u32 srcreg = (opcode & 7);
47455: OpcodeFamily = 16; CurrentInstrCycles = 6;
47456: {{ uae_s32 src = m68k_dreg(regs, srcreg);
47457: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47458: { int flgs = ((uae_s32)(src)) < 0;
47459: int flgo = ((uae_s32)(0)) < 0;
47460: int flgn = ((uae_s32)(newv)) < 0;
47461: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47462: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47463: COPY_CARRY;
47464: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
47465: SET_NFLG (((uae_s32)(newv)) < 0);
47466: m68k_dreg(regs, srcreg) = (newv);
47467: }}}}m68k_incpc(2);
47468: fill_prefetch_2 ();
47469: return 6;
47470: }
47471: unsigned long REGPARAM2 CPUFUNC(op_4090_5)(uae_u32 opcode) /* NEGX */
47472: {
47473: uae_u32 srcreg = (opcode & 7);
47474: OpcodeFamily = 16; CurrentInstrCycles = 20;
47475: {{ uaecptr srca = m68k_areg(regs, srcreg);
47476: if ((srca & 1) != 0) {
47477: last_fault_for_exception_3 = srca;
47478: last_op_for_exception_3 = opcode;
47479: last_addr_for_exception_3 = m68k_getpc() + 2;
47480: Exception(3, 0, M68000_EXC_SRC_CPU);
47481: goto endlabel2726;
47482: }
47483: {{ uae_s32 src = get_long(srca);
47484: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47485: { int flgs = ((uae_s32)(src)) < 0;
47486: int flgo = ((uae_s32)(0)) < 0;
47487: int flgn = ((uae_s32)(newv)) < 0;
47488: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47489: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47490: COPY_CARRY;
47491: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
47492: SET_NFLG (((uae_s32)(newv)) < 0);
47493: m68k_incpc(2);
47494: fill_prefetch_2 ();
47495: put_long(srca,newv);
47496: }}}}}}endlabel2726: ;
47497: return 20;
47498: }
47499: unsigned long REGPARAM2 CPUFUNC(op_4098_5)(uae_u32 opcode) /* NEGX */
47500: {
47501: uae_u32 srcreg = (opcode & 7);
47502: OpcodeFamily = 16; CurrentInstrCycles = 20;
47503: {{ uaecptr srca = m68k_areg(regs, srcreg);
47504: if ((srca & 1) != 0) {
47505: last_fault_for_exception_3 = srca;
47506: last_op_for_exception_3 = opcode;
47507: last_addr_for_exception_3 = m68k_getpc() + 2;
47508: Exception(3, 0, M68000_EXC_SRC_CPU);
47509: goto endlabel2727;
47510: }
47511: {{ uae_s32 src = get_long(srca);
47512: m68k_areg(regs, srcreg) += 4;
47513: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47514: { int flgs = ((uae_s32)(src)) < 0;
47515: int flgo = ((uae_s32)(0)) < 0;
47516: int flgn = ((uae_s32)(newv)) < 0;
47517: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47518: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47519: COPY_CARRY;
47520: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
47521: SET_NFLG (((uae_s32)(newv)) < 0);
47522: m68k_incpc(2);
47523: fill_prefetch_2 ();
47524: put_long(srca,newv);
47525: }}}}}}endlabel2727: ;
47526: return 20;
47527: }
47528: unsigned long REGPARAM2 CPUFUNC(op_40a0_5)(uae_u32 opcode) /* NEGX */
47529: {
47530: uae_u32 srcreg = (opcode & 7);
47531: OpcodeFamily = 16; CurrentInstrCycles = 22;
47532: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
47533: if ((srca & 1) != 0) {
47534: last_fault_for_exception_3 = srca;
47535: last_op_for_exception_3 = opcode;
47536: last_addr_for_exception_3 = m68k_getpc() + 2;
47537: Exception(3, 0, M68000_EXC_SRC_CPU);
47538: goto endlabel2728;
47539: }
47540: {{ uae_s32 src = get_long(srca);
47541: m68k_areg (regs, srcreg) = srca;
47542: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47543: { int flgs = ((uae_s32)(src)) < 0;
47544: int flgo = ((uae_s32)(0)) < 0;
47545: int flgn = ((uae_s32)(newv)) < 0;
47546: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47547: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47548: COPY_CARRY;
47549: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
47550: SET_NFLG (((uae_s32)(newv)) < 0);
47551: m68k_incpc(2);
47552: fill_prefetch_2 ();
47553: put_long(srca,newv);
47554: }}}}}}endlabel2728: ;
47555: return 22;
47556: }
47557: unsigned long REGPARAM2 CPUFUNC(op_40a8_5)(uae_u32 opcode) /* NEGX */
47558: {
47559: uae_u32 srcreg = (opcode & 7);
47560: OpcodeFamily = 16; CurrentInstrCycles = 24;
47561: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
47562: if ((srca & 1) != 0) {
47563: last_fault_for_exception_3 = srca;
47564: last_op_for_exception_3 = opcode;
47565: last_addr_for_exception_3 = m68k_getpc() + 4;
47566: Exception(3, 0, M68000_EXC_SRC_CPU);
47567: goto endlabel2729;
47568: }
47569: {{ uae_s32 src = get_long(srca);
47570: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47571: { int flgs = ((uae_s32)(src)) < 0;
47572: int flgo = ((uae_s32)(0)) < 0;
47573: int flgn = ((uae_s32)(newv)) < 0;
47574: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47575: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47576: COPY_CARRY;
47577: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
47578: SET_NFLG (((uae_s32)(newv)) < 0);
47579: m68k_incpc(4);
47580: fill_prefetch_0 ();
47581: put_long(srca,newv);
47582: }}}}}}endlabel2729: ;
47583: return 24;
47584: }
47585: unsigned long REGPARAM2 CPUFUNC(op_40b0_5)(uae_u32 opcode) /* NEGX */
47586: {
47587: uae_u32 srcreg = (opcode & 7);
47588: OpcodeFamily = 16; CurrentInstrCycles = 26;
47589: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
47590: BusCyclePenalty += 2;
47591: if ((srca & 1) != 0) {
47592: last_fault_for_exception_3 = srca;
47593: last_op_for_exception_3 = opcode;
47594: last_addr_for_exception_3 = m68k_getpc() + 4;
47595: Exception(3, 0, M68000_EXC_SRC_CPU);
47596: goto endlabel2730;
47597: }
47598: {{ uae_s32 src = get_long(srca);
47599: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47600: { int flgs = ((uae_s32)(src)) < 0;
47601: int flgo = ((uae_s32)(0)) < 0;
47602: int flgn = ((uae_s32)(newv)) < 0;
47603: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47604: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47605: COPY_CARRY;
47606: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
47607: SET_NFLG (((uae_s32)(newv)) < 0);
47608: m68k_incpc(4);
47609: fill_prefetch_0 ();
47610: put_long(srca,newv);
47611: }}}}}}endlabel2730: ;
47612: return 26;
47613: }
47614: unsigned long REGPARAM2 CPUFUNC(op_40b8_5)(uae_u32 opcode) /* NEGX */
47615: {
47616: OpcodeFamily = 16; CurrentInstrCycles = 24;
47617: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
47618: if ((srca & 1) != 0) {
47619: last_fault_for_exception_3 = srca;
47620: last_op_for_exception_3 = opcode;
47621: last_addr_for_exception_3 = m68k_getpc() + 4;
47622: Exception(3, 0, M68000_EXC_SRC_CPU);
47623: goto endlabel2731;
47624: }
47625: {{ uae_s32 src = get_long(srca);
47626: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47627: { int flgs = ((uae_s32)(src)) < 0;
47628: int flgo = ((uae_s32)(0)) < 0;
47629: int flgn = ((uae_s32)(newv)) < 0;
47630: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47631: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47632: COPY_CARRY;
47633: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
47634: SET_NFLG (((uae_s32)(newv)) < 0);
47635: m68k_incpc(4);
47636: fill_prefetch_0 ();
47637: put_long(srca,newv);
47638: }}}}}}endlabel2731: ;
47639: return 24;
47640: }
47641: unsigned long REGPARAM2 CPUFUNC(op_40b9_5)(uae_u32 opcode) /* NEGX */
47642: {
47643: OpcodeFamily = 16; CurrentInstrCycles = 28;
47644: {{ uaecptr srca = get_ilong_prefetch(2);
47645: if ((srca & 1) != 0) {
47646: last_fault_for_exception_3 = srca;
47647: last_op_for_exception_3 = opcode;
47648: last_addr_for_exception_3 = m68k_getpc() + 6;
47649: Exception(3, 0, M68000_EXC_SRC_CPU);
47650: goto endlabel2732;
47651: }
47652: {{ uae_s32 src = get_long(srca);
47653: { uae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);
47654: { int flgs = ((uae_s32)(src)) < 0;
47655: int flgo = ((uae_s32)(0)) < 0;
47656: int flgn = ((uae_s32)(newv)) < 0;
47657: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
47658: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
47659: COPY_CARRY;
47660: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
47661: SET_NFLG (((uae_s32)(newv)) < 0);
47662: m68k_incpc(6);
47663: fill_prefetch_0 ();
47664: put_long(srca,newv);
47665: }}}}}}endlabel2732: ;
47666: return 28;
47667: }
47668: unsigned long REGPARAM2 CPUFUNC(op_40c0_5)(uae_u32 opcode) /* MVSR2 */
47669: {
47670: uae_u32 srcreg = (opcode & 7);
47671: OpcodeFamily = 32; CurrentInstrCycles = 6;
47672: {{ MakeSR();
47673: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
47674: }}m68k_incpc(2);
47675: fill_prefetch_2 ();
47676: return 6;
47677: }
47678: unsigned long REGPARAM2 CPUFUNC(op_40d0_5)(uae_u32 opcode) /* MVSR2 */
47679: {
47680: uae_u32 srcreg = (opcode & 7);
47681: OpcodeFamily = 32; CurrentInstrCycles = 12;
47682: {{ uaecptr srca = m68k_areg(regs, srcreg);
47683: if ((srca & 1) != 0) {
47684: last_fault_for_exception_3 = srca;
47685: last_op_for_exception_3 = opcode;
47686: last_addr_for_exception_3 = m68k_getpc() + 2;
47687: Exception(3, 0, M68000_EXC_SRC_CPU);
47688: goto endlabel2734;
47689: }
47690: { MakeSR();
47691: m68k_incpc(2);
47692: fill_prefetch_2 ();
47693: put_word(srca,regs.sr);
47694: }}}endlabel2734: ;
47695: return 12;
47696: }
47697: unsigned long REGPARAM2 CPUFUNC(op_40d8_5)(uae_u32 opcode) /* MVSR2 */
47698: {
47699: uae_u32 srcreg = (opcode & 7);
47700: OpcodeFamily = 32; CurrentInstrCycles = 12;
47701: {{ uaecptr srca = m68k_areg(regs, srcreg);
47702: if ((srca & 1) != 0) {
47703: last_fault_for_exception_3 = srca;
47704: last_op_for_exception_3 = opcode;
47705: last_addr_for_exception_3 = m68k_getpc() + 2;
47706: Exception(3, 0, M68000_EXC_SRC_CPU);
47707: goto endlabel2735;
47708: }
47709: { m68k_areg(regs, srcreg) += 2;
47710: MakeSR();
47711: m68k_incpc(2);
47712: fill_prefetch_2 ();
47713: put_word(srca,regs.sr);
47714: }}}endlabel2735: ;
47715: return 12;
47716: }
47717: unsigned long REGPARAM2 CPUFUNC(op_40e0_5)(uae_u32 opcode) /* MVSR2 */
47718: {
47719: uae_u32 srcreg = (opcode & 7);
47720: OpcodeFamily = 32; CurrentInstrCycles = 14;
47721: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
47722: if ((srca & 1) != 0) {
47723: last_fault_for_exception_3 = srca;
47724: last_op_for_exception_3 = opcode;
47725: last_addr_for_exception_3 = m68k_getpc() + 2;
47726: Exception(3, 0, M68000_EXC_SRC_CPU);
47727: goto endlabel2736;
47728: }
47729: { m68k_areg (regs, srcreg) = srca;
47730: MakeSR();
47731: m68k_incpc(2);
47732: fill_prefetch_2 ();
47733: put_word(srca,regs.sr);
47734: }}}endlabel2736: ;
47735: return 14;
47736: }
47737: unsigned long REGPARAM2 CPUFUNC(op_40e8_5)(uae_u32 opcode) /* MVSR2 */
47738: {
47739: uae_u32 srcreg = (opcode & 7);
47740: OpcodeFamily = 32; CurrentInstrCycles = 16;
47741: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
47742: if ((srca & 1) != 0) {
47743: last_fault_for_exception_3 = srca;
47744: last_op_for_exception_3 = opcode;
47745: last_addr_for_exception_3 = m68k_getpc() + 4;
47746: Exception(3, 0, M68000_EXC_SRC_CPU);
47747: goto endlabel2737;
47748: }
47749: { MakeSR();
47750: m68k_incpc(4);
47751: fill_prefetch_0 ();
47752: put_word(srca,regs.sr);
47753: }}}endlabel2737: ;
47754: return 16;
47755: }
47756: unsigned long REGPARAM2 CPUFUNC(op_40f0_5)(uae_u32 opcode) /* MVSR2 */
47757: {
47758: uae_u32 srcreg = (opcode & 7);
47759: OpcodeFamily = 32; CurrentInstrCycles = 18;
47760: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
47761: BusCyclePenalty += 2;
47762: if ((srca & 1) != 0) {
47763: last_fault_for_exception_3 = srca;
47764: last_op_for_exception_3 = opcode;
47765: last_addr_for_exception_3 = m68k_getpc() + 4;
47766: Exception(3, 0, M68000_EXC_SRC_CPU);
47767: goto endlabel2738;
47768: }
47769: { MakeSR();
47770: m68k_incpc(4);
47771: fill_prefetch_0 ();
47772: put_word(srca,regs.sr);
47773: }}}endlabel2738: ;
47774: return 18;
47775: }
47776: unsigned long REGPARAM2 CPUFUNC(op_40f8_5)(uae_u32 opcode) /* MVSR2 */
47777: {
47778: OpcodeFamily = 32; CurrentInstrCycles = 16;
47779: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
47780: if ((srca & 1) != 0) {
47781: last_fault_for_exception_3 = srca;
47782: last_op_for_exception_3 = opcode;
47783: last_addr_for_exception_3 = m68k_getpc() + 4;
47784: Exception(3, 0, M68000_EXC_SRC_CPU);
47785: goto endlabel2739;
47786: }
47787: { MakeSR();
47788: m68k_incpc(4);
47789: fill_prefetch_0 ();
47790: put_word(srca,regs.sr);
47791: }}}endlabel2739: ;
47792: return 16;
47793: }
47794: unsigned long REGPARAM2 CPUFUNC(op_40f9_5)(uae_u32 opcode) /* MVSR2 */
47795: {
47796: OpcodeFamily = 32; CurrentInstrCycles = 20;
47797: {{ uaecptr srca = get_ilong_prefetch(2);
47798: if ((srca & 1) != 0) {
47799: last_fault_for_exception_3 = srca;
47800: last_op_for_exception_3 = opcode;
47801: last_addr_for_exception_3 = m68k_getpc() + 6;
47802: Exception(3, 0, M68000_EXC_SRC_CPU);
47803: goto endlabel2740;
47804: }
47805: { MakeSR();
47806: m68k_incpc(6);
47807: fill_prefetch_0 ();
47808: put_word(srca,regs.sr);
47809: }}}endlabel2740: ;
47810: return 20;
47811: }
47812: unsigned long REGPARAM2 CPUFUNC(op_4180_5)(uae_u32 opcode) /* CHK */
47813: {
47814: uae_u32 srcreg = (opcode & 7);
47815: uae_u32 dstreg = (opcode >> 9) & 7;
47816: OpcodeFamily = 80; CurrentInstrCycles = 10;
47817: { uaecptr oldpc = m68k_getpc();
47818: { uae_s16 src = m68k_dreg(regs, srcreg);
47819: { uae_s16 dst = m68k_dreg(regs, dstreg);
47820: m68k_incpc(2);
47821: fill_prefetch_2 ();
47822: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2741; }
47823: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2741; }
47824: }}}endlabel2741: ;
47825: return 10;
47826: }
47827: unsigned long REGPARAM2 CPUFUNC(op_4190_5)(uae_u32 opcode) /* CHK */
47828: {
47829: uae_u32 srcreg = (opcode & 7);
47830: uae_u32 dstreg = (opcode >> 9) & 7;
47831: OpcodeFamily = 80; CurrentInstrCycles = 14;
47832: { uaecptr oldpc = m68k_getpc();
47833: { uaecptr srca = m68k_areg(regs, srcreg);
47834: if ((srca & 1) != 0) {
47835: last_fault_for_exception_3 = srca;
47836: last_op_for_exception_3 = opcode;
47837: last_addr_for_exception_3 = m68k_getpc() + 2;
47838: Exception(3, 0, M68000_EXC_SRC_CPU);
47839: goto endlabel2742;
47840: }
47841: {{ uae_s16 src = get_word(srca);
47842: { uae_s16 dst = m68k_dreg(regs, dstreg);
47843: m68k_incpc(2);
47844: fill_prefetch_2 ();
47845: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2742; }
47846: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2742; }
47847: }}}}}endlabel2742: ;
47848: return 14;
47849: }
47850: unsigned long REGPARAM2 CPUFUNC(op_4198_5)(uae_u32 opcode) /* CHK */
47851: {
47852: uae_u32 srcreg = (opcode & 7);
47853: uae_u32 dstreg = (opcode >> 9) & 7;
47854: OpcodeFamily = 80; CurrentInstrCycles = 14;
47855: { uaecptr oldpc = m68k_getpc();
47856: { uaecptr srca = m68k_areg(regs, srcreg);
47857: if ((srca & 1) != 0) {
47858: last_fault_for_exception_3 = srca;
47859: last_op_for_exception_3 = opcode;
47860: last_addr_for_exception_3 = m68k_getpc() + 2;
47861: Exception(3, 0, M68000_EXC_SRC_CPU);
47862: goto endlabel2743;
47863: }
47864: {{ uae_s16 src = get_word(srca);
47865: m68k_areg(regs, srcreg) += 2;
47866: { uae_s16 dst = m68k_dreg(regs, dstreg);
47867: m68k_incpc(2);
47868: fill_prefetch_2 ();
47869: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2743; }
47870: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2743; }
47871: }}}}}endlabel2743: ;
47872: return 14;
47873: }
47874: unsigned long REGPARAM2 CPUFUNC(op_41a0_5)(uae_u32 opcode) /* CHK */
47875: {
47876: uae_u32 srcreg = (opcode & 7);
47877: uae_u32 dstreg = (opcode >> 9) & 7;
47878: OpcodeFamily = 80; CurrentInstrCycles = 16;
47879: { uaecptr oldpc = m68k_getpc();
47880: { uaecptr srca = m68k_areg(regs, srcreg) - 2;
47881: if ((srca & 1) != 0) {
47882: last_fault_for_exception_3 = srca;
47883: last_op_for_exception_3 = opcode;
47884: last_addr_for_exception_3 = m68k_getpc() + 2;
47885: Exception(3, 0, M68000_EXC_SRC_CPU);
47886: goto endlabel2744;
47887: }
47888: {{ uae_s16 src = get_word(srca);
47889: m68k_areg (regs, srcreg) = srca;
47890: { uae_s16 dst = m68k_dreg(regs, dstreg);
47891: m68k_incpc(2);
47892: fill_prefetch_2 ();
47893: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2744; }
47894: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2744; }
47895: }}}}}endlabel2744: ;
47896: return 16;
47897: }
47898: unsigned long REGPARAM2 CPUFUNC(op_41a8_5)(uae_u32 opcode) /* CHK */
47899: {
47900: uae_u32 srcreg = (opcode & 7);
47901: uae_u32 dstreg = (opcode >> 9) & 7;
47902: OpcodeFamily = 80; CurrentInstrCycles = 18;
47903: { uaecptr oldpc = m68k_getpc();
47904: { uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
47905: if ((srca & 1) != 0) {
47906: last_fault_for_exception_3 = srca;
47907: last_op_for_exception_3 = opcode;
47908: last_addr_for_exception_3 = m68k_getpc() + 4;
47909: Exception(3, 0, M68000_EXC_SRC_CPU);
47910: goto endlabel2745;
47911: }
47912: {{ uae_s16 src = get_word(srca);
47913: { uae_s16 dst = m68k_dreg(regs, dstreg);
47914: m68k_incpc(4);
47915: fill_prefetch_0 ();
47916: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2745; }
47917: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2745; }
47918: }}}}}endlabel2745: ;
47919: return 18;
47920: }
47921: unsigned long REGPARAM2 CPUFUNC(op_41b0_5)(uae_u32 opcode) /* CHK */
47922: {
47923: uae_u32 srcreg = (opcode & 7);
47924: uae_u32 dstreg = (opcode >> 9) & 7;
47925: OpcodeFamily = 80; CurrentInstrCycles = 20;
47926: { uaecptr oldpc = m68k_getpc();
47927: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
47928: BusCyclePenalty += 2;
47929: if ((srca & 1) != 0) {
47930: last_fault_for_exception_3 = srca;
47931: last_op_for_exception_3 = opcode;
47932: last_addr_for_exception_3 = m68k_getpc() + 4;
47933: Exception(3, 0, M68000_EXC_SRC_CPU);
47934: goto endlabel2746;
47935: }
47936: {{ uae_s16 src = get_word(srca);
47937: { uae_s16 dst = m68k_dreg(regs, dstreg);
47938: m68k_incpc(4);
47939: fill_prefetch_0 ();
47940: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2746; }
47941: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2746; }
47942: }}}}}endlabel2746: ;
47943: return 20;
47944: }
47945: unsigned long REGPARAM2 CPUFUNC(op_41b8_5)(uae_u32 opcode) /* CHK */
47946: {
47947: uae_u32 dstreg = (opcode >> 9) & 7;
47948: OpcodeFamily = 80; CurrentInstrCycles = 18;
47949: { uaecptr oldpc = m68k_getpc();
47950: { uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
47951: if ((srca & 1) != 0) {
47952: last_fault_for_exception_3 = srca;
47953: last_op_for_exception_3 = opcode;
47954: last_addr_for_exception_3 = m68k_getpc() + 4;
47955: Exception(3, 0, M68000_EXC_SRC_CPU);
47956: goto endlabel2747;
47957: }
47958: {{ uae_s16 src = get_word(srca);
47959: { uae_s16 dst = m68k_dreg(regs, dstreg);
47960: m68k_incpc(4);
47961: fill_prefetch_0 ();
47962: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2747; }
47963: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2747; }
47964: }}}}}endlabel2747: ;
47965: return 18;
47966: }
47967: unsigned long REGPARAM2 CPUFUNC(op_41b9_5)(uae_u32 opcode) /* CHK */
47968: {
47969: uae_u32 dstreg = (opcode >> 9) & 7;
47970: OpcodeFamily = 80; CurrentInstrCycles = 22;
47971: { uaecptr oldpc = m68k_getpc();
47972: { uaecptr srca = get_ilong_prefetch(2);
47973: if ((srca & 1) != 0) {
47974: last_fault_for_exception_3 = srca;
47975: last_op_for_exception_3 = opcode;
47976: last_addr_for_exception_3 = m68k_getpc() + 6;
47977: Exception(3, 0, M68000_EXC_SRC_CPU);
47978: goto endlabel2748;
47979: }
47980: {{ uae_s16 src = get_word(srca);
47981: { uae_s16 dst = m68k_dreg(regs, dstreg);
47982: m68k_incpc(6);
47983: fill_prefetch_0 ();
47984: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2748; }
47985: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2748; }
47986: }}}}}endlabel2748: ;
47987: return 22;
47988: }
47989: unsigned long REGPARAM2 CPUFUNC(op_41ba_5)(uae_u32 opcode) /* CHK */
47990: {
47991: uae_u32 dstreg = (opcode >> 9) & 7;
47992: OpcodeFamily = 80; CurrentInstrCycles = 18;
47993: { uaecptr oldpc = m68k_getpc();
47994: { uaecptr srca = m68k_getpc () + 2;
47995: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
47996: if ((srca & 1) != 0) {
47997: last_fault_for_exception_3 = srca;
47998: last_op_for_exception_3 = opcode;
47999: last_addr_for_exception_3 = m68k_getpc() + 4;
48000: Exception(3, 0, M68000_EXC_SRC_CPU);
48001: goto endlabel2749;
48002: }
48003: {{ uae_s16 src = get_word(srca);
48004: { uae_s16 dst = m68k_dreg(regs, dstreg);
48005: m68k_incpc(4);
48006: fill_prefetch_0 ();
48007: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2749; }
48008: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2749; }
48009: }}}}}endlabel2749: ;
48010: return 18;
48011: }
48012: unsigned long REGPARAM2 CPUFUNC(op_41bb_5)(uae_u32 opcode) /* CHK */
48013: {
48014: uae_u32 dstreg = (opcode >> 9) & 7;
48015: OpcodeFamily = 80; CurrentInstrCycles = 20;
48016: { uaecptr oldpc = m68k_getpc();
48017: { uaecptr tmppc = m68k_getpc() + 2;
48018: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
48019: BusCyclePenalty += 2;
48020: if ((srca & 1) != 0) {
48021: last_fault_for_exception_3 = srca;
48022: last_op_for_exception_3 = opcode;
48023: last_addr_for_exception_3 = m68k_getpc() + 4;
48024: Exception(3, 0, M68000_EXC_SRC_CPU);
48025: goto endlabel2750;
48026: }
48027: {{ uae_s16 src = get_word(srca);
48028: { uae_s16 dst = m68k_dreg(regs, dstreg);
48029: m68k_incpc(4);
48030: fill_prefetch_0 ();
48031: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2750; }
48032: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2750; }
48033: }}}}}endlabel2750: ;
48034: return 20;
48035: }
48036: unsigned long REGPARAM2 CPUFUNC(op_41bc_5)(uae_u32 opcode) /* CHK */
48037: {
48038: uae_u32 dstreg = (opcode >> 9) & 7;
48039: OpcodeFamily = 80; CurrentInstrCycles = 14;
48040: { uaecptr oldpc = m68k_getpc();
48041: { uae_s16 src = get_iword_prefetch(2);
48042: { uae_s16 dst = m68k_dreg(regs, dstreg);
48043: m68k_incpc(4);
48044: fill_prefetch_0 ();
48045: if ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2751; }
48046: else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2751; }
48047: }}}endlabel2751: ;
48048: return 14;
48049: }
48050: unsigned long REGPARAM2 CPUFUNC(op_41d0_5)(uae_u32 opcode) /* LEA */
48051: {
48052: uae_u32 srcreg = (opcode & 7);
48053: uae_u32 dstreg = (opcode >> 9) & 7;
48054: OpcodeFamily = 56; CurrentInstrCycles = 4;
48055: {{ uaecptr srca = m68k_areg(regs, srcreg);
48056: { m68k_areg(regs, dstreg) = (srca);
48057: }}}m68k_incpc(2);
48058: fill_prefetch_2 ();
48059: return 4;
48060: }
48061: unsigned long REGPARAM2 CPUFUNC(op_41e8_5)(uae_u32 opcode) /* LEA */
48062: {
48063: uae_u32 srcreg = (opcode & 7);
48064: uae_u32 dstreg = (opcode >> 9) & 7;
48065: OpcodeFamily = 56; CurrentInstrCycles = 8;
48066: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
48067: { m68k_areg(regs, dstreg) = (srca);
48068: }}}m68k_incpc(4);
48069: fill_prefetch_0 ();
48070: return 8;
48071: }
48072: unsigned long REGPARAM2 CPUFUNC(op_41f0_5)(uae_u32 opcode) /* LEA */
48073: {
48074: uae_u32 srcreg = (opcode & 7);
48075: uae_u32 dstreg = (opcode >> 9) & 7;
48076: OpcodeFamily = 56; CurrentInstrCycles = 14;
48077: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
48078: BusCyclePenalty += 2;
48079: { m68k_areg(regs, dstreg) = (srca);
48080: }}}m68k_incpc(4);
48081: fill_prefetch_0 ();
48082: return 14;
48083: }
48084: unsigned long REGPARAM2 CPUFUNC(op_41f8_5)(uae_u32 opcode) /* LEA */
48085: {
48086: uae_u32 dstreg = (opcode >> 9) & 7;
48087: OpcodeFamily = 56; CurrentInstrCycles = 8;
48088: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
48089: { m68k_areg(regs, dstreg) = (srca);
48090: }}}m68k_incpc(4);
48091: fill_prefetch_0 ();
48092: return 8;
48093: }
48094: unsigned long REGPARAM2 CPUFUNC(op_41f9_5)(uae_u32 opcode) /* LEA */
48095: {
48096: uae_u32 dstreg = (opcode >> 9) & 7;
48097: OpcodeFamily = 56; CurrentInstrCycles = 12;
48098: {{ uaecptr srca = get_ilong_prefetch(2);
48099: { m68k_areg(regs, dstreg) = (srca);
48100: }}}m68k_incpc(6);
48101: fill_prefetch_0 ();
48102: return 12;
48103: }
48104: unsigned long REGPARAM2 CPUFUNC(op_41fa_5)(uae_u32 opcode) /* LEA */
48105: {
48106: uae_u32 dstreg = (opcode >> 9) & 7;
48107: OpcodeFamily = 56; CurrentInstrCycles = 8;
48108: {{ uaecptr srca = m68k_getpc () + 2;
48109: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
48110: { m68k_areg(regs, dstreg) = (srca);
48111: }}}m68k_incpc(4);
48112: fill_prefetch_0 ();
48113: return 8;
48114: }
48115: unsigned long REGPARAM2 CPUFUNC(op_41fb_5)(uae_u32 opcode) /* LEA */
48116: {
48117: uae_u32 dstreg = (opcode >> 9) & 7;
48118: OpcodeFamily = 56; CurrentInstrCycles = 14;
48119: {{ uaecptr tmppc = m68k_getpc() + 2;
48120: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
48121: BusCyclePenalty += 2;
48122: { m68k_areg(regs, dstreg) = (srca);
48123: }}}m68k_incpc(4);
48124: fill_prefetch_0 ();
48125: return 14;
48126: }
48127: unsigned long REGPARAM2 CPUFUNC(op_4200_5)(uae_u32 opcode) /* CLR */
48128: {
48129: uae_u32 srcreg = (opcode & 7);
48130: OpcodeFamily = 18; CurrentInstrCycles = 4;
48131: {{ CLEAR_CZNV;
48132: SET_ZFLG (((uae_s8)(0)) == 0);
48133: SET_NFLG (((uae_s8)(0)) < 0);
48134: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
48135: }}m68k_incpc(2);
48136: fill_prefetch_2 ();
48137: return 4;
48138: }
48139: unsigned long REGPARAM2 CPUFUNC(op_4210_5)(uae_u32 opcode) /* CLR */
48140: {
48141: uae_u32 srcreg = (opcode & 7);
48142: OpcodeFamily = 18; CurrentInstrCycles = 12;
48143: {{ uaecptr srca = m68k_areg(regs, srcreg);
48144: uae_s8 src = get_byte(srca);
48145: CLEAR_CZNV;
48146: SET_ZFLG (((uae_s8)(0)) == 0);
48147: SET_NFLG (((uae_s8)(0)) < 0);
48148: m68k_incpc(2);
48149: fill_prefetch_2 ();
48150: put_byte(srca,0);
48151: }}return 12;
48152: }
48153: unsigned long REGPARAM2 CPUFUNC(op_4218_5)(uae_u32 opcode) /* CLR */
48154: {
48155: uae_u32 srcreg = (opcode & 7);
48156: OpcodeFamily = 18; CurrentInstrCycles = 12;
48157: {{ uaecptr srca = m68k_areg(regs, srcreg);
48158: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
48159: uae_s8 src = get_byte(srca);
48160: CLEAR_CZNV;
48161: SET_ZFLG (((uae_s8)(0)) == 0);
48162: SET_NFLG (((uae_s8)(0)) < 0);
48163: m68k_incpc(2);
48164: fill_prefetch_2 ();
48165: put_byte(srca,0);
48166: }}return 12;
48167: }
48168: unsigned long REGPARAM2 CPUFUNC(op_4220_5)(uae_u32 opcode) /* CLR */
48169: {
48170: uae_u32 srcreg = (opcode & 7);
48171: OpcodeFamily = 18; CurrentInstrCycles = 14;
48172: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
48173: m68k_areg (regs, srcreg) = srca;
48174: uae_s8 src = get_byte(srca);
48175: CLEAR_CZNV;
48176: SET_ZFLG (((uae_s8)(0)) == 0);
48177: SET_NFLG (((uae_s8)(0)) < 0);
48178: m68k_incpc(2);
48179: fill_prefetch_2 ();
48180: put_byte(srca,0);
48181: }}return 14;
48182: }
48183: unsigned long REGPARAM2 CPUFUNC(op_4228_5)(uae_u32 opcode) /* CLR */
48184: {
48185: uae_u32 srcreg = (opcode & 7);
48186: OpcodeFamily = 18; CurrentInstrCycles = 16;
48187: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
48188: uae_s8 src = get_byte(srca);
48189: CLEAR_CZNV;
48190: SET_ZFLG (((uae_s8)(0)) == 0);
48191: SET_NFLG (((uae_s8)(0)) < 0);
48192: m68k_incpc(4);
48193: fill_prefetch_0 ();
48194: put_byte(srca,0);
48195: }}return 16;
48196: }
48197: unsigned long REGPARAM2 CPUFUNC(op_4230_5)(uae_u32 opcode) /* CLR */
48198: {
48199: uae_u32 srcreg = (opcode & 7);
48200: OpcodeFamily = 18; CurrentInstrCycles = 18;
48201: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
48202: BusCyclePenalty += 2;
48203: uae_s8 src = get_byte(srca);
48204: CLEAR_CZNV;
48205: SET_ZFLG (((uae_s8)(0)) == 0);
48206: SET_NFLG (((uae_s8)(0)) < 0);
48207: m68k_incpc(4);
48208: fill_prefetch_0 ();
48209: put_byte(srca,0);
48210: }}return 18;
48211: }
48212: unsigned long REGPARAM2 CPUFUNC(op_4238_5)(uae_u32 opcode) /* CLR */
48213: {
48214: OpcodeFamily = 18; CurrentInstrCycles = 16;
48215: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
48216: uae_s8 src = get_byte(srca);
48217: CLEAR_CZNV;
48218: SET_ZFLG (((uae_s8)(0)) == 0);
48219: SET_NFLG (((uae_s8)(0)) < 0);
48220: m68k_incpc(4);
48221: fill_prefetch_0 ();
48222: put_byte(srca,0);
48223: }}return 16;
48224: }
48225: unsigned long REGPARAM2 CPUFUNC(op_4239_5)(uae_u32 opcode) /* CLR */
48226: {
48227: OpcodeFamily = 18; CurrentInstrCycles = 20;
48228: {{ uaecptr srca = get_ilong_prefetch(2);
48229: uae_s8 src = get_byte(srca);
48230: CLEAR_CZNV;
48231: SET_ZFLG (((uae_s8)(0)) == 0);
48232: SET_NFLG (((uae_s8)(0)) < 0);
48233: m68k_incpc(6);
48234: fill_prefetch_0 ();
48235: put_byte(srca,0);
48236: }}return 20;
48237: }
48238: unsigned long REGPARAM2 CPUFUNC(op_4240_5)(uae_u32 opcode) /* CLR */
48239: {
48240: uae_u32 srcreg = (opcode & 7);
48241: OpcodeFamily = 18; CurrentInstrCycles = 4;
48242: {{ CLEAR_CZNV;
48243: SET_ZFLG (((uae_s16)(0)) == 0);
48244: SET_NFLG (((uae_s16)(0)) < 0);
48245: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
48246: }}m68k_incpc(2);
48247: fill_prefetch_2 ();
48248: return 4;
48249: }
48250: unsigned long REGPARAM2 CPUFUNC(op_4250_5)(uae_u32 opcode) /* CLR */
48251: {
48252: uae_u32 srcreg = (opcode & 7);
48253: OpcodeFamily = 18; CurrentInstrCycles = 12;
48254: {{ uaecptr srca = m68k_areg(regs, srcreg);
48255: if ((srca & 1) != 0) {
48256: last_fault_for_exception_3 = srca;
48257: last_op_for_exception_3 = opcode;
48258: last_addr_for_exception_3 = m68k_getpc() + 2;
48259: Exception(3, 0, M68000_EXC_SRC_CPU);
48260: goto endlabel2768;
48261: }
48262: { uae_s16 src = get_word(srca);
48263: CLEAR_CZNV;
48264: SET_ZFLG (((uae_s16)(0)) == 0);
48265: SET_NFLG (((uae_s16)(0)) < 0);
48266: m68k_incpc(2);
48267: fill_prefetch_2 ();
48268: put_word(srca,0);
48269: }}}endlabel2768: ;
48270: return 12;
48271: }
48272: unsigned long REGPARAM2 CPUFUNC(op_4258_5)(uae_u32 opcode) /* CLR */
48273: {
48274: uae_u32 srcreg = (opcode & 7);
48275: OpcodeFamily = 18; CurrentInstrCycles = 12;
48276: {{ uaecptr srca = m68k_areg(regs, srcreg);
48277: if ((srca & 1) != 0) {
48278: last_fault_for_exception_3 = srca;
48279: last_op_for_exception_3 = opcode;
48280: last_addr_for_exception_3 = m68k_getpc() + 2;
48281: Exception(3, 0, M68000_EXC_SRC_CPU);
48282: goto endlabel2769;
48283: }
48284: { m68k_areg(regs, srcreg) += 2;
48285: uae_s16 src = get_word(srca);
48286: CLEAR_CZNV;
48287: SET_ZFLG (((uae_s16)(0)) == 0);
48288: SET_NFLG (((uae_s16)(0)) < 0);
48289: m68k_incpc(2);
48290: fill_prefetch_2 ();
48291: put_word(srca,0);
48292: }}}endlabel2769: ;
48293: return 12;
48294: }
48295: unsigned long REGPARAM2 CPUFUNC(op_4260_5)(uae_u32 opcode) /* CLR */
48296: {
48297: uae_u32 srcreg = (opcode & 7);
48298: OpcodeFamily = 18; CurrentInstrCycles = 14;
48299: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
48300: if ((srca & 1) != 0) {
48301: last_fault_for_exception_3 = srca;
48302: last_op_for_exception_3 = opcode;
48303: last_addr_for_exception_3 = m68k_getpc() + 2;
48304: Exception(3, 0, M68000_EXC_SRC_CPU);
48305: goto endlabel2770;
48306: }
48307: { m68k_areg (regs, srcreg) = srca;
48308: uae_s16 src = get_word(srca);
48309: CLEAR_CZNV;
48310: SET_ZFLG (((uae_s16)(0)) == 0);
48311: SET_NFLG (((uae_s16)(0)) < 0);
48312: m68k_incpc(2);
48313: fill_prefetch_2 ();
48314: put_word(srca,0);
48315: }}}endlabel2770: ;
48316: return 14;
48317: }
48318: unsigned long REGPARAM2 CPUFUNC(op_4268_5)(uae_u32 opcode) /* CLR */
48319: {
48320: uae_u32 srcreg = (opcode & 7);
48321: OpcodeFamily = 18; CurrentInstrCycles = 16;
48322: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
48323: if ((srca & 1) != 0) {
48324: last_fault_for_exception_3 = srca;
48325: last_op_for_exception_3 = opcode;
48326: last_addr_for_exception_3 = m68k_getpc() + 4;
48327: Exception(3, 0, M68000_EXC_SRC_CPU);
48328: goto endlabel2771;
48329: }
48330: { uae_s16 src = get_word(srca);
48331: CLEAR_CZNV;
48332: SET_ZFLG (((uae_s16)(0)) == 0);
48333: SET_NFLG (((uae_s16)(0)) < 0);
48334: m68k_incpc(4);
48335: fill_prefetch_0 ();
48336: put_word(srca,0);
48337: }}}endlabel2771: ;
48338: return 16;
48339: }
48340: #endif
48341:
48342: #ifdef PART_4
48343: unsigned long REGPARAM2 CPUFUNC(op_4270_5)(uae_u32 opcode) /* CLR */
48344: {
48345: uae_u32 srcreg = (opcode & 7);
48346: OpcodeFamily = 18; CurrentInstrCycles = 18;
48347: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
48348: BusCyclePenalty += 2;
48349: if ((srca & 1) != 0) {
48350: last_fault_for_exception_3 = srca;
48351: last_op_for_exception_3 = opcode;
48352: last_addr_for_exception_3 = m68k_getpc() + 4;
48353: Exception(3, 0, M68000_EXC_SRC_CPU);
48354: goto endlabel2772;
48355: }
48356: { uae_s16 src = get_word(srca);
48357: CLEAR_CZNV;
48358: SET_ZFLG (((uae_s16)(0)) == 0);
48359: SET_NFLG (((uae_s16)(0)) < 0);
48360: m68k_incpc(4);
48361: fill_prefetch_0 ();
48362: put_word(srca,0);
48363: }}}endlabel2772: ;
48364: return 18;
48365: }
48366: unsigned long REGPARAM2 CPUFUNC(op_4278_5)(uae_u32 opcode) /* CLR */
48367: {
48368: OpcodeFamily = 18; CurrentInstrCycles = 16;
48369: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
48370: if ((srca & 1) != 0) {
48371: last_fault_for_exception_3 = srca;
48372: last_op_for_exception_3 = opcode;
48373: last_addr_for_exception_3 = m68k_getpc() + 4;
48374: Exception(3, 0, M68000_EXC_SRC_CPU);
48375: goto endlabel2773;
48376: }
48377: { uae_s16 src = get_word(srca);
48378: CLEAR_CZNV;
48379: SET_ZFLG (((uae_s16)(0)) == 0);
48380: SET_NFLG (((uae_s16)(0)) < 0);
48381: m68k_incpc(4);
48382: fill_prefetch_0 ();
48383: put_word(srca,0);
48384: }}}endlabel2773: ;
48385: return 16;
48386: }
48387: unsigned long REGPARAM2 CPUFUNC(op_4279_5)(uae_u32 opcode) /* CLR */
48388: {
48389: OpcodeFamily = 18; CurrentInstrCycles = 20;
48390: {{ uaecptr srca = get_ilong_prefetch(2);
48391: if ((srca & 1) != 0) {
48392: last_fault_for_exception_3 = srca;
48393: last_op_for_exception_3 = opcode;
48394: last_addr_for_exception_3 = m68k_getpc() + 6;
48395: Exception(3, 0, M68000_EXC_SRC_CPU);
48396: goto endlabel2774;
48397: }
48398: { uae_s16 src = get_word(srca);
48399: CLEAR_CZNV;
48400: SET_ZFLG (((uae_s16)(0)) == 0);
48401: SET_NFLG (((uae_s16)(0)) < 0);
48402: m68k_incpc(6);
48403: fill_prefetch_0 ();
48404: put_word(srca,0);
48405: }}}endlabel2774: ;
48406: return 20;
48407: }
48408: unsigned long REGPARAM2 CPUFUNC(op_4280_5)(uae_u32 opcode) /* CLR */
48409: {
48410: uae_u32 srcreg = (opcode & 7);
48411: OpcodeFamily = 18; CurrentInstrCycles = 6;
48412: {{ CLEAR_CZNV;
48413: SET_ZFLG (((uae_s32)(0)) == 0);
48414: SET_NFLG (((uae_s32)(0)) < 0);
48415: m68k_dreg(regs, srcreg) = (0);
48416: }}m68k_incpc(2);
48417: fill_prefetch_2 ();
48418: return 6;
48419: }
48420: unsigned long REGPARAM2 CPUFUNC(op_4290_5)(uae_u32 opcode) /* CLR */
48421: {
48422: uae_u32 srcreg = (opcode & 7);
48423: OpcodeFamily = 18; CurrentInstrCycles = 20;
48424: {{ uaecptr srca = m68k_areg(regs, srcreg);
48425: if ((srca & 1) != 0) {
48426: last_fault_for_exception_3 = srca;
48427: last_op_for_exception_3 = opcode;
48428: last_addr_for_exception_3 = m68k_getpc() + 2;
48429: Exception(3, 0, M68000_EXC_SRC_CPU);
48430: goto endlabel2776;
48431: }
48432: { uae_s32 src = get_long(srca);
48433: CLEAR_CZNV;
48434: SET_ZFLG (((uae_s32)(0)) == 0);
48435: SET_NFLG (((uae_s32)(0)) < 0);
48436: m68k_incpc(2);
48437: fill_prefetch_2 ();
48438: put_long(srca,0);
48439: }}}endlabel2776: ;
48440: return 20;
48441: }
48442: unsigned long REGPARAM2 CPUFUNC(op_4298_5)(uae_u32 opcode) /* CLR */
48443: {
48444: uae_u32 srcreg = (opcode & 7);
48445: OpcodeFamily = 18; CurrentInstrCycles = 20;
48446: {{ uaecptr srca = m68k_areg(regs, srcreg);
48447: if ((srca & 1) != 0) {
48448: last_fault_for_exception_3 = srca;
48449: last_op_for_exception_3 = opcode;
48450: last_addr_for_exception_3 = m68k_getpc() + 2;
48451: Exception(3, 0, M68000_EXC_SRC_CPU);
48452: goto endlabel2777;
48453: }
48454: { m68k_areg(regs, srcreg) += 4;
48455: uae_s32 src = get_long(srca);
48456: CLEAR_CZNV;
48457: SET_ZFLG (((uae_s32)(0)) == 0);
48458: SET_NFLG (((uae_s32)(0)) < 0);
48459: m68k_incpc(2);
48460: fill_prefetch_2 ();
48461: put_long(srca,0);
48462: }}}endlabel2777: ;
48463: return 20;
48464: }
48465: unsigned long REGPARAM2 CPUFUNC(op_42a0_5)(uae_u32 opcode) /* CLR */
48466: {
48467: uae_u32 srcreg = (opcode & 7);
48468: OpcodeFamily = 18; CurrentInstrCycles = 22;
48469: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
48470: if ((srca & 1) != 0) {
48471: last_fault_for_exception_3 = srca;
48472: last_op_for_exception_3 = opcode;
48473: last_addr_for_exception_3 = m68k_getpc() + 2;
48474: Exception(3, 0, M68000_EXC_SRC_CPU);
48475: goto endlabel2778;
48476: }
48477: { m68k_areg (regs, srcreg) = srca;
48478: uae_s32 src = get_long(srca);
48479: CLEAR_CZNV;
48480: SET_ZFLG (((uae_s32)(0)) == 0);
48481: SET_NFLG (((uae_s32)(0)) < 0);
48482: m68k_incpc(2);
48483: fill_prefetch_2 ();
48484: put_long(srca,0);
48485: }}}endlabel2778: ;
48486: return 22;
48487: }
48488: unsigned long REGPARAM2 CPUFUNC(op_42a8_5)(uae_u32 opcode) /* CLR */
48489: {
48490: uae_u32 srcreg = (opcode & 7);
48491: OpcodeFamily = 18; CurrentInstrCycles = 24;
48492: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
48493: if ((srca & 1) != 0) {
48494: last_fault_for_exception_3 = srca;
48495: last_op_for_exception_3 = opcode;
48496: last_addr_for_exception_3 = m68k_getpc() + 4;
48497: Exception(3, 0, M68000_EXC_SRC_CPU);
48498: goto endlabel2779;
48499: }
48500: { uae_s32 src = get_long(srca);
48501: CLEAR_CZNV;
48502: SET_ZFLG (((uae_s32)(0)) == 0);
48503: SET_NFLG (((uae_s32)(0)) < 0);
48504: m68k_incpc(4);
48505: fill_prefetch_0 ();
48506: put_long(srca,0);
48507: }}}endlabel2779: ;
48508: return 24;
48509: }
48510: unsigned long REGPARAM2 CPUFUNC(op_42b0_5)(uae_u32 opcode) /* CLR */
48511: {
48512: uae_u32 srcreg = (opcode & 7);
48513: OpcodeFamily = 18; CurrentInstrCycles = 26;
48514: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
48515: BusCyclePenalty += 2;
48516: if ((srca & 1) != 0) {
48517: last_fault_for_exception_3 = srca;
48518: last_op_for_exception_3 = opcode;
48519: last_addr_for_exception_3 = m68k_getpc() + 4;
48520: Exception(3, 0, M68000_EXC_SRC_CPU);
48521: goto endlabel2780;
48522: }
48523: { uae_s32 src = get_long(srca);
48524: CLEAR_CZNV;
48525: SET_ZFLG (((uae_s32)(0)) == 0);
48526: SET_NFLG (((uae_s32)(0)) < 0);
48527: m68k_incpc(4);
48528: fill_prefetch_0 ();
48529: put_long(srca,0);
48530: }}}endlabel2780: ;
48531: return 26;
48532: }
48533: unsigned long REGPARAM2 CPUFUNC(op_42b8_5)(uae_u32 opcode) /* CLR */
48534: {
48535: OpcodeFamily = 18; CurrentInstrCycles = 24;
48536: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
48537: if ((srca & 1) != 0) {
48538: last_fault_for_exception_3 = srca;
48539: last_op_for_exception_3 = opcode;
48540: last_addr_for_exception_3 = m68k_getpc() + 4;
48541: Exception(3, 0, M68000_EXC_SRC_CPU);
48542: goto endlabel2781;
48543: }
48544: { uae_s32 src = get_long(srca);
48545: CLEAR_CZNV;
48546: SET_ZFLG (((uae_s32)(0)) == 0);
48547: SET_NFLG (((uae_s32)(0)) < 0);
48548: m68k_incpc(4);
48549: fill_prefetch_0 ();
48550: put_long(srca,0);
48551: }}}endlabel2781: ;
48552: return 24;
48553: }
48554: unsigned long REGPARAM2 CPUFUNC(op_42b9_5)(uae_u32 opcode) /* CLR */
48555: {
48556: OpcodeFamily = 18; CurrentInstrCycles = 28;
48557: {{ uaecptr srca = get_ilong_prefetch(2);
48558: if ((srca & 1) != 0) {
48559: last_fault_for_exception_3 = srca;
48560: last_op_for_exception_3 = opcode;
48561: last_addr_for_exception_3 = m68k_getpc() + 6;
48562: Exception(3, 0, M68000_EXC_SRC_CPU);
48563: goto endlabel2782;
48564: }
48565: { uae_s32 src = get_long(srca);
48566: CLEAR_CZNV;
48567: SET_ZFLG (((uae_s32)(0)) == 0);
48568: SET_NFLG (((uae_s32)(0)) < 0);
48569: m68k_incpc(6);
48570: fill_prefetch_0 ();
48571: put_long(srca,0);
48572: }}}endlabel2782: ;
48573: return 28;
48574: }
48575: unsigned long REGPARAM2 CPUFUNC(op_4400_5)(uae_u32 opcode) /* NEG */
48576: {
48577: uae_u32 srcreg = (opcode & 7);
48578: OpcodeFamily = 15; CurrentInstrCycles = 4;
48579: {{ uae_s8 src = m68k_dreg(regs, srcreg);
48580: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
48581: { int flgs = ((uae_s8)(src)) < 0;
48582: int flgo = ((uae_s8)(0)) < 0;
48583: int flgn = ((uae_s8)(dst)) < 0;
48584: SET_ZFLG (((uae_s8)(dst)) == 0);
48585: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48586: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
48587: COPY_CARRY;
48588: SET_NFLG (flgn != 0);
48589: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
48590: }}}}}m68k_incpc(2);
48591: fill_prefetch_2 ();
48592: return 4;
48593: }
48594: unsigned long REGPARAM2 CPUFUNC(op_4410_5)(uae_u32 opcode) /* NEG */
48595: {
48596: uae_u32 srcreg = (opcode & 7);
48597: OpcodeFamily = 15; CurrentInstrCycles = 12;
48598: {{ uaecptr srca = m68k_areg(regs, srcreg);
48599: { uae_s8 src = get_byte(srca);
48600: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
48601: { int flgs = ((uae_s8)(src)) < 0;
48602: int flgo = ((uae_s8)(0)) < 0;
48603: int flgn = ((uae_s8)(dst)) < 0;
48604: SET_ZFLG (((uae_s8)(dst)) == 0);
48605: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48606: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
48607: COPY_CARRY;
48608: SET_NFLG (flgn != 0);
48609: m68k_incpc(2);
48610: fill_prefetch_2 ();
48611: put_byte(srca,dst);
48612: }}}}}}return 12;
48613: }
48614: unsigned long REGPARAM2 CPUFUNC(op_4418_5)(uae_u32 opcode) /* NEG */
48615: {
48616: uae_u32 srcreg = (opcode & 7);
48617: OpcodeFamily = 15; CurrentInstrCycles = 12;
48618: {{ uaecptr srca = m68k_areg(regs, srcreg);
48619: { uae_s8 src = get_byte(srca);
48620: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
48621: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
48622: { int flgs = ((uae_s8)(src)) < 0;
48623: int flgo = ((uae_s8)(0)) < 0;
48624: int flgn = ((uae_s8)(dst)) < 0;
48625: SET_ZFLG (((uae_s8)(dst)) == 0);
48626: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48627: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
48628: COPY_CARRY;
48629: SET_NFLG (flgn != 0);
48630: m68k_incpc(2);
48631: fill_prefetch_2 ();
48632: put_byte(srca,dst);
48633: }}}}}}return 12;
48634: }
48635: unsigned long REGPARAM2 CPUFUNC(op_4420_5)(uae_u32 opcode) /* NEG */
48636: {
48637: uae_u32 srcreg = (opcode & 7);
48638: OpcodeFamily = 15; CurrentInstrCycles = 14;
48639: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
48640: { uae_s8 src = get_byte(srca);
48641: m68k_areg (regs, srcreg) = srca;
48642: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
48643: { int flgs = ((uae_s8)(src)) < 0;
48644: int flgo = ((uae_s8)(0)) < 0;
48645: int flgn = ((uae_s8)(dst)) < 0;
48646: SET_ZFLG (((uae_s8)(dst)) == 0);
48647: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48648: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
48649: COPY_CARRY;
48650: SET_NFLG (flgn != 0);
48651: m68k_incpc(2);
48652: fill_prefetch_2 ();
48653: put_byte(srca,dst);
48654: }}}}}}return 14;
48655: }
48656: unsigned long REGPARAM2 CPUFUNC(op_4428_5)(uae_u32 opcode) /* NEG */
48657: {
48658: uae_u32 srcreg = (opcode & 7);
48659: OpcodeFamily = 15; CurrentInstrCycles = 16;
48660: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
48661: { uae_s8 src = get_byte(srca);
48662: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
48663: { int flgs = ((uae_s8)(src)) < 0;
48664: int flgo = ((uae_s8)(0)) < 0;
48665: int flgn = ((uae_s8)(dst)) < 0;
48666: SET_ZFLG (((uae_s8)(dst)) == 0);
48667: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48668: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
48669: COPY_CARRY;
48670: SET_NFLG (flgn != 0);
48671: m68k_incpc(4);
48672: fill_prefetch_0 ();
48673: put_byte(srca,dst);
48674: }}}}}}return 16;
48675: }
48676: unsigned long REGPARAM2 CPUFUNC(op_4430_5)(uae_u32 opcode) /* NEG */
48677: {
48678: uae_u32 srcreg = (opcode & 7);
48679: OpcodeFamily = 15; CurrentInstrCycles = 18;
48680: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
48681: BusCyclePenalty += 2;
48682: { uae_s8 src = get_byte(srca);
48683: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
48684: { int flgs = ((uae_s8)(src)) < 0;
48685: int flgo = ((uae_s8)(0)) < 0;
48686: int flgn = ((uae_s8)(dst)) < 0;
48687: SET_ZFLG (((uae_s8)(dst)) == 0);
48688: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48689: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
48690: COPY_CARRY;
48691: SET_NFLG (flgn != 0);
48692: m68k_incpc(4);
48693: fill_prefetch_0 ();
48694: put_byte(srca,dst);
48695: }}}}}}return 18;
48696: }
48697: unsigned long REGPARAM2 CPUFUNC(op_4438_5)(uae_u32 opcode) /* NEG */
48698: {
48699: OpcodeFamily = 15; CurrentInstrCycles = 16;
48700: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
48701: { uae_s8 src = get_byte(srca);
48702: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
48703: { int flgs = ((uae_s8)(src)) < 0;
48704: int flgo = ((uae_s8)(0)) < 0;
48705: int flgn = ((uae_s8)(dst)) < 0;
48706: SET_ZFLG (((uae_s8)(dst)) == 0);
48707: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48708: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
48709: COPY_CARRY;
48710: SET_NFLG (flgn != 0);
48711: m68k_incpc(4);
48712: fill_prefetch_0 ();
48713: put_byte(srca,dst);
48714: }}}}}}return 16;
48715: }
48716: unsigned long REGPARAM2 CPUFUNC(op_4439_5)(uae_u32 opcode) /* NEG */
48717: {
48718: OpcodeFamily = 15; CurrentInstrCycles = 20;
48719: {{ uaecptr srca = get_ilong_prefetch(2);
48720: { uae_s8 src = get_byte(srca);
48721: {{uae_u32 dst = ((uae_s8)(0)) - ((uae_s8)(src));
48722: { int flgs = ((uae_s8)(src)) < 0;
48723: int flgo = ((uae_s8)(0)) < 0;
48724: int flgn = ((uae_s8)(dst)) < 0;
48725: SET_ZFLG (((uae_s8)(dst)) == 0);
48726: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48727: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
48728: COPY_CARRY;
48729: SET_NFLG (flgn != 0);
48730: m68k_incpc(6);
48731: fill_prefetch_0 ();
48732: put_byte(srca,dst);
48733: }}}}}}return 20;
48734: }
48735: unsigned long REGPARAM2 CPUFUNC(op_4440_5)(uae_u32 opcode) /* NEG */
48736: {
48737: uae_u32 srcreg = (opcode & 7);
48738: OpcodeFamily = 15; CurrentInstrCycles = 4;
48739: {{ uae_s16 src = m68k_dreg(regs, srcreg);
48740: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
48741: { int flgs = ((uae_s16)(src)) < 0;
48742: int flgo = ((uae_s16)(0)) < 0;
48743: int flgn = ((uae_s16)(dst)) < 0;
48744: SET_ZFLG (((uae_s16)(dst)) == 0);
48745: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48746: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
48747: COPY_CARRY;
48748: SET_NFLG (flgn != 0);
48749: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
48750: }}}}}m68k_incpc(2);
48751: fill_prefetch_2 ();
48752: return 4;
48753: }
48754: unsigned long REGPARAM2 CPUFUNC(op_4450_5)(uae_u32 opcode) /* NEG */
48755: {
48756: uae_u32 srcreg = (opcode & 7);
48757: OpcodeFamily = 15; CurrentInstrCycles = 12;
48758: {{ uaecptr srca = m68k_areg(regs, srcreg);
48759: if ((srca & 1) != 0) {
48760: last_fault_for_exception_3 = srca;
48761: last_op_for_exception_3 = opcode;
48762: last_addr_for_exception_3 = m68k_getpc() + 2;
48763: Exception(3, 0, M68000_EXC_SRC_CPU);
48764: goto endlabel2792;
48765: }
48766: {{ uae_s16 src = get_word(srca);
48767: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
48768: { int flgs = ((uae_s16)(src)) < 0;
48769: int flgo = ((uae_s16)(0)) < 0;
48770: int flgn = ((uae_s16)(dst)) < 0;
48771: SET_ZFLG (((uae_s16)(dst)) == 0);
48772: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48773: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
48774: COPY_CARRY;
48775: SET_NFLG (flgn != 0);
48776: m68k_incpc(2);
48777: fill_prefetch_2 ();
48778: put_word(srca,dst);
48779: }}}}}}}endlabel2792: ;
48780: return 12;
48781: }
48782: unsigned long REGPARAM2 CPUFUNC(op_4458_5)(uae_u32 opcode) /* NEG */
48783: {
48784: uae_u32 srcreg = (opcode & 7);
48785: OpcodeFamily = 15; CurrentInstrCycles = 12;
48786: {{ uaecptr srca = m68k_areg(regs, srcreg);
48787: if ((srca & 1) != 0) {
48788: last_fault_for_exception_3 = srca;
48789: last_op_for_exception_3 = opcode;
48790: last_addr_for_exception_3 = m68k_getpc() + 2;
48791: Exception(3, 0, M68000_EXC_SRC_CPU);
48792: goto endlabel2793;
48793: }
48794: {{ uae_s16 src = get_word(srca);
48795: m68k_areg(regs, srcreg) += 2;
48796: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
48797: { int flgs = ((uae_s16)(src)) < 0;
48798: int flgo = ((uae_s16)(0)) < 0;
48799: int flgn = ((uae_s16)(dst)) < 0;
48800: SET_ZFLG (((uae_s16)(dst)) == 0);
48801: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48802: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
48803: COPY_CARRY;
48804: SET_NFLG (flgn != 0);
48805: m68k_incpc(2);
48806: fill_prefetch_2 ();
48807: put_word(srca,dst);
48808: }}}}}}}endlabel2793: ;
48809: return 12;
48810: }
48811: unsigned long REGPARAM2 CPUFUNC(op_4460_5)(uae_u32 opcode) /* NEG */
48812: {
48813: uae_u32 srcreg = (opcode & 7);
48814: OpcodeFamily = 15; CurrentInstrCycles = 14;
48815: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
48816: if ((srca & 1) != 0) {
48817: last_fault_for_exception_3 = srca;
48818: last_op_for_exception_3 = opcode;
48819: last_addr_for_exception_3 = m68k_getpc() + 2;
48820: Exception(3, 0, M68000_EXC_SRC_CPU);
48821: goto endlabel2794;
48822: }
48823: {{ uae_s16 src = get_word(srca);
48824: m68k_areg (regs, srcreg) = srca;
48825: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
48826: { int flgs = ((uae_s16)(src)) < 0;
48827: int flgo = ((uae_s16)(0)) < 0;
48828: int flgn = ((uae_s16)(dst)) < 0;
48829: SET_ZFLG (((uae_s16)(dst)) == 0);
48830: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48831: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
48832: COPY_CARRY;
48833: SET_NFLG (flgn != 0);
48834: m68k_incpc(2);
48835: fill_prefetch_2 ();
48836: put_word(srca,dst);
48837: }}}}}}}endlabel2794: ;
48838: return 14;
48839: }
48840: unsigned long REGPARAM2 CPUFUNC(op_4468_5)(uae_u32 opcode) /* NEG */
48841: {
48842: uae_u32 srcreg = (opcode & 7);
48843: OpcodeFamily = 15; CurrentInstrCycles = 16;
48844: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
48845: if ((srca & 1) != 0) {
48846: last_fault_for_exception_3 = srca;
48847: last_op_for_exception_3 = opcode;
48848: last_addr_for_exception_3 = m68k_getpc() + 4;
48849: Exception(3, 0, M68000_EXC_SRC_CPU);
48850: goto endlabel2795;
48851: }
48852: {{ uae_s16 src = get_word(srca);
48853: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
48854: { int flgs = ((uae_s16)(src)) < 0;
48855: int flgo = ((uae_s16)(0)) < 0;
48856: int flgn = ((uae_s16)(dst)) < 0;
48857: SET_ZFLG (((uae_s16)(dst)) == 0);
48858: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48859: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
48860: COPY_CARRY;
48861: SET_NFLG (flgn != 0);
48862: m68k_incpc(4);
48863: fill_prefetch_0 ();
48864: put_word(srca,dst);
48865: }}}}}}}endlabel2795: ;
48866: return 16;
48867: }
48868: unsigned long REGPARAM2 CPUFUNC(op_4470_5)(uae_u32 opcode) /* NEG */
48869: {
48870: uae_u32 srcreg = (opcode & 7);
48871: OpcodeFamily = 15; CurrentInstrCycles = 18;
48872: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
48873: BusCyclePenalty += 2;
48874: if ((srca & 1) != 0) {
48875: last_fault_for_exception_3 = srca;
48876: last_op_for_exception_3 = opcode;
48877: last_addr_for_exception_3 = m68k_getpc() + 4;
48878: Exception(3, 0, M68000_EXC_SRC_CPU);
48879: goto endlabel2796;
48880: }
48881: {{ uae_s16 src = get_word(srca);
48882: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
48883: { int flgs = ((uae_s16)(src)) < 0;
48884: int flgo = ((uae_s16)(0)) < 0;
48885: int flgn = ((uae_s16)(dst)) < 0;
48886: SET_ZFLG (((uae_s16)(dst)) == 0);
48887: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48888: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
48889: COPY_CARRY;
48890: SET_NFLG (flgn != 0);
48891: m68k_incpc(4);
48892: fill_prefetch_0 ();
48893: put_word(srca,dst);
48894: }}}}}}}endlabel2796: ;
48895: return 18;
48896: }
48897: unsigned long REGPARAM2 CPUFUNC(op_4478_5)(uae_u32 opcode) /* NEG */
48898: {
48899: OpcodeFamily = 15; CurrentInstrCycles = 16;
48900: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
48901: if ((srca & 1) != 0) {
48902: last_fault_for_exception_3 = srca;
48903: last_op_for_exception_3 = opcode;
48904: last_addr_for_exception_3 = m68k_getpc() + 4;
48905: Exception(3, 0, M68000_EXC_SRC_CPU);
48906: goto endlabel2797;
48907: }
48908: {{ uae_s16 src = get_word(srca);
48909: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
48910: { int flgs = ((uae_s16)(src)) < 0;
48911: int flgo = ((uae_s16)(0)) < 0;
48912: int flgn = ((uae_s16)(dst)) < 0;
48913: SET_ZFLG (((uae_s16)(dst)) == 0);
48914: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48915: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
48916: COPY_CARRY;
48917: SET_NFLG (flgn != 0);
48918: m68k_incpc(4);
48919: fill_prefetch_0 ();
48920: put_word(srca,dst);
48921: }}}}}}}endlabel2797: ;
48922: return 16;
48923: }
48924: unsigned long REGPARAM2 CPUFUNC(op_4479_5)(uae_u32 opcode) /* NEG */
48925: {
48926: OpcodeFamily = 15; CurrentInstrCycles = 20;
48927: {{ uaecptr srca = get_ilong_prefetch(2);
48928: if ((srca & 1) != 0) {
48929: last_fault_for_exception_3 = srca;
48930: last_op_for_exception_3 = opcode;
48931: last_addr_for_exception_3 = m68k_getpc() + 6;
48932: Exception(3, 0, M68000_EXC_SRC_CPU);
48933: goto endlabel2798;
48934: }
48935: {{ uae_s16 src = get_word(srca);
48936: {{uae_u32 dst = ((uae_s16)(0)) - ((uae_s16)(src));
48937: { int flgs = ((uae_s16)(src)) < 0;
48938: int flgo = ((uae_s16)(0)) < 0;
48939: int flgn = ((uae_s16)(dst)) < 0;
48940: SET_ZFLG (((uae_s16)(dst)) == 0);
48941: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48942: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
48943: COPY_CARRY;
48944: SET_NFLG (flgn != 0);
48945: m68k_incpc(6);
48946: fill_prefetch_0 ();
48947: put_word(srca,dst);
48948: }}}}}}}endlabel2798: ;
48949: return 20;
48950: }
48951: unsigned long REGPARAM2 CPUFUNC(op_4480_5)(uae_u32 opcode) /* NEG */
48952: {
48953: uae_u32 srcreg = (opcode & 7);
48954: OpcodeFamily = 15; CurrentInstrCycles = 6;
48955: {{ uae_s32 src = m68k_dreg(regs, srcreg);
48956: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
48957: { int flgs = ((uae_s32)(src)) < 0;
48958: int flgo = ((uae_s32)(0)) < 0;
48959: int flgn = ((uae_s32)(dst)) < 0;
48960: SET_ZFLG (((uae_s32)(dst)) == 0);
48961: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48962: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
48963: COPY_CARRY;
48964: SET_NFLG (flgn != 0);
48965: m68k_dreg(regs, srcreg) = (dst);
48966: }}}}}m68k_incpc(2);
48967: fill_prefetch_2 ();
48968: return 6;
48969: }
48970: unsigned long REGPARAM2 CPUFUNC(op_4490_5)(uae_u32 opcode) /* NEG */
48971: {
48972: uae_u32 srcreg = (opcode & 7);
48973: OpcodeFamily = 15; CurrentInstrCycles = 20;
48974: {{ uaecptr srca = m68k_areg(regs, srcreg);
48975: if ((srca & 1) != 0) {
48976: last_fault_for_exception_3 = srca;
48977: last_op_for_exception_3 = opcode;
48978: last_addr_for_exception_3 = m68k_getpc() + 2;
48979: Exception(3, 0, M68000_EXC_SRC_CPU);
48980: goto endlabel2800;
48981: }
48982: {{ uae_s32 src = get_long(srca);
48983: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
48984: { int flgs = ((uae_s32)(src)) < 0;
48985: int flgo = ((uae_s32)(0)) < 0;
48986: int flgn = ((uae_s32)(dst)) < 0;
48987: SET_ZFLG (((uae_s32)(dst)) == 0);
48988: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
48989: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
48990: COPY_CARRY;
48991: SET_NFLG (flgn != 0);
48992: m68k_incpc(2);
48993: fill_prefetch_2 ();
48994: put_long(srca,dst);
48995: }}}}}}}endlabel2800: ;
48996: return 20;
48997: }
48998: unsigned long REGPARAM2 CPUFUNC(op_4498_5)(uae_u32 opcode) /* NEG */
48999: {
49000: uae_u32 srcreg = (opcode & 7);
49001: OpcodeFamily = 15; CurrentInstrCycles = 20;
49002: {{ uaecptr srca = m68k_areg(regs, srcreg);
49003: if ((srca & 1) != 0) {
49004: last_fault_for_exception_3 = srca;
49005: last_op_for_exception_3 = opcode;
49006: last_addr_for_exception_3 = m68k_getpc() + 2;
49007: Exception(3, 0, M68000_EXC_SRC_CPU);
49008: goto endlabel2801;
49009: }
49010: {{ uae_s32 src = get_long(srca);
49011: m68k_areg(regs, srcreg) += 4;
49012: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
49013: { int flgs = ((uae_s32)(src)) < 0;
49014: int flgo = ((uae_s32)(0)) < 0;
49015: int flgn = ((uae_s32)(dst)) < 0;
49016: SET_ZFLG (((uae_s32)(dst)) == 0);
49017: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
49018: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
49019: COPY_CARRY;
49020: SET_NFLG (flgn != 0);
49021: m68k_incpc(2);
49022: fill_prefetch_2 ();
49023: put_long(srca,dst);
49024: }}}}}}}endlabel2801: ;
49025: return 20;
49026: }
49027: unsigned long REGPARAM2 CPUFUNC(op_44a0_5)(uae_u32 opcode) /* NEG */
49028: {
49029: uae_u32 srcreg = (opcode & 7);
49030: OpcodeFamily = 15; CurrentInstrCycles = 22;
49031: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
49032: if ((srca & 1) != 0) {
49033: last_fault_for_exception_3 = srca;
49034: last_op_for_exception_3 = opcode;
49035: last_addr_for_exception_3 = m68k_getpc() + 2;
49036: Exception(3, 0, M68000_EXC_SRC_CPU);
49037: goto endlabel2802;
49038: }
49039: {{ uae_s32 src = get_long(srca);
49040: m68k_areg (regs, srcreg) = srca;
49041: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
49042: { int flgs = ((uae_s32)(src)) < 0;
49043: int flgo = ((uae_s32)(0)) < 0;
49044: int flgn = ((uae_s32)(dst)) < 0;
49045: SET_ZFLG (((uae_s32)(dst)) == 0);
49046: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
49047: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
49048: COPY_CARRY;
49049: SET_NFLG (flgn != 0);
49050: m68k_incpc(2);
49051: fill_prefetch_2 ();
49052: put_long(srca,dst);
49053: }}}}}}}endlabel2802: ;
49054: return 22;
49055: }
49056: unsigned long REGPARAM2 CPUFUNC(op_44a8_5)(uae_u32 opcode) /* NEG */
49057: {
49058: uae_u32 srcreg = (opcode & 7);
49059: OpcodeFamily = 15; CurrentInstrCycles = 24;
49060: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
49061: if ((srca & 1) != 0) {
49062: last_fault_for_exception_3 = srca;
49063: last_op_for_exception_3 = opcode;
49064: last_addr_for_exception_3 = m68k_getpc() + 4;
49065: Exception(3, 0, M68000_EXC_SRC_CPU);
49066: goto endlabel2803;
49067: }
49068: {{ uae_s32 src = get_long(srca);
49069: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
49070: { int flgs = ((uae_s32)(src)) < 0;
49071: int flgo = ((uae_s32)(0)) < 0;
49072: int flgn = ((uae_s32)(dst)) < 0;
49073: SET_ZFLG (((uae_s32)(dst)) == 0);
49074: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
49075: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
49076: COPY_CARRY;
49077: SET_NFLG (flgn != 0);
49078: m68k_incpc(4);
49079: fill_prefetch_0 ();
49080: put_long(srca,dst);
49081: }}}}}}}endlabel2803: ;
49082: return 24;
49083: }
49084: unsigned long REGPARAM2 CPUFUNC(op_44b0_5)(uae_u32 opcode) /* NEG */
49085: {
49086: uae_u32 srcreg = (opcode & 7);
49087: OpcodeFamily = 15; CurrentInstrCycles = 26;
49088: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
49089: BusCyclePenalty += 2;
49090: if ((srca & 1) != 0) {
49091: last_fault_for_exception_3 = srca;
49092: last_op_for_exception_3 = opcode;
49093: last_addr_for_exception_3 = m68k_getpc() + 4;
49094: Exception(3, 0, M68000_EXC_SRC_CPU);
49095: goto endlabel2804;
49096: }
49097: {{ uae_s32 src = get_long(srca);
49098: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
49099: { int flgs = ((uae_s32)(src)) < 0;
49100: int flgo = ((uae_s32)(0)) < 0;
49101: int flgn = ((uae_s32)(dst)) < 0;
49102: SET_ZFLG (((uae_s32)(dst)) == 0);
49103: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
49104: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
49105: COPY_CARRY;
49106: SET_NFLG (flgn != 0);
49107: m68k_incpc(4);
49108: fill_prefetch_0 ();
49109: put_long(srca,dst);
49110: }}}}}}}endlabel2804: ;
49111: return 26;
49112: }
49113: unsigned long REGPARAM2 CPUFUNC(op_44b8_5)(uae_u32 opcode) /* NEG */
49114: {
49115: OpcodeFamily = 15; CurrentInstrCycles = 24;
49116: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
49117: if ((srca & 1) != 0) {
49118: last_fault_for_exception_3 = srca;
49119: last_op_for_exception_3 = opcode;
49120: last_addr_for_exception_3 = m68k_getpc() + 4;
49121: Exception(3, 0, M68000_EXC_SRC_CPU);
49122: goto endlabel2805;
49123: }
49124: {{ uae_s32 src = get_long(srca);
49125: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
49126: { int flgs = ((uae_s32)(src)) < 0;
49127: int flgo = ((uae_s32)(0)) < 0;
49128: int flgn = ((uae_s32)(dst)) < 0;
49129: SET_ZFLG (((uae_s32)(dst)) == 0);
49130: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
49131: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
49132: COPY_CARRY;
49133: SET_NFLG (flgn != 0);
49134: m68k_incpc(4);
49135: fill_prefetch_0 ();
49136: put_long(srca,dst);
49137: }}}}}}}endlabel2805: ;
49138: return 24;
49139: }
49140: unsigned long REGPARAM2 CPUFUNC(op_44b9_5)(uae_u32 opcode) /* NEG */
49141: {
49142: OpcodeFamily = 15; CurrentInstrCycles = 28;
49143: {{ uaecptr srca = get_ilong_prefetch(2);
49144: if ((srca & 1) != 0) {
49145: last_fault_for_exception_3 = srca;
49146: last_op_for_exception_3 = opcode;
49147: last_addr_for_exception_3 = m68k_getpc() + 6;
49148: Exception(3, 0, M68000_EXC_SRC_CPU);
49149: goto endlabel2806;
49150: }
49151: {{ uae_s32 src = get_long(srca);
49152: {{uae_u32 dst = ((uae_s32)(0)) - ((uae_s32)(src));
49153: { int flgs = ((uae_s32)(src)) < 0;
49154: int flgo = ((uae_s32)(0)) < 0;
49155: int flgn = ((uae_s32)(dst)) < 0;
49156: SET_ZFLG (((uae_s32)(dst)) == 0);
49157: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
49158: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
49159: COPY_CARRY;
49160: SET_NFLG (flgn != 0);
49161: m68k_incpc(6);
49162: fill_prefetch_0 ();
49163: put_long(srca,dst);
49164: }}}}}}}endlabel2806: ;
49165: return 28;
49166: }
49167: unsigned long REGPARAM2 CPUFUNC(op_44c0_5)(uae_u32 opcode) /* MV2SR */
49168: {
49169: uae_u32 srcreg = (opcode & 7);
49170: OpcodeFamily = 33; CurrentInstrCycles = 12;
49171: {{ uae_s16 src = m68k_dreg(regs, srcreg);
49172: MakeSR();
49173: regs.sr &= 0xFF00;
49174: regs.sr |= src & 0xFF;
49175: MakeFromSR();
49176: }}m68k_incpc(2);
49177: fill_prefetch_2 ();
49178: return 12;
49179: }
49180: unsigned long REGPARAM2 CPUFUNC(op_44d0_5)(uae_u32 opcode) /* MV2SR */
49181: {
49182: uae_u32 srcreg = (opcode & 7);
49183: OpcodeFamily = 33; CurrentInstrCycles = 16;
49184: {{ uaecptr srca = m68k_areg(regs, srcreg);
49185: if ((srca & 1) != 0) {
49186: last_fault_for_exception_3 = srca;
49187: last_op_for_exception_3 = opcode;
49188: last_addr_for_exception_3 = m68k_getpc() + 2;
49189: Exception(3, 0, M68000_EXC_SRC_CPU);
49190: goto endlabel2808;
49191: }
49192: {{ uae_s16 src = get_word(srca);
49193: MakeSR();
49194: regs.sr &= 0xFF00;
49195: regs.sr |= src & 0xFF;
49196: MakeFromSR();
49197: }}}}m68k_incpc(2);
49198: fill_prefetch_2 ();
49199: endlabel2808: ;
49200: return 16;
49201: }
49202: unsigned long REGPARAM2 CPUFUNC(op_44d8_5)(uae_u32 opcode) /* MV2SR */
49203: {
49204: uae_u32 srcreg = (opcode & 7);
49205: OpcodeFamily = 33; CurrentInstrCycles = 16;
49206: {{ uaecptr srca = m68k_areg(regs, srcreg);
49207: if ((srca & 1) != 0) {
49208: last_fault_for_exception_3 = srca;
49209: last_op_for_exception_3 = opcode;
49210: last_addr_for_exception_3 = m68k_getpc() + 2;
49211: Exception(3, 0, M68000_EXC_SRC_CPU);
49212: goto endlabel2809;
49213: }
49214: {{ uae_s16 src = get_word(srca);
49215: m68k_areg(regs, srcreg) += 2;
49216: MakeSR();
49217: regs.sr &= 0xFF00;
49218: regs.sr |= src & 0xFF;
49219: MakeFromSR();
49220: }}}}m68k_incpc(2);
49221: fill_prefetch_2 ();
49222: endlabel2809: ;
49223: return 16;
49224: }
49225: unsigned long REGPARAM2 CPUFUNC(op_44e0_5)(uae_u32 opcode) /* MV2SR */
49226: {
49227: uae_u32 srcreg = (opcode & 7);
49228: OpcodeFamily = 33; CurrentInstrCycles = 18;
49229: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
49230: if ((srca & 1) != 0) {
49231: last_fault_for_exception_3 = srca;
49232: last_op_for_exception_3 = opcode;
49233: last_addr_for_exception_3 = m68k_getpc() + 2;
49234: Exception(3, 0, M68000_EXC_SRC_CPU);
49235: goto endlabel2810;
49236: }
49237: {{ uae_s16 src = get_word(srca);
49238: m68k_areg (regs, srcreg) = srca;
49239: MakeSR();
49240: regs.sr &= 0xFF00;
49241: regs.sr |= src & 0xFF;
49242: MakeFromSR();
49243: }}}}m68k_incpc(2);
49244: fill_prefetch_2 ();
49245: endlabel2810: ;
49246: return 18;
49247: }
49248: unsigned long REGPARAM2 CPUFUNC(op_44e8_5)(uae_u32 opcode) /* MV2SR */
49249: {
49250: uae_u32 srcreg = (opcode & 7);
49251: OpcodeFamily = 33; CurrentInstrCycles = 20;
49252: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
49253: if ((srca & 1) != 0) {
49254: last_fault_for_exception_3 = srca;
49255: last_op_for_exception_3 = opcode;
49256: last_addr_for_exception_3 = m68k_getpc() + 4;
49257: Exception(3, 0, M68000_EXC_SRC_CPU);
49258: goto endlabel2811;
49259: }
49260: {{ uae_s16 src = get_word(srca);
49261: MakeSR();
49262: regs.sr &= 0xFF00;
49263: regs.sr |= src & 0xFF;
49264: MakeFromSR();
49265: }}}}m68k_incpc(4);
49266: fill_prefetch_0 ();
49267: endlabel2811: ;
49268: return 20;
49269: }
49270: unsigned long REGPARAM2 CPUFUNC(op_44f0_5)(uae_u32 opcode) /* MV2SR */
49271: {
49272: uae_u32 srcreg = (opcode & 7);
49273: OpcodeFamily = 33; CurrentInstrCycles = 22;
49274: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
49275: BusCyclePenalty += 2;
49276: if ((srca & 1) != 0) {
49277: last_fault_for_exception_3 = srca;
49278: last_op_for_exception_3 = opcode;
49279: last_addr_for_exception_3 = m68k_getpc() + 4;
49280: Exception(3, 0, M68000_EXC_SRC_CPU);
49281: goto endlabel2812;
49282: }
49283: {{ uae_s16 src = get_word(srca);
49284: MakeSR();
49285: regs.sr &= 0xFF00;
49286: regs.sr |= src & 0xFF;
49287: MakeFromSR();
49288: }}}}m68k_incpc(4);
49289: fill_prefetch_0 ();
49290: endlabel2812: ;
49291: return 22;
49292: }
49293: unsigned long REGPARAM2 CPUFUNC(op_44f8_5)(uae_u32 opcode) /* MV2SR */
49294: {
49295: OpcodeFamily = 33; CurrentInstrCycles = 20;
49296: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
49297: if ((srca & 1) != 0) {
49298: last_fault_for_exception_3 = srca;
49299: last_op_for_exception_3 = opcode;
49300: last_addr_for_exception_3 = m68k_getpc() + 4;
49301: Exception(3, 0, M68000_EXC_SRC_CPU);
49302: goto endlabel2813;
49303: }
49304: {{ uae_s16 src = get_word(srca);
49305: MakeSR();
49306: regs.sr &= 0xFF00;
49307: regs.sr |= src & 0xFF;
49308: MakeFromSR();
49309: }}}}m68k_incpc(4);
49310: fill_prefetch_0 ();
49311: endlabel2813: ;
49312: return 20;
49313: }
49314: unsigned long REGPARAM2 CPUFUNC(op_44f9_5)(uae_u32 opcode) /* MV2SR */
49315: {
49316: OpcodeFamily = 33; CurrentInstrCycles = 24;
49317: {{ uaecptr srca = get_ilong_prefetch(2);
49318: if ((srca & 1) != 0) {
49319: last_fault_for_exception_3 = srca;
49320: last_op_for_exception_3 = opcode;
49321: last_addr_for_exception_3 = m68k_getpc() + 6;
49322: Exception(3, 0, M68000_EXC_SRC_CPU);
49323: goto endlabel2814;
49324: }
49325: {{ uae_s16 src = get_word(srca);
49326: MakeSR();
49327: regs.sr &= 0xFF00;
49328: regs.sr |= src & 0xFF;
49329: MakeFromSR();
49330: }}}}m68k_incpc(6);
49331: fill_prefetch_0 ();
49332: endlabel2814: ;
49333: return 24;
49334: }
49335: unsigned long REGPARAM2 CPUFUNC(op_44fa_5)(uae_u32 opcode) /* MV2SR */
49336: {
49337: OpcodeFamily = 33; CurrentInstrCycles = 20;
49338: {{ uaecptr srca = m68k_getpc () + 2;
49339: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
49340: if ((srca & 1) != 0) {
49341: last_fault_for_exception_3 = srca;
49342: last_op_for_exception_3 = opcode;
49343: last_addr_for_exception_3 = m68k_getpc() + 4;
49344: Exception(3, 0, M68000_EXC_SRC_CPU);
49345: goto endlabel2815;
49346: }
49347: {{ uae_s16 src = get_word(srca);
49348: MakeSR();
49349: regs.sr &= 0xFF00;
49350: regs.sr |= src & 0xFF;
49351: MakeFromSR();
49352: }}}}m68k_incpc(4);
49353: fill_prefetch_0 ();
49354: endlabel2815: ;
49355: return 20;
49356: }
49357: unsigned long REGPARAM2 CPUFUNC(op_44fb_5)(uae_u32 opcode) /* MV2SR */
49358: {
49359: OpcodeFamily = 33; CurrentInstrCycles = 22;
49360: {{ uaecptr tmppc = m68k_getpc() + 2;
49361: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
49362: BusCyclePenalty += 2;
49363: if ((srca & 1) != 0) {
49364: last_fault_for_exception_3 = srca;
49365: last_op_for_exception_3 = opcode;
49366: last_addr_for_exception_3 = m68k_getpc() + 4;
49367: Exception(3, 0, M68000_EXC_SRC_CPU);
49368: goto endlabel2816;
49369: }
49370: {{ uae_s16 src = get_word(srca);
49371: MakeSR();
49372: regs.sr &= 0xFF00;
49373: regs.sr |= src & 0xFF;
49374: MakeFromSR();
49375: }}}}m68k_incpc(4);
49376: fill_prefetch_0 ();
49377: endlabel2816: ;
49378: return 22;
49379: }
49380: unsigned long REGPARAM2 CPUFUNC(op_44fc_5)(uae_u32 opcode) /* MV2SR */
49381: {
49382: OpcodeFamily = 33; CurrentInstrCycles = 16;
49383: {{ uae_s16 src = get_iword_prefetch(2);
49384: MakeSR();
49385: regs.sr &= 0xFF00;
49386: regs.sr |= src & 0xFF;
49387: MakeFromSR();
49388: }}m68k_incpc(4);
49389: fill_prefetch_0 ();
49390: return 16;
49391: }
49392: unsigned long REGPARAM2 CPUFUNC(op_4600_5)(uae_u32 opcode) /* NOT */
49393: {
49394: uae_u32 srcreg = (opcode & 7);
49395: OpcodeFamily = 19; CurrentInstrCycles = 4;
49396: {{ uae_s8 src = m68k_dreg(regs, srcreg);
49397: { uae_u32 dst = ~src;
49398: CLEAR_CZNV;
49399: SET_ZFLG (((uae_s8)(dst)) == 0);
49400: SET_NFLG (((uae_s8)(dst)) < 0);
49401: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
49402: }}}m68k_incpc(2);
49403: fill_prefetch_2 ();
49404: return 4;
49405: }
49406: unsigned long REGPARAM2 CPUFUNC(op_4610_5)(uae_u32 opcode) /* NOT */
49407: {
49408: uae_u32 srcreg = (opcode & 7);
49409: OpcodeFamily = 19; CurrentInstrCycles = 12;
49410: {{ uaecptr srca = m68k_areg(regs, srcreg);
49411: { uae_s8 src = get_byte(srca);
49412: { uae_u32 dst = ~src;
49413: CLEAR_CZNV;
49414: SET_ZFLG (((uae_s8)(dst)) == 0);
49415: SET_NFLG (((uae_s8)(dst)) < 0);
49416: m68k_incpc(2);
49417: fill_prefetch_2 ();
49418: put_byte(srca,dst);
49419: }}}}return 12;
49420: }
49421: unsigned long REGPARAM2 CPUFUNC(op_4618_5)(uae_u32 opcode) /* NOT */
49422: {
49423: uae_u32 srcreg = (opcode & 7);
49424: OpcodeFamily = 19; CurrentInstrCycles = 12;
49425: {{ uaecptr srca = m68k_areg(regs, srcreg);
49426: { uae_s8 src = get_byte(srca);
49427: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
49428: { uae_u32 dst = ~src;
49429: CLEAR_CZNV;
49430: SET_ZFLG (((uae_s8)(dst)) == 0);
49431: SET_NFLG (((uae_s8)(dst)) < 0);
49432: m68k_incpc(2);
49433: fill_prefetch_2 ();
49434: put_byte(srca,dst);
49435: }}}}return 12;
49436: }
49437: unsigned long REGPARAM2 CPUFUNC(op_4620_5)(uae_u32 opcode) /* NOT */
49438: {
49439: uae_u32 srcreg = (opcode & 7);
49440: OpcodeFamily = 19; CurrentInstrCycles = 14;
49441: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
49442: { uae_s8 src = get_byte(srca);
49443: m68k_areg (regs, srcreg) = srca;
49444: { uae_u32 dst = ~src;
49445: CLEAR_CZNV;
49446: SET_ZFLG (((uae_s8)(dst)) == 0);
49447: SET_NFLG (((uae_s8)(dst)) < 0);
49448: m68k_incpc(2);
49449: fill_prefetch_2 ();
49450: put_byte(srca,dst);
49451: }}}}return 14;
49452: }
49453: unsigned long REGPARAM2 CPUFUNC(op_4628_5)(uae_u32 opcode) /* NOT */
49454: {
49455: uae_u32 srcreg = (opcode & 7);
49456: OpcodeFamily = 19; CurrentInstrCycles = 16;
49457: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
49458: { uae_s8 src = get_byte(srca);
49459: { uae_u32 dst = ~src;
49460: CLEAR_CZNV;
49461: SET_ZFLG (((uae_s8)(dst)) == 0);
49462: SET_NFLG (((uae_s8)(dst)) < 0);
49463: m68k_incpc(4);
49464: fill_prefetch_0 ();
49465: put_byte(srca,dst);
49466: }}}}return 16;
49467: }
49468: unsigned long REGPARAM2 CPUFUNC(op_4630_5)(uae_u32 opcode) /* NOT */
49469: {
49470: uae_u32 srcreg = (opcode & 7);
49471: OpcodeFamily = 19; CurrentInstrCycles = 18;
49472: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
49473: BusCyclePenalty += 2;
49474: { uae_s8 src = get_byte(srca);
49475: { uae_u32 dst = ~src;
49476: CLEAR_CZNV;
49477: SET_ZFLG (((uae_s8)(dst)) == 0);
49478: SET_NFLG (((uae_s8)(dst)) < 0);
49479: m68k_incpc(4);
49480: fill_prefetch_0 ();
49481: put_byte(srca,dst);
49482: }}}}return 18;
49483: }
49484: unsigned long REGPARAM2 CPUFUNC(op_4638_5)(uae_u32 opcode) /* NOT */
49485: {
49486: OpcodeFamily = 19; CurrentInstrCycles = 16;
49487: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
49488: { uae_s8 src = get_byte(srca);
49489: { uae_u32 dst = ~src;
49490: CLEAR_CZNV;
49491: SET_ZFLG (((uae_s8)(dst)) == 0);
49492: SET_NFLG (((uae_s8)(dst)) < 0);
49493: m68k_incpc(4);
49494: fill_prefetch_0 ();
49495: put_byte(srca,dst);
49496: }}}}return 16;
49497: }
49498: unsigned long REGPARAM2 CPUFUNC(op_4639_5)(uae_u32 opcode) /* NOT */
49499: {
49500: OpcodeFamily = 19; CurrentInstrCycles = 20;
49501: {{ uaecptr srca = get_ilong_prefetch(2);
49502: { uae_s8 src = get_byte(srca);
49503: { uae_u32 dst = ~src;
49504: CLEAR_CZNV;
49505: SET_ZFLG (((uae_s8)(dst)) == 0);
49506: SET_NFLG (((uae_s8)(dst)) < 0);
49507: m68k_incpc(6);
49508: fill_prefetch_0 ();
49509: put_byte(srca,dst);
49510: }}}}return 20;
49511: }
49512: unsigned long REGPARAM2 CPUFUNC(op_4640_5)(uae_u32 opcode) /* NOT */
49513: {
49514: uae_u32 srcreg = (opcode & 7);
49515: OpcodeFamily = 19; CurrentInstrCycles = 4;
49516: {{ uae_s16 src = m68k_dreg(regs, srcreg);
49517: { uae_u32 dst = ~src;
49518: CLEAR_CZNV;
49519: SET_ZFLG (((uae_s16)(dst)) == 0);
49520: SET_NFLG (((uae_s16)(dst)) < 0);
49521: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
49522: }}}m68k_incpc(2);
49523: fill_prefetch_2 ();
49524: return 4;
49525: }
49526: unsigned long REGPARAM2 CPUFUNC(op_4650_5)(uae_u32 opcode) /* NOT */
49527: {
49528: uae_u32 srcreg = (opcode & 7);
49529: OpcodeFamily = 19; CurrentInstrCycles = 12;
49530: {{ uaecptr srca = m68k_areg(regs, srcreg);
49531: if ((srca & 1) != 0) {
49532: last_fault_for_exception_3 = srca;
49533: last_op_for_exception_3 = opcode;
49534: last_addr_for_exception_3 = m68k_getpc() + 2;
49535: Exception(3, 0, M68000_EXC_SRC_CPU);
49536: goto endlabel2827;
49537: }
49538: {{ uae_s16 src = get_word(srca);
49539: { uae_u32 dst = ~src;
49540: CLEAR_CZNV;
49541: SET_ZFLG (((uae_s16)(dst)) == 0);
49542: SET_NFLG (((uae_s16)(dst)) < 0);
49543: m68k_incpc(2);
49544: fill_prefetch_2 ();
49545: put_word(srca,dst);
49546: }}}}}endlabel2827: ;
49547: return 12;
49548: }
49549: unsigned long REGPARAM2 CPUFUNC(op_4658_5)(uae_u32 opcode) /* NOT */
49550: {
49551: uae_u32 srcreg = (opcode & 7);
49552: OpcodeFamily = 19; CurrentInstrCycles = 12;
49553: {{ uaecptr srca = m68k_areg(regs, srcreg);
49554: if ((srca & 1) != 0) {
49555: last_fault_for_exception_3 = srca;
49556: last_op_for_exception_3 = opcode;
49557: last_addr_for_exception_3 = m68k_getpc() + 2;
49558: Exception(3, 0, M68000_EXC_SRC_CPU);
49559: goto endlabel2828;
49560: }
49561: {{ uae_s16 src = get_word(srca);
49562: m68k_areg(regs, srcreg) += 2;
49563: { uae_u32 dst = ~src;
49564: CLEAR_CZNV;
49565: SET_ZFLG (((uae_s16)(dst)) == 0);
49566: SET_NFLG (((uae_s16)(dst)) < 0);
49567: m68k_incpc(2);
49568: fill_prefetch_2 ();
49569: put_word(srca,dst);
49570: }}}}}endlabel2828: ;
49571: return 12;
49572: }
49573: unsigned long REGPARAM2 CPUFUNC(op_4660_5)(uae_u32 opcode) /* NOT */
49574: {
49575: uae_u32 srcreg = (opcode & 7);
49576: OpcodeFamily = 19; CurrentInstrCycles = 14;
49577: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
49578: if ((srca & 1) != 0) {
49579: last_fault_for_exception_3 = srca;
49580: last_op_for_exception_3 = opcode;
49581: last_addr_for_exception_3 = m68k_getpc() + 2;
49582: Exception(3, 0, M68000_EXC_SRC_CPU);
49583: goto endlabel2829;
49584: }
49585: {{ uae_s16 src = get_word(srca);
49586: m68k_areg (regs, srcreg) = srca;
49587: { uae_u32 dst = ~src;
49588: CLEAR_CZNV;
49589: SET_ZFLG (((uae_s16)(dst)) == 0);
49590: SET_NFLG (((uae_s16)(dst)) < 0);
49591: m68k_incpc(2);
49592: fill_prefetch_2 ();
49593: put_word(srca,dst);
49594: }}}}}endlabel2829: ;
49595: return 14;
49596: }
49597: unsigned long REGPARAM2 CPUFUNC(op_4668_5)(uae_u32 opcode) /* NOT */
49598: {
49599: uae_u32 srcreg = (opcode & 7);
49600: OpcodeFamily = 19; CurrentInstrCycles = 16;
49601: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
49602: if ((srca & 1) != 0) {
49603: last_fault_for_exception_3 = srca;
49604: last_op_for_exception_3 = opcode;
49605: last_addr_for_exception_3 = m68k_getpc() + 4;
49606: Exception(3, 0, M68000_EXC_SRC_CPU);
49607: goto endlabel2830;
49608: }
49609: {{ uae_s16 src = get_word(srca);
49610: { uae_u32 dst = ~src;
49611: CLEAR_CZNV;
49612: SET_ZFLG (((uae_s16)(dst)) == 0);
49613: SET_NFLG (((uae_s16)(dst)) < 0);
49614: m68k_incpc(4);
49615: fill_prefetch_0 ();
49616: put_word(srca,dst);
49617: }}}}}endlabel2830: ;
49618: return 16;
49619: }
49620: unsigned long REGPARAM2 CPUFUNC(op_4670_5)(uae_u32 opcode) /* NOT */
49621: {
49622: uae_u32 srcreg = (opcode & 7);
49623: OpcodeFamily = 19; CurrentInstrCycles = 18;
49624: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
49625: BusCyclePenalty += 2;
49626: if ((srca & 1) != 0) {
49627: last_fault_for_exception_3 = srca;
49628: last_op_for_exception_3 = opcode;
49629: last_addr_for_exception_3 = m68k_getpc() + 4;
49630: Exception(3, 0, M68000_EXC_SRC_CPU);
49631: goto endlabel2831;
49632: }
49633: {{ uae_s16 src = get_word(srca);
49634: { uae_u32 dst = ~src;
49635: CLEAR_CZNV;
49636: SET_ZFLG (((uae_s16)(dst)) == 0);
49637: SET_NFLG (((uae_s16)(dst)) < 0);
49638: m68k_incpc(4);
49639: fill_prefetch_0 ();
49640: put_word(srca,dst);
49641: }}}}}endlabel2831: ;
49642: return 18;
49643: }
49644: unsigned long REGPARAM2 CPUFUNC(op_4678_5)(uae_u32 opcode) /* NOT */
49645: {
49646: OpcodeFamily = 19; CurrentInstrCycles = 16;
49647: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
49648: if ((srca & 1) != 0) {
49649: last_fault_for_exception_3 = srca;
49650: last_op_for_exception_3 = opcode;
49651: last_addr_for_exception_3 = m68k_getpc() + 4;
49652: Exception(3, 0, M68000_EXC_SRC_CPU);
49653: goto endlabel2832;
49654: }
49655: {{ uae_s16 src = get_word(srca);
49656: { uae_u32 dst = ~src;
49657: CLEAR_CZNV;
49658: SET_ZFLG (((uae_s16)(dst)) == 0);
49659: SET_NFLG (((uae_s16)(dst)) < 0);
49660: m68k_incpc(4);
49661: fill_prefetch_0 ();
49662: put_word(srca,dst);
49663: }}}}}endlabel2832: ;
49664: return 16;
49665: }
49666: unsigned long REGPARAM2 CPUFUNC(op_4679_5)(uae_u32 opcode) /* NOT */
49667: {
49668: OpcodeFamily = 19; CurrentInstrCycles = 20;
49669: {{ uaecptr srca = get_ilong_prefetch(2);
49670: if ((srca & 1) != 0) {
49671: last_fault_for_exception_3 = srca;
49672: last_op_for_exception_3 = opcode;
49673: last_addr_for_exception_3 = m68k_getpc() + 6;
49674: Exception(3, 0, M68000_EXC_SRC_CPU);
49675: goto endlabel2833;
49676: }
49677: {{ uae_s16 src = get_word(srca);
49678: { uae_u32 dst = ~src;
49679: CLEAR_CZNV;
49680: SET_ZFLG (((uae_s16)(dst)) == 0);
49681: SET_NFLG (((uae_s16)(dst)) < 0);
49682: m68k_incpc(6);
49683: fill_prefetch_0 ();
49684: put_word(srca,dst);
49685: }}}}}endlabel2833: ;
49686: return 20;
49687: }
49688: unsigned long REGPARAM2 CPUFUNC(op_4680_5)(uae_u32 opcode) /* NOT */
49689: {
49690: uae_u32 srcreg = (opcode & 7);
49691: OpcodeFamily = 19; CurrentInstrCycles = 6;
49692: {{ uae_s32 src = m68k_dreg(regs, srcreg);
49693: { uae_u32 dst = ~src;
49694: CLEAR_CZNV;
49695: SET_ZFLG (((uae_s32)(dst)) == 0);
49696: SET_NFLG (((uae_s32)(dst)) < 0);
49697: m68k_dreg(regs, srcreg) = (dst);
49698: }}}m68k_incpc(2);
49699: fill_prefetch_2 ();
49700: return 6;
49701: }
49702: unsigned long REGPARAM2 CPUFUNC(op_4690_5)(uae_u32 opcode) /* NOT */
49703: {
49704: uae_u32 srcreg = (opcode & 7);
49705: OpcodeFamily = 19; CurrentInstrCycles = 20;
49706: {{ uaecptr srca = m68k_areg(regs, srcreg);
49707: if ((srca & 1) != 0) {
49708: last_fault_for_exception_3 = srca;
49709: last_op_for_exception_3 = opcode;
49710: last_addr_for_exception_3 = m68k_getpc() + 2;
49711: Exception(3, 0, M68000_EXC_SRC_CPU);
49712: goto endlabel2835;
49713: }
49714: {{ uae_s32 src = get_long(srca);
49715: { uae_u32 dst = ~src;
49716: CLEAR_CZNV;
49717: SET_ZFLG (((uae_s32)(dst)) == 0);
49718: SET_NFLG (((uae_s32)(dst)) < 0);
49719: m68k_incpc(2);
49720: fill_prefetch_2 ();
49721: put_long(srca,dst);
49722: }}}}}endlabel2835: ;
49723: return 20;
49724: }
49725: unsigned long REGPARAM2 CPUFUNC(op_4698_5)(uae_u32 opcode) /* NOT */
49726: {
49727: uae_u32 srcreg = (opcode & 7);
49728: OpcodeFamily = 19; CurrentInstrCycles = 20;
49729: {{ uaecptr srca = m68k_areg(regs, srcreg);
49730: if ((srca & 1) != 0) {
49731: last_fault_for_exception_3 = srca;
49732: last_op_for_exception_3 = opcode;
49733: last_addr_for_exception_3 = m68k_getpc() + 2;
49734: Exception(3, 0, M68000_EXC_SRC_CPU);
49735: goto endlabel2836;
49736: }
49737: {{ uae_s32 src = get_long(srca);
49738: m68k_areg(regs, srcreg) += 4;
49739: { uae_u32 dst = ~src;
49740: CLEAR_CZNV;
49741: SET_ZFLG (((uae_s32)(dst)) == 0);
49742: SET_NFLG (((uae_s32)(dst)) < 0);
49743: m68k_incpc(2);
49744: fill_prefetch_2 ();
49745: put_long(srca,dst);
49746: }}}}}endlabel2836: ;
49747: return 20;
49748: }
49749: unsigned long REGPARAM2 CPUFUNC(op_46a0_5)(uae_u32 opcode) /* NOT */
49750: {
49751: uae_u32 srcreg = (opcode & 7);
49752: OpcodeFamily = 19; CurrentInstrCycles = 22;
49753: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
49754: if ((srca & 1) != 0) {
49755: last_fault_for_exception_3 = srca;
49756: last_op_for_exception_3 = opcode;
49757: last_addr_for_exception_3 = m68k_getpc() + 2;
49758: Exception(3, 0, M68000_EXC_SRC_CPU);
49759: goto endlabel2837;
49760: }
49761: {{ uae_s32 src = get_long(srca);
49762: m68k_areg (regs, srcreg) = srca;
49763: { uae_u32 dst = ~src;
49764: CLEAR_CZNV;
49765: SET_ZFLG (((uae_s32)(dst)) == 0);
49766: SET_NFLG (((uae_s32)(dst)) < 0);
49767: m68k_incpc(2);
49768: fill_prefetch_2 ();
49769: put_long(srca,dst);
49770: }}}}}endlabel2837: ;
49771: return 22;
49772: }
49773: unsigned long REGPARAM2 CPUFUNC(op_46a8_5)(uae_u32 opcode) /* NOT */
49774: {
49775: uae_u32 srcreg = (opcode & 7);
49776: OpcodeFamily = 19; CurrentInstrCycles = 24;
49777: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
49778: if ((srca & 1) != 0) {
49779: last_fault_for_exception_3 = srca;
49780: last_op_for_exception_3 = opcode;
49781: last_addr_for_exception_3 = m68k_getpc() + 4;
49782: Exception(3, 0, M68000_EXC_SRC_CPU);
49783: goto endlabel2838;
49784: }
49785: {{ uae_s32 src = get_long(srca);
49786: { uae_u32 dst = ~src;
49787: CLEAR_CZNV;
49788: SET_ZFLG (((uae_s32)(dst)) == 0);
49789: SET_NFLG (((uae_s32)(dst)) < 0);
49790: m68k_incpc(4);
49791: fill_prefetch_0 ();
49792: put_long(srca,dst);
49793: }}}}}endlabel2838: ;
49794: return 24;
49795: }
49796: unsigned long REGPARAM2 CPUFUNC(op_46b0_5)(uae_u32 opcode) /* NOT */
49797: {
49798: uae_u32 srcreg = (opcode & 7);
49799: OpcodeFamily = 19; CurrentInstrCycles = 26;
49800: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
49801: BusCyclePenalty += 2;
49802: if ((srca & 1) != 0) {
49803: last_fault_for_exception_3 = srca;
49804: last_op_for_exception_3 = opcode;
49805: last_addr_for_exception_3 = m68k_getpc() + 4;
49806: Exception(3, 0, M68000_EXC_SRC_CPU);
49807: goto endlabel2839;
49808: }
49809: {{ uae_s32 src = get_long(srca);
49810: { uae_u32 dst = ~src;
49811: CLEAR_CZNV;
49812: SET_ZFLG (((uae_s32)(dst)) == 0);
49813: SET_NFLG (((uae_s32)(dst)) < 0);
49814: m68k_incpc(4);
49815: fill_prefetch_0 ();
49816: put_long(srca,dst);
49817: }}}}}endlabel2839: ;
49818: return 26;
49819: }
49820: unsigned long REGPARAM2 CPUFUNC(op_46b8_5)(uae_u32 opcode) /* NOT */
49821: {
49822: OpcodeFamily = 19; CurrentInstrCycles = 24;
49823: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
49824: if ((srca & 1) != 0) {
49825: last_fault_for_exception_3 = srca;
49826: last_op_for_exception_3 = opcode;
49827: last_addr_for_exception_3 = m68k_getpc() + 4;
49828: Exception(3, 0, M68000_EXC_SRC_CPU);
49829: goto endlabel2840;
49830: }
49831: {{ uae_s32 src = get_long(srca);
49832: { uae_u32 dst = ~src;
49833: CLEAR_CZNV;
49834: SET_ZFLG (((uae_s32)(dst)) == 0);
49835: SET_NFLG (((uae_s32)(dst)) < 0);
49836: m68k_incpc(4);
49837: fill_prefetch_0 ();
49838: put_long(srca,dst);
49839: }}}}}endlabel2840: ;
49840: return 24;
49841: }
49842: unsigned long REGPARAM2 CPUFUNC(op_46b9_5)(uae_u32 opcode) /* NOT */
49843: {
49844: OpcodeFamily = 19; CurrentInstrCycles = 28;
49845: {{ uaecptr srca = get_ilong_prefetch(2);
49846: if ((srca & 1) != 0) {
49847: last_fault_for_exception_3 = srca;
49848: last_op_for_exception_3 = opcode;
49849: last_addr_for_exception_3 = m68k_getpc() + 6;
49850: Exception(3, 0, M68000_EXC_SRC_CPU);
49851: goto endlabel2841;
49852: }
49853: {{ uae_s32 src = get_long(srca);
49854: { uae_u32 dst = ~src;
49855: CLEAR_CZNV;
49856: SET_ZFLG (((uae_s32)(dst)) == 0);
49857: SET_NFLG (((uae_s32)(dst)) < 0);
49858: m68k_incpc(6);
49859: fill_prefetch_0 ();
49860: put_long(srca,dst);
49861: }}}}}endlabel2841: ;
49862: return 28;
49863: }
49864: unsigned long REGPARAM2 CPUFUNC(op_46c0_5)(uae_u32 opcode) /* MV2SR */
49865: {
49866: uae_u32 srcreg = (opcode & 7);
49867: OpcodeFamily = 33; CurrentInstrCycles = 12;
49868: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2842; }
49869: {{ uae_s16 src = m68k_dreg(regs, srcreg);
49870: regs.sr = src;
49871: MakeFromSR();
49872: }}}m68k_incpc(2);
49873: fill_prefetch_2 ();
49874: endlabel2842: ;
49875: return 12;
49876: }
49877: unsigned long REGPARAM2 CPUFUNC(op_46d0_5)(uae_u32 opcode) /* MV2SR */
49878: {
49879: uae_u32 srcreg = (opcode & 7);
49880: OpcodeFamily = 33; CurrentInstrCycles = 16;
49881: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2843; }
49882: {{ uaecptr srca = m68k_areg(regs, srcreg);
49883: if ((srca & 1) != 0) {
49884: last_fault_for_exception_3 = srca;
49885: last_op_for_exception_3 = opcode;
49886: last_addr_for_exception_3 = m68k_getpc() + 2;
49887: Exception(3, 0, M68000_EXC_SRC_CPU);
49888: goto endlabel2843;
49889: }
49890: {{ uae_s16 src = get_word(srca);
49891: regs.sr = src;
49892: MakeFromSR();
49893: }}}}}m68k_incpc(2);
49894: fill_prefetch_2 ();
49895: endlabel2843: ;
49896: return 16;
49897: }
49898: unsigned long REGPARAM2 CPUFUNC(op_46d8_5)(uae_u32 opcode) /* MV2SR */
49899: {
49900: uae_u32 srcreg = (opcode & 7);
49901: OpcodeFamily = 33; CurrentInstrCycles = 16;
49902: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2844; }
49903: {{ uaecptr srca = m68k_areg(regs, srcreg);
49904: if ((srca & 1) != 0) {
49905: last_fault_for_exception_3 = srca;
49906: last_op_for_exception_3 = opcode;
49907: last_addr_for_exception_3 = m68k_getpc() + 2;
49908: Exception(3, 0, M68000_EXC_SRC_CPU);
49909: goto endlabel2844;
49910: }
49911: {{ uae_s16 src = get_word(srca);
49912: m68k_areg(regs, srcreg) += 2;
49913: regs.sr = src;
49914: MakeFromSR();
49915: }}}}}m68k_incpc(2);
49916: fill_prefetch_2 ();
49917: endlabel2844: ;
49918: return 16;
49919: }
49920: unsigned long REGPARAM2 CPUFUNC(op_46e0_5)(uae_u32 opcode) /* MV2SR */
49921: {
49922: uae_u32 srcreg = (opcode & 7);
49923: OpcodeFamily = 33; CurrentInstrCycles = 18;
49924: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2845; }
49925: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
49926: if ((srca & 1) != 0) {
49927: last_fault_for_exception_3 = srca;
49928: last_op_for_exception_3 = opcode;
49929: last_addr_for_exception_3 = m68k_getpc() + 2;
49930: Exception(3, 0, M68000_EXC_SRC_CPU);
49931: goto endlabel2845;
49932: }
49933: {{ uae_s16 src = get_word(srca);
49934: m68k_areg (regs, srcreg) = srca;
49935: regs.sr = src;
49936: MakeFromSR();
49937: }}}}}m68k_incpc(2);
49938: fill_prefetch_2 ();
49939: endlabel2845: ;
49940: return 18;
49941: }
49942: unsigned long REGPARAM2 CPUFUNC(op_46e8_5)(uae_u32 opcode) /* MV2SR */
49943: {
49944: uae_u32 srcreg = (opcode & 7);
49945: OpcodeFamily = 33; CurrentInstrCycles = 20;
49946: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2846; }
49947: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
49948: if ((srca & 1) != 0) {
49949: last_fault_for_exception_3 = srca;
49950: last_op_for_exception_3 = opcode;
49951: last_addr_for_exception_3 = m68k_getpc() + 4;
49952: Exception(3, 0, M68000_EXC_SRC_CPU);
49953: goto endlabel2846;
49954: }
49955: {{ uae_s16 src = get_word(srca);
49956: regs.sr = src;
49957: MakeFromSR();
49958: }}}}}m68k_incpc(4);
49959: fill_prefetch_0 ();
49960: endlabel2846: ;
49961: return 20;
49962: }
49963: unsigned long REGPARAM2 CPUFUNC(op_46f0_5)(uae_u32 opcode) /* MV2SR */
49964: {
49965: uae_u32 srcreg = (opcode & 7);
49966: OpcodeFamily = 33; CurrentInstrCycles = 22;
49967: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2847; }
49968: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
49969: BusCyclePenalty += 2;
49970: if ((srca & 1) != 0) {
49971: last_fault_for_exception_3 = srca;
49972: last_op_for_exception_3 = opcode;
49973: last_addr_for_exception_3 = m68k_getpc() + 4;
49974: Exception(3, 0, M68000_EXC_SRC_CPU);
49975: goto endlabel2847;
49976: }
49977: {{ uae_s16 src = get_word(srca);
49978: regs.sr = src;
49979: MakeFromSR();
49980: }}}}}m68k_incpc(4);
49981: fill_prefetch_0 ();
49982: endlabel2847: ;
49983: return 22;
49984: }
49985: unsigned long REGPARAM2 CPUFUNC(op_46f8_5)(uae_u32 opcode) /* MV2SR */
49986: {
49987: OpcodeFamily = 33; CurrentInstrCycles = 20;
49988: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2848; }
49989: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
49990: if ((srca & 1) != 0) {
49991: last_fault_for_exception_3 = srca;
49992: last_op_for_exception_3 = opcode;
49993: last_addr_for_exception_3 = m68k_getpc() + 4;
49994: Exception(3, 0, M68000_EXC_SRC_CPU);
49995: goto endlabel2848;
49996: }
49997: {{ uae_s16 src = get_word(srca);
49998: regs.sr = src;
49999: MakeFromSR();
50000: }}}}}m68k_incpc(4);
50001: fill_prefetch_0 ();
50002: endlabel2848: ;
50003: return 20;
50004: }
50005: unsigned long REGPARAM2 CPUFUNC(op_46f9_5)(uae_u32 opcode) /* MV2SR */
50006: {
50007: OpcodeFamily = 33; CurrentInstrCycles = 24;
50008: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2849; }
50009: {{ uaecptr srca = get_ilong_prefetch(2);
50010: if ((srca & 1) != 0) {
50011: last_fault_for_exception_3 = srca;
50012: last_op_for_exception_3 = opcode;
50013: last_addr_for_exception_3 = m68k_getpc() + 6;
50014: Exception(3, 0, M68000_EXC_SRC_CPU);
50015: goto endlabel2849;
50016: }
50017: {{ uae_s16 src = get_word(srca);
50018: regs.sr = src;
50019: MakeFromSR();
50020: }}}}}m68k_incpc(6);
50021: fill_prefetch_0 ();
50022: endlabel2849: ;
50023: return 24;
50024: }
50025: unsigned long REGPARAM2 CPUFUNC(op_46fa_5)(uae_u32 opcode) /* MV2SR */
50026: {
50027: OpcodeFamily = 33; CurrentInstrCycles = 20;
50028: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2850; }
50029: {{ uaecptr srca = m68k_getpc () + 2;
50030: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
50031: if ((srca & 1) != 0) {
50032: last_fault_for_exception_3 = srca;
50033: last_op_for_exception_3 = opcode;
50034: last_addr_for_exception_3 = m68k_getpc() + 4;
50035: Exception(3, 0, M68000_EXC_SRC_CPU);
50036: goto endlabel2850;
50037: }
50038: {{ uae_s16 src = get_word(srca);
50039: regs.sr = src;
50040: MakeFromSR();
50041: }}}}}m68k_incpc(4);
50042: fill_prefetch_0 ();
50043: endlabel2850: ;
50044: return 20;
50045: }
50046: unsigned long REGPARAM2 CPUFUNC(op_46fb_5)(uae_u32 opcode) /* MV2SR */
50047: {
50048: OpcodeFamily = 33; CurrentInstrCycles = 22;
50049: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2851; }
50050: {{ uaecptr tmppc = m68k_getpc() + 2;
50051: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
50052: BusCyclePenalty += 2;
50053: if ((srca & 1) != 0) {
50054: last_fault_for_exception_3 = srca;
50055: last_op_for_exception_3 = opcode;
50056: last_addr_for_exception_3 = m68k_getpc() + 4;
50057: Exception(3, 0, M68000_EXC_SRC_CPU);
50058: goto endlabel2851;
50059: }
50060: {{ uae_s16 src = get_word(srca);
50061: regs.sr = src;
50062: MakeFromSR();
50063: }}}}}m68k_incpc(4);
50064: fill_prefetch_0 ();
50065: endlabel2851: ;
50066: return 22;
50067: }
50068: unsigned long REGPARAM2 CPUFUNC(op_46fc_5)(uae_u32 opcode) /* MV2SR */
50069: {
50070: OpcodeFamily = 33; CurrentInstrCycles = 16;
50071: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2852; }
50072: {{ uae_s16 src = get_iword_prefetch(2);
50073: regs.sr = src;
50074: MakeFromSR();
50075: }}}m68k_incpc(4);
50076: fill_prefetch_0 ();
50077: endlabel2852: ;
50078: return 16;
50079: }
50080: unsigned long REGPARAM2 CPUFUNC(op_4800_5)(uae_u32 opcode) /* NBCD */
50081: {
50082: uae_u32 srcreg = (opcode & 7);
50083: OpcodeFamily = 17; CurrentInstrCycles = 6;
50084: {{ uae_s8 src = m68k_dreg(regs, srcreg);
50085: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
50086: uae_u16 newv_hi = - (src & 0xF0);
50087: uae_u16 newv;
50088: int cflg;
50089: if (newv_lo > 9) { newv_lo -= 6; }
50090: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
50091: if (cflg) newv -= 0x60;
50092: SET_CFLG (cflg);
50093: COPY_CARRY;
50094: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
50095: SET_NFLG (((uae_s8)(newv)) < 0);
50096: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
50097: }}}m68k_incpc(2);
50098: fill_prefetch_2 ();
50099: return 6;
50100: }
50101: unsigned long REGPARAM2 CPUFUNC(op_4810_5)(uae_u32 opcode) /* NBCD */
50102: {
50103: uae_u32 srcreg = (opcode & 7);
50104: OpcodeFamily = 17; CurrentInstrCycles = 12;
50105: {{ uaecptr srca = m68k_areg(regs, srcreg);
50106: { uae_s8 src = get_byte(srca);
50107: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
50108: uae_u16 newv_hi = - (src & 0xF0);
50109: uae_u16 newv;
50110: int cflg;
50111: if (newv_lo > 9) { newv_lo -= 6; }
50112: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
50113: if (cflg) newv -= 0x60;
50114: SET_CFLG (cflg);
50115: COPY_CARRY;
50116: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
50117: SET_NFLG (((uae_s8)(newv)) < 0);
50118: m68k_incpc(2);
50119: fill_prefetch_2 ();
50120: put_byte(srca,newv);
50121: }}}}return 12;
50122: }
50123: unsigned long REGPARAM2 CPUFUNC(op_4818_5)(uae_u32 opcode) /* NBCD */
50124: {
50125: uae_u32 srcreg = (opcode & 7);
50126: OpcodeFamily = 17; CurrentInstrCycles = 12;
50127: {{ uaecptr srca = m68k_areg(regs, srcreg);
50128: { uae_s8 src = get_byte(srca);
50129: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
50130: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
50131: uae_u16 newv_hi = - (src & 0xF0);
50132: uae_u16 newv;
50133: int cflg;
50134: if (newv_lo > 9) { newv_lo -= 6; }
50135: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
50136: if (cflg) newv -= 0x60;
50137: SET_CFLG (cflg);
50138: COPY_CARRY;
50139: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
50140: SET_NFLG (((uae_s8)(newv)) < 0);
50141: m68k_incpc(2);
50142: fill_prefetch_2 ();
50143: put_byte(srca,newv);
50144: }}}}return 12;
50145: }
50146: unsigned long REGPARAM2 CPUFUNC(op_4820_5)(uae_u32 opcode) /* NBCD */
50147: {
50148: uae_u32 srcreg = (opcode & 7);
50149: OpcodeFamily = 17; CurrentInstrCycles = 14;
50150: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
50151: { uae_s8 src = get_byte(srca);
50152: m68k_areg (regs, srcreg) = srca;
50153: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
50154: uae_u16 newv_hi = - (src & 0xF0);
50155: uae_u16 newv;
50156: int cflg;
50157: if (newv_lo > 9) { newv_lo -= 6; }
50158: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
50159: if (cflg) newv -= 0x60;
50160: SET_CFLG (cflg);
50161: COPY_CARRY;
50162: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
50163: SET_NFLG (((uae_s8)(newv)) < 0);
50164: m68k_incpc(2);
50165: fill_prefetch_2 ();
50166: put_byte(srca,newv);
50167: }}}}return 14;
50168: }
50169: unsigned long REGPARAM2 CPUFUNC(op_4828_5)(uae_u32 opcode) /* NBCD */
50170: {
50171: uae_u32 srcreg = (opcode & 7);
50172: OpcodeFamily = 17; CurrentInstrCycles = 16;
50173: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
50174: { uae_s8 src = get_byte(srca);
50175: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
50176: uae_u16 newv_hi = - (src & 0xF0);
50177: uae_u16 newv;
50178: int cflg;
50179: if (newv_lo > 9) { newv_lo -= 6; }
50180: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
50181: if (cflg) newv -= 0x60;
50182: SET_CFLG (cflg);
50183: COPY_CARRY;
50184: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
50185: SET_NFLG (((uae_s8)(newv)) < 0);
50186: m68k_incpc(4);
50187: fill_prefetch_0 ();
50188: put_byte(srca,newv);
50189: }}}}return 16;
50190: }
50191: unsigned long REGPARAM2 CPUFUNC(op_4830_5)(uae_u32 opcode) /* NBCD */
50192: {
50193: uae_u32 srcreg = (opcode & 7);
50194: OpcodeFamily = 17; CurrentInstrCycles = 18;
50195: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
50196: BusCyclePenalty += 2;
50197: { uae_s8 src = get_byte(srca);
50198: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
50199: uae_u16 newv_hi = - (src & 0xF0);
50200: uae_u16 newv;
50201: int cflg;
50202: if (newv_lo > 9) { newv_lo -= 6; }
50203: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
50204: if (cflg) newv -= 0x60;
50205: SET_CFLG (cflg);
50206: COPY_CARRY;
50207: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
50208: SET_NFLG (((uae_s8)(newv)) < 0);
50209: m68k_incpc(4);
50210: fill_prefetch_0 ();
50211: put_byte(srca,newv);
50212: }}}}return 18;
50213: }
50214: unsigned long REGPARAM2 CPUFUNC(op_4838_5)(uae_u32 opcode) /* NBCD */
50215: {
50216: OpcodeFamily = 17; CurrentInstrCycles = 16;
50217: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
50218: { uae_s8 src = get_byte(srca);
50219: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
50220: uae_u16 newv_hi = - (src & 0xF0);
50221: uae_u16 newv;
50222: int cflg;
50223: if (newv_lo > 9) { newv_lo -= 6; }
50224: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
50225: if (cflg) newv -= 0x60;
50226: SET_CFLG (cflg);
50227: COPY_CARRY;
50228: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
50229: SET_NFLG (((uae_s8)(newv)) < 0);
50230: m68k_incpc(4);
50231: fill_prefetch_0 ();
50232: put_byte(srca,newv);
50233: }}}}return 16;
50234: }
50235: unsigned long REGPARAM2 CPUFUNC(op_4839_5)(uae_u32 opcode) /* NBCD */
50236: {
50237: OpcodeFamily = 17; CurrentInstrCycles = 20;
50238: {{ uaecptr srca = get_ilong_prefetch(2);
50239: { uae_s8 src = get_byte(srca);
50240: { uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
50241: uae_u16 newv_hi = - (src & 0xF0);
50242: uae_u16 newv;
50243: int cflg;
50244: if (newv_lo > 9) { newv_lo -= 6; }
50245: newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90;
50246: if (cflg) newv -= 0x60;
50247: SET_CFLG (cflg);
50248: COPY_CARRY;
50249: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
50250: SET_NFLG (((uae_s8)(newv)) < 0);
50251: m68k_incpc(6);
50252: fill_prefetch_0 ();
50253: put_byte(srca,newv);
50254: }}}}return 20;
50255: }
50256: unsigned long REGPARAM2 CPUFUNC(op_4840_5)(uae_u32 opcode) /* SWAP */
50257: {
50258: uae_u32 srcreg = (opcode & 7);
50259: OpcodeFamily = 34; CurrentInstrCycles = 4;
50260: {{ uae_s32 src = m68k_dreg(regs, srcreg);
50261: { uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
50262: CLEAR_CZNV;
50263: SET_ZFLG (((uae_s32)(dst)) == 0);
50264: SET_NFLG (((uae_s32)(dst)) < 0);
50265: m68k_dreg(regs, srcreg) = (dst);
50266: }}}m68k_incpc(2);
50267: fill_prefetch_2 ();
50268: return 4;
50269: }
50270: unsigned long REGPARAM2 CPUFUNC(op_4850_5)(uae_u32 opcode) /* PEA */
50271: {
50272: uae_u32 srcreg = (opcode & 7);
50273: OpcodeFamily = 57; CurrentInstrCycles = 12;
50274: {{ uaecptr srca = m68k_areg(regs, srcreg);
50275: { uaecptr dsta = m68k_areg(regs, 7) - 4;
50276: if ((dsta & 1) != 0) {
50277: last_fault_for_exception_3 = dsta;
50278: last_op_for_exception_3 = opcode;
50279: last_addr_for_exception_3 = m68k_getpc() + 2;
50280: Exception(3, 0, M68000_EXC_SRC_CPU);
50281: goto endlabel2862;
50282: }
50283: { m68k_areg (regs, 7) = dsta;
50284: m68k_incpc(2);
50285: fill_prefetch_2 ();
50286: put_long(dsta,srca);
50287: }}}}endlabel2862: ;
50288: return 12;
50289: }
50290: unsigned long REGPARAM2 CPUFUNC(op_4868_5)(uae_u32 opcode) /* PEA */
50291: {
50292: uae_u32 srcreg = (opcode & 7);
50293: OpcodeFamily = 57; CurrentInstrCycles = 16;
50294: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
50295: { uaecptr dsta = m68k_areg(regs, 7) - 4;
50296: if ((dsta & 1) != 0) {
50297: last_fault_for_exception_3 = dsta;
50298: last_op_for_exception_3 = opcode;
50299: last_addr_for_exception_3 = m68k_getpc() + 4;
50300: Exception(3, 0, M68000_EXC_SRC_CPU);
50301: goto endlabel2863;
50302: }
50303: { m68k_areg (regs, 7) = dsta;
50304: m68k_incpc(4);
50305: fill_prefetch_0 ();
50306: put_long(dsta,srca);
50307: }}}}endlabel2863: ;
50308: return 16;
50309: }
50310: unsigned long REGPARAM2 CPUFUNC(op_4870_5)(uae_u32 opcode) /* PEA */
50311: {
50312: uae_u32 srcreg = (opcode & 7);
50313: OpcodeFamily = 57; CurrentInstrCycles = 22;
50314: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
50315: BusCyclePenalty += 2;
50316: { uaecptr dsta = m68k_areg(regs, 7) - 4;
50317: if ((dsta & 1) != 0) {
50318: last_fault_for_exception_3 = dsta;
50319: last_op_for_exception_3 = opcode;
50320: last_addr_for_exception_3 = m68k_getpc() + 4;
50321: Exception(3, 0, M68000_EXC_SRC_CPU);
50322: goto endlabel2864;
50323: }
50324: { m68k_areg (regs, 7) = dsta;
50325: m68k_incpc(4);
50326: fill_prefetch_0 ();
50327: put_long(dsta,srca);
50328: }}}}endlabel2864: ;
50329: return 22;
50330: }
50331: unsigned long REGPARAM2 CPUFUNC(op_4878_5)(uae_u32 opcode) /* PEA */
50332: {
50333: OpcodeFamily = 57; CurrentInstrCycles = 16;
50334: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
50335: { uaecptr dsta = m68k_areg(regs, 7) - 4;
50336: if ((dsta & 1) != 0) {
50337: last_fault_for_exception_3 = dsta;
50338: last_op_for_exception_3 = opcode;
50339: last_addr_for_exception_3 = m68k_getpc() + 4;
50340: Exception(3, 0, M68000_EXC_SRC_CPU);
50341: goto endlabel2865;
50342: }
50343: { m68k_areg (regs, 7) = dsta;
50344: m68k_incpc(4);
50345: fill_prefetch_0 ();
50346: put_long(dsta,srca);
50347: }}}}endlabel2865: ;
50348: return 16;
50349: }
50350: unsigned long REGPARAM2 CPUFUNC(op_4879_5)(uae_u32 opcode) /* PEA */
50351: {
50352: OpcodeFamily = 57; CurrentInstrCycles = 20;
50353: {{ uaecptr srca = get_ilong_prefetch(2);
50354: { uaecptr dsta = m68k_areg(regs, 7) - 4;
50355: if ((dsta & 1) != 0) {
50356: last_fault_for_exception_3 = dsta;
50357: last_op_for_exception_3 = opcode;
50358: last_addr_for_exception_3 = m68k_getpc() + 6;
50359: Exception(3, 0, M68000_EXC_SRC_CPU);
50360: goto endlabel2866;
50361: }
50362: { m68k_areg (regs, 7) = dsta;
50363: m68k_incpc(6);
50364: fill_prefetch_0 ();
50365: put_long(dsta,srca);
50366: }}}}endlabel2866: ;
50367: return 20;
50368: }
50369: unsigned long REGPARAM2 CPUFUNC(op_487a_5)(uae_u32 opcode) /* PEA */
50370: {
50371: OpcodeFamily = 57; CurrentInstrCycles = 16;
50372: {{ uaecptr srca = m68k_getpc () + 2;
50373: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
50374: { uaecptr dsta = m68k_areg(regs, 7) - 4;
50375: if ((dsta & 1) != 0) {
50376: last_fault_for_exception_3 = dsta;
50377: last_op_for_exception_3 = opcode;
50378: last_addr_for_exception_3 = m68k_getpc() + 4;
50379: Exception(3, 0, M68000_EXC_SRC_CPU);
50380: goto endlabel2867;
50381: }
50382: { m68k_areg (regs, 7) = dsta;
50383: m68k_incpc(4);
50384: fill_prefetch_0 ();
50385: put_long(dsta,srca);
50386: }}}}endlabel2867: ;
50387: return 16;
50388: }
50389: unsigned long REGPARAM2 CPUFUNC(op_487b_5)(uae_u32 opcode) /* PEA */
50390: {
50391: OpcodeFamily = 57; CurrentInstrCycles = 22;
50392: {{ uaecptr tmppc = m68k_getpc() + 2;
50393: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
50394: BusCyclePenalty += 2;
50395: { uaecptr dsta = m68k_areg(regs, 7) - 4;
50396: if ((dsta & 1) != 0) {
50397: last_fault_for_exception_3 = dsta;
50398: last_op_for_exception_3 = opcode;
50399: last_addr_for_exception_3 = m68k_getpc() + 4;
50400: Exception(3, 0, M68000_EXC_SRC_CPU);
50401: goto endlabel2868;
50402: }
50403: { m68k_areg (regs, 7) = dsta;
50404: m68k_incpc(4);
50405: fill_prefetch_0 ();
50406: put_long(dsta,srca);
50407: }}}}endlabel2868: ;
50408: return 22;
50409: }
50410: unsigned long REGPARAM2 CPUFUNC(op_4880_5)(uae_u32 opcode) /* EXT */
50411: {
50412: uae_u32 srcreg = (opcode & 7);
50413: OpcodeFamily = 36; CurrentInstrCycles = 4;
50414: {{ uae_s32 src = m68k_dreg(regs, srcreg);
50415: { uae_u16 dst = (uae_s16)(uae_s8)src;
50416: CLEAR_CZNV;
50417: SET_ZFLG (((uae_s16)(dst)) == 0);
50418: SET_NFLG (((uae_s16)(dst)) < 0);
50419: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
50420: }}}m68k_incpc(2);
50421: fill_prefetch_2 ();
50422: return 4;
50423: }
50424: unsigned long REGPARAM2 CPUFUNC(op_4890_5)(uae_u32 opcode) /* MVMLE */
50425: {
50426: uae_u32 dstreg = opcode & 7;
50427: unsigned int retcycles = 0;
50428: OpcodeFamily = 38; CurrentInstrCycles = 8;
50429: { uae_u16 mask = get_iword_prefetch(2);
50430: retcycles = 0;
50431: { uaecptr srca = m68k_areg(regs, dstreg);
50432: if ((srca & 1) != 0) {
50433: last_fault_for_exception_3 = srca;
50434: last_op_for_exception_3 = opcode;
50435: last_addr_for_exception_3 = m68k_getpc() + 4;
50436: Exception(3, 0, M68000_EXC_SRC_CPU);
50437: goto endlabel2870;
50438: }
50439: {m68k_incpc(4);
50440: fill_prefetch_0 ();
50441: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50442: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
50443: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
50444: }}}}endlabel2870: ;
50445: return (8+retcycles);
50446: }
50447: unsigned long REGPARAM2 CPUFUNC(op_48a0_5)(uae_u32 opcode) /* MVMLE */
50448: {
50449: uae_u32 dstreg = opcode & 7;
50450: unsigned int retcycles = 0;
50451: OpcodeFamily = 38; CurrentInstrCycles = 8;
50452: { uae_u16 mask = get_iword_prefetch(2);
50453: retcycles = 0;
50454: { uaecptr srca = m68k_areg(regs, dstreg) - 0;
50455: if ((srca & 1) != 0) {
50456: last_fault_for_exception_3 = srca;
50457: last_op_for_exception_3 = opcode;
50458: last_addr_for_exception_3 = m68k_getpc() + 4;
50459: Exception(3, 0, M68000_EXC_SRC_CPU);
50460: goto endlabel2871;
50461: }
50462: {m68k_incpc(4);
50463: fill_prefetch_0 ();
50464: { uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
50465: while (amask) { srca -= 2; put_word(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=4; }
50466: while (dmask) { srca -= 2; put_word(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=4; }
50467: m68k_areg(regs, dstreg) = srca;
50468: }}}}endlabel2871: ;
50469: return (8+retcycles);
50470: }
50471: unsigned long REGPARAM2 CPUFUNC(op_48a8_5)(uae_u32 opcode) /* MVMLE */
50472: {
50473: uae_u32 dstreg = opcode & 7;
50474: unsigned int retcycles = 0;
50475: OpcodeFamily = 38; CurrentInstrCycles = 12;
50476: { uae_u16 mask = get_iword_prefetch(2);
50477: retcycles = 0;
50478: { uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
50479: if ((srca & 1) != 0) {
50480: last_fault_for_exception_3 = srca;
50481: last_op_for_exception_3 = opcode;
50482: last_addr_for_exception_3 = m68k_getpc() + 6;
50483: Exception(3, 0, M68000_EXC_SRC_CPU);
50484: goto endlabel2872;
50485: }
50486: {m68k_incpc(6);
50487: fill_prefetch_0 ();
50488: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50489: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
50490: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
50491: }}}}endlabel2872: ;
50492: return (12+retcycles);
50493: }
50494: unsigned long REGPARAM2 CPUFUNC(op_48b0_5)(uae_u32 opcode) /* MVMLE */
50495: {
50496: uae_u32 dstreg = opcode & 7;
50497: unsigned int retcycles = 0;
50498: OpcodeFamily = 38; CurrentInstrCycles = 14;
50499: { uae_u16 mask = get_iword_prefetch(2);
50500: retcycles = 0;
50501: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
50502: BusCyclePenalty += 2;
50503: if ((srca & 1) != 0) {
50504: last_fault_for_exception_3 = srca;
50505: last_op_for_exception_3 = opcode;
50506: last_addr_for_exception_3 = m68k_getpc() + 6;
50507: Exception(3, 0, M68000_EXC_SRC_CPU);
50508: goto endlabel2873;
50509: }
50510: {m68k_incpc(6);
50511: fill_prefetch_0 ();
50512: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50513: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
50514: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
50515: }}}}endlabel2873: ;
50516: return (14+retcycles);
50517: }
50518: unsigned long REGPARAM2 CPUFUNC(op_48b8_5)(uae_u32 opcode) /* MVMLE */
50519: {
50520: unsigned int retcycles = 0;
50521: OpcodeFamily = 38; CurrentInstrCycles = 12;
50522: { uae_u16 mask = get_iword_prefetch(2);
50523: retcycles = 0;
50524: { uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(4);
50525: if ((srca & 1) != 0) {
50526: last_fault_for_exception_3 = srca;
50527: last_op_for_exception_3 = opcode;
50528: last_addr_for_exception_3 = m68k_getpc() + 6;
50529: Exception(3, 0, M68000_EXC_SRC_CPU);
50530: goto endlabel2874;
50531: }
50532: {m68k_incpc(6);
50533: fill_prefetch_0 ();
50534: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50535: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
50536: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
50537: }}}}endlabel2874: ;
50538: return (12+retcycles);
50539: }
50540: unsigned long REGPARAM2 CPUFUNC(op_48b9_5)(uae_u32 opcode) /* MVMLE */
50541: {
50542: unsigned int retcycles = 0;
50543: OpcodeFamily = 38; CurrentInstrCycles = 16;
50544: { uae_u16 mask = get_iword_prefetch(2);
50545: retcycles = 0;
50546: { uaecptr srca = get_ilong_prefetch(4);
50547: if ((srca & 1) != 0) {
50548: last_fault_for_exception_3 = srca;
50549: last_op_for_exception_3 = opcode;
50550: last_addr_for_exception_3 = m68k_getpc() + 8;
50551: Exception(3, 0, M68000_EXC_SRC_CPU);
50552: goto endlabel2875;
50553: }
50554: {m68k_incpc(8);
50555: fill_prefetch_0 ();
50556: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50557: while (dmask) { put_word(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
50558: while (amask) { put_word(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
50559: }}}}endlabel2875: ;
50560: return (16+retcycles);
50561: }
50562: unsigned long REGPARAM2 CPUFUNC(op_48c0_5)(uae_u32 opcode) /* EXT */
50563: {
50564: uae_u32 srcreg = (opcode & 7);
50565: OpcodeFamily = 36; CurrentInstrCycles = 4;
50566: {{ uae_s32 src = m68k_dreg(regs, srcreg);
50567: { uae_u32 dst = (uae_s32)(uae_s16)src;
50568: CLEAR_CZNV;
50569: SET_ZFLG (((uae_s32)(dst)) == 0);
50570: SET_NFLG (((uae_s32)(dst)) < 0);
50571: m68k_dreg(regs, srcreg) = (dst);
50572: }}}m68k_incpc(2);
50573: fill_prefetch_2 ();
50574: return 4;
50575: }
50576: unsigned long REGPARAM2 CPUFUNC(op_48d0_5)(uae_u32 opcode) /* MVMLE */
50577: {
50578: uae_u32 dstreg = opcode & 7;
50579: unsigned int retcycles = 0;
50580: OpcodeFamily = 38; CurrentInstrCycles = 8;
50581: { uae_u16 mask = get_iword_prefetch(2);
50582: retcycles = 0;
50583: { uaecptr srca = m68k_areg(regs, dstreg);
50584: if ((srca & 1) != 0) {
50585: last_fault_for_exception_3 = srca;
50586: last_op_for_exception_3 = opcode;
50587: last_addr_for_exception_3 = m68k_getpc() + 4;
50588: Exception(3, 0, M68000_EXC_SRC_CPU);
50589: goto endlabel2877;
50590: }
50591: {m68k_incpc(4);
50592: fill_prefetch_0 ();
50593: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50594: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
50595: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
50596: }}}}endlabel2877: ;
50597: return (8+retcycles);
50598: }
50599: unsigned long REGPARAM2 CPUFUNC(op_48e0_5)(uae_u32 opcode) /* MVMLE */
50600: {
50601: uae_u32 dstreg = opcode & 7;
50602: unsigned int retcycles = 0;
50603: OpcodeFamily = 38; CurrentInstrCycles = 8;
50604: { uae_u16 mask = get_iword_prefetch(2);
50605: retcycles = 0;
50606: { uaecptr srca = m68k_areg(regs, dstreg) - 0;
50607: if ((srca & 1) != 0) {
50608: last_fault_for_exception_3 = srca;
50609: last_op_for_exception_3 = opcode;
50610: last_addr_for_exception_3 = m68k_getpc() + 4;
50611: Exception(3, 0, M68000_EXC_SRC_CPU);
50612: goto endlabel2878;
50613: }
50614: {m68k_incpc(4);
50615: fill_prefetch_0 ();
50616: { uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
50617: while (amask) { srca -= 4; put_long(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=8; }
50618: while (dmask) { srca -= 4; put_long(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=8; }
50619: m68k_areg(regs, dstreg) = srca;
50620: }}}}endlabel2878: ;
50621: return (8+retcycles);
50622: }
50623: unsigned long REGPARAM2 CPUFUNC(op_48e8_5)(uae_u32 opcode) /* MVMLE */
50624: {
50625: uae_u32 dstreg = opcode & 7;
50626: unsigned int retcycles = 0;
50627: OpcodeFamily = 38; CurrentInstrCycles = 12;
50628: { uae_u16 mask = get_iword_prefetch(2);
50629: retcycles = 0;
50630: { uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
50631: if ((srca & 1) != 0) {
50632: last_fault_for_exception_3 = srca;
50633: last_op_for_exception_3 = opcode;
50634: last_addr_for_exception_3 = m68k_getpc() + 6;
50635: Exception(3, 0, M68000_EXC_SRC_CPU);
50636: goto endlabel2879;
50637: }
50638: {m68k_incpc(6);
50639: fill_prefetch_0 ();
50640: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50641: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
50642: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
50643: }}}}endlabel2879: ;
50644: return (12+retcycles);
50645: }
50646: unsigned long REGPARAM2 CPUFUNC(op_48f0_5)(uae_u32 opcode) /* MVMLE */
50647: {
50648: uae_u32 dstreg = opcode & 7;
50649: unsigned int retcycles = 0;
50650: OpcodeFamily = 38; CurrentInstrCycles = 14;
50651: { uae_u16 mask = get_iword_prefetch(2);
50652: retcycles = 0;
50653: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
50654: BusCyclePenalty += 2;
50655: if ((srca & 1) != 0) {
50656: last_fault_for_exception_3 = srca;
50657: last_op_for_exception_3 = opcode;
50658: last_addr_for_exception_3 = m68k_getpc() + 6;
50659: Exception(3, 0, M68000_EXC_SRC_CPU);
50660: goto endlabel2880;
50661: }
50662: {m68k_incpc(6);
50663: fill_prefetch_0 ();
50664: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50665: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
50666: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
50667: }}}}endlabel2880: ;
50668: return (14+retcycles);
50669: }
50670: unsigned long REGPARAM2 CPUFUNC(op_48f8_5)(uae_u32 opcode) /* MVMLE */
50671: {
50672: unsigned int retcycles = 0;
50673: OpcodeFamily = 38; CurrentInstrCycles = 12;
50674: { uae_u16 mask = get_iword_prefetch(2);
50675: retcycles = 0;
50676: { uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(4);
50677: if ((srca & 1) != 0) {
50678: last_fault_for_exception_3 = srca;
50679: last_op_for_exception_3 = opcode;
50680: last_addr_for_exception_3 = m68k_getpc() + 6;
50681: Exception(3, 0, M68000_EXC_SRC_CPU);
50682: goto endlabel2881;
50683: }
50684: {m68k_incpc(6);
50685: fill_prefetch_0 ();
50686: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50687: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
50688: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
50689: }}}}endlabel2881: ;
50690: return (12+retcycles);
50691: }
50692: unsigned long REGPARAM2 CPUFUNC(op_48f9_5)(uae_u32 opcode) /* MVMLE */
50693: {
50694: unsigned int retcycles = 0;
50695: OpcodeFamily = 38; CurrentInstrCycles = 16;
50696: { uae_u16 mask = get_iword_prefetch(2);
50697: retcycles = 0;
50698: { uaecptr srca = get_ilong_prefetch(4);
50699: if ((srca & 1) != 0) {
50700: last_fault_for_exception_3 = srca;
50701: last_op_for_exception_3 = opcode;
50702: last_addr_for_exception_3 = m68k_getpc() + 8;
50703: Exception(3, 0, M68000_EXC_SRC_CPU);
50704: goto endlabel2882;
50705: }
50706: {m68k_incpc(8);
50707: fill_prefetch_0 ();
50708: { uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
50709: while (dmask) { put_long(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
50710: while (amask) { put_long(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
50711: }}}}endlabel2882: ;
50712: return (16+retcycles);
50713: }
50714: unsigned long REGPARAM2 CPUFUNC(op_4a00_5)(uae_u32 opcode) /* TST */
50715: {
50716: uae_u32 srcreg = (opcode & 7);
50717: OpcodeFamily = 20; CurrentInstrCycles = 4;
50718: {{ uae_s8 src = m68k_dreg(regs, srcreg);
50719: CLEAR_CZNV;
50720: SET_ZFLG (((uae_s8)(src)) == 0);
50721: SET_NFLG (((uae_s8)(src)) < 0);
50722: }}m68k_incpc(2);
50723: fill_prefetch_2 ();
50724: return 4;
50725: }
50726: unsigned long REGPARAM2 CPUFUNC(op_4a10_5)(uae_u32 opcode) /* TST */
50727: {
50728: uae_u32 srcreg = (opcode & 7);
50729: OpcodeFamily = 20; CurrentInstrCycles = 8;
50730: {{ uaecptr srca = m68k_areg(regs, srcreg);
50731: { uae_s8 src = get_byte(srca);
50732: CLEAR_CZNV;
50733: SET_ZFLG (((uae_s8)(src)) == 0);
50734: SET_NFLG (((uae_s8)(src)) < 0);
50735: }}}m68k_incpc(2);
50736: fill_prefetch_2 ();
50737: return 8;
50738: }
50739: unsigned long REGPARAM2 CPUFUNC(op_4a18_5)(uae_u32 opcode) /* TST */
50740: {
50741: uae_u32 srcreg = (opcode & 7);
50742: OpcodeFamily = 20; CurrentInstrCycles = 8;
50743: {{ uaecptr srca = m68k_areg(regs, srcreg);
50744: { uae_s8 src = get_byte(srca);
50745: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
50746: CLEAR_CZNV;
50747: SET_ZFLG (((uae_s8)(src)) == 0);
50748: SET_NFLG (((uae_s8)(src)) < 0);
50749: }}}m68k_incpc(2);
50750: fill_prefetch_2 ();
50751: return 8;
50752: }
50753: unsigned long REGPARAM2 CPUFUNC(op_4a20_5)(uae_u32 opcode) /* TST */
50754: {
50755: uae_u32 srcreg = (opcode & 7);
50756: OpcodeFamily = 20; CurrentInstrCycles = 10;
50757: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
50758: { uae_s8 src = get_byte(srca);
50759: m68k_areg (regs, srcreg) = srca;
50760: CLEAR_CZNV;
50761: SET_ZFLG (((uae_s8)(src)) == 0);
50762: SET_NFLG (((uae_s8)(src)) < 0);
50763: }}}m68k_incpc(2);
50764: fill_prefetch_2 ();
50765: return 10;
50766: }
50767: unsigned long REGPARAM2 CPUFUNC(op_4a28_5)(uae_u32 opcode) /* TST */
50768: {
50769: uae_u32 srcreg = (opcode & 7);
50770: OpcodeFamily = 20; CurrentInstrCycles = 12;
50771: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
50772: { uae_s8 src = get_byte(srca);
50773: CLEAR_CZNV;
50774: SET_ZFLG (((uae_s8)(src)) == 0);
50775: SET_NFLG (((uae_s8)(src)) < 0);
50776: }}}m68k_incpc(4);
50777: fill_prefetch_0 ();
50778: return 12;
50779: }
50780: unsigned long REGPARAM2 CPUFUNC(op_4a30_5)(uae_u32 opcode) /* TST */
50781: {
50782: uae_u32 srcreg = (opcode & 7);
50783: OpcodeFamily = 20; CurrentInstrCycles = 14;
50784: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
50785: BusCyclePenalty += 2;
50786: { uae_s8 src = get_byte(srca);
50787: CLEAR_CZNV;
50788: SET_ZFLG (((uae_s8)(src)) == 0);
50789: SET_NFLG (((uae_s8)(src)) < 0);
50790: }}}m68k_incpc(4);
50791: fill_prefetch_0 ();
50792: return 14;
50793: }
50794: unsigned long REGPARAM2 CPUFUNC(op_4a38_5)(uae_u32 opcode) /* TST */
50795: {
50796: OpcodeFamily = 20; CurrentInstrCycles = 12;
50797: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
50798: { uae_s8 src = get_byte(srca);
50799: CLEAR_CZNV;
50800: SET_ZFLG (((uae_s8)(src)) == 0);
50801: SET_NFLG (((uae_s8)(src)) < 0);
50802: }}}m68k_incpc(4);
50803: fill_prefetch_0 ();
50804: return 12;
50805: }
50806: unsigned long REGPARAM2 CPUFUNC(op_4a39_5)(uae_u32 opcode) /* TST */
50807: {
50808: OpcodeFamily = 20; CurrentInstrCycles = 16;
50809: {{ uaecptr srca = get_ilong_prefetch(2);
50810: { uae_s8 src = get_byte(srca);
50811: CLEAR_CZNV;
50812: SET_ZFLG (((uae_s8)(src)) == 0);
50813: SET_NFLG (((uae_s8)(src)) < 0);
50814: }}}m68k_incpc(6);
50815: fill_prefetch_0 ();
50816: return 16;
50817: }
50818: unsigned long REGPARAM2 CPUFUNC(op_4a3a_5)(uae_u32 opcode) /* TST */
50819: {
50820: OpcodeFamily = 20; CurrentInstrCycles = 12;
50821: {{ uaecptr srca = m68k_getpc () + 2;
50822: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
50823: { uae_s8 src = get_byte(srca);
50824: CLEAR_CZNV;
50825: SET_ZFLG (((uae_s8)(src)) == 0);
50826: SET_NFLG (((uae_s8)(src)) < 0);
50827: }}}m68k_incpc(4);
50828: fill_prefetch_0 ();
50829: return 12;
50830: }
50831: unsigned long REGPARAM2 CPUFUNC(op_4a3b_5)(uae_u32 opcode) /* TST */
50832: {
50833: OpcodeFamily = 20; CurrentInstrCycles = 14;
50834: {{ uaecptr tmppc = m68k_getpc() + 2;
50835: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
50836: BusCyclePenalty += 2;
50837: { uae_s8 src = get_byte(srca);
50838: CLEAR_CZNV;
50839: SET_ZFLG (((uae_s8)(src)) == 0);
50840: SET_NFLG (((uae_s8)(src)) < 0);
50841: }}}m68k_incpc(4);
50842: fill_prefetch_0 ();
50843: return 14;
50844: }
50845: unsigned long REGPARAM2 CPUFUNC(op_4a3c_5)(uae_u32 opcode) /* TST */
50846: {
50847: OpcodeFamily = 20; CurrentInstrCycles = 8;
50848: {{ uae_s8 src = get_ibyte_prefetch(2);
50849: CLEAR_CZNV;
50850: SET_ZFLG (((uae_s8)(src)) == 0);
50851: SET_NFLG (((uae_s8)(src)) < 0);
50852: }}m68k_incpc(4);
50853: fill_prefetch_0 ();
50854: return 8;
50855: }
50856: unsigned long REGPARAM2 CPUFUNC(op_4a40_5)(uae_u32 opcode) /* TST */
50857: {
50858: uae_u32 srcreg = (opcode & 7);
50859: OpcodeFamily = 20; CurrentInstrCycles = 4;
50860: {{ uae_s16 src = m68k_dreg(regs, srcreg);
50861: CLEAR_CZNV;
50862: SET_ZFLG (((uae_s16)(src)) == 0);
50863: SET_NFLG (((uae_s16)(src)) < 0);
50864: }}m68k_incpc(2);
50865: fill_prefetch_2 ();
50866: return 4;
50867: }
50868: unsigned long REGPARAM2 CPUFUNC(op_4a48_5)(uae_u32 opcode) /* TST */
50869: {
50870: uae_u32 srcreg = (opcode & 7);
50871: OpcodeFamily = 20; CurrentInstrCycles = 4;
50872: {{ uae_s16 src = m68k_areg(regs, srcreg);
50873: CLEAR_CZNV;
50874: SET_ZFLG (((uae_s16)(src)) == 0);
50875: SET_NFLG (((uae_s16)(src)) < 0);
50876: }}m68k_incpc(2);
50877: fill_prefetch_2 ();
50878: return 4;
50879: }
50880: unsigned long REGPARAM2 CPUFUNC(op_4a50_5)(uae_u32 opcode) /* TST */
50881: {
50882: uae_u32 srcreg = (opcode & 7);
50883: OpcodeFamily = 20; CurrentInstrCycles = 8;
50884: {{ uaecptr srca = m68k_areg(regs, srcreg);
50885: if ((srca & 1) != 0) {
50886: last_fault_for_exception_3 = srca;
50887: last_op_for_exception_3 = opcode;
50888: last_addr_for_exception_3 = m68k_getpc() + 2;
50889: Exception(3, 0, M68000_EXC_SRC_CPU);
50890: goto endlabel2896;
50891: }
50892: {{ uae_s16 src = get_word(srca);
50893: CLEAR_CZNV;
50894: SET_ZFLG (((uae_s16)(src)) == 0);
50895: SET_NFLG (((uae_s16)(src)) < 0);
50896: }}}}m68k_incpc(2);
50897: fill_prefetch_2 ();
50898: endlabel2896: ;
50899: return 8;
50900: }
50901: unsigned long REGPARAM2 CPUFUNC(op_4a58_5)(uae_u32 opcode) /* TST */
50902: {
50903: uae_u32 srcreg = (opcode & 7);
50904: OpcodeFamily = 20; CurrentInstrCycles = 8;
50905: {{ uaecptr srca = m68k_areg(regs, srcreg);
50906: if ((srca & 1) != 0) {
50907: last_fault_for_exception_3 = srca;
50908: last_op_for_exception_3 = opcode;
50909: last_addr_for_exception_3 = m68k_getpc() + 2;
50910: Exception(3, 0, M68000_EXC_SRC_CPU);
50911: goto endlabel2897;
50912: }
50913: {{ uae_s16 src = get_word(srca);
50914: m68k_areg(regs, srcreg) += 2;
50915: CLEAR_CZNV;
50916: SET_ZFLG (((uae_s16)(src)) == 0);
50917: SET_NFLG (((uae_s16)(src)) < 0);
50918: }}}}m68k_incpc(2);
50919: fill_prefetch_2 ();
50920: endlabel2897: ;
50921: return 8;
50922: }
50923: unsigned long REGPARAM2 CPUFUNC(op_4a60_5)(uae_u32 opcode) /* TST */
50924: {
50925: uae_u32 srcreg = (opcode & 7);
50926: OpcodeFamily = 20; CurrentInstrCycles = 10;
50927: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
50928: if ((srca & 1) != 0) {
50929: last_fault_for_exception_3 = srca;
50930: last_op_for_exception_3 = opcode;
50931: last_addr_for_exception_3 = m68k_getpc() + 2;
50932: Exception(3, 0, M68000_EXC_SRC_CPU);
50933: goto endlabel2898;
50934: }
50935: {{ uae_s16 src = get_word(srca);
50936: m68k_areg (regs, srcreg) = srca;
50937: CLEAR_CZNV;
50938: SET_ZFLG (((uae_s16)(src)) == 0);
50939: SET_NFLG (((uae_s16)(src)) < 0);
50940: }}}}m68k_incpc(2);
50941: fill_prefetch_2 ();
50942: endlabel2898: ;
50943: return 10;
50944: }
50945: unsigned long REGPARAM2 CPUFUNC(op_4a68_5)(uae_u32 opcode) /* TST */
50946: {
50947: uae_u32 srcreg = (opcode & 7);
50948: OpcodeFamily = 20; CurrentInstrCycles = 12;
50949: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
50950: if ((srca & 1) != 0) {
50951: last_fault_for_exception_3 = srca;
50952: last_op_for_exception_3 = opcode;
50953: last_addr_for_exception_3 = m68k_getpc() + 4;
50954: Exception(3, 0, M68000_EXC_SRC_CPU);
50955: goto endlabel2899;
50956: }
50957: {{ uae_s16 src = get_word(srca);
50958: CLEAR_CZNV;
50959: SET_ZFLG (((uae_s16)(src)) == 0);
50960: SET_NFLG (((uae_s16)(src)) < 0);
50961: }}}}m68k_incpc(4);
50962: fill_prefetch_0 ();
50963: endlabel2899: ;
50964: return 12;
50965: }
50966: unsigned long REGPARAM2 CPUFUNC(op_4a70_5)(uae_u32 opcode) /* TST */
50967: {
50968: uae_u32 srcreg = (opcode & 7);
50969: OpcodeFamily = 20; CurrentInstrCycles = 14;
50970: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
50971: BusCyclePenalty += 2;
50972: if ((srca & 1) != 0) {
50973: last_fault_for_exception_3 = srca;
50974: last_op_for_exception_3 = opcode;
50975: last_addr_for_exception_3 = m68k_getpc() + 4;
50976: Exception(3, 0, M68000_EXC_SRC_CPU);
50977: goto endlabel2900;
50978: }
50979: {{ uae_s16 src = get_word(srca);
50980: CLEAR_CZNV;
50981: SET_ZFLG (((uae_s16)(src)) == 0);
50982: SET_NFLG (((uae_s16)(src)) < 0);
50983: }}}}m68k_incpc(4);
50984: fill_prefetch_0 ();
50985: endlabel2900: ;
50986: return 14;
50987: }
50988: unsigned long REGPARAM2 CPUFUNC(op_4a78_5)(uae_u32 opcode) /* TST */
50989: {
50990: OpcodeFamily = 20; CurrentInstrCycles = 12;
50991: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
50992: if ((srca & 1) != 0) {
50993: last_fault_for_exception_3 = srca;
50994: last_op_for_exception_3 = opcode;
50995: last_addr_for_exception_3 = m68k_getpc() + 4;
50996: Exception(3, 0, M68000_EXC_SRC_CPU);
50997: goto endlabel2901;
50998: }
50999: {{ uae_s16 src = get_word(srca);
51000: CLEAR_CZNV;
51001: SET_ZFLG (((uae_s16)(src)) == 0);
51002: SET_NFLG (((uae_s16)(src)) < 0);
51003: }}}}m68k_incpc(4);
51004: fill_prefetch_0 ();
51005: endlabel2901: ;
51006: return 12;
51007: }
51008: unsigned long REGPARAM2 CPUFUNC(op_4a79_5)(uae_u32 opcode) /* TST */
51009: {
51010: OpcodeFamily = 20; CurrentInstrCycles = 16;
51011: {{ uaecptr srca = get_ilong_prefetch(2);
51012: if ((srca & 1) != 0) {
51013: last_fault_for_exception_3 = srca;
51014: last_op_for_exception_3 = opcode;
51015: last_addr_for_exception_3 = m68k_getpc() + 6;
51016: Exception(3, 0, M68000_EXC_SRC_CPU);
51017: goto endlabel2902;
51018: }
51019: {{ uae_s16 src = get_word(srca);
51020: CLEAR_CZNV;
51021: SET_ZFLG (((uae_s16)(src)) == 0);
51022: SET_NFLG (((uae_s16)(src)) < 0);
51023: }}}}m68k_incpc(6);
51024: fill_prefetch_0 ();
51025: endlabel2902: ;
51026: return 16;
51027: }
51028: unsigned long REGPARAM2 CPUFUNC(op_4a7a_5)(uae_u32 opcode) /* TST */
51029: {
51030: OpcodeFamily = 20; CurrentInstrCycles = 12;
51031: {{ uaecptr srca = m68k_getpc () + 2;
51032: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
51033: if ((srca & 1) != 0) {
51034: last_fault_for_exception_3 = srca;
51035: last_op_for_exception_3 = opcode;
51036: last_addr_for_exception_3 = m68k_getpc() + 4;
51037: Exception(3, 0, M68000_EXC_SRC_CPU);
51038: goto endlabel2903;
51039: }
51040: {{ uae_s16 src = get_word(srca);
51041: CLEAR_CZNV;
51042: SET_ZFLG (((uae_s16)(src)) == 0);
51043: SET_NFLG (((uae_s16)(src)) < 0);
51044: }}}}m68k_incpc(4);
51045: fill_prefetch_0 ();
51046: endlabel2903: ;
51047: return 12;
51048: }
51049: unsigned long REGPARAM2 CPUFUNC(op_4a7b_5)(uae_u32 opcode) /* TST */
51050: {
51051: OpcodeFamily = 20; CurrentInstrCycles = 14;
51052: {{ uaecptr tmppc = m68k_getpc() + 2;
51053: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
51054: BusCyclePenalty += 2;
51055: if ((srca & 1) != 0) {
51056: last_fault_for_exception_3 = srca;
51057: last_op_for_exception_3 = opcode;
51058: last_addr_for_exception_3 = m68k_getpc() + 4;
51059: Exception(3, 0, M68000_EXC_SRC_CPU);
51060: goto endlabel2904;
51061: }
51062: {{ uae_s16 src = get_word(srca);
51063: CLEAR_CZNV;
51064: SET_ZFLG (((uae_s16)(src)) == 0);
51065: SET_NFLG (((uae_s16)(src)) < 0);
51066: }}}}m68k_incpc(4);
51067: fill_prefetch_0 ();
51068: endlabel2904: ;
51069: return 14;
51070: }
51071: unsigned long REGPARAM2 CPUFUNC(op_4a7c_5)(uae_u32 opcode) /* TST */
51072: {
51073: OpcodeFamily = 20; CurrentInstrCycles = 8;
51074: {{ uae_s16 src = get_iword_prefetch(2);
51075: CLEAR_CZNV;
51076: SET_ZFLG (((uae_s16)(src)) == 0);
51077: SET_NFLG (((uae_s16)(src)) < 0);
51078: }}m68k_incpc(4);
51079: fill_prefetch_0 ();
51080: return 8;
51081: }
51082: unsigned long REGPARAM2 CPUFUNC(op_4a80_5)(uae_u32 opcode) /* TST */
51083: {
51084: uae_u32 srcreg = (opcode & 7);
51085: OpcodeFamily = 20; CurrentInstrCycles = 4;
51086: {{ uae_s32 src = m68k_dreg(regs, srcreg);
51087: CLEAR_CZNV;
51088: SET_ZFLG (((uae_s32)(src)) == 0);
51089: SET_NFLG (((uae_s32)(src)) < 0);
51090: }}m68k_incpc(2);
51091: fill_prefetch_2 ();
51092: return 4;
51093: }
51094: unsigned long REGPARAM2 CPUFUNC(op_4a88_5)(uae_u32 opcode) /* TST */
51095: {
51096: uae_u32 srcreg = (opcode & 7);
51097: OpcodeFamily = 20; CurrentInstrCycles = 4;
51098: {{ uae_s32 src = m68k_areg(regs, srcreg);
51099: CLEAR_CZNV;
51100: SET_ZFLG (((uae_s32)(src)) == 0);
51101: SET_NFLG (((uae_s32)(src)) < 0);
51102: }}m68k_incpc(2);
51103: fill_prefetch_2 ();
51104: return 4;
51105: }
51106: unsigned long REGPARAM2 CPUFUNC(op_4a90_5)(uae_u32 opcode) /* TST */
51107: {
51108: uae_u32 srcreg = (opcode & 7);
51109: OpcodeFamily = 20; CurrentInstrCycles = 12;
51110: {{ uaecptr srca = m68k_areg(regs, srcreg);
51111: if ((srca & 1) != 0) {
51112: last_fault_for_exception_3 = srca;
51113: last_op_for_exception_3 = opcode;
51114: last_addr_for_exception_3 = m68k_getpc() + 2;
51115: Exception(3, 0, M68000_EXC_SRC_CPU);
51116: goto endlabel2908;
51117: }
51118: {{ uae_s32 src = get_long(srca);
51119: CLEAR_CZNV;
51120: SET_ZFLG (((uae_s32)(src)) == 0);
51121: SET_NFLG (((uae_s32)(src)) < 0);
51122: }}}}m68k_incpc(2);
51123: fill_prefetch_2 ();
51124: endlabel2908: ;
51125: return 12;
51126: }
51127: unsigned long REGPARAM2 CPUFUNC(op_4a98_5)(uae_u32 opcode) /* TST */
51128: {
51129: uae_u32 srcreg = (opcode & 7);
51130: OpcodeFamily = 20; CurrentInstrCycles = 12;
51131: {{ uaecptr srca = m68k_areg(regs, srcreg);
51132: if ((srca & 1) != 0) {
51133: last_fault_for_exception_3 = srca;
51134: last_op_for_exception_3 = opcode;
51135: last_addr_for_exception_3 = m68k_getpc() + 2;
51136: Exception(3, 0, M68000_EXC_SRC_CPU);
51137: goto endlabel2909;
51138: }
51139: {{ uae_s32 src = get_long(srca);
51140: m68k_areg(regs, srcreg) += 4;
51141: CLEAR_CZNV;
51142: SET_ZFLG (((uae_s32)(src)) == 0);
51143: SET_NFLG (((uae_s32)(src)) < 0);
51144: }}}}m68k_incpc(2);
51145: fill_prefetch_2 ();
51146: endlabel2909: ;
51147: return 12;
51148: }
51149: unsigned long REGPARAM2 CPUFUNC(op_4aa0_5)(uae_u32 opcode) /* TST */
51150: {
51151: uae_u32 srcreg = (opcode & 7);
51152: OpcodeFamily = 20; CurrentInstrCycles = 14;
51153: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
51154: if ((srca & 1) != 0) {
51155: last_fault_for_exception_3 = srca;
51156: last_op_for_exception_3 = opcode;
51157: last_addr_for_exception_3 = m68k_getpc() + 2;
51158: Exception(3, 0, M68000_EXC_SRC_CPU);
51159: goto endlabel2910;
51160: }
51161: {{ uae_s32 src = get_long(srca);
51162: m68k_areg (regs, srcreg) = srca;
51163: CLEAR_CZNV;
51164: SET_ZFLG (((uae_s32)(src)) == 0);
51165: SET_NFLG (((uae_s32)(src)) < 0);
51166: }}}}m68k_incpc(2);
51167: fill_prefetch_2 ();
51168: endlabel2910: ;
51169: return 14;
51170: }
51171: unsigned long REGPARAM2 CPUFUNC(op_4aa8_5)(uae_u32 opcode) /* TST */
51172: {
51173: uae_u32 srcreg = (opcode & 7);
51174: OpcodeFamily = 20; CurrentInstrCycles = 16;
51175: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
51176: if ((srca & 1) != 0) {
51177: last_fault_for_exception_3 = srca;
51178: last_op_for_exception_3 = opcode;
51179: last_addr_for_exception_3 = m68k_getpc() + 4;
51180: Exception(3, 0, M68000_EXC_SRC_CPU);
51181: goto endlabel2911;
51182: }
51183: {{ uae_s32 src = get_long(srca);
51184: CLEAR_CZNV;
51185: SET_ZFLG (((uae_s32)(src)) == 0);
51186: SET_NFLG (((uae_s32)(src)) < 0);
51187: }}}}m68k_incpc(4);
51188: fill_prefetch_0 ();
51189: endlabel2911: ;
51190: return 16;
51191: }
51192: unsigned long REGPARAM2 CPUFUNC(op_4ab0_5)(uae_u32 opcode) /* TST */
51193: {
51194: uae_u32 srcreg = (opcode & 7);
51195: OpcodeFamily = 20; CurrentInstrCycles = 18;
51196: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
51197: BusCyclePenalty += 2;
51198: if ((srca & 1) != 0) {
51199: last_fault_for_exception_3 = srca;
51200: last_op_for_exception_3 = opcode;
51201: last_addr_for_exception_3 = m68k_getpc() + 4;
51202: Exception(3, 0, M68000_EXC_SRC_CPU);
51203: goto endlabel2912;
51204: }
51205: {{ uae_s32 src = get_long(srca);
51206: CLEAR_CZNV;
51207: SET_ZFLG (((uae_s32)(src)) == 0);
51208: SET_NFLG (((uae_s32)(src)) < 0);
51209: }}}}m68k_incpc(4);
51210: fill_prefetch_0 ();
51211: endlabel2912: ;
51212: return 18;
51213: }
51214: unsigned long REGPARAM2 CPUFUNC(op_4ab8_5)(uae_u32 opcode) /* TST */
51215: {
51216: OpcodeFamily = 20; CurrentInstrCycles = 16;
51217: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
51218: if ((srca & 1) != 0) {
51219: last_fault_for_exception_3 = srca;
51220: last_op_for_exception_3 = opcode;
51221: last_addr_for_exception_3 = m68k_getpc() + 4;
51222: Exception(3, 0, M68000_EXC_SRC_CPU);
51223: goto endlabel2913;
51224: }
51225: {{ uae_s32 src = get_long(srca);
51226: CLEAR_CZNV;
51227: SET_ZFLG (((uae_s32)(src)) == 0);
51228: SET_NFLG (((uae_s32)(src)) < 0);
51229: }}}}m68k_incpc(4);
51230: fill_prefetch_0 ();
51231: endlabel2913: ;
51232: return 16;
51233: }
51234: unsigned long REGPARAM2 CPUFUNC(op_4ab9_5)(uae_u32 opcode) /* TST */
51235: {
51236: OpcodeFamily = 20; CurrentInstrCycles = 20;
51237: {{ uaecptr srca = get_ilong_prefetch(2);
51238: if ((srca & 1) != 0) {
51239: last_fault_for_exception_3 = srca;
51240: last_op_for_exception_3 = opcode;
51241: last_addr_for_exception_3 = m68k_getpc() + 6;
51242: Exception(3, 0, M68000_EXC_SRC_CPU);
51243: goto endlabel2914;
51244: }
51245: {{ uae_s32 src = get_long(srca);
51246: CLEAR_CZNV;
51247: SET_ZFLG (((uae_s32)(src)) == 0);
51248: SET_NFLG (((uae_s32)(src)) < 0);
51249: }}}}m68k_incpc(6);
51250: fill_prefetch_0 ();
51251: endlabel2914: ;
51252: return 20;
51253: }
51254: unsigned long REGPARAM2 CPUFUNC(op_4aba_5)(uae_u32 opcode) /* TST */
51255: {
51256: OpcodeFamily = 20; CurrentInstrCycles = 16;
51257: {{ uaecptr srca = m68k_getpc () + 2;
51258: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
51259: if ((srca & 1) != 0) {
51260: last_fault_for_exception_3 = srca;
51261: last_op_for_exception_3 = opcode;
51262: last_addr_for_exception_3 = m68k_getpc() + 4;
51263: Exception(3, 0, M68000_EXC_SRC_CPU);
51264: goto endlabel2915;
51265: }
51266: {{ uae_s32 src = get_long(srca);
51267: CLEAR_CZNV;
51268: SET_ZFLG (((uae_s32)(src)) == 0);
51269: SET_NFLG (((uae_s32)(src)) < 0);
51270: }}}}m68k_incpc(4);
51271: fill_prefetch_0 ();
51272: endlabel2915: ;
51273: return 16;
51274: }
51275: unsigned long REGPARAM2 CPUFUNC(op_4abb_5)(uae_u32 opcode) /* TST */
51276: {
51277: OpcodeFamily = 20; CurrentInstrCycles = 18;
51278: {{ uaecptr tmppc = m68k_getpc() + 2;
51279: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
51280: BusCyclePenalty += 2;
51281: if ((srca & 1) != 0) {
51282: last_fault_for_exception_3 = srca;
51283: last_op_for_exception_3 = opcode;
51284: last_addr_for_exception_3 = m68k_getpc() + 4;
51285: Exception(3, 0, M68000_EXC_SRC_CPU);
51286: goto endlabel2916;
51287: }
51288: {{ uae_s32 src = get_long(srca);
51289: CLEAR_CZNV;
51290: SET_ZFLG (((uae_s32)(src)) == 0);
51291: SET_NFLG (((uae_s32)(src)) < 0);
51292: }}}}m68k_incpc(4);
51293: fill_prefetch_0 ();
51294: endlabel2916: ;
51295: return 18;
51296: }
51297: unsigned long REGPARAM2 CPUFUNC(op_4abc_5)(uae_u32 opcode) /* TST */
51298: {
51299: OpcodeFamily = 20; CurrentInstrCycles = 12;
51300: {{ uae_s32 src = get_ilong_prefetch(2);
51301: CLEAR_CZNV;
51302: SET_ZFLG (((uae_s32)(src)) == 0);
51303: SET_NFLG (((uae_s32)(src)) < 0);
51304: }}m68k_incpc(6);
51305: fill_prefetch_0 ();
51306: return 12;
51307: }
51308: unsigned long REGPARAM2 CPUFUNC(op_4ac0_5)(uae_u32 opcode) /* TAS */
51309: {
51310: uae_u32 srcreg = (opcode & 7);
51311: OpcodeFamily = 98; CurrentInstrCycles = 4;
51312: {{ uae_s8 src = m68k_dreg(regs, srcreg);
51313: CLEAR_CZNV;
51314: SET_ZFLG (((uae_s8)(src)) == 0);
51315: SET_NFLG (((uae_s8)(src)) < 0);
51316: src |= 0x80;
51317: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
51318: }}m68k_incpc(2);
51319: fill_prefetch_2 ();
51320: return 4;
51321: }
51322: unsigned long REGPARAM2 CPUFUNC(op_4ad0_5)(uae_u32 opcode) /* TAS */
51323: {
51324: uae_u32 srcreg = (opcode & 7);
51325: OpcodeFamily = 98; CurrentInstrCycles = 14;
51326: {{ uaecptr srca = m68k_areg(regs, srcreg);
51327: { uae_s8 src = get_byte(srca);
51328: CLEAR_CZNV;
51329: SET_ZFLG (((uae_s8)(src)) == 0);
51330: SET_NFLG (((uae_s8)(src)) < 0);
51331: src |= 0x80;
51332: m68k_incpc(2);
51333: fill_prefetch_2 ();
51334: put_byte(srca,src);
51335: }}}return 14;
51336: }
51337: unsigned long REGPARAM2 CPUFUNC(op_4ad8_5)(uae_u32 opcode) /* TAS */
51338: {
51339: uae_u32 srcreg = (opcode & 7);
51340: OpcodeFamily = 98; CurrentInstrCycles = 14;
51341: {{ uaecptr srca = m68k_areg(regs, srcreg);
51342: { uae_s8 src = get_byte(srca);
51343: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
51344: CLEAR_CZNV;
51345: SET_ZFLG (((uae_s8)(src)) == 0);
51346: SET_NFLG (((uae_s8)(src)) < 0);
51347: src |= 0x80;
51348: m68k_incpc(2);
51349: fill_prefetch_2 ();
51350: put_byte(srca,src);
51351: }}}return 14;
51352: }
51353: unsigned long REGPARAM2 CPUFUNC(op_4ae0_5)(uae_u32 opcode) /* TAS */
51354: {
51355: uae_u32 srcreg = (opcode & 7);
51356: OpcodeFamily = 98; CurrentInstrCycles = 16;
51357: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
51358: { uae_s8 src = get_byte(srca);
51359: m68k_areg (regs, srcreg) = srca;
51360: CLEAR_CZNV;
51361: SET_ZFLG (((uae_s8)(src)) == 0);
51362: SET_NFLG (((uae_s8)(src)) < 0);
51363: src |= 0x80;
51364: m68k_incpc(2);
51365: fill_prefetch_2 ();
51366: put_byte(srca,src);
51367: }}}return 16;
51368: }
51369: unsigned long REGPARAM2 CPUFUNC(op_4ae8_5)(uae_u32 opcode) /* TAS */
51370: {
51371: uae_u32 srcreg = (opcode & 7);
51372: OpcodeFamily = 98; CurrentInstrCycles = 18;
51373: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
51374: { uae_s8 src = get_byte(srca);
51375: CLEAR_CZNV;
51376: SET_ZFLG (((uae_s8)(src)) == 0);
51377: SET_NFLG (((uae_s8)(src)) < 0);
51378: src |= 0x80;
51379: m68k_incpc(4);
51380: fill_prefetch_0 ();
51381: put_byte(srca,src);
51382: }}}return 18;
51383: }
51384: unsigned long REGPARAM2 CPUFUNC(op_4af0_5)(uae_u32 opcode) /* TAS */
51385: {
51386: uae_u32 srcreg = (opcode & 7);
51387: OpcodeFamily = 98; CurrentInstrCycles = 20;
51388: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
51389: BusCyclePenalty += 2;
51390: { uae_s8 src = get_byte(srca);
51391: CLEAR_CZNV;
51392: SET_ZFLG (((uae_s8)(src)) == 0);
51393: SET_NFLG (((uae_s8)(src)) < 0);
51394: src |= 0x80;
51395: m68k_incpc(4);
51396: fill_prefetch_0 ();
51397: put_byte(srca,src);
51398: }}}return 20;
51399: }
51400: unsigned long REGPARAM2 CPUFUNC(op_4af8_5)(uae_u32 opcode) /* TAS */
51401: {
51402: OpcodeFamily = 98; CurrentInstrCycles = 18;
51403: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
51404: { uae_s8 src = get_byte(srca);
51405: CLEAR_CZNV;
51406: SET_ZFLG (((uae_s8)(src)) == 0);
51407: SET_NFLG (((uae_s8)(src)) < 0);
51408: src |= 0x80;
51409: m68k_incpc(4);
51410: fill_prefetch_0 ();
51411: put_byte(srca,src);
51412: }}}return 18;
51413: }
51414: unsigned long REGPARAM2 CPUFUNC(op_4af9_5)(uae_u32 opcode) /* TAS */
51415: {
51416: OpcodeFamily = 98; CurrentInstrCycles = 22;
51417: {{ uaecptr srca = get_ilong_prefetch(2);
51418: { uae_s8 src = get_byte(srca);
51419: CLEAR_CZNV;
51420: SET_ZFLG (((uae_s8)(src)) == 0);
51421: SET_NFLG (((uae_s8)(src)) < 0);
51422: src |= 0x80;
51423: m68k_incpc(6);
51424: fill_prefetch_0 ();
51425: put_byte(srca,src);
51426: }}}return 22;
51427: }
51428: unsigned long REGPARAM2 CPUFUNC(op_4c90_5)(uae_u32 opcode) /* MVMEL */
51429: {
51430: uae_u32 dstreg = opcode & 7;
51431: unsigned int retcycles = 0;
51432: OpcodeFamily = 37; CurrentInstrCycles = 12;
51433: { uae_u16 mask = get_iword_prefetch(2);
51434: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51435: retcycles = 0;
51436: { uaecptr srca = m68k_areg(regs, dstreg);
51437: if ((srca & 1) != 0) {
51438: last_fault_for_exception_3 = srca;
51439: last_op_for_exception_3 = opcode;
51440: last_addr_for_exception_3 = m68k_getpc() + 4;
51441: Exception(3, 0, M68000_EXC_SRC_CPU);
51442: goto endlabel2926;
51443: }
51444: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
51445: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
51446: }}}}m68k_incpc(4);
51447: fill_prefetch_0 ();
51448: endlabel2926: ;
51449: return (12+retcycles);
51450: }
51451: unsigned long REGPARAM2 CPUFUNC(op_4c98_5)(uae_u32 opcode) /* MVMEL */
51452: {
51453: uae_u32 dstreg = opcode & 7;
51454: unsigned int retcycles = 0;
51455: OpcodeFamily = 37; CurrentInstrCycles = 12;
51456: { uae_u16 mask = get_iword_prefetch(2);
51457: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51458: retcycles = 0;
51459: { uaecptr srca = m68k_areg(regs, dstreg);
51460: if ((srca & 1) != 0) {
51461: last_fault_for_exception_3 = srca;
51462: last_op_for_exception_3 = opcode;
51463: last_addr_for_exception_3 = m68k_getpc() + 4;
51464: Exception(3, 0, M68000_EXC_SRC_CPU);
51465: goto endlabel2927;
51466: }
51467: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
51468: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
51469: m68k_areg(regs, dstreg) = srca;
51470: }}}}m68k_incpc(4);
51471: fill_prefetch_0 ();
51472: endlabel2927: ;
51473: return (12+retcycles);
51474: }
51475: unsigned long REGPARAM2 CPUFUNC(op_4ca8_5)(uae_u32 opcode) /* MVMEL */
51476: {
51477: uae_u32 dstreg = opcode & 7;
51478: unsigned int retcycles = 0;
51479: OpcodeFamily = 37; CurrentInstrCycles = 16;
51480: { uae_u16 mask = get_iword_prefetch(2);
51481: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51482: retcycles = 0;
51483: { uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
51484: if ((srca & 1) != 0) {
51485: last_fault_for_exception_3 = srca;
51486: last_op_for_exception_3 = opcode;
51487: last_addr_for_exception_3 = m68k_getpc() + 6;
51488: Exception(3, 0, M68000_EXC_SRC_CPU);
51489: goto endlabel2928;
51490: }
51491: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
51492: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
51493: }}}}m68k_incpc(6);
51494: fill_prefetch_0 ();
51495: endlabel2928: ;
51496: return (16+retcycles);
51497: }
51498: unsigned long REGPARAM2 CPUFUNC(op_4cb0_5)(uae_u32 opcode) /* MVMEL */
51499: {
51500: uae_u32 dstreg = opcode & 7;
51501: unsigned int retcycles = 0;
51502: OpcodeFamily = 37; CurrentInstrCycles = 18;
51503: { uae_u16 mask = get_iword_prefetch(2);
51504: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51505: retcycles = 0;
51506: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
51507: BusCyclePenalty += 2;
51508: if ((srca & 1) != 0) {
51509: last_fault_for_exception_3 = srca;
51510: last_op_for_exception_3 = opcode;
51511: last_addr_for_exception_3 = m68k_getpc() + 6;
51512: Exception(3, 0, M68000_EXC_SRC_CPU);
51513: goto endlabel2929;
51514: }
51515: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
51516: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
51517: }}}}m68k_incpc(6);
51518: fill_prefetch_0 ();
51519: endlabel2929: ;
51520: return (18+retcycles);
51521: }
51522: unsigned long REGPARAM2 CPUFUNC(op_4cb8_5)(uae_u32 opcode) /* MVMEL */
51523: {
51524: unsigned int retcycles = 0;
51525: OpcodeFamily = 37; CurrentInstrCycles = 16;
51526: { uae_u16 mask = get_iword_prefetch(2);
51527: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51528: retcycles = 0;
51529: { uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(4);
51530: if ((srca & 1) != 0) {
51531: last_fault_for_exception_3 = srca;
51532: last_op_for_exception_3 = opcode;
51533: last_addr_for_exception_3 = m68k_getpc() + 6;
51534: Exception(3, 0, M68000_EXC_SRC_CPU);
51535: goto endlabel2930;
51536: }
51537: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
51538: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
51539: }}}}m68k_incpc(6);
51540: fill_prefetch_0 ();
51541: endlabel2930: ;
51542: return (16+retcycles);
51543: }
51544: unsigned long REGPARAM2 CPUFUNC(op_4cb9_5)(uae_u32 opcode) /* MVMEL */
51545: {
51546: unsigned int retcycles = 0;
51547: OpcodeFamily = 37; CurrentInstrCycles = 20;
51548: { uae_u16 mask = get_iword_prefetch(2);
51549: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51550: retcycles = 0;
51551: { uaecptr srca = get_ilong_prefetch(4);
51552: if ((srca & 1) != 0) {
51553: last_fault_for_exception_3 = srca;
51554: last_op_for_exception_3 = opcode;
51555: last_addr_for_exception_3 = m68k_getpc() + 8;
51556: Exception(3, 0, M68000_EXC_SRC_CPU);
51557: goto endlabel2931;
51558: }
51559: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
51560: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
51561: }}}}m68k_incpc(8);
51562: fill_prefetch_0 ();
51563: endlabel2931: ;
51564: return (20+retcycles);
51565: }
51566: unsigned long REGPARAM2 CPUFUNC(op_4cba_5)(uae_u32 opcode) /* MVMEL */
51567: {
51568: uae_u32 dstreg = 2;
51569: unsigned int retcycles = 0;
51570: OpcodeFamily = 37; CurrentInstrCycles = 16;
51571: { uae_u16 mask = get_iword_prefetch(2);
51572: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51573: retcycles = 0;
51574: { uaecptr srca = m68k_getpc () + 4;
51575: srca += (uae_s32)(uae_s16)get_iword_prefetch(4);
51576: if ((srca & 1) != 0) {
51577: last_fault_for_exception_3 = srca;
51578: last_op_for_exception_3 = opcode;
51579: last_addr_for_exception_3 = m68k_getpc() + 6;
51580: Exception(3, 0, M68000_EXC_SRC_CPU);
51581: goto endlabel2932;
51582: }
51583: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
51584: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
51585: }}}}m68k_incpc(6);
51586: fill_prefetch_0 ();
51587: endlabel2932: ;
51588: return (16+retcycles);
51589: }
51590: unsigned long REGPARAM2 CPUFUNC(op_4cbb_5)(uae_u32 opcode) /* MVMEL */
51591: {
51592: uae_u32 dstreg = 3;
51593: unsigned int retcycles = 0;
51594: OpcodeFamily = 37; CurrentInstrCycles = 18;
51595: { uae_u16 mask = get_iword_prefetch(2);
51596: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51597: retcycles = 0;
51598: { uaecptr tmppc = m68k_getpc() + 4;
51599: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(4));
51600: BusCyclePenalty += 2;
51601: if ((srca & 1) != 0) {
51602: last_fault_for_exception_3 = srca;
51603: last_op_for_exception_3 = opcode;
51604: last_addr_for_exception_3 = m68k_getpc() + 6;
51605: Exception(3, 0, M68000_EXC_SRC_CPU);
51606: goto endlabel2933;
51607: }
51608: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
51609: while (amask) { m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
51610: }}}}m68k_incpc(6);
51611: fill_prefetch_0 ();
51612: endlabel2933: ;
51613: return (18+retcycles);
51614: }
51615: unsigned long REGPARAM2 CPUFUNC(op_4cd0_5)(uae_u32 opcode) /* MVMEL */
51616: {
51617: uae_u32 dstreg = opcode & 7;
51618: unsigned int retcycles = 0;
51619: OpcodeFamily = 37; CurrentInstrCycles = 12;
51620: { uae_u16 mask = get_iword_prefetch(2);
51621: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51622: retcycles = 0;
51623: { uaecptr srca = m68k_areg(regs, dstreg);
51624: if ((srca & 1) != 0) {
51625: last_fault_for_exception_3 = srca;
51626: last_op_for_exception_3 = opcode;
51627: last_addr_for_exception_3 = m68k_getpc() + 4;
51628: Exception(3, 0, M68000_EXC_SRC_CPU);
51629: goto endlabel2934;
51630: }
51631: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
51632: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
51633: }}}}m68k_incpc(4);
51634: fill_prefetch_0 ();
51635: endlabel2934: ;
51636: return (12+retcycles);
51637: }
51638: unsigned long REGPARAM2 CPUFUNC(op_4cd8_5)(uae_u32 opcode) /* MVMEL */
51639: {
51640: uae_u32 dstreg = opcode & 7;
51641: unsigned int retcycles = 0;
51642: OpcodeFamily = 37; CurrentInstrCycles = 12;
51643: { uae_u16 mask = get_iword_prefetch(2);
51644: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51645: retcycles = 0;
51646: { uaecptr srca = m68k_areg(regs, dstreg);
51647: if ((srca & 1) != 0) {
51648: last_fault_for_exception_3 = srca;
51649: last_op_for_exception_3 = opcode;
51650: last_addr_for_exception_3 = m68k_getpc() + 4;
51651: Exception(3, 0, M68000_EXC_SRC_CPU);
51652: goto endlabel2935;
51653: }
51654: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
51655: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
51656: m68k_areg(regs, dstreg) = srca;
51657: }}}}m68k_incpc(4);
51658: fill_prefetch_0 ();
51659: endlabel2935: ;
51660: return (12+retcycles);
51661: }
51662: unsigned long REGPARAM2 CPUFUNC(op_4ce8_5)(uae_u32 opcode) /* MVMEL */
51663: {
51664: uae_u32 dstreg = opcode & 7;
51665: unsigned int retcycles = 0;
51666: OpcodeFamily = 37; CurrentInstrCycles = 16;
51667: { uae_u16 mask = get_iword_prefetch(2);
51668: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51669: retcycles = 0;
51670: { uaecptr srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(4);
51671: if ((srca & 1) != 0) {
51672: last_fault_for_exception_3 = srca;
51673: last_op_for_exception_3 = opcode;
51674: last_addr_for_exception_3 = m68k_getpc() + 6;
51675: Exception(3, 0, M68000_EXC_SRC_CPU);
51676: goto endlabel2936;
51677: }
51678: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
51679: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
51680: }}}}m68k_incpc(6);
51681: fill_prefetch_0 ();
51682: endlabel2936: ;
51683: return (16+retcycles);
51684: }
51685: unsigned long REGPARAM2 CPUFUNC(op_4cf0_5)(uae_u32 opcode) /* MVMEL */
51686: {
51687: uae_u32 dstreg = opcode & 7;
51688: unsigned int retcycles = 0;
51689: OpcodeFamily = 37; CurrentInstrCycles = 18;
51690: { uae_u16 mask = get_iword_prefetch(2);
51691: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51692: retcycles = 0;
51693: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4));
51694: BusCyclePenalty += 2;
51695: if ((srca & 1) != 0) {
51696: last_fault_for_exception_3 = srca;
51697: last_op_for_exception_3 = opcode;
51698: last_addr_for_exception_3 = m68k_getpc() + 6;
51699: Exception(3, 0, M68000_EXC_SRC_CPU);
51700: goto endlabel2937;
51701: }
51702: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
51703: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
51704: }}}}m68k_incpc(6);
51705: fill_prefetch_0 ();
51706: endlabel2937: ;
51707: return (18+retcycles);
51708: }
51709: unsigned long REGPARAM2 CPUFUNC(op_4cf8_5)(uae_u32 opcode) /* MVMEL */
51710: {
51711: unsigned int retcycles = 0;
51712: OpcodeFamily = 37; CurrentInstrCycles = 16;
51713: { uae_u16 mask = get_iword_prefetch(2);
51714: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51715: retcycles = 0;
51716: { uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(4);
51717: if ((srca & 1) != 0) {
51718: last_fault_for_exception_3 = srca;
51719: last_op_for_exception_3 = opcode;
51720: last_addr_for_exception_3 = m68k_getpc() + 6;
51721: Exception(3, 0, M68000_EXC_SRC_CPU);
51722: goto endlabel2938;
51723: }
51724: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
51725: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
51726: }}}}m68k_incpc(6);
51727: fill_prefetch_0 ();
51728: endlabel2938: ;
51729: return (16+retcycles);
51730: }
51731: unsigned long REGPARAM2 CPUFUNC(op_4cf9_5)(uae_u32 opcode) /* MVMEL */
51732: {
51733: unsigned int retcycles = 0;
51734: OpcodeFamily = 37; CurrentInstrCycles = 20;
51735: { uae_u16 mask = get_iword_prefetch(2);
51736: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51737: retcycles = 0;
51738: { uaecptr srca = get_ilong_prefetch(4);
51739: if ((srca & 1) != 0) {
51740: last_fault_for_exception_3 = srca;
51741: last_op_for_exception_3 = opcode;
51742: last_addr_for_exception_3 = m68k_getpc() + 8;
51743: Exception(3, 0, M68000_EXC_SRC_CPU);
51744: goto endlabel2939;
51745: }
51746: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
51747: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
51748: }}}}m68k_incpc(8);
51749: fill_prefetch_0 ();
51750: endlabel2939: ;
51751: return (20+retcycles);
51752: }
51753: unsigned long REGPARAM2 CPUFUNC(op_4cfa_5)(uae_u32 opcode) /* MVMEL */
51754: {
51755: uae_u32 dstreg = 2;
51756: unsigned int retcycles = 0;
51757: OpcodeFamily = 37; CurrentInstrCycles = 16;
51758: { uae_u16 mask = get_iword_prefetch(2);
51759: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51760: retcycles = 0;
51761: { uaecptr srca = m68k_getpc () + 4;
51762: srca += (uae_s32)(uae_s16)get_iword_prefetch(4);
51763: if ((srca & 1) != 0) {
51764: last_fault_for_exception_3 = srca;
51765: last_op_for_exception_3 = opcode;
51766: last_addr_for_exception_3 = m68k_getpc() + 6;
51767: Exception(3, 0, M68000_EXC_SRC_CPU);
51768: goto endlabel2940;
51769: }
51770: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
51771: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
51772: }}}}m68k_incpc(6);
51773: fill_prefetch_0 ();
51774: endlabel2940: ;
51775: return (16+retcycles);
51776: }
51777: unsigned long REGPARAM2 CPUFUNC(op_4cfb_5)(uae_u32 opcode) /* MVMEL */
51778: {
51779: uae_u32 dstreg = 3;
51780: unsigned int retcycles = 0;
51781: OpcodeFamily = 37; CurrentInstrCycles = 18;
51782: { uae_u16 mask = get_iword_prefetch(2);
51783: unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
51784: retcycles = 0;
51785: { uaecptr tmppc = m68k_getpc() + 4;
51786: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(4));
51787: BusCyclePenalty += 2;
51788: if ((srca & 1) != 0) {
51789: last_fault_for_exception_3 = srca;
51790: last_op_for_exception_3 = opcode;
51791: last_addr_for_exception_3 = m68k_getpc() + 6;
51792: Exception(3, 0, M68000_EXC_SRC_CPU);
51793: goto endlabel2941;
51794: }
51795: {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = get_long(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
51796: while (amask) { m68k_areg(regs, movem_index1[amask]) = get_long(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
51797: }}}}m68k_incpc(6);
51798: fill_prefetch_0 ();
51799: endlabel2941: ;
51800: return (18+retcycles);
51801: }
51802: unsigned long REGPARAM2 CPUFUNC(op_4e40_5)(uae_u32 opcode) /* TRAP */
51803: {
51804: uae_u32 srcreg = (opcode & 15);
51805: OpcodeFamily = 39; CurrentInstrCycles = 4;
51806: {{ uae_u32 src = srcreg;
51807: m68k_incpc(2);
51808: fill_prefetch_2 ();
51809: Exception(src+32,0,M68000_EXC_SRC_CPU);
51810: }}return 4;
51811: }
51812: unsigned long REGPARAM2 CPUFUNC(op_4e50_5)(uae_u32 opcode) /* LINK */
51813: {
51814: uae_u32 srcreg = (opcode & 7);
51815: OpcodeFamily = 47; CurrentInstrCycles = 18;
51816: {{ uaecptr olda = m68k_areg(regs, 7) - 4;
51817: if ((olda & 1) != 0) {
51818: last_fault_for_exception_3 = olda;
51819: last_op_for_exception_3 = opcode;
51820: last_addr_for_exception_3 = m68k_getpc() + 2;
51821: Exception(3, 0, M68000_EXC_SRC_CPU);
51822: goto endlabel2943;
51823: }
51824: { m68k_areg (regs, 7) = olda;
51825: { uae_s32 src = m68k_areg(regs, srcreg);
51826: m68k_incpc(2);
51827: fill_prefetch_2 ();
51828: put_long(olda,src);
51829: m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
51830: { uae_s16 offs = get_iword_prefetch(0);
51831: m68k_areg(regs, 7) += offs;
51832: }}}}}m68k_incpc(2);
51833: fill_prefetch_2 ();
51834: endlabel2943: ;
51835: return 18;
51836: }
51837: unsigned long REGPARAM2 CPUFUNC(op_4e58_5)(uae_u32 opcode) /* UNLK */
51838: {
51839: uae_u32 srcreg = (opcode & 7);
51840: OpcodeFamily = 48; CurrentInstrCycles = 12;
51841: {{ uae_s32 src = m68k_areg(regs, srcreg);
51842: m68k_areg(regs, 7) = src;
51843: { uaecptr olda = m68k_areg(regs, 7);
51844: if ((olda & 1) != 0) {
51845: last_fault_for_exception_3 = olda;
51846: last_op_for_exception_3 = opcode;
51847: last_addr_for_exception_3 = m68k_getpc() + 2;
51848: Exception(3, 0, M68000_EXC_SRC_CPU);
51849: goto endlabel2944;
51850: }
51851: {{ uae_s32 old = get_long(olda);
51852: m68k_areg(regs, 7) += 4;
51853: m68k_areg(regs, srcreg) = (old);
51854: }}}}}m68k_incpc(2);
51855: fill_prefetch_2 ();
51856: endlabel2944: ;
51857: return 12;
51858: }
51859: unsigned long REGPARAM2 CPUFUNC(op_4e60_5)(uae_u32 opcode) /* MVR2USP */
51860: {
51861: uae_u32 srcreg = (opcode & 7);
51862: OpcodeFamily = 40; CurrentInstrCycles = 4;
51863: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2945; }
51864: {{ uae_s32 src = m68k_areg(regs, srcreg);
51865: regs.usp = src;
51866: }}}m68k_incpc(2);
51867: fill_prefetch_2 ();
51868: endlabel2945: ;
51869: return 4;
51870: }
51871: unsigned long REGPARAM2 CPUFUNC(op_4e68_5)(uae_u32 opcode) /* MVUSP2R */
51872: {
51873: uae_u32 srcreg = (opcode & 7);
51874: OpcodeFamily = 41; CurrentInstrCycles = 4;
51875: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2946; }
51876: {{ m68k_areg(regs, srcreg) = (regs.usp);
51877: }}}m68k_incpc(2);
51878: fill_prefetch_2 ();
51879: endlabel2946: ;
51880: return 4;
51881: }
51882: unsigned long REGPARAM2 CPUFUNC(op_4e70_5)(uae_u32 opcode) /* RESET */
51883: {
51884: OpcodeFamily = 42; CurrentInstrCycles = 132;
51885: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2947; }
51886: { customreset();
51887: }}m68k_incpc(2);
51888: fill_prefetch_2 ();
51889: endlabel2947: ;
51890: return 132;
51891: }
51892: unsigned long REGPARAM2 CPUFUNC(op_4e71_5)(uae_u32 opcode) /* NOP */
51893: {
51894: OpcodeFamily = 43; CurrentInstrCycles = 4;
51895: {}m68k_incpc(2);
51896: fill_prefetch_2 ();
51897: return 4;
51898: }
51899: unsigned long REGPARAM2 CPUFUNC(op_4e72_5)(uae_u32 opcode) /* STOP */
51900: {
51901: OpcodeFamily = 44; CurrentInstrCycles = 4;
51902: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2949; }
51903: {{ uae_s16 src = get_iword_prefetch(2);
51904: regs.sr = src;
51905: MakeFromSR();
51906: m68k_setstopped(1);
51907: }}}m68k_incpc(4);
51908: fill_prefetch_0 ();
51909: endlabel2949: ;
51910: return 4;
51911: }
51912: unsigned long REGPARAM2 CPUFUNC(op_4e73_5)(uae_u32 opcode) /* RTE */
51913: {
51914: OpcodeFamily = 45; CurrentInstrCycles = 20;
51915: {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2950; }
51916: {{ uaecptr sra = m68k_areg(regs, 7);
51917: if ((sra & 1) != 0) {
51918: last_fault_for_exception_3 = sra;
51919: last_op_for_exception_3 = opcode;
51920: last_addr_for_exception_3 = m68k_getpc() + 2;
51921: Exception(3, 0, M68000_EXC_SRC_CPU);
51922: goto endlabel2950;
51923: }
51924: {{ uae_s16 sr = get_word(sra);
51925: m68k_areg(regs, 7) += 2;
51926: { uaecptr pca = m68k_areg(regs, 7);
51927: if ((pca & 1) != 0) {
51928: last_fault_for_exception_3 = pca;
51929: last_op_for_exception_3 = opcode;
51930: last_addr_for_exception_3 = m68k_getpc() + 2;
51931: Exception(3, 0, M68000_EXC_SRC_CPU);
51932: goto endlabel2950;
51933: }
51934: {{ uae_s32 pc = get_long(pca);
51935: m68k_areg(regs, 7) += 4;
51936: regs.sr = sr; m68k_setpc_rte(pc);
51937: fill_prefetch_0 ();
51938: MakeFromSR();
51939: }}}}}}}}endlabel2950: ;
51940: return 20;
51941: }
51942: unsigned long REGPARAM2 CPUFUNC(op_4e74_5)(uae_u32 opcode) /* RTD */
51943: {
51944: OpcodeFamily = 46; CurrentInstrCycles = 16;
51945: {{ uaecptr pca = m68k_areg(regs, 7);
51946: if ((pca & 1) != 0) {
51947: last_fault_for_exception_3 = pca;
51948: last_op_for_exception_3 = opcode;
51949: last_addr_for_exception_3 = m68k_getpc() + 2;
51950: Exception(3, 0, M68000_EXC_SRC_CPU);
51951: goto endlabel2951;
51952: }
51953: {{ uae_s32 pc = get_long(pca);
51954: m68k_areg(regs, 7) += 4;
51955: { uae_s16 offs = get_iword_prefetch(2);
51956: m68k_areg(regs, 7) += offs;
51957: m68k_setpc_rte(pc);
51958: fill_prefetch_0 ();
51959: }}}}}endlabel2951: ;
51960: return 16;
51961: }
51962: unsigned long REGPARAM2 CPUFUNC(op_4e75_5)(uae_u32 opcode) /* RTS */
51963: {
51964: OpcodeFamily = 49; CurrentInstrCycles = 16;
51965: { m68k_do_rts();
51966: fill_prefetch_0 ();
51967: }return 16;
51968: }
51969: unsigned long REGPARAM2 CPUFUNC(op_4e76_5)(uae_u32 opcode) /* TRAPV */
51970: {
51971: OpcodeFamily = 50; CurrentInstrCycles = 4;
51972: {m68k_incpc(2);
51973: fill_prefetch_2 ();
51974: if (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel2953; }
51975: }endlabel2953: ;
51976: return 4;
51977: }
51978: unsigned long REGPARAM2 CPUFUNC(op_4e77_5)(uae_u32 opcode) /* RTR */
51979: {
51980: OpcodeFamily = 51; CurrentInstrCycles = 20;
51981: { MakeSR();
51982: { uaecptr sra = m68k_areg(regs, 7);
51983: if ((sra & 1) != 0) {
51984: last_fault_for_exception_3 = sra;
51985: last_op_for_exception_3 = opcode;
51986: last_addr_for_exception_3 = m68k_getpc() + 2;
51987: Exception(3, 0, M68000_EXC_SRC_CPU);
51988: goto endlabel2954;
51989: }
51990: {{ uae_s16 sr = get_word(sra);
51991: m68k_areg(regs, 7) += 2;
51992: { uaecptr pca = m68k_areg(regs, 7);
51993: if ((pca & 1) != 0) {
51994: last_fault_for_exception_3 = pca;
51995: last_op_for_exception_3 = opcode;
51996: last_addr_for_exception_3 = m68k_getpc() + 2;
51997: Exception(3, 0, M68000_EXC_SRC_CPU);
51998: goto endlabel2954;
51999: }
52000: {{ uae_s32 pc = get_long(pca);
52001: m68k_areg(regs, 7) += 4;
52002: regs.sr &= 0xFF00; sr &= 0xFF;
52003: regs.sr |= sr; m68k_setpc(pc);
52004: fill_prefetch_0 ();
52005: MakeFromSR();
52006: }}}}}}}endlabel2954: ;
52007: return 20;
52008: }
52009: unsigned long REGPARAM2 CPUFUNC(op_4e90_5)(uae_u32 opcode) /* JSR */
52010: {
52011: uae_u32 srcreg = (opcode & 7);
52012: OpcodeFamily = 52; CurrentInstrCycles = 16;
52013: {{ uaecptr srca = m68k_areg(regs, srcreg);
52014: m68k_do_jsr(m68k_getpc() + 2, srca);
52015: fill_prefetch_0 ();
52016: }}return 16;
52017: }
52018: unsigned long REGPARAM2 CPUFUNC(op_4ea8_5)(uae_u32 opcode) /* JSR */
52019: {
52020: uae_u32 srcreg = (opcode & 7);
52021: OpcodeFamily = 52; CurrentInstrCycles = 18;
52022: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
52023: m68k_do_jsr(m68k_getpc() + 4, srca);
52024: fill_prefetch_0 ();
52025: }}return 18;
52026: }
52027: unsigned long REGPARAM2 CPUFUNC(op_4eb0_5)(uae_u32 opcode) /* JSR */
52028: {
52029: uae_u32 srcreg = (opcode & 7);
52030: OpcodeFamily = 52; CurrentInstrCycles = 22;
52031: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
52032: BusCyclePenalty += 2;
52033: m68k_do_jsr(m68k_getpc() + 4, srca);
52034: fill_prefetch_0 ();
52035: }}return 22;
52036: }
52037: unsigned long REGPARAM2 CPUFUNC(op_4eb8_5)(uae_u32 opcode) /* JSR */
52038: {
52039: OpcodeFamily = 52; CurrentInstrCycles = 18;
52040: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
52041: m68k_do_jsr(m68k_getpc() + 4, srca);
52042: fill_prefetch_0 ();
52043: }}return 18;
52044: }
52045: unsigned long REGPARAM2 CPUFUNC(op_4eb9_5)(uae_u32 opcode) /* JSR */
52046: {
52047: OpcodeFamily = 52; CurrentInstrCycles = 20;
52048: {{ uaecptr srca = get_ilong_prefetch(2);
52049: m68k_do_jsr(m68k_getpc() + 6, srca);
52050: fill_prefetch_0 ();
52051: }}return 20;
52052: }
52053: unsigned long REGPARAM2 CPUFUNC(op_4eba_5)(uae_u32 opcode) /* JSR */
52054: {
52055: OpcodeFamily = 52; CurrentInstrCycles = 18;
52056: {{ uaecptr srca = m68k_getpc () + 2;
52057: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
52058: m68k_do_jsr(m68k_getpc() + 4, srca);
52059: fill_prefetch_0 ();
52060: }}return 18;
52061: }
52062: unsigned long REGPARAM2 CPUFUNC(op_4ebb_5)(uae_u32 opcode) /* JSR */
52063: {
52064: OpcodeFamily = 52; CurrentInstrCycles = 22;
52065: {{ uaecptr tmppc = m68k_getpc() + 2;
52066: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
52067: BusCyclePenalty += 2;
52068: m68k_do_jsr(m68k_getpc() + 4, srca);
52069: fill_prefetch_0 ();
52070: }}return 22;
52071: }
52072: unsigned long REGPARAM2 CPUFUNC(op_4ed0_5)(uae_u32 opcode) /* JMP */
52073: {
52074: uae_u32 srcreg = (opcode & 7);
52075: OpcodeFamily = 53; CurrentInstrCycles = 8;
52076: {{ uaecptr srca = m68k_areg(regs, srcreg);
52077: m68k_setpc(srca);
52078: fill_prefetch_0 ();
52079: }}return 8;
52080: }
52081: unsigned long REGPARAM2 CPUFUNC(op_4ee8_5)(uae_u32 opcode) /* JMP */
52082: {
52083: uae_u32 srcreg = (opcode & 7);
52084: OpcodeFamily = 53; CurrentInstrCycles = 10;
52085: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
52086: m68k_setpc(srca);
52087: fill_prefetch_0 ();
52088: }}return 10;
52089: }
52090: unsigned long REGPARAM2 CPUFUNC(op_4ef0_5)(uae_u32 opcode) /* JMP */
52091: {
52092: uae_u32 srcreg = (opcode & 7);
52093: OpcodeFamily = 53; CurrentInstrCycles = 14;
52094: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
52095: BusCyclePenalty += 2;
52096: m68k_setpc(srca);
52097: fill_prefetch_0 ();
52098: }}return 14;
52099: }
52100: unsigned long REGPARAM2 CPUFUNC(op_4ef8_5)(uae_u32 opcode) /* JMP */
52101: {
52102: OpcodeFamily = 53; CurrentInstrCycles = 10;
52103: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
52104: m68k_setpc(srca);
52105: fill_prefetch_0 ();
52106: }}return 10;
52107: }
52108: unsigned long REGPARAM2 CPUFUNC(op_4ef9_5)(uae_u32 opcode) /* JMP */
52109: {
52110: OpcodeFamily = 53; CurrentInstrCycles = 12;
52111: {{ uaecptr srca = get_ilong_prefetch(2);
52112: m68k_setpc(srca);
52113: fill_prefetch_0 ();
52114: }}return 12;
52115: }
52116: unsigned long REGPARAM2 CPUFUNC(op_4efa_5)(uae_u32 opcode) /* JMP */
52117: {
52118: OpcodeFamily = 53; CurrentInstrCycles = 10;
52119: {{ uaecptr srca = m68k_getpc () + 2;
52120: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
52121: m68k_setpc(srca);
52122: fill_prefetch_0 ();
52123: }}return 10;
52124: }
52125: unsigned long REGPARAM2 CPUFUNC(op_4efb_5)(uae_u32 opcode) /* JMP */
52126: {
52127: OpcodeFamily = 53; CurrentInstrCycles = 14;
52128: {{ uaecptr tmppc = m68k_getpc() + 2;
52129: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
52130: BusCyclePenalty += 2;
52131: m68k_setpc(srca);
52132: fill_prefetch_0 ();
52133: }}return 14;
52134: }
52135: unsigned long REGPARAM2 CPUFUNC(op_5000_5)(uae_u32 opcode) /* ADD */
52136: {
52137: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52138: uae_u32 dstreg = opcode & 7;
52139: OpcodeFamily = 11; CurrentInstrCycles = 4;
52140: {{ uae_u32 src = srcreg;
52141: { uae_s8 dst = m68k_dreg(regs, dstreg);
52142: { refill_prefetch (m68k_getpc(), 2);
52143: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
52144: { int flgs = ((uae_s8)(src)) < 0;
52145: int flgo = ((uae_s8)(dst)) < 0;
52146: int flgn = ((uae_s8)(newv)) < 0;
52147: SET_ZFLG (((uae_s8)(newv)) == 0);
52148: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52149: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
52150: COPY_CARRY;
52151: SET_NFLG (flgn != 0);
52152: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
52153: }}}}}}m68k_incpc(2);
52154: fill_prefetch_2 ();
52155: return 4;
52156: }
52157: unsigned long REGPARAM2 CPUFUNC(op_5010_5)(uae_u32 opcode) /* ADD */
52158: {
52159: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52160: uae_u32 dstreg = opcode & 7;
52161: OpcodeFamily = 11; CurrentInstrCycles = 12;
52162: {{ uae_u32 src = srcreg;
52163: { uaecptr dsta = m68k_areg(regs, dstreg);
52164: { uae_s8 dst = get_byte(dsta);
52165: { refill_prefetch (m68k_getpc(), 2);
52166: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
52167: { int flgs = ((uae_s8)(src)) < 0;
52168: int flgo = ((uae_s8)(dst)) < 0;
52169: int flgn = ((uae_s8)(newv)) < 0;
52170: SET_ZFLG (((uae_s8)(newv)) == 0);
52171: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52172: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
52173: COPY_CARRY;
52174: SET_NFLG (flgn != 0);
52175: m68k_incpc(2);
52176: fill_prefetch_2 ();
52177: put_byte(dsta,newv);
52178: }}}}}}}return 12;
52179: }
52180: unsigned long REGPARAM2 CPUFUNC(op_5018_5)(uae_u32 opcode) /* ADD */
52181: {
52182: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52183: uae_u32 dstreg = opcode & 7;
52184: OpcodeFamily = 11; CurrentInstrCycles = 12;
52185: {{ uae_u32 src = srcreg;
52186: { uaecptr dsta = m68k_areg(regs, dstreg);
52187: { uae_s8 dst = get_byte(dsta);
52188: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
52189: { refill_prefetch (m68k_getpc(), 2);
52190: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
52191: { int flgs = ((uae_s8)(src)) < 0;
52192: int flgo = ((uae_s8)(dst)) < 0;
52193: int flgn = ((uae_s8)(newv)) < 0;
52194: SET_ZFLG (((uae_s8)(newv)) == 0);
52195: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52196: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
52197: COPY_CARRY;
52198: SET_NFLG (flgn != 0);
52199: m68k_incpc(2);
52200: fill_prefetch_2 ();
52201: put_byte(dsta,newv);
52202: }}}}}}}return 12;
52203: }
52204: #endif
52205:
52206: #ifdef PART_5
52207: unsigned long REGPARAM2 CPUFUNC(op_5020_5)(uae_u32 opcode) /* ADD */
52208: {
52209: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52210: uae_u32 dstreg = opcode & 7;
52211: OpcodeFamily = 11; CurrentInstrCycles = 14;
52212: {{ uae_u32 src = srcreg;
52213: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
52214: { uae_s8 dst = get_byte(dsta);
52215: m68k_areg (regs, dstreg) = dsta;
52216: { refill_prefetch (m68k_getpc(), 2);
52217: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
52218: { int flgs = ((uae_s8)(src)) < 0;
52219: int flgo = ((uae_s8)(dst)) < 0;
52220: int flgn = ((uae_s8)(newv)) < 0;
52221: SET_ZFLG (((uae_s8)(newv)) == 0);
52222: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52223: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
52224: COPY_CARRY;
52225: SET_NFLG (flgn != 0);
52226: m68k_incpc(2);
52227: fill_prefetch_2 ();
52228: put_byte(dsta,newv);
52229: }}}}}}}return 14;
52230: }
52231: unsigned long REGPARAM2 CPUFUNC(op_5028_5)(uae_u32 opcode) /* ADD */
52232: {
52233: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52234: uae_u32 dstreg = opcode & 7;
52235: OpcodeFamily = 11; CurrentInstrCycles = 16;
52236: {{ uae_u32 src = srcreg;
52237: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
52238: { uae_s8 dst = get_byte(dsta);
52239: { refill_prefetch (m68k_getpc(), 2);
52240: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
52241: { int flgs = ((uae_s8)(src)) < 0;
52242: int flgo = ((uae_s8)(dst)) < 0;
52243: int flgn = ((uae_s8)(newv)) < 0;
52244: SET_ZFLG (((uae_s8)(newv)) == 0);
52245: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52246: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
52247: COPY_CARRY;
52248: SET_NFLG (flgn != 0);
52249: m68k_incpc(4);
52250: fill_prefetch_0 ();
52251: put_byte(dsta,newv);
52252: }}}}}}}return 16;
52253: }
52254: unsigned long REGPARAM2 CPUFUNC(op_5030_5)(uae_u32 opcode) /* ADD */
52255: {
52256: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52257: uae_u32 dstreg = opcode & 7;
52258: OpcodeFamily = 11; CurrentInstrCycles = 18;
52259: {{ uae_u32 src = srcreg;
52260: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
52261: BusCyclePenalty += 2;
52262: { uae_s8 dst = get_byte(dsta);
52263: { refill_prefetch (m68k_getpc(), 2);
52264: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
52265: { int flgs = ((uae_s8)(src)) < 0;
52266: int flgo = ((uae_s8)(dst)) < 0;
52267: int flgn = ((uae_s8)(newv)) < 0;
52268: SET_ZFLG (((uae_s8)(newv)) == 0);
52269: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52270: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
52271: COPY_CARRY;
52272: SET_NFLG (flgn != 0);
52273: m68k_incpc(4);
52274: fill_prefetch_0 ();
52275: put_byte(dsta,newv);
52276: }}}}}}}return 18;
52277: }
52278: unsigned long REGPARAM2 CPUFUNC(op_5038_5)(uae_u32 opcode) /* ADD */
52279: {
52280: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52281: OpcodeFamily = 11; CurrentInstrCycles = 16;
52282: {{ uae_u32 src = srcreg;
52283: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
52284: { uae_s8 dst = get_byte(dsta);
52285: { refill_prefetch (m68k_getpc(), 2);
52286: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
52287: { int flgs = ((uae_s8)(src)) < 0;
52288: int flgo = ((uae_s8)(dst)) < 0;
52289: int flgn = ((uae_s8)(newv)) < 0;
52290: SET_ZFLG (((uae_s8)(newv)) == 0);
52291: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52292: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
52293: COPY_CARRY;
52294: SET_NFLG (flgn != 0);
52295: m68k_incpc(4);
52296: fill_prefetch_0 ();
52297: put_byte(dsta,newv);
52298: }}}}}}}return 16;
52299: }
52300: unsigned long REGPARAM2 CPUFUNC(op_5039_5)(uae_u32 opcode) /* ADD */
52301: {
52302: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52303: OpcodeFamily = 11; CurrentInstrCycles = 20;
52304: {{ uae_u32 src = srcreg;
52305: { uaecptr dsta = get_ilong_prefetch(2);
52306: { uae_s8 dst = get_byte(dsta);
52307: { refill_prefetch (m68k_getpc(), 2);
52308: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
52309: { int flgs = ((uae_s8)(src)) < 0;
52310: int flgo = ((uae_s8)(dst)) < 0;
52311: int flgn = ((uae_s8)(newv)) < 0;
52312: SET_ZFLG (((uae_s8)(newv)) == 0);
52313: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52314: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
52315: COPY_CARRY;
52316: SET_NFLG (flgn != 0);
52317: m68k_incpc(6);
52318: fill_prefetch_0 ();
52319: put_byte(dsta,newv);
52320: }}}}}}}return 20;
52321: }
52322: unsigned long REGPARAM2 CPUFUNC(op_5040_5)(uae_u32 opcode) /* ADD */
52323: {
52324: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52325: uae_u32 dstreg = opcode & 7;
52326: OpcodeFamily = 11; CurrentInstrCycles = 4;
52327: {{ uae_u32 src = srcreg;
52328: { uae_s16 dst = m68k_dreg(regs, dstreg);
52329: { refill_prefetch (m68k_getpc(), 2);
52330: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
52331: { int flgs = ((uae_s16)(src)) < 0;
52332: int flgo = ((uae_s16)(dst)) < 0;
52333: int flgn = ((uae_s16)(newv)) < 0;
52334: SET_ZFLG (((uae_s16)(newv)) == 0);
52335: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52336: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
52337: COPY_CARRY;
52338: SET_NFLG (flgn != 0);
52339: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
52340: }}}}}}m68k_incpc(2);
52341: fill_prefetch_2 ();
52342: return 4;
52343: }
52344: unsigned long REGPARAM2 CPUFUNC(op_5048_5)(uae_u32 opcode) /* ADDA */
52345: {
52346: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52347: uae_u32 dstreg = opcode & 7;
52348: OpcodeFamily = 12; CurrentInstrCycles = 8;
52349: {{ uae_u32 src = srcreg;
52350: { uae_s32 dst = m68k_areg(regs, dstreg);
52351: { uae_u32 newv = dst + src;
52352: m68k_areg(regs, dstreg) = (newv);
52353: }}}}m68k_incpc(2);
52354: fill_prefetch_2 ();
52355: return 8;
52356: }
52357: unsigned long REGPARAM2 CPUFUNC(op_5050_5)(uae_u32 opcode) /* ADD */
52358: {
52359: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52360: uae_u32 dstreg = opcode & 7;
52361: OpcodeFamily = 11; CurrentInstrCycles = 12;
52362: {{ uae_u32 src = srcreg;
52363: { uaecptr dsta = m68k_areg(regs, dstreg);
52364: if ((dsta & 1) != 0) {
52365: last_fault_for_exception_3 = dsta;
52366: last_op_for_exception_3 = opcode;
52367: last_addr_for_exception_3 = m68k_getpc() + 2;
52368: Exception(3, 0, M68000_EXC_SRC_CPU);
52369: goto endlabel2979;
52370: }
52371: {{ uae_s16 dst = get_word(dsta);
52372: { refill_prefetch (m68k_getpc(), 2);
52373: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
52374: { int flgs = ((uae_s16)(src)) < 0;
52375: int flgo = ((uae_s16)(dst)) < 0;
52376: int flgn = ((uae_s16)(newv)) < 0;
52377: SET_ZFLG (((uae_s16)(newv)) == 0);
52378: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52379: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
52380: COPY_CARRY;
52381: SET_NFLG (flgn != 0);
52382: m68k_incpc(2);
52383: fill_prefetch_2 ();
52384: put_word(dsta,newv);
52385: }}}}}}}}endlabel2979: ;
52386: return 12;
52387: }
52388: unsigned long REGPARAM2 CPUFUNC(op_5058_5)(uae_u32 opcode) /* ADD */
52389: {
52390: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52391: uae_u32 dstreg = opcode & 7;
52392: OpcodeFamily = 11; CurrentInstrCycles = 12;
52393: {{ uae_u32 src = srcreg;
52394: { uaecptr dsta = m68k_areg(regs, dstreg);
52395: if ((dsta & 1) != 0) {
52396: last_fault_for_exception_3 = dsta;
52397: last_op_for_exception_3 = opcode;
52398: last_addr_for_exception_3 = m68k_getpc() + 2;
52399: Exception(3, 0, M68000_EXC_SRC_CPU);
52400: goto endlabel2980;
52401: }
52402: {{ uae_s16 dst = get_word(dsta);
52403: m68k_areg(regs, dstreg) += 2;
52404: { refill_prefetch (m68k_getpc(), 2);
52405: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
52406: { int flgs = ((uae_s16)(src)) < 0;
52407: int flgo = ((uae_s16)(dst)) < 0;
52408: int flgn = ((uae_s16)(newv)) < 0;
52409: SET_ZFLG (((uae_s16)(newv)) == 0);
52410: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52411: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
52412: COPY_CARRY;
52413: SET_NFLG (flgn != 0);
52414: m68k_incpc(2);
52415: fill_prefetch_2 ();
52416: put_word(dsta,newv);
52417: }}}}}}}}endlabel2980: ;
52418: return 12;
52419: }
52420: unsigned long REGPARAM2 CPUFUNC(op_5060_5)(uae_u32 opcode) /* ADD */
52421: {
52422: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52423: uae_u32 dstreg = opcode & 7;
52424: OpcodeFamily = 11; CurrentInstrCycles = 14;
52425: {{ uae_u32 src = srcreg;
52426: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
52427: if ((dsta & 1) != 0) {
52428: last_fault_for_exception_3 = dsta;
52429: last_op_for_exception_3 = opcode;
52430: last_addr_for_exception_3 = m68k_getpc() + 2;
52431: Exception(3, 0, M68000_EXC_SRC_CPU);
52432: goto endlabel2981;
52433: }
52434: {{ uae_s16 dst = get_word(dsta);
52435: m68k_areg (regs, dstreg) = dsta;
52436: { refill_prefetch (m68k_getpc(), 2);
52437: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
52438: { int flgs = ((uae_s16)(src)) < 0;
52439: int flgo = ((uae_s16)(dst)) < 0;
52440: int flgn = ((uae_s16)(newv)) < 0;
52441: SET_ZFLG (((uae_s16)(newv)) == 0);
52442: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52443: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
52444: COPY_CARRY;
52445: SET_NFLG (flgn != 0);
52446: m68k_incpc(2);
52447: fill_prefetch_2 ();
52448: put_word(dsta,newv);
52449: }}}}}}}}endlabel2981: ;
52450: return 14;
52451: }
52452: unsigned long REGPARAM2 CPUFUNC(op_5068_5)(uae_u32 opcode) /* ADD */
52453: {
52454: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52455: uae_u32 dstreg = opcode & 7;
52456: OpcodeFamily = 11; CurrentInstrCycles = 16;
52457: {{ uae_u32 src = srcreg;
52458: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
52459: if ((dsta & 1) != 0) {
52460: last_fault_for_exception_3 = dsta;
52461: last_op_for_exception_3 = opcode;
52462: last_addr_for_exception_3 = m68k_getpc() + 4;
52463: Exception(3, 0, M68000_EXC_SRC_CPU);
52464: goto endlabel2982;
52465: }
52466: {{ uae_s16 dst = get_word(dsta);
52467: { refill_prefetch (m68k_getpc(), 2);
52468: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
52469: { int flgs = ((uae_s16)(src)) < 0;
52470: int flgo = ((uae_s16)(dst)) < 0;
52471: int flgn = ((uae_s16)(newv)) < 0;
52472: SET_ZFLG (((uae_s16)(newv)) == 0);
52473: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52474: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
52475: COPY_CARRY;
52476: SET_NFLG (flgn != 0);
52477: m68k_incpc(4);
52478: fill_prefetch_0 ();
52479: put_word(dsta,newv);
52480: }}}}}}}}endlabel2982: ;
52481: return 16;
52482: }
52483: unsigned long REGPARAM2 CPUFUNC(op_5070_5)(uae_u32 opcode) /* ADD */
52484: {
52485: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52486: uae_u32 dstreg = opcode & 7;
52487: OpcodeFamily = 11; CurrentInstrCycles = 18;
52488: {{ uae_u32 src = srcreg;
52489: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
52490: BusCyclePenalty += 2;
52491: if ((dsta & 1) != 0) {
52492: last_fault_for_exception_3 = dsta;
52493: last_op_for_exception_3 = opcode;
52494: last_addr_for_exception_3 = m68k_getpc() + 4;
52495: Exception(3, 0, M68000_EXC_SRC_CPU);
52496: goto endlabel2983;
52497: }
52498: {{ uae_s16 dst = get_word(dsta);
52499: { refill_prefetch (m68k_getpc(), 2);
52500: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
52501: { int flgs = ((uae_s16)(src)) < 0;
52502: int flgo = ((uae_s16)(dst)) < 0;
52503: int flgn = ((uae_s16)(newv)) < 0;
52504: SET_ZFLG (((uae_s16)(newv)) == 0);
52505: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52506: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
52507: COPY_CARRY;
52508: SET_NFLG (flgn != 0);
52509: m68k_incpc(4);
52510: fill_prefetch_0 ();
52511: put_word(dsta,newv);
52512: }}}}}}}}endlabel2983: ;
52513: return 18;
52514: }
52515: unsigned long REGPARAM2 CPUFUNC(op_5078_5)(uae_u32 opcode) /* ADD */
52516: {
52517: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52518: OpcodeFamily = 11; CurrentInstrCycles = 16;
52519: {{ uae_u32 src = srcreg;
52520: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
52521: if ((dsta & 1) != 0) {
52522: last_fault_for_exception_3 = dsta;
52523: last_op_for_exception_3 = opcode;
52524: last_addr_for_exception_3 = m68k_getpc() + 4;
52525: Exception(3, 0, M68000_EXC_SRC_CPU);
52526: goto endlabel2984;
52527: }
52528: {{ uae_s16 dst = get_word(dsta);
52529: { refill_prefetch (m68k_getpc(), 2);
52530: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
52531: { int flgs = ((uae_s16)(src)) < 0;
52532: int flgo = ((uae_s16)(dst)) < 0;
52533: int flgn = ((uae_s16)(newv)) < 0;
52534: SET_ZFLG (((uae_s16)(newv)) == 0);
52535: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52536: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
52537: COPY_CARRY;
52538: SET_NFLG (flgn != 0);
52539: m68k_incpc(4);
52540: fill_prefetch_0 ();
52541: put_word(dsta,newv);
52542: }}}}}}}}endlabel2984: ;
52543: return 16;
52544: }
52545: unsigned long REGPARAM2 CPUFUNC(op_5079_5)(uae_u32 opcode) /* ADD */
52546: {
52547: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52548: OpcodeFamily = 11; CurrentInstrCycles = 20;
52549: {{ uae_u32 src = srcreg;
52550: { uaecptr dsta = get_ilong_prefetch(2);
52551: if ((dsta & 1) != 0) {
52552: last_fault_for_exception_3 = dsta;
52553: last_op_for_exception_3 = opcode;
52554: last_addr_for_exception_3 = m68k_getpc() + 6;
52555: Exception(3, 0, M68000_EXC_SRC_CPU);
52556: goto endlabel2985;
52557: }
52558: {{ uae_s16 dst = get_word(dsta);
52559: { refill_prefetch (m68k_getpc(), 2);
52560: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
52561: { int flgs = ((uae_s16)(src)) < 0;
52562: int flgo = ((uae_s16)(dst)) < 0;
52563: int flgn = ((uae_s16)(newv)) < 0;
52564: SET_ZFLG (((uae_s16)(newv)) == 0);
52565: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52566: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
52567: COPY_CARRY;
52568: SET_NFLG (flgn != 0);
52569: m68k_incpc(6);
52570: fill_prefetch_0 ();
52571: put_word(dsta,newv);
52572: }}}}}}}}endlabel2985: ;
52573: return 20;
52574: }
52575: unsigned long REGPARAM2 CPUFUNC(op_5080_5)(uae_u32 opcode) /* ADD */
52576: {
52577: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52578: uae_u32 dstreg = opcode & 7;
52579: OpcodeFamily = 11; CurrentInstrCycles = 8;
52580: {{ uae_u32 src = srcreg;
52581: { uae_s32 dst = m68k_dreg(regs, dstreg);
52582: { refill_prefetch (m68k_getpc(), 2);
52583: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
52584: { int flgs = ((uae_s32)(src)) < 0;
52585: int flgo = ((uae_s32)(dst)) < 0;
52586: int flgn = ((uae_s32)(newv)) < 0;
52587: SET_ZFLG (((uae_s32)(newv)) == 0);
52588: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52589: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
52590: COPY_CARRY;
52591: SET_NFLG (flgn != 0);
52592: m68k_dreg(regs, dstreg) = (newv);
52593: }}}}}}m68k_incpc(2);
52594: fill_prefetch_2 ();
52595: return 8;
52596: }
52597: unsigned long REGPARAM2 CPUFUNC(op_5088_5)(uae_u32 opcode) /* ADDA */
52598: {
52599: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52600: uae_u32 dstreg = opcode & 7;
52601: OpcodeFamily = 12; CurrentInstrCycles = 8;
52602: {{ uae_u32 src = srcreg;
52603: { uae_s32 dst = m68k_areg(regs, dstreg);
52604: { uae_u32 newv = dst + src;
52605: m68k_areg(regs, dstreg) = (newv);
52606: }}}}m68k_incpc(2);
52607: fill_prefetch_2 ();
52608: return 8;
52609: }
52610: unsigned long REGPARAM2 CPUFUNC(op_5090_5)(uae_u32 opcode) /* ADD */
52611: {
52612: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52613: uae_u32 dstreg = opcode & 7;
52614: OpcodeFamily = 11; CurrentInstrCycles = 20;
52615: {{ uae_u32 src = srcreg;
52616: { uaecptr dsta = m68k_areg(regs, dstreg);
52617: if ((dsta & 1) != 0) {
52618: last_fault_for_exception_3 = dsta;
52619: last_op_for_exception_3 = opcode;
52620: last_addr_for_exception_3 = m68k_getpc() + 2;
52621: Exception(3, 0, M68000_EXC_SRC_CPU);
52622: goto endlabel2988;
52623: }
52624: {{ uae_s32 dst = get_long(dsta);
52625: { refill_prefetch (m68k_getpc(), 2);
52626: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
52627: { int flgs = ((uae_s32)(src)) < 0;
52628: int flgo = ((uae_s32)(dst)) < 0;
52629: int flgn = ((uae_s32)(newv)) < 0;
52630: SET_ZFLG (((uae_s32)(newv)) == 0);
52631: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52632: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
52633: COPY_CARRY;
52634: SET_NFLG (flgn != 0);
52635: m68k_incpc(2);
52636: fill_prefetch_2 ();
52637: put_long(dsta,newv);
52638: }}}}}}}}endlabel2988: ;
52639: return 20;
52640: }
52641: unsigned long REGPARAM2 CPUFUNC(op_5098_5)(uae_u32 opcode) /* ADD */
52642: {
52643: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52644: uae_u32 dstreg = opcode & 7;
52645: OpcodeFamily = 11; CurrentInstrCycles = 20;
52646: {{ uae_u32 src = srcreg;
52647: { uaecptr dsta = m68k_areg(regs, dstreg);
52648: if ((dsta & 1) != 0) {
52649: last_fault_for_exception_3 = dsta;
52650: last_op_for_exception_3 = opcode;
52651: last_addr_for_exception_3 = m68k_getpc() + 2;
52652: Exception(3, 0, M68000_EXC_SRC_CPU);
52653: goto endlabel2989;
52654: }
52655: {{ uae_s32 dst = get_long(dsta);
52656: m68k_areg(regs, dstreg) += 4;
52657: { refill_prefetch (m68k_getpc(), 2);
52658: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
52659: { int flgs = ((uae_s32)(src)) < 0;
52660: int flgo = ((uae_s32)(dst)) < 0;
52661: int flgn = ((uae_s32)(newv)) < 0;
52662: SET_ZFLG (((uae_s32)(newv)) == 0);
52663: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52664: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
52665: COPY_CARRY;
52666: SET_NFLG (flgn != 0);
52667: m68k_incpc(2);
52668: fill_prefetch_2 ();
52669: put_long(dsta,newv);
52670: }}}}}}}}endlabel2989: ;
52671: return 20;
52672: }
52673: unsigned long REGPARAM2 CPUFUNC(op_50a0_5)(uae_u32 opcode) /* ADD */
52674: {
52675: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52676: uae_u32 dstreg = opcode & 7;
52677: OpcodeFamily = 11; CurrentInstrCycles = 22;
52678: {{ uae_u32 src = srcreg;
52679: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
52680: if ((dsta & 1) != 0) {
52681: last_fault_for_exception_3 = dsta;
52682: last_op_for_exception_3 = opcode;
52683: last_addr_for_exception_3 = m68k_getpc() + 2;
52684: Exception(3, 0, M68000_EXC_SRC_CPU);
52685: goto endlabel2990;
52686: }
52687: {{ uae_s32 dst = get_long(dsta);
52688: m68k_areg (regs, dstreg) = dsta;
52689: { refill_prefetch (m68k_getpc(), 2);
52690: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
52691: { int flgs = ((uae_s32)(src)) < 0;
52692: int flgo = ((uae_s32)(dst)) < 0;
52693: int flgn = ((uae_s32)(newv)) < 0;
52694: SET_ZFLG (((uae_s32)(newv)) == 0);
52695: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52696: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
52697: COPY_CARRY;
52698: SET_NFLG (flgn != 0);
52699: m68k_incpc(2);
52700: fill_prefetch_2 ();
52701: put_long(dsta,newv);
52702: }}}}}}}}endlabel2990: ;
52703: return 22;
52704: }
52705: unsigned long REGPARAM2 CPUFUNC(op_50a8_5)(uae_u32 opcode) /* ADD */
52706: {
52707: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52708: uae_u32 dstreg = opcode & 7;
52709: OpcodeFamily = 11; CurrentInstrCycles = 24;
52710: {{ uae_u32 src = srcreg;
52711: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
52712: if ((dsta & 1) != 0) {
52713: last_fault_for_exception_3 = dsta;
52714: last_op_for_exception_3 = opcode;
52715: last_addr_for_exception_3 = m68k_getpc() + 4;
52716: Exception(3, 0, M68000_EXC_SRC_CPU);
52717: goto endlabel2991;
52718: }
52719: {{ uae_s32 dst = get_long(dsta);
52720: { refill_prefetch (m68k_getpc(), 2);
52721: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
52722: { int flgs = ((uae_s32)(src)) < 0;
52723: int flgo = ((uae_s32)(dst)) < 0;
52724: int flgn = ((uae_s32)(newv)) < 0;
52725: SET_ZFLG (((uae_s32)(newv)) == 0);
52726: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52727: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
52728: COPY_CARRY;
52729: SET_NFLG (flgn != 0);
52730: m68k_incpc(4);
52731: fill_prefetch_0 ();
52732: put_long(dsta,newv);
52733: }}}}}}}}endlabel2991: ;
52734: return 24;
52735: }
52736: unsigned long REGPARAM2 CPUFUNC(op_50b0_5)(uae_u32 opcode) /* ADD */
52737: {
52738: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52739: uae_u32 dstreg = opcode & 7;
52740: OpcodeFamily = 11; CurrentInstrCycles = 26;
52741: {{ uae_u32 src = srcreg;
52742: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
52743: BusCyclePenalty += 2;
52744: if ((dsta & 1) != 0) {
52745: last_fault_for_exception_3 = dsta;
52746: last_op_for_exception_3 = opcode;
52747: last_addr_for_exception_3 = m68k_getpc() + 4;
52748: Exception(3, 0, M68000_EXC_SRC_CPU);
52749: goto endlabel2992;
52750: }
52751: {{ uae_s32 dst = get_long(dsta);
52752: { refill_prefetch (m68k_getpc(), 2);
52753: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
52754: { int flgs = ((uae_s32)(src)) < 0;
52755: int flgo = ((uae_s32)(dst)) < 0;
52756: int flgn = ((uae_s32)(newv)) < 0;
52757: SET_ZFLG (((uae_s32)(newv)) == 0);
52758: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52759: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
52760: COPY_CARRY;
52761: SET_NFLG (flgn != 0);
52762: m68k_incpc(4);
52763: fill_prefetch_0 ();
52764: put_long(dsta,newv);
52765: }}}}}}}}endlabel2992: ;
52766: return 26;
52767: }
52768: unsigned long REGPARAM2 CPUFUNC(op_50b8_5)(uae_u32 opcode) /* ADD */
52769: {
52770: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52771: OpcodeFamily = 11; CurrentInstrCycles = 24;
52772: {{ uae_u32 src = srcreg;
52773: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
52774: if ((dsta & 1) != 0) {
52775: last_fault_for_exception_3 = dsta;
52776: last_op_for_exception_3 = opcode;
52777: last_addr_for_exception_3 = m68k_getpc() + 4;
52778: Exception(3, 0, M68000_EXC_SRC_CPU);
52779: goto endlabel2993;
52780: }
52781: {{ uae_s32 dst = get_long(dsta);
52782: { refill_prefetch (m68k_getpc(), 2);
52783: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
52784: { int flgs = ((uae_s32)(src)) < 0;
52785: int flgo = ((uae_s32)(dst)) < 0;
52786: int flgn = ((uae_s32)(newv)) < 0;
52787: SET_ZFLG (((uae_s32)(newv)) == 0);
52788: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52789: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
52790: COPY_CARRY;
52791: SET_NFLG (flgn != 0);
52792: m68k_incpc(4);
52793: fill_prefetch_0 ();
52794: put_long(dsta,newv);
52795: }}}}}}}}endlabel2993: ;
52796: return 24;
52797: }
52798: unsigned long REGPARAM2 CPUFUNC(op_50b9_5)(uae_u32 opcode) /* ADD */
52799: {
52800: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52801: OpcodeFamily = 11; CurrentInstrCycles = 28;
52802: {{ uae_u32 src = srcreg;
52803: { uaecptr dsta = get_ilong_prefetch(2);
52804: if ((dsta & 1) != 0) {
52805: last_fault_for_exception_3 = dsta;
52806: last_op_for_exception_3 = opcode;
52807: last_addr_for_exception_3 = m68k_getpc() + 6;
52808: Exception(3, 0, M68000_EXC_SRC_CPU);
52809: goto endlabel2994;
52810: }
52811: {{ uae_s32 dst = get_long(dsta);
52812: { refill_prefetch (m68k_getpc(), 2);
52813: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
52814: { int flgs = ((uae_s32)(src)) < 0;
52815: int flgo = ((uae_s32)(dst)) < 0;
52816: int flgn = ((uae_s32)(newv)) < 0;
52817: SET_ZFLG (((uae_s32)(newv)) == 0);
52818: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
52819: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
52820: COPY_CARRY;
52821: SET_NFLG (flgn != 0);
52822: m68k_incpc(6);
52823: fill_prefetch_0 ();
52824: put_long(dsta,newv);
52825: }}}}}}}}endlabel2994: ;
52826: return 28;
52827: }
52828: unsigned long REGPARAM2 CPUFUNC(op_50c0_5)(uae_u32 opcode) /* Scc */
52829: {
52830: uae_u32 srcreg = (opcode & 7);
52831: OpcodeFamily = 59; CurrentInstrCycles = 4;
52832: {{{ int val = cctrue(0) ? 0xff : 0;
52833: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
52834: if (val) { m68k_incpc(2) ; return 4+2; }
52835: }}}m68k_incpc(2);
52836: fill_prefetch_2 ();
52837: return 4;
52838: }
52839: unsigned long REGPARAM2 CPUFUNC(op_50c8_5)(uae_u32 opcode) /* DBcc */
52840: {
52841: uae_u32 srcreg = (opcode & 7);
52842: OpcodeFamily = 58; CurrentInstrCycles = 12;
52843: {{ uae_s16 src = m68k_dreg(regs, srcreg);
52844: { uae_s16 offs = get_iword_prefetch(2);
52845: if (!cctrue(0)) {
52846: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
52847: if (src) {
52848: if (offs & 1) {
52849: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
52850: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
52851: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2996;
52852: }
52853: m68k_incpc((uae_s32)offs + 2);
52854: fill_prefetch_0 ();
52855: return 10;
52856: } else {
52857: m68k_incpc(4);
52858: fill_prefetch_0 ();
52859: return 14;
52860: }
52861: }
52862: }}}m68k_incpc(4);
52863: fill_prefetch_0 ();
52864: endlabel2996: ;
52865: return 12;
52866: }
52867: unsigned long REGPARAM2 CPUFUNC(op_50d0_5)(uae_u32 opcode) /* Scc */
52868: {
52869: uae_u32 srcreg = (opcode & 7);
52870: OpcodeFamily = 59; CurrentInstrCycles = 12;
52871: {{ uaecptr srca = m68k_areg(regs, srcreg);
52872: { int val = cctrue(0) ? 0xff : 0;
52873: m68k_incpc(2);
52874: fill_prefetch_2 ();
52875: put_byte(srca,val);
52876: }}}return 12;
52877: }
52878: unsigned long REGPARAM2 CPUFUNC(op_50d8_5)(uae_u32 opcode) /* Scc */
52879: {
52880: uae_u32 srcreg = (opcode & 7);
52881: OpcodeFamily = 59; CurrentInstrCycles = 12;
52882: {{ uaecptr srca = m68k_areg(regs, srcreg);
52883: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
52884: { int val = cctrue(0) ? 0xff : 0;
52885: m68k_incpc(2);
52886: fill_prefetch_2 ();
52887: put_byte(srca,val);
52888: }}}return 12;
52889: }
52890: unsigned long REGPARAM2 CPUFUNC(op_50e0_5)(uae_u32 opcode) /* Scc */
52891: {
52892: uae_u32 srcreg = (opcode & 7);
52893: OpcodeFamily = 59; CurrentInstrCycles = 14;
52894: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
52895: m68k_areg (regs, srcreg) = srca;
52896: { int val = cctrue(0) ? 0xff : 0;
52897: m68k_incpc(2);
52898: fill_prefetch_2 ();
52899: put_byte(srca,val);
52900: }}}return 14;
52901: }
52902: unsigned long REGPARAM2 CPUFUNC(op_50e8_5)(uae_u32 opcode) /* Scc */
52903: {
52904: uae_u32 srcreg = (opcode & 7);
52905: OpcodeFamily = 59; CurrentInstrCycles = 16;
52906: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
52907: { int val = cctrue(0) ? 0xff : 0;
52908: m68k_incpc(4);
52909: fill_prefetch_0 ();
52910: put_byte(srca,val);
52911: }}}return 16;
52912: }
52913: unsigned long REGPARAM2 CPUFUNC(op_50f0_5)(uae_u32 opcode) /* Scc */
52914: {
52915: uae_u32 srcreg = (opcode & 7);
52916: OpcodeFamily = 59; CurrentInstrCycles = 18;
52917: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
52918: BusCyclePenalty += 2;
52919: { int val = cctrue(0) ? 0xff : 0;
52920: m68k_incpc(4);
52921: fill_prefetch_0 ();
52922: put_byte(srca,val);
52923: }}}return 18;
52924: }
52925: unsigned long REGPARAM2 CPUFUNC(op_50f8_5)(uae_u32 opcode) /* Scc */
52926: {
52927: OpcodeFamily = 59; CurrentInstrCycles = 16;
52928: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
52929: { int val = cctrue(0) ? 0xff : 0;
52930: m68k_incpc(4);
52931: fill_prefetch_0 ();
52932: put_byte(srca,val);
52933: }}}return 16;
52934: }
52935: unsigned long REGPARAM2 CPUFUNC(op_50f9_5)(uae_u32 opcode) /* Scc */
52936: {
52937: OpcodeFamily = 59; CurrentInstrCycles = 20;
52938: {{ uaecptr srca = get_ilong_prefetch(2);
52939: { int val = cctrue(0) ? 0xff : 0;
52940: m68k_incpc(6);
52941: fill_prefetch_0 ();
52942: put_byte(srca,val);
52943: }}}return 20;
52944: }
52945: unsigned long REGPARAM2 CPUFUNC(op_5100_5)(uae_u32 opcode) /* SUB */
52946: {
52947: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52948: uae_u32 dstreg = opcode & 7;
52949: OpcodeFamily = 7; CurrentInstrCycles = 4;
52950: {{ uae_u32 src = srcreg;
52951: { uae_s8 dst = m68k_dreg(regs, dstreg);
52952: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
52953: { int flgs = ((uae_s8)(src)) < 0;
52954: int flgo = ((uae_s8)(dst)) < 0;
52955: int flgn = ((uae_s8)(newv)) < 0;
52956: SET_ZFLG (((uae_s8)(newv)) == 0);
52957: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
52958: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
52959: COPY_CARRY;
52960: SET_NFLG (flgn != 0);
52961: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
52962: }}}}}}m68k_incpc(2);
52963: fill_prefetch_2 ();
52964: return 4;
52965: }
52966: unsigned long REGPARAM2 CPUFUNC(op_5110_5)(uae_u32 opcode) /* SUB */
52967: {
52968: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52969: uae_u32 dstreg = opcode & 7;
52970: OpcodeFamily = 7; CurrentInstrCycles = 12;
52971: {{ uae_u32 src = srcreg;
52972: { uaecptr dsta = m68k_areg(regs, dstreg);
52973: { uae_s8 dst = get_byte(dsta);
52974: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
52975: { int flgs = ((uae_s8)(src)) < 0;
52976: int flgo = ((uae_s8)(dst)) < 0;
52977: int flgn = ((uae_s8)(newv)) < 0;
52978: SET_ZFLG (((uae_s8)(newv)) == 0);
52979: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
52980: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
52981: COPY_CARRY;
52982: SET_NFLG (flgn != 0);
52983: m68k_incpc(2);
52984: fill_prefetch_2 ();
52985: put_byte(dsta,newv);
52986: }}}}}}}return 12;
52987: }
52988: unsigned long REGPARAM2 CPUFUNC(op_5118_5)(uae_u32 opcode) /* SUB */
52989: {
52990: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
52991: uae_u32 dstreg = opcode & 7;
52992: OpcodeFamily = 7; CurrentInstrCycles = 12;
52993: {{ uae_u32 src = srcreg;
52994: { uaecptr dsta = m68k_areg(regs, dstreg);
52995: { uae_s8 dst = get_byte(dsta);
52996: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
52997: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
52998: { int flgs = ((uae_s8)(src)) < 0;
52999: int flgo = ((uae_s8)(dst)) < 0;
53000: int flgn = ((uae_s8)(newv)) < 0;
53001: SET_ZFLG (((uae_s8)(newv)) == 0);
53002: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53003: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
53004: COPY_CARRY;
53005: SET_NFLG (flgn != 0);
53006: m68k_incpc(2);
53007: fill_prefetch_2 ();
53008: put_byte(dsta,newv);
53009: }}}}}}}return 12;
53010: }
53011: unsigned long REGPARAM2 CPUFUNC(op_5120_5)(uae_u32 opcode) /* SUB */
53012: {
53013: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53014: uae_u32 dstreg = opcode & 7;
53015: OpcodeFamily = 7; CurrentInstrCycles = 14;
53016: {{ uae_u32 src = srcreg;
53017: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
53018: { uae_s8 dst = get_byte(dsta);
53019: m68k_areg (regs, dstreg) = dsta;
53020: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
53021: { int flgs = ((uae_s8)(src)) < 0;
53022: int flgo = ((uae_s8)(dst)) < 0;
53023: int flgn = ((uae_s8)(newv)) < 0;
53024: SET_ZFLG (((uae_s8)(newv)) == 0);
53025: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53026: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
53027: COPY_CARRY;
53028: SET_NFLG (flgn != 0);
53029: m68k_incpc(2);
53030: fill_prefetch_2 ();
53031: put_byte(dsta,newv);
53032: }}}}}}}return 14;
53033: }
53034: unsigned long REGPARAM2 CPUFUNC(op_5128_5)(uae_u32 opcode) /* SUB */
53035: {
53036: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53037: uae_u32 dstreg = opcode & 7;
53038: OpcodeFamily = 7; CurrentInstrCycles = 16;
53039: {{ uae_u32 src = srcreg;
53040: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
53041: { uae_s8 dst = get_byte(dsta);
53042: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
53043: { int flgs = ((uae_s8)(src)) < 0;
53044: int flgo = ((uae_s8)(dst)) < 0;
53045: int flgn = ((uae_s8)(newv)) < 0;
53046: SET_ZFLG (((uae_s8)(newv)) == 0);
53047: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53048: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
53049: COPY_CARRY;
53050: SET_NFLG (flgn != 0);
53051: m68k_incpc(4);
53052: fill_prefetch_0 ();
53053: put_byte(dsta,newv);
53054: }}}}}}}return 16;
53055: }
53056: unsigned long REGPARAM2 CPUFUNC(op_5130_5)(uae_u32 opcode) /* SUB */
53057: {
53058: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53059: uae_u32 dstreg = opcode & 7;
53060: OpcodeFamily = 7; CurrentInstrCycles = 18;
53061: {{ uae_u32 src = srcreg;
53062: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
53063: BusCyclePenalty += 2;
53064: { uae_s8 dst = get_byte(dsta);
53065: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
53066: { int flgs = ((uae_s8)(src)) < 0;
53067: int flgo = ((uae_s8)(dst)) < 0;
53068: int flgn = ((uae_s8)(newv)) < 0;
53069: SET_ZFLG (((uae_s8)(newv)) == 0);
53070: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53071: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
53072: COPY_CARRY;
53073: SET_NFLG (flgn != 0);
53074: m68k_incpc(4);
53075: fill_prefetch_0 ();
53076: put_byte(dsta,newv);
53077: }}}}}}}return 18;
53078: }
53079: unsigned long REGPARAM2 CPUFUNC(op_5138_5)(uae_u32 opcode) /* SUB */
53080: {
53081: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53082: OpcodeFamily = 7; CurrentInstrCycles = 16;
53083: {{ uae_u32 src = srcreg;
53084: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
53085: { uae_s8 dst = get_byte(dsta);
53086: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
53087: { int flgs = ((uae_s8)(src)) < 0;
53088: int flgo = ((uae_s8)(dst)) < 0;
53089: int flgn = ((uae_s8)(newv)) < 0;
53090: SET_ZFLG (((uae_s8)(newv)) == 0);
53091: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53092: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
53093: COPY_CARRY;
53094: SET_NFLG (flgn != 0);
53095: m68k_incpc(4);
53096: fill_prefetch_0 ();
53097: put_byte(dsta,newv);
53098: }}}}}}}return 16;
53099: }
53100: unsigned long REGPARAM2 CPUFUNC(op_5139_5)(uae_u32 opcode) /* SUB */
53101: {
53102: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53103: OpcodeFamily = 7; CurrentInstrCycles = 20;
53104: {{ uae_u32 src = srcreg;
53105: { uaecptr dsta = get_ilong_prefetch(2);
53106: { uae_s8 dst = get_byte(dsta);
53107: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
53108: { int flgs = ((uae_s8)(src)) < 0;
53109: int flgo = ((uae_s8)(dst)) < 0;
53110: int flgn = ((uae_s8)(newv)) < 0;
53111: SET_ZFLG (((uae_s8)(newv)) == 0);
53112: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53113: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
53114: COPY_CARRY;
53115: SET_NFLG (flgn != 0);
53116: m68k_incpc(6);
53117: fill_prefetch_0 ();
53118: put_byte(dsta,newv);
53119: }}}}}}}return 20;
53120: }
53121: unsigned long REGPARAM2 CPUFUNC(op_5140_5)(uae_u32 opcode) /* SUB */
53122: {
53123: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53124: uae_u32 dstreg = opcode & 7;
53125: OpcodeFamily = 7; CurrentInstrCycles = 4;
53126: {{ uae_u32 src = srcreg;
53127: { uae_s16 dst = m68k_dreg(regs, dstreg);
53128: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
53129: { int flgs = ((uae_s16)(src)) < 0;
53130: int flgo = ((uae_s16)(dst)) < 0;
53131: int flgn = ((uae_s16)(newv)) < 0;
53132: SET_ZFLG (((uae_s16)(newv)) == 0);
53133: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53134: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
53135: COPY_CARRY;
53136: SET_NFLG (flgn != 0);
53137: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
53138: }}}}}}m68k_incpc(2);
53139: fill_prefetch_2 ();
53140: return 4;
53141: }
53142: unsigned long REGPARAM2 CPUFUNC(op_5148_5)(uae_u32 opcode) /* SUBA */
53143: {
53144: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53145: uae_u32 dstreg = opcode & 7;
53146: OpcodeFamily = 8; CurrentInstrCycles = 8;
53147: {{ uae_u32 src = srcreg;
53148: { uae_s32 dst = m68k_areg(regs, dstreg);
53149: { uae_u32 newv = dst - src;
53150: m68k_areg(regs, dstreg) = (newv);
53151: }}}}m68k_incpc(2);
53152: fill_prefetch_2 ();
53153: return 8;
53154: }
53155: unsigned long REGPARAM2 CPUFUNC(op_5150_5)(uae_u32 opcode) /* SUB */
53156: {
53157: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53158: uae_u32 dstreg = opcode & 7;
53159: OpcodeFamily = 7; CurrentInstrCycles = 12;
53160: {{ uae_u32 src = srcreg;
53161: { uaecptr dsta = m68k_areg(regs, dstreg);
53162: if ((dsta & 1) != 0) {
53163: last_fault_for_exception_3 = dsta;
53164: last_op_for_exception_3 = opcode;
53165: last_addr_for_exception_3 = m68k_getpc() + 2;
53166: Exception(3, 0, M68000_EXC_SRC_CPU);
53167: goto endlabel3014;
53168: }
53169: {{ uae_s16 dst = get_word(dsta);
53170: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
53171: { int flgs = ((uae_s16)(src)) < 0;
53172: int flgo = ((uae_s16)(dst)) < 0;
53173: int flgn = ((uae_s16)(newv)) < 0;
53174: SET_ZFLG (((uae_s16)(newv)) == 0);
53175: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53176: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
53177: COPY_CARRY;
53178: SET_NFLG (flgn != 0);
53179: m68k_incpc(2);
53180: fill_prefetch_2 ();
53181: put_word(dsta,newv);
53182: }}}}}}}}endlabel3014: ;
53183: return 12;
53184: }
53185: unsigned long REGPARAM2 CPUFUNC(op_5158_5)(uae_u32 opcode) /* SUB */
53186: {
53187: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53188: uae_u32 dstreg = opcode & 7;
53189: OpcodeFamily = 7; CurrentInstrCycles = 12;
53190: {{ uae_u32 src = srcreg;
53191: { uaecptr dsta = m68k_areg(regs, dstreg);
53192: if ((dsta & 1) != 0) {
53193: last_fault_for_exception_3 = dsta;
53194: last_op_for_exception_3 = opcode;
53195: last_addr_for_exception_3 = m68k_getpc() + 2;
53196: Exception(3, 0, M68000_EXC_SRC_CPU);
53197: goto endlabel3015;
53198: }
53199: {{ uae_s16 dst = get_word(dsta);
53200: m68k_areg(regs, dstreg) += 2;
53201: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
53202: { int flgs = ((uae_s16)(src)) < 0;
53203: int flgo = ((uae_s16)(dst)) < 0;
53204: int flgn = ((uae_s16)(newv)) < 0;
53205: SET_ZFLG (((uae_s16)(newv)) == 0);
53206: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53207: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
53208: COPY_CARRY;
53209: SET_NFLG (flgn != 0);
53210: m68k_incpc(2);
53211: fill_prefetch_2 ();
53212: put_word(dsta,newv);
53213: }}}}}}}}endlabel3015: ;
53214: return 12;
53215: }
53216: unsigned long REGPARAM2 CPUFUNC(op_5160_5)(uae_u32 opcode) /* SUB */
53217: {
53218: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53219: uae_u32 dstreg = opcode & 7;
53220: OpcodeFamily = 7; CurrentInstrCycles = 14;
53221: {{ uae_u32 src = srcreg;
53222: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
53223: if ((dsta & 1) != 0) {
53224: last_fault_for_exception_3 = dsta;
53225: last_op_for_exception_3 = opcode;
53226: last_addr_for_exception_3 = m68k_getpc() + 2;
53227: Exception(3, 0, M68000_EXC_SRC_CPU);
53228: goto endlabel3016;
53229: }
53230: {{ uae_s16 dst = get_word(dsta);
53231: m68k_areg (regs, dstreg) = dsta;
53232: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
53233: { int flgs = ((uae_s16)(src)) < 0;
53234: int flgo = ((uae_s16)(dst)) < 0;
53235: int flgn = ((uae_s16)(newv)) < 0;
53236: SET_ZFLG (((uae_s16)(newv)) == 0);
53237: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53238: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
53239: COPY_CARRY;
53240: SET_NFLG (flgn != 0);
53241: m68k_incpc(2);
53242: fill_prefetch_2 ();
53243: put_word(dsta,newv);
53244: }}}}}}}}endlabel3016: ;
53245: return 14;
53246: }
53247: unsigned long REGPARAM2 CPUFUNC(op_5168_5)(uae_u32 opcode) /* SUB */
53248: {
53249: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53250: uae_u32 dstreg = opcode & 7;
53251: OpcodeFamily = 7; CurrentInstrCycles = 16;
53252: {{ uae_u32 src = srcreg;
53253: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
53254: if ((dsta & 1) != 0) {
53255: last_fault_for_exception_3 = dsta;
53256: last_op_for_exception_3 = opcode;
53257: last_addr_for_exception_3 = m68k_getpc() + 4;
53258: Exception(3, 0, M68000_EXC_SRC_CPU);
53259: goto endlabel3017;
53260: }
53261: {{ uae_s16 dst = get_word(dsta);
53262: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
53263: { int flgs = ((uae_s16)(src)) < 0;
53264: int flgo = ((uae_s16)(dst)) < 0;
53265: int flgn = ((uae_s16)(newv)) < 0;
53266: SET_ZFLG (((uae_s16)(newv)) == 0);
53267: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53268: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
53269: COPY_CARRY;
53270: SET_NFLG (flgn != 0);
53271: m68k_incpc(4);
53272: fill_prefetch_0 ();
53273: put_word(dsta,newv);
53274: }}}}}}}}endlabel3017: ;
53275: return 16;
53276: }
53277: unsigned long REGPARAM2 CPUFUNC(op_5170_5)(uae_u32 opcode) /* SUB */
53278: {
53279: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53280: uae_u32 dstreg = opcode & 7;
53281: OpcodeFamily = 7; CurrentInstrCycles = 18;
53282: {{ uae_u32 src = srcreg;
53283: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
53284: BusCyclePenalty += 2;
53285: if ((dsta & 1) != 0) {
53286: last_fault_for_exception_3 = dsta;
53287: last_op_for_exception_3 = opcode;
53288: last_addr_for_exception_3 = m68k_getpc() + 4;
53289: Exception(3, 0, M68000_EXC_SRC_CPU);
53290: goto endlabel3018;
53291: }
53292: {{ uae_s16 dst = get_word(dsta);
53293: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
53294: { int flgs = ((uae_s16)(src)) < 0;
53295: int flgo = ((uae_s16)(dst)) < 0;
53296: int flgn = ((uae_s16)(newv)) < 0;
53297: SET_ZFLG (((uae_s16)(newv)) == 0);
53298: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53299: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
53300: COPY_CARRY;
53301: SET_NFLG (flgn != 0);
53302: m68k_incpc(4);
53303: fill_prefetch_0 ();
53304: put_word(dsta,newv);
53305: }}}}}}}}endlabel3018: ;
53306: return 18;
53307: }
53308: unsigned long REGPARAM2 CPUFUNC(op_5178_5)(uae_u32 opcode) /* SUB */
53309: {
53310: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53311: OpcodeFamily = 7; CurrentInstrCycles = 16;
53312: {{ uae_u32 src = srcreg;
53313: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
53314: if ((dsta & 1) != 0) {
53315: last_fault_for_exception_3 = dsta;
53316: last_op_for_exception_3 = opcode;
53317: last_addr_for_exception_3 = m68k_getpc() + 4;
53318: Exception(3, 0, M68000_EXC_SRC_CPU);
53319: goto endlabel3019;
53320: }
53321: {{ uae_s16 dst = get_word(dsta);
53322: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
53323: { int flgs = ((uae_s16)(src)) < 0;
53324: int flgo = ((uae_s16)(dst)) < 0;
53325: int flgn = ((uae_s16)(newv)) < 0;
53326: SET_ZFLG (((uae_s16)(newv)) == 0);
53327: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53328: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
53329: COPY_CARRY;
53330: SET_NFLG (flgn != 0);
53331: m68k_incpc(4);
53332: fill_prefetch_0 ();
53333: put_word(dsta,newv);
53334: }}}}}}}}endlabel3019: ;
53335: return 16;
53336: }
53337: unsigned long REGPARAM2 CPUFUNC(op_5179_5)(uae_u32 opcode) /* SUB */
53338: {
53339: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53340: OpcodeFamily = 7; CurrentInstrCycles = 20;
53341: {{ uae_u32 src = srcreg;
53342: { uaecptr dsta = get_ilong_prefetch(2);
53343: if ((dsta & 1) != 0) {
53344: last_fault_for_exception_3 = dsta;
53345: last_op_for_exception_3 = opcode;
53346: last_addr_for_exception_3 = m68k_getpc() + 6;
53347: Exception(3, 0, M68000_EXC_SRC_CPU);
53348: goto endlabel3020;
53349: }
53350: {{ uae_s16 dst = get_word(dsta);
53351: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
53352: { int flgs = ((uae_s16)(src)) < 0;
53353: int flgo = ((uae_s16)(dst)) < 0;
53354: int flgn = ((uae_s16)(newv)) < 0;
53355: SET_ZFLG (((uae_s16)(newv)) == 0);
53356: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53357: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
53358: COPY_CARRY;
53359: SET_NFLG (flgn != 0);
53360: m68k_incpc(6);
53361: fill_prefetch_0 ();
53362: put_word(dsta,newv);
53363: }}}}}}}}endlabel3020: ;
53364: return 20;
53365: }
53366: unsigned long REGPARAM2 CPUFUNC(op_5180_5)(uae_u32 opcode) /* SUB */
53367: {
53368: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53369: uae_u32 dstreg = opcode & 7;
53370: OpcodeFamily = 7; CurrentInstrCycles = 8;
53371: {{ uae_u32 src = srcreg;
53372: { uae_s32 dst = m68k_dreg(regs, dstreg);
53373: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
53374: { int flgs = ((uae_s32)(src)) < 0;
53375: int flgo = ((uae_s32)(dst)) < 0;
53376: int flgn = ((uae_s32)(newv)) < 0;
53377: SET_ZFLG (((uae_s32)(newv)) == 0);
53378: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53379: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
53380: COPY_CARRY;
53381: SET_NFLG (flgn != 0);
53382: m68k_dreg(regs, dstreg) = (newv);
53383: }}}}}}m68k_incpc(2);
53384: fill_prefetch_2 ();
53385: return 8;
53386: }
53387: unsigned long REGPARAM2 CPUFUNC(op_5188_5)(uae_u32 opcode) /* SUBA */
53388: {
53389: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53390: uae_u32 dstreg = opcode & 7;
53391: OpcodeFamily = 8; CurrentInstrCycles = 8;
53392: {{ uae_u32 src = srcreg;
53393: { uae_s32 dst = m68k_areg(regs, dstreg);
53394: { uae_u32 newv = dst - src;
53395: m68k_areg(regs, dstreg) = (newv);
53396: }}}}m68k_incpc(2);
53397: fill_prefetch_2 ();
53398: return 8;
53399: }
53400: unsigned long REGPARAM2 CPUFUNC(op_5190_5)(uae_u32 opcode) /* SUB */
53401: {
53402: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53403: uae_u32 dstreg = opcode & 7;
53404: OpcodeFamily = 7; CurrentInstrCycles = 20;
53405: {{ uae_u32 src = srcreg;
53406: { uaecptr dsta = m68k_areg(regs, dstreg);
53407: if ((dsta & 1) != 0) {
53408: last_fault_for_exception_3 = dsta;
53409: last_op_for_exception_3 = opcode;
53410: last_addr_for_exception_3 = m68k_getpc() + 2;
53411: Exception(3, 0, M68000_EXC_SRC_CPU);
53412: goto endlabel3023;
53413: }
53414: {{ uae_s32 dst = get_long(dsta);
53415: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
53416: { int flgs = ((uae_s32)(src)) < 0;
53417: int flgo = ((uae_s32)(dst)) < 0;
53418: int flgn = ((uae_s32)(newv)) < 0;
53419: SET_ZFLG (((uae_s32)(newv)) == 0);
53420: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53421: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
53422: COPY_CARRY;
53423: SET_NFLG (flgn != 0);
53424: m68k_incpc(2);
53425: fill_prefetch_2 ();
53426: put_long(dsta,newv);
53427: }}}}}}}}endlabel3023: ;
53428: return 20;
53429: }
53430: unsigned long REGPARAM2 CPUFUNC(op_5198_5)(uae_u32 opcode) /* SUB */
53431: {
53432: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53433: uae_u32 dstreg = opcode & 7;
53434: OpcodeFamily = 7; CurrentInstrCycles = 20;
53435: {{ uae_u32 src = srcreg;
53436: { uaecptr dsta = m68k_areg(regs, dstreg);
53437: if ((dsta & 1) != 0) {
53438: last_fault_for_exception_3 = dsta;
53439: last_op_for_exception_3 = opcode;
53440: last_addr_for_exception_3 = m68k_getpc() + 2;
53441: Exception(3, 0, M68000_EXC_SRC_CPU);
53442: goto endlabel3024;
53443: }
53444: {{ uae_s32 dst = get_long(dsta);
53445: m68k_areg(regs, dstreg) += 4;
53446: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
53447: { int flgs = ((uae_s32)(src)) < 0;
53448: int flgo = ((uae_s32)(dst)) < 0;
53449: int flgn = ((uae_s32)(newv)) < 0;
53450: SET_ZFLG (((uae_s32)(newv)) == 0);
53451: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53452: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
53453: COPY_CARRY;
53454: SET_NFLG (flgn != 0);
53455: m68k_incpc(2);
53456: fill_prefetch_2 ();
53457: put_long(dsta,newv);
53458: }}}}}}}}endlabel3024: ;
53459: return 20;
53460: }
53461: unsigned long REGPARAM2 CPUFUNC(op_51a0_5)(uae_u32 opcode) /* SUB */
53462: {
53463: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53464: uae_u32 dstreg = opcode & 7;
53465: OpcodeFamily = 7; CurrentInstrCycles = 22;
53466: {{ uae_u32 src = srcreg;
53467: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
53468: if ((dsta & 1) != 0) {
53469: last_fault_for_exception_3 = dsta;
53470: last_op_for_exception_3 = opcode;
53471: last_addr_for_exception_3 = m68k_getpc() + 2;
53472: Exception(3, 0, M68000_EXC_SRC_CPU);
53473: goto endlabel3025;
53474: }
53475: {{ uae_s32 dst = get_long(dsta);
53476: m68k_areg (regs, dstreg) = dsta;
53477: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
53478: { int flgs = ((uae_s32)(src)) < 0;
53479: int flgo = ((uae_s32)(dst)) < 0;
53480: int flgn = ((uae_s32)(newv)) < 0;
53481: SET_ZFLG (((uae_s32)(newv)) == 0);
53482: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53483: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
53484: COPY_CARRY;
53485: SET_NFLG (flgn != 0);
53486: m68k_incpc(2);
53487: fill_prefetch_2 ();
53488: put_long(dsta,newv);
53489: }}}}}}}}endlabel3025: ;
53490: return 22;
53491: }
53492: unsigned long REGPARAM2 CPUFUNC(op_51a8_5)(uae_u32 opcode) /* SUB */
53493: {
53494: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53495: uae_u32 dstreg = opcode & 7;
53496: OpcodeFamily = 7; CurrentInstrCycles = 24;
53497: {{ uae_u32 src = srcreg;
53498: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
53499: if ((dsta & 1) != 0) {
53500: last_fault_for_exception_3 = dsta;
53501: last_op_for_exception_3 = opcode;
53502: last_addr_for_exception_3 = m68k_getpc() + 4;
53503: Exception(3, 0, M68000_EXC_SRC_CPU);
53504: goto endlabel3026;
53505: }
53506: {{ uae_s32 dst = get_long(dsta);
53507: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
53508: { int flgs = ((uae_s32)(src)) < 0;
53509: int flgo = ((uae_s32)(dst)) < 0;
53510: int flgn = ((uae_s32)(newv)) < 0;
53511: SET_ZFLG (((uae_s32)(newv)) == 0);
53512: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53513: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
53514: COPY_CARRY;
53515: SET_NFLG (flgn != 0);
53516: m68k_incpc(4);
53517: fill_prefetch_0 ();
53518: put_long(dsta,newv);
53519: }}}}}}}}endlabel3026: ;
53520: return 24;
53521: }
53522: unsigned long REGPARAM2 CPUFUNC(op_51b0_5)(uae_u32 opcode) /* SUB */
53523: {
53524: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53525: uae_u32 dstreg = opcode & 7;
53526: OpcodeFamily = 7; CurrentInstrCycles = 26;
53527: {{ uae_u32 src = srcreg;
53528: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
53529: BusCyclePenalty += 2;
53530: if ((dsta & 1) != 0) {
53531: last_fault_for_exception_3 = dsta;
53532: last_op_for_exception_3 = opcode;
53533: last_addr_for_exception_3 = m68k_getpc() + 4;
53534: Exception(3, 0, M68000_EXC_SRC_CPU);
53535: goto endlabel3027;
53536: }
53537: {{ uae_s32 dst = get_long(dsta);
53538: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
53539: { int flgs = ((uae_s32)(src)) < 0;
53540: int flgo = ((uae_s32)(dst)) < 0;
53541: int flgn = ((uae_s32)(newv)) < 0;
53542: SET_ZFLG (((uae_s32)(newv)) == 0);
53543: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53544: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
53545: COPY_CARRY;
53546: SET_NFLG (flgn != 0);
53547: m68k_incpc(4);
53548: fill_prefetch_0 ();
53549: put_long(dsta,newv);
53550: }}}}}}}}endlabel3027: ;
53551: return 26;
53552: }
53553: unsigned long REGPARAM2 CPUFUNC(op_51b8_5)(uae_u32 opcode) /* SUB */
53554: {
53555: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53556: OpcodeFamily = 7; CurrentInstrCycles = 24;
53557: {{ uae_u32 src = srcreg;
53558: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
53559: if ((dsta & 1) != 0) {
53560: last_fault_for_exception_3 = dsta;
53561: last_op_for_exception_3 = opcode;
53562: last_addr_for_exception_3 = m68k_getpc() + 4;
53563: Exception(3, 0, M68000_EXC_SRC_CPU);
53564: goto endlabel3028;
53565: }
53566: {{ uae_s32 dst = get_long(dsta);
53567: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
53568: { int flgs = ((uae_s32)(src)) < 0;
53569: int flgo = ((uae_s32)(dst)) < 0;
53570: int flgn = ((uae_s32)(newv)) < 0;
53571: SET_ZFLG (((uae_s32)(newv)) == 0);
53572: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53573: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
53574: COPY_CARRY;
53575: SET_NFLG (flgn != 0);
53576: m68k_incpc(4);
53577: fill_prefetch_0 ();
53578: put_long(dsta,newv);
53579: }}}}}}}}endlabel3028: ;
53580: return 24;
53581: }
53582: unsigned long REGPARAM2 CPUFUNC(op_51b9_5)(uae_u32 opcode) /* SUB */
53583: {
53584: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
53585: OpcodeFamily = 7; CurrentInstrCycles = 28;
53586: {{ uae_u32 src = srcreg;
53587: { uaecptr dsta = get_ilong_prefetch(2);
53588: if ((dsta & 1) != 0) {
53589: last_fault_for_exception_3 = dsta;
53590: last_op_for_exception_3 = opcode;
53591: last_addr_for_exception_3 = m68k_getpc() + 6;
53592: Exception(3, 0, M68000_EXC_SRC_CPU);
53593: goto endlabel3029;
53594: }
53595: {{ uae_s32 dst = get_long(dsta);
53596: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
53597: { int flgs = ((uae_s32)(src)) < 0;
53598: int flgo = ((uae_s32)(dst)) < 0;
53599: int flgn = ((uae_s32)(newv)) < 0;
53600: SET_ZFLG (((uae_s32)(newv)) == 0);
53601: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
53602: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
53603: COPY_CARRY;
53604: SET_NFLG (flgn != 0);
53605: m68k_incpc(6);
53606: fill_prefetch_0 ();
53607: put_long(dsta,newv);
53608: }}}}}}}}endlabel3029: ;
53609: return 28;
53610: }
53611: unsigned long REGPARAM2 CPUFUNC(op_51c0_5)(uae_u32 opcode) /* Scc */
53612: {
53613: uae_u32 srcreg = (opcode & 7);
53614: OpcodeFamily = 59; CurrentInstrCycles = 4;
53615: {{{ int val = cctrue(1) ? 0xff : 0;
53616: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
53617: if (val) { m68k_incpc(2) ; return 4+2; }
53618: }}}m68k_incpc(2);
53619: fill_prefetch_2 ();
53620: return 4;
53621: }
53622: unsigned long REGPARAM2 CPUFUNC(op_51c8_5)(uae_u32 opcode) /* DBcc */
53623: {
53624: uae_u32 srcreg = (opcode & 7);
53625: OpcodeFamily = 58; CurrentInstrCycles = 12;
53626: {{ uae_s16 src = m68k_dreg(regs, srcreg);
53627: { uae_s16 offs = get_iword_prefetch(2);
53628: if (!cctrue(1)) {
53629: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
53630: if (src) {
53631: if (offs & 1) {
53632: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
53633: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
53634: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3031;
53635: }
53636: m68k_incpc((uae_s32)offs + 2);
53637: fill_prefetch_0 ();
53638: return 10;
53639: } else {
53640: m68k_incpc(4);
53641: fill_prefetch_0 ();
53642: return 14;
53643: }
53644: }
53645: }}}m68k_incpc(4);
53646: fill_prefetch_0 ();
53647: endlabel3031: ;
53648: return 12;
53649: }
53650: unsigned long REGPARAM2 CPUFUNC(op_51d0_5)(uae_u32 opcode) /* Scc */
53651: {
53652: uae_u32 srcreg = (opcode & 7);
53653: OpcodeFamily = 59; CurrentInstrCycles = 12;
53654: {{ uaecptr srca = m68k_areg(regs, srcreg);
53655: { int val = cctrue(1) ? 0xff : 0;
53656: m68k_incpc(2);
53657: fill_prefetch_2 ();
53658: put_byte(srca,val);
53659: }}}return 12;
53660: }
53661: unsigned long REGPARAM2 CPUFUNC(op_51d8_5)(uae_u32 opcode) /* Scc */
53662: {
53663: uae_u32 srcreg = (opcode & 7);
53664: OpcodeFamily = 59; CurrentInstrCycles = 12;
53665: {{ uaecptr srca = m68k_areg(regs, srcreg);
53666: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
53667: { int val = cctrue(1) ? 0xff : 0;
53668: m68k_incpc(2);
53669: fill_prefetch_2 ();
53670: put_byte(srca,val);
53671: }}}return 12;
53672: }
53673: unsigned long REGPARAM2 CPUFUNC(op_51e0_5)(uae_u32 opcode) /* Scc */
53674: {
53675: uae_u32 srcreg = (opcode & 7);
53676: OpcodeFamily = 59; CurrentInstrCycles = 14;
53677: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
53678: m68k_areg (regs, srcreg) = srca;
53679: { int val = cctrue(1) ? 0xff : 0;
53680: m68k_incpc(2);
53681: fill_prefetch_2 ();
53682: put_byte(srca,val);
53683: }}}return 14;
53684: }
53685: unsigned long REGPARAM2 CPUFUNC(op_51e8_5)(uae_u32 opcode) /* Scc */
53686: {
53687: uae_u32 srcreg = (opcode & 7);
53688: OpcodeFamily = 59; CurrentInstrCycles = 16;
53689: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
53690: { int val = cctrue(1) ? 0xff : 0;
53691: m68k_incpc(4);
53692: fill_prefetch_0 ();
53693: put_byte(srca,val);
53694: }}}return 16;
53695: }
53696: unsigned long REGPARAM2 CPUFUNC(op_51f0_5)(uae_u32 opcode) /* Scc */
53697: {
53698: uae_u32 srcreg = (opcode & 7);
53699: OpcodeFamily = 59; CurrentInstrCycles = 18;
53700: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
53701: BusCyclePenalty += 2;
53702: { int val = cctrue(1) ? 0xff : 0;
53703: m68k_incpc(4);
53704: fill_prefetch_0 ();
53705: put_byte(srca,val);
53706: }}}return 18;
53707: }
53708: unsigned long REGPARAM2 CPUFUNC(op_51f8_5)(uae_u32 opcode) /* Scc */
53709: {
53710: OpcodeFamily = 59; CurrentInstrCycles = 16;
53711: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
53712: { int val = cctrue(1) ? 0xff : 0;
53713: m68k_incpc(4);
53714: fill_prefetch_0 ();
53715: put_byte(srca,val);
53716: }}}return 16;
53717: }
53718: unsigned long REGPARAM2 CPUFUNC(op_51f9_5)(uae_u32 opcode) /* Scc */
53719: {
53720: OpcodeFamily = 59; CurrentInstrCycles = 20;
53721: {{ uaecptr srca = get_ilong_prefetch(2);
53722: { int val = cctrue(1) ? 0xff : 0;
53723: m68k_incpc(6);
53724: fill_prefetch_0 ();
53725: put_byte(srca,val);
53726: }}}return 20;
53727: }
53728: unsigned long REGPARAM2 CPUFUNC(op_52c0_5)(uae_u32 opcode) /* Scc */
53729: {
53730: uae_u32 srcreg = (opcode & 7);
53731: OpcodeFamily = 59; CurrentInstrCycles = 4;
53732: {{{ int val = cctrue(2) ? 0xff : 0;
53733: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
53734: if (val) { m68k_incpc(2) ; return 4+2; }
53735: }}}m68k_incpc(2);
53736: fill_prefetch_2 ();
53737: return 4;
53738: }
53739: unsigned long REGPARAM2 CPUFUNC(op_52c8_5)(uae_u32 opcode) /* DBcc */
53740: {
53741: uae_u32 srcreg = (opcode & 7);
53742: OpcodeFamily = 58; CurrentInstrCycles = 12;
53743: {{ uae_s16 src = m68k_dreg(regs, srcreg);
53744: { uae_s16 offs = get_iword_prefetch(2);
53745: if (!cctrue(2)) {
53746: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
53747: if (src) {
53748: if (offs & 1) {
53749: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
53750: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
53751: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3040;
53752: }
53753: m68k_incpc((uae_s32)offs + 2);
53754: fill_prefetch_0 ();
53755: return 10;
53756: } else {
53757: m68k_incpc(4);
53758: fill_prefetch_0 ();
53759: return 14;
53760: }
53761: }
53762: }}}m68k_incpc(4);
53763: fill_prefetch_0 ();
53764: endlabel3040: ;
53765: return 12;
53766: }
53767: unsigned long REGPARAM2 CPUFUNC(op_52d0_5)(uae_u32 opcode) /* Scc */
53768: {
53769: uae_u32 srcreg = (opcode & 7);
53770: OpcodeFamily = 59; CurrentInstrCycles = 12;
53771: {{ uaecptr srca = m68k_areg(regs, srcreg);
53772: { int val = cctrue(2) ? 0xff : 0;
53773: m68k_incpc(2);
53774: fill_prefetch_2 ();
53775: put_byte(srca,val);
53776: }}}return 12;
53777: }
53778: unsigned long REGPARAM2 CPUFUNC(op_52d8_5)(uae_u32 opcode) /* Scc */
53779: {
53780: uae_u32 srcreg = (opcode & 7);
53781: OpcodeFamily = 59; CurrentInstrCycles = 12;
53782: {{ uaecptr srca = m68k_areg(regs, srcreg);
53783: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
53784: { int val = cctrue(2) ? 0xff : 0;
53785: m68k_incpc(2);
53786: fill_prefetch_2 ();
53787: put_byte(srca,val);
53788: }}}return 12;
53789: }
53790: unsigned long REGPARAM2 CPUFUNC(op_52e0_5)(uae_u32 opcode) /* Scc */
53791: {
53792: uae_u32 srcreg = (opcode & 7);
53793: OpcodeFamily = 59; CurrentInstrCycles = 14;
53794: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
53795: m68k_areg (regs, srcreg) = srca;
53796: { int val = cctrue(2) ? 0xff : 0;
53797: m68k_incpc(2);
53798: fill_prefetch_2 ();
53799: put_byte(srca,val);
53800: }}}return 14;
53801: }
53802: unsigned long REGPARAM2 CPUFUNC(op_52e8_5)(uae_u32 opcode) /* Scc */
53803: {
53804: uae_u32 srcreg = (opcode & 7);
53805: OpcodeFamily = 59; CurrentInstrCycles = 16;
53806: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
53807: { int val = cctrue(2) ? 0xff : 0;
53808: m68k_incpc(4);
53809: fill_prefetch_0 ();
53810: put_byte(srca,val);
53811: }}}return 16;
53812: }
53813: unsigned long REGPARAM2 CPUFUNC(op_52f0_5)(uae_u32 opcode) /* Scc */
53814: {
53815: uae_u32 srcreg = (opcode & 7);
53816: OpcodeFamily = 59; CurrentInstrCycles = 18;
53817: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
53818: BusCyclePenalty += 2;
53819: { int val = cctrue(2) ? 0xff : 0;
53820: m68k_incpc(4);
53821: fill_prefetch_0 ();
53822: put_byte(srca,val);
53823: }}}return 18;
53824: }
53825: unsigned long REGPARAM2 CPUFUNC(op_52f8_5)(uae_u32 opcode) /* Scc */
53826: {
53827: OpcodeFamily = 59; CurrentInstrCycles = 16;
53828: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
53829: { int val = cctrue(2) ? 0xff : 0;
53830: m68k_incpc(4);
53831: fill_prefetch_0 ();
53832: put_byte(srca,val);
53833: }}}return 16;
53834: }
53835: unsigned long REGPARAM2 CPUFUNC(op_52f9_5)(uae_u32 opcode) /* Scc */
53836: {
53837: OpcodeFamily = 59; CurrentInstrCycles = 20;
53838: {{ uaecptr srca = get_ilong_prefetch(2);
53839: { int val = cctrue(2) ? 0xff : 0;
53840: m68k_incpc(6);
53841: fill_prefetch_0 ();
53842: put_byte(srca,val);
53843: }}}return 20;
53844: }
53845: unsigned long REGPARAM2 CPUFUNC(op_53c0_5)(uae_u32 opcode) /* Scc */
53846: {
53847: uae_u32 srcreg = (opcode & 7);
53848: OpcodeFamily = 59; CurrentInstrCycles = 4;
53849: {{{ int val = cctrue(3) ? 0xff : 0;
53850: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
53851: if (val) { m68k_incpc(2) ; return 4+2; }
53852: }}}m68k_incpc(2);
53853: fill_prefetch_2 ();
53854: return 4;
53855: }
53856: unsigned long REGPARAM2 CPUFUNC(op_53c8_5)(uae_u32 opcode) /* DBcc */
53857: {
53858: uae_u32 srcreg = (opcode & 7);
53859: OpcodeFamily = 58; CurrentInstrCycles = 12;
53860: {{ uae_s16 src = m68k_dreg(regs, srcreg);
53861: { uae_s16 offs = get_iword_prefetch(2);
53862: if (!cctrue(3)) {
53863: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
53864: if (src) {
53865: if (offs & 1) {
53866: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
53867: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
53868: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3049;
53869: }
53870: m68k_incpc((uae_s32)offs + 2);
53871: fill_prefetch_0 ();
53872: return 10;
53873: } else {
53874: m68k_incpc(4);
53875: fill_prefetch_0 ();
53876: return 14;
53877: }
53878: }
53879: }}}m68k_incpc(4);
53880: fill_prefetch_0 ();
53881: endlabel3049: ;
53882: return 12;
53883: }
53884: unsigned long REGPARAM2 CPUFUNC(op_53d0_5)(uae_u32 opcode) /* Scc */
53885: {
53886: uae_u32 srcreg = (opcode & 7);
53887: OpcodeFamily = 59; CurrentInstrCycles = 12;
53888: {{ uaecptr srca = m68k_areg(regs, srcreg);
53889: { int val = cctrue(3) ? 0xff : 0;
53890: m68k_incpc(2);
53891: fill_prefetch_2 ();
53892: put_byte(srca,val);
53893: }}}return 12;
53894: }
53895: unsigned long REGPARAM2 CPUFUNC(op_53d8_5)(uae_u32 opcode) /* Scc */
53896: {
53897: uae_u32 srcreg = (opcode & 7);
53898: OpcodeFamily = 59; CurrentInstrCycles = 12;
53899: {{ uaecptr srca = m68k_areg(regs, srcreg);
53900: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
53901: { int val = cctrue(3) ? 0xff : 0;
53902: m68k_incpc(2);
53903: fill_prefetch_2 ();
53904: put_byte(srca,val);
53905: }}}return 12;
53906: }
53907: unsigned long REGPARAM2 CPUFUNC(op_53e0_5)(uae_u32 opcode) /* Scc */
53908: {
53909: uae_u32 srcreg = (opcode & 7);
53910: OpcodeFamily = 59; CurrentInstrCycles = 14;
53911: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
53912: m68k_areg (regs, srcreg) = srca;
53913: { int val = cctrue(3) ? 0xff : 0;
53914: m68k_incpc(2);
53915: fill_prefetch_2 ();
53916: put_byte(srca,val);
53917: }}}return 14;
53918: }
53919: unsigned long REGPARAM2 CPUFUNC(op_53e8_5)(uae_u32 opcode) /* Scc */
53920: {
53921: uae_u32 srcreg = (opcode & 7);
53922: OpcodeFamily = 59; CurrentInstrCycles = 16;
53923: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
53924: { int val = cctrue(3) ? 0xff : 0;
53925: m68k_incpc(4);
53926: fill_prefetch_0 ();
53927: put_byte(srca,val);
53928: }}}return 16;
53929: }
53930: unsigned long REGPARAM2 CPUFUNC(op_53f0_5)(uae_u32 opcode) /* Scc */
53931: {
53932: uae_u32 srcreg = (opcode & 7);
53933: OpcodeFamily = 59; CurrentInstrCycles = 18;
53934: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
53935: BusCyclePenalty += 2;
53936: { int val = cctrue(3) ? 0xff : 0;
53937: m68k_incpc(4);
53938: fill_prefetch_0 ();
53939: put_byte(srca,val);
53940: }}}return 18;
53941: }
53942: unsigned long REGPARAM2 CPUFUNC(op_53f8_5)(uae_u32 opcode) /* Scc */
53943: {
53944: OpcodeFamily = 59; CurrentInstrCycles = 16;
53945: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
53946: { int val = cctrue(3) ? 0xff : 0;
53947: m68k_incpc(4);
53948: fill_prefetch_0 ();
53949: put_byte(srca,val);
53950: }}}return 16;
53951: }
53952: unsigned long REGPARAM2 CPUFUNC(op_53f9_5)(uae_u32 opcode) /* Scc */
53953: {
53954: OpcodeFamily = 59; CurrentInstrCycles = 20;
53955: {{ uaecptr srca = get_ilong_prefetch(2);
53956: { int val = cctrue(3) ? 0xff : 0;
53957: m68k_incpc(6);
53958: fill_prefetch_0 ();
53959: put_byte(srca,val);
53960: }}}return 20;
53961: }
53962: unsigned long REGPARAM2 CPUFUNC(op_54c0_5)(uae_u32 opcode) /* Scc */
53963: {
53964: uae_u32 srcreg = (opcode & 7);
53965: OpcodeFamily = 59; CurrentInstrCycles = 4;
53966: {{{ int val = cctrue(4) ? 0xff : 0;
53967: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
53968: if (val) { m68k_incpc(2) ; return 4+2; }
53969: }}}m68k_incpc(2);
53970: fill_prefetch_2 ();
53971: return 4;
53972: }
53973: unsigned long REGPARAM2 CPUFUNC(op_54c8_5)(uae_u32 opcode) /* DBcc */
53974: {
53975: uae_u32 srcreg = (opcode & 7);
53976: OpcodeFamily = 58; CurrentInstrCycles = 12;
53977: {{ uae_s16 src = m68k_dreg(regs, srcreg);
53978: { uae_s16 offs = get_iword_prefetch(2);
53979: if (!cctrue(4)) {
53980: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
53981: if (src) {
53982: if (offs & 1) {
53983: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
53984: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
53985: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3058;
53986: }
53987: m68k_incpc((uae_s32)offs + 2);
53988: fill_prefetch_0 ();
53989: return 10;
53990: } else {
53991: m68k_incpc(4);
53992: fill_prefetch_0 ();
53993: return 14;
53994: }
53995: }
53996: }}}m68k_incpc(4);
53997: fill_prefetch_0 ();
53998: endlabel3058: ;
53999: return 12;
54000: }
54001: unsigned long REGPARAM2 CPUFUNC(op_54d0_5)(uae_u32 opcode) /* Scc */
54002: {
54003: uae_u32 srcreg = (opcode & 7);
54004: OpcodeFamily = 59; CurrentInstrCycles = 12;
54005: {{ uaecptr srca = m68k_areg(regs, srcreg);
54006: { int val = cctrue(4) ? 0xff : 0;
54007: m68k_incpc(2);
54008: fill_prefetch_2 ();
54009: put_byte(srca,val);
54010: }}}return 12;
54011: }
54012: unsigned long REGPARAM2 CPUFUNC(op_54d8_5)(uae_u32 opcode) /* Scc */
54013: {
54014: uae_u32 srcreg = (opcode & 7);
54015: OpcodeFamily = 59; CurrentInstrCycles = 12;
54016: {{ uaecptr srca = m68k_areg(regs, srcreg);
54017: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
54018: { int val = cctrue(4) ? 0xff : 0;
54019: m68k_incpc(2);
54020: fill_prefetch_2 ();
54021: put_byte(srca,val);
54022: }}}return 12;
54023: }
54024: unsigned long REGPARAM2 CPUFUNC(op_54e0_5)(uae_u32 opcode) /* Scc */
54025: {
54026: uae_u32 srcreg = (opcode & 7);
54027: OpcodeFamily = 59; CurrentInstrCycles = 14;
54028: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
54029: m68k_areg (regs, srcreg) = srca;
54030: { int val = cctrue(4) ? 0xff : 0;
54031: m68k_incpc(2);
54032: fill_prefetch_2 ();
54033: put_byte(srca,val);
54034: }}}return 14;
54035: }
54036: unsigned long REGPARAM2 CPUFUNC(op_54e8_5)(uae_u32 opcode) /* Scc */
54037: {
54038: uae_u32 srcreg = (opcode & 7);
54039: OpcodeFamily = 59; CurrentInstrCycles = 16;
54040: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
54041: { int val = cctrue(4) ? 0xff : 0;
54042: m68k_incpc(4);
54043: fill_prefetch_0 ();
54044: put_byte(srca,val);
54045: }}}return 16;
54046: }
54047: unsigned long REGPARAM2 CPUFUNC(op_54f0_5)(uae_u32 opcode) /* Scc */
54048: {
54049: uae_u32 srcreg = (opcode & 7);
54050: OpcodeFamily = 59; CurrentInstrCycles = 18;
54051: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
54052: BusCyclePenalty += 2;
54053: { int val = cctrue(4) ? 0xff : 0;
54054: m68k_incpc(4);
54055: fill_prefetch_0 ();
54056: put_byte(srca,val);
54057: }}}return 18;
54058: }
54059: unsigned long REGPARAM2 CPUFUNC(op_54f8_5)(uae_u32 opcode) /* Scc */
54060: {
54061: OpcodeFamily = 59; CurrentInstrCycles = 16;
54062: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
54063: { int val = cctrue(4) ? 0xff : 0;
54064: m68k_incpc(4);
54065: fill_prefetch_0 ();
54066: put_byte(srca,val);
54067: }}}return 16;
54068: }
54069: unsigned long REGPARAM2 CPUFUNC(op_54f9_5)(uae_u32 opcode) /* Scc */
54070: {
54071: OpcodeFamily = 59; CurrentInstrCycles = 20;
54072: {{ uaecptr srca = get_ilong_prefetch(2);
54073: { int val = cctrue(4) ? 0xff : 0;
54074: m68k_incpc(6);
54075: fill_prefetch_0 ();
54076: put_byte(srca,val);
54077: }}}return 20;
54078: }
54079: unsigned long REGPARAM2 CPUFUNC(op_55c0_5)(uae_u32 opcode) /* Scc */
54080: {
54081: uae_u32 srcreg = (opcode & 7);
54082: OpcodeFamily = 59; CurrentInstrCycles = 4;
54083: {{{ int val = cctrue(5) ? 0xff : 0;
54084: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
54085: if (val) { m68k_incpc(2) ; return 4+2; }
54086: }}}m68k_incpc(2);
54087: fill_prefetch_2 ();
54088: return 4;
54089: }
54090: unsigned long REGPARAM2 CPUFUNC(op_55c8_5)(uae_u32 opcode) /* DBcc */
54091: {
54092: uae_u32 srcreg = (opcode & 7);
54093: OpcodeFamily = 58; CurrentInstrCycles = 12;
54094: {{ uae_s16 src = m68k_dreg(regs, srcreg);
54095: { uae_s16 offs = get_iword_prefetch(2);
54096: if (!cctrue(5)) {
54097: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
54098: if (src) {
54099: if (offs & 1) {
54100: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
54101: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
54102: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3067;
54103: }
54104: m68k_incpc((uae_s32)offs + 2);
54105: fill_prefetch_0 ();
54106: return 10;
54107: } else {
54108: m68k_incpc(4);
54109: fill_prefetch_0 ();
54110: return 14;
54111: }
54112: }
54113: }}}m68k_incpc(4);
54114: fill_prefetch_0 ();
54115: endlabel3067: ;
54116: return 12;
54117: }
54118: unsigned long REGPARAM2 CPUFUNC(op_55d0_5)(uae_u32 opcode) /* Scc */
54119: {
54120: uae_u32 srcreg = (opcode & 7);
54121: OpcodeFamily = 59; CurrentInstrCycles = 12;
54122: {{ uaecptr srca = m68k_areg(regs, srcreg);
54123: { int val = cctrue(5) ? 0xff : 0;
54124: m68k_incpc(2);
54125: fill_prefetch_2 ();
54126: put_byte(srca,val);
54127: }}}return 12;
54128: }
54129: unsigned long REGPARAM2 CPUFUNC(op_55d8_5)(uae_u32 opcode) /* Scc */
54130: {
54131: uae_u32 srcreg = (opcode & 7);
54132: OpcodeFamily = 59; CurrentInstrCycles = 12;
54133: {{ uaecptr srca = m68k_areg(regs, srcreg);
54134: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
54135: { int val = cctrue(5) ? 0xff : 0;
54136: m68k_incpc(2);
54137: fill_prefetch_2 ();
54138: put_byte(srca,val);
54139: }}}return 12;
54140: }
54141: unsigned long REGPARAM2 CPUFUNC(op_55e0_5)(uae_u32 opcode) /* Scc */
54142: {
54143: uae_u32 srcreg = (opcode & 7);
54144: OpcodeFamily = 59; CurrentInstrCycles = 14;
54145: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
54146: m68k_areg (regs, srcreg) = srca;
54147: { int val = cctrue(5) ? 0xff : 0;
54148: m68k_incpc(2);
54149: fill_prefetch_2 ();
54150: put_byte(srca,val);
54151: }}}return 14;
54152: }
54153: unsigned long REGPARAM2 CPUFUNC(op_55e8_5)(uae_u32 opcode) /* Scc */
54154: {
54155: uae_u32 srcreg = (opcode & 7);
54156: OpcodeFamily = 59; CurrentInstrCycles = 16;
54157: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
54158: { int val = cctrue(5) ? 0xff : 0;
54159: m68k_incpc(4);
54160: fill_prefetch_0 ();
54161: put_byte(srca,val);
54162: }}}return 16;
54163: }
54164: unsigned long REGPARAM2 CPUFUNC(op_55f0_5)(uae_u32 opcode) /* Scc */
54165: {
54166: uae_u32 srcreg = (opcode & 7);
54167: OpcodeFamily = 59; CurrentInstrCycles = 18;
54168: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
54169: BusCyclePenalty += 2;
54170: { int val = cctrue(5) ? 0xff : 0;
54171: m68k_incpc(4);
54172: fill_prefetch_0 ();
54173: put_byte(srca,val);
54174: }}}return 18;
54175: }
54176: unsigned long REGPARAM2 CPUFUNC(op_55f8_5)(uae_u32 opcode) /* Scc */
54177: {
54178: OpcodeFamily = 59; CurrentInstrCycles = 16;
54179: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
54180: { int val = cctrue(5) ? 0xff : 0;
54181: m68k_incpc(4);
54182: fill_prefetch_0 ();
54183: put_byte(srca,val);
54184: }}}return 16;
54185: }
54186: unsigned long REGPARAM2 CPUFUNC(op_55f9_5)(uae_u32 opcode) /* Scc */
54187: {
54188: OpcodeFamily = 59; CurrentInstrCycles = 20;
54189: {{ uaecptr srca = get_ilong_prefetch(2);
54190: { int val = cctrue(5) ? 0xff : 0;
54191: m68k_incpc(6);
54192: fill_prefetch_0 ();
54193: put_byte(srca,val);
54194: }}}return 20;
54195: }
54196: unsigned long REGPARAM2 CPUFUNC(op_56c0_5)(uae_u32 opcode) /* Scc */
54197: {
54198: uae_u32 srcreg = (opcode & 7);
54199: OpcodeFamily = 59; CurrentInstrCycles = 4;
54200: {{{ int val = cctrue(6) ? 0xff : 0;
54201: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
54202: if (val) { m68k_incpc(2) ; return 4+2; }
54203: }}}m68k_incpc(2);
54204: fill_prefetch_2 ();
54205: return 4;
54206: }
54207: unsigned long REGPARAM2 CPUFUNC(op_56c8_5)(uae_u32 opcode) /* DBcc */
54208: {
54209: uae_u32 srcreg = (opcode & 7);
54210: OpcodeFamily = 58; CurrentInstrCycles = 12;
54211: {{ uae_s16 src = m68k_dreg(regs, srcreg);
54212: { uae_s16 offs = get_iword_prefetch(2);
54213: if (!cctrue(6)) {
54214: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
54215: if (src) {
54216: if (offs & 1) {
54217: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
54218: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
54219: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3076;
54220: }
54221: m68k_incpc((uae_s32)offs + 2);
54222: fill_prefetch_0 ();
54223: return 10;
54224: } else {
54225: m68k_incpc(4);
54226: fill_prefetch_0 ();
54227: return 14;
54228: }
54229: }
54230: }}}m68k_incpc(4);
54231: fill_prefetch_0 ();
54232: endlabel3076: ;
54233: return 12;
54234: }
54235: unsigned long REGPARAM2 CPUFUNC(op_56d0_5)(uae_u32 opcode) /* Scc */
54236: {
54237: uae_u32 srcreg = (opcode & 7);
54238: OpcodeFamily = 59; CurrentInstrCycles = 12;
54239: {{ uaecptr srca = m68k_areg(regs, srcreg);
54240: { int val = cctrue(6) ? 0xff : 0;
54241: m68k_incpc(2);
54242: fill_prefetch_2 ();
54243: put_byte(srca,val);
54244: }}}return 12;
54245: }
54246: unsigned long REGPARAM2 CPUFUNC(op_56d8_5)(uae_u32 opcode) /* Scc */
54247: {
54248: uae_u32 srcreg = (opcode & 7);
54249: OpcodeFamily = 59; CurrentInstrCycles = 12;
54250: {{ uaecptr srca = m68k_areg(regs, srcreg);
54251: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
54252: { int val = cctrue(6) ? 0xff : 0;
54253: m68k_incpc(2);
54254: fill_prefetch_2 ();
54255: put_byte(srca,val);
54256: }}}return 12;
54257: }
54258: unsigned long REGPARAM2 CPUFUNC(op_56e0_5)(uae_u32 opcode) /* Scc */
54259: {
54260: uae_u32 srcreg = (opcode & 7);
54261: OpcodeFamily = 59; CurrentInstrCycles = 14;
54262: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
54263: m68k_areg (regs, srcreg) = srca;
54264: { int val = cctrue(6) ? 0xff : 0;
54265: m68k_incpc(2);
54266: fill_prefetch_2 ();
54267: put_byte(srca,val);
54268: }}}return 14;
54269: }
54270: unsigned long REGPARAM2 CPUFUNC(op_56e8_5)(uae_u32 opcode) /* Scc */
54271: {
54272: uae_u32 srcreg = (opcode & 7);
54273: OpcodeFamily = 59; CurrentInstrCycles = 16;
54274: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
54275: { int val = cctrue(6) ? 0xff : 0;
54276: m68k_incpc(4);
54277: fill_prefetch_0 ();
54278: put_byte(srca,val);
54279: }}}return 16;
54280: }
54281: unsigned long REGPARAM2 CPUFUNC(op_56f0_5)(uae_u32 opcode) /* Scc */
54282: {
54283: uae_u32 srcreg = (opcode & 7);
54284: OpcodeFamily = 59; CurrentInstrCycles = 18;
54285: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
54286: BusCyclePenalty += 2;
54287: { int val = cctrue(6) ? 0xff : 0;
54288: m68k_incpc(4);
54289: fill_prefetch_0 ();
54290: put_byte(srca,val);
54291: }}}return 18;
54292: }
54293: unsigned long REGPARAM2 CPUFUNC(op_56f8_5)(uae_u32 opcode) /* Scc */
54294: {
54295: OpcodeFamily = 59; CurrentInstrCycles = 16;
54296: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
54297: { int val = cctrue(6) ? 0xff : 0;
54298: m68k_incpc(4);
54299: fill_prefetch_0 ();
54300: put_byte(srca,val);
54301: }}}return 16;
54302: }
54303: unsigned long REGPARAM2 CPUFUNC(op_56f9_5)(uae_u32 opcode) /* Scc */
54304: {
54305: OpcodeFamily = 59; CurrentInstrCycles = 20;
54306: {{ uaecptr srca = get_ilong_prefetch(2);
54307: { int val = cctrue(6) ? 0xff : 0;
54308: m68k_incpc(6);
54309: fill_prefetch_0 ();
54310: put_byte(srca,val);
54311: }}}return 20;
54312: }
54313: unsigned long REGPARAM2 CPUFUNC(op_57c0_5)(uae_u32 opcode) /* Scc */
54314: {
54315: uae_u32 srcreg = (opcode & 7);
54316: OpcodeFamily = 59; CurrentInstrCycles = 4;
54317: {{{ int val = cctrue(7) ? 0xff : 0;
54318: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
54319: if (val) { m68k_incpc(2) ; return 4+2; }
54320: }}}m68k_incpc(2);
54321: fill_prefetch_2 ();
54322: return 4;
54323: }
54324: unsigned long REGPARAM2 CPUFUNC(op_57c8_5)(uae_u32 opcode) /* DBcc */
54325: {
54326: uae_u32 srcreg = (opcode & 7);
54327: OpcodeFamily = 58; CurrentInstrCycles = 12;
54328: {{ uae_s16 src = m68k_dreg(regs, srcreg);
54329: { uae_s16 offs = get_iword_prefetch(2);
54330: if (!cctrue(7)) {
54331: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
54332: if (src) {
54333: if (offs & 1) {
54334: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
54335: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
54336: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3085;
54337: }
54338: m68k_incpc((uae_s32)offs + 2);
54339: fill_prefetch_0 ();
54340: return 10;
54341: } else {
54342: m68k_incpc(4);
54343: fill_prefetch_0 ();
54344: return 14;
54345: }
54346: }
54347: }}}m68k_incpc(4);
54348: fill_prefetch_0 ();
54349: endlabel3085: ;
54350: return 12;
54351: }
54352: unsigned long REGPARAM2 CPUFUNC(op_57d0_5)(uae_u32 opcode) /* Scc */
54353: {
54354: uae_u32 srcreg = (opcode & 7);
54355: OpcodeFamily = 59; CurrentInstrCycles = 12;
54356: {{ uaecptr srca = m68k_areg(regs, srcreg);
54357: { int val = cctrue(7) ? 0xff : 0;
54358: m68k_incpc(2);
54359: fill_prefetch_2 ();
54360: put_byte(srca,val);
54361: }}}return 12;
54362: }
54363: unsigned long REGPARAM2 CPUFUNC(op_57d8_5)(uae_u32 opcode) /* Scc */
54364: {
54365: uae_u32 srcreg = (opcode & 7);
54366: OpcodeFamily = 59; CurrentInstrCycles = 12;
54367: {{ uaecptr srca = m68k_areg(regs, srcreg);
54368: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
54369: { int val = cctrue(7) ? 0xff : 0;
54370: m68k_incpc(2);
54371: fill_prefetch_2 ();
54372: put_byte(srca,val);
54373: }}}return 12;
54374: }
54375: unsigned long REGPARAM2 CPUFUNC(op_57e0_5)(uae_u32 opcode) /* Scc */
54376: {
54377: uae_u32 srcreg = (opcode & 7);
54378: OpcodeFamily = 59; CurrentInstrCycles = 14;
54379: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
54380: m68k_areg (regs, srcreg) = srca;
54381: { int val = cctrue(7) ? 0xff : 0;
54382: m68k_incpc(2);
54383: fill_prefetch_2 ();
54384: put_byte(srca,val);
54385: }}}return 14;
54386: }
54387: unsigned long REGPARAM2 CPUFUNC(op_57e8_5)(uae_u32 opcode) /* Scc */
54388: {
54389: uae_u32 srcreg = (opcode & 7);
54390: OpcodeFamily = 59; CurrentInstrCycles = 16;
54391: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
54392: { int val = cctrue(7) ? 0xff : 0;
54393: m68k_incpc(4);
54394: fill_prefetch_0 ();
54395: put_byte(srca,val);
54396: }}}return 16;
54397: }
54398: unsigned long REGPARAM2 CPUFUNC(op_57f0_5)(uae_u32 opcode) /* Scc */
54399: {
54400: uae_u32 srcreg = (opcode & 7);
54401: OpcodeFamily = 59; CurrentInstrCycles = 18;
54402: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
54403: BusCyclePenalty += 2;
54404: { int val = cctrue(7) ? 0xff : 0;
54405: m68k_incpc(4);
54406: fill_prefetch_0 ();
54407: put_byte(srca,val);
54408: }}}return 18;
54409: }
54410: unsigned long REGPARAM2 CPUFUNC(op_57f8_5)(uae_u32 opcode) /* Scc */
54411: {
54412: OpcodeFamily = 59; CurrentInstrCycles = 16;
54413: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
54414: { int val = cctrue(7) ? 0xff : 0;
54415: m68k_incpc(4);
54416: fill_prefetch_0 ();
54417: put_byte(srca,val);
54418: }}}return 16;
54419: }
54420: unsigned long REGPARAM2 CPUFUNC(op_57f9_5)(uae_u32 opcode) /* Scc */
54421: {
54422: OpcodeFamily = 59; CurrentInstrCycles = 20;
54423: {{ uaecptr srca = get_ilong_prefetch(2);
54424: { int val = cctrue(7) ? 0xff : 0;
54425: m68k_incpc(6);
54426: fill_prefetch_0 ();
54427: put_byte(srca,val);
54428: }}}return 20;
54429: }
54430: unsigned long REGPARAM2 CPUFUNC(op_58c0_5)(uae_u32 opcode) /* Scc */
54431: {
54432: uae_u32 srcreg = (opcode & 7);
54433: OpcodeFamily = 59; CurrentInstrCycles = 4;
54434: {{{ int val = cctrue(8) ? 0xff : 0;
54435: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
54436: if (val) { m68k_incpc(2) ; return 4+2; }
54437: }}}m68k_incpc(2);
54438: fill_prefetch_2 ();
54439: return 4;
54440: }
54441: unsigned long REGPARAM2 CPUFUNC(op_58c8_5)(uae_u32 opcode) /* DBcc */
54442: {
54443: uae_u32 srcreg = (opcode & 7);
54444: OpcodeFamily = 58; CurrentInstrCycles = 12;
54445: {{ uae_s16 src = m68k_dreg(regs, srcreg);
54446: { uae_s16 offs = get_iword_prefetch(2);
54447: if (!cctrue(8)) {
54448: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
54449: if (src) {
54450: if (offs & 1) {
54451: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
54452: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
54453: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3094;
54454: }
54455: m68k_incpc((uae_s32)offs + 2);
54456: fill_prefetch_0 ();
54457: return 10;
54458: } else {
54459: m68k_incpc(4);
54460: fill_prefetch_0 ();
54461: return 14;
54462: }
54463: }
54464: }}}m68k_incpc(4);
54465: fill_prefetch_0 ();
54466: endlabel3094: ;
54467: return 12;
54468: }
54469: unsigned long REGPARAM2 CPUFUNC(op_58d0_5)(uae_u32 opcode) /* Scc */
54470: {
54471: uae_u32 srcreg = (opcode & 7);
54472: OpcodeFamily = 59; CurrentInstrCycles = 12;
54473: {{ uaecptr srca = m68k_areg(regs, srcreg);
54474: { int val = cctrue(8) ? 0xff : 0;
54475: m68k_incpc(2);
54476: fill_prefetch_2 ();
54477: put_byte(srca,val);
54478: }}}return 12;
54479: }
54480: unsigned long REGPARAM2 CPUFUNC(op_58d8_5)(uae_u32 opcode) /* Scc */
54481: {
54482: uae_u32 srcreg = (opcode & 7);
54483: OpcodeFamily = 59; CurrentInstrCycles = 12;
54484: {{ uaecptr srca = m68k_areg(regs, srcreg);
54485: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
54486: { int val = cctrue(8) ? 0xff : 0;
54487: m68k_incpc(2);
54488: fill_prefetch_2 ();
54489: put_byte(srca,val);
54490: }}}return 12;
54491: }
54492: unsigned long REGPARAM2 CPUFUNC(op_58e0_5)(uae_u32 opcode) /* Scc */
54493: {
54494: uae_u32 srcreg = (opcode & 7);
54495: OpcodeFamily = 59; CurrentInstrCycles = 14;
54496: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
54497: m68k_areg (regs, srcreg) = srca;
54498: { int val = cctrue(8) ? 0xff : 0;
54499: m68k_incpc(2);
54500: fill_prefetch_2 ();
54501: put_byte(srca,val);
54502: }}}return 14;
54503: }
54504: unsigned long REGPARAM2 CPUFUNC(op_58e8_5)(uae_u32 opcode) /* Scc */
54505: {
54506: uae_u32 srcreg = (opcode & 7);
54507: OpcodeFamily = 59; CurrentInstrCycles = 16;
54508: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
54509: { int val = cctrue(8) ? 0xff : 0;
54510: m68k_incpc(4);
54511: fill_prefetch_0 ();
54512: put_byte(srca,val);
54513: }}}return 16;
54514: }
54515: unsigned long REGPARAM2 CPUFUNC(op_58f0_5)(uae_u32 opcode) /* Scc */
54516: {
54517: uae_u32 srcreg = (opcode & 7);
54518: OpcodeFamily = 59; CurrentInstrCycles = 18;
54519: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
54520: BusCyclePenalty += 2;
54521: { int val = cctrue(8) ? 0xff : 0;
54522: m68k_incpc(4);
54523: fill_prefetch_0 ();
54524: put_byte(srca,val);
54525: }}}return 18;
54526: }
54527: unsigned long REGPARAM2 CPUFUNC(op_58f8_5)(uae_u32 opcode) /* Scc */
54528: {
54529: OpcodeFamily = 59; CurrentInstrCycles = 16;
54530: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
54531: { int val = cctrue(8) ? 0xff : 0;
54532: m68k_incpc(4);
54533: fill_prefetch_0 ();
54534: put_byte(srca,val);
54535: }}}return 16;
54536: }
54537: unsigned long REGPARAM2 CPUFUNC(op_58f9_5)(uae_u32 opcode) /* Scc */
54538: {
54539: OpcodeFamily = 59; CurrentInstrCycles = 20;
54540: {{ uaecptr srca = get_ilong_prefetch(2);
54541: { int val = cctrue(8) ? 0xff : 0;
54542: m68k_incpc(6);
54543: fill_prefetch_0 ();
54544: put_byte(srca,val);
54545: }}}return 20;
54546: }
54547: unsigned long REGPARAM2 CPUFUNC(op_59c0_5)(uae_u32 opcode) /* Scc */
54548: {
54549: uae_u32 srcreg = (opcode & 7);
54550: OpcodeFamily = 59; CurrentInstrCycles = 4;
54551: {{{ int val = cctrue(9) ? 0xff : 0;
54552: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
54553: if (val) { m68k_incpc(2) ; return 4+2; }
54554: }}}m68k_incpc(2);
54555: fill_prefetch_2 ();
54556: return 4;
54557: }
54558: unsigned long REGPARAM2 CPUFUNC(op_59c8_5)(uae_u32 opcode) /* DBcc */
54559: {
54560: uae_u32 srcreg = (opcode & 7);
54561: OpcodeFamily = 58; CurrentInstrCycles = 12;
54562: {{ uae_s16 src = m68k_dreg(regs, srcreg);
54563: { uae_s16 offs = get_iword_prefetch(2);
54564: if (!cctrue(9)) {
54565: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
54566: if (src) {
54567: if (offs & 1) {
54568: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
54569: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
54570: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3103;
54571: }
54572: m68k_incpc((uae_s32)offs + 2);
54573: fill_prefetch_0 ();
54574: return 10;
54575: } else {
54576: m68k_incpc(4);
54577: fill_prefetch_0 ();
54578: return 14;
54579: }
54580: }
54581: }}}m68k_incpc(4);
54582: fill_prefetch_0 ();
54583: endlabel3103: ;
54584: return 12;
54585: }
54586: unsigned long REGPARAM2 CPUFUNC(op_59d0_5)(uae_u32 opcode) /* Scc */
54587: {
54588: uae_u32 srcreg = (opcode & 7);
54589: OpcodeFamily = 59; CurrentInstrCycles = 12;
54590: {{ uaecptr srca = m68k_areg(regs, srcreg);
54591: { int val = cctrue(9) ? 0xff : 0;
54592: m68k_incpc(2);
54593: fill_prefetch_2 ();
54594: put_byte(srca,val);
54595: }}}return 12;
54596: }
54597: unsigned long REGPARAM2 CPUFUNC(op_59d8_5)(uae_u32 opcode) /* Scc */
54598: {
54599: uae_u32 srcreg = (opcode & 7);
54600: OpcodeFamily = 59; CurrentInstrCycles = 12;
54601: {{ uaecptr srca = m68k_areg(regs, srcreg);
54602: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
54603: { int val = cctrue(9) ? 0xff : 0;
54604: m68k_incpc(2);
54605: fill_prefetch_2 ();
54606: put_byte(srca,val);
54607: }}}return 12;
54608: }
54609: unsigned long REGPARAM2 CPUFUNC(op_59e0_5)(uae_u32 opcode) /* Scc */
54610: {
54611: uae_u32 srcreg = (opcode & 7);
54612: OpcodeFamily = 59; CurrentInstrCycles = 14;
54613: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
54614: m68k_areg (regs, srcreg) = srca;
54615: { int val = cctrue(9) ? 0xff : 0;
54616: m68k_incpc(2);
54617: fill_prefetch_2 ();
54618: put_byte(srca,val);
54619: }}}return 14;
54620: }
54621: unsigned long REGPARAM2 CPUFUNC(op_59e8_5)(uae_u32 opcode) /* Scc */
54622: {
54623: uae_u32 srcreg = (opcode & 7);
54624: OpcodeFamily = 59; CurrentInstrCycles = 16;
54625: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
54626: { int val = cctrue(9) ? 0xff : 0;
54627: m68k_incpc(4);
54628: fill_prefetch_0 ();
54629: put_byte(srca,val);
54630: }}}return 16;
54631: }
54632: unsigned long REGPARAM2 CPUFUNC(op_59f0_5)(uae_u32 opcode) /* Scc */
54633: {
54634: uae_u32 srcreg = (opcode & 7);
54635: OpcodeFamily = 59; CurrentInstrCycles = 18;
54636: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
54637: BusCyclePenalty += 2;
54638: { int val = cctrue(9) ? 0xff : 0;
54639: m68k_incpc(4);
54640: fill_prefetch_0 ();
54641: put_byte(srca,val);
54642: }}}return 18;
54643: }
54644: unsigned long REGPARAM2 CPUFUNC(op_59f8_5)(uae_u32 opcode) /* Scc */
54645: {
54646: OpcodeFamily = 59; CurrentInstrCycles = 16;
54647: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
54648: { int val = cctrue(9) ? 0xff : 0;
54649: m68k_incpc(4);
54650: fill_prefetch_0 ();
54651: put_byte(srca,val);
54652: }}}return 16;
54653: }
54654: unsigned long REGPARAM2 CPUFUNC(op_59f9_5)(uae_u32 opcode) /* Scc */
54655: {
54656: OpcodeFamily = 59; CurrentInstrCycles = 20;
54657: {{ uaecptr srca = get_ilong_prefetch(2);
54658: { int val = cctrue(9) ? 0xff : 0;
54659: m68k_incpc(6);
54660: fill_prefetch_0 ();
54661: put_byte(srca,val);
54662: }}}return 20;
54663: }
54664: unsigned long REGPARAM2 CPUFUNC(op_5ac0_5)(uae_u32 opcode) /* Scc */
54665: {
54666: uae_u32 srcreg = (opcode & 7);
54667: OpcodeFamily = 59; CurrentInstrCycles = 4;
54668: {{{ int val = cctrue(10) ? 0xff : 0;
54669: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
54670: if (val) { m68k_incpc(2) ; return 4+2; }
54671: }}}m68k_incpc(2);
54672: fill_prefetch_2 ();
54673: return 4;
54674: }
54675: unsigned long REGPARAM2 CPUFUNC(op_5ac8_5)(uae_u32 opcode) /* DBcc */
54676: {
54677: uae_u32 srcreg = (opcode & 7);
54678: OpcodeFamily = 58; CurrentInstrCycles = 12;
54679: {{ uae_s16 src = m68k_dreg(regs, srcreg);
54680: { uae_s16 offs = get_iword_prefetch(2);
54681: if (!cctrue(10)) {
54682: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
54683: if (src) {
54684: if (offs & 1) {
54685: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
54686: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
54687: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3112;
54688: }
54689: m68k_incpc((uae_s32)offs + 2);
54690: fill_prefetch_0 ();
54691: return 10;
54692: } else {
54693: m68k_incpc(4);
54694: fill_prefetch_0 ();
54695: return 14;
54696: }
54697: }
54698: }}}m68k_incpc(4);
54699: fill_prefetch_0 ();
54700: endlabel3112: ;
54701: return 12;
54702: }
54703: unsigned long REGPARAM2 CPUFUNC(op_5ad0_5)(uae_u32 opcode) /* Scc */
54704: {
54705: uae_u32 srcreg = (opcode & 7);
54706: OpcodeFamily = 59; CurrentInstrCycles = 12;
54707: {{ uaecptr srca = m68k_areg(regs, srcreg);
54708: { int val = cctrue(10) ? 0xff : 0;
54709: m68k_incpc(2);
54710: fill_prefetch_2 ();
54711: put_byte(srca,val);
54712: }}}return 12;
54713: }
54714: unsigned long REGPARAM2 CPUFUNC(op_5ad8_5)(uae_u32 opcode) /* Scc */
54715: {
54716: uae_u32 srcreg = (opcode & 7);
54717: OpcodeFamily = 59; CurrentInstrCycles = 12;
54718: {{ uaecptr srca = m68k_areg(regs, srcreg);
54719: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
54720: { int val = cctrue(10) ? 0xff : 0;
54721: m68k_incpc(2);
54722: fill_prefetch_2 ();
54723: put_byte(srca,val);
54724: }}}return 12;
54725: }
54726: unsigned long REGPARAM2 CPUFUNC(op_5ae0_5)(uae_u32 opcode) /* Scc */
54727: {
54728: uae_u32 srcreg = (opcode & 7);
54729: OpcodeFamily = 59; CurrentInstrCycles = 14;
54730: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
54731: m68k_areg (regs, srcreg) = srca;
54732: { int val = cctrue(10) ? 0xff : 0;
54733: m68k_incpc(2);
54734: fill_prefetch_2 ();
54735: put_byte(srca,val);
54736: }}}return 14;
54737: }
54738: unsigned long REGPARAM2 CPUFUNC(op_5ae8_5)(uae_u32 opcode) /* Scc */
54739: {
54740: uae_u32 srcreg = (opcode & 7);
54741: OpcodeFamily = 59; CurrentInstrCycles = 16;
54742: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
54743: { int val = cctrue(10) ? 0xff : 0;
54744: m68k_incpc(4);
54745: fill_prefetch_0 ();
54746: put_byte(srca,val);
54747: }}}return 16;
54748: }
54749: unsigned long REGPARAM2 CPUFUNC(op_5af0_5)(uae_u32 opcode) /* Scc */
54750: {
54751: uae_u32 srcreg = (opcode & 7);
54752: OpcodeFamily = 59; CurrentInstrCycles = 18;
54753: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
54754: BusCyclePenalty += 2;
54755: { int val = cctrue(10) ? 0xff : 0;
54756: m68k_incpc(4);
54757: fill_prefetch_0 ();
54758: put_byte(srca,val);
54759: }}}return 18;
54760: }
54761: unsigned long REGPARAM2 CPUFUNC(op_5af8_5)(uae_u32 opcode) /* Scc */
54762: {
54763: OpcodeFamily = 59; CurrentInstrCycles = 16;
54764: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
54765: { int val = cctrue(10) ? 0xff : 0;
54766: m68k_incpc(4);
54767: fill_prefetch_0 ();
54768: put_byte(srca,val);
54769: }}}return 16;
54770: }
54771: unsigned long REGPARAM2 CPUFUNC(op_5af9_5)(uae_u32 opcode) /* Scc */
54772: {
54773: OpcodeFamily = 59; CurrentInstrCycles = 20;
54774: {{ uaecptr srca = get_ilong_prefetch(2);
54775: { int val = cctrue(10) ? 0xff : 0;
54776: m68k_incpc(6);
54777: fill_prefetch_0 ();
54778: put_byte(srca,val);
54779: }}}return 20;
54780: }
54781: unsigned long REGPARAM2 CPUFUNC(op_5bc0_5)(uae_u32 opcode) /* Scc */
54782: {
54783: uae_u32 srcreg = (opcode & 7);
54784: OpcodeFamily = 59; CurrentInstrCycles = 4;
54785: {{{ int val = cctrue(11) ? 0xff : 0;
54786: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
54787: if (val) { m68k_incpc(2) ; return 4+2; }
54788: }}}m68k_incpc(2);
54789: fill_prefetch_2 ();
54790: return 4;
54791: }
54792: unsigned long REGPARAM2 CPUFUNC(op_5bc8_5)(uae_u32 opcode) /* DBcc */
54793: {
54794: uae_u32 srcreg = (opcode & 7);
54795: OpcodeFamily = 58; CurrentInstrCycles = 12;
54796: {{ uae_s16 src = m68k_dreg(regs, srcreg);
54797: { uae_s16 offs = get_iword_prefetch(2);
54798: if (!cctrue(11)) {
54799: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
54800: if (src) {
54801: if (offs & 1) {
54802: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
54803: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
54804: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3121;
54805: }
54806: m68k_incpc((uae_s32)offs + 2);
54807: fill_prefetch_0 ();
54808: return 10;
54809: } else {
54810: m68k_incpc(4);
54811: fill_prefetch_0 ();
54812: return 14;
54813: }
54814: }
54815: }}}m68k_incpc(4);
54816: fill_prefetch_0 ();
54817: endlabel3121: ;
54818: return 12;
54819: }
54820: unsigned long REGPARAM2 CPUFUNC(op_5bd0_5)(uae_u32 opcode) /* Scc */
54821: {
54822: uae_u32 srcreg = (opcode & 7);
54823: OpcodeFamily = 59; CurrentInstrCycles = 12;
54824: {{ uaecptr srca = m68k_areg(regs, srcreg);
54825: { int val = cctrue(11) ? 0xff : 0;
54826: m68k_incpc(2);
54827: fill_prefetch_2 ();
54828: put_byte(srca,val);
54829: }}}return 12;
54830: }
54831: unsigned long REGPARAM2 CPUFUNC(op_5bd8_5)(uae_u32 opcode) /* Scc */
54832: {
54833: uae_u32 srcreg = (opcode & 7);
54834: OpcodeFamily = 59; CurrentInstrCycles = 12;
54835: {{ uaecptr srca = m68k_areg(regs, srcreg);
54836: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
54837: { int val = cctrue(11) ? 0xff : 0;
54838: m68k_incpc(2);
54839: fill_prefetch_2 ();
54840: put_byte(srca,val);
54841: }}}return 12;
54842: }
54843: unsigned long REGPARAM2 CPUFUNC(op_5be0_5)(uae_u32 opcode) /* Scc */
54844: {
54845: uae_u32 srcreg = (opcode & 7);
54846: OpcodeFamily = 59; CurrentInstrCycles = 14;
54847: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
54848: m68k_areg (regs, srcreg) = srca;
54849: { int val = cctrue(11) ? 0xff : 0;
54850: m68k_incpc(2);
54851: fill_prefetch_2 ();
54852: put_byte(srca,val);
54853: }}}return 14;
54854: }
54855: unsigned long REGPARAM2 CPUFUNC(op_5be8_5)(uae_u32 opcode) /* Scc */
54856: {
54857: uae_u32 srcreg = (opcode & 7);
54858: OpcodeFamily = 59; CurrentInstrCycles = 16;
54859: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
54860: { int val = cctrue(11) ? 0xff : 0;
54861: m68k_incpc(4);
54862: fill_prefetch_0 ();
54863: put_byte(srca,val);
54864: }}}return 16;
54865: }
54866: unsigned long REGPARAM2 CPUFUNC(op_5bf0_5)(uae_u32 opcode) /* Scc */
54867: {
54868: uae_u32 srcreg = (opcode & 7);
54869: OpcodeFamily = 59; CurrentInstrCycles = 18;
54870: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
54871: BusCyclePenalty += 2;
54872: { int val = cctrue(11) ? 0xff : 0;
54873: m68k_incpc(4);
54874: fill_prefetch_0 ();
54875: put_byte(srca,val);
54876: }}}return 18;
54877: }
54878: unsigned long REGPARAM2 CPUFUNC(op_5bf8_5)(uae_u32 opcode) /* Scc */
54879: {
54880: OpcodeFamily = 59; CurrentInstrCycles = 16;
54881: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
54882: { int val = cctrue(11) ? 0xff : 0;
54883: m68k_incpc(4);
54884: fill_prefetch_0 ();
54885: put_byte(srca,val);
54886: }}}return 16;
54887: }
54888: unsigned long REGPARAM2 CPUFUNC(op_5bf9_5)(uae_u32 opcode) /* Scc */
54889: {
54890: OpcodeFamily = 59; CurrentInstrCycles = 20;
54891: {{ uaecptr srca = get_ilong_prefetch(2);
54892: { int val = cctrue(11) ? 0xff : 0;
54893: m68k_incpc(6);
54894: fill_prefetch_0 ();
54895: put_byte(srca,val);
54896: }}}return 20;
54897: }
54898: unsigned long REGPARAM2 CPUFUNC(op_5cc0_5)(uae_u32 opcode) /* Scc */
54899: {
54900: uae_u32 srcreg = (opcode & 7);
54901: OpcodeFamily = 59; CurrentInstrCycles = 4;
54902: {{{ int val = cctrue(12) ? 0xff : 0;
54903: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
54904: if (val) { m68k_incpc(2) ; return 4+2; }
54905: }}}m68k_incpc(2);
54906: fill_prefetch_2 ();
54907: return 4;
54908: }
54909: unsigned long REGPARAM2 CPUFUNC(op_5cc8_5)(uae_u32 opcode) /* DBcc */
54910: {
54911: uae_u32 srcreg = (opcode & 7);
54912: OpcodeFamily = 58; CurrentInstrCycles = 12;
54913: {{ uae_s16 src = m68k_dreg(regs, srcreg);
54914: { uae_s16 offs = get_iword_prefetch(2);
54915: if (!cctrue(12)) {
54916: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
54917: if (src) {
54918: if (offs & 1) {
54919: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
54920: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
54921: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3130;
54922: }
54923: m68k_incpc((uae_s32)offs + 2);
54924: fill_prefetch_0 ();
54925: return 10;
54926: } else {
54927: m68k_incpc(4);
54928: fill_prefetch_0 ();
54929: return 14;
54930: }
54931: }
54932: }}}m68k_incpc(4);
54933: fill_prefetch_0 ();
54934: endlabel3130: ;
54935: return 12;
54936: }
54937: unsigned long REGPARAM2 CPUFUNC(op_5cd0_5)(uae_u32 opcode) /* Scc */
54938: {
54939: uae_u32 srcreg = (opcode & 7);
54940: OpcodeFamily = 59; CurrentInstrCycles = 12;
54941: {{ uaecptr srca = m68k_areg(regs, srcreg);
54942: { int val = cctrue(12) ? 0xff : 0;
54943: m68k_incpc(2);
54944: fill_prefetch_2 ();
54945: put_byte(srca,val);
54946: }}}return 12;
54947: }
54948: unsigned long REGPARAM2 CPUFUNC(op_5cd8_5)(uae_u32 opcode) /* Scc */
54949: {
54950: uae_u32 srcreg = (opcode & 7);
54951: OpcodeFamily = 59; CurrentInstrCycles = 12;
54952: {{ uaecptr srca = m68k_areg(regs, srcreg);
54953: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
54954: { int val = cctrue(12) ? 0xff : 0;
54955: m68k_incpc(2);
54956: fill_prefetch_2 ();
54957: put_byte(srca,val);
54958: }}}return 12;
54959: }
54960: unsigned long REGPARAM2 CPUFUNC(op_5ce0_5)(uae_u32 opcode) /* Scc */
54961: {
54962: uae_u32 srcreg = (opcode & 7);
54963: OpcodeFamily = 59; CurrentInstrCycles = 14;
54964: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
54965: m68k_areg (regs, srcreg) = srca;
54966: { int val = cctrue(12) ? 0xff : 0;
54967: m68k_incpc(2);
54968: fill_prefetch_2 ();
54969: put_byte(srca,val);
54970: }}}return 14;
54971: }
54972: unsigned long REGPARAM2 CPUFUNC(op_5ce8_5)(uae_u32 opcode) /* Scc */
54973: {
54974: uae_u32 srcreg = (opcode & 7);
54975: OpcodeFamily = 59; CurrentInstrCycles = 16;
54976: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
54977: { int val = cctrue(12) ? 0xff : 0;
54978: m68k_incpc(4);
54979: fill_prefetch_0 ();
54980: put_byte(srca,val);
54981: }}}return 16;
54982: }
54983: unsigned long REGPARAM2 CPUFUNC(op_5cf0_5)(uae_u32 opcode) /* Scc */
54984: {
54985: uae_u32 srcreg = (opcode & 7);
54986: OpcodeFamily = 59; CurrentInstrCycles = 18;
54987: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
54988: BusCyclePenalty += 2;
54989: { int val = cctrue(12) ? 0xff : 0;
54990: m68k_incpc(4);
54991: fill_prefetch_0 ();
54992: put_byte(srca,val);
54993: }}}return 18;
54994: }
54995: unsigned long REGPARAM2 CPUFUNC(op_5cf8_5)(uae_u32 opcode) /* Scc */
54996: {
54997: OpcodeFamily = 59; CurrentInstrCycles = 16;
54998: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
54999: { int val = cctrue(12) ? 0xff : 0;
55000: m68k_incpc(4);
55001: fill_prefetch_0 ();
55002: put_byte(srca,val);
55003: }}}return 16;
55004: }
55005: unsigned long REGPARAM2 CPUFUNC(op_5cf9_5)(uae_u32 opcode) /* Scc */
55006: {
55007: OpcodeFamily = 59; CurrentInstrCycles = 20;
55008: {{ uaecptr srca = get_ilong_prefetch(2);
55009: { int val = cctrue(12) ? 0xff : 0;
55010: m68k_incpc(6);
55011: fill_prefetch_0 ();
55012: put_byte(srca,val);
55013: }}}return 20;
55014: }
55015: unsigned long REGPARAM2 CPUFUNC(op_5dc0_5)(uae_u32 opcode) /* Scc */
55016: {
55017: uae_u32 srcreg = (opcode & 7);
55018: OpcodeFamily = 59; CurrentInstrCycles = 4;
55019: {{{ int val = cctrue(13) ? 0xff : 0;
55020: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
55021: if (val) { m68k_incpc(2) ; return 4+2; }
55022: }}}m68k_incpc(2);
55023: fill_prefetch_2 ();
55024: return 4;
55025: }
55026: unsigned long REGPARAM2 CPUFUNC(op_5dc8_5)(uae_u32 opcode) /* DBcc */
55027: {
55028: uae_u32 srcreg = (opcode & 7);
55029: OpcodeFamily = 58; CurrentInstrCycles = 12;
55030: {{ uae_s16 src = m68k_dreg(regs, srcreg);
55031: { uae_s16 offs = get_iword_prefetch(2);
55032: if (!cctrue(13)) {
55033: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
55034: if (src) {
55035: if (offs & 1) {
55036: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
55037: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
55038: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3139;
55039: }
55040: m68k_incpc((uae_s32)offs + 2);
55041: fill_prefetch_0 ();
55042: return 10;
55043: } else {
55044: m68k_incpc(4);
55045: fill_prefetch_0 ();
55046: return 14;
55047: }
55048: }
55049: }}}m68k_incpc(4);
55050: fill_prefetch_0 ();
55051: endlabel3139: ;
55052: return 12;
55053: }
55054: unsigned long REGPARAM2 CPUFUNC(op_5dd0_5)(uae_u32 opcode) /* Scc */
55055: {
55056: uae_u32 srcreg = (opcode & 7);
55057: OpcodeFamily = 59; CurrentInstrCycles = 12;
55058: {{ uaecptr srca = m68k_areg(regs, srcreg);
55059: { int val = cctrue(13) ? 0xff : 0;
55060: m68k_incpc(2);
55061: fill_prefetch_2 ();
55062: put_byte(srca,val);
55063: }}}return 12;
55064: }
55065: unsigned long REGPARAM2 CPUFUNC(op_5dd8_5)(uae_u32 opcode) /* Scc */
55066: {
55067: uae_u32 srcreg = (opcode & 7);
55068: OpcodeFamily = 59; CurrentInstrCycles = 12;
55069: {{ uaecptr srca = m68k_areg(regs, srcreg);
55070: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
55071: { int val = cctrue(13) ? 0xff : 0;
55072: m68k_incpc(2);
55073: fill_prefetch_2 ();
55074: put_byte(srca,val);
55075: }}}return 12;
55076: }
55077: unsigned long REGPARAM2 CPUFUNC(op_5de0_5)(uae_u32 opcode) /* Scc */
55078: {
55079: uae_u32 srcreg = (opcode & 7);
55080: OpcodeFamily = 59; CurrentInstrCycles = 14;
55081: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
55082: m68k_areg (regs, srcreg) = srca;
55083: { int val = cctrue(13) ? 0xff : 0;
55084: m68k_incpc(2);
55085: fill_prefetch_2 ();
55086: put_byte(srca,val);
55087: }}}return 14;
55088: }
55089: unsigned long REGPARAM2 CPUFUNC(op_5de8_5)(uae_u32 opcode) /* Scc */
55090: {
55091: uae_u32 srcreg = (opcode & 7);
55092: OpcodeFamily = 59; CurrentInstrCycles = 16;
55093: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
55094: { int val = cctrue(13) ? 0xff : 0;
55095: m68k_incpc(4);
55096: fill_prefetch_0 ();
55097: put_byte(srca,val);
55098: }}}return 16;
55099: }
55100: unsigned long REGPARAM2 CPUFUNC(op_5df0_5)(uae_u32 opcode) /* Scc */
55101: {
55102: uae_u32 srcreg = (opcode & 7);
55103: OpcodeFamily = 59; CurrentInstrCycles = 18;
55104: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
55105: BusCyclePenalty += 2;
55106: { int val = cctrue(13) ? 0xff : 0;
55107: m68k_incpc(4);
55108: fill_prefetch_0 ();
55109: put_byte(srca,val);
55110: }}}return 18;
55111: }
55112: unsigned long REGPARAM2 CPUFUNC(op_5df8_5)(uae_u32 opcode) /* Scc */
55113: {
55114: OpcodeFamily = 59; CurrentInstrCycles = 16;
55115: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
55116: { int val = cctrue(13) ? 0xff : 0;
55117: m68k_incpc(4);
55118: fill_prefetch_0 ();
55119: put_byte(srca,val);
55120: }}}return 16;
55121: }
55122: unsigned long REGPARAM2 CPUFUNC(op_5df9_5)(uae_u32 opcode) /* Scc */
55123: {
55124: OpcodeFamily = 59; CurrentInstrCycles = 20;
55125: {{ uaecptr srca = get_ilong_prefetch(2);
55126: { int val = cctrue(13) ? 0xff : 0;
55127: m68k_incpc(6);
55128: fill_prefetch_0 ();
55129: put_byte(srca,val);
55130: }}}return 20;
55131: }
55132: unsigned long REGPARAM2 CPUFUNC(op_5ec0_5)(uae_u32 opcode) /* Scc */
55133: {
55134: uae_u32 srcreg = (opcode & 7);
55135: OpcodeFamily = 59; CurrentInstrCycles = 4;
55136: {{{ int val = cctrue(14) ? 0xff : 0;
55137: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
55138: if (val) { m68k_incpc(2) ; return 4+2; }
55139: }}}m68k_incpc(2);
55140: fill_prefetch_2 ();
55141: return 4;
55142: }
55143: unsigned long REGPARAM2 CPUFUNC(op_5ec8_5)(uae_u32 opcode) /* DBcc */
55144: {
55145: uae_u32 srcreg = (opcode & 7);
55146: OpcodeFamily = 58; CurrentInstrCycles = 12;
55147: {{ uae_s16 src = m68k_dreg(regs, srcreg);
55148: { uae_s16 offs = get_iword_prefetch(2);
55149: if (!cctrue(14)) {
55150: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
55151: if (src) {
55152: if (offs & 1) {
55153: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
55154: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
55155: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3148;
55156: }
55157: m68k_incpc((uae_s32)offs + 2);
55158: fill_prefetch_0 ();
55159: return 10;
55160: } else {
55161: m68k_incpc(4);
55162: fill_prefetch_0 ();
55163: return 14;
55164: }
55165: }
55166: }}}m68k_incpc(4);
55167: fill_prefetch_0 ();
55168: endlabel3148: ;
55169: return 12;
55170: }
55171: unsigned long REGPARAM2 CPUFUNC(op_5ed0_5)(uae_u32 opcode) /* Scc */
55172: {
55173: uae_u32 srcreg = (opcode & 7);
55174: OpcodeFamily = 59; CurrentInstrCycles = 12;
55175: {{ uaecptr srca = m68k_areg(regs, srcreg);
55176: { int val = cctrue(14) ? 0xff : 0;
55177: m68k_incpc(2);
55178: fill_prefetch_2 ();
55179: put_byte(srca,val);
55180: }}}return 12;
55181: }
55182: unsigned long REGPARAM2 CPUFUNC(op_5ed8_5)(uae_u32 opcode) /* Scc */
55183: {
55184: uae_u32 srcreg = (opcode & 7);
55185: OpcodeFamily = 59; CurrentInstrCycles = 12;
55186: {{ uaecptr srca = m68k_areg(regs, srcreg);
55187: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
55188: { int val = cctrue(14) ? 0xff : 0;
55189: m68k_incpc(2);
55190: fill_prefetch_2 ();
55191: put_byte(srca,val);
55192: }}}return 12;
55193: }
55194: unsigned long REGPARAM2 CPUFUNC(op_5ee0_5)(uae_u32 opcode) /* Scc */
55195: {
55196: uae_u32 srcreg = (opcode & 7);
55197: OpcodeFamily = 59; CurrentInstrCycles = 14;
55198: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
55199: m68k_areg (regs, srcreg) = srca;
55200: { int val = cctrue(14) ? 0xff : 0;
55201: m68k_incpc(2);
55202: fill_prefetch_2 ();
55203: put_byte(srca,val);
55204: }}}return 14;
55205: }
55206: unsigned long REGPARAM2 CPUFUNC(op_5ee8_5)(uae_u32 opcode) /* Scc */
55207: {
55208: uae_u32 srcreg = (opcode & 7);
55209: OpcodeFamily = 59; CurrentInstrCycles = 16;
55210: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
55211: { int val = cctrue(14) ? 0xff : 0;
55212: m68k_incpc(4);
55213: fill_prefetch_0 ();
55214: put_byte(srca,val);
55215: }}}return 16;
55216: }
55217: unsigned long REGPARAM2 CPUFUNC(op_5ef0_5)(uae_u32 opcode) /* Scc */
55218: {
55219: uae_u32 srcreg = (opcode & 7);
55220: OpcodeFamily = 59; CurrentInstrCycles = 18;
55221: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
55222: BusCyclePenalty += 2;
55223: { int val = cctrue(14) ? 0xff : 0;
55224: m68k_incpc(4);
55225: fill_prefetch_0 ();
55226: put_byte(srca,val);
55227: }}}return 18;
55228: }
55229: unsigned long REGPARAM2 CPUFUNC(op_5ef8_5)(uae_u32 opcode) /* Scc */
55230: {
55231: OpcodeFamily = 59; CurrentInstrCycles = 16;
55232: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
55233: { int val = cctrue(14) ? 0xff : 0;
55234: m68k_incpc(4);
55235: fill_prefetch_0 ();
55236: put_byte(srca,val);
55237: }}}return 16;
55238: }
55239: unsigned long REGPARAM2 CPUFUNC(op_5ef9_5)(uae_u32 opcode) /* Scc */
55240: {
55241: OpcodeFamily = 59; CurrentInstrCycles = 20;
55242: {{ uaecptr srca = get_ilong_prefetch(2);
55243: { int val = cctrue(14) ? 0xff : 0;
55244: m68k_incpc(6);
55245: fill_prefetch_0 ();
55246: put_byte(srca,val);
55247: }}}return 20;
55248: }
55249: unsigned long REGPARAM2 CPUFUNC(op_5fc0_5)(uae_u32 opcode) /* Scc */
55250: {
55251: uae_u32 srcreg = (opcode & 7);
55252: OpcodeFamily = 59; CurrentInstrCycles = 4;
55253: {{{ int val = cctrue(15) ? 0xff : 0;
55254: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
55255: if (val) { m68k_incpc(2) ; return 4+2; }
55256: }}}m68k_incpc(2);
55257: fill_prefetch_2 ();
55258: return 4;
55259: }
55260: unsigned long REGPARAM2 CPUFUNC(op_5fc8_5)(uae_u32 opcode) /* DBcc */
55261: {
55262: uae_u32 srcreg = (opcode & 7);
55263: OpcodeFamily = 58; CurrentInstrCycles = 12;
55264: {{ uae_s16 src = m68k_dreg(regs, srcreg);
55265: { uae_s16 offs = get_iword_prefetch(2);
55266: if (!cctrue(15)) {
55267: m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
55268: if (src) {
55269: if (offs & 1) {
55270: last_addr_for_exception_3 = m68k_getpc() + 2 + 2;
55271: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;
55272: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3157;
55273: }
55274: m68k_incpc((uae_s32)offs + 2);
55275: fill_prefetch_0 ();
55276: return 10;
55277: } else {
55278: m68k_incpc(4);
55279: fill_prefetch_0 ();
55280: return 14;
55281: }
55282: }
55283: }}}m68k_incpc(4);
55284: fill_prefetch_0 ();
55285: endlabel3157: ;
55286: return 12;
55287: }
55288: unsigned long REGPARAM2 CPUFUNC(op_5fd0_5)(uae_u32 opcode) /* Scc */
55289: {
55290: uae_u32 srcreg = (opcode & 7);
55291: OpcodeFamily = 59; CurrentInstrCycles = 12;
55292: {{ uaecptr srca = m68k_areg(regs, srcreg);
55293: { int val = cctrue(15) ? 0xff : 0;
55294: m68k_incpc(2);
55295: fill_prefetch_2 ();
55296: put_byte(srca,val);
55297: }}}return 12;
55298: }
55299: unsigned long REGPARAM2 CPUFUNC(op_5fd8_5)(uae_u32 opcode) /* Scc */
55300: {
55301: uae_u32 srcreg = (opcode & 7);
55302: OpcodeFamily = 59; CurrentInstrCycles = 12;
55303: {{ uaecptr srca = m68k_areg(regs, srcreg);
55304: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
55305: { int val = cctrue(15) ? 0xff : 0;
55306: m68k_incpc(2);
55307: fill_prefetch_2 ();
55308: put_byte(srca,val);
55309: }}}return 12;
55310: }
55311: unsigned long REGPARAM2 CPUFUNC(op_5fe0_5)(uae_u32 opcode) /* Scc */
55312: {
55313: uae_u32 srcreg = (opcode & 7);
55314: OpcodeFamily = 59; CurrentInstrCycles = 14;
55315: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
55316: m68k_areg (regs, srcreg) = srca;
55317: { int val = cctrue(15) ? 0xff : 0;
55318: m68k_incpc(2);
55319: fill_prefetch_2 ();
55320: put_byte(srca,val);
55321: }}}return 14;
55322: }
55323: #endif
55324:
55325: #ifdef PART_6
55326: unsigned long REGPARAM2 CPUFUNC(op_5fe8_5)(uae_u32 opcode) /* Scc */
55327: {
55328: uae_u32 srcreg = (opcode & 7);
55329: OpcodeFamily = 59; CurrentInstrCycles = 16;
55330: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
55331: { int val = cctrue(15) ? 0xff : 0;
55332: m68k_incpc(4);
55333: fill_prefetch_0 ();
55334: put_byte(srca,val);
55335: }}}return 16;
55336: }
55337: unsigned long REGPARAM2 CPUFUNC(op_5ff0_5)(uae_u32 opcode) /* Scc */
55338: {
55339: uae_u32 srcreg = (opcode & 7);
55340: OpcodeFamily = 59; CurrentInstrCycles = 18;
55341: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
55342: BusCyclePenalty += 2;
55343: { int val = cctrue(15) ? 0xff : 0;
55344: m68k_incpc(4);
55345: fill_prefetch_0 ();
55346: put_byte(srca,val);
55347: }}}return 18;
55348: }
55349: unsigned long REGPARAM2 CPUFUNC(op_5ff8_5)(uae_u32 opcode) /* Scc */
55350: {
55351: OpcodeFamily = 59; CurrentInstrCycles = 16;
55352: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
55353: { int val = cctrue(15) ? 0xff : 0;
55354: m68k_incpc(4);
55355: fill_prefetch_0 ();
55356: put_byte(srca,val);
55357: }}}return 16;
55358: }
55359: unsigned long REGPARAM2 CPUFUNC(op_5ff9_5)(uae_u32 opcode) /* Scc */
55360: {
55361: OpcodeFamily = 59; CurrentInstrCycles = 20;
55362: {{ uaecptr srca = get_ilong_prefetch(2);
55363: { int val = cctrue(15) ? 0xff : 0;
55364: m68k_incpc(6);
55365: fill_prefetch_0 ();
55366: put_byte(srca,val);
55367: }}}return 20;
55368: }
55369: unsigned long REGPARAM2 CPUFUNC(op_6000_5)(uae_u32 opcode) /* Bcc */
55370: {
55371: OpcodeFamily = 55; CurrentInstrCycles = 12;
55372: {{ uae_s16 src = get_iword_prefetch(2);
55373: if (!cctrue(0)) goto didnt_jump;
55374: if (src & 1) {
55375: last_addr_for_exception_3 = m68k_getpc() + 2;
55376: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55377: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3165;
55378: }
55379: m68k_incpc ((uae_s32)src + 2);
55380: fill_prefetch_0 ();
55381: return 10;
55382: didnt_jump:;
55383: }}m68k_incpc(4);
55384: fill_prefetch_0 ();
55385: endlabel3165: ;
55386: return 12;
55387: }
55388: unsigned long REGPARAM2 CPUFUNC(op_6001_5)(uae_u32 opcode) /* Bcc */
55389: {
55390: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55391: OpcodeFamily = 55; CurrentInstrCycles = 8;
55392: {{ uae_u32 src = srcreg;
55393: if (!cctrue(0)) goto didnt_jump;
55394: if (src & 1) {
55395: last_addr_for_exception_3 = m68k_getpc() + 2;
55396: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55397: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3166;
55398: }
55399: m68k_incpc ((uae_s32)src + 2);
55400: fill_prefetch_0 ();
55401: return 10;
55402: didnt_jump:;
55403: }}m68k_incpc(2);
55404: fill_prefetch_2 ();
55405: endlabel3166: ;
55406: return 8;
55407: }
55408: unsigned long REGPARAM2 CPUFUNC(op_60ff_5)(uae_u32 opcode) /* Bcc */
55409: {
55410: OpcodeFamily = 55; CurrentInstrCycles = 12;
55411: { m68k_incpc(2);
55412: if (!cctrue(0)) goto endlabel3167;
55413: last_addr_for_exception_3 = m68k_getpc() + 2;
55414: last_fault_for_exception_3 = m68k_getpc() + 1;
55415: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3167;
55416: { uae_s32 src = get_ilong_prefetch(2);
55417: if (!cctrue(0)) goto didnt_jump;
55418: if (src & 1) {
55419: last_addr_for_exception_3 = m68k_getpc() + 2;
55420: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55421: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3167;
55422: }
55423: m68k_incpc ((uae_s32)src + 2);
55424: fill_prefetch_0 ();
55425: return 10;
55426: didnt_jump:;
55427: }}m68k_incpc(6);
55428: fill_prefetch_0 ();
55429: endlabel3167: ;
55430: return 12;
55431: }
55432: unsigned long REGPARAM2 CPUFUNC(op_6100_5)(uae_u32 opcode) /* BSR */
55433: {
55434: OpcodeFamily = 54; CurrentInstrCycles = 18;
55435: {{ uae_s16 src = get_iword_prefetch(2);
55436: uae_s32 s = (uae_s32)src + 2;
55437: if (src & 1) {
55438: last_addr_for_exception_3 = m68k_getpc() + 2;
55439: last_fault_for_exception_3 = m68k_getpc() + s;
55440: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3168;
55441: }
55442: m68k_do_bsr(m68k_getpc() + 4, s);
55443: fill_prefetch_0 ();
55444: }}endlabel3168: ;
55445: return 18;
55446: }
55447: unsigned long REGPARAM2 CPUFUNC(op_6101_5)(uae_u32 opcode) /* BSR */
55448: {
55449: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55450: OpcodeFamily = 54; CurrentInstrCycles = 18;
55451: {{ uae_u32 src = srcreg;
55452: uae_s32 s = (uae_s32)src + 2;
55453: if (src & 1) {
55454: last_addr_for_exception_3 = m68k_getpc() + 2;
55455: last_fault_for_exception_3 = m68k_getpc() + s;
55456: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3169;
55457: }
55458: m68k_do_bsr(m68k_getpc() + 2, s);
55459: fill_prefetch_0 ();
55460: }}endlabel3169: ;
55461: return 18;
55462: }
55463: unsigned long REGPARAM2 CPUFUNC(op_61ff_5)(uae_u32 opcode) /* BSR */
55464: {
55465: OpcodeFamily = 54; CurrentInstrCycles = 18;
55466: {{ uae_s32 src = get_ilong_prefetch(2);
55467: uae_s32 s = (uae_s32)src + 2;
55468: if (src & 1) {
55469: last_addr_for_exception_3 = m68k_getpc() + 2;
55470: last_fault_for_exception_3 = m68k_getpc() + s;
55471: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3170;
55472: }
55473: m68k_do_bsr(m68k_getpc() + 6, s);
55474: fill_prefetch_0 ();
55475: }}endlabel3170: ;
55476: return 18;
55477: }
55478: unsigned long REGPARAM2 CPUFUNC(op_6200_5)(uae_u32 opcode) /* Bcc */
55479: {
55480: OpcodeFamily = 55; CurrentInstrCycles = 12;
55481: {{ uae_s16 src = get_iword_prefetch(2);
55482: if (!cctrue(2)) goto didnt_jump;
55483: if (src & 1) {
55484: last_addr_for_exception_3 = m68k_getpc() + 2;
55485: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55486: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3171;
55487: }
55488: m68k_incpc ((uae_s32)src + 2);
55489: fill_prefetch_0 ();
55490: return 10;
55491: didnt_jump:;
55492: }}m68k_incpc(4);
55493: fill_prefetch_0 ();
55494: endlabel3171: ;
55495: return 12;
55496: }
55497: unsigned long REGPARAM2 CPUFUNC(op_6201_5)(uae_u32 opcode) /* Bcc */
55498: {
55499: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55500: OpcodeFamily = 55; CurrentInstrCycles = 8;
55501: {{ uae_u32 src = srcreg;
55502: if (!cctrue(2)) goto didnt_jump;
55503: if (src & 1) {
55504: last_addr_for_exception_3 = m68k_getpc() + 2;
55505: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55506: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3172;
55507: }
55508: m68k_incpc ((uae_s32)src + 2);
55509: fill_prefetch_0 ();
55510: return 10;
55511: didnt_jump:;
55512: }}m68k_incpc(2);
55513: fill_prefetch_2 ();
55514: endlabel3172: ;
55515: return 8;
55516: }
55517: unsigned long REGPARAM2 CPUFUNC(op_62ff_5)(uae_u32 opcode) /* Bcc */
55518: {
55519: OpcodeFamily = 55; CurrentInstrCycles = 12;
55520: { m68k_incpc(2);
55521: if (!cctrue(2)) goto endlabel3173;
55522: last_addr_for_exception_3 = m68k_getpc() + 2;
55523: last_fault_for_exception_3 = m68k_getpc() + 1;
55524: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3173;
55525: { uae_s32 src = get_ilong_prefetch(2);
55526: if (!cctrue(2)) goto didnt_jump;
55527: if (src & 1) {
55528: last_addr_for_exception_3 = m68k_getpc() + 2;
55529: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55530: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3173;
55531: }
55532: m68k_incpc ((uae_s32)src + 2);
55533: fill_prefetch_0 ();
55534: return 10;
55535: didnt_jump:;
55536: }}m68k_incpc(6);
55537: fill_prefetch_0 ();
55538: endlabel3173: ;
55539: return 12;
55540: }
55541: unsigned long REGPARAM2 CPUFUNC(op_6300_5)(uae_u32 opcode) /* Bcc */
55542: {
55543: OpcodeFamily = 55; CurrentInstrCycles = 12;
55544: {{ uae_s16 src = get_iword_prefetch(2);
55545: if (!cctrue(3)) goto didnt_jump;
55546: if (src & 1) {
55547: last_addr_for_exception_3 = m68k_getpc() + 2;
55548: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55549: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3174;
55550: }
55551: m68k_incpc ((uae_s32)src + 2);
55552: fill_prefetch_0 ();
55553: return 10;
55554: didnt_jump:;
55555: }}m68k_incpc(4);
55556: fill_prefetch_0 ();
55557: endlabel3174: ;
55558: return 12;
55559: }
55560: unsigned long REGPARAM2 CPUFUNC(op_6301_5)(uae_u32 opcode) /* Bcc */
55561: {
55562: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55563: OpcodeFamily = 55; CurrentInstrCycles = 8;
55564: {{ uae_u32 src = srcreg;
55565: if (!cctrue(3)) goto didnt_jump;
55566: if (src & 1) {
55567: last_addr_for_exception_3 = m68k_getpc() + 2;
55568: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55569: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3175;
55570: }
55571: m68k_incpc ((uae_s32)src + 2);
55572: fill_prefetch_0 ();
55573: return 10;
55574: didnt_jump:;
55575: }}m68k_incpc(2);
55576: fill_prefetch_2 ();
55577: endlabel3175: ;
55578: return 8;
55579: }
55580: unsigned long REGPARAM2 CPUFUNC(op_63ff_5)(uae_u32 opcode) /* Bcc */
55581: {
55582: OpcodeFamily = 55; CurrentInstrCycles = 12;
55583: { m68k_incpc(2);
55584: if (!cctrue(3)) goto endlabel3176;
55585: last_addr_for_exception_3 = m68k_getpc() + 2;
55586: last_fault_for_exception_3 = m68k_getpc() + 1;
55587: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3176;
55588: { uae_s32 src = get_ilong_prefetch(2);
55589: if (!cctrue(3)) goto didnt_jump;
55590: if (src & 1) {
55591: last_addr_for_exception_3 = m68k_getpc() + 2;
55592: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55593: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3176;
55594: }
55595: m68k_incpc ((uae_s32)src + 2);
55596: fill_prefetch_0 ();
55597: return 10;
55598: didnt_jump:;
55599: }}m68k_incpc(6);
55600: fill_prefetch_0 ();
55601: endlabel3176: ;
55602: return 12;
55603: }
55604: unsigned long REGPARAM2 CPUFUNC(op_6400_5)(uae_u32 opcode) /* Bcc */
55605: {
55606: OpcodeFamily = 55; CurrentInstrCycles = 12;
55607: {{ uae_s16 src = get_iword_prefetch(2);
55608: if (!cctrue(4)) goto didnt_jump;
55609: if (src & 1) {
55610: last_addr_for_exception_3 = m68k_getpc() + 2;
55611: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55612: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3177;
55613: }
55614: m68k_incpc ((uae_s32)src + 2);
55615: fill_prefetch_0 ();
55616: return 10;
55617: didnt_jump:;
55618: }}m68k_incpc(4);
55619: fill_prefetch_0 ();
55620: endlabel3177: ;
55621: return 12;
55622: }
55623: unsigned long REGPARAM2 CPUFUNC(op_6401_5)(uae_u32 opcode) /* Bcc */
55624: {
55625: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55626: OpcodeFamily = 55; CurrentInstrCycles = 8;
55627: {{ uae_u32 src = srcreg;
55628: if (!cctrue(4)) goto didnt_jump;
55629: if (src & 1) {
55630: last_addr_for_exception_3 = m68k_getpc() + 2;
55631: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55632: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3178;
55633: }
55634: m68k_incpc ((uae_s32)src + 2);
55635: fill_prefetch_0 ();
55636: return 10;
55637: didnt_jump:;
55638: }}m68k_incpc(2);
55639: fill_prefetch_2 ();
55640: endlabel3178: ;
55641: return 8;
55642: }
55643: unsigned long REGPARAM2 CPUFUNC(op_64ff_5)(uae_u32 opcode) /* Bcc */
55644: {
55645: OpcodeFamily = 55; CurrentInstrCycles = 12;
55646: { m68k_incpc(2);
55647: if (!cctrue(4)) goto endlabel3179;
55648: last_addr_for_exception_3 = m68k_getpc() + 2;
55649: last_fault_for_exception_3 = m68k_getpc() + 1;
55650: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3179;
55651: { uae_s32 src = get_ilong_prefetch(2);
55652: if (!cctrue(4)) goto didnt_jump;
55653: if (src & 1) {
55654: last_addr_for_exception_3 = m68k_getpc() + 2;
55655: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55656: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3179;
55657: }
55658: m68k_incpc ((uae_s32)src + 2);
55659: fill_prefetch_0 ();
55660: return 10;
55661: didnt_jump:;
55662: }}m68k_incpc(6);
55663: fill_prefetch_0 ();
55664: endlabel3179: ;
55665: return 12;
55666: }
55667: unsigned long REGPARAM2 CPUFUNC(op_6500_5)(uae_u32 opcode) /* Bcc */
55668: {
55669: OpcodeFamily = 55; CurrentInstrCycles = 12;
55670: {{ uae_s16 src = get_iword_prefetch(2);
55671: if (!cctrue(5)) goto didnt_jump;
55672: if (src & 1) {
55673: last_addr_for_exception_3 = m68k_getpc() + 2;
55674: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55675: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3180;
55676: }
55677: m68k_incpc ((uae_s32)src + 2);
55678: fill_prefetch_0 ();
55679: return 10;
55680: didnt_jump:;
55681: }}m68k_incpc(4);
55682: fill_prefetch_0 ();
55683: endlabel3180: ;
55684: return 12;
55685: }
55686: unsigned long REGPARAM2 CPUFUNC(op_6501_5)(uae_u32 opcode) /* Bcc */
55687: {
55688: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55689: OpcodeFamily = 55; CurrentInstrCycles = 8;
55690: {{ uae_u32 src = srcreg;
55691: if (!cctrue(5)) goto didnt_jump;
55692: if (src & 1) {
55693: last_addr_for_exception_3 = m68k_getpc() + 2;
55694: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55695: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3181;
55696: }
55697: m68k_incpc ((uae_s32)src + 2);
55698: fill_prefetch_0 ();
55699: return 10;
55700: didnt_jump:;
55701: }}m68k_incpc(2);
55702: fill_prefetch_2 ();
55703: endlabel3181: ;
55704: return 8;
55705: }
55706: unsigned long REGPARAM2 CPUFUNC(op_65ff_5)(uae_u32 opcode) /* Bcc */
55707: {
55708: OpcodeFamily = 55; CurrentInstrCycles = 12;
55709: { m68k_incpc(2);
55710: if (!cctrue(5)) goto endlabel3182;
55711: last_addr_for_exception_3 = m68k_getpc() + 2;
55712: last_fault_for_exception_3 = m68k_getpc() + 1;
55713: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3182;
55714: { uae_s32 src = get_ilong_prefetch(2);
55715: if (!cctrue(5)) goto didnt_jump;
55716: if (src & 1) {
55717: last_addr_for_exception_3 = m68k_getpc() + 2;
55718: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55719: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3182;
55720: }
55721: m68k_incpc ((uae_s32)src + 2);
55722: fill_prefetch_0 ();
55723: return 10;
55724: didnt_jump:;
55725: }}m68k_incpc(6);
55726: fill_prefetch_0 ();
55727: endlabel3182: ;
55728: return 12;
55729: }
55730: unsigned long REGPARAM2 CPUFUNC(op_6600_5)(uae_u32 opcode) /* Bcc */
55731: {
55732: OpcodeFamily = 55; CurrentInstrCycles = 12;
55733: {{ uae_s16 src = get_iword_prefetch(2);
55734: if (!cctrue(6)) goto didnt_jump;
55735: if (src & 1) {
55736: last_addr_for_exception_3 = m68k_getpc() + 2;
55737: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55738: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3183;
55739: }
55740: m68k_incpc ((uae_s32)src + 2);
55741: fill_prefetch_0 ();
55742: return 10;
55743: didnt_jump:;
55744: }}m68k_incpc(4);
55745: fill_prefetch_0 ();
55746: endlabel3183: ;
55747: return 12;
55748: }
55749: unsigned long REGPARAM2 CPUFUNC(op_6601_5)(uae_u32 opcode) /* Bcc */
55750: {
55751: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55752: OpcodeFamily = 55; CurrentInstrCycles = 8;
55753: {{ uae_u32 src = srcreg;
55754: if (!cctrue(6)) goto didnt_jump;
55755: if (src & 1) {
55756: last_addr_for_exception_3 = m68k_getpc() + 2;
55757: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55758: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3184;
55759: }
55760: m68k_incpc ((uae_s32)src + 2);
55761: fill_prefetch_0 ();
55762: return 10;
55763: didnt_jump:;
55764: }}m68k_incpc(2);
55765: fill_prefetch_2 ();
55766: endlabel3184: ;
55767: return 8;
55768: }
55769: unsigned long REGPARAM2 CPUFUNC(op_66ff_5)(uae_u32 opcode) /* Bcc */
55770: {
55771: OpcodeFamily = 55; CurrentInstrCycles = 12;
55772: { m68k_incpc(2);
55773: if (!cctrue(6)) goto endlabel3185;
55774: last_addr_for_exception_3 = m68k_getpc() + 2;
55775: last_fault_for_exception_3 = m68k_getpc() + 1;
55776: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3185;
55777: { uae_s32 src = get_ilong_prefetch(2);
55778: if (!cctrue(6)) goto didnt_jump;
55779: if (src & 1) {
55780: last_addr_for_exception_3 = m68k_getpc() + 2;
55781: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55782: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3185;
55783: }
55784: m68k_incpc ((uae_s32)src + 2);
55785: fill_prefetch_0 ();
55786: return 10;
55787: didnt_jump:;
55788: }}m68k_incpc(6);
55789: fill_prefetch_0 ();
55790: endlabel3185: ;
55791: return 12;
55792: }
55793: unsigned long REGPARAM2 CPUFUNC(op_6700_5)(uae_u32 opcode) /* Bcc */
55794: {
55795: OpcodeFamily = 55; CurrentInstrCycles = 12;
55796: {{ uae_s16 src = get_iword_prefetch(2);
55797: if (!cctrue(7)) goto didnt_jump;
55798: if (src & 1) {
55799: last_addr_for_exception_3 = m68k_getpc() + 2;
55800: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55801: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3186;
55802: }
55803: m68k_incpc ((uae_s32)src + 2);
55804: fill_prefetch_0 ();
55805: return 10;
55806: didnt_jump:;
55807: }}m68k_incpc(4);
55808: fill_prefetch_0 ();
55809: endlabel3186: ;
55810: return 12;
55811: }
55812: unsigned long REGPARAM2 CPUFUNC(op_6701_5)(uae_u32 opcode) /* Bcc */
55813: {
55814: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55815: OpcodeFamily = 55; CurrentInstrCycles = 8;
55816: {{ uae_u32 src = srcreg;
55817: if (!cctrue(7)) goto didnt_jump;
55818: if (src & 1) {
55819: last_addr_for_exception_3 = m68k_getpc() + 2;
55820: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55821: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3187;
55822: }
55823: m68k_incpc ((uae_s32)src + 2);
55824: fill_prefetch_0 ();
55825: return 10;
55826: didnt_jump:;
55827: }}m68k_incpc(2);
55828: fill_prefetch_2 ();
55829: endlabel3187: ;
55830: return 8;
55831: }
55832: unsigned long REGPARAM2 CPUFUNC(op_67ff_5)(uae_u32 opcode) /* Bcc */
55833: {
55834: OpcodeFamily = 55; CurrentInstrCycles = 12;
55835: { m68k_incpc(2);
55836: if (!cctrue(7)) goto endlabel3188;
55837: last_addr_for_exception_3 = m68k_getpc() + 2;
55838: last_fault_for_exception_3 = m68k_getpc() + 1;
55839: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3188;
55840: { uae_s32 src = get_ilong_prefetch(2);
55841: if (!cctrue(7)) goto didnt_jump;
55842: if (src & 1) {
55843: last_addr_for_exception_3 = m68k_getpc() + 2;
55844: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55845: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3188;
55846: }
55847: m68k_incpc ((uae_s32)src + 2);
55848: fill_prefetch_0 ();
55849: return 10;
55850: didnt_jump:;
55851: }}m68k_incpc(6);
55852: fill_prefetch_0 ();
55853: endlabel3188: ;
55854: return 12;
55855: }
55856: unsigned long REGPARAM2 CPUFUNC(op_6800_5)(uae_u32 opcode) /* Bcc */
55857: {
55858: OpcodeFamily = 55; CurrentInstrCycles = 12;
55859: {{ uae_s16 src = get_iword_prefetch(2);
55860: if (!cctrue(8)) goto didnt_jump;
55861: if (src & 1) {
55862: last_addr_for_exception_3 = m68k_getpc() + 2;
55863: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55864: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3189;
55865: }
55866: m68k_incpc ((uae_s32)src + 2);
55867: fill_prefetch_0 ();
55868: return 10;
55869: didnt_jump:;
55870: }}m68k_incpc(4);
55871: fill_prefetch_0 ();
55872: endlabel3189: ;
55873: return 12;
55874: }
55875: unsigned long REGPARAM2 CPUFUNC(op_6801_5)(uae_u32 opcode) /* Bcc */
55876: {
55877: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55878: OpcodeFamily = 55; CurrentInstrCycles = 8;
55879: {{ uae_u32 src = srcreg;
55880: if (!cctrue(8)) goto didnt_jump;
55881: if (src & 1) {
55882: last_addr_for_exception_3 = m68k_getpc() + 2;
55883: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55884: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3190;
55885: }
55886: m68k_incpc ((uae_s32)src + 2);
55887: fill_prefetch_0 ();
55888: return 10;
55889: didnt_jump:;
55890: }}m68k_incpc(2);
55891: fill_prefetch_2 ();
55892: endlabel3190: ;
55893: return 8;
55894: }
55895: unsigned long REGPARAM2 CPUFUNC(op_68ff_5)(uae_u32 opcode) /* Bcc */
55896: {
55897: OpcodeFamily = 55; CurrentInstrCycles = 12;
55898: { m68k_incpc(2);
55899: if (!cctrue(8)) goto endlabel3191;
55900: last_addr_for_exception_3 = m68k_getpc() + 2;
55901: last_fault_for_exception_3 = m68k_getpc() + 1;
55902: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3191;
55903: { uae_s32 src = get_ilong_prefetch(2);
55904: if (!cctrue(8)) goto didnt_jump;
55905: if (src & 1) {
55906: last_addr_for_exception_3 = m68k_getpc() + 2;
55907: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55908: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3191;
55909: }
55910: m68k_incpc ((uae_s32)src + 2);
55911: fill_prefetch_0 ();
55912: return 10;
55913: didnt_jump:;
55914: }}m68k_incpc(6);
55915: fill_prefetch_0 ();
55916: endlabel3191: ;
55917: return 12;
55918: }
55919: unsigned long REGPARAM2 CPUFUNC(op_6900_5)(uae_u32 opcode) /* Bcc */
55920: {
55921: OpcodeFamily = 55; CurrentInstrCycles = 12;
55922: {{ uae_s16 src = get_iword_prefetch(2);
55923: if (!cctrue(9)) goto didnt_jump;
55924: if (src & 1) {
55925: last_addr_for_exception_3 = m68k_getpc() + 2;
55926: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55927: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3192;
55928: }
55929: m68k_incpc ((uae_s32)src + 2);
55930: fill_prefetch_0 ();
55931: return 10;
55932: didnt_jump:;
55933: }}m68k_incpc(4);
55934: fill_prefetch_0 ();
55935: endlabel3192: ;
55936: return 12;
55937: }
55938: unsigned long REGPARAM2 CPUFUNC(op_6901_5)(uae_u32 opcode) /* Bcc */
55939: {
55940: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
55941: OpcodeFamily = 55; CurrentInstrCycles = 8;
55942: {{ uae_u32 src = srcreg;
55943: if (!cctrue(9)) goto didnt_jump;
55944: if (src & 1) {
55945: last_addr_for_exception_3 = m68k_getpc() + 2;
55946: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55947: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3193;
55948: }
55949: m68k_incpc ((uae_s32)src + 2);
55950: fill_prefetch_0 ();
55951: return 10;
55952: didnt_jump:;
55953: }}m68k_incpc(2);
55954: fill_prefetch_2 ();
55955: endlabel3193: ;
55956: return 8;
55957: }
55958: unsigned long REGPARAM2 CPUFUNC(op_69ff_5)(uae_u32 opcode) /* Bcc */
55959: {
55960: OpcodeFamily = 55; CurrentInstrCycles = 12;
55961: { m68k_incpc(2);
55962: if (!cctrue(9)) goto endlabel3194;
55963: last_addr_for_exception_3 = m68k_getpc() + 2;
55964: last_fault_for_exception_3 = m68k_getpc() + 1;
55965: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3194;
55966: { uae_s32 src = get_ilong_prefetch(2);
55967: if (!cctrue(9)) goto didnt_jump;
55968: if (src & 1) {
55969: last_addr_for_exception_3 = m68k_getpc() + 2;
55970: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55971: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3194;
55972: }
55973: m68k_incpc ((uae_s32)src + 2);
55974: fill_prefetch_0 ();
55975: return 10;
55976: didnt_jump:;
55977: }}m68k_incpc(6);
55978: fill_prefetch_0 ();
55979: endlabel3194: ;
55980: return 12;
55981: }
55982: unsigned long REGPARAM2 CPUFUNC(op_6a00_5)(uae_u32 opcode) /* Bcc */
55983: {
55984: OpcodeFamily = 55; CurrentInstrCycles = 12;
55985: {{ uae_s16 src = get_iword_prefetch(2);
55986: if (!cctrue(10)) goto didnt_jump;
55987: if (src & 1) {
55988: last_addr_for_exception_3 = m68k_getpc() + 2;
55989: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
55990: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3195;
55991: }
55992: m68k_incpc ((uae_s32)src + 2);
55993: fill_prefetch_0 ();
55994: return 10;
55995: didnt_jump:;
55996: }}m68k_incpc(4);
55997: fill_prefetch_0 ();
55998: endlabel3195: ;
55999: return 12;
56000: }
56001: unsigned long REGPARAM2 CPUFUNC(op_6a01_5)(uae_u32 opcode) /* Bcc */
56002: {
56003: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
56004: OpcodeFamily = 55; CurrentInstrCycles = 8;
56005: {{ uae_u32 src = srcreg;
56006: if (!cctrue(10)) goto didnt_jump;
56007: if (src & 1) {
56008: last_addr_for_exception_3 = m68k_getpc() + 2;
56009: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56010: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3196;
56011: }
56012: m68k_incpc ((uae_s32)src + 2);
56013: fill_prefetch_0 ();
56014: return 10;
56015: didnt_jump:;
56016: }}m68k_incpc(2);
56017: fill_prefetch_2 ();
56018: endlabel3196: ;
56019: return 8;
56020: }
56021: unsigned long REGPARAM2 CPUFUNC(op_6aff_5)(uae_u32 opcode) /* Bcc */
56022: {
56023: OpcodeFamily = 55; CurrentInstrCycles = 12;
56024: { m68k_incpc(2);
56025: if (!cctrue(10)) goto endlabel3197;
56026: last_addr_for_exception_3 = m68k_getpc() + 2;
56027: last_fault_for_exception_3 = m68k_getpc() + 1;
56028: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3197;
56029: { uae_s32 src = get_ilong_prefetch(2);
56030: if (!cctrue(10)) goto didnt_jump;
56031: if (src & 1) {
56032: last_addr_for_exception_3 = m68k_getpc() + 2;
56033: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56034: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3197;
56035: }
56036: m68k_incpc ((uae_s32)src + 2);
56037: fill_prefetch_0 ();
56038: return 10;
56039: didnt_jump:;
56040: }}m68k_incpc(6);
56041: fill_prefetch_0 ();
56042: endlabel3197: ;
56043: return 12;
56044: }
56045: unsigned long REGPARAM2 CPUFUNC(op_6b00_5)(uae_u32 opcode) /* Bcc */
56046: {
56047: OpcodeFamily = 55; CurrentInstrCycles = 12;
56048: {{ uae_s16 src = get_iword_prefetch(2);
56049: if (!cctrue(11)) goto didnt_jump;
56050: if (src & 1) {
56051: last_addr_for_exception_3 = m68k_getpc() + 2;
56052: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56053: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3198;
56054: }
56055: m68k_incpc ((uae_s32)src + 2);
56056: fill_prefetch_0 ();
56057: return 10;
56058: didnt_jump:;
56059: }}m68k_incpc(4);
56060: fill_prefetch_0 ();
56061: endlabel3198: ;
56062: return 12;
56063: }
56064: unsigned long REGPARAM2 CPUFUNC(op_6b01_5)(uae_u32 opcode) /* Bcc */
56065: {
56066: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
56067: OpcodeFamily = 55; CurrentInstrCycles = 8;
56068: {{ uae_u32 src = srcreg;
56069: if (!cctrue(11)) goto didnt_jump;
56070: if (src & 1) {
56071: last_addr_for_exception_3 = m68k_getpc() + 2;
56072: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56073: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3199;
56074: }
56075: m68k_incpc ((uae_s32)src + 2);
56076: fill_prefetch_0 ();
56077: return 10;
56078: didnt_jump:;
56079: }}m68k_incpc(2);
56080: fill_prefetch_2 ();
56081: endlabel3199: ;
56082: return 8;
56083: }
56084: unsigned long REGPARAM2 CPUFUNC(op_6bff_5)(uae_u32 opcode) /* Bcc */
56085: {
56086: OpcodeFamily = 55; CurrentInstrCycles = 12;
56087: { m68k_incpc(2);
56088: if (!cctrue(11)) goto endlabel3200;
56089: last_addr_for_exception_3 = m68k_getpc() + 2;
56090: last_fault_for_exception_3 = m68k_getpc() + 1;
56091: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3200;
56092: { uae_s32 src = get_ilong_prefetch(2);
56093: if (!cctrue(11)) goto didnt_jump;
56094: if (src & 1) {
56095: last_addr_for_exception_3 = m68k_getpc() + 2;
56096: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56097: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3200;
56098: }
56099: m68k_incpc ((uae_s32)src + 2);
56100: fill_prefetch_0 ();
56101: return 10;
56102: didnt_jump:;
56103: }}m68k_incpc(6);
56104: fill_prefetch_0 ();
56105: endlabel3200: ;
56106: return 12;
56107: }
56108: unsigned long REGPARAM2 CPUFUNC(op_6c00_5)(uae_u32 opcode) /* Bcc */
56109: {
56110: OpcodeFamily = 55; CurrentInstrCycles = 12;
56111: {{ uae_s16 src = get_iword_prefetch(2);
56112: if (!cctrue(12)) goto didnt_jump;
56113: if (src & 1) {
56114: last_addr_for_exception_3 = m68k_getpc() + 2;
56115: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56116: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3201;
56117: }
56118: m68k_incpc ((uae_s32)src + 2);
56119: fill_prefetch_0 ();
56120: return 10;
56121: didnt_jump:;
56122: }}m68k_incpc(4);
56123: fill_prefetch_0 ();
56124: endlabel3201: ;
56125: return 12;
56126: }
56127: unsigned long REGPARAM2 CPUFUNC(op_6c01_5)(uae_u32 opcode) /* Bcc */
56128: {
56129: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
56130: OpcodeFamily = 55; CurrentInstrCycles = 8;
56131: {{ uae_u32 src = srcreg;
56132: if (!cctrue(12)) goto didnt_jump;
56133: if (src & 1) {
56134: last_addr_for_exception_3 = m68k_getpc() + 2;
56135: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56136: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3202;
56137: }
56138: m68k_incpc ((uae_s32)src + 2);
56139: fill_prefetch_0 ();
56140: return 10;
56141: didnt_jump:;
56142: }}m68k_incpc(2);
56143: fill_prefetch_2 ();
56144: endlabel3202: ;
56145: return 8;
56146: }
56147: unsigned long REGPARAM2 CPUFUNC(op_6cff_5)(uae_u32 opcode) /* Bcc */
56148: {
56149: OpcodeFamily = 55; CurrentInstrCycles = 12;
56150: { m68k_incpc(2);
56151: if (!cctrue(12)) goto endlabel3203;
56152: last_addr_for_exception_3 = m68k_getpc() + 2;
56153: last_fault_for_exception_3 = m68k_getpc() + 1;
56154: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3203;
56155: { uae_s32 src = get_ilong_prefetch(2);
56156: if (!cctrue(12)) goto didnt_jump;
56157: if (src & 1) {
56158: last_addr_for_exception_3 = m68k_getpc() + 2;
56159: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56160: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3203;
56161: }
56162: m68k_incpc ((uae_s32)src + 2);
56163: fill_prefetch_0 ();
56164: return 10;
56165: didnt_jump:;
56166: }}m68k_incpc(6);
56167: fill_prefetch_0 ();
56168: endlabel3203: ;
56169: return 12;
56170: }
56171: unsigned long REGPARAM2 CPUFUNC(op_6d00_5)(uae_u32 opcode) /* Bcc */
56172: {
56173: OpcodeFamily = 55; CurrentInstrCycles = 12;
56174: {{ uae_s16 src = get_iword_prefetch(2);
56175: if (!cctrue(13)) goto didnt_jump;
56176: if (src & 1) {
56177: last_addr_for_exception_3 = m68k_getpc() + 2;
56178: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56179: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3204;
56180: }
56181: m68k_incpc ((uae_s32)src + 2);
56182: fill_prefetch_0 ();
56183: return 10;
56184: didnt_jump:;
56185: }}m68k_incpc(4);
56186: fill_prefetch_0 ();
56187: endlabel3204: ;
56188: return 12;
56189: }
56190: unsigned long REGPARAM2 CPUFUNC(op_6d01_5)(uae_u32 opcode) /* Bcc */
56191: {
56192: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
56193: OpcodeFamily = 55; CurrentInstrCycles = 8;
56194: {{ uae_u32 src = srcreg;
56195: if (!cctrue(13)) goto didnt_jump;
56196: if (src & 1) {
56197: last_addr_for_exception_3 = m68k_getpc() + 2;
56198: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56199: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3205;
56200: }
56201: m68k_incpc ((uae_s32)src + 2);
56202: fill_prefetch_0 ();
56203: return 10;
56204: didnt_jump:;
56205: }}m68k_incpc(2);
56206: fill_prefetch_2 ();
56207: endlabel3205: ;
56208: return 8;
56209: }
56210: unsigned long REGPARAM2 CPUFUNC(op_6dff_5)(uae_u32 opcode) /* Bcc */
56211: {
56212: OpcodeFamily = 55; CurrentInstrCycles = 12;
56213: { m68k_incpc(2);
56214: if (!cctrue(13)) goto endlabel3206;
56215: last_addr_for_exception_3 = m68k_getpc() + 2;
56216: last_fault_for_exception_3 = m68k_getpc() + 1;
56217: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3206;
56218: { uae_s32 src = get_ilong_prefetch(2);
56219: if (!cctrue(13)) goto didnt_jump;
56220: if (src & 1) {
56221: last_addr_for_exception_3 = m68k_getpc() + 2;
56222: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56223: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3206;
56224: }
56225: m68k_incpc ((uae_s32)src + 2);
56226: fill_prefetch_0 ();
56227: return 10;
56228: didnt_jump:;
56229: }}m68k_incpc(6);
56230: fill_prefetch_0 ();
56231: endlabel3206: ;
56232: return 12;
56233: }
56234: unsigned long REGPARAM2 CPUFUNC(op_6e00_5)(uae_u32 opcode) /* Bcc */
56235: {
56236: OpcodeFamily = 55; CurrentInstrCycles = 12;
56237: {{ uae_s16 src = get_iword_prefetch(2);
56238: if (!cctrue(14)) goto didnt_jump;
56239: if (src & 1) {
56240: last_addr_for_exception_3 = m68k_getpc() + 2;
56241: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56242: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3207;
56243: }
56244: m68k_incpc ((uae_s32)src + 2);
56245: fill_prefetch_0 ();
56246: return 10;
56247: didnt_jump:;
56248: }}m68k_incpc(4);
56249: fill_prefetch_0 ();
56250: endlabel3207: ;
56251: return 12;
56252: }
56253: unsigned long REGPARAM2 CPUFUNC(op_6e01_5)(uae_u32 opcode) /* Bcc */
56254: {
56255: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
56256: OpcodeFamily = 55; CurrentInstrCycles = 8;
56257: {{ uae_u32 src = srcreg;
56258: if (!cctrue(14)) goto didnt_jump;
56259: if (src & 1) {
56260: last_addr_for_exception_3 = m68k_getpc() + 2;
56261: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56262: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3208;
56263: }
56264: m68k_incpc ((uae_s32)src + 2);
56265: fill_prefetch_0 ();
56266: return 10;
56267: didnt_jump:;
56268: }}m68k_incpc(2);
56269: fill_prefetch_2 ();
56270: endlabel3208: ;
56271: return 8;
56272: }
56273: unsigned long REGPARAM2 CPUFUNC(op_6eff_5)(uae_u32 opcode) /* Bcc */
56274: {
56275: OpcodeFamily = 55; CurrentInstrCycles = 12;
56276: { m68k_incpc(2);
56277: if (!cctrue(14)) goto endlabel3209;
56278: last_addr_for_exception_3 = m68k_getpc() + 2;
56279: last_fault_for_exception_3 = m68k_getpc() + 1;
56280: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3209;
56281: { uae_s32 src = get_ilong_prefetch(2);
56282: if (!cctrue(14)) goto didnt_jump;
56283: if (src & 1) {
56284: last_addr_for_exception_3 = m68k_getpc() + 2;
56285: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56286: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3209;
56287: }
56288: m68k_incpc ((uae_s32)src + 2);
56289: fill_prefetch_0 ();
56290: return 10;
56291: didnt_jump:;
56292: }}m68k_incpc(6);
56293: fill_prefetch_0 ();
56294: endlabel3209: ;
56295: return 12;
56296: }
56297: unsigned long REGPARAM2 CPUFUNC(op_6f00_5)(uae_u32 opcode) /* Bcc */
56298: {
56299: OpcodeFamily = 55; CurrentInstrCycles = 12;
56300: {{ uae_s16 src = get_iword_prefetch(2);
56301: if (!cctrue(15)) goto didnt_jump;
56302: if (src & 1) {
56303: last_addr_for_exception_3 = m68k_getpc() + 2;
56304: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56305: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3210;
56306: }
56307: m68k_incpc ((uae_s32)src + 2);
56308: fill_prefetch_0 ();
56309: return 10;
56310: didnt_jump:;
56311: }}m68k_incpc(4);
56312: fill_prefetch_0 ();
56313: endlabel3210: ;
56314: return 12;
56315: }
56316: unsigned long REGPARAM2 CPUFUNC(op_6f01_5)(uae_u32 opcode) /* Bcc */
56317: {
56318: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
56319: OpcodeFamily = 55; CurrentInstrCycles = 8;
56320: {{ uae_u32 src = srcreg;
56321: if (!cctrue(15)) goto didnt_jump;
56322: if (src & 1) {
56323: last_addr_for_exception_3 = m68k_getpc() + 2;
56324: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56325: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3211;
56326: }
56327: m68k_incpc ((uae_s32)src + 2);
56328: fill_prefetch_0 ();
56329: return 10;
56330: didnt_jump:;
56331: }}m68k_incpc(2);
56332: fill_prefetch_2 ();
56333: endlabel3211: ;
56334: return 8;
56335: }
56336: unsigned long REGPARAM2 CPUFUNC(op_6fff_5)(uae_u32 opcode) /* Bcc */
56337: {
56338: OpcodeFamily = 55; CurrentInstrCycles = 12;
56339: { m68k_incpc(2);
56340: if (!cctrue(15)) goto endlabel3212;
56341: last_addr_for_exception_3 = m68k_getpc() + 2;
56342: last_fault_for_exception_3 = m68k_getpc() + 1;
56343: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3212;
56344: { uae_s32 src = get_ilong_prefetch(2);
56345: if (!cctrue(15)) goto didnt_jump;
56346: if (src & 1) {
56347: last_addr_for_exception_3 = m68k_getpc() + 2;
56348: last_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;
56349: last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel3212;
56350: }
56351: m68k_incpc ((uae_s32)src + 2);
56352: fill_prefetch_0 ();
56353: return 10;
56354: didnt_jump:;
56355: }}m68k_incpc(6);
56356: fill_prefetch_0 ();
56357: endlabel3212: ;
56358: return 12;
56359: }
56360: unsigned long REGPARAM2 CPUFUNC(op_7000_5)(uae_u32 opcode) /* MOVE */
56361: {
56362: uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
56363: uae_u32 dstreg = (opcode >> 9) & 7;
56364: OpcodeFamily = 30; CurrentInstrCycles = 4;
56365: {{ uae_u32 src = srcreg;
56366: { CLEAR_CZNV;
56367: SET_ZFLG (((uae_s32)(src)) == 0);
56368: SET_NFLG (((uae_s32)(src)) < 0);
56369: m68k_dreg(regs, dstreg) = (src);
56370: }}}m68k_incpc(2);
56371: fill_prefetch_2 ();
56372: return 4;
56373: }
56374: unsigned long REGPARAM2 CPUFUNC(op_8000_5)(uae_u32 opcode) /* OR */
56375: {
56376: uae_u32 srcreg = (opcode & 7);
56377: uae_u32 dstreg = (opcode >> 9) & 7;
56378: OpcodeFamily = 1; CurrentInstrCycles = 4;
56379: {{ uae_s8 src = m68k_dreg(regs, srcreg);
56380: { uae_s8 dst = m68k_dreg(regs, dstreg);
56381: src |= dst;
56382: CLEAR_CZNV;
56383: SET_ZFLG (((uae_s8)(src)) == 0);
56384: SET_NFLG (((uae_s8)(src)) < 0);
56385: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56386: }}}m68k_incpc(2);
56387: fill_prefetch_2 ();
56388: return 4;
56389: }
56390: unsigned long REGPARAM2 CPUFUNC(op_8010_5)(uae_u32 opcode) /* OR */
56391: {
56392: uae_u32 srcreg = (opcode & 7);
56393: uae_u32 dstreg = (opcode >> 9) & 7;
56394: OpcodeFamily = 1; CurrentInstrCycles = 8;
56395: {{ uaecptr srca = m68k_areg(regs, srcreg);
56396: { uae_s8 src = get_byte(srca);
56397: { uae_s8 dst = m68k_dreg(regs, dstreg);
56398: src |= dst;
56399: CLEAR_CZNV;
56400: SET_ZFLG (((uae_s8)(src)) == 0);
56401: SET_NFLG (((uae_s8)(src)) < 0);
56402: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56403: }}}}m68k_incpc(2);
56404: fill_prefetch_2 ();
56405: return 8;
56406: }
56407: unsigned long REGPARAM2 CPUFUNC(op_8018_5)(uae_u32 opcode) /* OR */
56408: {
56409: uae_u32 srcreg = (opcode & 7);
56410: uae_u32 dstreg = (opcode >> 9) & 7;
56411: OpcodeFamily = 1; CurrentInstrCycles = 8;
56412: {{ uaecptr srca = m68k_areg(regs, srcreg);
56413: { uae_s8 src = get_byte(srca);
56414: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
56415: { uae_s8 dst = m68k_dreg(regs, dstreg);
56416: src |= dst;
56417: CLEAR_CZNV;
56418: SET_ZFLG (((uae_s8)(src)) == 0);
56419: SET_NFLG (((uae_s8)(src)) < 0);
56420: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56421: }}}}m68k_incpc(2);
56422: fill_prefetch_2 ();
56423: return 8;
56424: }
56425: unsigned long REGPARAM2 CPUFUNC(op_8020_5)(uae_u32 opcode) /* OR */
56426: {
56427: uae_u32 srcreg = (opcode & 7);
56428: uae_u32 dstreg = (opcode >> 9) & 7;
56429: OpcodeFamily = 1; CurrentInstrCycles = 10;
56430: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
56431: { uae_s8 src = get_byte(srca);
56432: m68k_areg (regs, srcreg) = srca;
56433: { uae_s8 dst = m68k_dreg(regs, dstreg);
56434: src |= dst;
56435: CLEAR_CZNV;
56436: SET_ZFLG (((uae_s8)(src)) == 0);
56437: SET_NFLG (((uae_s8)(src)) < 0);
56438: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56439: }}}}m68k_incpc(2);
56440: fill_prefetch_2 ();
56441: return 10;
56442: }
56443: unsigned long REGPARAM2 CPUFUNC(op_8028_5)(uae_u32 opcode) /* OR */
56444: {
56445: uae_u32 srcreg = (opcode & 7);
56446: uae_u32 dstreg = (opcode >> 9) & 7;
56447: OpcodeFamily = 1; CurrentInstrCycles = 12;
56448: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
56449: { uae_s8 src = get_byte(srca);
56450: { uae_s8 dst = m68k_dreg(regs, dstreg);
56451: src |= dst;
56452: CLEAR_CZNV;
56453: SET_ZFLG (((uae_s8)(src)) == 0);
56454: SET_NFLG (((uae_s8)(src)) < 0);
56455: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56456: }}}}m68k_incpc(4);
56457: fill_prefetch_0 ();
56458: return 12;
56459: }
56460: unsigned long REGPARAM2 CPUFUNC(op_8030_5)(uae_u32 opcode) /* OR */
56461: {
56462: uae_u32 srcreg = (opcode & 7);
56463: uae_u32 dstreg = (opcode >> 9) & 7;
56464: OpcodeFamily = 1; CurrentInstrCycles = 14;
56465: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
56466: BusCyclePenalty += 2;
56467: { uae_s8 src = get_byte(srca);
56468: { uae_s8 dst = m68k_dreg(regs, dstreg);
56469: src |= dst;
56470: CLEAR_CZNV;
56471: SET_ZFLG (((uae_s8)(src)) == 0);
56472: SET_NFLG (((uae_s8)(src)) < 0);
56473: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56474: }}}}m68k_incpc(4);
56475: fill_prefetch_0 ();
56476: return 14;
56477: }
56478: unsigned long REGPARAM2 CPUFUNC(op_8038_5)(uae_u32 opcode) /* OR */
56479: {
56480: uae_u32 dstreg = (opcode >> 9) & 7;
56481: OpcodeFamily = 1; CurrentInstrCycles = 12;
56482: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
56483: { uae_s8 src = get_byte(srca);
56484: { uae_s8 dst = m68k_dreg(regs, dstreg);
56485: src |= dst;
56486: CLEAR_CZNV;
56487: SET_ZFLG (((uae_s8)(src)) == 0);
56488: SET_NFLG (((uae_s8)(src)) < 0);
56489: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56490: }}}}m68k_incpc(4);
56491: fill_prefetch_0 ();
56492: return 12;
56493: }
56494: unsigned long REGPARAM2 CPUFUNC(op_8039_5)(uae_u32 opcode) /* OR */
56495: {
56496: uae_u32 dstreg = (opcode >> 9) & 7;
56497: OpcodeFamily = 1; CurrentInstrCycles = 16;
56498: {{ uaecptr srca = get_ilong_prefetch(2);
56499: { uae_s8 src = get_byte(srca);
56500: { uae_s8 dst = m68k_dreg(regs, dstreg);
56501: src |= dst;
56502: CLEAR_CZNV;
56503: SET_ZFLG (((uae_s8)(src)) == 0);
56504: SET_NFLG (((uae_s8)(src)) < 0);
56505: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56506: }}}}m68k_incpc(6);
56507: fill_prefetch_0 ();
56508: return 16;
56509: }
56510: unsigned long REGPARAM2 CPUFUNC(op_803a_5)(uae_u32 opcode) /* OR */
56511: {
56512: uae_u32 dstreg = (opcode >> 9) & 7;
56513: OpcodeFamily = 1; CurrentInstrCycles = 12;
56514: {{ uaecptr srca = m68k_getpc () + 2;
56515: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
56516: { uae_s8 src = get_byte(srca);
56517: { uae_s8 dst = m68k_dreg(regs, dstreg);
56518: src |= dst;
56519: CLEAR_CZNV;
56520: SET_ZFLG (((uae_s8)(src)) == 0);
56521: SET_NFLG (((uae_s8)(src)) < 0);
56522: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56523: }}}}m68k_incpc(4);
56524: fill_prefetch_0 ();
56525: return 12;
56526: }
56527: unsigned long REGPARAM2 CPUFUNC(op_803b_5)(uae_u32 opcode) /* OR */
56528: {
56529: uae_u32 dstreg = (opcode >> 9) & 7;
56530: OpcodeFamily = 1; CurrentInstrCycles = 14;
56531: {{ uaecptr tmppc = m68k_getpc() + 2;
56532: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
56533: BusCyclePenalty += 2;
56534: { uae_s8 src = get_byte(srca);
56535: { uae_s8 dst = m68k_dreg(regs, dstreg);
56536: src |= dst;
56537: CLEAR_CZNV;
56538: SET_ZFLG (((uae_s8)(src)) == 0);
56539: SET_NFLG (((uae_s8)(src)) < 0);
56540: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56541: }}}}m68k_incpc(4);
56542: fill_prefetch_0 ();
56543: return 14;
56544: }
56545: unsigned long REGPARAM2 CPUFUNC(op_803c_5)(uae_u32 opcode) /* OR */
56546: {
56547: uae_u32 dstreg = (opcode >> 9) & 7;
56548: OpcodeFamily = 1; CurrentInstrCycles = 8;
56549: {{ uae_s8 src = get_ibyte_prefetch(2);
56550: { uae_s8 dst = m68k_dreg(regs, dstreg);
56551: src |= dst;
56552: CLEAR_CZNV;
56553: SET_ZFLG (((uae_s8)(src)) == 0);
56554: SET_NFLG (((uae_s8)(src)) < 0);
56555: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
56556: }}}m68k_incpc(4);
56557: fill_prefetch_0 ();
56558: return 8;
56559: }
56560: unsigned long REGPARAM2 CPUFUNC(op_8040_5)(uae_u32 opcode) /* OR */
56561: {
56562: uae_u32 srcreg = (opcode & 7);
56563: uae_u32 dstreg = (opcode >> 9) & 7;
56564: OpcodeFamily = 1; CurrentInstrCycles = 4;
56565: {{ uae_s16 src = m68k_dreg(regs, srcreg);
56566: { uae_s16 dst = m68k_dreg(regs, dstreg);
56567: src |= dst;
56568: CLEAR_CZNV;
56569: SET_ZFLG (((uae_s16)(src)) == 0);
56570: SET_NFLG (((uae_s16)(src)) < 0);
56571: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56572: }}}m68k_incpc(2);
56573: fill_prefetch_2 ();
56574: return 4;
56575: }
56576: unsigned long REGPARAM2 CPUFUNC(op_8050_5)(uae_u32 opcode) /* OR */
56577: {
56578: uae_u32 srcreg = (opcode & 7);
56579: uae_u32 dstreg = (opcode >> 9) & 7;
56580: OpcodeFamily = 1; CurrentInstrCycles = 8;
56581: {{ uaecptr srca = m68k_areg(regs, srcreg);
56582: if ((srca & 1) != 0) {
56583: last_fault_for_exception_3 = srca;
56584: last_op_for_exception_3 = opcode;
56585: last_addr_for_exception_3 = m68k_getpc() + 2;
56586: Exception(3, 0, M68000_EXC_SRC_CPU);
56587: goto endlabel3226;
56588: }
56589: {{ uae_s16 src = get_word(srca);
56590: { uae_s16 dst = m68k_dreg(regs, dstreg);
56591: src |= dst;
56592: CLEAR_CZNV;
56593: SET_ZFLG (((uae_s16)(src)) == 0);
56594: SET_NFLG (((uae_s16)(src)) < 0);
56595: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56596: }}}}}m68k_incpc(2);
56597: fill_prefetch_2 ();
56598: endlabel3226: ;
56599: return 8;
56600: }
56601: unsigned long REGPARAM2 CPUFUNC(op_8058_5)(uae_u32 opcode) /* OR */
56602: {
56603: uae_u32 srcreg = (opcode & 7);
56604: uae_u32 dstreg = (opcode >> 9) & 7;
56605: OpcodeFamily = 1; CurrentInstrCycles = 8;
56606: {{ uaecptr srca = m68k_areg(regs, srcreg);
56607: if ((srca & 1) != 0) {
56608: last_fault_for_exception_3 = srca;
56609: last_op_for_exception_3 = opcode;
56610: last_addr_for_exception_3 = m68k_getpc() + 2;
56611: Exception(3, 0, M68000_EXC_SRC_CPU);
56612: goto endlabel3227;
56613: }
56614: {{ uae_s16 src = get_word(srca);
56615: m68k_areg(regs, srcreg) += 2;
56616: { uae_s16 dst = m68k_dreg(regs, dstreg);
56617: src |= dst;
56618: CLEAR_CZNV;
56619: SET_ZFLG (((uae_s16)(src)) == 0);
56620: SET_NFLG (((uae_s16)(src)) < 0);
56621: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56622: }}}}}m68k_incpc(2);
56623: fill_prefetch_2 ();
56624: endlabel3227: ;
56625: return 8;
56626: }
56627: unsigned long REGPARAM2 CPUFUNC(op_8060_5)(uae_u32 opcode) /* OR */
56628: {
56629: uae_u32 srcreg = (opcode & 7);
56630: uae_u32 dstreg = (opcode >> 9) & 7;
56631: OpcodeFamily = 1; CurrentInstrCycles = 10;
56632: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
56633: if ((srca & 1) != 0) {
56634: last_fault_for_exception_3 = srca;
56635: last_op_for_exception_3 = opcode;
56636: last_addr_for_exception_3 = m68k_getpc() + 2;
56637: Exception(3, 0, M68000_EXC_SRC_CPU);
56638: goto endlabel3228;
56639: }
56640: {{ uae_s16 src = get_word(srca);
56641: m68k_areg (regs, srcreg) = srca;
56642: { uae_s16 dst = m68k_dreg(regs, dstreg);
56643: src |= dst;
56644: CLEAR_CZNV;
56645: SET_ZFLG (((uae_s16)(src)) == 0);
56646: SET_NFLG (((uae_s16)(src)) < 0);
56647: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56648: }}}}}m68k_incpc(2);
56649: fill_prefetch_2 ();
56650: endlabel3228: ;
56651: return 10;
56652: }
56653: unsigned long REGPARAM2 CPUFUNC(op_8068_5)(uae_u32 opcode) /* OR */
56654: {
56655: uae_u32 srcreg = (opcode & 7);
56656: uae_u32 dstreg = (opcode >> 9) & 7;
56657: OpcodeFamily = 1; CurrentInstrCycles = 12;
56658: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
56659: if ((srca & 1) != 0) {
56660: last_fault_for_exception_3 = srca;
56661: last_op_for_exception_3 = opcode;
56662: last_addr_for_exception_3 = m68k_getpc() + 4;
56663: Exception(3, 0, M68000_EXC_SRC_CPU);
56664: goto endlabel3229;
56665: }
56666: {{ uae_s16 src = get_word(srca);
56667: { uae_s16 dst = m68k_dreg(regs, dstreg);
56668: src |= dst;
56669: CLEAR_CZNV;
56670: SET_ZFLG (((uae_s16)(src)) == 0);
56671: SET_NFLG (((uae_s16)(src)) < 0);
56672: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56673: }}}}}m68k_incpc(4);
56674: fill_prefetch_0 ();
56675: endlabel3229: ;
56676: return 12;
56677: }
56678: unsigned long REGPARAM2 CPUFUNC(op_8070_5)(uae_u32 opcode) /* OR */
56679: {
56680: uae_u32 srcreg = (opcode & 7);
56681: uae_u32 dstreg = (opcode >> 9) & 7;
56682: OpcodeFamily = 1; CurrentInstrCycles = 14;
56683: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
56684: BusCyclePenalty += 2;
56685: if ((srca & 1) != 0) {
56686: last_fault_for_exception_3 = srca;
56687: last_op_for_exception_3 = opcode;
56688: last_addr_for_exception_3 = m68k_getpc() + 4;
56689: Exception(3, 0, M68000_EXC_SRC_CPU);
56690: goto endlabel3230;
56691: }
56692: {{ uae_s16 src = get_word(srca);
56693: { uae_s16 dst = m68k_dreg(regs, dstreg);
56694: src |= dst;
56695: CLEAR_CZNV;
56696: SET_ZFLG (((uae_s16)(src)) == 0);
56697: SET_NFLG (((uae_s16)(src)) < 0);
56698: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56699: }}}}}m68k_incpc(4);
56700: fill_prefetch_0 ();
56701: endlabel3230: ;
56702: return 14;
56703: }
56704: unsigned long REGPARAM2 CPUFUNC(op_8078_5)(uae_u32 opcode) /* OR */
56705: {
56706: uae_u32 dstreg = (opcode >> 9) & 7;
56707: OpcodeFamily = 1; CurrentInstrCycles = 12;
56708: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
56709: if ((srca & 1) != 0) {
56710: last_fault_for_exception_3 = srca;
56711: last_op_for_exception_3 = opcode;
56712: last_addr_for_exception_3 = m68k_getpc() + 4;
56713: Exception(3, 0, M68000_EXC_SRC_CPU);
56714: goto endlabel3231;
56715: }
56716: {{ uae_s16 src = get_word(srca);
56717: { uae_s16 dst = m68k_dreg(regs, dstreg);
56718: src |= dst;
56719: CLEAR_CZNV;
56720: SET_ZFLG (((uae_s16)(src)) == 0);
56721: SET_NFLG (((uae_s16)(src)) < 0);
56722: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56723: }}}}}m68k_incpc(4);
56724: fill_prefetch_0 ();
56725: endlabel3231: ;
56726: return 12;
56727: }
56728: unsigned long REGPARAM2 CPUFUNC(op_8079_5)(uae_u32 opcode) /* OR */
56729: {
56730: uae_u32 dstreg = (opcode >> 9) & 7;
56731: OpcodeFamily = 1; CurrentInstrCycles = 16;
56732: {{ uaecptr srca = get_ilong_prefetch(2);
56733: if ((srca & 1) != 0) {
56734: last_fault_for_exception_3 = srca;
56735: last_op_for_exception_3 = opcode;
56736: last_addr_for_exception_3 = m68k_getpc() + 6;
56737: Exception(3, 0, M68000_EXC_SRC_CPU);
56738: goto endlabel3232;
56739: }
56740: {{ uae_s16 src = get_word(srca);
56741: { uae_s16 dst = m68k_dreg(regs, dstreg);
56742: src |= dst;
56743: CLEAR_CZNV;
56744: SET_ZFLG (((uae_s16)(src)) == 0);
56745: SET_NFLG (((uae_s16)(src)) < 0);
56746: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56747: }}}}}m68k_incpc(6);
56748: fill_prefetch_0 ();
56749: endlabel3232: ;
56750: return 16;
56751: }
56752: unsigned long REGPARAM2 CPUFUNC(op_807a_5)(uae_u32 opcode) /* OR */
56753: {
56754: uae_u32 dstreg = (opcode >> 9) & 7;
56755: OpcodeFamily = 1; CurrentInstrCycles = 12;
56756: {{ uaecptr srca = m68k_getpc () + 2;
56757: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
56758: if ((srca & 1) != 0) {
56759: last_fault_for_exception_3 = srca;
56760: last_op_for_exception_3 = opcode;
56761: last_addr_for_exception_3 = m68k_getpc() + 4;
56762: Exception(3, 0, M68000_EXC_SRC_CPU);
56763: goto endlabel3233;
56764: }
56765: {{ uae_s16 src = get_word(srca);
56766: { uae_s16 dst = m68k_dreg(regs, dstreg);
56767: src |= dst;
56768: CLEAR_CZNV;
56769: SET_ZFLG (((uae_s16)(src)) == 0);
56770: SET_NFLG (((uae_s16)(src)) < 0);
56771: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56772: }}}}}m68k_incpc(4);
56773: fill_prefetch_0 ();
56774: endlabel3233: ;
56775: return 12;
56776: }
56777: unsigned long REGPARAM2 CPUFUNC(op_807b_5)(uae_u32 opcode) /* OR */
56778: {
56779: uae_u32 dstreg = (opcode >> 9) & 7;
56780: OpcodeFamily = 1; CurrentInstrCycles = 14;
56781: {{ uaecptr tmppc = m68k_getpc() + 2;
56782: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
56783: BusCyclePenalty += 2;
56784: if ((srca & 1) != 0) {
56785: last_fault_for_exception_3 = srca;
56786: last_op_for_exception_3 = opcode;
56787: last_addr_for_exception_3 = m68k_getpc() + 4;
56788: Exception(3, 0, M68000_EXC_SRC_CPU);
56789: goto endlabel3234;
56790: }
56791: {{ uae_s16 src = get_word(srca);
56792: { uae_s16 dst = m68k_dreg(regs, dstreg);
56793: src |= dst;
56794: CLEAR_CZNV;
56795: SET_ZFLG (((uae_s16)(src)) == 0);
56796: SET_NFLG (((uae_s16)(src)) < 0);
56797: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56798: }}}}}m68k_incpc(4);
56799: fill_prefetch_0 ();
56800: endlabel3234: ;
56801: return 14;
56802: }
56803: unsigned long REGPARAM2 CPUFUNC(op_807c_5)(uae_u32 opcode) /* OR */
56804: {
56805: uae_u32 dstreg = (opcode >> 9) & 7;
56806: OpcodeFamily = 1; CurrentInstrCycles = 8;
56807: {{ uae_s16 src = get_iword_prefetch(2);
56808: { uae_s16 dst = m68k_dreg(regs, dstreg);
56809: src |= dst;
56810: CLEAR_CZNV;
56811: SET_ZFLG (((uae_s16)(src)) == 0);
56812: SET_NFLG (((uae_s16)(src)) < 0);
56813: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
56814: }}}m68k_incpc(4);
56815: fill_prefetch_0 ();
56816: return 8;
56817: }
56818: unsigned long REGPARAM2 CPUFUNC(op_8080_5)(uae_u32 opcode) /* OR */
56819: {
56820: uae_u32 srcreg = (opcode & 7);
56821: uae_u32 dstreg = (opcode >> 9) & 7;
56822: OpcodeFamily = 1; CurrentInstrCycles = 8;
56823: {{ uae_s32 src = m68k_dreg(regs, srcreg);
56824: { uae_s32 dst = m68k_dreg(regs, dstreg);
56825: src |= dst;
56826: CLEAR_CZNV;
56827: SET_ZFLG (((uae_s32)(src)) == 0);
56828: SET_NFLG (((uae_s32)(src)) < 0);
56829: m68k_dreg(regs, dstreg) = (src);
56830: }}}m68k_incpc(2);
56831: fill_prefetch_2 ();
56832: return 8;
56833: }
56834: unsigned long REGPARAM2 CPUFUNC(op_8090_5)(uae_u32 opcode) /* OR */
56835: {
56836: uae_u32 srcreg = (opcode & 7);
56837: uae_u32 dstreg = (opcode >> 9) & 7;
56838: OpcodeFamily = 1; CurrentInstrCycles = 14;
56839: {{ uaecptr srca = m68k_areg(regs, srcreg);
56840: if ((srca & 1) != 0) {
56841: last_fault_for_exception_3 = srca;
56842: last_op_for_exception_3 = opcode;
56843: last_addr_for_exception_3 = m68k_getpc() + 2;
56844: Exception(3, 0, M68000_EXC_SRC_CPU);
56845: goto endlabel3237;
56846: }
56847: {{ uae_s32 src = get_long(srca);
56848: { uae_s32 dst = m68k_dreg(regs, dstreg);
56849: src |= dst;
56850: CLEAR_CZNV;
56851: SET_ZFLG (((uae_s32)(src)) == 0);
56852: SET_NFLG (((uae_s32)(src)) < 0);
56853: m68k_dreg(regs, dstreg) = (src);
56854: }}}}}m68k_incpc(2);
56855: fill_prefetch_2 ();
56856: endlabel3237: ;
56857: return 14;
56858: }
56859: unsigned long REGPARAM2 CPUFUNC(op_8098_5)(uae_u32 opcode) /* OR */
56860: {
56861: uae_u32 srcreg = (opcode & 7);
56862: uae_u32 dstreg = (opcode >> 9) & 7;
56863: OpcodeFamily = 1; CurrentInstrCycles = 14;
56864: {{ uaecptr srca = m68k_areg(regs, srcreg);
56865: if ((srca & 1) != 0) {
56866: last_fault_for_exception_3 = srca;
56867: last_op_for_exception_3 = opcode;
56868: last_addr_for_exception_3 = m68k_getpc() + 2;
56869: Exception(3, 0, M68000_EXC_SRC_CPU);
56870: goto endlabel3238;
56871: }
56872: {{ uae_s32 src = get_long(srca);
56873: m68k_areg(regs, srcreg) += 4;
56874: { uae_s32 dst = m68k_dreg(regs, dstreg);
56875: src |= dst;
56876: CLEAR_CZNV;
56877: SET_ZFLG (((uae_s32)(src)) == 0);
56878: SET_NFLG (((uae_s32)(src)) < 0);
56879: m68k_dreg(regs, dstreg) = (src);
56880: }}}}}m68k_incpc(2);
56881: fill_prefetch_2 ();
56882: endlabel3238: ;
56883: return 14;
56884: }
56885: unsigned long REGPARAM2 CPUFUNC(op_80a0_5)(uae_u32 opcode) /* OR */
56886: {
56887: uae_u32 srcreg = (opcode & 7);
56888: uae_u32 dstreg = (opcode >> 9) & 7;
56889: OpcodeFamily = 1; CurrentInstrCycles = 16;
56890: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
56891: if ((srca & 1) != 0) {
56892: last_fault_for_exception_3 = srca;
56893: last_op_for_exception_3 = opcode;
56894: last_addr_for_exception_3 = m68k_getpc() + 2;
56895: Exception(3, 0, M68000_EXC_SRC_CPU);
56896: goto endlabel3239;
56897: }
56898: {{ uae_s32 src = get_long(srca);
56899: m68k_areg (regs, srcreg) = srca;
56900: { uae_s32 dst = m68k_dreg(regs, dstreg);
56901: src |= dst;
56902: CLEAR_CZNV;
56903: SET_ZFLG (((uae_s32)(src)) == 0);
56904: SET_NFLG (((uae_s32)(src)) < 0);
56905: m68k_dreg(regs, dstreg) = (src);
56906: }}}}}m68k_incpc(2);
56907: fill_prefetch_2 ();
56908: endlabel3239: ;
56909: return 16;
56910: }
56911: unsigned long REGPARAM2 CPUFUNC(op_80a8_5)(uae_u32 opcode) /* OR */
56912: {
56913: uae_u32 srcreg = (opcode & 7);
56914: uae_u32 dstreg = (opcode >> 9) & 7;
56915: OpcodeFamily = 1; CurrentInstrCycles = 18;
56916: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
56917: if ((srca & 1) != 0) {
56918: last_fault_for_exception_3 = srca;
56919: last_op_for_exception_3 = opcode;
56920: last_addr_for_exception_3 = m68k_getpc() + 4;
56921: Exception(3, 0, M68000_EXC_SRC_CPU);
56922: goto endlabel3240;
56923: }
56924: {{ uae_s32 src = get_long(srca);
56925: { uae_s32 dst = m68k_dreg(regs, dstreg);
56926: src |= dst;
56927: CLEAR_CZNV;
56928: SET_ZFLG (((uae_s32)(src)) == 0);
56929: SET_NFLG (((uae_s32)(src)) < 0);
56930: m68k_dreg(regs, dstreg) = (src);
56931: }}}}}m68k_incpc(4);
56932: fill_prefetch_0 ();
56933: endlabel3240: ;
56934: return 18;
56935: }
56936: unsigned long REGPARAM2 CPUFUNC(op_80b0_5)(uae_u32 opcode) /* OR */
56937: {
56938: uae_u32 srcreg = (opcode & 7);
56939: uae_u32 dstreg = (opcode >> 9) & 7;
56940: OpcodeFamily = 1; CurrentInstrCycles = 20;
56941: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
56942: BusCyclePenalty += 2;
56943: if ((srca & 1) != 0) {
56944: last_fault_for_exception_3 = srca;
56945: last_op_for_exception_3 = opcode;
56946: last_addr_for_exception_3 = m68k_getpc() + 4;
56947: Exception(3, 0, M68000_EXC_SRC_CPU);
56948: goto endlabel3241;
56949: }
56950: {{ uae_s32 src = get_long(srca);
56951: { uae_s32 dst = m68k_dreg(regs, dstreg);
56952: src |= dst;
56953: CLEAR_CZNV;
56954: SET_ZFLG (((uae_s32)(src)) == 0);
56955: SET_NFLG (((uae_s32)(src)) < 0);
56956: m68k_dreg(regs, dstreg) = (src);
56957: }}}}}m68k_incpc(4);
56958: fill_prefetch_0 ();
56959: endlabel3241: ;
56960: return 20;
56961: }
56962: unsigned long REGPARAM2 CPUFUNC(op_80b8_5)(uae_u32 opcode) /* OR */
56963: {
56964: uae_u32 dstreg = (opcode >> 9) & 7;
56965: OpcodeFamily = 1; CurrentInstrCycles = 18;
56966: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
56967: if ((srca & 1) != 0) {
56968: last_fault_for_exception_3 = srca;
56969: last_op_for_exception_3 = opcode;
56970: last_addr_for_exception_3 = m68k_getpc() + 4;
56971: Exception(3, 0, M68000_EXC_SRC_CPU);
56972: goto endlabel3242;
56973: }
56974: {{ uae_s32 src = get_long(srca);
56975: { uae_s32 dst = m68k_dreg(regs, dstreg);
56976: src |= dst;
56977: CLEAR_CZNV;
56978: SET_ZFLG (((uae_s32)(src)) == 0);
56979: SET_NFLG (((uae_s32)(src)) < 0);
56980: m68k_dreg(regs, dstreg) = (src);
56981: }}}}}m68k_incpc(4);
56982: fill_prefetch_0 ();
56983: endlabel3242: ;
56984: return 18;
56985: }
56986: unsigned long REGPARAM2 CPUFUNC(op_80b9_5)(uae_u32 opcode) /* OR */
56987: {
56988: uae_u32 dstreg = (opcode >> 9) & 7;
56989: OpcodeFamily = 1; CurrentInstrCycles = 22;
56990: {{ uaecptr srca = get_ilong_prefetch(2);
56991: if ((srca & 1) != 0) {
56992: last_fault_for_exception_3 = srca;
56993: last_op_for_exception_3 = opcode;
56994: last_addr_for_exception_3 = m68k_getpc() + 6;
56995: Exception(3, 0, M68000_EXC_SRC_CPU);
56996: goto endlabel3243;
56997: }
56998: {{ uae_s32 src = get_long(srca);
56999: { uae_s32 dst = m68k_dreg(regs, dstreg);
57000: src |= dst;
57001: CLEAR_CZNV;
57002: SET_ZFLG (((uae_s32)(src)) == 0);
57003: SET_NFLG (((uae_s32)(src)) < 0);
57004: m68k_dreg(regs, dstreg) = (src);
57005: }}}}}m68k_incpc(6);
57006: fill_prefetch_0 ();
57007: endlabel3243: ;
57008: return 22;
57009: }
57010: unsigned long REGPARAM2 CPUFUNC(op_80ba_5)(uae_u32 opcode) /* OR */
57011: {
57012: uae_u32 dstreg = (opcode >> 9) & 7;
57013: OpcodeFamily = 1; CurrentInstrCycles = 18;
57014: {{ uaecptr srca = m68k_getpc () + 2;
57015: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
57016: if ((srca & 1) != 0) {
57017: last_fault_for_exception_3 = srca;
57018: last_op_for_exception_3 = opcode;
57019: last_addr_for_exception_3 = m68k_getpc() + 4;
57020: Exception(3, 0, M68000_EXC_SRC_CPU);
57021: goto endlabel3244;
57022: }
57023: {{ uae_s32 src = get_long(srca);
57024: { uae_s32 dst = m68k_dreg(regs, dstreg);
57025: src |= dst;
57026: CLEAR_CZNV;
57027: SET_ZFLG (((uae_s32)(src)) == 0);
57028: SET_NFLG (((uae_s32)(src)) < 0);
57029: m68k_dreg(regs, dstreg) = (src);
57030: }}}}}m68k_incpc(4);
57031: fill_prefetch_0 ();
57032: endlabel3244: ;
57033: return 18;
57034: }
57035: unsigned long REGPARAM2 CPUFUNC(op_80bb_5)(uae_u32 opcode) /* OR */
57036: {
57037: uae_u32 dstreg = (opcode >> 9) & 7;
57038: OpcodeFamily = 1; CurrentInstrCycles = 20;
57039: {{ uaecptr tmppc = m68k_getpc() + 2;
57040: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
57041: BusCyclePenalty += 2;
57042: if ((srca & 1) != 0) {
57043: last_fault_for_exception_3 = srca;
57044: last_op_for_exception_3 = opcode;
57045: last_addr_for_exception_3 = m68k_getpc() + 4;
57046: Exception(3, 0, M68000_EXC_SRC_CPU);
57047: goto endlabel3245;
57048: }
57049: {{ uae_s32 src = get_long(srca);
57050: { uae_s32 dst = m68k_dreg(regs, dstreg);
57051: src |= dst;
57052: CLEAR_CZNV;
57053: SET_ZFLG (((uae_s32)(src)) == 0);
57054: SET_NFLG (((uae_s32)(src)) < 0);
57055: m68k_dreg(regs, dstreg) = (src);
57056: }}}}}m68k_incpc(4);
57057: fill_prefetch_0 ();
57058: endlabel3245: ;
57059: return 20;
57060: }
57061: unsigned long REGPARAM2 CPUFUNC(op_80bc_5)(uae_u32 opcode) /* OR */
57062: {
57063: uae_u32 dstreg = (opcode >> 9) & 7;
57064: OpcodeFamily = 1; CurrentInstrCycles = 16;
57065: {{ uae_s32 src = get_ilong_prefetch(2);
57066: { uae_s32 dst = m68k_dreg(regs, dstreg);
57067: src |= dst;
57068: CLEAR_CZNV;
57069: SET_ZFLG (((uae_s32)(src)) == 0);
57070: SET_NFLG (((uae_s32)(src)) < 0);
57071: m68k_dreg(regs, dstreg) = (src);
57072: }}}m68k_incpc(6);
57073: fill_prefetch_0 ();
57074: return 16;
57075: }
57076: unsigned long REGPARAM2 CPUFUNC(op_80c0_5)(uae_u32 opcode) /* DIVU */
57077: {
57078: uae_u32 srcreg = (opcode & 7);
57079: uae_u32 dstreg = (opcode >> 9) & 7;
57080: unsigned int retcycles = 0;
57081: OpcodeFamily = 60; CurrentInstrCycles = 4;
57082: { uaecptr oldpc = m68k_getpc();
57083: { uae_s16 src = m68k_dreg(regs, srcreg);
57084: { uae_s32 dst = m68k_dreg(regs, dstreg);
57085: m68k_incpc(2);
57086: fill_prefetch_2 ();
57087: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3247; } else {
57088: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57089: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57090: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57091: {
57092: CLEAR_CZNV;
57093: SET_ZFLG (((uae_s16)(newv)) == 0);
57094: SET_NFLG (((uae_s16)(newv)) < 0);
57095: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57096: m68k_dreg(regs, dstreg) = (newv);
57097: }
57098: }
57099: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57100: }}}endlabel3247: ;
57101: return (4+retcycles);
57102: }
57103: unsigned long REGPARAM2 CPUFUNC(op_80d0_5)(uae_u32 opcode) /* DIVU */
57104: {
57105: uae_u32 srcreg = (opcode & 7);
57106: uae_u32 dstreg = (opcode >> 9) & 7;
57107: unsigned int retcycles = 0;
57108: OpcodeFamily = 60; CurrentInstrCycles = 8;
57109: { uaecptr oldpc = m68k_getpc();
57110: { uaecptr srca = m68k_areg(regs, srcreg);
57111: if ((srca & 1) != 0) {
57112: last_fault_for_exception_3 = srca;
57113: last_op_for_exception_3 = opcode;
57114: last_addr_for_exception_3 = m68k_getpc() + 2;
57115: Exception(3, 0, M68000_EXC_SRC_CPU);
57116: goto endlabel3248;
57117: }
57118: {{ uae_s16 src = get_word(srca);
57119: { uae_s32 dst = m68k_dreg(regs, dstreg);
57120: m68k_incpc(2);
57121: fill_prefetch_2 ();
57122: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3248; } else {
57123: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57124: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57125: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57126: {
57127: CLEAR_CZNV;
57128: SET_ZFLG (((uae_s16)(newv)) == 0);
57129: SET_NFLG (((uae_s16)(newv)) < 0);
57130: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57131: m68k_dreg(regs, dstreg) = (newv);
57132: }
57133: }
57134: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57135: }}}}}endlabel3248: ;
57136: return (8+retcycles);
57137: }
57138: unsigned long REGPARAM2 CPUFUNC(op_80d8_5)(uae_u32 opcode) /* DIVU */
57139: {
57140: uae_u32 srcreg = (opcode & 7);
57141: uae_u32 dstreg = (opcode >> 9) & 7;
57142: unsigned int retcycles = 0;
57143: OpcodeFamily = 60; CurrentInstrCycles = 8;
57144: { uaecptr oldpc = m68k_getpc();
57145: { uaecptr srca = m68k_areg(regs, srcreg);
57146: if ((srca & 1) != 0) {
57147: last_fault_for_exception_3 = srca;
57148: last_op_for_exception_3 = opcode;
57149: last_addr_for_exception_3 = m68k_getpc() + 2;
57150: Exception(3, 0, M68000_EXC_SRC_CPU);
57151: goto endlabel3249;
57152: }
57153: {{ uae_s16 src = get_word(srca);
57154: m68k_areg(regs, srcreg) += 2;
57155: { uae_s32 dst = m68k_dreg(regs, dstreg);
57156: m68k_incpc(2);
57157: fill_prefetch_2 ();
57158: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3249; } else {
57159: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57160: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57161: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57162: {
57163: CLEAR_CZNV;
57164: SET_ZFLG (((uae_s16)(newv)) == 0);
57165: SET_NFLG (((uae_s16)(newv)) < 0);
57166: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57167: m68k_dreg(regs, dstreg) = (newv);
57168: }
57169: }
57170: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57171: }}}}}endlabel3249: ;
57172: return (8+retcycles);
57173: }
57174: unsigned long REGPARAM2 CPUFUNC(op_80e0_5)(uae_u32 opcode) /* DIVU */
57175: {
57176: uae_u32 srcreg = (opcode & 7);
57177: uae_u32 dstreg = (opcode >> 9) & 7;
57178: unsigned int retcycles = 0;
57179: OpcodeFamily = 60; CurrentInstrCycles = 10;
57180: { uaecptr oldpc = m68k_getpc();
57181: { uaecptr srca = m68k_areg(regs, srcreg) - 2;
57182: if ((srca & 1) != 0) {
57183: last_fault_for_exception_3 = srca;
57184: last_op_for_exception_3 = opcode;
57185: last_addr_for_exception_3 = m68k_getpc() + 2;
57186: Exception(3, 0, M68000_EXC_SRC_CPU);
57187: goto endlabel3250;
57188: }
57189: {{ uae_s16 src = get_word(srca);
57190: m68k_areg (regs, srcreg) = srca;
57191: { uae_s32 dst = m68k_dreg(regs, dstreg);
57192: m68k_incpc(2);
57193: fill_prefetch_2 ();
57194: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3250; } else {
57195: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57196: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57197: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57198: {
57199: CLEAR_CZNV;
57200: SET_ZFLG (((uae_s16)(newv)) == 0);
57201: SET_NFLG (((uae_s16)(newv)) < 0);
57202: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57203: m68k_dreg(regs, dstreg) = (newv);
57204: }
57205: }
57206: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57207: }}}}}endlabel3250: ;
57208: return (10+retcycles);
57209: }
57210: unsigned long REGPARAM2 CPUFUNC(op_80e8_5)(uae_u32 opcode) /* DIVU */
57211: {
57212: uae_u32 srcreg = (opcode & 7);
57213: uae_u32 dstreg = (opcode >> 9) & 7;
57214: unsigned int retcycles = 0;
57215: OpcodeFamily = 60; CurrentInstrCycles = 12;
57216: { uaecptr oldpc = m68k_getpc();
57217: { uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
57218: if ((srca & 1) != 0) {
57219: last_fault_for_exception_3 = srca;
57220: last_op_for_exception_3 = opcode;
57221: last_addr_for_exception_3 = m68k_getpc() + 4;
57222: Exception(3, 0, M68000_EXC_SRC_CPU);
57223: goto endlabel3251;
57224: }
57225: {{ uae_s16 src = get_word(srca);
57226: { uae_s32 dst = m68k_dreg(regs, dstreg);
57227: m68k_incpc(4);
57228: fill_prefetch_0 ();
57229: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3251; } else {
57230: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57231: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57232: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57233: {
57234: CLEAR_CZNV;
57235: SET_ZFLG (((uae_s16)(newv)) == 0);
57236: SET_NFLG (((uae_s16)(newv)) < 0);
57237: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57238: m68k_dreg(regs, dstreg) = (newv);
57239: }
57240: }
57241: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57242: }}}}}endlabel3251: ;
57243: return (12+retcycles);
57244: }
57245: unsigned long REGPARAM2 CPUFUNC(op_80f0_5)(uae_u32 opcode) /* DIVU */
57246: {
57247: uae_u32 srcreg = (opcode & 7);
57248: uae_u32 dstreg = (opcode >> 9) & 7;
57249: unsigned int retcycles = 0;
57250: OpcodeFamily = 60; CurrentInstrCycles = 14;
57251: { uaecptr oldpc = m68k_getpc();
57252: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
57253: BusCyclePenalty += 2;
57254: if ((srca & 1) != 0) {
57255: last_fault_for_exception_3 = srca;
57256: last_op_for_exception_3 = opcode;
57257: last_addr_for_exception_3 = m68k_getpc() + 4;
57258: Exception(3, 0, M68000_EXC_SRC_CPU);
57259: goto endlabel3252;
57260: }
57261: {{ uae_s16 src = get_word(srca);
57262: { uae_s32 dst = m68k_dreg(regs, dstreg);
57263: m68k_incpc(4);
57264: fill_prefetch_0 ();
57265: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3252; } else {
57266: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57267: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57268: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57269: {
57270: CLEAR_CZNV;
57271: SET_ZFLG (((uae_s16)(newv)) == 0);
57272: SET_NFLG (((uae_s16)(newv)) < 0);
57273: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57274: m68k_dreg(regs, dstreg) = (newv);
57275: }
57276: }
57277: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57278: }}}}}endlabel3252: ;
57279: return (14+retcycles);
57280: }
57281: unsigned long REGPARAM2 CPUFUNC(op_80f8_5)(uae_u32 opcode) /* DIVU */
57282: {
57283: uae_u32 dstreg = (opcode >> 9) & 7;
57284: unsigned int retcycles = 0;
57285: OpcodeFamily = 60; CurrentInstrCycles = 12;
57286: { uaecptr oldpc = m68k_getpc();
57287: { uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
57288: if ((srca & 1) != 0) {
57289: last_fault_for_exception_3 = srca;
57290: last_op_for_exception_3 = opcode;
57291: last_addr_for_exception_3 = m68k_getpc() + 4;
57292: Exception(3, 0, M68000_EXC_SRC_CPU);
57293: goto endlabel3253;
57294: }
57295: {{ uae_s16 src = get_word(srca);
57296: { uae_s32 dst = m68k_dreg(regs, dstreg);
57297: m68k_incpc(4);
57298: fill_prefetch_0 ();
57299: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3253; } else {
57300: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57301: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57302: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57303: {
57304: CLEAR_CZNV;
57305: SET_ZFLG (((uae_s16)(newv)) == 0);
57306: SET_NFLG (((uae_s16)(newv)) < 0);
57307: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57308: m68k_dreg(regs, dstreg) = (newv);
57309: }
57310: }
57311: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57312: }}}}}endlabel3253: ;
57313: return (12+retcycles);
57314: }
57315: unsigned long REGPARAM2 CPUFUNC(op_80f9_5)(uae_u32 opcode) /* DIVU */
57316: {
57317: uae_u32 dstreg = (opcode >> 9) & 7;
57318: unsigned int retcycles = 0;
57319: OpcodeFamily = 60; CurrentInstrCycles = 16;
57320: { uaecptr oldpc = m68k_getpc();
57321: { uaecptr srca = get_ilong_prefetch(2);
57322: if ((srca & 1) != 0) {
57323: last_fault_for_exception_3 = srca;
57324: last_op_for_exception_3 = opcode;
57325: last_addr_for_exception_3 = m68k_getpc() + 6;
57326: Exception(3, 0, M68000_EXC_SRC_CPU);
57327: goto endlabel3254;
57328: }
57329: {{ uae_s16 src = get_word(srca);
57330: { uae_s32 dst = m68k_dreg(regs, dstreg);
57331: m68k_incpc(6);
57332: fill_prefetch_0 ();
57333: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3254; } else {
57334: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57335: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57336: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57337: {
57338: CLEAR_CZNV;
57339: SET_ZFLG (((uae_s16)(newv)) == 0);
57340: SET_NFLG (((uae_s16)(newv)) < 0);
57341: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57342: m68k_dreg(regs, dstreg) = (newv);
57343: }
57344: }
57345: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57346: }}}}}endlabel3254: ;
57347: return (16+retcycles);
57348: }
57349: unsigned long REGPARAM2 CPUFUNC(op_80fa_5)(uae_u32 opcode) /* DIVU */
57350: {
57351: uae_u32 dstreg = (opcode >> 9) & 7;
57352: unsigned int retcycles = 0;
57353: OpcodeFamily = 60; CurrentInstrCycles = 12;
57354: { uaecptr oldpc = m68k_getpc();
57355: { uaecptr srca = m68k_getpc () + 2;
57356: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
57357: if ((srca & 1) != 0) {
57358: last_fault_for_exception_3 = srca;
57359: last_op_for_exception_3 = opcode;
57360: last_addr_for_exception_3 = m68k_getpc() + 4;
57361: Exception(3, 0, M68000_EXC_SRC_CPU);
57362: goto endlabel3255;
57363: }
57364: {{ uae_s16 src = get_word(srca);
57365: { uae_s32 dst = m68k_dreg(regs, dstreg);
57366: m68k_incpc(4);
57367: fill_prefetch_0 ();
57368: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3255; } else {
57369: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57370: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57371: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57372: {
57373: CLEAR_CZNV;
57374: SET_ZFLG (((uae_s16)(newv)) == 0);
57375: SET_NFLG (((uae_s16)(newv)) < 0);
57376: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57377: m68k_dreg(regs, dstreg) = (newv);
57378: }
57379: }
57380: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57381: }}}}}endlabel3255: ;
57382: return (12+retcycles);
57383: }
57384: unsigned long REGPARAM2 CPUFUNC(op_80fb_5)(uae_u32 opcode) /* DIVU */
57385: {
57386: uae_u32 dstreg = (opcode >> 9) & 7;
57387: unsigned int retcycles = 0;
57388: OpcodeFamily = 60; CurrentInstrCycles = 14;
57389: { uaecptr oldpc = m68k_getpc();
57390: { uaecptr tmppc = m68k_getpc() + 2;
57391: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
57392: BusCyclePenalty += 2;
57393: if ((srca & 1) != 0) {
57394: last_fault_for_exception_3 = srca;
57395: last_op_for_exception_3 = opcode;
57396: last_addr_for_exception_3 = m68k_getpc() + 4;
57397: Exception(3, 0, M68000_EXC_SRC_CPU);
57398: goto endlabel3256;
57399: }
57400: {{ uae_s16 src = get_word(srca);
57401: { uae_s32 dst = m68k_dreg(regs, dstreg);
57402: m68k_incpc(4);
57403: fill_prefetch_0 ();
57404: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3256; } else {
57405: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57406: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57407: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57408: {
57409: CLEAR_CZNV;
57410: SET_ZFLG (((uae_s16)(newv)) == 0);
57411: SET_NFLG (((uae_s16)(newv)) < 0);
57412: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57413: m68k_dreg(regs, dstreg) = (newv);
57414: }
57415: }
57416: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57417: }}}}}endlabel3256: ;
57418: return (14+retcycles);
57419: }
57420: unsigned long REGPARAM2 CPUFUNC(op_80fc_5)(uae_u32 opcode) /* DIVU */
57421: {
57422: uae_u32 dstreg = (opcode >> 9) & 7;
57423: unsigned int retcycles = 0;
57424: OpcodeFamily = 60; CurrentInstrCycles = 8;
57425: { uaecptr oldpc = m68k_getpc();
57426: { uae_s16 src = get_iword_prefetch(2);
57427: { uae_s32 dst = m68k_dreg(regs, dstreg);
57428: m68k_incpc(4);
57429: fill_prefetch_0 ();
57430: if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel3257; } else {
57431: uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
57432: uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
57433: if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57434: {
57435: CLEAR_CZNV;
57436: SET_ZFLG (((uae_s16)(newv)) == 0);
57437: SET_NFLG (((uae_s16)(newv)) < 0);
57438: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57439: m68k_dreg(regs, dstreg) = (newv);
57440: }
57441: }
57442: retcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);
57443: }}}endlabel3257: ;
57444: return (8+retcycles);
57445: }
57446: unsigned long REGPARAM2 CPUFUNC(op_8100_5)(uae_u32 opcode) /* SBCD */
57447: {
57448: uae_u32 srcreg = (opcode & 7);
57449: uae_u32 dstreg = (opcode >> 9) & 7;
57450: OpcodeFamily = 10; CurrentInstrCycles = 6;
57451: {{ uae_s8 src = m68k_dreg(regs, srcreg);
57452: { uae_s8 dst = m68k_dreg(regs, dstreg);
57453: { uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);
57454: uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
57455: uae_u16 newv, tmp_newv;
57456: int bcd = 0;
57457: newv = tmp_newv = newv_hi + newv_lo;
57458: if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
57459: if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
57460: SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);
57461: COPY_CARRY;
57462: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
57463: SET_NFLG (((uae_s8)(newv)) < 0);
57464: SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
57465: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
57466: }}}}m68k_incpc(2);
57467: fill_prefetch_2 ();
57468: return 6;
57469: }
57470: unsigned long REGPARAM2 CPUFUNC(op_8108_5)(uae_u32 opcode) /* SBCD */
57471: {
57472: uae_u32 srcreg = (opcode & 7);
57473: uae_u32 dstreg = (opcode >> 9) & 7;
57474: OpcodeFamily = 10; CurrentInstrCycles = 18;
57475: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
57476: { uae_s8 src = get_byte(srca);
57477: m68k_areg (regs, srcreg) = srca;
57478: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
57479: { uae_s8 dst = get_byte(dsta);
57480: m68k_areg (regs, dstreg) = dsta;
57481: { uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);
57482: uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
57483: uae_u16 newv, tmp_newv;
57484: int bcd = 0;
57485: newv = tmp_newv = newv_hi + newv_lo;
57486: if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
57487: if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
57488: SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);
57489: COPY_CARRY;
57490: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
57491: SET_NFLG (((uae_s8)(newv)) < 0);
57492: SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
57493: m68k_incpc(2);
57494: fill_prefetch_2 ();
57495: put_byte(dsta,newv);
57496: }}}}}}return 18;
57497: }
57498: unsigned long REGPARAM2 CPUFUNC(op_8110_5)(uae_u32 opcode) /* OR */
57499: {
57500: uae_u32 srcreg = ((opcode >> 9) & 7);
57501: uae_u32 dstreg = opcode & 7;
57502: OpcodeFamily = 1; CurrentInstrCycles = 12;
57503: {{ uae_s8 src = m68k_dreg(regs, srcreg);
57504: { uaecptr dsta = m68k_areg(regs, dstreg);
57505: { uae_s8 dst = get_byte(dsta);
57506: src |= dst;
57507: CLEAR_CZNV;
57508: SET_ZFLG (((uae_s8)(src)) == 0);
57509: SET_NFLG (((uae_s8)(src)) < 0);
57510: m68k_incpc(2);
57511: fill_prefetch_2 ();
57512: put_byte(dsta,src);
57513: }}}}return 12;
57514: }
57515: unsigned long REGPARAM2 CPUFUNC(op_8118_5)(uae_u32 opcode) /* OR */
57516: {
57517: uae_u32 srcreg = ((opcode >> 9) & 7);
57518: uae_u32 dstreg = opcode & 7;
57519: OpcodeFamily = 1; CurrentInstrCycles = 12;
57520: {{ uae_s8 src = m68k_dreg(regs, srcreg);
57521: { uaecptr dsta = m68k_areg(regs, dstreg);
57522: { uae_s8 dst = get_byte(dsta);
57523: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
57524: src |= dst;
57525: CLEAR_CZNV;
57526: SET_ZFLG (((uae_s8)(src)) == 0);
57527: SET_NFLG (((uae_s8)(src)) < 0);
57528: m68k_incpc(2);
57529: fill_prefetch_2 ();
57530: put_byte(dsta,src);
57531: }}}}return 12;
57532: }
57533: unsigned long REGPARAM2 CPUFUNC(op_8120_5)(uae_u32 opcode) /* OR */
57534: {
57535: uae_u32 srcreg = ((opcode >> 9) & 7);
57536: uae_u32 dstreg = opcode & 7;
57537: OpcodeFamily = 1; CurrentInstrCycles = 14;
57538: {{ uae_s8 src = m68k_dreg(regs, srcreg);
57539: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
57540: { uae_s8 dst = get_byte(dsta);
57541: m68k_areg (regs, dstreg) = dsta;
57542: src |= dst;
57543: CLEAR_CZNV;
57544: SET_ZFLG (((uae_s8)(src)) == 0);
57545: SET_NFLG (((uae_s8)(src)) < 0);
57546: m68k_incpc(2);
57547: fill_prefetch_2 ();
57548: put_byte(dsta,src);
57549: }}}}return 14;
57550: }
57551: unsigned long REGPARAM2 CPUFUNC(op_8128_5)(uae_u32 opcode) /* OR */
57552: {
57553: uae_u32 srcreg = ((opcode >> 9) & 7);
57554: uae_u32 dstreg = opcode & 7;
57555: OpcodeFamily = 1; CurrentInstrCycles = 16;
57556: {{ uae_s8 src = m68k_dreg(regs, srcreg);
57557: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
57558: { uae_s8 dst = get_byte(dsta);
57559: src |= dst;
57560: CLEAR_CZNV;
57561: SET_ZFLG (((uae_s8)(src)) == 0);
57562: SET_NFLG (((uae_s8)(src)) < 0);
57563: m68k_incpc(4);
57564: fill_prefetch_0 ();
57565: put_byte(dsta,src);
57566: }}}}return 16;
57567: }
57568: unsigned long REGPARAM2 CPUFUNC(op_8130_5)(uae_u32 opcode) /* OR */
57569: {
57570: uae_u32 srcreg = ((opcode >> 9) & 7);
57571: uae_u32 dstreg = opcode & 7;
57572: OpcodeFamily = 1; CurrentInstrCycles = 18;
57573: {{ uae_s8 src = m68k_dreg(regs, srcreg);
57574: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
57575: BusCyclePenalty += 2;
57576: { uae_s8 dst = get_byte(dsta);
57577: src |= dst;
57578: CLEAR_CZNV;
57579: SET_ZFLG (((uae_s8)(src)) == 0);
57580: SET_NFLG (((uae_s8)(src)) < 0);
57581: m68k_incpc(4);
57582: fill_prefetch_0 ();
57583: put_byte(dsta,src);
57584: }}}}return 18;
57585: }
57586: unsigned long REGPARAM2 CPUFUNC(op_8138_5)(uae_u32 opcode) /* OR */
57587: {
57588: uae_u32 srcreg = ((opcode >> 9) & 7);
57589: OpcodeFamily = 1; CurrentInstrCycles = 16;
57590: {{ uae_s8 src = m68k_dreg(regs, srcreg);
57591: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
57592: { uae_s8 dst = get_byte(dsta);
57593: src |= dst;
57594: CLEAR_CZNV;
57595: SET_ZFLG (((uae_s8)(src)) == 0);
57596: SET_NFLG (((uae_s8)(src)) < 0);
57597: m68k_incpc(4);
57598: fill_prefetch_0 ();
57599: put_byte(dsta,src);
57600: }}}}return 16;
57601: }
57602: unsigned long REGPARAM2 CPUFUNC(op_8139_5)(uae_u32 opcode) /* OR */
57603: {
57604: uae_u32 srcreg = ((opcode >> 9) & 7);
57605: OpcodeFamily = 1; CurrentInstrCycles = 20;
57606: {{ uae_s8 src = m68k_dreg(regs, srcreg);
57607: { uaecptr dsta = get_ilong_prefetch(2);
57608: { uae_s8 dst = get_byte(dsta);
57609: src |= dst;
57610: CLEAR_CZNV;
57611: SET_ZFLG (((uae_s8)(src)) == 0);
57612: SET_NFLG (((uae_s8)(src)) < 0);
57613: m68k_incpc(6);
57614: fill_prefetch_0 ();
57615: put_byte(dsta,src);
57616: }}}}return 20;
57617: }
57618: unsigned long REGPARAM2 CPUFUNC(op_8150_5)(uae_u32 opcode) /* OR */
57619: {
57620: uae_u32 srcreg = ((opcode >> 9) & 7);
57621: uae_u32 dstreg = opcode & 7;
57622: OpcodeFamily = 1; CurrentInstrCycles = 12;
57623: {{ uae_s16 src = m68k_dreg(regs, srcreg);
57624: { uaecptr dsta = m68k_areg(regs, dstreg);
57625: if ((dsta & 1) != 0) {
57626: last_fault_for_exception_3 = dsta;
57627: last_op_for_exception_3 = opcode;
57628: last_addr_for_exception_3 = m68k_getpc() + 2;
57629: Exception(3, 0, M68000_EXC_SRC_CPU);
57630: goto endlabel3267;
57631: }
57632: {{ uae_s16 dst = get_word(dsta);
57633: src |= dst;
57634: CLEAR_CZNV;
57635: SET_ZFLG (((uae_s16)(src)) == 0);
57636: SET_NFLG (((uae_s16)(src)) < 0);
57637: m68k_incpc(2);
57638: fill_prefetch_2 ();
57639: put_word(dsta,src);
57640: }}}}}endlabel3267: ;
57641: return 12;
57642: }
57643: unsigned long REGPARAM2 CPUFUNC(op_8158_5)(uae_u32 opcode) /* OR */
57644: {
57645: uae_u32 srcreg = ((opcode >> 9) & 7);
57646: uae_u32 dstreg = opcode & 7;
57647: OpcodeFamily = 1; CurrentInstrCycles = 12;
57648: {{ uae_s16 src = m68k_dreg(regs, srcreg);
57649: { uaecptr dsta = m68k_areg(regs, dstreg);
57650: if ((dsta & 1) != 0) {
57651: last_fault_for_exception_3 = dsta;
57652: last_op_for_exception_3 = opcode;
57653: last_addr_for_exception_3 = m68k_getpc() + 2;
57654: Exception(3, 0, M68000_EXC_SRC_CPU);
57655: goto endlabel3268;
57656: }
57657: {{ uae_s16 dst = get_word(dsta);
57658: m68k_areg(regs, dstreg) += 2;
57659: src |= dst;
57660: CLEAR_CZNV;
57661: SET_ZFLG (((uae_s16)(src)) == 0);
57662: SET_NFLG (((uae_s16)(src)) < 0);
57663: m68k_incpc(2);
57664: fill_prefetch_2 ();
57665: put_word(dsta,src);
57666: }}}}}endlabel3268: ;
57667: return 12;
57668: }
57669: unsigned long REGPARAM2 CPUFUNC(op_8160_5)(uae_u32 opcode) /* OR */
57670: {
57671: uae_u32 srcreg = ((opcode >> 9) & 7);
57672: uae_u32 dstreg = opcode & 7;
57673: OpcodeFamily = 1; CurrentInstrCycles = 14;
57674: {{ uae_s16 src = m68k_dreg(regs, srcreg);
57675: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
57676: if ((dsta & 1) != 0) {
57677: last_fault_for_exception_3 = dsta;
57678: last_op_for_exception_3 = opcode;
57679: last_addr_for_exception_3 = m68k_getpc() + 2;
57680: Exception(3, 0, M68000_EXC_SRC_CPU);
57681: goto endlabel3269;
57682: }
57683: {{ uae_s16 dst = get_word(dsta);
57684: m68k_areg (regs, dstreg) = dsta;
57685: src |= dst;
57686: CLEAR_CZNV;
57687: SET_ZFLG (((uae_s16)(src)) == 0);
57688: SET_NFLG (((uae_s16)(src)) < 0);
57689: m68k_incpc(2);
57690: fill_prefetch_2 ();
57691: put_word(dsta,src);
57692: }}}}}endlabel3269: ;
57693: return 14;
57694: }
57695: unsigned long REGPARAM2 CPUFUNC(op_8168_5)(uae_u32 opcode) /* OR */
57696: {
57697: uae_u32 srcreg = ((opcode >> 9) & 7);
57698: uae_u32 dstreg = opcode & 7;
57699: OpcodeFamily = 1; CurrentInstrCycles = 16;
57700: {{ uae_s16 src = m68k_dreg(regs, srcreg);
57701: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
57702: if ((dsta & 1) != 0) {
57703: last_fault_for_exception_3 = dsta;
57704: last_op_for_exception_3 = opcode;
57705: last_addr_for_exception_3 = m68k_getpc() + 4;
57706: Exception(3, 0, M68000_EXC_SRC_CPU);
57707: goto endlabel3270;
57708: }
57709: {{ uae_s16 dst = get_word(dsta);
57710: src |= dst;
57711: CLEAR_CZNV;
57712: SET_ZFLG (((uae_s16)(src)) == 0);
57713: SET_NFLG (((uae_s16)(src)) < 0);
57714: m68k_incpc(4);
57715: fill_prefetch_0 ();
57716: put_word(dsta,src);
57717: }}}}}endlabel3270: ;
57718: return 16;
57719: }
57720: unsigned long REGPARAM2 CPUFUNC(op_8170_5)(uae_u32 opcode) /* OR */
57721: {
57722: uae_u32 srcreg = ((opcode >> 9) & 7);
57723: uae_u32 dstreg = opcode & 7;
57724: OpcodeFamily = 1; CurrentInstrCycles = 18;
57725: {{ uae_s16 src = m68k_dreg(regs, srcreg);
57726: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
57727: BusCyclePenalty += 2;
57728: if ((dsta & 1) != 0) {
57729: last_fault_for_exception_3 = dsta;
57730: last_op_for_exception_3 = opcode;
57731: last_addr_for_exception_3 = m68k_getpc() + 4;
57732: Exception(3, 0, M68000_EXC_SRC_CPU);
57733: goto endlabel3271;
57734: }
57735: {{ uae_s16 dst = get_word(dsta);
57736: src |= dst;
57737: CLEAR_CZNV;
57738: SET_ZFLG (((uae_s16)(src)) == 0);
57739: SET_NFLG (((uae_s16)(src)) < 0);
57740: m68k_incpc(4);
57741: fill_prefetch_0 ();
57742: put_word(dsta,src);
57743: }}}}}endlabel3271: ;
57744: return 18;
57745: }
57746: unsigned long REGPARAM2 CPUFUNC(op_8178_5)(uae_u32 opcode) /* OR */
57747: {
57748: uae_u32 srcreg = ((opcode >> 9) & 7);
57749: OpcodeFamily = 1; CurrentInstrCycles = 16;
57750: {{ uae_s16 src = m68k_dreg(regs, srcreg);
57751: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
57752: if ((dsta & 1) != 0) {
57753: last_fault_for_exception_3 = dsta;
57754: last_op_for_exception_3 = opcode;
57755: last_addr_for_exception_3 = m68k_getpc() + 4;
57756: Exception(3, 0, M68000_EXC_SRC_CPU);
57757: goto endlabel3272;
57758: }
57759: {{ uae_s16 dst = get_word(dsta);
57760: src |= dst;
57761: CLEAR_CZNV;
57762: SET_ZFLG (((uae_s16)(src)) == 0);
57763: SET_NFLG (((uae_s16)(src)) < 0);
57764: m68k_incpc(4);
57765: fill_prefetch_0 ();
57766: put_word(dsta,src);
57767: }}}}}endlabel3272: ;
57768: return 16;
57769: }
57770: unsigned long REGPARAM2 CPUFUNC(op_8179_5)(uae_u32 opcode) /* OR */
57771: {
57772: uae_u32 srcreg = ((opcode >> 9) & 7);
57773: OpcodeFamily = 1; CurrentInstrCycles = 20;
57774: {{ uae_s16 src = m68k_dreg(regs, srcreg);
57775: { uaecptr dsta = get_ilong_prefetch(2);
57776: if ((dsta & 1) != 0) {
57777: last_fault_for_exception_3 = dsta;
57778: last_op_for_exception_3 = opcode;
57779: last_addr_for_exception_3 = m68k_getpc() + 6;
57780: Exception(3, 0, M68000_EXC_SRC_CPU);
57781: goto endlabel3273;
57782: }
57783: {{ uae_s16 dst = get_word(dsta);
57784: src |= dst;
57785: CLEAR_CZNV;
57786: SET_ZFLG (((uae_s16)(src)) == 0);
57787: SET_NFLG (((uae_s16)(src)) < 0);
57788: m68k_incpc(6);
57789: fill_prefetch_0 ();
57790: put_word(dsta,src);
57791: }}}}}endlabel3273: ;
57792: return 20;
57793: }
57794: unsigned long REGPARAM2 CPUFUNC(op_8190_5)(uae_u32 opcode) /* OR */
57795: {
57796: uae_u32 srcreg = ((opcode >> 9) & 7);
57797: uae_u32 dstreg = opcode & 7;
57798: OpcodeFamily = 1; CurrentInstrCycles = 20;
57799: {{ uae_s32 src = m68k_dreg(regs, srcreg);
57800: { uaecptr dsta = m68k_areg(regs, dstreg);
57801: if ((dsta & 1) != 0) {
57802: last_fault_for_exception_3 = dsta;
57803: last_op_for_exception_3 = opcode;
57804: last_addr_for_exception_3 = m68k_getpc() + 2;
57805: Exception(3, 0, M68000_EXC_SRC_CPU);
57806: goto endlabel3274;
57807: }
57808: {{ uae_s32 dst = get_long(dsta);
57809: src |= dst;
57810: CLEAR_CZNV;
57811: SET_ZFLG (((uae_s32)(src)) == 0);
57812: SET_NFLG (((uae_s32)(src)) < 0);
57813: m68k_incpc(2);
57814: fill_prefetch_2 ();
57815: put_long(dsta,src);
57816: }}}}}endlabel3274: ;
57817: return 20;
57818: }
57819: unsigned long REGPARAM2 CPUFUNC(op_8198_5)(uae_u32 opcode) /* OR */
57820: {
57821: uae_u32 srcreg = ((opcode >> 9) & 7);
57822: uae_u32 dstreg = opcode & 7;
57823: OpcodeFamily = 1; CurrentInstrCycles = 20;
57824: {{ uae_s32 src = m68k_dreg(regs, srcreg);
57825: { uaecptr dsta = m68k_areg(regs, dstreg);
57826: if ((dsta & 1) != 0) {
57827: last_fault_for_exception_3 = dsta;
57828: last_op_for_exception_3 = opcode;
57829: last_addr_for_exception_3 = m68k_getpc() + 2;
57830: Exception(3, 0, M68000_EXC_SRC_CPU);
57831: goto endlabel3275;
57832: }
57833: {{ uae_s32 dst = get_long(dsta);
57834: m68k_areg(regs, dstreg) += 4;
57835: src |= dst;
57836: CLEAR_CZNV;
57837: SET_ZFLG (((uae_s32)(src)) == 0);
57838: SET_NFLG (((uae_s32)(src)) < 0);
57839: m68k_incpc(2);
57840: fill_prefetch_2 ();
57841: put_long(dsta,src);
57842: }}}}}endlabel3275: ;
57843: return 20;
57844: }
57845: unsigned long REGPARAM2 CPUFUNC(op_81a0_5)(uae_u32 opcode) /* OR */
57846: {
57847: uae_u32 srcreg = ((opcode >> 9) & 7);
57848: uae_u32 dstreg = opcode & 7;
57849: OpcodeFamily = 1; CurrentInstrCycles = 22;
57850: {{ uae_s32 src = m68k_dreg(regs, srcreg);
57851: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
57852: if ((dsta & 1) != 0) {
57853: last_fault_for_exception_3 = dsta;
57854: last_op_for_exception_3 = opcode;
57855: last_addr_for_exception_3 = m68k_getpc() + 2;
57856: Exception(3, 0, M68000_EXC_SRC_CPU);
57857: goto endlabel3276;
57858: }
57859: {{ uae_s32 dst = get_long(dsta);
57860: m68k_areg (regs, dstreg) = dsta;
57861: src |= dst;
57862: CLEAR_CZNV;
57863: SET_ZFLG (((uae_s32)(src)) == 0);
57864: SET_NFLG (((uae_s32)(src)) < 0);
57865: m68k_incpc(2);
57866: fill_prefetch_2 ();
57867: put_long(dsta,src);
57868: }}}}}endlabel3276: ;
57869: return 22;
57870: }
57871: unsigned long REGPARAM2 CPUFUNC(op_81a8_5)(uae_u32 opcode) /* OR */
57872: {
57873: uae_u32 srcreg = ((opcode >> 9) & 7);
57874: uae_u32 dstreg = opcode & 7;
57875: OpcodeFamily = 1; CurrentInstrCycles = 24;
57876: {{ uae_s32 src = m68k_dreg(regs, srcreg);
57877: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
57878: if ((dsta & 1) != 0) {
57879: last_fault_for_exception_3 = dsta;
57880: last_op_for_exception_3 = opcode;
57881: last_addr_for_exception_3 = m68k_getpc() + 4;
57882: Exception(3, 0, M68000_EXC_SRC_CPU);
57883: goto endlabel3277;
57884: }
57885: {{ uae_s32 dst = get_long(dsta);
57886: src |= dst;
57887: CLEAR_CZNV;
57888: SET_ZFLG (((uae_s32)(src)) == 0);
57889: SET_NFLG (((uae_s32)(src)) < 0);
57890: m68k_incpc(4);
57891: fill_prefetch_0 ();
57892: put_long(dsta,src);
57893: }}}}}endlabel3277: ;
57894: return 24;
57895: }
57896: unsigned long REGPARAM2 CPUFUNC(op_81b0_5)(uae_u32 opcode) /* OR */
57897: {
57898: uae_u32 srcreg = ((opcode >> 9) & 7);
57899: uae_u32 dstreg = opcode & 7;
57900: OpcodeFamily = 1; CurrentInstrCycles = 26;
57901: {{ uae_s32 src = m68k_dreg(regs, srcreg);
57902: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
57903: BusCyclePenalty += 2;
57904: if ((dsta & 1) != 0) {
57905: last_fault_for_exception_3 = dsta;
57906: last_op_for_exception_3 = opcode;
57907: last_addr_for_exception_3 = m68k_getpc() + 4;
57908: Exception(3, 0, M68000_EXC_SRC_CPU);
57909: goto endlabel3278;
57910: }
57911: {{ uae_s32 dst = get_long(dsta);
57912: src |= dst;
57913: CLEAR_CZNV;
57914: SET_ZFLG (((uae_s32)(src)) == 0);
57915: SET_NFLG (((uae_s32)(src)) < 0);
57916: m68k_incpc(4);
57917: fill_prefetch_0 ();
57918: put_long(dsta,src);
57919: }}}}}endlabel3278: ;
57920: return 26;
57921: }
57922: unsigned long REGPARAM2 CPUFUNC(op_81b8_5)(uae_u32 opcode) /* OR */
57923: {
57924: uae_u32 srcreg = ((opcode >> 9) & 7);
57925: OpcodeFamily = 1; CurrentInstrCycles = 24;
57926: {{ uae_s32 src = m68k_dreg(regs, srcreg);
57927: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
57928: if ((dsta & 1) != 0) {
57929: last_fault_for_exception_3 = dsta;
57930: last_op_for_exception_3 = opcode;
57931: last_addr_for_exception_3 = m68k_getpc() + 4;
57932: Exception(3, 0, M68000_EXC_SRC_CPU);
57933: goto endlabel3279;
57934: }
57935: {{ uae_s32 dst = get_long(dsta);
57936: src |= dst;
57937: CLEAR_CZNV;
57938: SET_ZFLG (((uae_s32)(src)) == 0);
57939: SET_NFLG (((uae_s32)(src)) < 0);
57940: m68k_incpc(4);
57941: fill_prefetch_0 ();
57942: put_long(dsta,src);
57943: }}}}}endlabel3279: ;
57944: return 24;
57945: }
57946: unsigned long REGPARAM2 CPUFUNC(op_81b9_5)(uae_u32 opcode) /* OR */
57947: {
57948: uae_u32 srcreg = ((opcode >> 9) & 7);
57949: OpcodeFamily = 1; CurrentInstrCycles = 28;
57950: {{ uae_s32 src = m68k_dreg(regs, srcreg);
57951: { uaecptr dsta = get_ilong_prefetch(2);
57952: if ((dsta & 1) != 0) {
57953: last_fault_for_exception_3 = dsta;
57954: last_op_for_exception_3 = opcode;
57955: last_addr_for_exception_3 = m68k_getpc() + 6;
57956: Exception(3, 0, M68000_EXC_SRC_CPU);
57957: goto endlabel3280;
57958: }
57959: {{ uae_s32 dst = get_long(dsta);
57960: src |= dst;
57961: CLEAR_CZNV;
57962: SET_ZFLG (((uae_s32)(src)) == 0);
57963: SET_NFLG (((uae_s32)(src)) < 0);
57964: m68k_incpc(6);
57965: fill_prefetch_0 ();
57966: put_long(dsta,src);
57967: }}}}}endlabel3280: ;
57968: return 28;
57969: }
57970: unsigned long REGPARAM2 CPUFUNC(op_81c0_5)(uae_u32 opcode) /* DIVS */
57971: {
57972: uae_u32 srcreg = (opcode & 7);
57973: uae_u32 dstreg = (opcode >> 9) & 7;
57974: unsigned int retcycles = 0;
57975: OpcodeFamily = 61; CurrentInstrCycles = 4;
57976: { uaecptr oldpc = m68k_getpc();
57977: { uae_s16 src = m68k_dreg(regs, srcreg);
57978: { uae_s32 dst = m68k_dreg(regs, dstreg);
57979: m68k_incpc(2);
57980: fill_prefetch_2 ();
57981: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3281; } else {
57982: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
57983: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
57984: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
57985: {
57986: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
57987: CLEAR_CZNV;
57988: SET_ZFLG (((uae_s16)(newv)) == 0);
57989: SET_NFLG (((uae_s16)(newv)) < 0);
57990: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
57991: m68k_dreg(regs, dstreg) = (newv);
57992: }
57993: }
57994: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
57995: }}}endlabel3281: ;
57996: return (4+retcycles);
57997: }
57998: unsigned long REGPARAM2 CPUFUNC(op_81d0_5)(uae_u32 opcode) /* DIVS */
57999: {
58000: uae_u32 srcreg = (opcode & 7);
58001: uae_u32 dstreg = (opcode >> 9) & 7;
58002: unsigned int retcycles = 0;
58003: OpcodeFamily = 61; CurrentInstrCycles = 8;
58004: { uaecptr oldpc = m68k_getpc();
58005: { uaecptr srca = m68k_areg(regs, srcreg);
58006: if ((srca & 1) != 0) {
58007: last_fault_for_exception_3 = srca;
58008: last_op_for_exception_3 = opcode;
58009: last_addr_for_exception_3 = m68k_getpc() + 2;
58010: Exception(3, 0, M68000_EXC_SRC_CPU);
58011: goto endlabel3282;
58012: }
58013: {{ uae_s16 src = get_word(srca);
58014: { uae_s32 dst = m68k_dreg(regs, dstreg);
58015: m68k_incpc(2);
58016: fill_prefetch_2 ();
58017: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3282; } else {
58018: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58019: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58020: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58021: {
58022: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58023: CLEAR_CZNV;
58024: SET_ZFLG (((uae_s16)(newv)) == 0);
58025: SET_NFLG (((uae_s16)(newv)) < 0);
58026: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58027: m68k_dreg(regs, dstreg) = (newv);
58028: }
58029: }
58030: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58031: }}}}}endlabel3282: ;
58032: return (8+retcycles);
58033: }
58034: unsigned long REGPARAM2 CPUFUNC(op_81d8_5)(uae_u32 opcode) /* DIVS */
58035: {
58036: uae_u32 srcreg = (opcode & 7);
58037: uae_u32 dstreg = (opcode >> 9) & 7;
58038: unsigned int retcycles = 0;
58039: OpcodeFamily = 61; CurrentInstrCycles = 8;
58040: { uaecptr oldpc = m68k_getpc();
58041: { uaecptr srca = m68k_areg(regs, srcreg);
58042: if ((srca & 1) != 0) {
58043: last_fault_for_exception_3 = srca;
58044: last_op_for_exception_3 = opcode;
58045: last_addr_for_exception_3 = m68k_getpc() + 2;
58046: Exception(3, 0, M68000_EXC_SRC_CPU);
58047: goto endlabel3283;
58048: }
58049: {{ uae_s16 src = get_word(srca);
58050: m68k_areg(regs, srcreg) += 2;
58051: { uae_s32 dst = m68k_dreg(regs, dstreg);
58052: m68k_incpc(2);
58053: fill_prefetch_2 ();
58054: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3283; } else {
58055: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58056: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58057: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58058: {
58059: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58060: CLEAR_CZNV;
58061: SET_ZFLG (((uae_s16)(newv)) == 0);
58062: SET_NFLG (((uae_s16)(newv)) < 0);
58063: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58064: m68k_dreg(regs, dstreg) = (newv);
58065: }
58066: }
58067: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58068: }}}}}endlabel3283: ;
58069: return (8+retcycles);
58070: }
58071: unsigned long REGPARAM2 CPUFUNC(op_81e0_5)(uae_u32 opcode) /* DIVS */
58072: {
58073: uae_u32 srcreg = (opcode & 7);
58074: uae_u32 dstreg = (opcode >> 9) & 7;
58075: unsigned int retcycles = 0;
58076: OpcodeFamily = 61; CurrentInstrCycles = 10;
58077: { uaecptr oldpc = m68k_getpc();
58078: { uaecptr srca = m68k_areg(regs, srcreg) - 2;
58079: if ((srca & 1) != 0) {
58080: last_fault_for_exception_3 = srca;
58081: last_op_for_exception_3 = opcode;
58082: last_addr_for_exception_3 = m68k_getpc() + 2;
58083: Exception(3, 0, M68000_EXC_SRC_CPU);
58084: goto endlabel3284;
58085: }
58086: {{ uae_s16 src = get_word(srca);
58087: m68k_areg (regs, srcreg) = srca;
58088: { uae_s32 dst = m68k_dreg(regs, dstreg);
58089: m68k_incpc(2);
58090: fill_prefetch_2 ();
58091: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3284; } else {
58092: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58093: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58094: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58095: {
58096: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58097: CLEAR_CZNV;
58098: SET_ZFLG (((uae_s16)(newv)) == 0);
58099: SET_NFLG (((uae_s16)(newv)) < 0);
58100: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58101: m68k_dreg(regs, dstreg) = (newv);
58102: }
58103: }
58104: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58105: }}}}}endlabel3284: ;
58106: return (10+retcycles);
58107: }
58108: unsigned long REGPARAM2 CPUFUNC(op_81e8_5)(uae_u32 opcode) /* DIVS */
58109: {
58110: uae_u32 srcreg = (opcode & 7);
58111: uae_u32 dstreg = (opcode >> 9) & 7;
58112: unsigned int retcycles = 0;
58113: OpcodeFamily = 61; CurrentInstrCycles = 12;
58114: { uaecptr oldpc = m68k_getpc();
58115: { uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
58116: if ((srca & 1) != 0) {
58117: last_fault_for_exception_3 = srca;
58118: last_op_for_exception_3 = opcode;
58119: last_addr_for_exception_3 = m68k_getpc() + 4;
58120: Exception(3, 0, M68000_EXC_SRC_CPU);
58121: goto endlabel3285;
58122: }
58123: {{ uae_s16 src = get_word(srca);
58124: { uae_s32 dst = m68k_dreg(regs, dstreg);
58125: m68k_incpc(4);
58126: fill_prefetch_0 ();
58127: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3285; } else {
58128: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58129: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58130: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58131: {
58132: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58133: CLEAR_CZNV;
58134: SET_ZFLG (((uae_s16)(newv)) == 0);
58135: SET_NFLG (((uae_s16)(newv)) < 0);
58136: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58137: m68k_dreg(regs, dstreg) = (newv);
58138: }
58139: }
58140: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58141: }}}}}endlabel3285: ;
58142: return (12+retcycles);
58143: }
58144: unsigned long REGPARAM2 CPUFUNC(op_81f0_5)(uae_u32 opcode) /* DIVS */
58145: {
58146: uae_u32 srcreg = (opcode & 7);
58147: uae_u32 dstreg = (opcode >> 9) & 7;
58148: unsigned int retcycles = 0;
58149: OpcodeFamily = 61; CurrentInstrCycles = 14;
58150: { uaecptr oldpc = m68k_getpc();
58151: { uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
58152: BusCyclePenalty += 2;
58153: if ((srca & 1) != 0) {
58154: last_fault_for_exception_3 = srca;
58155: last_op_for_exception_3 = opcode;
58156: last_addr_for_exception_3 = m68k_getpc() + 4;
58157: Exception(3, 0, M68000_EXC_SRC_CPU);
58158: goto endlabel3286;
58159: }
58160: {{ uae_s16 src = get_word(srca);
58161: { uae_s32 dst = m68k_dreg(regs, dstreg);
58162: m68k_incpc(4);
58163: fill_prefetch_0 ();
58164: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3286; } else {
58165: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58166: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58167: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58168: {
58169: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58170: CLEAR_CZNV;
58171: SET_ZFLG (((uae_s16)(newv)) == 0);
58172: SET_NFLG (((uae_s16)(newv)) < 0);
58173: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58174: m68k_dreg(regs, dstreg) = (newv);
58175: }
58176: }
58177: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58178: }}}}}endlabel3286: ;
58179: return (14+retcycles);
58180: }
58181: unsigned long REGPARAM2 CPUFUNC(op_81f8_5)(uae_u32 opcode) /* DIVS */
58182: {
58183: uae_u32 dstreg = (opcode >> 9) & 7;
58184: unsigned int retcycles = 0;
58185: OpcodeFamily = 61; CurrentInstrCycles = 12;
58186: { uaecptr oldpc = m68k_getpc();
58187: { uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
58188: if ((srca & 1) != 0) {
58189: last_fault_for_exception_3 = srca;
58190: last_op_for_exception_3 = opcode;
58191: last_addr_for_exception_3 = m68k_getpc() + 4;
58192: Exception(3, 0, M68000_EXC_SRC_CPU);
58193: goto endlabel3287;
58194: }
58195: {{ uae_s16 src = get_word(srca);
58196: { uae_s32 dst = m68k_dreg(regs, dstreg);
58197: m68k_incpc(4);
58198: fill_prefetch_0 ();
58199: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3287; } else {
58200: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58201: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58202: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58203: {
58204: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58205: CLEAR_CZNV;
58206: SET_ZFLG (((uae_s16)(newv)) == 0);
58207: SET_NFLG (((uae_s16)(newv)) < 0);
58208: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58209: m68k_dreg(regs, dstreg) = (newv);
58210: }
58211: }
58212: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58213: }}}}}endlabel3287: ;
58214: return (12+retcycles);
58215: }
58216: unsigned long REGPARAM2 CPUFUNC(op_81f9_5)(uae_u32 opcode) /* DIVS */
58217: {
58218: uae_u32 dstreg = (opcode >> 9) & 7;
58219: unsigned int retcycles = 0;
58220: OpcodeFamily = 61; CurrentInstrCycles = 16;
58221: { uaecptr oldpc = m68k_getpc();
58222: { uaecptr srca = get_ilong_prefetch(2);
58223: if ((srca & 1) != 0) {
58224: last_fault_for_exception_3 = srca;
58225: last_op_for_exception_3 = opcode;
58226: last_addr_for_exception_3 = m68k_getpc() + 6;
58227: Exception(3, 0, M68000_EXC_SRC_CPU);
58228: goto endlabel3288;
58229: }
58230: {{ uae_s16 src = get_word(srca);
58231: { uae_s32 dst = m68k_dreg(regs, dstreg);
58232: m68k_incpc(6);
58233: fill_prefetch_0 ();
58234: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3288; } else {
58235: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58236: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58237: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58238: {
58239: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58240: CLEAR_CZNV;
58241: SET_ZFLG (((uae_s16)(newv)) == 0);
58242: SET_NFLG (((uae_s16)(newv)) < 0);
58243: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58244: m68k_dreg(regs, dstreg) = (newv);
58245: }
58246: }
58247: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58248: }}}}}endlabel3288: ;
58249: return (16+retcycles);
58250: }
58251: unsigned long REGPARAM2 CPUFUNC(op_81fa_5)(uae_u32 opcode) /* DIVS */
58252: {
58253: uae_u32 dstreg = (opcode >> 9) & 7;
58254: unsigned int retcycles = 0;
58255: OpcodeFamily = 61; CurrentInstrCycles = 12;
58256: { uaecptr oldpc = m68k_getpc();
58257: { uaecptr srca = m68k_getpc () + 2;
58258: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
58259: if ((srca & 1) != 0) {
58260: last_fault_for_exception_3 = srca;
58261: last_op_for_exception_3 = opcode;
58262: last_addr_for_exception_3 = m68k_getpc() + 4;
58263: Exception(3, 0, M68000_EXC_SRC_CPU);
58264: goto endlabel3289;
58265: }
58266: {{ uae_s16 src = get_word(srca);
58267: { uae_s32 dst = m68k_dreg(regs, dstreg);
58268: m68k_incpc(4);
58269: fill_prefetch_0 ();
58270: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3289; } else {
58271: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58272: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58273: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58274: {
58275: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58276: CLEAR_CZNV;
58277: SET_ZFLG (((uae_s16)(newv)) == 0);
58278: SET_NFLG (((uae_s16)(newv)) < 0);
58279: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58280: m68k_dreg(regs, dstreg) = (newv);
58281: }
58282: }
58283: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58284: }}}}}endlabel3289: ;
58285: return (12+retcycles);
58286: }
58287: unsigned long REGPARAM2 CPUFUNC(op_81fb_5)(uae_u32 opcode) /* DIVS */
58288: {
58289: uae_u32 dstreg = (opcode >> 9) & 7;
58290: unsigned int retcycles = 0;
58291: OpcodeFamily = 61; CurrentInstrCycles = 14;
58292: { uaecptr oldpc = m68k_getpc();
58293: { uaecptr tmppc = m68k_getpc() + 2;
58294: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
58295: BusCyclePenalty += 2;
58296: if ((srca & 1) != 0) {
58297: last_fault_for_exception_3 = srca;
58298: last_op_for_exception_3 = opcode;
58299: last_addr_for_exception_3 = m68k_getpc() + 4;
58300: Exception(3, 0, M68000_EXC_SRC_CPU);
58301: goto endlabel3290;
58302: }
58303: {{ uae_s16 src = get_word(srca);
58304: { uae_s32 dst = m68k_dreg(regs, dstreg);
58305: m68k_incpc(4);
58306: fill_prefetch_0 ();
58307: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3290; } else {
58308: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58309: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58310: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58311: {
58312: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58313: CLEAR_CZNV;
58314: SET_ZFLG (((uae_s16)(newv)) == 0);
58315: SET_NFLG (((uae_s16)(newv)) < 0);
58316: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58317: m68k_dreg(regs, dstreg) = (newv);
58318: }
58319: }
58320: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58321: }}}}}endlabel3290: ;
58322: return (14+retcycles);
58323: }
58324: unsigned long REGPARAM2 CPUFUNC(op_81fc_5)(uae_u32 opcode) /* DIVS */
58325: {
58326: uae_u32 dstreg = (opcode >> 9) & 7;
58327: unsigned int retcycles = 0;
58328: OpcodeFamily = 61; CurrentInstrCycles = 8;
58329: { uaecptr oldpc = m68k_getpc();
58330: { uae_s16 src = get_iword_prefetch(2);
58331: { uae_s32 dst = m68k_dreg(regs, dstreg);
58332: m68k_incpc(4);
58333: fill_prefetch_0 ();
58334: if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel3291; } else {
58335: uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
58336: uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
58337: if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
58338: {
58339: if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
58340: CLEAR_CZNV;
58341: SET_ZFLG (((uae_s16)(newv)) == 0);
58342: SET_NFLG (((uae_s16)(newv)) < 0);
58343: newv = (newv & 0xffff) | ((uae_u32)rem << 16);
58344: m68k_dreg(regs, dstreg) = (newv);
58345: }
58346: }
58347: retcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);
58348: }}}endlabel3291: ;
58349: return (8+retcycles);
58350: }
58351: unsigned long REGPARAM2 CPUFUNC(op_9000_5)(uae_u32 opcode) /* SUB */
58352: {
58353: uae_u32 srcreg = (opcode & 7);
58354: uae_u32 dstreg = (opcode >> 9) & 7;
58355: OpcodeFamily = 7; CurrentInstrCycles = 4;
58356: {{ uae_s8 src = m68k_dreg(regs, srcreg);
58357: { uae_s8 dst = m68k_dreg(regs, dstreg);
58358: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58359: { int flgs = ((uae_s8)(src)) < 0;
58360: int flgo = ((uae_s8)(dst)) < 0;
58361: int flgn = ((uae_s8)(newv)) < 0;
58362: SET_ZFLG (((uae_s8)(newv)) == 0);
58363: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58364: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58365: COPY_CARRY;
58366: SET_NFLG (flgn != 0);
58367: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58368: }}}}}}m68k_incpc(2);
58369: fill_prefetch_2 ();
58370: return 4;
58371: }
58372: unsigned long REGPARAM2 CPUFUNC(op_9010_5)(uae_u32 opcode) /* SUB */
58373: {
58374: uae_u32 srcreg = (opcode & 7);
58375: uae_u32 dstreg = (opcode >> 9) & 7;
58376: OpcodeFamily = 7; CurrentInstrCycles = 8;
58377: {{ uaecptr srca = m68k_areg(regs, srcreg);
58378: { uae_s8 src = get_byte(srca);
58379: { uae_s8 dst = m68k_dreg(regs, dstreg);
58380: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58381: { int flgs = ((uae_s8)(src)) < 0;
58382: int flgo = ((uae_s8)(dst)) < 0;
58383: int flgn = ((uae_s8)(newv)) < 0;
58384: SET_ZFLG (((uae_s8)(newv)) == 0);
58385: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58386: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58387: COPY_CARRY;
58388: SET_NFLG (flgn != 0);
58389: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58390: }}}}}}}m68k_incpc(2);
58391: fill_prefetch_2 ();
58392: return 8;
58393: }
58394: unsigned long REGPARAM2 CPUFUNC(op_9018_5)(uae_u32 opcode) /* SUB */
58395: {
58396: uae_u32 srcreg = (opcode & 7);
58397: uae_u32 dstreg = (opcode >> 9) & 7;
58398: OpcodeFamily = 7; CurrentInstrCycles = 8;
58399: {{ uaecptr srca = m68k_areg(regs, srcreg);
58400: { uae_s8 src = get_byte(srca);
58401: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
58402: { uae_s8 dst = m68k_dreg(regs, dstreg);
58403: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58404: { int flgs = ((uae_s8)(src)) < 0;
58405: int flgo = ((uae_s8)(dst)) < 0;
58406: int flgn = ((uae_s8)(newv)) < 0;
58407: SET_ZFLG (((uae_s8)(newv)) == 0);
58408: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58409: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58410: COPY_CARRY;
58411: SET_NFLG (flgn != 0);
58412: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58413: }}}}}}}m68k_incpc(2);
58414: fill_prefetch_2 ();
58415: return 8;
58416: }
58417: unsigned long REGPARAM2 CPUFUNC(op_9020_5)(uae_u32 opcode) /* SUB */
58418: {
58419: uae_u32 srcreg = (opcode & 7);
58420: uae_u32 dstreg = (opcode >> 9) & 7;
58421: OpcodeFamily = 7; CurrentInstrCycles = 10;
58422: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
58423: { uae_s8 src = get_byte(srca);
58424: m68k_areg (regs, srcreg) = srca;
58425: { uae_s8 dst = m68k_dreg(regs, dstreg);
58426: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58427: { int flgs = ((uae_s8)(src)) < 0;
58428: int flgo = ((uae_s8)(dst)) < 0;
58429: int flgn = ((uae_s8)(newv)) < 0;
58430: SET_ZFLG (((uae_s8)(newv)) == 0);
58431: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58432: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58433: COPY_CARRY;
58434: SET_NFLG (flgn != 0);
58435: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58436: }}}}}}}m68k_incpc(2);
58437: fill_prefetch_2 ();
58438: return 10;
58439: }
58440: unsigned long REGPARAM2 CPUFUNC(op_9028_5)(uae_u32 opcode) /* SUB */
58441: {
58442: uae_u32 srcreg = (opcode & 7);
58443: uae_u32 dstreg = (opcode >> 9) & 7;
58444: OpcodeFamily = 7; CurrentInstrCycles = 12;
58445: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
58446: { uae_s8 src = get_byte(srca);
58447: { uae_s8 dst = m68k_dreg(regs, dstreg);
58448: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58449: { int flgs = ((uae_s8)(src)) < 0;
58450: int flgo = ((uae_s8)(dst)) < 0;
58451: int flgn = ((uae_s8)(newv)) < 0;
58452: SET_ZFLG (((uae_s8)(newv)) == 0);
58453: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58454: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58455: COPY_CARRY;
58456: SET_NFLG (flgn != 0);
58457: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58458: }}}}}}}m68k_incpc(4);
58459: fill_prefetch_0 ();
58460: return 12;
58461: }
58462: unsigned long REGPARAM2 CPUFUNC(op_9030_5)(uae_u32 opcode) /* SUB */
58463: {
58464: uae_u32 srcreg = (opcode & 7);
58465: uae_u32 dstreg = (opcode >> 9) & 7;
58466: OpcodeFamily = 7; CurrentInstrCycles = 14;
58467: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
58468: BusCyclePenalty += 2;
58469: { uae_s8 src = get_byte(srca);
58470: { uae_s8 dst = m68k_dreg(regs, dstreg);
58471: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58472: { int flgs = ((uae_s8)(src)) < 0;
58473: int flgo = ((uae_s8)(dst)) < 0;
58474: int flgn = ((uae_s8)(newv)) < 0;
58475: SET_ZFLG (((uae_s8)(newv)) == 0);
58476: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58477: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58478: COPY_CARRY;
58479: SET_NFLG (flgn != 0);
58480: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58481: }}}}}}}m68k_incpc(4);
58482: fill_prefetch_0 ();
58483: return 14;
58484: }
58485: unsigned long REGPARAM2 CPUFUNC(op_9038_5)(uae_u32 opcode) /* SUB */
58486: {
58487: uae_u32 dstreg = (opcode >> 9) & 7;
58488: OpcodeFamily = 7; CurrentInstrCycles = 12;
58489: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
58490: { uae_s8 src = get_byte(srca);
58491: { uae_s8 dst = m68k_dreg(regs, dstreg);
58492: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58493: { int flgs = ((uae_s8)(src)) < 0;
58494: int flgo = ((uae_s8)(dst)) < 0;
58495: int flgn = ((uae_s8)(newv)) < 0;
58496: SET_ZFLG (((uae_s8)(newv)) == 0);
58497: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58498: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58499: COPY_CARRY;
58500: SET_NFLG (flgn != 0);
58501: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58502: }}}}}}}m68k_incpc(4);
58503: fill_prefetch_0 ();
58504: return 12;
58505: }
58506: unsigned long REGPARAM2 CPUFUNC(op_9039_5)(uae_u32 opcode) /* SUB */
58507: {
58508: uae_u32 dstreg = (opcode >> 9) & 7;
58509: OpcodeFamily = 7; CurrentInstrCycles = 16;
58510: {{ uaecptr srca = get_ilong_prefetch(2);
58511: { uae_s8 src = get_byte(srca);
58512: { uae_s8 dst = m68k_dreg(regs, dstreg);
58513: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58514: { int flgs = ((uae_s8)(src)) < 0;
58515: int flgo = ((uae_s8)(dst)) < 0;
58516: int flgn = ((uae_s8)(newv)) < 0;
58517: SET_ZFLG (((uae_s8)(newv)) == 0);
58518: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58519: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58520: COPY_CARRY;
58521: SET_NFLG (flgn != 0);
58522: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58523: }}}}}}}m68k_incpc(6);
58524: fill_prefetch_0 ();
58525: return 16;
58526: }
58527: unsigned long REGPARAM2 CPUFUNC(op_903a_5)(uae_u32 opcode) /* SUB */
58528: {
58529: uae_u32 dstreg = (opcode >> 9) & 7;
58530: OpcodeFamily = 7; CurrentInstrCycles = 12;
58531: {{ uaecptr srca = m68k_getpc () + 2;
58532: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
58533: { uae_s8 src = get_byte(srca);
58534: { uae_s8 dst = m68k_dreg(regs, dstreg);
58535: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58536: { int flgs = ((uae_s8)(src)) < 0;
58537: int flgo = ((uae_s8)(dst)) < 0;
58538: int flgn = ((uae_s8)(newv)) < 0;
58539: SET_ZFLG (((uae_s8)(newv)) == 0);
58540: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58541: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58542: COPY_CARRY;
58543: SET_NFLG (flgn != 0);
58544: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58545: }}}}}}}m68k_incpc(4);
58546: fill_prefetch_0 ();
58547: return 12;
58548: }
58549: unsigned long REGPARAM2 CPUFUNC(op_903b_5)(uae_u32 opcode) /* SUB */
58550: {
58551: uae_u32 dstreg = (opcode >> 9) & 7;
58552: OpcodeFamily = 7; CurrentInstrCycles = 14;
58553: {{ uaecptr tmppc = m68k_getpc() + 2;
58554: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
58555: BusCyclePenalty += 2;
58556: { uae_s8 src = get_byte(srca);
58557: { uae_s8 dst = m68k_dreg(regs, dstreg);
58558: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58559: { int flgs = ((uae_s8)(src)) < 0;
58560: int flgo = ((uae_s8)(dst)) < 0;
58561: int flgn = ((uae_s8)(newv)) < 0;
58562: SET_ZFLG (((uae_s8)(newv)) == 0);
58563: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58564: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58565: COPY_CARRY;
58566: SET_NFLG (flgn != 0);
58567: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58568: }}}}}}}m68k_incpc(4);
58569: fill_prefetch_0 ();
58570: return 14;
58571: }
58572: unsigned long REGPARAM2 CPUFUNC(op_903c_5)(uae_u32 opcode) /* SUB */
58573: {
58574: uae_u32 dstreg = (opcode >> 9) & 7;
58575: OpcodeFamily = 7; CurrentInstrCycles = 8;
58576: {{ uae_s8 src = get_ibyte_prefetch(2);
58577: { uae_s8 dst = m68k_dreg(regs, dstreg);
58578: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
58579: { int flgs = ((uae_s8)(src)) < 0;
58580: int flgo = ((uae_s8)(dst)) < 0;
58581: int flgn = ((uae_s8)(newv)) < 0;
58582: SET_ZFLG (((uae_s8)(newv)) == 0);
58583: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58584: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
58585: COPY_CARRY;
58586: SET_NFLG (flgn != 0);
58587: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
58588: }}}}}}m68k_incpc(4);
58589: fill_prefetch_0 ();
58590: return 8;
58591: }
58592: unsigned long REGPARAM2 CPUFUNC(op_9040_5)(uae_u32 opcode) /* SUB */
58593: {
58594: uae_u32 srcreg = (opcode & 7);
58595: uae_u32 dstreg = (opcode >> 9) & 7;
58596: OpcodeFamily = 7; CurrentInstrCycles = 4;
58597: {{ uae_s16 src = m68k_dreg(regs, srcreg);
58598: { uae_s16 dst = m68k_dreg(regs, dstreg);
58599: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58600: { int flgs = ((uae_s16)(src)) < 0;
58601: int flgo = ((uae_s16)(dst)) < 0;
58602: int flgn = ((uae_s16)(newv)) < 0;
58603: SET_ZFLG (((uae_s16)(newv)) == 0);
58604: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58605: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58606: COPY_CARRY;
58607: SET_NFLG (flgn != 0);
58608: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58609: }}}}}}m68k_incpc(2);
58610: fill_prefetch_2 ();
58611: return 4;
58612: }
58613: unsigned long REGPARAM2 CPUFUNC(op_9048_5)(uae_u32 opcode) /* SUB */
58614: {
58615: uae_u32 srcreg = (opcode & 7);
58616: uae_u32 dstreg = (opcode >> 9) & 7;
58617: OpcodeFamily = 7; CurrentInstrCycles = 4;
58618: {{ uae_s16 src = m68k_areg(regs, srcreg);
58619: { uae_s16 dst = m68k_dreg(regs, dstreg);
58620: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58621: { int flgs = ((uae_s16)(src)) < 0;
58622: int flgo = ((uae_s16)(dst)) < 0;
58623: int flgn = ((uae_s16)(newv)) < 0;
58624: SET_ZFLG (((uae_s16)(newv)) == 0);
58625: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58626: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58627: COPY_CARRY;
58628: SET_NFLG (flgn != 0);
58629: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58630: }}}}}}m68k_incpc(2);
58631: fill_prefetch_2 ();
58632: return 4;
58633: }
58634: unsigned long REGPARAM2 CPUFUNC(op_9050_5)(uae_u32 opcode) /* SUB */
58635: {
58636: uae_u32 srcreg = (opcode & 7);
58637: uae_u32 dstreg = (opcode >> 9) & 7;
58638: OpcodeFamily = 7; CurrentInstrCycles = 8;
58639: {{ uaecptr srca = m68k_areg(regs, srcreg);
58640: if ((srca & 1) != 0) {
58641: last_fault_for_exception_3 = srca;
58642: last_op_for_exception_3 = opcode;
58643: last_addr_for_exception_3 = m68k_getpc() + 2;
58644: Exception(3, 0, M68000_EXC_SRC_CPU);
58645: goto endlabel3305;
58646: }
58647: {{ uae_s16 src = get_word(srca);
58648: { uae_s16 dst = m68k_dreg(regs, dstreg);
58649: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58650: { int flgs = ((uae_s16)(src)) < 0;
58651: int flgo = ((uae_s16)(dst)) < 0;
58652: int flgn = ((uae_s16)(newv)) < 0;
58653: SET_ZFLG (((uae_s16)(newv)) == 0);
58654: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58655: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58656: COPY_CARRY;
58657: SET_NFLG (flgn != 0);
58658: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58659: }}}}}}}}m68k_incpc(2);
58660: fill_prefetch_2 ();
58661: endlabel3305: ;
58662: return 8;
58663: }
58664: unsigned long REGPARAM2 CPUFUNC(op_9058_5)(uae_u32 opcode) /* SUB */
58665: {
58666: uae_u32 srcreg = (opcode & 7);
58667: uae_u32 dstreg = (opcode >> 9) & 7;
58668: OpcodeFamily = 7; CurrentInstrCycles = 8;
58669: {{ uaecptr srca = m68k_areg(regs, srcreg);
58670: if ((srca & 1) != 0) {
58671: last_fault_for_exception_3 = srca;
58672: last_op_for_exception_3 = opcode;
58673: last_addr_for_exception_3 = m68k_getpc() + 2;
58674: Exception(3, 0, M68000_EXC_SRC_CPU);
58675: goto endlabel3306;
58676: }
58677: {{ uae_s16 src = get_word(srca);
58678: m68k_areg(regs, srcreg) += 2;
58679: { uae_s16 dst = m68k_dreg(regs, dstreg);
58680: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58681: { int flgs = ((uae_s16)(src)) < 0;
58682: int flgo = ((uae_s16)(dst)) < 0;
58683: int flgn = ((uae_s16)(newv)) < 0;
58684: SET_ZFLG (((uae_s16)(newv)) == 0);
58685: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58686: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58687: COPY_CARRY;
58688: SET_NFLG (flgn != 0);
58689: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58690: }}}}}}}}m68k_incpc(2);
58691: fill_prefetch_2 ();
58692: endlabel3306: ;
58693: return 8;
58694: }
58695: unsigned long REGPARAM2 CPUFUNC(op_9060_5)(uae_u32 opcode) /* SUB */
58696: {
58697: uae_u32 srcreg = (opcode & 7);
58698: uae_u32 dstreg = (opcode >> 9) & 7;
58699: OpcodeFamily = 7; CurrentInstrCycles = 10;
58700: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
58701: if ((srca & 1) != 0) {
58702: last_fault_for_exception_3 = srca;
58703: last_op_for_exception_3 = opcode;
58704: last_addr_for_exception_3 = m68k_getpc() + 2;
58705: Exception(3, 0, M68000_EXC_SRC_CPU);
58706: goto endlabel3307;
58707: }
58708: {{ uae_s16 src = get_word(srca);
58709: m68k_areg (regs, srcreg) = srca;
58710: { uae_s16 dst = m68k_dreg(regs, dstreg);
58711: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58712: { int flgs = ((uae_s16)(src)) < 0;
58713: int flgo = ((uae_s16)(dst)) < 0;
58714: int flgn = ((uae_s16)(newv)) < 0;
58715: SET_ZFLG (((uae_s16)(newv)) == 0);
58716: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58717: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58718: COPY_CARRY;
58719: SET_NFLG (flgn != 0);
58720: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58721: }}}}}}}}m68k_incpc(2);
58722: fill_prefetch_2 ();
58723: endlabel3307: ;
58724: return 10;
58725: }
58726: unsigned long REGPARAM2 CPUFUNC(op_9068_5)(uae_u32 opcode) /* SUB */
58727: {
58728: uae_u32 srcreg = (opcode & 7);
58729: uae_u32 dstreg = (opcode >> 9) & 7;
58730: OpcodeFamily = 7; CurrentInstrCycles = 12;
58731: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
58732: if ((srca & 1) != 0) {
58733: last_fault_for_exception_3 = srca;
58734: last_op_for_exception_3 = opcode;
58735: last_addr_for_exception_3 = m68k_getpc() + 4;
58736: Exception(3, 0, M68000_EXC_SRC_CPU);
58737: goto endlabel3308;
58738: }
58739: {{ uae_s16 src = get_word(srca);
58740: { uae_s16 dst = m68k_dreg(regs, dstreg);
58741: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58742: { int flgs = ((uae_s16)(src)) < 0;
58743: int flgo = ((uae_s16)(dst)) < 0;
58744: int flgn = ((uae_s16)(newv)) < 0;
58745: SET_ZFLG (((uae_s16)(newv)) == 0);
58746: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58747: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58748: COPY_CARRY;
58749: SET_NFLG (flgn != 0);
58750: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58751: }}}}}}}}m68k_incpc(4);
58752: fill_prefetch_0 ();
58753: endlabel3308: ;
58754: return 12;
58755: }
58756: unsigned long REGPARAM2 CPUFUNC(op_9070_5)(uae_u32 opcode) /* SUB */
58757: {
58758: uae_u32 srcreg = (opcode & 7);
58759: uae_u32 dstreg = (opcode >> 9) & 7;
58760: OpcodeFamily = 7; CurrentInstrCycles = 14;
58761: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
58762: BusCyclePenalty += 2;
58763: if ((srca & 1) != 0) {
58764: last_fault_for_exception_3 = srca;
58765: last_op_for_exception_3 = opcode;
58766: last_addr_for_exception_3 = m68k_getpc() + 4;
58767: Exception(3, 0, M68000_EXC_SRC_CPU);
58768: goto endlabel3309;
58769: }
58770: {{ uae_s16 src = get_word(srca);
58771: { uae_s16 dst = m68k_dreg(regs, dstreg);
58772: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58773: { int flgs = ((uae_s16)(src)) < 0;
58774: int flgo = ((uae_s16)(dst)) < 0;
58775: int flgn = ((uae_s16)(newv)) < 0;
58776: SET_ZFLG (((uae_s16)(newv)) == 0);
58777: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58778: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58779: COPY_CARRY;
58780: SET_NFLG (flgn != 0);
58781: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58782: }}}}}}}}m68k_incpc(4);
58783: fill_prefetch_0 ();
58784: endlabel3309: ;
58785: return 14;
58786: }
58787: unsigned long REGPARAM2 CPUFUNC(op_9078_5)(uae_u32 opcode) /* SUB */
58788: {
58789: uae_u32 dstreg = (opcode >> 9) & 7;
58790: OpcodeFamily = 7; CurrentInstrCycles = 12;
58791: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
58792: if ((srca & 1) != 0) {
58793: last_fault_for_exception_3 = srca;
58794: last_op_for_exception_3 = opcode;
58795: last_addr_for_exception_3 = m68k_getpc() + 4;
58796: Exception(3, 0, M68000_EXC_SRC_CPU);
58797: goto endlabel3310;
58798: }
58799: {{ uae_s16 src = get_word(srca);
58800: { uae_s16 dst = m68k_dreg(regs, dstreg);
58801: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58802: { int flgs = ((uae_s16)(src)) < 0;
58803: int flgo = ((uae_s16)(dst)) < 0;
58804: int flgn = ((uae_s16)(newv)) < 0;
58805: SET_ZFLG (((uae_s16)(newv)) == 0);
58806: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58807: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58808: COPY_CARRY;
58809: SET_NFLG (flgn != 0);
58810: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58811: }}}}}}}}m68k_incpc(4);
58812: fill_prefetch_0 ();
58813: endlabel3310: ;
58814: return 12;
58815: }
58816: unsigned long REGPARAM2 CPUFUNC(op_9079_5)(uae_u32 opcode) /* SUB */
58817: {
58818: uae_u32 dstreg = (opcode >> 9) & 7;
58819: OpcodeFamily = 7; CurrentInstrCycles = 16;
58820: {{ uaecptr srca = get_ilong_prefetch(2);
58821: if ((srca & 1) != 0) {
58822: last_fault_for_exception_3 = srca;
58823: last_op_for_exception_3 = opcode;
58824: last_addr_for_exception_3 = m68k_getpc() + 6;
58825: Exception(3, 0, M68000_EXC_SRC_CPU);
58826: goto endlabel3311;
58827: }
58828: {{ uae_s16 src = get_word(srca);
58829: { uae_s16 dst = m68k_dreg(regs, dstreg);
58830: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58831: { int flgs = ((uae_s16)(src)) < 0;
58832: int flgo = ((uae_s16)(dst)) < 0;
58833: int flgn = ((uae_s16)(newv)) < 0;
58834: SET_ZFLG (((uae_s16)(newv)) == 0);
58835: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58836: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58837: COPY_CARRY;
58838: SET_NFLG (flgn != 0);
58839: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58840: }}}}}}}}m68k_incpc(6);
58841: fill_prefetch_0 ();
58842: endlabel3311: ;
58843: return 16;
58844: }
58845: unsigned long REGPARAM2 CPUFUNC(op_907a_5)(uae_u32 opcode) /* SUB */
58846: {
58847: uae_u32 dstreg = (opcode >> 9) & 7;
58848: OpcodeFamily = 7; CurrentInstrCycles = 12;
58849: {{ uaecptr srca = m68k_getpc () + 2;
58850: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
58851: if ((srca & 1) != 0) {
58852: last_fault_for_exception_3 = srca;
58853: last_op_for_exception_3 = opcode;
58854: last_addr_for_exception_3 = m68k_getpc() + 4;
58855: Exception(3, 0, M68000_EXC_SRC_CPU);
58856: goto endlabel3312;
58857: }
58858: {{ uae_s16 src = get_word(srca);
58859: { uae_s16 dst = m68k_dreg(regs, dstreg);
58860: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58861: { int flgs = ((uae_s16)(src)) < 0;
58862: int flgo = ((uae_s16)(dst)) < 0;
58863: int flgn = ((uae_s16)(newv)) < 0;
58864: SET_ZFLG (((uae_s16)(newv)) == 0);
58865: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58866: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58867: COPY_CARRY;
58868: SET_NFLG (flgn != 0);
58869: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58870: }}}}}}}}m68k_incpc(4);
58871: fill_prefetch_0 ();
58872: endlabel3312: ;
58873: return 12;
58874: }
58875: unsigned long REGPARAM2 CPUFUNC(op_907b_5)(uae_u32 opcode) /* SUB */
58876: {
58877: uae_u32 dstreg = (opcode >> 9) & 7;
58878: OpcodeFamily = 7; CurrentInstrCycles = 14;
58879: {{ uaecptr tmppc = m68k_getpc() + 2;
58880: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
58881: BusCyclePenalty += 2;
58882: if ((srca & 1) != 0) {
58883: last_fault_for_exception_3 = srca;
58884: last_op_for_exception_3 = opcode;
58885: last_addr_for_exception_3 = m68k_getpc() + 4;
58886: Exception(3, 0, M68000_EXC_SRC_CPU);
58887: goto endlabel3313;
58888: }
58889: {{ uae_s16 src = get_word(srca);
58890: { uae_s16 dst = m68k_dreg(regs, dstreg);
58891: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58892: { int flgs = ((uae_s16)(src)) < 0;
58893: int flgo = ((uae_s16)(dst)) < 0;
58894: int flgn = ((uae_s16)(newv)) < 0;
58895: SET_ZFLG (((uae_s16)(newv)) == 0);
58896: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58897: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58898: COPY_CARRY;
58899: SET_NFLG (flgn != 0);
58900: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58901: }}}}}}}}m68k_incpc(4);
58902: fill_prefetch_0 ();
58903: endlabel3313: ;
58904: return 14;
58905: }
58906: unsigned long REGPARAM2 CPUFUNC(op_907c_5)(uae_u32 opcode) /* SUB */
58907: {
58908: uae_u32 dstreg = (opcode >> 9) & 7;
58909: OpcodeFamily = 7; CurrentInstrCycles = 8;
58910: {{ uae_s16 src = get_iword_prefetch(2);
58911: { uae_s16 dst = m68k_dreg(regs, dstreg);
58912: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
58913: { int flgs = ((uae_s16)(src)) < 0;
58914: int flgo = ((uae_s16)(dst)) < 0;
58915: int flgn = ((uae_s16)(newv)) < 0;
58916: SET_ZFLG (((uae_s16)(newv)) == 0);
58917: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58918: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
58919: COPY_CARRY;
58920: SET_NFLG (flgn != 0);
58921: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
58922: }}}}}}m68k_incpc(4);
58923: fill_prefetch_0 ();
58924: return 8;
58925: }
58926: unsigned long REGPARAM2 CPUFUNC(op_9080_5)(uae_u32 opcode) /* SUB */
58927: {
58928: uae_u32 srcreg = (opcode & 7);
58929: uae_u32 dstreg = (opcode >> 9) & 7;
58930: OpcodeFamily = 7; CurrentInstrCycles = 8;
58931: {{ uae_s32 src = m68k_dreg(regs, srcreg);
58932: { uae_s32 dst = m68k_dreg(regs, dstreg);
58933: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
58934: { int flgs = ((uae_s32)(src)) < 0;
58935: int flgo = ((uae_s32)(dst)) < 0;
58936: int flgn = ((uae_s32)(newv)) < 0;
58937: SET_ZFLG (((uae_s32)(newv)) == 0);
58938: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58939: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
58940: COPY_CARRY;
58941: SET_NFLG (flgn != 0);
58942: m68k_dreg(regs, dstreg) = (newv);
58943: }}}}}}m68k_incpc(2);
58944: fill_prefetch_2 ();
58945: return 8;
58946: }
58947: unsigned long REGPARAM2 CPUFUNC(op_9088_5)(uae_u32 opcode) /* SUB */
58948: {
58949: uae_u32 srcreg = (opcode & 7);
58950: uae_u32 dstreg = (opcode >> 9) & 7;
58951: OpcodeFamily = 7; CurrentInstrCycles = 8;
58952: {{ uae_s32 src = m68k_areg(regs, srcreg);
58953: { uae_s32 dst = m68k_dreg(regs, dstreg);
58954: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
58955: { int flgs = ((uae_s32)(src)) < 0;
58956: int flgo = ((uae_s32)(dst)) < 0;
58957: int flgn = ((uae_s32)(newv)) < 0;
58958: SET_ZFLG (((uae_s32)(newv)) == 0);
58959: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58960: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
58961: COPY_CARRY;
58962: SET_NFLG (flgn != 0);
58963: m68k_dreg(regs, dstreg) = (newv);
58964: }}}}}}m68k_incpc(2);
58965: fill_prefetch_2 ();
58966: return 8;
58967: }
58968: unsigned long REGPARAM2 CPUFUNC(op_9090_5)(uae_u32 opcode) /* SUB */
58969: {
58970: uae_u32 srcreg = (opcode & 7);
58971: uae_u32 dstreg = (opcode >> 9) & 7;
58972: OpcodeFamily = 7; CurrentInstrCycles = 14;
58973: {{ uaecptr srca = m68k_areg(regs, srcreg);
58974: if ((srca & 1) != 0) {
58975: last_fault_for_exception_3 = srca;
58976: last_op_for_exception_3 = opcode;
58977: last_addr_for_exception_3 = m68k_getpc() + 2;
58978: Exception(3, 0, M68000_EXC_SRC_CPU);
58979: goto endlabel3317;
58980: }
58981: {{ uae_s32 src = get_long(srca);
58982: { uae_s32 dst = m68k_dreg(regs, dstreg);
58983: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
58984: { int flgs = ((uae_s32)(src)) < 0;
58985: int flgo = ((uae_s32)(dst)) < 0;
58986: int flgn = ((uae_s32)(newv)) < 0;
58987: SET_ZFLG (((uae_s32)(newv)) == 0);
58988: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
58989: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
58990: COPY_CARRY;
58991: SET_NFLG (flgn != 0);
58992: m68k_dreg(regs, dstreg) = (newv);
58993: }}}}}}}}m68k_incpc(2);
58994: fill_prefetch_2 ();
58995: endlabel3317: ;
58996: return 14;
58997: }
58998: unsigned long REGPARAM2 CPUFUNC(op_9098_5)(uae_u32 opcode) /* SUB */
58999: {
59000: uae_u32 srcreg = (opcode & 7);
59001: uae_u32 dstreg = (opcode >> 9) & 7;
59002: OpcodeFamily = 7; CurrentInstrCycles = 14;
59003: {{ uaecptr srca = m68k_areg(regs, srcreg);
59004: if ((srca & 1) != 0) {
59005: last_fault_for_exception_3 = srca;
59006: last_op_for_exception_3 = opcode;
59007: last_addr_for_exception_3 = m68k_getpc() + 2;
59008: Exception(3, 0, M68000_EXC_SRC_CPU);
59009: goto endlabel3318;
59010: }
59011: {{ uae_s32 src = get_long(srca);
59012: m68k_areg(regs, srcreg) += 4;
59013: { uae_s32 dst = m68k_dreg(regs, dstreg);
59014: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
59015: { int flgs = ((uae_s32)(src)) < 0;
59016: int flgo = ((uae_s32)(dst)) < 0;
59017: int flgn = ((uae_s32)(newv)) < 0;
59018: SET_ZFLG (((uae_s32)(newv)) == 0);
59019: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59020: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
59021: COPY_CARRY;
59022: SET_NFLG (flgn != 0);
59023: m68k_dreg(regs, dstreg) = (newv);
59024: }}}}}}}}m68k_incpc(2);
59025: fill_prefetch_2 ();
59026: endlabel3318: ;
59027: return 14;
59028: }
59029: unsigned long REGPARAM2 CPUFUNC(op_90a0_5)(uae_u32 opcode) /* SUB */
59030: {
59031: uae_u32 srcreg = (opcode & 7);
59032: uae_u32 dstreg = (opcode >> 9) & 7;
59033: OpcodeFamily = 7; CurrentInstrCycles = 16;
59034: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
59035: if ((srca & 1) != 0) {
59036: last_fault_for_exception_3 = srca;
59037: last_op_for_exception_3 = opcode;
59038: last_addr_for_exception_3 = m68k_getpc() + 2;
59039: Exception(3, 0, M68000_EXC_SRC_CPU);
59040: goto endlabel3319;
59041: }
59042: {{ uae_s32 src = get_long(srca);
59043: m68k_areg (regs, srcreg) = srca;
59044: { uae_s32 dst = m68k_dreg(regs, dstreg);
59045: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
59046: { int flgs = ((uae_s32)(src)) < 0;
59047: int flgo = ((uae_s32)(dst)) < 0;
59048: int flgn = ((uae_s32)(newv)) < 0;
59049: SET_ZFLG (((uae_s32)(newv)) == 0);
59050: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59051: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
59052: COPY_CARRY;
59053: SET_NFLG (flgn != 0);
59054: m68k_dreg(regs, dstreg) = (newv);
59055: }}}}}}}}m68k_incpc(2);
59056: fill_prefetch_2 ();
59057: endlabel3319: ;
59058: return 16;
59059: }
59060: unsigned long REGPARAM2 CPUFUNC(op_90a8_5)(uae_u32 opcode) /* SUB */
59061: {
59062: uae_u32 srcreg = (opcode & 7);
59063: uae_u32 dstreg = (opcode >> 9) & 7;
59064: OpcodeFamily = 7; CurrentInstrCycles = 18;
59065: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
59066: if ((srca & 1) != 0) {
59067: last_fault_for_exception_3 = srca;
59068: last_op_for_exception_3 = opcode;
59069: last_addr_for_exception_3 = m68k_getpc() + 4;
59070: Exception(3, 0, M68000_EXC_SRC_CPU);
59071: goto endlabel3320;
59072: }
59073: {{ uae_s32 src = get_long(srca);
59074: { uae_s32 dst = m68k_dreg(regs, dstreg);
59075: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
59076: { int flgs = ((uae_s32)(src)) < 0;
59077: int flgo = ((uae_s32)(dst)) < 0;
59078: int flgn = ((uae_s32)(newv)) < 0;
59079: SET_ZFLG (((uae_s32)(newv)) == 0);
59080: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59081: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
59082: COPY_CARRY;
59083: SET_NFLG (flgn != 0);
59084: m68k_dreg(regs, dstreg) = (newv);
59085: }}}}}}}}m68k_incpc(4);
59086: fill_prefetch_0 ();
59087: endlabel3320: ;
59088: return 18;
59089: }
59090: unsigned long REGPARAM2 CPUFUNC(op_90b0_5)(uae_u32 opcode) /* SUB */
59091: {
59092: uae_u32 srcreg = (opcode & 7);
59093: uae_u32 dstreg = (opcode >> 9) & 7;
59094: OpcodeFamily = 7; CurrentInstrCycles = 20;
59095: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
59096: BusCyclePenalty += 2;
59097: if ((srca & 1) != 0) {
59098: last_fault_for_exception_3 = srca;
59099: last_op_for_exception_3 = opcode;
59100: last_addr_for_exception_3 = m68k_getpc() + 4;
59101: Exception(3, 0, M68000_EXC_SRC_CPU);
59102: goto endlabel3321;
59103: }
59104: {{ uae_s32 src = get_long(srca);
59105: { uae_s32 dst = m68k_dreg(regs, dstreg);
59106: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
59107: { int flgs = ((uae_s32)(src)) < 0;
59108: int flgo = ((uae_s32)(dst)) < 0;
59109: int flgn = ((uae_s32)(newv)) < 0;
59110: SET_ZFLG (((uae_s32)(newv)) == 0);
59111: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59112: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
59113: COPY_CARRY;
59114: SET_NFLG (flgn != 0);
59115: m68k_dreg(regs, dstreg) = (newv);
59116: }}}}}}}}m68k_incpc(4);
59117: fill_prefetch_0 ();
59118: endlabel3321: ;
59119: return 20;
59120: }
59121: unsigned long REGPARAM2 CPUFUNC(op_90b8_5)(uae_u32 opcode) /* SUB */
59122: {
59123: uae_u32 dstreg = (opcode >> 9) & 7;
59124: OpcodeFamily = 7; CurrentInstrCycles = 18;
59125: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
59126: if ((srca & 1) != 0) {
59127: last_fault_for_exception_3 = srca;
59128: last_op_for_exception_3 = opcode;
59129: last_addr_for_exception_3 = m68k_getpc() + 4;
59130: Exception(3, 0, M68000_EXC_SRC_CPU);
59131: goto endlabel3322;
59132: }
59133: {{ uae_s32 src = get_long(srca);
59134: { uae_s32 dst = m68k_dreg(regs, dstreg);
59135: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
59136: { int flgs = ((uae_s32)(src)) < 0;
59137: int flgo = ((uae_s32)(dst)) < 0;
59138: int flgn = ((uae_s32)(newv)) < 0;
59139: SET_ZFLG (((uae_s32)(newv)) == 0);
59140: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59141: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
59142: COPY_CARRY;
59143: SET_NFLG (flgn != 0);
59144: m68k_dreg(regs, dstreg) = (newv);
59145: }}}}}}}}m68k_incpc(4);
59146: fill_prefetch_0 ();
59147: endlabel3322: ;
59148: return 18;
59149: }
59150: unsigned long REGPARAM2 CPUFUNC(op_90b9_5)(uae_u32 opcode) /* SUB */
59151: {
59152: uae_u32 dstreg = (opcode >> 9) & 7;
59153: OpcodeFamily = 7; CurrentInstrCycles = 22;
59154: {{ uaecptr srca = get_ilong_prefetch(2);
59155: if ((srca & 1) != 0) {
59156: last_fault_for_exception_3 = srca;
59157: last_op_for_exception_3 = opcode;
59158: last_addr_for_exception_3 = m68k_getpc() + 6;
59159: Exception(3, 0, M68000_EXC_SRC_CPU);
59160: goto endlabel3323;
59161: }
59162: {{ uae_s32 src = get_long(srca);
59163: { uae_s32 dst = m68k_dreg(regs, dstreg);
59164: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
59165: { int flgs = ((uae_s32)(src)) < 0;
59166: int flgo = ((uae_s32)(dst)) < 0;
59167: int flgn = ((uae_s32)(newv)) < 0;
59168: SET_ZFLG (((uae_s32)(newv)) == 0);
59169: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59170: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
59171: COPY_CARRY;
59172: SET_NFLG (flgn != 0);
59173: m68k_dreg(regs, dstreg) = (newv);
59174: }}}}}}}}m68k_incpc(6);
59175: fill_prefetch_0 ();
59176: endlabel3323: ;
59177: return 22;
59178: }
59179: unsigned long REGPARAM2 CPUFUNC(op_90ba_5)(uae_u32 opcode) /* SUB */
59180: {
59181: uae_u32 dstreg = (opcode >> 9) & 7;
59182: OpcodeFamily = 7; CurrentInstrCycles = 18;
59183: {{ uaecptr srca = m68k_getpc () + 2;
59184: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
59185: if ((srca & 1) != 0) {
59186: last_fault_for_exception_3 = srca;
59187: last_op_for_exception_3 = opcode;
59188: last_addr_for_exception_3 = m68k_getpc() + 4;
59189: Exception(3, 0, M68000_EXC_SRC_CPU);
59190: goto endlabel3324;
59191: }
59192: {{ uae_s32 src = get_long(srca);
59193: { uae_s32 dst = m68k_dreg(regs, dstreg);
59194: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
59195: { int flgs = ((uae_s32)(src)) < 0;
59196: int flgo = ((uae_s32)(dst)) < 0;
59197: int flgn = ((uae_s32)(newv)) < 0;
59198: SET_ZFLG (((uae_s32)(newv)) == 0);
59199: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59200: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
59201: COPY_CARRY;
59202: SET_NFLG (flgn != 0);
59203: m68k_dreg(regs, dstreg) = (newv);
59204: }}}}}}}}m68k_incpc(4);
59205: fill_prefetch_0 ();
59206: endlabel3324: ;
59207: return 18;
59208: }
59209: unsigned long REGPARAM2 CPUFUNC(op_90bb_5)(uae_u32 opcode) /* SUB */
59210: {
59211: uae_u32 dstreg = (opcode >> 9) & 7;
59212: OpcodeFamily = 7; CurrentInstrCycles = 20;
59213: {{ uaecptr tmppc = m68k_getpc() + 2;
59214: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
59215: BusCyclePenalty += 2;
59216: if ((srca & 1) != 0) {
59217: last_fault_for_exception_3 = srca;
59218: last_op_for_exception_3 = opcode;
59219: last_addr_for_exception_3 = m68k_getpc() + 4;
59220: Exception(3, 0, M68000_EXC_SRC_CPU);
59221: goto endlabel3325;
59222: }
59223: {{ uae_s32 src = get_long(srca);
59224: { uae_s32 dst = m68k_dreg(regs, dstreg);
59225: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
59226: { int flgs = ((uae_s32)(src)) < 0;
59227: int flgo = ((uae_s32)(dst)) < 0;
59228: int flgn = ((uae_s32)(newv)) < 0;
59229: SET_ZFLG (((uae_s32)(newv)) == 0);
59230: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59231: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
59232: COPY_CARRY;
59233: SET_NFLG (flgn != 0);
59234: m68k_dreg(regs, dstreg) = (newv);
59235: }}}}}}}}m68k_incpc(4);
59236: fill_prefetch_0 ();
59237: endlabel3325: ;
59238: return 20;
59239: }
59240: unsigned long REGPARAM2 CPUFUNC(op_90bc_5)(uae_u32 opcode) /* SUB */
59241: {
59242: uae_u32 dstreg = (opcode >> 9) & 7;
59243: OpcodeFamily = 7; CurrentInstrCycles = 16;
59244: {{ uae_s32 src = get_ilong_prefetch(2);
59245: { uae_s32 dst = m68k_dreg(regs, dstreg);
59246: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
59247: { int flgs = ((uae_s32)(src)) < 0;
59248: int flgo = ((uae_s32)(dst)) < 0;
59249: int flgn = ((uae_s32)(newv)) < 0;
59250: SET_ZFLG (((uae_s32)(newv)) == 0);
59251: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59252: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
59253: COPY_CARRY;
59254: SET_NFLG (flgn != 0);
59255: m68k_dreg(regs, dstreg) = (newv);
59256: }}}}}}m68k_incpc(6);
59257: fill_prefetch_0 ();
59258: return 16;
59259: }
59260: unsigned long REGPARAM2 CPUFUNC(op_90c0_5)(uae_u32 opcode) /* SUBA */
59261: {
59262: uae_u32 srcreg = (opcode & 7);
59263: uae_u32 dstreg = (opcode >> 9) & 7;
59264: OpcodeFamily = 8; CurrentInstrCycles = 8;
59265: {{ uae_s16 src = m68k_dreg(regs, srcreg);
59266: { uae_s32 dst = m68k_areg(regs, dstreg);
59267: { uae_u32 newv = dst - src;
59268: m68k_areg(regs, dstreg) = (newv);
59269: }}}}m68k_incpc(2);
59270: fill_prefetch_2 ();
59271: return 8;
59272: }
59273: unsigned long REGPARAM2 CPUFUNC(op_90c8_5)(uae_u32 opcode) /* SUBA */
59274: {
59275: uae_u32 srcreg = (opcode & 7);
59276: uae_u32 dstreg = (opcode >> 9) & 7;
59277: OpcodeFamily = 8; CurrentInstrCycles = 8;
59278: {{ uae_s16 src = m68k_areg(regs, srcreg);
59279: { uae_s32 dst = m68k_areg(regs, dstreg);
59280: { uae_u32 newv = dst - src;
59281: m68k_areg(regs, dstreg) = (newv);
59282: }}}}m68k_incpc(2);
59283: fill_prefetch_2 ();
59284: return 8;
59285: }
59286: unsigned long REGPARAM2 CPUFUNC(op_90d0_5)(uae_u32 opcode) /* SUBA */
59287: {
59288: uae_u32 srcreg = (opcode & 7);
59289: uae_u32 dstreg = (opcode >> 9) & 7;
59290: OpcodeFamily = 8; CurrentInstrCycles = 12;
59291: {{ uaecptr srca = m68k_areg(regs, srcreg);
59292: if ((srca & 1) != 0) {
59293: last_fault_for_exception_3 = srca;
59294: last_op_for_exception_3 = opcode;
59295: last_addr_for_exception_3 = m68k_getpc() + 2;
59296: Exception(3, 0, M68000_EXC_SRC_CPU);
59297: goto endlabel3329;
59298: }
59299: {{ uae_s16 src = get_word(srca);
59300: { uae_s32 dst = m68k_areg(regs, dstreg);
59301: { uae_u32 newv = dst - src;
59302: m68k_areg(regs, dstreg) = (newv);
59303: }}}}}}m68k_incpc(2);
59304: fill_prefetch_2 ();
59305: endlabel3329: ;
59306: return 12;
59307: }
59308: unsigned long REGPARAM2 CPUFUNC(op_90d8_5)(uae_u32 opcode) /* SUBA */
59309: {
59310: uae_u32 srcreg = (opcode & 7);
59311: uae_u32 dstreg = (opcode >> 9) & 7;
59312: OpcodeFamily = 8; CurrentInstrCycles = 12;
59313: {{ uaecptr srca = m68k_areg(regs, srcreg);
59314: if ((srca & 1) != 0) {
59315: last_fault_for_exception_3 = srca;
59316: last_op_for_exception_3 = opcode;
59317: last_addr_for_exception_3 = m68k_getpc() + 2;
59318: Exception(3, 0, M68000_EXC_SRC_CPU);
59319: goto endlabel3330;
59320: }
59321: {{ uae_s16 src = get_word(srca);
59322: m68k_areg(regs, srcreg) += 2;
59323: { uae_s32 dst = m68k_areg(regs, dstreg);
59324: { uae_u32 newv = dst - src;
59325: m68k_areg(regs, dstreg) = (newv);
59326: }}}}}}m68k_incpc(2);
59327: fill_prefetch_2 ();
59328: endlabel3330: ;
59329: return 12;
59330: }
59331: unsigned long REGPARAM2 CPUFUNC(op_90e0_5)(uae_u32 opcode) /* SUBA */
59332: {
59333: uae_u32 srcreg = (opcode & 7);
59334: uae_u32 dstreg = (opcode >> 9) & 7;
59335: OpcodeFamily = 8; CurrentInstrCycles = 14;
59336: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
59337: if ((srca & 1) != 0) {
59338: last_fault_for_exception_3 = srca;
59339: last_op_for_exception_3 = opcode;
59340: last_addr_for_exception_3 = m68k_getpc() + 2;
59341: Exception(3, 0, M68000_EXC_SRC_CPU);
59342: goto endlabel3331;
59343: }
59344: {{ uae_s16 src = get_word(srca);
59345: m68k_areg (regs, srcreg) = srca;
59346: { uae_s32 dst = m68k_areg(regs, dstreg);
59347: { uae_u32 newv = dst - src;
59348: m68k_areg(regs, dstreg) = (newv);
59349: }}}}}}m68k_incpc(2);
59350: fill_prefetch_2 ();
59351: endlabel3331: ;
59352: return 14;
59353: }
59354: unsigned long REGPARAM2 CPUFUNC(op_90e8_5)(uae_u32 opcode) /* SUBA */
59355: {
59356: uae_u32 srcreg = (opcode & 7);
59357: uae_u32 dstreg = (opcode >> 9) & 7;
59358: OpcodeFamily = 8; CurrentInstrCycles = 16;
59359: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
59360: if ((srca & 1) != 0) {
59361: last_fault_for_exception_3 = srca;
59362: last_op_for_exception_3 = opcode;
59363: last_addr_for_exception_3 = m68k_getpc() + 4;
59364: Exception(3, 0, M68000_EXC_SRC_CPU);
59365: goto endlabel3332;
59366: }
59367: {{ uae_s16 src = get_word(srca);
59368: { uae_s32 dst = m68k_areg(regs, dstreg);
59369: { uae_u32 newv = dst - src;
59370: m68k_areg(regs, dstreg) = (newv);
59371: }}}}}}m68k_incpc(4);
59372: fill_prefetch_0 ();
59373: endlabel3332: ;
59374: return 16;
59375: }
59376: unsigned long REGPARAM2 CPUFUNC(op_90f0_5)(uae_u32 opcode) /* SUBA */
59377: {
59378: uae_u32 srcreg = (opcode & 7);
59379: uae_u32 dstreg = (opcode >> 9) & 7;
59380: OpcodeFamily = 8; CurrentInstrCycles = 18;
59381: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
59382: BusCyclePenalty += 2;
59383: if ((srca & 1) != 0) {
59384: last_fault_for_exception_3 = srca;
59385: last_op_for_exception_3 = opcode;
59386: last_addr_for_exception_3 = m68k_getpc() + 4;
59387: Exception(3, 0, M68000_EXC_SRC_CPU);
59388: goto endlabel3333;
59389: }
59390: {{ uae_s16 src = get_word(srca);
59391: { uae_s32 dst = m68k_areg(regs, dstreg);
59392: { uae_u32 newv = dst - src;
59393: m68k_areg(regs, dstreg) = (newv);
59394: }}}}}}m68k_incpc(4);
59395: fill_prefetch_0 ();
59396: endlabel3333: ;
59397: return 18;
59398: }
59399: unsigned long REGPARAM2 CPUFUNC(op_90f8_5)(uae_u32 opcode) /* SUBA */
59400: {
59401: uae_u32 dstreg = (opcode >> 9) & 7;
59402: OpcodeFamily = 8; CurrentInstrCycles = 16;
59403: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
59404: if ((srca & 1) != 0) {
59405: last_fault_for_exception_3 = srca;
59406: last_op_for_exception_3 = opcode;
59407: last_addr_for_exception_3 = m68k_getpc() + 4;
59408: Exception(3, 0, M68000_EXC_SRC_CPU);
59409: goto endlabel3334;
59410: }
59411: {{ uae_s16 src = get_word(srca);
59412: { uae_s32 dst = m68k_areg(regs, dstreg);
59413: { uae_u32 newv = dst - src;
59414: m68k_areg(regs, dstreg) = (newv);
59415: }}}}}}m68k_incpc(4);
59416: fill_prefetch_0 ();
59417: endlabel3334: ;
59418: return 16;
59419: }
59420: unsigned long REGPARAM2 CPUFUNC(op_90f9_5)(uae_u32 opcode) /* SUBA */
59421: {
59422: uae_u32 dstreg = (opcode >> 9) & 7;
59423: OpcodeFamily = 8; CurrentInstrCycles = 20;
59424: {{ uaecptr srca = get_ilong_prefetch(2);
59425: if ((srca & 1) != 0) {
59426: last_fault_for_exception_3 = srca;
59427: last_op_for_exception_3 = opcode;
59428: last_addr_for_exception_3 = m68k_getpc() + 6;
59429: Exception(3, 0, M68000_EXC_SRC_CPU);
59430: goto endlabel3335;
59431: }
59432: {{ uae_s16 src = get_word(srca);
59433: { uae_s32 dst = m68k_areg(regs, dstreg);
59434: { uae_u32 newv = dst - src;
59435: m68k_areg(regs, dstreg) = (newv);
59436: }}}}}}m68k_incpc(6);
59437: fill_prefetch_0 ();
59438: endlabel3335: ;
59439: return 20;
59440: }
59441: unsigned long REGPARAM2 CPUFUNC(op_90fa_5)(uae_u32 opcode) /* SUBA */
59442: {
59443: uae_u32 dstreg = (opcode >> 9) & 7;
59444: OpcodeFamily = 8; CurrentInstrCycles = 16;
59445: {{ uaecptr srca = m68k_getpc () + 2;
59446: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
59447: if ((srca & 1) != 0) {
59448: last_fault_for_exception_3 = srca;
59449: last_op_for_exception_3 = opcode;
59450: last_addr_for_exception_3 = m68k_getpc() + 4;
59451: Exception(3, 0, M68000_EXC_SRC_CPU);
59452: goto endlabel3336;
59453: }
59454: {{ uae_s16 src = get_word(srca);
59455: { uae_s32 dst = m68k_areg(regs, dstreg);
59456: { uae_u32 newv = dst - src;
59457: m68k_areg(regs, dstreg) = (newv);
59458: }}}}}}m68k_incpc(4);
59459: fill_prefetch_0 ();
59460: endlabel3336: ;
59461: return 16;
59462: }
59463: unsigned long REGPARAM2 CPUFUNC(op_90fb_5)(uae_u32 opcode) /* SUBA */
59464: {
59465: uae_u32 dstreg = (opcode >> 9) & 7;
59466: OpcodeFamily = 8; CurrentInstrCycles = 18;
59467: {{ uaecptr tmppc = m68k_getpc() + 2;
59468: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
59469: BusCyclePenalty += 2;
59470: if ((srca & 1) != 0) {
59471: last_fault_for_exception_3 = srca;
59472: last_op_for_exception_3 = opcode;
59473: last_addr_for_exception_3 = m68k_getpc() + 4;
59474: Exception(3, 0, M68000_EXC_SRC_CPU);
59475: goto endlabel3337;
59476: }
59477: {{ uae_s16 src = get_word(srca);
59478: { uae_s32 dst = m68k_areg(regs, dstreg);
59479: { uae_u32 newv = dst - src;
59480: m68k_areg(regs, dstreg) = (newv);
59481: }}}}}}m68k_incpc(4);
59482: fill_prefetch_0 ();
59483: endlabel3337: ;
59484: return 18;
59485: }
59486: unsigned long REGPARAM2 CPUFUNC(op_90fc_5)(uae_u32 opcode) /* SUBA */
59487: {
59488: uae_u32 dstreg = (opcode >> 9) & 7;
59489: OpcodeFamily = 8; CurrentInstrCycles = 12;
59490: {{ uae_s16 src = get_iword_prefetch(2);
59491: { uae_s32 dst = m68k_areg(regs, dstreg);
59492: { uae_u32 newv = dst - src;
59493: m68k_areg(regs, dstreg) = (newv);
59494: }}}}m68k_incpc(4);
59495: fill_prefetch_0 ();
59496: return 12;
59497: }
59498: unsigned long REGPARAM2 CPUFUNC(op_9100_5)(uae_u32 opcode) /* SUBX */
59499: {
59500: uae_u32 srcreg = (opcode & 7);
59501: uae_u32 dstreg = (opcode >> 9) & 7;
59502: OpcodeFamily = 9; CurrentInstrCycles = 4;
59503: {{ uae_s8 src = m68k_dreg(regs, srcreg);
59504: { uae_s8 dst = m68k_dreg(regs, dstreg);
59505: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
59506: { int flgs = ((uae_s8)(src)) < 0;
59507: int flgo = ((uae_s8)(dst)) < 0;
59508: int flgn = ((uae_s8)(newv)) < 0;
59509: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
59510: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
59511: COPY_CARRY;
59512: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
59513: SET_NFLG (((uae_s8)(newv)) < 0);
59514: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
59515: }}}}}m68k_incpc(2);
59516: fill_prefetch_2 ();
59517: return 4;
59518: }
59519: unsigned long REGPARAM2 CPUFUNC(op_9108_5)(uae_u32 opcode) /* SUBX */
59520: {
59521: uae_u32 srcreg = (opcode & 7);
59522: uae_u32 dstreg = (opcode >> 9) & 7;
59523: OpcodeFamily = 9; CurrentInstrCycles = 18;
59524: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
59525: { uae_s8 src = get_byte(srca);
59526: m68k_areg (regs, srcreg) = srca;
59527: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
59528: { uae_s8 dst = get_byte(dsta);
59529: m68k_areg (regs, dstreg) = dsta;
59530: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
59531: { int flgs = ((uae_s8)(src)) < 0;
59532: int flgo = ((uae_s8)(dst)) < 0;
59533: int flgn = ((uae_s8)(newv)) < 0;
59534: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
59535: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
59536: COPY_CARRY;
59537: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
59538: SET_NFLG (((uae_s8)(newv)) < 0);
59539: m68k_incpc(2);
59540: fill_prefetch_2 ();
59541: put_byte(dsta,newv);
59542: }}}}}}}return 18;
59543: }
59544: unsigned long REGPARAM2 CPUFUNC(op_9110_5)(uae_u32 opcode) /* SUB */
59545: {
59546: uae_u32 srcreg = ((opcode >> 9) & 7);
59547: uae_u32 dstreg = opcode & 7;
59548: OpcodeFamily = 7; CurrentInstrCycles = 12;
59549: {{ uae_s8 src = m68k_dreg(regs, srcreg);
59550: { uaecptr dsta = m68k_areg(regs, dstreg);
59551: { uae_s8 dst = get_byte(dsta);
59552: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
59553: { int flgs = ((uae_s8)(src)) < 0;
59554: int flgo = ((uae_s8)(dst)) < 0;
59555: int flgn = ((uae_s8)(newv)) < 0;
59556: SET_ZFLG (((uae_s8)(newv)) == 0);
59557: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59558: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
59559: COPY_CARRY;
59560: SET_NFLG (flgn != 0);
59561: m68k_incpc(2);
59562: fill_prefetch_2 ();
59563: put_byte(dsta,newv);
59564: }}}}}}}return 12;
59565: }
59566: unsigned long REGPARAM2 CPUFUNC(op_9118_5)(uae_u32 opcode) /* SUB */
59567: {
59568: uae_u32 srcreg = ((opcode >> 9) & 7);
59569: uae_u32 dstreg = opcode & 7;
59570: OpcodeFamily = 7; CurrentInstrCycles = 12;
59571: {{ uae_s8 src = m68k_dreg(regs, srcreg);
59572: { uaecptr dsta = m68k_areg(regs, dstreg);
59573: { uae_s8 dst = get_byte(dsta);
59574: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
59575: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
59576: { int flgs = ((uae_s8)(src)) < 0;
59577: int flgo = ((uae_s8)(dst)) < 0;
59578: int flgn = ((uae_s8)(newv)) < 0;
59579: SET_ZFLG (((uae_s8)(newv)) == 0);
59580: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59581: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
59582: COPY_CARRY;
59583: SET_NFLG (flgn != 0);
59584: m68k_incpc(2);
59585: fill_prefetch_2 ();
59586: put_byte(dsta,newv);
59587: }}}}}}}return 12;
59588: }
59589: unsigned long REGPARAM2 CPUFUNC(op_9120_5)(uae_u32 opcode) /* SUB */
59590: {
59591: uae_u32 srcreg = ((opcode >> 9) & 7);
59592: uae_u32 dstreg = opcode & 7;
59593: OpcodeFamily = 7; CurrentInstrCycles = 14;
59594: {{ uae_s8 src = m68k_dreg(regs, srcreg);
59595: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
59596: { uae_s8 dst = get_byte(dsta);
59597: m68k_areg (regs, dstreg) = dsta;
59598: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
59599: { int flgs = ((uae_s8)(src)) < 0;
59600: int flgo = ((uae_s8)(dst)) < 0;
59601: int flgn = ((uae_s8)(newv)) < 0;
59602: SET_ZFLG (((uae_s8)(newv)) == 0);
59603: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59604: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
59605: COPY_CARRY;
59606: SET_NFLG (flgn != 0);
59607: m68k_incpc(2);
59608: fill_prefetch_2 ();
59609: put_byte(dsta,newv);
59610: }}}}}}}return 14;
59611: }
59612: unsigned long REGPARAM2 CPUFUNC(op_9128_5)(uae_u32 opcode) /* SUB */
59613: {
59614: uae_u32 srcreg = ((opcode >> 9) & 7);
59615: uae_u32 dstreg = opcode & 7;
59616: OpcodeFamily = 7; CurrentInstrCycles = 16;
59617: {{ uae_s8 src = m68k_dreg(regs, srcreg);
59618: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
59619: { uae_s8 dst = get_byte(dsta);
59620: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
59621: { int flgs = ((uae_s8)(src)) < 0;
59622: int flgo = ((uae_s8)(dst)) < 0;
59623: int flgn = ((uae_s8)(newv)) < 0;
59624: SET_ZFLG (((uae_s8)(newv)) == 0);
59625: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59626: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
59627: COPY_CARRY;
59628: SET_NFLG (flgn != 0);
59629: m68k_incpc(4);
59630: fill_prefetch_0 ();
59631: put_byte(dsta,newv);
59632: }}}}}}}return 16;
59633: }
59634: unsigned long REGPARAM2 CPUFUNC(op_9130_5)(uae_u32 opcode) /* SUB */
59635: {
59636: uae_u32 srcreg = ((opcode >> 9) & 7);
59637: uae_u32 dstreg = opcode & 7;
59638: OpcodeFamily = 7; CurrentInstrCycles = 18;
59639: {{ uae_s8 src = m68k_dreg(regs, srcreg);
59640: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
59641: BusCyclePenalty += 2;
59642: { uae_s8 dst = get_byte(dsta);
59643: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
59644: { int flgs = ((uae_s8)(src)) < 0;
59645: int flgo = ((uae_s8)(dst)) < 0;
59646: int flgn = ((uae_s8)(newv)) < 0;
59647: SET_ZFLG (((uae_s8)(newv)) == 0);
59648: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59649: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
59650: COPY_CARRY;
59651: SET_NFLG (flgn != 0);
59652: m68k_incpc(4);
59653: fill_prefetch_0 ();
59654: put_byte(dsta,newv);
59655: }}}}}}}return 18;
59656: }
59657: unsigned long REGPARAM2 CPUFUNC(op_9138_5)(uae_u32 opcode) /* SUB */
59658: {
59659: uae_u32 srcreg = ((opcode >> 9) & 7);
59660: OpcodeFamily = 7; CurrentInstrCycles = 16;
59661: {{ uae_s8 src = m68k_dreg(regs, srcreg);
59662: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
59663: { uae_s8 dst = get_byte(dsta);
59664: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
59665: { int flgs = ((uae_s8)(src)) < 0;
59666: int flgo = ((uae_s8)(dst)) < 0;
59667: int flgn = ((uae_s8)(newv)) < 0;
59668: SET_ZFLG (((uae_s8)(newv)) == 0);
59669: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59670: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
59671: COPY_CARRY;
59672: SET_NFLG (flgn != 0);
59673: m68k_incpc(4);
59674: fill_prefetch_0 ();
59675: put_byte(dsta,newv);
59676: }}}}}}}return 16;
59677: }
59678: unsigned long REGPARAM2 CPUFUNC(op_9139_5)(uae_u32 opcode) /* SUB */
59679: {
59680: uae_u32 srcreg = ((opcode >> 9) & 7);
59681: OpcodeFamily = 7; CurrentInstrCycles = 20;
59682: {{ uae_s8 src = m68k_dreg(regs, srcreg);
59683: { uaecptr dsta = get_ilong_prefetch(2);
59684: { uae_s8 dst = get_byte(dsta);
59685: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
59686: { int flgs = ((uae_s8)(src)) < 0;
59687: int flgo = ((uae_s8)(dst)) < 0;
59688: int flgn = ((uae_s8)(newv)) < 0;
59689: SET_ZFLG (((uae_s8)(newv)) == 0);
59690: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59691: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
59692: COPY_CARRY;
59693: SET_NFLG (flgn != 0);
59694: m68k_incpc(6);
59695: fill_prefetch_0 ();
59696: put_byte(dsta,newv);
59697: }}}}}}}return 20;
59698: }
59699: unsigned long REGPARAM2 CPUFUNC(op_9140_5)(uae_u32 opcode) /* SUBX */
59700: {
59701: uae_u32 srcreg = (opcode & 7);
59702: uae_u32 dstreg = (opcode >> 9) & 7;
59703: OpcodeFamily = 9; CurrentInstrCycles = 4;
59704: {{ uae_s16 src = m68k_dreg(regs, srcreg);
59705: { uae_s16 dst = m68k_dreg(regs, dstreg);
59706: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
59707: { int flgs = ((uae_s16)(src)) < 0;
59708: int flgo = ((uae_s16)(dst)) < 0;
59709: int flgn = ((uae_s16)(newv)) < 0;
59710: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
59711: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
59712: COPY_CARRY;
59713: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
59714: SET_NFLG (((uae_s16)(newv)) < 0);
59715: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
59716: }}}}}m68k_incpc(2);
59717: fill_prefetch_2 ();
59718: return 4;
59719: }
59720: unsigned long REGPARAM2 CPUFUNC(op_9148_5)(uae_u32 opcode) /* SUBX */
59721: {
59722: uae_u32 srcreg = (opcode & 7);
59723: uae_u32 dstreg = (opcode >> 9) & 7;
59724: OpcodeFamily = 9; CurrentInstrCycles = 18;
59725: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
59726: if ((srca & 1) != 0) {
59727: last_fault_for_exception_3 = srca;
59728: last_op_for_exception_3 = opcode;
59729: last_addr_for_exception_3 = m68k_getpc() + 2;
59730: Exception(3, 0, M68000_EXC_SRC_CPU);
59731: goto endlabel3349;
59732: }
59733: {{ uae_s16 src = get_word(srca);
59734: m68k_areg (regs, srcreg) = srca;
59735: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
59736: if ((dsta & 1) != 0) {
59737: last_fault_for_exception_3 = dsta;
59738: last_op_for_exception_3 = opcode;
59739: last_addr_for_exception_3 = m68k_getpc() + 2;
59740: Exception(3, 0, M68000_EXC_SRC_CPU);
59741: goto endlabel3349;
59742: }
59743: {{ uae_s16 dst = get_word(dsta);
59744: m68k_areg (regs, dstreg) = dsta;
59745: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
59746: { int flgs = ((uae_s16)(src)) < 0;
59747: int flgo = ((uae_s16)(dst)) < 0;
59748: int flgn = ((uae_s16)(newv)) < 0;
59749: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
59750: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
59751: COPY_CARRY;
59752: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
59753: SET_NFLG (((uae_s16)(newv)) < 0);
59754: m68k_incpc(2);
59755: fill_prefetch_2 ();
59756: put_word(dsta,newv);
59757: }}}}}}}}}endlabel3349: ;
59758: return 18;
59759: }
59760: unsigned long REGPARAM2 CPUFUNC(op_9150_5)(uae_u32 opcode) /* SUB */
59761: {
59762: uae_u32 srcreg = ((opcode >> 9) & 7);
59763: uae_u32 dstreg = opcode & 7;
59764: OpcodeFamily = 7; CurrentInstrCycles = 12;
59765: {{ uae_s16 src = m68k_dreg(regs, srcreg);
59766: { uaecptr dsta = m68k_areg(regs, dstreg);
59767: if ((dsta & 1) != 0) {
59768: last_fault_for_exception_3 = dsta;
59769: last_op_for_exception_3 = opcode;
59770: last_addr_for_exception_3 = m68k_getpc() + 2;
59771: Exception(3, 0, M68000_EXC_SRC_CPU);
59772: goto endlabel3350;
59773: }
59774: {{ uae_s16 dst = get_word(dsta);
59775: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
59776: { int flgs = ((uae_s16)(src)) < 0;
59777: int flgo = ((uae_s16)(dst)) < 0;
59778: int flgn = ((uae_s16)(newv)) < 0;
59779: SET_ZFLG (((uae_s16)(newv)) == 0);
59780: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59781: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
59782: COPY_CARRY;
59783: SET_NFLG (flgn != 0);
59784: m68k_incpc(2);
59785: fill_prefetch_2 ();
59786: put_word(dsta,newv);
59787: }}}}}}}}endlabel3350: ;
59788: return 12;
59789: }
59790: unsigned long REGPARAM2 CPUFUNC(op_9158_5)(uae_u32 opcode) /* SUB */
59791: {
59792: uae_u32 srcreg = ((opcode >> 9) & 7);
59793: uae_u32 dstreg = opcode & 7;
59794: OpcodeFamily = 7; CurrentInstrCycles = 12;
59795: {{ uae_s16 src = m68k_dreg(regs, srcreg);
59796: { uaecptr dsta = m68k_areg(regs, dstreg);
59797: if ((dsta & 1) != 0) {
59798: last_fault_for_exception_3 = dsta;
59799: last_op_for_exception_3 = opcode;
59800: last_addr_for_exception_3 = m68k_getpc() + 2;
59801: Exception(3, 0, M68000_EXC_SRC_CPU);
59802: goto endlabel3351;
59803: }
59804: {{ uae_s16 dst = get_word(dsta);
59805: m68k_areg(regs, dstreg) += 2;
59806: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
59807: { int flgs = ((uae_s16)(src)) < 0;
59808: int flgo = ((uae_s16)(dst)) < 0;
59809: int flgn = ((uae_s16)(newv)) < 0;
59810: SET_ZFLG (((uae_s16)(newv)) == 0);
59811: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59812: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
59813: COPY_CARRY;
59814: SET_NFLG (flgn != 0);
59815: m68k_incpc(2);
59816: fill_prefetch_2 ();
59817: put_word(dsta,newv);
59818: }}}}}}}}endlabel3351: ;
59819: return 12;
59820: }
59821: unsigned long REGPARAM2 CPUFUNC(op_9160_5)(uae_u32 opcode) /* SUB */
59822: {
59823: uae_u32 srcreg = ((opcode >> 9) & 7);
59824: uae_u32 dstreg = opcode & 7;
59825: OpcodeFamily = 7; CurrentInstrCycles = 14;
59826: {{ uae_s16 src = m68k_dreg(regs, srcreg);
59827: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
59828: if ((dsta & 1) != 0) {
59829: last_fault_for_exception_3 = dsta;
59830: last_op_for_exception_3 = opcode;
59831: last_addr_for_exception_3 = m68k_getpc() + 2;
59832: Exception(3, 0, M68000_EXC_SRC_CPU);
59833: goto endlabel3352;
59834: }
59835: {{ uae_s16 dst = get_word(dsta);
59836: m68k_areg (regs, dstreg) = dsta;
59837: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
59838: { int flgs = ((uae_s16)(src)) < 0;
59839: int flgo = ((uae_s16)(dst)) < 0;
59840: int flgn = ((uae_s16)(newv)) < 0;
59841: SET_ZFLG (((uae_s16)(newv)) == 0);
59842: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59843: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
59844: COPY_CARRY;
59845: SET_NFLG (flgn != 0);
59846: m68k_incpc(2);
59847: fill_prefetch_2 ();
59848: put_word(dsta,newv);
59849: }}}}}}}}endlabel3352: ;
59850: return 14;
59851: }
59852: unsigned long REGPARAM2 CPUFUNC(op_9168_5)(uae_u32 opcode) /* SUB */
59853: {
59854: uae_u32 srcreg = ((opcode >> 9) & 7);
59855: uae_u32 dstreg = opcode & 7;
59856: OpcodeFamily = 7; CurrentInstrCycles = 16;
59857: {{ uae_s16 src = m68k_dreg(regs, srcreg);
59858: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
59859: if ((dsta & 1) != 0) {
59860: last_fault_for_exception_3 = dsta;
59861: last_op_for_exception_3 = opcode;
59862: last_addr_for_exception_3 = m68k_getpc() + 4;
59863: Exception(3, 0, M68000_EXC_SRC_CPU);
59864: goto endlabel3353;
59865: }
59866: {{ uae_s16 dst = get_word(dsta);
59867: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
59868: { int flgs = ((uae_s16)(src)) < 0;
59869: int flgo = ((uae_s16)(dst)) < 0;
59870: int flgn = ((uae_s16)(newv)) < 0;
59871: SET_ZFLG (((uae_s16)(newv)) == 0);
59872: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59873: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
59874: COPY_CARRY;
59875: SET_NFLG (flgn != 0);
59876: m68k_incpc(4);
59877: fill_prefetch_0 ();
59878: put_word(dsta,newv);
59879: }}}}}}}}endlabel3353: ;
59880: return 16;
59881: }
59882: unsigned long REGPARAM2 CPUFUNC(op_9170_5)(uae_u32 opcode) /* SUB */
59883: {
59884: uae_u32 srcreg = ((opcode >> 9) & 7);
59885: uae_u32 dstreg = opcode & 7;
59886: OpcodeFamily = 7; CurrentInstrCycles = 18;
59887: {{ uae_s16 src = m68k_dreg(regs, srcreg);
59888: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
59889: BusCyclePenalty += 2;
59890: if ((dsta & 1) != 0) {
59891: last_fault_for_exception_3 = dsta;
59892: last_op_for_exception_3 = opcode;
59893: last_addr_for_exception_3 = m68k_getpc() + 4;
59894: Exception(3, 0, M68000_EXC_SRC_CPU);
59895: goto endlabel3354;
59896: }
59897: {{ uae_s16 dst = get_word(dsta);
59898: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
59899: { int flgs = ((uae_s16)(src)) < 0;
59900: int flgo = ((uae_s16)(dst)) < 0;
59901: int flgn = ((uae_s16)(newv)) < 0;
59902: SET_ZFLG (((uae_s16)(newv)) == 0);
59903: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59904: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
59905: COPY_CARRY;
59906: SET_NFLG (flgn != 0);
59907: m68k_incpc(4);
59908: fill_prefetch_0 ();
59909: put_word(dsta,newv);
59910: }}}}}}}}endlabel3354: ;
59911: return 18;
59912: }
59913: unsigned long REGPARAM2 CPUFUNC(op_9178_5)(uae_u32 opcode) /* SUB */
59914: {
59915: uae_u32 srcreg = ((opcode >> 9) & 7);
59916: OpcodeFamily = 7; CurrentInstrCycles = 16;
59917: {{ uae_s16 src = m68k_dreg(regs, srcreg);
59918: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
59919: if ((dsta & 1) != 0) {
59920: last_fault_for_exception_3 = dsta;
59921: last_op_for_exception_3 = opcode;
59922: last_addr_for_exception_3 = m68k_getpc() + 4;
59923: Exception(3, 0, M68000_EXC_SRC_CPU);
59924: goto endlabel3355;
59925: }
59926: {{ uae_s16 dst = get_word(dsta);
59927: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
59928: { int flgs = ((uae_s16)(src)) < 0;
59929: int flgo = ((uae_s16)(dst)) < 0;
59930: int flgn = ((uae_s16)(newv)) < 0;
59931: SET_ZFLG (((uae_s16)(newv)) == 0);
59932: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59933: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
59934: COPY_CARRY;
59935: SET_NFLG (flgn != 0);
59936: m68k_incpc(4);
59937: fill_prefetch_0 ();
59938: put_word(dsta,newv);
59939: }}}}}}}}endlabel3355: ;
59940: return 16;
59941: }
59942: unsigned long REGPARAM2 CPUFUNC(op_9179_5)(uae_u32 opcode) /* SUB */
59943: {
59944: uae_u32 srcreg = ((opcode >> 9) & 7);
59945: OpcodeFamily = 7; CurrentInstrCycles = 20;
59946: {{ uae_s16 src = m68k_dreg(regs, srcreg);
59947: { uaecptr dsta = get_ilong_prefetch(2);
59948: if ((dsta & 1) != 0) {
59949: last_fault_for_exception_3 = dsta;
59950: last_op_for_exception_3 = opcode;
59951: last_addr_for_exception_3 = m68k_getpc() + 6;
59952: Exception(3, 0, M68000_EXC_SRC_CPU);
59953: goto endlabel3356;
59954: }
59955: {{ uae_s16 dst = get_word(dsta);
59956: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
59957: { int flgs = ((uae_s16)(src)) < 0;
59958: int flgo = ((uae_s16)(dst)) < 0;
59959: int flgn = ((uae_s16)(newv)) < 0;
59960: SET_ZFLG (((uae_s16)(newv)) == 0);
59961: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
59962: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
59963: COPY_CARRY;
59964: SET_NFLG (flgn != 0);
59965: m68k_incpc(6);
59966: fill_prefetch_0 ();
59967: put_word(dsta,newv);
59968: }}}}}}}}endlabel3356: ;
59969: return 20;
59970: }
59971: unsigned long REGPARAM2 CPUFUNC(op_9180_5)(uae_u32 opcode) /* SUBX */
59972: {
59973: uae_u32 srcreg = (opcode & 7);
59974: uae_u32 dstreg = (opcode >> 9) & 7;
59975: OpcodeFamily = 9; CurrentInstrCycles = 8;
59976: {{ uae_s32 src = m68k_dreg(regs, srcreg);
59977: { uae_s32 dst = m68k_dreg(regs, dstreg);
59978: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
59979: { int flgs = ((uae_s32)(src)) < 0;
59980: int flgo = ((uae_s32)(dst)) < 0;
59981: int flgn = ((uae_s32)(newv)) < 0;
59982: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
59983: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
59984: COPY_CARRY;
59985: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
59986: SET_NFLG (((uae_s32)(newv)) < 0);
59987: m68k_dreg(regs, dstreg) = (newv);
59988: }}}}}m68k_incpc(2);
59989: fill_prefetch_2 ();
59990: return 8;
59991: }
59992: unsigned long REGPARAM2 CPUFUNC(op_9188_5)(uae_u32 opcode) /* SUBX */
59993: {
59994: uae_u32 srcreg = (opcode & 7);
59995: uae_u32 dstreg = (opcode >> 9) & 7;
59996: OpcodeFamily = 9; CurrentInstrCycles = 30;
59997: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
59998: if ((srca & 1) != 0) {
59999: last_fault_for_exception_3 = srca;
60000: last_op_for_exception_3 = opcode;
60001: last_addr_for_exception_3 = m68k_getpc() + 2;
60002: Exception(3, 0, M68000_EXC_SRC_CPU);
60003: goto endlabel3358;
60004: }
60005: {{ uae_s32 src = get_long(srca);
60006: m68k_areg (regs, srcreg) = srca;
60007: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
60008: if ((dsta & 1) != 0) {
60009: last_fault_for_exception_3 = dsta;
60010: last_op_for_exception_3 = opcode;
60011: last_addr_for_exception_3 = m68k_getpc() + 2;
60012: Exception(3, 0, M68000_EXC_SRC_CPU);
60013: goto endlabel3358;
60014: }
60015: {{ uae_s32 dst = get_long(dsta);
60016: m68k_areg (regs, dstreg) = dsta;
60017: { uae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);
60018: { int flgs = ((uae_s32)(src)) < 0;
60019: int flgo = ((uae_s32)(dst)) < 0;
60020: int flgn = ((uae_s32)(newv)) < 0;
60021: SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
60022: SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
60023: COPY_CARRY;
60024: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
60025: SET_NFLG (((uae_s32)(newv)) < 0);
60026: m68k_incpc(2);
60027: fill_prefetch_2 ();
60028: put_long(dsta,newv);
60029: }}}}}}}}}endlabel3358: ;
60030: return 30;
60031: }
60032: unsigned long REGPARAM2 CPUFUNC(op_9190_5)(uae_u32 opcode) /* SUB */
60033: {
60034: uae_u32 srcreg = ((opcode >> 9) & 7);
60035: uae_u32 dstreg = opcode & 7;
60036: OpcodeFamily = 7; CurrentInstrCycles = 20;
60037: {{ uae_s32 src = m68k_dreg(regs, srcreg);
60038: { uaecptr dsta = m68k_areg(regs, dstreg);
60039: if ((dsta & 1) != 0) {
60040: last_fault_for_exception_3 = dsta;
60041: last_op_for_exception_3 = opcode;
60042: last_addr_for_exception_3 = m68k_getpc() + 2;
60043: Exception(3, 0, M68000_EXC_SRC_CPU);
60044: goto endlabel3359;
60045: }
60046: {{ uae_s32 dst = get_long(dsta);
60047: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
60048: { int flgs = ((uae_s32)(src)) < 0;
60049: int flgo = ((uae_s32)(dst)) < 0;
60050: int flgn = ((uae_s32)(newv)) < 0;
60051: SET_ZFLG (((uae_s32)(newv)) == 0);
60052: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
60053: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
60054: COPY_CARRY;
60055: SET_NFLG (flgn != 0);
60056: m68k_incpc(2);
60057: fill_prefetch_2 ();
60058: put_long(dsta,newv);
60059: }}}}}}}}endlabel3359: ;
60060: return 20;
60061: }
60062: unsigned long REGPARAM2 CPUFUNC(op_9198_5)(uae_u32 opcode) /* SUB */
60063: {
60064: uae_u32 srcreg = ((opcode >> 9) & 7);
60065: uae_u32 dstreg = opcode & 7;
60066: OpcodeFamily = 7; CurrentInstrCycles = 20;
60067: {{ uae_s32 src = m68k_dreg(regs, srcreg);
60068: { uaecptr dsta = m68k_areg(regs, dstreg);
60069: if ((dsta & 1) != 0) {
60070: last_fault_for_exception_3 = dsta;
60071: last_op_for_exception_3 = opcode;
60072: last_addr_for_exception_3 = m68k_getpc() + 2;
60073: Exception(3, 0, M68000_EXC_SRC_CPU);
60074: goto endlabel3360;
60075: }
60076: {{ uae_s32 dst = get_long(dsta);
60077: m68k_areg(regs, dstreg) += 4;
60078: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
60079: { int flgs = ((uae_s32)(src)) < 0;
60080: int flgo = ((uae_s32)(dst)) < 0;
60081: int flgn = ((uae_s32)(newv)) < 0;
60082: SET_ZFLG (((uae_s32)(newv)) == 0);
60083: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
60084: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
60085: COPY_CARRY;
60086: SET_NFLG (flgn != 0);
60087: m68k_incpc(2);
60088: fill_prefetch_2 ();
60089: put_long(dsta,newv);
60090: }}}}}}}}endlabel3360: ;
60091: return 20;
60092: }
60093: unsigned long REGPARAM2 CPUFUNC(op_91a0_5)(uae_u32 opcode) /* SUB */
60094: {
60095: uae_u32 srcreg = ((opcode >> 9) & 7);
60096: uae_u32 dstreg = opcode & 7;
60097: OpcodeFamily = 7; CurrentInstrCycles = 22;
60098: {{ uae_s32 src = m68k_dreg(regs, srcreg);
60099: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
60100: if ((dsta & 1) != 0) {
60101: last_fault_for_exception_3 = dsta;
60102: last_op_for_exception_3 = opcode;
60103: last_addr_for_exception_3 = m68k_getpc() + 2;
60104: Exception(3, 0, M68000_EXC_SRC_CPU);
60105: goto endlabel3361;
60106: }
60107: {{ uae_s32 dst = get_long(dsta);
60108: m68k_areg (regs, dstreg) = dsta;
60109: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
60110: { int flgs = ((uae_s32)(src)) < 0;
60111: int flgo = ((uae_s32)(dst)) < 0;
60112: int flgn = ((uae_s32)(newv)) < 0;
60113: SET_ZFLG (((uae_s32)(newv)) == 0);
60114: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
60115: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
60116: COPY_CARRY;
60117: SET_NFLG (flgn != 0);
60118: m68k_incpc(2);
60119: fill_prefetch_2 ();
60120: put_long(dsta,newv);
60121: }}}}}}}}endlabel3361: ;
60122: return 22;
60123: }
60124: unsigned long REGPARAM2 CPUFUNC(op_91a8_5)(uae_u32 opcode) /* SUB */
60125: {
60126: uae_u32 srcreg = ((opcode >> 9) & 7);
60127: uae_u32 dstreg = opcode & 7;
60128: OpcodeFamily = 7; CurrentInstrCycles = 24;
60129: {{ uae_s32 src = m68k_dreg(regs, srcreg);
60130: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
60131: if ((dsta & 1) != 0) {
60132: last_fault_for_exception_3 = dsta;
60133: last_op_for_exception_3 = opcode;
60134: last_addr_for_exception_3 = m68k_getpc() + 4;
60135: Exception(3, 0, M68000_EXC_SRC_CPU);
60136: goto endlabel3362;
60137: }
60138: {{ uae_s32 dst = get_long(dsta);
60139: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
60140: { int flgs = ((uae_s32)(src)) < 0;
60141: int flgo = ((uae_s32)(dst)) < 0;
60142: int flgn = ((uae_s32)(newv)) < 0;
60143: SET_ZFLG (((uae_s32)(newv)) == 0);
60144: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
60145: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
60146: COPY_CARRY;
60147: SET_NFLG (flgn != 0);
60148: m68k_incpc(4);
60149: fill_prefetch_0 ();
60150: put_long(dsta,newv);
60151: }}}}}}}}endlabel3362: ;
60152: return 24;
60153: }
60154: unsigned long REGPARAM2 CPUFUNC(op_91b0_5)(uae_u32 opcode) /* SUB */
60155: {
60156: uae_u32 srcreg = ((opcode >> 9) & 7);
60157: uae_u32 dstreg = opcode & 7;
60158: OpcodeFamily = 7; CurrentInstrCycles = 26;
60159: {{ uae_s32 src = m68k_dreg(regs, srcreg);
60160: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
60161: BusCyclePenalty += 2;
60162: if ((dsta & 1) != 0) {
60163: last_fault_for_exception_3 = dsta;
60164: last_op_for_exception_3 = opcode;
60165: last_addr_for_exception_3 = m68k_getpc() + 4;
60166: Exception(3, 0, M68000_EXC_SRC_CPU);
60167: goto endlabel3363;
60168: }
60169: {{ uae_s32 dst = get_long(dsta);
60170: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
60171: { int flgs = ((uae_s32)(src)) < 0;
60172: int flgo = ((uae_s32)(dst)) < 0;
60173: int flgn = ((uae_s32)(newv)) < 0;
60174: SET_ZFLG (((uae_s32)(newv)) == 0);
60175: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
60176: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
60177: COPY_CARRY;
60178: SET_NFLG (flgn != 0);
60179: m68k_incpc(4);
60180: fill_prefetch_0 ();
60181: put_long(dsta,newv);
60182: }}}}}}}}endlabel3363: ;
60183: return 26;
60184: }
60185: unsigned long REGPARAM2 CPUFUNC(op_91b8_5)(uae_u32 opcode) /* SUB */
60186: {
60187: uae_u32 srcreg = ((opcode >> 9) & 7);
60188: OpcodeFamily = 7; CurrentInstrCycles = 24;
60189: {{ uae_s32 src = m68k_dreg(regs, srcreg);
60190: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
60191: if ((dsta & 1) != 0) {
60192: last_fault_for_exception_3 = dsta;
60193: last_op_for_exception_3 = opcode;
60194: last_addr_for_exception_3 = m68k_getpc() + 4;
60195: Exception(3, 0, M68000_EXC_SRC_CPU);
60196: goto endlabel3364;
60197: }
60198: {{ uae_s32 dst = get_long(dsta);
60199: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
60200: { int flgs = ((uae_s32)(src)) < 0;
60201: int flgo = ((uae_s32)(dst)) < 0;
60202: int flgn = ((uae_s32)(newv)) < 0;
60203: SET_ZFLG (((uae_s32)(newv)) == 0);
60204: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
60205: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
60206: COPY_CARRY;
60207: SET_NFLG (flgn != 0);
60208: m68k_incpc(4);
60209: fill_prefetch_0 ();
60210: put_long(dsta,newv);
60211: }}}}}}}}endlabel3364: ;
60212: return 24;
60213: }
60214: unsigned long REGPARAM2 CPUFUNC(op_91b9_5)(uae_u32 opcode) /* SUB */
60215: {
60216: uae_u32 srcreg = ((opcode >> 9) & 7);
60217: OpcodeFamily = 7; CurrentInstrCycles = 28;
60218: {{ uae_s32 src = m68k_dreg(regs, srcreg);
60219: { uaecptr dsta = get_ilong_prefetch(2);
60220: if ((dsta & 1) != 0) {
60221: last_fault_for_exception_3 = dsta;
60222: last_op_for_exception_3 = opcode;
60223: last_addr_for_exception_3 = m68k_getpc() + 6;
60224: Exception(3, 0, M68000_EXC_SRC_CPU);
60225: goto endlabel3365;
60226: }
60227: {{ uae_s32 dst = get_long(dsta);
60228: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
60229: { int flgs = ((uae_s32)(src)) < 0;
60230: int flgo = ((uae_s32)(dst)) < 0;
60231: int flgn = ((uae_s32)(newv)) < 0;
60232: SET_ZFLG (((uae_s32)(newv)) == 0);
60233: SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
60234: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
60235: COPY_CARRY;
60236: SET_NFLG (flgn != 0);
60237: m68k_incpc(6);
60238: fill_prefetch_0 ();
60239: put_long(dsta,newv);
60240: }}}}}}}}endlabel3365: ;
60241: return 28;
60242: }
60243: unsigned long REGPARAM2 CPUFUNC(op_91c0_5)(uae_u32 opcode) /* SUBA */
60244: {
60245: uae_u32 srcreg = (opcode & 7);
60246: uae_u32 dstreg = (opcode >> 9) & 7;
60247: OpcodeFamily = 8; CurrentInstrCycles = 8;
60248: {{ uae_s32 src = m68k_dreg(regs, srcreg);
60249: { uae_s32 dst = m68k_areg(regs, dstreg);
60250: { uae_u32 newv = dst - src;
60251: m68k_areg(regs, dstreg) = (newv);
60252: }}}}m68k_incpc(2);
60253: fill_prefetch_2 ();
60254: return 8;
60255: }
60256: unsigned long REGPARAM2 CPUFUNC(op_91c8_5)(uae_u32 opcode) /* SUBA */
60257: {
60258: uae_u32 srcreg = (opcode & 7);
60259: uae_u32 dstreg = (opcode >> 9) & 7;
60260: OpcodeFamily = 8; CurrentInstrCycles = 8;
60261: {{ uae_s32 src = m68k_areg(regs, srcreg);
60262: { uae_s32 dst = m68k_areg(regs, dstreg);
60263: { uae_u32 newv = dst - src;
60264: m68k_areg(regs, dstreg) = (newv);
60265: }}}}m68k_incpc(2);
60266: fill_prefetch_2 ();
60267: return 8;
60268: }
60269: unsigned long REGPARAM2 CPUFUNC(op_91d0_5)(uae_u32 opcode) /* SUBA */
60270: {
60271: uae_u32 srcreg = (opcode & 7);
60272: uae_u32 dstreg = (opcode >> 9) & 7;
60273: OpcodeFamily = 8; CurrentInstrCycles = 14;
60274: {{ uaecptr srca = m68k_areg(regs, srcreg);
60275: if ((srca & 1) != 0) {
60276: last_fault_for_exception_3 = srca;
60277: last_op_for_exception_3 = opcode;
60278: last_addr_for_exception_3 = m68k_getpc() + 2;
60279: Exception(3, 0, M68000_EXC_SRC_CPU);
60280: goto endlabel3368;
60281: }
60282: {{ uae_s32 src = get_long(srca);
60283: { uae_s32 dst = m68k_areg(regs, dstreg);
60284: { uae_u32 newv = dst - src;
60285: m68k_areg(regs, dstreg) = (newv);
60286: }}}}}}m68k_incpc(2);
60287: fill_prefetch_2 ();
60288: endlabel3368: ;
60289: return 14;
60290: }
60291: unsigned long REGPARAM2 CPUFUNC(op_91d8_5)(uae_u32 opcode) /* SUBA */
60292: {
60293: uae_u32 srcreg = (opcode & 7);
60294: uae_u32 dstreg = (opcode >> 9) & 7;
60295: OpcodeFamily = 8; CurrentInstrCycles = 14;
60296: {{ uaecptr srca = m68k_areg(regs, srcreg);
60297: if ((srca & 1) != 0) {
60298: last_fault_for_exception_3 = srca;
60299: last_op_for_exception_3 = opcode;
60300: last_addr_for_exception_3 = m68k_getpc() + 2;
60301: Exception(3, 0, M68000_EXC_SRC_CPU);
60302: goto endlabel3369;
60303: }
60304: {{ uae_s32 src = get_long(srca);
60305: m68k_areg(regs, srcreg) += 4;
60306: { uae_s32 dst = m68k_areg(regs, dstreg);
60307: { uae_u32 newv = dst - src;
60308: m68k_areg(regs, dstreg) = (newv);
60309: }}}}}}m68k_incpc(2);
60310: fill_prefetch_2 ();
60311: endlabel3369: ;
60312: return 14;
60313: }
60314: unsigned long REGPARAM2 CPUFUNC(op_91e0_5)(uae_u32 opcode) /* SUBA */
60315: {
60316: uae_u32 srcreg = (opcode & 7);
60317: uae_u32 dstreg = (opcode >> 9) & 7;
60318: OpcodeFamily = 8; CurrentInstrCycles = 16;
60319: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
60320: if ((srca & 1) != 0) {
60321: last_fault_for_exception_3 = srca;
60322: last_op_for_exception_3 = opcode;
60323: last_addr_for_exception_3 = m68k_getpc() + 2;
60324: Exception(3, 0, M68000_EXC_SRC_CPU);
60325: goto endlabel3370;
60326: }
60327: {{ uae_s32 src = get_long(srca);
60328: m68k_areg (regs, srcreg) = srca;
60329: { uae_s32 dst = m68k_areg(regs, dstreg);
60330: { uae_u32 newv = dst - src;
60331: m68k_areg(regs, dstreg) = (newv);
60332: }}}}}}m68k_incpc(2);
60333: fill_prefetch_2 ();
60334: endlabel3370: ;
60335: return 16;
60336: }
60337: unsigned long REGPARAM2 CPUFUNC(op_91e8_5)(uae_u32 opcode) /* SUBA */
60338: {
60339: uae_u32 srcreg = (opcode & 7);
60340: uae_u32 dstreg = (opcode >> 9) & 7;
60341: OpcodeFamily = 8; CurrentInstrCycles = 18;
60342: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
60343: if ((srca & 1) != 0) {
60344: last_fault_for_exception_3 = srca;
60345: last_op_for_exception_3 = opcode;
60346: last_addr_for_exception_3 = m68k_getpc() + 4;
60347: Exception(3, 0, M68000_EXC_SRC_CPU);
60348: goto endlabel3371;
60349: }
60350: {{ uae_s32 src = get_long(srca);
60351: { uae_s32 dst = m68k_areg(regs, dstreg);
60352: { uae_u32 newv = dst - src;
60353: m68k_areg(regs, dstreg) = (newv);
60354: }}}}}}m68k_incpc(4);
60355: fill_prefetch_0 ();
60356: endlabel3371: ;
60357: return 18;
60358: }
60359: unsigned long REGPARAM2 CPUFUNC(op_91f0_5)(uae_u32 opcode) /* SUBA */
60360: {
60361: uae_u32 srcreg = (opcode & 7);
60362: uae_u32 dstreg = (opcode >> 9) & 7;
60363: OpcodeFamily = 8; CurrentInstrCycles = 20;
60364: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
60365: BusCyclePenalty += 2;
60366: if ((srca & 1) != 0) {
60367: last_fault_for_exception_3 = srca;
60368: last_op_for_exception_3 = opcode;
60369: last_addr_for_exception_3 = m68k_getpc() + 4;
60370: Exception(3, 0, M68000_EXC_SRC_CPU);
60371: goto endlabel3372;
60372: }
60373: {{ uae_s32 src = get_long(srca);
60374: { uae_s32 dst = m68k_areg(regs, dstreg);
60375: { uae_u32 newv = dst - src;
60376: m68k_areg(regs, dstreg) = (newv);
60377: }}}}}}m68k_incpc(4);
60378: fill_prefetch_0 ();
60379: endlabel3372: ;
60380: return 20;
60381: }
60382: unsigned long REGPARAM2 CPUFUNC(op_91f8_5)(uae_u32 opcode) /* SUBA */
60383: {
60384: uae_u32 dstreg = (opcode >> 9) & 7;
60385: OpcodeFamily = 8; CurrentInstrCycles = 18;
60386: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
60387: if ((srca & 1) != 0) {
60388: last_fault_for_exception_3 = srca;
60389: last_op_for_exception_3 = opcode;
60390: last_addr_for_exception_3 = m68k_getpc() + 4;
60391: Exception(3, 0, M68000_EXC_SRC_CPU);
60392: goto endlabel3373;
60393: }
60394: {{ uae_s32 src = get_long(srca);
60395: { uae_s32 dst = m68k_areg(regs, dstreg);
60396: { uae_u32 newv = dst - src;
60397: m68k_areg(regs, dstreg) = (newv);
60398: }}}}}}m68k_incpc(4);
60399: fill_prefetch_0 ();
60400: endlabel3373: ;
60401: return 18;
60402: }
60403: unsigned long REGPARAM2 CPUFUNC(op_91f9_5)(uae_u32 opcode) /* SUBA */
60404: {
60405: uae_u32 dstreg = (opcode >> 9) & 7;
60406: OpcodeFamily = 8; CurrentInstrCycles = 22;
60407: {{ uaecptr srca = get_ilong_prefetch(2);
60408: if ((srca & 1) != 0) {
60409: last_fault_for_exception_3 = srca;
60410: last_op_for_exception_3 = opcode;
60411: last_addr_for_exception_3 = m68k_getpc() + 6;
60412: Exception(3, 0, M68000_EXC_SRC_CPU);
60413: goto endlabel3374;
60414: }
60415: {{ uae_s32 src = get_long(srca);
60416: { uae_s32 dst = m68k_areg(regs, dstreg);
60417: { uae_u32 newv = dst - src;
60418: m68k_areg(regs, dstreg) = (newv);
60419: }}}}}}m68k_incpc(6);
60420: fill_prefetch_0 ();
60421: endlabel3374: ;
60422: return 22;
60423: }
60424: unsigned long REGPARAM2 CPUFUNC(op_91fa_5)(uae_u32 opcode) /* SUBA */
60425: {
60426: uae_u32 dstreg = (opcode >> 9) & 7;
60427: OpcodeFamily = 8; CurrentInstrCycles = 18;
60428: {{ uaecptr srca = m68k_getpc () + 2;
60429: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
60430: if ((srca & 1) != 0) {
60431: last_fault_for_exception_3 = srca;
60432: last_op_for_exception_3 = opcode;
60433: last_addr_for_exception_3 = m68k_getpc() + 4;
60434: Exception(3, 0, M68000_EXC_SRC_CPU);
60435: goto endlabel3375;
60436: }
60437: {{ uae_s32 src = get_long(srca);
60438: { uae_s32 dst = m68k_areg(regs, dstreg);
60439: { uae_u32 newv = dst - src;
60440: m68k_areg(regs, dstreg) = (newv);
60441: }}}}}}m68k_incpc(4);
60442: fill_prefetch_0 ();
60443: endlabel3375: ;
60444: return 18;
60445: }
60446: unsigned long REGPARAM2 CPUFUNC(op_91fb_5)(uae_u32 opcode) /* SUBA */
60447: {
60448: uae_u32 dstreg = (opcode >> 9) & 7;
60449: OpcodeFamily = 8; CurrentInstrCycles = 20;
60450: {{ uaecptr tmppc = m68k_getpc() + 2;
60451: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
60452: BusCyclePenalty += 2;
60453: if ((srca & 1) != 0) {
60454: last_fault_for_exception_3 = srca;
60455: last_op_for_exception_3 = opcode;
60456: last_addr_for_exception_3 = m68k_getpc() + 4;
60457: Exception(3, 0, M68000_EXC_SRC_CPU);
60458: goto endlabel3376;
60459: }
60460: {{ uae_s32 src = get_long(srca);
60461: { uae_s32 dst = m68k_areg(regs, dstreg);
60462: { uae_u32 newv = dst - src;
60463: m68k_areg(regs, dstreg) = (newv);
60464: }}}}}}m68k_incpc(4);
60465: fill_prefetch_0 ();
60466: endlabel3376: ;
60467: return 20;
60468: }
60469: unsigned long REGPARAM2 CPUFUNC(op_91fc_5)(uae_u32 opcode) /* SUBA */
60470: {
60471: uae_u32 dstreg = (opcode >> 9) & 7;
60472: OpcodeFamily = 8; CurrentInstrCycles = 16;
60473: {{ uae_s32 src = get_ilong_prefetch(2);
60474: { uae_s32 dst = m68k_areg(regs, dstreg);
60475: { uae_u32 newv = dst - src;
60476: m68k_areg(regs, dstreg) = (newv);
60477: }}}}m68k_incpc(6);
60478: fill_prefetch_0 ();
60479: return 16;
60480: }
60481: unsigned long REGPARAM2 CPUFUNC(op_b000_5)(uae_u32 opcode) /* CMP */
60482: {
60483: uae_u32 srcreg = (opcode & 7);
60484: uae_u32 dstreg = (opcode >> 9) & 7;
60485: OpcodeFamily = 25; CurrentInstrCycles = 4;
60486: {{ uae_s8 src = m68k_dreg(regs, srcreg);
60487: { uae_s8 dst = m68k_dreg(regs, dstreg);
60488: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60489: { int flgs = ((uae_s8)(src)) < 0;
60490: int flgo = ((uae_s8)(dst)) < 0;
60491: int flgn = ((uae_s8)(newv)) < 0;
60492: SET_ZFLG (((uae_s8)(newv)) == 0);
60493: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60494: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60495: SET_NFLG (flgn != 0);
60496: }}}}}}m68k_incpc(2);
60497: fill_prefetch_2 ();
60498: return 4;
60499: }
60500: unsigned long REGPARAM2 CPUFUNC(op_b010_5)(uae_u32 opcode) /* CMP */
60501: {
60502: uae_u32 srcreg = (opcode & 7);
60503: uae_u32 dstreg = (opcode >> 9) & 7;
60504: OpcodeFamily = 25; CurrentInstrCycles = 8;
60505: {{ uaecptr srca = m68k_areg(regs, srcreg);
60506: { uae_s8 src = get_byte(srca);
60507: { uae_s8 dst = m68k_dreg(regs, dstreg);
60508: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60509: { int flgs = ((uae_s8)(src)) < 0;
60510: int flgo = ((uae_s8)(dst)) < 0;
60511: int flgn = ((uae_s8)(newv)) < 0;
60512: SET_ZFLG (((uae_s8)(newv)) == 0);
60513: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60514: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60515: SET_NFLG (flgn != 0);
60516: }}}}}}}m68k_incpc(2);
60517: fill_prefetch_2 ();
60518: return 8;
60519: }
60520: unsigned long REGPARAM2 CPUFUNC(op_b018_5)(uae_u32 opcode) /* CMP */
60521: {
60522: uae_u32 srcreg = (opcode & 7);
60523: uae_u32 dstreg = (opcode >> 9) & 7;
60524: OpcodeFamily = 25; CurrentInstrCycles = 8;
60525: {{ uaecptr srca = m68k_areg(regs, srcreg);
60526: { uae_s8 src = get_byte(srca);
60527: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
60528: { uae_s8 dst = m68k_dreg(regs, dstreg);
60529: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60530: { int flgs = ((uae_s8)(src)) < 0;
60531: int flgo = ((uae_s8)(dst)) < 0;
60532: int flgn = ((uae_s8)(newv)) < 0;
60533: SET_ZFLG (((uae_s8)(newv)) == 0);
60534: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60535: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60536: SET_NFLG (flgn != 0);
60537: }}}}}}}m68k_incpc(2);
60538: fill_prefetch_2 ();
60539: return 8;
60540: }
60541: unsigned long REGPARAM2 CPUFUNC(op_b020_5)(uae_u32 opcode) /* CMP */
60542: {
60543: uae_u32 srcreg = (opcode & 7);
60544: uae_u32 dstreg = (opcode >> 9) & 7;
60545: OpcodeFamily = 25; CurrentInstrCycles = 10;
60546: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
60547: { uae_s8 src = get_byte(srca);
60548: m68k_areg (regs, srcreg) = srca;
60549: { uae_s8 dst = m68k_dreg(regs, dstreg);
60550: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60551: { int flgs = ((uae_s8)(src)) < 0;
60552: int flgo = ((uae_s8)(dst)) < 0;
60553: int flgn = ((uae_s8)(newv)) < 0;
60554: SET_ZFLG (((uae_s8)(newv)) == 0);
60555: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60556: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60557: SET_NFLG (flgn != 0);
60558: }}}}}}}m68k_incpc(2);
60559: fill_prefetch_2 ();
60560: return 10;
60561: }
60562: unsigned long REGPARAM2 CPUFUNC(op_b028_5)(uae_u32 opcode) /* CMP */
60563: {
60564: uae_u32 srcreg = (opcode & 7);
60565: uae_u32 dstreg = (opcode >> 9) & 7;
60566: OpcodeFamily = 25; CurrentInstrCycles = 12;
60567: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
60568: { uae_s8 src = get_byte(srca);
60569: { uae_s8 dst = m68k_dreg(regs, dstreg);
60570: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60571: { int flgs = ((uae_s8)(src)) < 0;
60572: int flgo = ((uae_s8)(dst)) < 0;
60573: int flgn = ((uae_s8)(newv)) < 0;
60574: SET_ZFLG (((uae_s8)(newv)) == 0);
60575: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60576: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60577: SET_NFLG (flgn != 0);
60578: }}}}}}}m68k_incpc(4);
60579: fill_prefetch_0 ();
60580: return 12;
60581: }
60582: unsigned long REGPARAM2 CPUFUNC(op_b030_5)(uae_u32 opcode) /* CMP */
60583: {
60584: uae_u32 srcreg = (opcode & 7);
60585: uae_u32 dstreg = (opcode >> 9) & 7;
60586: OpcodeFamily = 25; CurrentInstrCycles = 14;
60587: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
60588: BusCyclePenalty += 2;
60589: { uae_s8 src = get_byte(srca);
60590: { uae_s8 dst = m68k_dreg(regs, dstreg);
60591: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60592: { int flgs = ((uae_s8)(src)) < 0;
60593: int flgo = ((uae_s8)(dst)) < 0;
60594: int flgn = ((uae_s8)(newv)) < 0;
60595: SET_ZFLG (((uae_s8)(newv)) == 0);
60596: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60597: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60598: SET_NFLG (flgn != 0);
60599: }}}}}}}m68k_incpc(4);
60600: fill_prefetch_0 ();
60601: return 14;
60602: }
60603: unsigned long REGPARAM2 CPUFUNC(op_b038_5)(uae_u32 opcode) /* CMP */
60604: {
60605: uae_u32 dstreg = (opcode >> 9) & 7;
60606: OpcodeFamily = 25; CurrentInstrCycles = 12;
60607: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
60608: { uae_s8 src = get_byte(srca);
60609: { uae_s8 dst = m68k_dreg(regs, dstreg);
60610: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60611: { int flgs = ((uae_s8)(src)) < 0;
60612: int flgo = ((uae_s8)(dst)) < 0;
60613: int flgn = ((uae_s8)(newv)) < 0;
60614: SET_ZFLG (((uae_s8)(newv)) == 0);
60615: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60616: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60617: SET_NFLG (flgn != 0);
60618: }}}}}}}m68k_incpc(4);
60619: fill_prefetch_0 ();
60620: return 12;
60621: }
60622: unsigned long REGPARAM2 CPUFUNC(op_b039_5)(uae_u32 opcode) /* CMP */
60623: {
60624: uae_u32 dstreg = (opcode >> 9) & 7;
60625: OpcodeFamily = 25; CurrentInstrCycles = 16;
60626: {{ uaecptr srca = get_ilong_prefetch(2);
60627: { uae_s8 src = get_byte(srca);
60628: { uae_s8 dst = m68k_dreg(regs, dstreg);
60629: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60630: { int flgs = ((uae_s8)(src)) < 0;
60631: int flgo = ((uae_s8)(dst)) < 0;
60632: int flgn = ((uae_s8)(newv)) < 0;
60633: SET_ZFLG (((uae_s8)(newv)) == 0);
60634: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60635: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60636: SET_NFLG (flgn != 0);
60637: }}}}}}}m68k_incpc(6);
60638: fill_prefetch_0 ();
60639: return 16;
60640: }
60641: unsigned long REGPARAM2 CPUFUNC(op_b03a_5)(uae_u32 opcode) /* CMP */
60642: {
60643: uae_u32 dstreg = (opcode >> 9) & 7;
60644: OpcodeFamily = 25; CurrentInstrCycles = 12;
60645: {{ uaecptr srca = m68k_getpc () + 2;
60646: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
60647: { uae_s8 src = get_byte(srca);
60648: { uae_s8 dst = m68k_dreg(regs, dstreg);
60649: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60650: { int flgs = ((uae_s8)(src)) < 0;
60651: int flgo = ((uae_s8)(dst)) < 0;
60652: int flgn = ((uae_s8)(newv)) < 0;
60653: SET_ZFLG (((uae_s8)(newv)) == 0);
60654: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60655: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60656: SET_NFLG (flgn != 0);
60657: }}}}}}}m68k_incpc(4);
60658: fill_prefetch_0 ();
60659: return 12;
60660: }
60661: unsigned long REGPARAM2 CPUFUNC(op_b03b_5)(uae_u32 opcode) /* CMP */
60662: {
60663: uae_u32 dstreg = (opcode >> 9) & 7;
60664: OpcodeFamily = 25; CurrentInstrCycles = 14;
60665: {{ uaecptr tmppc = m68k_getpc() + 2;
60666: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
60667: BusCyclePenalty += 2;
60668: { uae_s8 src = get_byte(srca);
60669: { uae_s8 dst = m68k_dreg(regs, dstreg);
60670: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60671: { int flgs = ((uae_s8)(src)) < 0;
60672: int flgo = ((uae_s8)(dst)) < 0;
60673: int flgn = ((uae_s8)(newv)) < 0;
60674: SET_ZFLG (((uae_s8)(newv)) == 0);
60675: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60676: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60677: SET_NFLG (flgn != 0);
60678: }}}}}}}m68k_incpc(4);
60679: fill_prefetch_0 ();
60680: return 14;
60681: }
60682: #endif
60683:
60684: #ifdef PART_7
60685: unsigned long REGPARAM2 CPUFUNC(op_b03c_5)(uae_u32 opcode) /* CMP */
60686: {
60687: uae_u32 dstreg = (opcode >> 9) & 7;
60688: OpcodeFamily = 25; CurrentInstrCycles = 8;
60689: {{ uae_s8 src = get_ibyte_prefetch(2);
60690: { uae_s8 dst = m68k_dreg(regs, dstreg);
60691: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
60692: { int flgs = ((uae_s8)(src)) < 0;
60693: int flgo = ((uae_s8)(dst)) < 0;
60694: int flgn = ((uae_s8)(newv)) < 0;
60695: SET_ZFLG (((uae_s8)(newv)) == 0);
60696: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60697: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
60698: SET_NFLG (flgn != 0);
60699: }}}}}}m68k_incpc(4);
60700: fill_prefetch_0 ();
60701: return 8;
60702: }
60703: unsigned long REGPARAM2 CPUFUNC(op_b040_5)(uae_u32 opcode) /* CMP */
60704: {
60705: uae_u32 srcreg = (opcode & 7);
60706: uae_u32 dstreg = (opcode >> 9) & 7;
60707: OpcodeFamily = 25; CurrentInstrCycles = 4;
60708: {{ uae_s16 src = m68k_dreg(regs, srcreg);
60709: { uae_s16 dst = m68k_dreg(regs, dstreg);
60710: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60711: { int flgs = ((uae_s16)(src)) < 0;
60712: int flgo = ((uae_s16)(dst)) < 0;
60713: int flgn = ((uae_s16)(newv)) < 0;
60714: SET_ZFLG (((uae_s16)(newv)) == 0);
60715: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60716: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60717: SET_NFLG (flgn != 0);
60718: }}}}}}m68k_incpc(2);
60719: fill_prefetch_2 ();
60720: return 4;
60721: }
60722: unsigned long REGPARAM2 CPUFUNC(op_b048_5)(uae_u32 opcode) /* CMP */
60723: {
60724: uae_u32 srcreg = (opcode & 7);
60725: uae_u32 dstreg = (opcode >> 9) & 7;
60726: OpcodeFamily = 25; CurrentInstrCycles = 4;
60727: {{ uae_s16 src = m68k_areg(regs, srcreg);
60728: { uae_s16 dst = m68k_dreg(regs, dstreg);
60729: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60730: { int flgs = ((uae_s16)(src)) < 0;
60731: int flgo = ((uae_s16)(dst)) < 0;
60732: int flgn = ((uae_s16)(newv)) < 0;
60733: SET_ZFLG (((uae_s16)(newv)) == 0);
60734: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60735: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60736: SET_NFLG (flgn != 0);
60737: }}}}}}m68k_incpc(2);
60738: fill_prefetch_2 ();
60739: return 4;
60740: }
60741: unsigned long REGPARAM2 CPUFUNC(op_b050_5)(uae_u32 opcode) /* CMP */
60742: {
60743: uae_u32 srcreg = (opcode & 7);
60744: uae_u32 dstreg = (opcode >> 9) & 7;
60745: OpcodeFamily = 25; CurrentInstrCycles = 8;
60746: {{ uaecptr srca = m68k_areg(regs, srcreg);
60747: if ((srca & 1) != 0) {
60748: last_fault_for_exception_3 = srca;
60749: last_op_for_exception_3 = opcode;
60750: last_addr_for_exception_3 = m68k_getpc() + 2;
60751: Exception(3, 0, M68000_EXC_SRC_CPU);
60752: goto endlabel3391;
60753: }
60754: {{ uae_s16 src = get_word(srca);
60755: { uae_s16 dst = m68k_dreg(regs, dstreg);
60756: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60757: { int flgs = ((uae_s16)(src)) < 0;
60758: int flgo = ((uae_s16)(dst)) < 0;
60759: int flgn = ((uae_s16)(newv)) < 0;
60760: SET_ZFLG (((uae_s16)(newv)) == 0);
60761: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60762: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60763: SET_NFLG (flgn != 0);
60764: }}}}}}}}m68k_incpc(2);
60765: fill_prefetch_2 ();
60766: endlabel3391: ;
60767: return 8;
60768: }
60769: unsigned long REGPARAM2 CPUFUNC(op_b058_5)(uae_u32 opcode) /* CMP */
60770: {
60771: uae_u32 srcreg = (opcode & 7);
60772: uae_u32 dstreg = (opcode >> 9) & 7;
60773: OpcodeFamily = 25; CurrentInstrCycles = 8;
60774: {{ uaecptr srca = m68k_areg(regs, srcreg);
60775: if ((srca & 1) != 0) {
60776: last_fault_for_exception_3 = srca;
60777: last_op_for_exception_3 = opcode;
60778: last_addr_for_exception_3 = m68k_getpc() + 2;
60779: Exception(3, 0, M68000_EXC_SRC_CPU);
60780: goto endlabel3392;
60781: }
60782: {{ uae_s16 src = get_word(srca);
60783: m68k_areg(regs, srcreg) += 2;
60784: { uae_s16 dst = m68k_dreg(regs, dstreg);
60785: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60786: { int flgs = ((uae_s16)(src)) < 0;
60787: int flgo = ((uae_s16)(dst)) < 0;
60788: int flgn = ((uae_s16)(newv)) < 0;
60789: SET_ZFLG (((uae_s16)(newv)) == 0);
60790: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60791: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60792: SET_NFLG (flgn != 0);
60793: }}}}}}}}m68k_incpc(2);
60794: fill_prefetch_2 ();
60795: endlabel3392: ;
60796: return 8;
60797: }
60798: unsigned long REGPARAM2 CPUFUNC(op_b060_5)(uae_u32 opcode) /* CMP */
60799: {
60800: uae_u32 srcreg = (opcode & 7);
60801: uae_u32 dstreg = (opcode >> 9) & 7;
60802: OpcodeFamily = 25; CurrentInstrCycles = 10;
60803: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
60804: if ((srca & 1) != 0) {
60805: last_fault_for_exception_3 = srca;
60806: last_op_for_exception_3 = opcode;
60807: last_addr_for_exception_3 = m68k_getpc() + 2;
60808: Exception(3, 0, M68000_EXC_SRC_CPU);
60809: goto endlabel3393;
60810: }
60811: {{ uae_s16 src = get_word(srca);
60812: m68k_areg (regs, srcreg) = srca;
60813: { uae_s16 dst = m68k_dreg(regs, dstreg);
60814: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60815: { int flgs = ((uae_s16)(src)) < 0;
60816: int flgo = ((uae_s16)(dst)) < 0;
60817: int flgn = ((uae_s16)(newv)) < 0;
60818: SET_ZFLG (((uae_s16)(newv)) == 0);
60819: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60820: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60821: SET_NFLG (flgn != 0);
60822: }}}}}}}}m68k_incpc(2);
60823: fill_prefetch_2 ();
60824: endlabel3393: ;
60825: return 10;
60826: }
60827: unsigned long REGPARAM2 CPUFUNC(op_b068_5)(uae_u32 opcode) /* CMP */
60828: {
60829: uae_u32 srcreg = (opcode & 7);
60830: uae_u32 dstreg = (opcode >> 9) & 7;
60831: OpcodeFamily = 25; CurrentInstrCycles = 12;
60832: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
60833: if ((srca & 1) != 0) {
60834: last_fault_for_exception_3 = srca;
60835: last_op_for_exception_3 = opcode;
60836: last_addr_for_exception_3 = m68k_getpc() + 4;
60837: Exception(3, 0, M68000_EXC_SRC_CPU);
60838: goto endlabel3394;
60839: }
60840: {{ uae_s16 src = get_word(srca);
60841: { uae_s16 dst = m68k_dreg(regs, dstreg);
60842: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60843: { int flgs = ((uae_s16)(src)) < 0;
60844: int flgo = ((uae_s16)(dst)) < 0;
60845: int flgn = ((uae_s16)(newv)) < 0;
60846: SET_ZFLG (((uae_s16)(newv)) == 0);
60847: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60848: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60849: SET_NFLG (flgn != 0);
60850: }}}}}}}}m68k_incpc(4);
60851: fill_prefetch_0 ();
60852: endlabel3394: ;
60853: return 12;
60854: }
60855: unsigned long REGPARAM2 CPUFUNC(op_b070_5)(uae_u32 opcode) /* CMP */
60856: {
60857: uae_u32 srcreg = (opcode & 7);
60858: uae_u32 dstreg = (opcode >> 9) & 7;
60859: OpcodeFamily = 25; CurrentInstrCycles = 14;
60860: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
60861: BusCyclePenalty += 2;
60862: if ((srca & 1) != 0) {
60863: last_fault_for_exception_3 = srca;
60864: last_op_for_exception_3 = opcode;
60865: last_addr_for_exception_3 = m68k_getpc() + 4;
60866: Exception(3, 0, M68000_EXC_SRC_CPU);
60867: goto endlabel3395;
60868: }
60869: {{ uae_s16 src = get_word(srca);
60870: { uae_s16 dst = m68k_dreg(regs, dstreg);
60871: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60872: { int flgs = ((uae_s16)(src)) < 0;
60873: int flgo = ((uae_s16)(dst)) < 0;
60874: int flgn = ((uae_s16)(newv)) < 0;
60875: SET_ZFLG (((uae_s16)(newv)) == 0);
60876: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60877: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60878: SET_NFLG (flgn != 0);
60879: }}}}}}}}m68k_incpc(4);
60880: fill_prefetch_0 ();
60881: endlabel3395: ;
60882: return 14;
60883: }
60884: unsigned long REGPARAM2 CPUFUNC(op_b078_5)(uae_u32 opcode) /* CMP */
60885: {
60886: uae_u32 dstreg = (opcode >> 9) & 7;
60887: OpcodeFamily = 25; CurrentInstrCycles = 12;
60888: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
60889: if ((srca & 1) != 0) {
60890: last_fault_for_exception_3 = srca;
60891: last_op_for_exception_3 = opcode;
60892: last_addr_for_exception_3 = m68k_getpc() + 4;
60893: Exception(3, 0, M68000_EXC_SRC_CPU);
60894: goto endlabel3396;
60895: }
60896: {{ uae_s16 src = get_word(srca);
60897: { uae_s16 dst = m68k_dreg(regs, dstreg);
60898: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60899: { int flgs = ((uae_s16)(src)) < 0;
60900: int flgo = ((uae_s16)(dst)) < 0;
60901: int flgn = ((uae_s16)(newv)) < 0;
60902: SET_ZFLG (((uae_s16)(newv)) == 0);
60903: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60904: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60905: SET_NFLG (flgn != 0);
60906: }}}}}}}}m68k_incpc(4);
60907: fill_prefetch_0 ();
60908: endlabel3396: ;
60909: return 12;
60910: }
60911: unsigned long REGPARAM2 CPUFUNC(op_b079_5)(uae_u32 opcode) /* CMP */
60912: {
60913: uae_u32 dstreg = (opcode >> 9) & 7;
60914: OpcodeFamily = 25; CurrentInstrCycles = 16;
60915: {{ uaecptr srca = get_ilong_prefetch(2);
60916: if ((srca & 1) != 0) {
60917: last_fault_for_exception_3 = srca;
60918: last_op_for_exception_3 = opcode;
60919: last_addr_for_exception_3 = m68k_getpc() + 6;
60920: Exception(3, 0, M68000_EXC_SRC_CPU);
60921: goto endlabel3397;
60922: }
60923: {{ uae_s16 src = get_word(srca);
60924: { uae_s16 dst = m68k_dreg(regs, dstreg);
60925: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60926: { int flgs = ((uae_s16)(src)) < 0;
60927: int flgo = ((uae_s16)(dst)) < 0;
60928: int flgn = ((uae_s16)(newv)) < 0;
60929: SET_ZFLG (((uae_s16)(newv)) == 0);
60930: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60931: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60932: SET_NFLG (flgn != 0);
60933: }}}}}}}}m68k_incpc(6);
60934: fill_prefetch_0 ();
60935: endlabel3397: ;
60936: return 16;
60937: }
60938: unsigned long REGPARAM2 CPUFUNC(op_b07a_5)(uae_u32 opcode) /* CMP */
60939: {
60940: uae_u32 dstreg = (opcode >> 9) & 7;
60941: OpcodeFamily = 25; CurrentInstrCycles = 12;
60942: {{ uaecptr srca = m68k_getpc () + 2;
60943: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
60944: if ((srca & 1) != 0) {
60945: last_fault_for_exception_3 = srca;
60946: last_op_for_exception_3 = opcode;
60947: last_addr_for_exception_3 = m68k_getpc() + 4;
60948: Exception(3, 0, M68000_EXC_SRC_CPU);
60949: goto endlabel3398;
60950: }
60951: {{ uae_s16 src = get_word(srca);
60952: { uae_s16 dst = m68k_dreg(regs, dstreg);
60953: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60954: { int flgs = ((uae_s16)(src)) < 0;
60955: int flgo = ((uae_s16)(dst)) < 0;
60956: int flgn = ((uae_s16)(newv)) < 0;
60957: SET_ZFLG (((uae_s16)(newv)) == 0);
60958: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60959: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60960: SET_NFLG (flgn != 0);
60961: }}}}}}}}m68k_incpc(4);
60962: fill_prefetch_0 ();
60963: endlabel3398: ;
60964: return 12;
60965: }
60966: unsigned long REGPARAM2 CPUFUNC(op_b07b_5)(uae_u32 opcode) /* CMP */
60967: {
60968: uae_u32 dstreg = (opcode >> 9) & 7;
60969: OpcodeFamily = 25; CurrentInstrCycles = 14;
60970: {{ uaecptr tmppc = m68k_getpc() + 2;
60971: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
60972: BusCyclePenalty += 2;
60973: if ((srca & 1) != 0) {
60974: last_fault_for_exception_3 = srca;
60975: last_op_for_exception_3 = opcode;
60976: last_addr_for_exception_3 = m68k_getpc() + 4;
60977: Exception(3, 0, M68000_EXC_SRC_CPU);
60978: goto endlabel3399;
60979: }
60980: {{ uae_s16 src = get_word(srca);
60981: { uae_s16 dst = m68k_dreg(regs, dstreg);
60982: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
60983: { int flgs = ((uae_s16)(src)) < 0;
60984: int flgo = ((uae_s16)(dst)) < 0;
60985: int flgn = ((uae_s16)(newv)) < 0;
60986: SET_ZFLG (((uae_s16)(newv)) == 0);
60987: SET_VFLG ((flgs != flgo) && (flgn != flgo));
60988: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
60989: SET_NFLG (flgn != 0);
60990: }}}}}}}}m68k_incpc(4);
60991: fill_prefetch_0 ();
60992: endlabel3399: ;
60993: return 14;
60994: }
60995: unsigned long REGPARAM2 CPUFUNC(op_b07c_5)(uae_u32 opcode) /* CMP */
60996: {
60997: uae_u32 dstreg = (opcode >> 9) & 7;
60998: OpcodeFamily = 25; CurrentInstrCycles = 8;
60999: {{ uae_s16 src = get_iword_prefetch(2);
61000: { uae_s16 dst = m68k_dreg(regs, dstreg);
61001: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
61002: { int flgs = ((uae_s16)(src)) < 0;
61003: int flgo = ((uae_s16)(dst)) < 0;
61004: int flgn = ((uae_s16)(newv)) < 0;
61005: SET_ZFLG (((uae_s16)(newv)) == 0);
61006: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61007: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
61008: SET_NFLG (flgn != 0);
61009: }}}}}}m68k_incpc(4);
61010: fill_prefetch_0 ();
61011: return 8;
61012: }
61013: unsigned long REGPARAM2 CPUFUNC(op_b080_5)(uae_u32 opcode) /* CMP */
61014: {
61015: uae_u32 srcreg = (opcode & 7);
61016: uae_u32 dstreg = (opcode >> 9) & 7;
61017: OpcodeFamily = 25; CurrentInstrCycles = 6;
61018: {{ uae_s32 src = m68k_dreg(regs, srcreg);
61019: { uae_s32 dst = m68k_dreg(regs, dstreg);
61020: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61021: { int flgs = ((uae_s32)(src)) < 0;
61022: int flgo = ((uae_s32)(dst)) < 0;
61023: int flgn = ((uae_s32)(newv)) < 0;
61024: SET_ZFLG (((uae_s32)(newv)) == 0);
61025: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61026: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61027: SET_NFLG (flgn != 0);
61028: }}}}}}m68k_incpc(2);
61029: fill_prefetch_2 ();
61030: return 6;
61031: }
61032: unsigned long REGPARAM2 CPUFUNC(op_b088_5)(uae_u32 opcode) /* CMP */
61033: {
61034: uae_u32 srcreg = (opcode & 7);
61035: uae_u32 dstreg = (opcode >> 9) & 7;
61036: OpcodeFamily = 25; CurrentInstrCycles = 6;
61037: {{ uae_s32 src = m68k_areg(regs, srcreg);
61038: { uae_s32 dst = m68k_dreg(regs, dstreg);
61039: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61040: { int flgs = ((uae_s32)(src)) < 0;
61041: int flgo = ((uae_s32)(dst)) < 0;
61042: int flgn = ((uae_s32)(newv)) < 0;
61043: SET_ZFLG (((uae_s32)(newv)) == 0);
61044: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61045: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61046: SET_NFLG (flgn != 0);
61047: }}}}}}m68k_incpc(2);
61048: fill_prefetch_2 ();
61049: return 6;
61050: }
61051: unsigned long REGPARAM2 CPUFUNC(op_b090_5)(uae_u32 opcode) /* CMP */
61052: {
61053: uae_u32 srcreg = (opcode & 7);
61054: uae_u32 dstreg = (opcode >> 9) & 7;
61055: OpcodeFamily = 25; CurrentInstrCycles = 14;
61056: {{ uaecptr srca = m68k_areg(regs, srcreg);
61057: if ((srca & 1) != 0) {
61058: last_fault_for_exception_3 = srca;
61059: last_op_for_exception_3 = opcode;
61060: last_addr_for_exception_3 = m68k_getpc() + 2;
61061: Exception(3, 0, M68000_EXC_SRC_CPU);
61062: goto endlabel3403;
61063: }
61064: {{ uae_s32 src = get_long(srca);
61065: { uae_s32 dst = m68k_dreg(regs, dstreg);
61066: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61067: { int flgs = ((uae_s32)(src)) < 0;
61068: int flgo = ((uae_s32)(dst)) < 0;
61069: int flgn = ((uae_s32)(newv)) < 0;
61070: SET_ZFLG (((uae_s32)(newv)) == 0);
61071: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61072: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61073: SET_NFLG (flgn != 0);
61074: }}}}}}}}m68k_incpc(2);
61075: fill_prefetch_2 ();
61076: endlabel3403: ;
61077: return 14;
61078: }
61079: unsigned long REGPARAM2 CPUFUNC(op_b098_5)(uae_u32 opcode) /* CMP */
61080: {
61081: uae_u32 srcreg = (opcode & 7);
61082: uae_u32 dstreg = (opcode >> 9) & 7;
61083: OpcodeFamily = 25; CurrentInstrCycles = 14;
61084: {{ uaecptr srca = m68k_areg(regs, srcreg);
61085: if ((srca & 1) != 0) {
61086: last_fault_for_exception_3 = srca;
61087: last_op_for_exception_3 = opcode;
61088: last_addr_for_exception_3 = m68k_getpc() + 2;
61089: Exception(3, 0, M68000_EXC_SRC_CPU);
61090: goto endlabel3404;
61091: }
61092: {{ uae_s32 src = get_long(srca);
61093: m68k_areg(regs, srcreg) += 4;
61094: { uae_s32 dst = m68k_dreg(regs, dstreg);
61095: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61096: { int flgs = ((uae_s32)(src)) < 0;
61097: int flgo = ((uae_s32)(dst)) < 0;
61098: int flgn = ((uae_s32)(newv)) < 0;
61099: SET_ZFLG (((uae_s32)(newv)) == 0);
61100: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61101: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61102: SET_NFLG (flgn != 0);
61103: }}}}}}}}m68k_incpc(2);
61104: fill_prefetch_2 ();
61105: endlabel3404: ;
61106: return 14;
61107: }
61108: unsigned long REGPARAM2 CPUFUNC(op_b0a0_5)(uae_u32 opcode) /* CMP */
61109: {
61110: uae_u32 srcreg = (opcode & 7);
61111: uae_u32 dstreg = (opcode >> 9) & 7;
61112: OpcodeFamily = 25; CurrentInstrCycles = 16;
61113: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
61114: if ((srca & 1) != 0) {
61115: last_fault_for_exception_3 = srca;
61116: last_op_for_exception_3 = opcode;
61117: last_addr_for_exception_3 = m68k_getpc() + 2;
61118: Exception(3, 0, M68000_EXC_SRC_CPU);
61119: goto endlabel3405;
61120: }
61121: {{ uae_s32 src = get_long(srca);
61122: m68k_areg (regs, srcreg) = srca;
61123: { uae_s32 dst = m68k_dreg(regs, dstreg);
61124: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61125: { int flgs = ((uae_s32)(src)) < 0;
61126: int flgo = ((uae_s32)(dst)) < 0;
61127: int flgn = ((uae_s32)(newv)) < 0;
61128: SET_ZFLG (((uae_s32)(newv)) == 0);
61129: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61130: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61131: SET_NFLG (flgn != 0);
61132: }}}}}}}}m68k_incpc(2);
61133: fill_prefetch_2 ();
61134: endlabel3405: ;
61135: return 16;
61136: }
61137: unsigned long REGPARAM2 CPUFUNC(op_b0a8_5)(uae_u32 opcode) /* CMP */
61138: {
61139: uae_u32 srcreg = (opcode & 7);
61140: uae_u32 dstreg = (opcode >> 9) & 7;
61141: OpcodeFamily = 25; CurrentInstrCycles = 18;
61142: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
61143: if ((srca & 1) != 0) {
61144: last_fault_for_exception_3 = srca;
61145: last_op_for_exception_3 = opcode;
61146: last_addr_for_exception_3 = m68k_getpc() + 4;
61147: Exception(3, 0, M68000_EXC_SRC_CPU);
61148: goto endlabel3406;
61149: }
61150: {{ uae_s32 src = get_long(srca);
61151: { uae_s32 dst = m68k_dreg(regs, dstreg);
61152: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61153: { int flgs = ((uae_s32)(src)) < 0;
61154: int flgo = ((uae_s32)(dst)) < 0;
61155: int flgn = ((uae_s32)(newv)) < 0;
61156: SET_ZFLG (((uae_s32)(newv)) == 0);
61157: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61158: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61159: SET_NFLG (flgn != 0);
61160: }}}}}}}}m68k_incpc(4);
61161: fill_prefetch_0 ();
61162: endlabel3406: ;
61163: return 18;
61164: }
61165: unsigned long REGPARAM2 CPUFUNC(op_b0b0_5)(uae_u32 opcode) /* CMP */
61166: {
61167: uae_u32 srcreg = (opcode & 7);
61168: uae_u32 dstreg = (opcode >> 9) & 7;
61169: OpcodeFamily = 25; CurrentInstrCycles = 20;
61170: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
61171: BusCyclePenalty += 2;
61172: if ((srca & 1) != 0) {
61173: last_fault_for_exception_3 = srca;
61174: last_op_for_exception_3 = opcode;
61175: last_addr_for_exception_3 = m68k_getpc() + 4;
61176: Exception(3, 0, M68000_EXC_SRC_CPU);
61177: goto endlabel3407;
61178: }
61179: {{ uae_s32 src = get_long(srca);
61180: { uae_s32 dst = m68k_dreg(regs, dstreg);
61181: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61182: { int flgs = ((uae_s32)(src)) < 0;
61183: int flgo = ((uae_s32)(dst)) < 0;
61184: int flgn = ((uae_s32)(newv)) < 0;
61185: SET_ZFLG (((uae_s32)(newv)) == 0);
61186: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61187: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61188: SET_NFLG (flgn != 0);
61189: }}}}}}}}m68k_incpc(4);
61190: fill_prefetch_0 ();
61191: endlabel3407: ;
61192: return 20;
61193: }
61194: unsigned long REGPARAM2 CPUFUNC(op_b0b8_5)(uae_u32 opcode) /* CMP */
61195: {
61196: uae_u32 dstreg = (opcode >> 9) & 7;
61197: OpcodeFamily = 25; CurrentInstrCycles = 18;
61198: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
61199: if ((srca & 1) != 0) {
61200: last_fault_for_exception_3 = srca;
61201: last_op_for_exception_3 = opcode;
61202: last_addr_for_exception_3 = m68k_getpc() + 4;
61203: Exception(3, 0, M68000_EXC_SRC_CPU);
61204: goto endlabel3408;
61205: }
61206: {{ uae_s32 src = get_long(srca);
61207: { uae_s32 dst = m68k_dreg(regs, dstreg);
61208: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61209: { int flgs = ((uae_s32)(src)) < 0;
61210: int flgo = ((uae_s32)(dst)) < 0;
61211: int flgn = ((uae_s32)(newv)) < 0;
61212: SET_ZFLG (((uae_s32)(newv)) == 0);
61213: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61214: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61215: SET_NFLG (flgn != 0);
61216: }}}}}}}}m68k_incpc(4);
61217: fill_prefetch_0 ();
61218: endlabel3408: ;
61219: return 18;
61220: }
61221: unsigned long REGPARAM2 CPUFUNC(op_b0b9_5)(uae_u32 opcode) /* CMP */
61222: {
61223: uae_u32 dstreg = (opcode >> 9) & 7;
61224: OpcodeFamily = 25; CurrentInstrCycles = 22;
61225: {{ uaecptr srca = get_ilong_prefetch(2);
61226: if ((srca & 1) != 0) {
61227: last_fault_for_exception_3 = srca;
61228: last_op_for_exception_3 = opcode;
61229: last_addr_for_exception_3 = m68k_getpc() + 6;
61230: Exception(3, 0, M68000_EXC_SRC_CPU);
61231: goto endlabel3409;
61232: }
61233: {{ uae_s32 src = get_long(srca);
61234: { uae_s32 dst = m68k_dreg(regs, dstreg);
61235: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61236: { int flgs = ((uae_s32)(src)) < 0;
61237: int flgo = ((uae_s32)(dst)) < 0;
61238: int flgn = ((uae_s32)(newv)) < 0;
61239: SET_ZFLG (((uae_s32)(newv)) == 0);
61240: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61241: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61242: SET_NFLG (flgn != 0);
61243: }}}}}}}}m68k_incpc(6);
61244: fill_prefetch_0 ();
61245: endlabel3409: ;
61246: return 22;
61247: }
61248: unsigned long REGPARAM2 CPUFUNC(op_b0ba_5)(uae_u32 opcode) /* CMP */
61249: {
61250: uae_u32 dstreg = (opcode >> 9) & 7;
61251: OpcodeFamily = 25; CurrentInstrCycles = 18;
61252: {{ uaecptr srca = m68k_getpc () + 2;
61253: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
61254: if ((srca & 1) != 0) {
61255: last_fault_for_exception_3 = srca;
61256: last_op_for_exception_3 = opcode;
61257: last_addr_for_exception_3 = m68k_getpc() + 4;
61258: Exception(3, 0, M68000_EXC_SRC_CPU);
61259: goto endlabel3410;
61260: }
61261: {{ uae_s32 src = get_long(srca);
61262: { uae_s32 dst = m68k_dreg(regs, dstreg);
61263: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61264: { int flgs = ((uae_s32)(src)) < 0;
61265: int flgo = ((uae_s32)(dst)) < 0;
61266: int flgn = ((uae_s32)(newv)) < 0;
61267: SET_ZFLG (((uae_s32)(newv)) == 0);
61268: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61269: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61270: SET_NFLG (flgn != 0);
61271: }}}}}}}}m68k_incpc(4);
61272: fill_prefetch_0 ();
61273: endlabel3410: ;
61274: return 18;
61275: }
61276: unsigned long REGPARAM2 CPUFUNC(op_b0bb_5)(uae_u32 opcode) /* CMP */
61277: {
61278: uae_u32 dstreg = (opcode >> 9) & 7;
61279: OpcodeFamily = 25; CurrentInstrCycles = 20;
61280: {{ uaecptr tmppc = m68k_getpc() + 2;
61281: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
61282: BusCyclePenalty += 2;
61283: if ((srca & 1) != 0) {
61284: last_fault_for_exception_3 = srca;
61285: last_op_for_exception_3 = opcode;
61286: last_addr_for_exception_3 = m68k_getpc() + 4;
61287: Exception(3, 0, M68000_EXC_SRC_CPU);
61288: goto endlabel3411;
61289: }
61290: {{ uae_s32 src = get_long(srca);
61291: { uae_s32 dst = m68k_dreg(regs, dstreg);
61292: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61293: { int flgs = ((uae_s32)(src)) < 0;
61294: int flgo = ((uae_s32)(dst)) < 0;
61295: int flgn = ((uae_s32)(newv)) < 0;
61296: SET_ZFLG (((uae_s32)(newv)) == 0);
61297: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61298: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61299: SET_NFLG (flgn != 0);
61300: }}}}}}}}m68k_incpc(4);
61301: fill_prefetch_0 ();
61302: endlabel3411: ;
61303: return 20;
61304: }
61305: unsigned long REGPARAM2 CPUFUNC(op_b0bc_5)(uae_u32 opcode) /* CMP */
61306: {
61307: uae_u32 dstreg = (opcode >> 9) & 7;
61308: OpcodeFamily = 25; CurrentInstrCycles = 14;
61309: {{ uae_s32 src = get_ilong_prefetch(2);
61310: { uae_s32 dst = m68k_dreg(regs, dstreg);
61311: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61312: { int flgs = ((uae_s32)(src)) < 0;
61313: int flgo = ((uae_s32)(dst)) < 0;
61314: int flgn = ((uae_s32)(newv)) < 0;
61315: SET_ZFLG (((uae_s32)(newv)) == 0);
61316: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61317: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61318: SET_NFLG (flgn != 0);
61319: }}}}}}m68k_incpc(6);
61320: fill_prefetch_0 ();
61321: return 14;
61322: }
61323: unsigned long REGPARAM2 CPUFUNC(op_b0c0_5)(uae_u32 opcode) /* CMPA */
61324: {
61325: uae_u32 srcreg = (opcode & 7);
61326: uae_u32 dstreg = (opcode >> 9) & 7;
61327: OpcodeFamily = 27; CurrentInstrCycles = 6;
61328: {{ uae_s16 src = m68k_dreg(regs, srcreg);
61329: { uae_s32 dst = m68k_areg(regs, dstreg);
61330: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61331: { int flgs = ((uae_s32)(src)) < 0;
61332: int flgo = ((uae_s32)(dst)) < 0;
61333: int flgn = ((uae_s32)(newv)) < 0;
61334: SET_ZFLG (((uae_s32)(newv)) == 0);
61335: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61336: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61337: SET_NFLG (flgn != 0);
61338: }}}}}}m68k_incpc(2);
61339: fill_prefetch_2 ();
61340: return 6;
61341: }
61342: unsigned long REGPARAM2 CPUFUNC(op_b0c8_5)(uae_u32 opcode) /* CMPA */
61343: {
61344: uae_u32 srcreg = (opcode & 7);
61345: uae_u32 dstreg = (opcode >> 9) & 7;
61346: OpcodeFamily = 27; CurrentInstrCycles = 6;
61347: {{ uae_s16 src = m68k_areg(regs, srcreg);
61348: { uae_s32 dst = m68k_areg(regs, dstreg);
61349: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61350: { int flgs = ((uae_s32)(src)) < 0;
61351: int flgo = ((uae_s32)(dst)) < 0;
61352: int flgn = ((uae_s32)(newv)) < 0;
61353: SET_ZFLG (((uae_s32)(newv)) == 0);
61354: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61355: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61356: SET_NFLG (flgn != 0);
61357: }}}}}}m68k_incpc(2);
61358: fill_prefetch_2 ();
61359: return 6;
61360: }
61361: unsigned long REGPARAM2 CPUFUNC(op_b0d0_5)(uae_u32 opcode) /* CMPA */
61362: {
61363: uae_u32 srcreg = (opcode & 7);
61364: uae_u32 dstreg = (opcode >> 9) & 7;
61365: OpcodeFamily = 27; CurrentInstrCycles = 10;
61366: {{ uaecptr srca = m68k_areg(regs, srcreg);
61367: if ((srca & 1) != 0) {
61368: last_fault_for_exception_3 = srca;
61369: last_op_for_exception_3 = opcode;
61370: last_addr_for_exception_3 = m68k_getpc() + 2;
61371: Exception(3, 0, M68000_EXC_SRC_CPU);
61372: goto endlabel3415;
61373: }
61374: {{ uae_s16 src = get_word(srca);
61375: { uae_s32 dst = m68k_areg(regs, dstreg);
61376: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61377: { int flgs = ((uae_s32)(src)) < 0;
61378: int flgo = ((uae_s32)(dst)) < 0;
61379: int flgn = ((uae_s32)(newv)) < 0;
61380: SET_ZFLG (((uae_s32)(newv)) == 0);
61381: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61382: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61383: SET_NFLG (flgn != 0);
61384: }}}}}}}}m68k_incpc(2);
61385: fill_prefetch_2 ();
61386: endlabel3415: ;
61387: return 10;
61388: }
61389: unsigned long REGPARAM2 CPUFUNC(op_b0d8_5)(uae_u32 opcode) /* CMPA */
61390: {
61391: uae_u32 srcreg = (opcode & 7);
61392: uae_u32 dstreg = (opcode >> 9) & 7;
61393: OpcodeFamily = 27; CurrentInstrCycles = 10;
61394: {{ uaecptr srca = m68k_areg(regs, srcreg);
61395: if ((srca & 1) != 0) {
61396: last_fault_for_exception_3 = srca;
61397: last_op_for_exception_3 = opcode;
61398: last_addr_for_exception_3 = m68k_getpc() + 2;
61399: Exception(3, 0, M68000_EXC_SRC_CPU);
61400: goto endlabel3416;
61401: }
61402: {{ uae_s16 src = get_word(srca);
61403: m68k_areg(regs, srcreg) += 2;
61404: { uae_s32 dst = m68k_areg(regs, dstreg);
61405: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61406: { int flgs = ((uae_s32)(src)) < 0;
61407: int flgo = ((uae_s32)(dst)) < 0;
61408: int flgn = ((uae_s32)(newv)) < 0;
61409: SET_ZFLG (((uae_s32)(newv)) == 0);
61410: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61411: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61412: SET_NFLG (flgn != 0);
61413: }}}}}}}}m68k_incpc(2);
61414: fill_prefetch_2 ();
61415: endlabel3416: ;
61416: return 10;
61417: }
61418: unsigned long REGPARAM2 CPUFUNC(op_b0e0_5)(uae_u32 opcode) /* CMPA */
61419: {
61420: uae_u32 srcreg = (opcode & 7);
61421: uae_u32 dstreg = (opcode >> 9) & 7;
61422: OpcodeFamily = 27; CurrentInstrCycles = 12;
61423: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
61424: if ((srca & 1) != 0) {
61425: last_fault_for_exception_3 = srca;
61426: last_op_for_exception_3 = opcode;
61427: last_addr_for_exception_3 = m68k_getpc() + 2;
61428: Exception(3, 0, M68000_EXC_SRC_CPU);
61429: goto endlabel3417;
61430: }
61431: {{ uae_s16 src = get_word(srca);
61432: m68k_areg (regs, srcreg) = srca;
61433: { uae_s32 dst = m68k_areg(regs, dstreg);
61434: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61435: { int flgs = ((uae_s32)(src)) < 0;
61436: int flgo = ((uae_s32)(dst)) < 0;
61437: int flgn = ((uae_s32)(newv)) < 0;
61438: SET_ZFLG (((uae_s32)(newv)) == 0);
61439: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61440: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61441: SET_NFLG (flgn != 0);
61442: }}}}}}}}m68k_incpc(2);
61443: fill_prefetch_2 ();
61444: endlabel3417: ;
61445: return 12;
61446: }
61447: unsigned long REGPARAM2 CPUFUNC(op_b0e8_5)(uae_u32 opcode) /* CMPA */
61448: {
61449: uae_u32 srcreg = (opcode & 7);
61450: uae_u32 dstreg = (opcode >> 9) & 7;
61451: OpcodeFamily = 27; CurrentInstrCycles = 14;
61452: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
61453: if ((srca & 1) != 0) {
61454: last_fault_for_exception_3 = srca;
61455: last_op_for_exception_3 = opcode;
61456: last_addr_for_exception_3 = m68k_getpc() + 4;
61457: Exception(3, 0, M68000_EXC_SRC_CPU);
61458: goto endlabel3418;
61459: }
61460: {{ uae_s16 src = get_word(srca);
61461: { uae_s32 dst = m68k_areg(regs, dstreg);
61462: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61463: { int flgs = ((uae_s32)(src)) < 0;
61464: int flgo = ((uae_s32)(dst)) < 0;
61465: int flgn = ((uae_s32)(newv)) < 0;
61466: SET_ZFLG (((uae_s32)(newv)) == 0);
61467: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61468: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61469: SET_NFLG (flgn != 0);
61470: }}}}}}}}m68k_incpc(4);
61471: fill_prefetch_0 ();
61472: endlabel3418: ;
61473: return 14;
61474: }
61475: unsigned long REGPARAM2 CPUFUNC(op_b0f0_5)(uae_u32 opcode) /* CMPA */
61476: {
61477: uae_u32 srcreg = (opcode & 7);
61478: uae_u32 dstreg = (opcode >> 9) & 7;
61479: OpcodeFamily = 27; CurrentInstrCycles = 16;
61480: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
61481: BusCyclePenalty += 2;
61482: if ((srca & 1) != 0) {
61483: last_fault_for_exception_3 = srca;
61484: last_op_for_exception_3 = opcode;
61485: last_addr_for_exception_3 = m68k_getpc() + 4;
61486: Exception(3, 0, M68000_EXC_SRC_CPU);
61487: goto endlabel3419;
61488: }
61489: {{ uae_s16 src = get_word(srca);
61490: { uae_s32 dst = m68k_areg(regs, dstreg);
61491: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61492: { int flgs = ((uae_s32)(src)) < 0;
61493: int flgo = ((uae_s32)(dst)) < 0;
61494: int flgn = ((uae_s32)(newv)) < 0;
61495: SET_ZFLG (((uae_s32)(newv)) == 0);
61496: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61497: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61498: SET_NFLG (flgn != 0);
61499: }}}}}}}}m68k_incpc(4);
61500: fill_prefetch_0 ();
61501: endlabel3419: ;
61502: return 16;
61503: }
61504: unsigned long REGPARAM2 CPUFUNC(op_b0f8_5)(uae_u32 opcode) /* CMPA */
61505: {
61506: uae_u32 dstreg = (opcode >> 9) & 7;
61507: OpcodeFamily = 27; CurrentInstrCycles = 14;
61508: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
61509: if ((srca & 1) != 0) {
61510: last_fault_for_exception_3 = srca;
61511: last_op_for_exception_3 = opcode;
61512: last_addr_for_exception_3 = m68k_getpc() + 4;
61513: Exception(3, 0, M68000_EXC_SRC_CPU);
61514: goto endlabel3420;
61515: }
61516: {{ uae_s16 src = get_word(srca);
61517: { uae_s32 dst = m68k_areg(regs, dstreg);
61518: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61519: { int flgs = ((uae_s32)(src)) < 0;
61520: int flgo = ((uae_s32)(dst)) < 0;
61521: int flgn = ((uae_s32)(newv)) < 0;
61522: SET_ZFLG (((uae_s32)(newv)) == 0);
61523: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61524: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61525: SET_NFLG (flgn != 0);
61526: }}}}}}}}m68k_incpc(4);
61527: fill_prefetch_0 ();
61528: endlabel3420: ;
61529: return 14;
61530: }
61531: unsigned long REGPARAM2 CPUFUNC(op_b0f9_5)(uae_u32 opcode) /* CMPA */
61532: {
61533: uae_u32 dstreg = (opcode >> 9) & 7;
61534: OpcodeFamily = 27; CurrentInstrCycles = 18;
61535: {{ uaecptr srca = get_ilong_prefetch(2);
61536: if ((srca & 1) != 0) {
61537: last_fault_for_exception_3 = srca;
61538: last_op_for_exception_3 = opcode;
61539: last_addr_for_exception_3 = m68k_getpc() + 6;
61540: Exception(3, 0, M68000_EXC_SRC_CPU);
61541: goto endlabel3421;
61542: }
61543: {{ uae_s16 src = get_word(srca);
61544: { uae_s32 dst = m68k_areg(regs, dstreg);
61545: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61546: { int flgs = ((uae_s32)(src)) < 0;
61547: int flgo = ((uae_s32)(dst)) < 0;
61548: int flgn = ((uae_s32)(newv)) < 0;
61549: SET_ZFLG (((uae_s32)(newv)) == 0);
61550: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61551: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61552: SET_NFLG (flgn != 0);
61553: }}}}}}}}m68k_incpc(6);
61554: fill_prefetch_0 ();
61555: endlabel3421: ;
61556: return 18;
61557: }
61558: unsigned long REGPARAM2 CPUFUNC(op_b0fa_5)(uae_u32 opcode) /* CMPA */
61559: {
61560: uae_u32 dstreg = (opcode >> 9) & 7;
61561: OpcodeFamily = 27; CurrentInstrCycles = 14;
61562: {{ uaecptr srca = m68k_getpc () + 2;
61563: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
61564: if ((srca & 1) != 0) {
61565: last_fault_for_exception_3 = srca;
61566: last_op_for_exception_3 = opcode;
61567: last_addr_for_exception_3 = m68k_getpc() + 4;
61568: Exception(3, 0, M68000_EXC_SRC_CPU);
61569: goto endlabel3422;
61570: }
61571: {{ uae_s16 src = get_word(srca);
61572: { uae_s32 dst = m68k_areg(regs, dstreg);
61573: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61574: { int flgs = ((uae_s32)(src)) < 0;
61575: int flgo = ((uae_s32)(dst)) < 0;
61576: int flgn = ((uae_s32)(newv)) < 0;
61577: SET_ZFLG (((uae_s32)(newv)) == 0);
61578: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61579: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61580: SET_NFLG (flgn != 0);
61581: }}}}}}}}m68k_incpc(4);
61582: fill_prefetch_0 ();
61583: endlabel3422: ;
61584: return 14;
61585: }
61586: unsigned long REGPARAM2 CPUFUNC(op_b0fb_5)(uae_u32 opcode) /* CMPA */
61587: {
61588: uae_u32 dstreg = (opcode >> 9) & 7;
61589: OpcodeFamily = 27; CurrentInstrCycles = 16;
61590: {{ uaecptr tmppc = m68k_getpc() + 2;
61591: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
61592: BusCyclePenalty += 2;
61593: if ((srca & 1) != 0) {
61594: last_fault_for_exception_3 = srca;
61595: last_op_for_exception_3 = opcode;
61596: last_addr_for_exception_3 = m68k_getpc() + 4;
61597: Exception(3, 0, M68000_EXC_SRC_CPU);
61598: goto endlabel3423;
61599: }
61600: {{ uae_s16 src = get_word(srca);
61601: { uae_s32 dst = m68k_areg(regs, dstreg);
61602: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61603: { int flgs = ((uae_s32)(src)) < 0;
61604: int flgo = ((uae_s32)(dst)) < 0;
61605: int flgn = ((uae_s32)(newv)) < 0;
61606: SET_ZFLG (((uae_s32)(newv)) == 0);
61607: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61608: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61609: SET_NFLG (flgn != 0);
61610: }}}}}}}}m68k_incpc(4);
61611: fill_prefetch_0 ();
61612: endlabel3423: ;
61613: return 16;
61614: }
61615: unsigned long REGPARAM2 CPUFUNC(op_b0fc_5)(uae_u32 opcode) /* CMPA */
61616: {
61617: uae_u32 dstreg = (opcode >> 9) & 7;
61618: OpcodeFamily = 27; CurrentInstrCycles = 10;
61619: {{ uae_s16 src = get_iword_prefetch(2);
61620: { uae_s32 dst = m68k_areg(regs, dstreg);
61621: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
61622: { int flgs = ((uae_s32)(src)) < 0;
61623: int flgo = ((uae_s32)(dst)) < 0;
61624: int flgn = ((uae_s32)(newv)) < 0;
61625: SET_ZFLG (((uae_s32)(newv)) == 0);
61626: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61627: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
61628: SET_NFLG (flgn != 0);
61629: }}}}}}m68k_incpc(4);
61630: fill_prefetch_0 ();
61631: return 10;
61632: }
61633: unsigned long REGPARAM2 CPUFUNC(op_b100_5)(uae_u32 opcode) /* EOR */
61634: {
61635: uae_u32 srcreg = ((opcode >> 9) & 7);
61636: uae_u32 dstreg = opcode & 7;
61637: OpcodeFamily = 3; CurrentInstrCycles = 4;
61638: {{ uae_s8 src = m68k_dreg(regs, srcreg);
61639: { uae_s8 dst = m68k_dreg(regs, dstreg);
61640: src ^= dst;
61641: CLEAR_CZNV;
61642: SET_ZFLG (((uae_s8)(src)) == 0);
61643: SET_NFLG (((uae_s8)(src)) < 0);
61644: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
61645: }}}m68k_incpc(2);
61646: fill_prefetch_2 ();
61647: return 4;
61648: }
61649: unsigned long REGPARAM2 CPUFUNC(op_b108_5)(uae_u32 opcode) /* CMPM */
61650: {
61651: uae_u32 srcreg = (opcode & 7);
61652: uae_u32 dstreg = (opcode >> 9) & 7;
61653: OpcodeFamily = 26; CurrentInstrCycles = 12;
61654: {{ uaecptr srca = m68k_areg(regs, srcreg);
61655: { uae_s8 src = get_byte(srca);
61656: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
61657: { uaecptr dsta = m68k_areg(regs, dstreg);
61658: { uae_s8 dst = get_byte(dsta);
61659: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
61660: {{uae_u32 newv = ((uae_s8)(dst)) - ((uae_s8)(src));
61661: { int flgs = ((uae_s8)(src)) < 0;
61662: int flgo = ((uae_s8)(dst)) < 0;
61663: int flgn = ((uae_s8)(newv)) < 0;
61664: SET_ZFLG (((uae_s8)(newv)) == 0);
61665: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61666: SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
61667: SET_NFLG (flgn != 0);
61668: }}}}}}}}m68k_incpc(2);
61669: fill_prefetch_2 ();
61670: return 12;
61671: }
61672: unsigned long REGPARAM2 CPUFUNC(op_b110_5)(uae_u32 opcode) /* EOR */
61673: {
61674: uae_u32 srcreg = ((opcode >> 9) & 7);
61675: uae_u32 dstreg = opcode & 7;
61676: OpcodeFamily = 3; CurrentInstrCycles = 12;
61677: {{ uae_s8 src = m68k_dreg(regs, srcreg);
61678: { uaecptr dsta = m68k_areg(regs, dstreg);
61679: { uae_s8 dst = get_byte(dsta);
61680: src ^= dst;
61681: CLEAR_CZNV;
61682: SET_ZFLG (((uae_s8)(src)) == 0);
61683: SET_NFLG (((uae_s8)(src)) < 0);
61684: m68k_incpc(2);
61685: fill_prefetch_2 ();
61686: put_byte(dsta,src);
61687: }}}}return 12;
61688: }
61689: unsigned long REGPARAM2 CPUFUNC(op_b118_5)(uae_u32 opcode) /* EOR */
61690: {
61691: uae_u32 srcreg = ((opcode >> 9) & 7);
61692: uae_u32 dstreg = opcode & 7;
61693: OpcodeFamily = 3; CurrentInstrCycles = 12;
61694: {{ uae_s8 src = m68k_dreg(regs, srcreg);
61695: { uaecptr dsta = m68k_areg(regs, dstreg);
61696: { uae_s8 dst = get_byte(dsta);
61697: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
61698: src ^= dst;
61699: CLEAR_CZNV;
61700: SET_ZFLG (((uae_s8)(src)) == 0);
61701: SET_NFLG (((uae_s8)(src)) < 0);
61702: m68k_incpc(2);
61703: fill_prefetch_2 ();
61704: put_byte(dsta,src);
61705: }}}}return 12;
61706: }
61707: unsigned long REGPARAM2 CPUFUNC(op_b120_5)(uae_u32 opcode) /* EOR */
61708: {
61709: uae_u32 srcreg = ((opcode >> 9) & 7);
61710: uae_u32 dstreg = opcode & 7;
61711: OpcodeFamily = 3; CurrentInstrCycles = 14;
61712: {{ uae_s8 src = m68k_dreg(regs, srcreg);
61713: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
61714: { uae_s8 dst = get_byte(dsta);
61715: m68k_areg (regs, dstreg) = dsta;
61716: src ^= dst;
61717: CLEAR_CZNV;
61718: SET_ZFLG (((uae_s8)(src)) == 0);
61719: SET_NFLG (((uae_s8)(src)) < 0);
61720: m68k_incpc(2);
61721: fill_prefetch_2 ();
61722: put_byte(dsta,src);
61723: }}}}return 14;
61724: }
61725: unsigned long REGPARAM2 CPUFUNC(op_b128_5)(uae_u32 opcode) /* EOR */
61726: {
61727: uae_u32 srcreg = ((opcode >> 9) & 7);
61728: uae_u32 dstreg = opcode & 7;
61729: OpcodeFamily = 3; CurrentInstrCycles = 16;
61730: {{ uae_s8 src = m68k_dreg(regs, srcreg);
61731: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
61732: { uae_s8 dst = get_byte(dsta);
61733: src ^= dst;
61734: CLEAR_CZNV;
61735: SET_ZFLG (((uae_s8)(src)) == 0);
61736: SET_NFLG (((uae_s8)(src)) < 0);
61737: m68k_incpc(4);
61738: fill_prefetch_0 ();
61739: put_byte(dsta,src);
61740: }}}}return 16;
61741: }
61742: unsigned long REGPARAM2 CPUFUNC(op_b130_5)(uae_u32 opcode) /* EOR */
61743: {
61744: uae_u32 srcreg = ((opcode >> 9) & 7);
61745: uae_u32 dstreg = opcode & 7;
61746: OpcodeFamily = 3; CurrentInstrCycles = 18;
61747: {{ uae_s8 src = m68k_dreg(regs, srcreg);
61748: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
61749: BusCyclePenalty += 2;
61750: { uae_s8 dst = get_byte(dsta);
61751: src ^= dst;
61752: CLEAR_CZNV;
61753: SET_ZFLG (((uae_s8)(src)) == 0);
61754: SET_NFLG (((uae_s8)(src)) < 0);
61755: m68k_incpc(4);
61756: fill_prefetch_0 ();
61757: put_byte(dsta,src);
61758: }}}}return 18;
61759: }
61760: unsigned long REGPARAM2 CPUFUNC(op_b138_5)(uae_u32 opcode) /* EOR */
61761: {
61762: uae_u32 srcreg = ((opcode >> 9) & 7);
61763: OpcodeFamily = 3; CurrentInstrCycles = 16;
61764: {{ uae_s8 src = m68k_dreg(regs, srcreg);
61765: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
61766: { uae_s8 dst = get_byte(dsta);
61767: src ^= dst;
61768: CLEAR_CZNV;
61769: SET_ZFLG (((uae_s8)(src)) == 0);
61770: SET_NFLG (((uae_s8)(src)) < 0);
61771: m68k_incpc(4);
61772: fill_prefetch_0 ();
61773: put_byte(dsta,src);
61774: }}}}return 16;
61775: }
61776: unsigned long REGPARAM2 CPUFUNC(op_b139_5)(uae_u32 opcode) /* EOR */
61777: {
61778: uae_u32 srcreg = ((opcode >> 9) & 7);
61779: OpcodeFamily = 3; CurrentInstrCycles = 20;
61780: {{ uae_s8 src = m68k_dreg(regs, srcreg);
61781: { uaecptr dsta = get_ilong_prefetch(2);
61782: { uae_s8 dst = get_byte(dsta);
61783: src ^= dst;
61784: CLEAR_CZNV;
61785: SET_ZFLG (((uae_s8)(src)) == 0);
61786: SET_NFLG (((uae_s8)(src)) < 0);
61787: m68k_incpc(6);
61788: fill_prefetch_0 ();
61789: put_byte(dsta,src);
61790: }}}}return 20;
61791: }
61792: unsigned long REGPARAM2 CPUFUNC(op_b140_5)(uae_u32 opcode) /* EOR */
61793: {
61794: uae_u32 srcreg = ((opcode >> 9) & 7);
61795: uae_u32 dstreg = opcode & 7;
61796: OpcodeFamily = 3; CurrentInstrCycles = 4;
61797: {{ uae_s16 src = m68k_dreg(regs, srcreg);
61798: { uae_s16 dst = m68k_dreg(regs, dstreg);
61799: src ^= dst;
61800: CLEAR_CZNV;
61801: SET_ZFLG (((uae_s16)(src)) == 0);
61802: SET_NFLG (((uae_s16)(src)) < 0);
61803: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
61804: }}}m68k_incpc(2);
61805: fill_prefetch_2 ();
61806: return 4;
61807: }
61808: unsigned long REGPARAM2 CPUFUNC(op_b148_5)(uae_u32 opcode) /* CMPM */
61809: {
61810: uae_u32 srcreg = (opcode & 7);
61811: uae_u32 dstreg = (opcode >> 9) & 7;
61812: OpcodeFamily = 26; CurrentInstrCycles = 12;
61813: {{ uaecptr srca = m68k_areg(regs, srcreg);
61814: if ((srca & 1) != 0) {
61815: last_fault_for_exception_3 = srca;
61816: last_op_for_exception_3 = opcode;
61817: last_addr_for_exception_3 = m68k_getpc() + 2;
61818: Exception(3, 0, M68000_EXC_SRC_CPU);
61819: goto endlabel3435;
61820: }
61821: {{ uae_s16 src = get_word(srca);
61822: m68k_areg(regs, srcreg) += 2;
61823: { uaecptr dsta = m68k_areg(regs, dstreg);
61824: if ((dsta & 1) != 0) {
61825: last_fault_for_exception_3 = dsta;
61826: last_op_for_exception_3 = opcode;
61827: last_addr_for_exception_3 = m68k_getpc() + 2;
61828: Exception(3, 0, M68000_EXC_SRC_CPU);
61829: goto endlabel3435;
61830: }
61831: {{ uae_s16 dst = get_word(dsta);
61832: m68k_areg(regs, dstreg) += 2;
61833: {{uae_u32 newv = ((uae_s16)(dst)) - ((uae_s16)(src));
61834: { int flgs = ((uae_s16)(src)) < 0;
61835: int flgo = ((uae_s16)(dst)) < 0;
61836: int flgn = ((uae_s16)(newv)) < 0;
61837: SET_ZFLG (((uae_s16)(newv)) == 0);
61838: SET_VFLG ((flgs != flgo) && (flgn != flgo));
61839: SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
61840: SET_NFLG (flgn != 0);
61841: }}}}}}}}}}m68k_incpc(2);
61842: fill_prefetch_2 ();
61843: endlabel3435: ;
61844: return 12;
61845: }
61846: unsigned long REGPARAM2 CPUFUNC(op_b150_5)(uae_u32 opcode) /* EOR */
61847: {
61848: uae_u32 srcreg = ((opcode >> 9) & 7);
61849: uae_u32 dstreg = opcode & 7;
61850: OpcodeFamily = 3; CurrentInstrCycles = 12;
61851: {{ uae_s16 src = m68k_dreg(regs, srcreg);
61852: { uaecptr dsta = m68k_areg(regs, dstreg);
61853: if ((dsta & 1) != 0) {
61854: last_fault_for_exception_3 = dsta;
61855: last_op_for_exception_3 = opcode;
61856: last_addr_for_exception_3 = m68k_getpc() + 2;
61857: Exception(3, 0, M68000_EXC_SRC_CPU);
61858: goto endlabel3436;
61859: }
61860: {{ uae_s16 dst = get_word(dsta);
61861: src ^= dst;
61862: CLEAR_CZNV;
61863: SET_ZFLG (((uae_s16)(src)) == 0);
61864: SET_NFLG (((uae_s16)(src)) < 0);
61865: m68k_incpc(2);
61866: fill_prefetch_2 ();
61867: put_word(dsta,src);
61868: }}}}}endlabel3436: ;
61869: return 12;
61870: }
61871: unsigned long REGPARAM2 CPUFUNC(op_b158_5)(uae_u32 opcode) /* EOR */
61872: {
61873: uae_u32 srcreg = ((opcode >> 9) & 7);
61874: uae_u32 dstreg = opcode & 7;
61875: OpcodeFamily = 3; CurrentInstrCycles = 12;
61876: {{ uae_s16 src = m68k_dreg(regs, srcreg);
61877: { uaecptr dsta = m68k_areg(regs, dstreg);
61878: if ((dsta & 1) != 0) {
61879: last_fault_for_exception_3 = dsta;
61880: last_op_for_exception_3 = opcode;
61881: last_addr_for_exception_3 = m68k_getpc() + 2;
61882: Exception(3, 0, M68000_EXC_SRC_CPU);
61883: goto endlabel3437;
61884: }
61885: {{ uae_s16 dst = get_word(dsta);
61886: m68k_areg(regs, dstreg) += 2;
61887: src ^= dst;
61888: CLEAR_CZNV;
61889: SET_ZFLG (((uae_s16)(src)) == 0);
61890: SET_NFLG (((uae_s16)(src)) < 0);
61891: m68k_incpc(2);
61892: fill_prefetch_2 ();
61893: put_word(dsta,src);
61894: }}}}}endlabel3437: ;
61895: return 12;
61896: }
61897: unsigned long REGPARAM2 CPUFUNC(op_b160_5)(uae_u32 opcode) /* EOR */
61898: {
61899: uae_u32 srcreg = ((opcode >> 9) & 7);
61900: uae_u32 dstreg = opcode & 7;
61901: OpcodeFamily = 3; CurrentInstrCycles = 14;
61902: {{ uae_s16 src = m68k_dreg(regs, srcreg);
61903: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
61904: if ((dsta & 1) != 0) {
61905: last_fault_for_exception_3 = dsta;
61906: last_op_for_exception_3 = opcode;
61907: last_addr_for_exception_3 = m68k_getpc() + 2;
61908: Exception(3, 0, M68000_EXC_SRC_CPU);
61909: goto endlabel3438;
61910: }
61911: {{ uae_s16 dst = get_word(dsta);
61912: m68k_areg (regs, dstreg) = dsta;
61913: src ^= dst;
61914: CLEAR_CZNV;
61915: SET_ZFLG (((uae_s16)(src)) == 0);
61916: SET_NFLG (((uae_s16)(src)) < 0);
61917: m68k_incpc(2);
61918: fill_prefetch_2 ();
61919: put_word(dsta,src);
61920: }}}}}endlabel3438: ;
61921: return 14;
61922: }
61923: unsigned long REGPARAM2 CPUFUNC(op_b168_5)(uae_u32 opcode) /* EOR */
61924: {
61925: uae_u32 srcreg = ((opcode >> 9) & 7);
61926: uae_u32 dstreg = opcode & 7;
61927: OpcodeFamily = 3; CurrentInstrCycles = 16;
61928: {{ uae_s16 src = m68k_dreg(regs, srcreg);
61929: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
61930: if ((dsta & 1) != 0) {
61931: last_fault_for_exception_3 = dsta;
61932: last_op_for_exception_3 = opcode;
61933: last_addr_for_exception_3 = m68k_getpc() + 4;
61934: Exception(3, 0, M68000_EXC_SRC_CPU);
61935: goto endlabel3439;
61936: }
61937: {{ uae_s16 dst = get_word(dsta);
61938: src ^= dst;
61939: CLEAR_CZNV;
61940: SET_ZFLG (((uae_s16)(src)) == 0);
61941: SET_NFLG (((uae_s16)(src)) < 0);
61942: m68k_incpc(4);
61943: fill_prefetch_0 ();
61944: put_word(dsta,src);
61945: }}}}}endlabel3439: ;
61946: return 16;
61947: }
61948: unsigned long REGPARAM2 CPUFUNC(op_b170_5)(uae_u32 opcode) /* EOR */
61949: {
61950: uae_u32 srcreg = ((opcode >> 9) & 7);
61951: uae_u32 dstreg = opcode & 7;
61952: OpcodeFamily = 3; CurrentInstrCycles = 18;
61953: {{ uae_s16 src = m68k_dreg(regs, srcreg);
61954: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
61955: BusCyclePenalty += 2;
61956: if ((dsta & 1) != 0) {
61957: last_fault_for_exception_3 = dsta;
61958: last_op_for_exception_3 = opcode;
61959: last_addr_for_exception_3 = m68k_getpc() + 4;
61960: Exception(3, 0, M68000_EXC_SRC_CPU);
61961: goto endlabel3440;
61962: }
61963: {{ uae_s16 dst = get_word(dsta);
61964: src ^= dst;
61965: CLEAR_CZNV;
61966: SET_ZFLG (((uae_s16)(src)) == 0);
61967: SET_NFLG (((uae_s16)(src)) < 0);
61968: m68k_incpc(4);
61969: fill_prefetch_0 ();
61970: put_word(dsta,src);
61971: }}}}}endlabel3440: ;
61972: return 18;
61973: }
61974: unsigned long REGPARAM2 CPUFUNC(op_b178_5)(uae_u32 opcode) /* EOR */
61975: {
61976: uae_u32 srcreg = ((opcode >> 9) & 7);
61977: OpcodeFamily = 3; CurrentInstrCycles = 16;
61978: {{ uae_s16 src = m68k_dreg(regs, srcreg);
61979: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
61980: if ((dsta & 1) != 0) {
61981: last_fault_for_exception_3 = dsta;
61982: last_op_for_exception_3 = opcode;
61983: last_addr_for_exception_3 = m68k_getpc() + 4;
61984: Exception(3, 0, M68000_EXC_SRC_CPU);
61985: goto endlabel3441;
61986: }
61987: {{ uae_s16 dst = get_word(dsta);
61988: src ^= dst;
61989: CLEAR_CZNV;
61990: SET_ZFLG (((uae_s16)(src)) == 0);
61991: SET_NFLG (((uae_s16)(src)) < 0);
61992: m68k_incpc(4);
61993: fill_prefetch_0 ();
61994: put_word(dsta,src);
61995: }}}}}endlabel3441: ;
61996: return 16;
61997: }
61998: unsigned long REGPARAM2 CPUFUNC(op_b179_5)(uae_u32 opcode) /* EOR */
61999: {
62000: uae_u32 srcreg = ((opcode >> 9) & 7);
62001: OpcodeFamily = 3; CurrentInstrCycles = 20;
62002: {{ uae_s16 src = m68k_dreg(regs, srcreg);
62003: { uaecptr dsta = get_ilong_prefetch(2);
62004: if ((dsta & 1) != 0) {
62005: last_fault_for_exception_3 = dsta;
62006: last_op_for_exception_3 = opcode;
62007: last_addr_for_exception_3 = m68k_getpc() + 6;
62008: Exception(3, 0, M68000_EXC_SRC_CPU);
62009: goto endlabel3442;
62010: }
62011: {{ uae_s16 dst = get_word(dsta);
62012: src ^= dst;
62013: CLEAR_CZNV;
62014: SET_ZFLG (((uae_s16)(src)) == 0);
62015: SET_NFLG (((uae_s16)(src)) < 0);
62016: m68k_incpc(6);
62017: fill_prefetch_0 ();
62018: put_word(dsta,src);
62019: }}}}}endlabel3442: ;
62020: return 20;
62021: }
62022: unsigned long REGPARAM2 CPUFUNC(op_b180_5)(uae_u32 opcode) /* EOR */
62023: {
62024: uae_u32 srcreg = ((opcode >> 9) & 7);
62025: uae_u32 dstreg = opcode & 7;
62026: OpcodeFamily = 3; CurrentInstrCycles = 8;
62027: {{ uae_s32 src = m68k_dreg(regs, srcreg);
62028: { uae_s32 dst = m68k_dreg(regs, dstreg);
62029: src ^= dst;
62030: CLEAR_CZNV;
62031: SET_ZFLG (((uae_s32)(src)) == 0);
62032: SET_NFLG (((uae_s32)(src)) < 0);
62033: m68k_dreg(regs, dstreg) = (src);
62034: }}}m68k_incpc(2);
62035: fill_prefetch_2 ();
62036: return 8;
62037: }
62038: unsigned long REGPARAM2 CPUFUNC(op_b188_5)(uae_u32 opcode) /* CMPM */
62039: {
62040: uae_u32 srcreg = (opcode & 7);
62041: uae_u32 dstreg = (opcode >> 9) & 7;
62042: OpcodeFamily = 26; CurrentInstrCycles = 20;
62043: {{ uaecptr srca = m68k_areg(regs, srcreg);
62044: if ((srca & 1) != 0) {
62045: last_fault_for_exception_3 = srca;
62046: last_op_for_exception_3 = opcode;
62047: last_addr_for_exception_3 = m68k_getpc() + 2;
62048: Exception(3, 0, M68000_EXC_SRC_CPU);
62049: goto endlabel3444;
62050: }
62051: {{ uae_s32 src = get_long(srca);
62052: m68k_areg(regs, srcreg) += 4;
62053: { uaecptr dsta = m68k_areg(regs, dstreg);
62054: if ((dsta & 1) != 0) {
62055: last_fault_for_exception_3 = dsta;
62056: last_op_for_exception_3 = opcode;
62057: last_addr_for_exception_3 = m68k_getpc() + 2;
62058: Exception(3, 0, M68000_EXC_SRC_CPU);
62059: goto endlabel3444;
62060: }
62061: {{ uae_s32 dst = get_long(dsta);
62062: m68k_areg(regs, dstreg) += 4;
62063: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62064: { int flgs = ((uae_s32)(src)) < 0;
62065: int flgo = ((uae_s32)(dst)) < 0;
62066: int flgn = ((uae_s32)(newv)) < 0;
62067: SET_ZFLG (((uae_s32)(newv)) == 0);
62068: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62069: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62070: SET_NFLG (flgn != 0);
62071: }}}}}}}}}}m68k_incpc(2);
62072: fill_prefetch_2 ();
62073: endlabel3444: ;
62074: return 20;
62075: }
62076: unsigned long REGPARAM2 CPUFUNC(op_b190_5)(uae_u32 opcode) /* EOR */
62077: {
62078: uae_u32 srcreg = ((opcode >> 9) & 7);
62079: uae_u32 dstreg = opcode & 7;
62080: OpcodeFamily = 3; CurrentInstrCycles = 20;
62081: {{ uae_s32 src = m68k_dreg(regs, srcreg);
62082: { uaecptr dsta = m68k_areg(regs, dstreg);
62083: if ((dsta & 1) != 0) {
62084: last_fault_for_exception_3 = dsta;
62085: last_op_for_exception_3 = opcode;
62086: last_addr_for_exception_3 = m68k_getpc() + 2;
62087: Exception(3, 0, M68000_EXC_SRC_CPU);
62088: goto endlabel3445;
62089: }
62090: {{ uae_s32 dst = get_long(dsta);
62091: src ^= dst;
62092: CLEAR_CZNV;
62093: SET_ZFLG (((uae_s32)(src)) == 0);
62094: SET_NFLG (((uae_s32)(src)) < 0);
62095: m68k_incpc(2);
62096: fill_prefetch_2 ();
62097: put_long(dsta,src);
62098: }}}}}endlabel3445: ;
62099: return 20;
62100: }
62101: unsigned long REGPARAM2 CPUFUNC(op_b198_5)(uae_u32 opcode) /* EOR */
62102: {
62103: uae_u32 srcreg = ((opcode >> 9) & 7);
62104: uae_u32 dstreg = opcode & 7;
62105: OpcodeFamily = 3; CurrentInstrCycles = 20;
62106: {{ uae_s32 src = m68k_dreg(regs, srcreg);
62107: { uaecptr dsta = m68k_areg(regs, dstreg);
62108: if ((dsta & 1) != 0) {
62109: last_fault_for_exception_3 = dsta;
62110: last_op_for_exception_3 = opcode;
62111: last_addr_for_exception_3 = m68k_getpc() + 2;
62112: Exception(3, 0, M68000_EXC_SRC_CPU);
62113: goto endlabel3446;
62114: }
62115: {{ uae_s32 dst = get_long(dsta);
62116: m68k_areg(regs, dstreg) += 4;
62117: src ^= dst;
62118: CLEAR_CZNV;
62119: SET_ZFLG (((uae_s32)(src)) == 0);
62120: SET_NFLG (((uae_s32)(src)) < 0);
62121: m68k_incpc(2);
62122: fill_prefetch_2 ();
62123: put_long(dsta,src);
62124: }}}}}endlabel3446: ;
62125: return 20;
62126: }
62127: unsigned long REGPARAM2 CPUFUNC(op_b1a0_5)(uae_u32 opcode) /* EOR */
62128: {
62129: uae_u32 srcreg = ((opcode >> 9) & 7);
62130: uae_u32 dstreg = opcode & 7;
62131: OpcodeFamily = 3; CurrentInstrCycles = 22;
62132: {{ uae_s32 src = m68k_dreg(regs, srcreg);
62133: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
62134: if ((dsta & 1) != 0) {
62135: last_fault_for_exception_3 = dsta;
62136: last_op_for_exception_3 = opcode;
62137: last_addr_for_exception_3 = m68k_getpc() + 2;
62138: Exception(3, 0, M68000_EXC_SRC_CPU);
62139: goto endlabel3447;
62140: }
62141: {{ uae_s32 dst = get_long(dsta);
62142: m68k_areg (regs, dstreg) = dsta;
62143: src ^= dst;
62144: CLEAR_CZNV;
62145: SET_ZFLG (((uae_s32)(src)) == 0);
62146: SET_NFLG (((uae_s32)(src)) < 0);
62147: m68k_incpc(2);
62148: fill_prefetch_2 ();
62149: put_long(dsta,src);
62150: }}}}}endlabel3447: ;
62151: return 22;
62152: }
62153: unsigned long REGPARAM2 CPUFUNC(op_b1a8_5)(uae_u32 opcode) /* EOR */
62154: {
62155: uae_u32 srcreg = ((opcode >> 9) & 7);
62156: uae_u32 dstreg = opcode & 7;
62157: OpcodeFamily = 3; CurrentInstrCycles = 24;
62158: {{ uae_s32 src = m68k_dreg(regs, srcreg);
62159: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
62160: if ((dsta & 1) != 0) {
62161: last_fault_for_exception_3 = dsta;
62162: last_op_for_exception_3 = opcode;
62163: last_addr_for_exception_3 = m68k_getpc() + 4;
62164: Exception(3, 0, M68000_EXC_SRC_CPU);
62165: goto endlabel3448;
62166: }
62167: {{ uae_s32 dst = get_long(dsta);
62168: src ^= dst;
62169: CLEAR_CZNV;
62170: SET_ZFLG (((uae_s32)(src)) == 0);
62171: SET_NFLG (((uae_s32)(src)) < 0);
62172: m68k_incpc(4);
62173: fill_prefetch_0 ();
62174: put_long(dsta,src);
62175: }}}}}endlabel3448: ;
62176: return 24;
62177: }
62178: unsigned long REGPARAM2 CPUFUNC(op_b1b0_5)(uae_u32 opcode) /* EOR */
62179: {
62180: uae_u32 srcreg = ((opcode >> 9) & 7);
62181: uae_u32 dstreg = opcode & 7;
62182: OpcodeFamily = 3; CurrentInstrCycles = 26;
62183: {{ uae_s32 src = m68k_dreg(regs, srcreg);
62184: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
62185: BusCyclePenalty += 2;
62186: if ((dsta & 1) != 0) {
62187: last_fault_for_exception_3 = dsta;
62188: last_op_for_exception_3 = opcode;
62189: last_addr_for_exception_3 = m68k_getpc() + 4;
62190: Exception(3, 0, M68000_EXC_SRC_CPU);
62191: goto endlabel3449;
62192: }
62193: {{ uae_s32 dst = get_long(dsta);
62194: src ^= dst;
62195: CLEAR_CZNV;
62196: SET_ZFLG (((uae_s32)(src)) == 0);
62197: SET_NFLG (((uae_s32)(src)) < 0);
62198: m68k_incpc(4);
62199: fill_prefetch_0 ();
62200: put_long(dsta,src);
62201: }}}}}endlabel3449: ;
62202: return 26;
62203: }
62204: unsigned long REGPARAM2 CPUFUNC(op_b1b8_5)(uae_u32 opcode) /* EOR */
62205: {
62206: uae_u32 srcreg = ((opcode >> 9) & 7);
62207: OpcodeFamily = 3; CurrentInstrCycles = 24;
62208: {{ uae_s32 src = m68k_dreg(regs, srcreg);
62209: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
62210: if ((dsta & 1) != 0) {
62211: last_fault_for_exception_3 = dsta;
62212: last_op_for_exception_3 = opcode;
62213: last_addr_for_exception_3 = m68k_getpc() + 4;
62214: Exception(3, 0, M68000_EXC_SRC_CPU);
62215: goto endlabel3450;
62216: }
62217: {{ uae_s32 dst = get_long(dsta);
62218: src ^= dst;
62219: CLEAR_CZNV;
62220: SET_ZFLG (((uae_s32)(src)) == 0);
62221: SET_NFLG (((uae_s32)(src)) < 0);
62222: m68k_incpc(4);
62223: fill_prefetch_0 ();
62224: put_long(dsta,src);
62225: }}}}}endlabel3450: ;
62226: return 24;
62227: }
62228: unsigned long REGPARAM2 CPUFUNC(op_b1b9_5)(uae_u32 opcode) /* EOR */
62229: {
62230: uae_u32 srcreg = ((opcode >> 9) & 7);
62231: OpcodeFamily = 3; CurrentInstrCycles = 28;
62232: {{ uae_s32 src = m68k_dreg(regs, srcreg);
62233: { uaecptr dsta = get_ilong_prefetch(2);
62234: if ((dsta & 1) != 0) {
62235: last_fault_for_exception_3 = dsta;
62236: last_op_for_exception_3 = opcode;
62237: last_addr_for_exception_3 = m68k_getpc() + 6;
62238: Exception(3, 0, M68000_EXC_SRC_CPU);
62239: goto endlabel3451;
62240: }
62241: {{ uae_s32 dst = get_long(dsta);
62242: src ^= dst;
62243: CLEAR_CZNV;
62244: SET_ZFLG (((uae_s32)(src)) == 0);
62245: SET_NFLG (((uae_s32)(src)) < 0);
62246: m68k_incpc(6);
62247: fill_prefetch_0 ();
62248: put_long(dsta,src);
62249: }}}}}endlabel3451: ;
62250: return 28;
62251: }
62252: unsigned long REGPARAM2 CPUFUNC(op_b1c0_5)(uae_u32 opcode) /* CMPA */
62253: {
62254: uae_u32 srcreg = (opcode & 7);
62255: uae_u32 dstreg = (opcode >> 9) & 7;
62256: OpcodeFamily = 27; CurrentInstrCycles = 6;
62257: {{ uae_s32 src = m68k_dreg(regs, srcreg);
62258: { uae_s32 dst = m68k_areg(regs, dstreg);
62259: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62260: { int flgs = ((uae_s32)(src)) < 0;
62261: int flgo = ((uae_s32)(dst)) < 0;
62262: int flgn = ((uae_s32)(newv)) < 0;
62263: SET_ZFLG (((uae_s32)(newv)) == 0);
62264: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62265: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62266: SET_NFLG (flgn != 0);
62267: }}}}}}m68k_incpc(2);
62268: fill_prefetch_2 ();
62269: return 6;
62270: }
62271: unsigned long REGPARAM2 CPUFUNC(op_b1c8_5)(uae_u32 opcode) /* CMPA */
62272: {
62273: uae_u32 srcreg = (opcode & 7);
62274: uae_u32 dstreg = (opcode >> 9) & 7;
62275: OpcodeFamily = 27; CurrentInstrCycles = 6;
62276: {{ uae_s32 src = m68k_areg(regs, srcreg);
62277: { uae_s32 dst = m68k_areg(regs, dstreg);
62278: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62279: { int flgs = ((uae_s32)(src)) < 0;
62280: int flgo = ((uae_s32)(dst)) < 0;
62281: int flgn = ((uae_s32)(newv)) < 0;
62282: SET_ZFLG (((uae_s32)(newv)) == 0);
62283: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62284: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62285: SET_NFLG (flgn != 0);
62286: }}}}}}m68k_incpc(2);
62287: fill_prefetch_2 ();
62288: return 6;
62289: }
62290: unsigned long REGPARAM2 CPUFUNC(op_b1d0_5)(uae_u32 opcode) /* CMPA */
62291: {
62292: uae_u32 srcreg = (opcode & 7);
62293: uae_u32 dstreg = (opcode >> 9) & 7;
62294: OpcodeFamily = 27; CurrentInstrCycles = 14;
62295: {{ uaecptr srca = m68k_areg(regs, srcreg);
62296: if ((srca & 1) != 0) {
62297: last_fault_for_exception_3 = srca;
62298: last_op_for_exception_3 = opcode;
62299: last_addr_for_exception_3 = m68k_getpc() + 2;
62300: Exception(3, 0, M68000_EXC_SRC_CPU);
62301: goto endlabel3454;
62302: }
62303: {{ uae_s32 src = get_long(srca);
62304: { uae_s32 dst = m68k_areg(regs, dstreg);
62305: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62306: { int flgs = ((uae_s32)(src)) < 0;
62307: int flgo = ((uae_s32)(dst)) < 0;
62308: int flgn = ((uae_s32)(newv)) < 0;
62309: SET_ZFLG (((uae_s32)(newv)) == 0);
62310: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62311: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62312: SET_NFLG (flgn != 0);
62313: }}}}}}}}m68k_incpc(2);
62314: fill_prefetch_2 ();
62315: endlabel3454: ;
62316: return 14;
62317: }
62318: unsigned long REGPARAM2 CPUFUNC(op_b1d8_5)(uae_u32 opcode) /* CMPA */
62319: {
62320: uae_u32 srcreg = (opcode & 7);
62321: uae_u32 dstreg = (opcode >> 9) & 7;
62322: OpcodeFamily = 27; CurrentInstrCycles = 14;
62323: {{ uaecptr srca = m68k_areg(regs, srcreg);
62324: if ((srca & 1) != 0) {
62325: last_fault_for_exception_3 = srca;
62326: last_op_for_exception_3 = opcode;
62327: last_addr_for_exception_3 = m68k_getpc() + 2;
62328: Exception(3, 0, M68000_EXC_SRC_CPU);
62329: goto endlabel3455;
62330: }
62331: {{ uae_s32 src = get_long(srca);
62332: m68k_areg(regs, srcreg) += 4;
62333: { uae_s32 dst = m68k_areg(regs, dstreg);
62334: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62335: { int flgs = ((uae_s32)(src)) < 0;
62336: int flgo = ((uae_s32)(dst)) < 0;
62337: int flgn = ((uae_s32)(newv)) < 0;
62338: SET_ZFLG (((uae_s32)(newv)) == 0);
62339: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62340: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62341: SET_NFLG (flgn != 0);
62342: }}}}}}}}m68k_incpc(2);
62343: fill_prefetch_2 ();
62344: endlabel3455: ;
62345: return 14;
62346: }
62347: unsigned long REGPARAM2 CPUFUNC(op_b1e0_5)(uae_u32 opcode) /* CMPA */
62348: {
62349: uae_u32 srcreg = (opcode & 7);
62350: uae_u32 dstreg = (opcode >> 9) & 7;
62351: OpcodeFamily = 27; CurrentInstrCycles = 16;
62352: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
62353: if ((srca & 1) != 0) {
62354: last_fault_for_exception_3 = srca;
62355: last_op_for_exception_3 = opcode;
62356: last_addr_for_exception_3 = m68k_getpc() + 2;
62357: Exception(3, 0, M68000_EXC_SRC_CPU);
62358: goto endlabel3456;
62359: }
62360: {{ uae_s32 src = get_long(srca);
62361: m68k_areg (regs, srcreg) = srca;
62362: { uae_s32 dst = m68k_areg(regs, dstreg);
62363: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62364: { int flgs = ((uae_s32)(src)) < 0;
62365: int flgo = ((uae_s32)(dst)) < 0;
62366: int flgn = ((uae_s32)(newv)) < 0;
62367: SET_ZFLG (((uae_s32)(newv)) == 0);
62368: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62369: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62370: SET_NFLG (flgn != 0);
62371: }}}}}}}}m68k_incpc(2);
62372: fill_prefetch_2 ();
62373: endlabel3456: ;
62374: return 16;
62375: }
62376: unsigned long REGPARAM2 CPUFUNC(op_b1e8_5)(uae_u32 opcode) /* CMPA */
62377: {
62378: uae_u32 srcreg = (opcode & 7);
62379: uae_u32 dstreg = (opcode >> 9) & 7;
62380: OpcodeFamily = 27; CurrentInstrCycles = 18;
62381: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
62382: if ((srca & 1) != 0) {
62383: last_fault_for_exception_3 = srca;
62384: last_op_for_exception_3 = opcode;
62385: last_addr_for_exception_3 = m68k_getpc() + 4;
62386: Exception(3, 0, M68000_EXC_SRC_CPU);
62387: goto endlabel3457;
62388: }
62389: {{ uae_s32 src = get_long(srca);
62390: { uae_s32 dst = m68k_areg(regs, dstreg);
62391: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62392: { int flgs = ((uae_s32)(src)) < 0;
62393: int flgo = ((uae_s32)(dst)) < 0;
62394: int flgn = ((uae_s32)(newv)) < 0;
62395: SET_ZFLG (((uae_s32)(newv)) == 0);
62396: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62397: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62398: SET_NFLG (flgn != 0);
62399: }}}}}}}}m68k_incpc(4);
62400: fill_prefetch_0 ();
62401: endlabel3457: ;
62402: return 18;
62403: }
62404: unsigned long REGPARAM2 CPUFUNC(op_b1f0_5)(uae_u32 opcode) /* CMPA */
62405: {
62406: uae_u32 srcreg = (opcode & 7);
62407: uae_u32 dstreg = (opcode >> 9) & 7;
62408: OpcodeFamily = 27; CurrentInstrCycles = 20;
62409: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
62410: BusCyclePenalty += 2;
62411: if ((srca & 1) != 0) {
62412: last_fault_for_exception_3 = srca;
62413: last_op_for_exception_3 = opcode;
62414: last_addr_for_exception_3 = m68k_getpc() + 4;
62415: Exception(3, 0, M68000_EXC_SRC_CPU);
62416: goto endlabel3458;
62417: }
62418: {{ uae_s32 src = get_long(srca);
62419: { uae_s32 dst = m68k_areg(regs, dstreg);
62420: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62421: { int flgs = ((uae_s32)(src)) < 0;
62422: int flgo = ((uae_s32)(dst)) < 0;
62423: int flgn = ((uae_s32)(newv)) < 0;
62424: SET_ZFLG (((uae_s32)(newv)) == 0);
62425: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62426: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62427: SET_NFLG (flgn != 0);
62428: }}}}}}}}m68k_incpc(4);
62429: fill_prefetch_0 ();
62430: endlabel3458: ;
62431: return 20;
62432: }
62433: unsigned long REGPARAM2 CPUFUNC(op_b1f8_5)(uae_u32 opcode) /* CMPA */
62434: {
62435: uae_u32 dstreg = (opcode >> 9) & 7;
62436: OpcodeFamily = 27; CurrentInstrCycles = 18;
62437: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
62438: if ((srca & 1) != 0) {
62439: last_fault_for_exception_3 = srca;
62440: last_op_for_exception_3 = opcode;
62441: last_addr_for_exception_3 = m68k_getpc() + 4;
62442: Exception(3, 0, M68000_EXC_SRC_CPU);
62443: goto endlabel3459;
62444: }
62445: {{ uae_s32 src = get_long(srca);
62446: { uae_s32 dst = m68k_areg(regs, dstreg);
62447: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62448: { int flgs = ((uae_s32)(src)) < 0;
62449: int flgo = ((uae_s32)(dst)) < 0;
62450: int flgn = ((uae_s32)(newv)) < 0;
62451: SET_ZFLG (((uae_s32)(newv)) == 0);
62452: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62453: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62454: SET_NFLG (flgn != 0);
62455: }}}}}}}}m68k_incpc(4);
62456: fill_prefetch_0 ();
62457: endlabel3459: ;
62458: return 18;
62459: }
62460: unsigned long REGPARAM2 CPUFUNC(op_b1f9_5)(uae_u32 opcode) /* CMPA */
62461: {
62462: uae_u32 dstreg = (opcode >> 9) & 7;
62463: OpcodeFamily = 27; CurrentInstrCycles = 22;
62464: {{ uaecptr srca = get_ilong_prefetch(2);
62465: if ((srca & 1) != 0) {
62466: last_fault_for_exception_3 = srca;
62467: last_op_for_exception_3 = opcode;
62468: last_addr_for_exception_3 = m68k_getpc() + 6;
62469: Exception(3, 0, M68000_EXC_SRC_CPU);
62470: goto endlabel3460;
62471: }
62472: {{ uae_s32 src = get_long(srca);
62473: { uae_s32 dst = m68k_areg(regs, dstreg);
62474: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62475: { int flgs = ((uae_s32)(src)) < 0;
62476: int flgo = ((uae_s32)(dst)) < 0;
62477: int flgn = ((uae_s32)(newv)) < 0;
62478: SET_ZFLG (((uae_s32)(newv)) == 0);
62479: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62480: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62481: SET_NFLG (flgn != 0);
62482: }}}}}}}}m68k_incpc(6);
62483: fill_prefetch_0 ();
62484: endlabel3460: ;
62485: return 22;
62486: }
62487: unsigned long REGPARAM2 CPUFUNC(op_b1fa_5)(uae_u32 opcode) /* CMPA */
62488: {
62489: uae_u32 dstreg = (opcode >> 9) & 7;
62490: OpcodeFamily = 27; CurrentInstrCycles = 18;
62491: {{ uaecptr srca = m68k_getpc () + 2;
62492: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
62493: if ((srca & 1) != 0) {
62494: last_fault_for_exception_3 = srca;
62495: last_op_for_exception_3 = opcode;
62496: last_addr_for_exception_3 = m68k_getpc() + 4;
62497: Exception(3, 0, M68000_EXC_SRC_CPU);
62498: goto endlabel3461;
62499: }
62500: {{ uae_s32 src = get_long(srca);
62501: { uae_s32 dst = m68k_areg(regs, dstreg);
62502: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62503: { int flgs = ((uae_s32)(src)) < 0;
62504: int flgo = ((uae_s32)(dst)) < 0;
62505: int flgn = ((uae_s32)(newv)) < 0;
62506: SET_ZFLG (((uae_s32)(newv)) == 0);
62507: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62508: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62509: SET_NFLG (flgn != 0);
62510: }}}}}}}}m68k_incpc(4);
62511: fill_prefetch_0 ();
62512: endlabel3461: ;
62513: return 18;
62514: }
62515: unsigned long REGPARAM2 CPUFUNC(op_b1fb_5)(uae_u32 opcode) /* CMPA */
62516: {
62517: uae_u32 dstreg = (opcode >> 9) & 7;
62518: OpcodeFamily = 27; CurrentInstrCycles = 20;
62519: {{ uaecptr tmppc = m68k_getpc() + 2;
62520: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
62521: BusCyclePenalty += 2;
62522: if ((srca & 1) != 0) {
62523: last_fault_for_exception_3 = srca;
62524: last_op_for_exception_3 = opcode;
62525: last_addr_for_exception_3 = m68k_getpc() + 4;
62526: Exception(3, 0, M68000_EXC_SRC_CPU);
62527: goto endlabel3462;
62528: }
62529: {{ uae_s32 src = get_long(srca);
62530: { uae_s32 dst = m68k_areg(regs, dstreg);
62531: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62532: { int flgs = ((uae_s32)(src)) < 0;
62533: int flgo = ((uae_s32)(dst)) < 0;
62534: int flgn = ((uae_s32)(newv)) < 0;
62535: SET_ZFLG (((uae_s32)(newv)) == 0);
62536: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62537: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62538: SET_NFLG (flgn != 0);
62539: }}}}}}}}m68k_incpc(4);
62540: fill_prefetch_0 ();
62541: endlabel3462: ;
62542: return 20;
62543: }
62544: unsigned long REGPARAM2 CPUFUNC(op_b1fc_5)(uae_u32 opcode) /* CMPA */
62545: {
62546: uae_u32 dstreg = (opcode >> 9) & 7;
62547: OpcodeFamily = 27; CurrentInstrCycles = 14;
62548: {{ uae_s32 src = get_ilong_prefetch(2);
62549: { uae_s32 dst = m68k_areg(regs, dstreg);
62550: {{uae_u32 newv = ((uae_s32)(dst)) - ((uae_s32)(src));
62551: { int flgs = ((uae_s32)(src)) < 0;
62552: int flgo = ((uae_s32)(dst)) < 0;
62553: int flgn = ((uae_s32)(newv)) < 0;
62554: SET_ZFLG (((uae_s32)(newv)) == 0);
62555: SET_VFLG ((flgs != flgo) && (flgn != flgo));
62556: SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
62557: SET_NFLG (flgn != 0);
62558: }}}}}}m68k_incpc(6);
62559: fill_prefetch_0 ();
62560: return 14;
62561: }
62562: unsigned long REGPARAM2 CPUFUNC(op_c000_5)(uae_u32 opcode) /* AND */
62563: {
62564: uae_u32 srcreg = (opcode & 7);
62565: uae_u32 dstreg = (opcode >> 9) & 7;
62566: OpcodeFamily = 2; CurrentInstrCycles = 4;
62567: {{ uae_s8 src = m68k_dreg(regs, srcreg);
62568: { uae_s8 dst = m68k_dreg(regs, dstreg);
62569: src &= dst;
62570: CLEAR_CZNV;
62571: SET_ZFLG (((uae_s8)(src)) == 0);
62572: SET_NFLG (((uae_s8)(src)) < 0);
62573: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62574: }}}m68k_incpc(2);
62575: fill_prefetch_2 ();
62576: return 4;
62577: }
62578: unsigned long REGPARAM2 CPUFUNC(op_c010_5)(uae_u32 opcode) /* AND */
62579: {
62580: uae_u32 srcreg = (opcode & 7);
62581: uae_u32 dstreg = (opcode >> 9) & 7;
62582: OpcodeFamily = 2; CurrentInstrCycles = 8;
62583: {{ uaecptr srca = m68k_areg(regs, srcreg);
62584: { uae_s8 src = get_byte(srca);
62585: { uae_s8 dst = m68k_dreg(regs, dstreg);
62586: src &= dst;
62587: CLEAR_CZNV;
62588: SET_ZFLG (((uae_s8)(src)) == 0);
62589: SET_NFLG (((uae_s8)(src)) < 0);
62590: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62591: }}}}m68k_incpc(2);
62592: fill_prefetch_2 ();
62593: return 8;
62594: }
62595: unsigned long REGPARAM2 CPUFUNC(op_c018_5)(uae_u32 opcode) /* AND */
62596: {
62597: uae_u32 srcreg = (opcode & 7);
62598: uae_u32 dstreg = (opcode >> 9) & 7;
62599: OpcodeFamily = 2; CurrentInstrCycles = 8;
62600: {{ uaecptr srca = m68k_areg(regs, srcreg);
62601: { uae_s8 src = get_byte(srca);
62602: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
62603: { uae_s8 dst = m68k_dreg(regs, dstreg);
62604: src &= dst;
62605: CLEAR_CZNV;
62606: SET_ZFLG (((uae_s8)(src)) == 0);
62607: SET_NFLG (((uae_s8)(src)) < 0);
62608: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62609: }}}}m68k_incpc(2);
62610: fill_prefetch_2 ();
62611: return 8;
62612: }
62613: unsigned long REGPARAM2 CPUFUNC(op_c020_5)(uae_u32 opcode) /* AND */
62614: {
62615: uae_u32 srcreg = (opcode & 7);
62616: uae_u32 dstreg = (opcode >> 9) & 7;
62617: OpcodeFamily = 2; CurrentInstrCycles = 10;
62618: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
62619: { uae_s8 src = get_byte(srca);
62620: m68k_areg (regs, srcreg) = srca;
62621: { uae_s8 dst = m68k_dreg(regs, dstreg);
62622: src &= dst;
62623: CLEAR_CZNV;
62624: SET_ZFLG (((uae_s8)(src)) == 0);
62625: SET_NFLG (((uae_s8)(src)) < 0);
62626: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62627: }}}}m68k_incpc(2);
62628: fill_prefetch_2 ();
62629: return 10;
62630: }
62631: unsigned long REGPARAM2 CPUFUNC(op_c028_5)(uae_u32 opcode) /* AND */
62632: {
62633: uae_u32 srcreg = (opcode & 7);
62634: uae_u32 dstreg = (opcode >> 9) & 7;
62635: OpcodeFamily = 2; CurrentInstrCycles = 12;
62636: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
62637: { uae_s8 src = get_byte(srca);
62638: { uae_s8 dst = m68k_dreg(regs, dstreg);
62639: src &= dst;
62640: CLEAR_CZNV;
62641: SET_ZFLG (((uae_s8)(src)) == 0);
62642: SET_NFLG (((uae_s8)(src)) < 0);
62643: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62644: }}}}m68k_incpc(4);
62645: fill_prefetch_0 ();
62646: return 12;
62647: }
62648: unsigned long REGPARAM2 CPUFUNC(op_c030_5)(uae_u32 opcode) /* AND */
62649: {
62650: uae_u32 srcreg = (opcode & 7);
62651: uae_u32 dstreg = (opcode >> 9) & 7;
62652: OpcodeFamily = 2; CurrentInstrCycles = 14;
62653: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
62654: BusCyclePenalty += 2;
62655: { uae_s8 src = get_byte(srca);
62656: { uae_s8 dst = m68k_dreg(regs, dstreg);
62657: src &= dst;
62658: CLEAR_CZNV;
62659: SET_ZFLG (((uae_s8)(src)) == 0);
62660: SET_NFLG (((uae_s8)(src)) < 0);
62661: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62662: }}}}m68k_incpc(4);
62663: fill_prefetch_0 ();
62664: return 14;
62665: }
62666: unsigned long REGPARAM2 CPUFUNC(op_c038_5)(uae_u32 opcode) /* AND */
62667: {
62668: uae_u32 dstreg = (opcode >> 9) & 7;
62669: OpcodeFamily = 2; CurrentInstrCycles = 12;
62670: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
62671: { uae_s8 src = get_byte(srca);
62672: { uae_s8 dst = m68k_dreg(regs, dstreg);
62673: src &= dst;
62674: CLEAR_CZNV;
62675: SET_ZFLG (((uae_s8)(src)) == 0);
62676: SET_NFLG (((uae_s8)(src)) < 0);
62677: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62678: }}}}m68k_incpc(4);
62679: fill_prefetch_0 ();
62680: return 12;
62681: }
62682: unsigned long REGPARAM2 CPUFUNC(op_c039_5)(uae_u32 opcode) /* AND */
62683: {
62684: uae_u32 dstreg = (opcode >> 9) & 7;
62685: OpcodeFamily = 2; CurrentInstrCycles = 16;
62686: {{ uaecptr srca = get_ilong_prefetch(2);
62687: { uae_s8 src = get_byte(srca);
62688: { uae_s8 dst = m68k_dreg(regs, dstreg);
62689: src &= dst;
62690: CLEAR_CZNV;
62691: SET_ZFLG (((uae_s8)(src)) == 0);
62692: SET_NFLG (((uae_s8)(src)) < 0);
62693: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62694: }}}}m68k_incpc(6);
62695: fill_prefetch_0 ();
62696: return 16;
62697: }
62698: unsigned long REGPARAM2 CPUFUNC(op_c03a_5)(uae_u32 opcode) /* AND */
62699: {
62700: uae_u32 dstreg = (opcode >> 9) & 7;
62701: OpcodeFamily = 2; CurrentInstrCycles = 12;
62702: {{ uaecptr srca = m68k_getpc () + 2;
62703: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
62704: { uae_s8 src = get_byte(srca);
62705: { uae_s8 dst = m68k_dreg(regs, dstreg);
62706: src &= dst;
62707: CLEAR_CZNV;
62708: SET_ZFLG (((uae_s8)(src)) == 0);
62709: SET_NFLG (((uae_s8)(src)) < 0);
62710: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62711: }}}}m68k_incpc(4);
62712: fill_prefetch_0 ();
62713: return 12;
62714: }
62715: unsigned long REGPARAM2 CPUFUNC(op_c03b_5)(uae_u32 opcode) /* AND */
62716: {
62717: uae_u32 dstreg = (opcode >> 9) & 7;
62718: OpcodeFamily = 2; CurrentInstrCycles = 14;
62719: {{ uaecptr tmppc = m68k_getpc() + 2;
62720: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
62721: BusCyclePenalty += 2;
62722: { uae_s8 src = get_byte(srca);
62723: { uae_s8 dst = m68k_dreg(regs, dstreg);
62724: src &= dst;
62725: CLEAR_CZNV;
62726: SET_ZFLG (((uae_s8)(src)) == 0);
62727: SET_NFLG (((uae_s8)(src)) < 0);
62728: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62729: }}}}m68k_incpc(4);
62730: fill_prefetch_0 ();
62731: return 14;
62732: }
62733: unsigned long REGPARAM2 CPUFUNC(op_c03c_5)(uae_u32 opcode) /* AND */
62734: {
62735: uae_u32 dstreg = (opcode >> 9) & 7;
62736: OpcodeFamily = 2; CurrentInstrCycles = 8;
62737: {{ uae_s8 src = get_ibyte_prefetch(2);
62738: { uae_s8 dst = m68k_dreg(regs, dstreg);
62739: src &= dst;
62740: CLEAR_CZNV;
62741: SET_ZFLG (((uae_s8)(src)) == 0);
62742: SET_NFLG (((uae_s8)(src)) < 0);
62743: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
62744: }}}m68k_incpc(4);
62745: fill_prefetch_0 ();
62746: return 8;
62747: }
62748: unsigned long REGPARAM2 CPUFUNC(op_c040_5)(uae_u32 opcode) /* AND */
62749: {
62750: uae_u32 srcreg = (opcode & 7);
62751: uae_u32 dstreg = (opcode >> 9) & 7;
62752: OpcodeFamily = 2; CurrentInstrCycles = 4;
62753: {{ uae_s16 src = m68k_dreg(regs, srcreg);
62754: { uae_s16 dst = m68k_dreg(regs, dstreg);
62755: src &= dst;
62756: CLEAR_CZNV;
62757: SET_ZFLG (((uae_s16)(src)) == 0);
62758: SET_NFLG (((uae_s16)(src)) < 0);
62759: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62760: }}}m68k_incpc(2);
62761: fill_prefetch_2 ();
62762: return 4;
62763: }
62764: unsigned long REGPARAM2 CPUFUNC(op_c050_5)(uae_u32 opcode) /* AND */
62765: {
62766: uae_u32 srcreg = (opcode & 7);
62767: uae_u32 dstreg = (opcode >> 9) & 7;
62768: OpcodeFamily = 2; CurrentInstrCycles = 8;
62769: {{ uaecptr srca = m68k_areg(regs, srcreg);
62770: if ((srca & 1) != 0) {
62771: last_fault_for_exception_3 = srca;
62772: last_op_for_exception_3 = opcode;
62773: last_addr_for_exception_3 = m68k_getpc() + 2;
62774: Exception(3, 0, M68000_EXC_SRC_CPU);
62775: goto endlabel3476;
62776: }
62777: {{ uae_s16 src = get_word(srca);
62778: { uae_s16 dst = m68k_dreg(regs, dstreg);
62779: src &= dst;
62780: CLEAR_CZNV;
62781: SET_ZFLG (((uae_s16)(src)) == 0);
62782: SET_NFLG (((uae_s16)(src)) < 0);
62783: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62784: }}}}}m68k_incpc(2);
62785: fill_prefetch_2 ();
62786: endlabel3476: ;
62787: return 8;
62788: }
62789: unsigned long REGPARAM2 CPUFUNC(op_c058_5)(uae_u32 opcode) /* AND */
62790: {
62791: uae_u32 srcreg = (opcode & 7);
62792: uae_u32 dstreg = (opcode >> 9) & 7;
62793: OpcodeFamily = 2; CurrentInstrCycles = 8;
62794: {{ uaecptr srca = m68k_areg(regs, srcreg);
62795: if ((srca & 1) != 0) {
62796: last_fault_for_exception_3 = srca;
62797: last_op_for_exception_3 = opcode;
62798: last_addr_for_exception_3 = m68k_getpc() + 2;
62799: Exception(3, 0, M68000_EXC_SRC_CPU);
62800: goto endlabel3477;
62801: }
62802: {{ uae_s16 src = get_word(srca);
62803: m68k_areg(regs, srcreg) += 2;
62804: { uae_s16 dst = m68k_dreg(regs, dstreg);
62805: src &= dst;
62806: CLEAR_CZNV;
62807: SET_ZFLG (((uae_s16)(src)) == 0);
62808: SET_NFLG (((uae_s16)(src)) < 0);
62809: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62810: }}}}}m68k_incpc(2);
62811: fill_prefetch_2 ();
62812: endlabel3477: ;
62813: return 8;
62814: }
62815: unsigned long REGPARAM2 CPUFUNC(op_c060_5)(uae_u32 opcode) /* AND */
62816: {
62817: uae_u32 srcreg = (opcode & 7);
62818: uae_u32 dstreg = (opcode >> 9) & 7;
62819: OpcodeFamily = 2; CurrentInstrCycles = 10;
62820: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
62821: if ((srca & 1) != 0) {
62822: last_fault_for_exception_3 = srca;
62823: last_op_for_exception_3 = opcode;
62824: last_addr_for_exception_3 = m68k_getpc() + 2;
62825: Exception(3, 0, M68000_EXC_SRC_CPU);
62826: goto endlabel3478;
62827: }
62828: {{ uae_s16 src = get_word(srca);
62829: m68k_areg (regs, srcreg) = srca;
62830: { uae_s16 dst = m68k_dreg(regs, dstreg);
62831: src &= dst;
62832: CLEAR_CZNV;
62833: SET_ZFLG (((uae_s16)(src)) == 0);
62834: SET_NFLG (((uae_s16)(src)) < 0);
62835: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62836: }}}}}m68k_incpc(2);
62837: fill_prefetch_2 ();
62838: endlabel3478: ;
62839: return 10;
62840: }
62841: unsigned long REGPARAM2 CPUFUNC(op_c068_5)(uae_u32 opcode) /* AND */
62842: {
62843: uae_u32 srcreg = (opcode & 7);
62844: uae_u32 dstreg = (opcode >> 9) & 7;
62845: OpcodeFamily = 2; CurrentInstrCycles = 12;
62846: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
62847: if ((srca & 1) != 0) {
62848: last_fault_for_exception_3 = srca;
62849: last_op_for_exception_3 = opcode;
62850: last_addr_for_exception_3 = m68k_getpc() + 4;
62851: Exception(3, 0, M68000_EXC_SRC_CPU);
62852: goto endlabel3479;
62853: }
62854: {{ uae_s16 src = get_word(srca);
62855: { uae_s16 dst = m68k_dreg(regs, dstreg);
62856: src &= dst;
62857: CLEAR_CZNV;
62858: SET_ZFLG (((uae_s16)(src)) == 0);
62859: SET_NFLG (((uae_s16)(src)) < 0);
62860: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62861: }}}}}m68k_incpc(4);
62862: fill_prefetch_0 ();
62863: endlabel3479: ;
62864: return 12;
62865: }
62866: unsigned long REGPARAM2 CPUFUNC(op_c070_5)(uae_u32 opcode) /* AND */
62867: {
62868: uae_u32 srcreg = (opcode & 7);
62869: uae_u32 dstreg = (opcode >> 9) & 7;
62870: OpcodeFamily = 2; CurrentInstrCycles = 14;
62871: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
62872: BusCyclePenalty += 2;
62873: if ((srca & 1) != 0) {
62874: last_fault_for_exception_3 = srca;
62875: last_op_for_exception_3 = opcode;
62876: last_addr_for_exception_3 = m68k_getpc() + 4;
62877: Exception(3, 0, M68000_EXC_SRC_CPU);
62878: goto endlabel3480;
62879: }
62880: {{ uae_s16 src = get_word(srca);
62881: { uae_s16 dst = m68k_dreg(regs, dstreg);
62882: src &= dst;
62883: CLEAR_CZNV;
62884: SET_ZFLG (((uae_s16)(src)) == 0);
62885: SET_NFLG (((uae_s16)(src)) < 0);
62886: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62887: }}}}}m68k_incpc(4);
62888: fill_prefetch_0 ();
62889: endlabel3480: ;
62890: return 14;
62891: }
62892: unsigned long REGPARAM2 CPUFUNC(op_c078_5)(uae_u32 opcode) /* AND */
62893: {
62894: uae_u32 dstreg = (opcode >> 9) & 7;
62895: OpcodeFamily = 2; CurrentInstrCycles = 12;
62896: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
62897: if ((srca & 1) != 0) {
62898: last_fault_for_exception_3 = srca;
62899: last_op_for_exception_3 = opcode;
62900: last_addr_for_exception_3 = m68k_getpc() + 4;
62901: Exception(3, 0, M68000_EXC_SRC_CPU);
62902: goto endlabel3481;
62903: }
62904: {{ uae_s16 src = get_word(srca);
62905: { uae_s16 dst = m68k_dreg(regs, dstreg);
62906: src &= dst;
62907: CLEAR_CZNV;
62908: SET_ZFLG (((uae_s16)(src)) == 0);
62909: SET_NFLG (((uae_s16)(src)) < 0);
62910: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62911: }}}}}m68k_incpc(4);
62912: fill_prefetch_0 ();
62913: endlabel3481: ;
62914: return 12;
62915: }
62916: unsigned long REGPARAM2 CPUFUNC(op_c079_5)(uae_u32 opcode) /* AND */
62917: {
62918: uae_u32 dstreg = (opcode >> 9) & 7;
62919: OpcodeFamily = 2; CurrentInstrCycles = 16;
62920: {{ uaecptr srca = get_ilong_prefetch(2);
62921: if ((srca & 1) != 0) {
62922: last_fault_for_exception_3 = srca;
62923: last_op_for_exception_3 = opcode;
62924: last_addr_for_exception_3 = m68k_getpc() + 6;
62925: Exception(3, 0, M68000_EXC_SRC_CPU);
62926: goto endlabel3482;
62927: }
62928: {{ uae_s16 src = get_word(srca);
62929: { uae_s16 dst = m68k_dreg(regs, dstreg);
62930: src &= dst;
62931: CLEAR_CZNV;
62932: SET_ZFLG (((uae_s16)(src)) == 0);
62933: SET_NFLG (((uae_s16)(src)) < 0);
62934: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62935: }}}}}m68k_incpc(6);
62936: fill_prefetch_0 ();
62937: endlabel3482: ;
62938: return 16;
62939: }
62940: unsigned long REGPARAM2 CPUFUNC(op_c07a_5)(uae_u32 opcode) /* AND */
62941: {
62942: uae_u32 dstreg = (opcode >> 9) & 7;
62943: OpcodeFamily = 2; CurrentInstrCycles = 12;
62944: {{ uaecptr srca = m68k_getpc () + 2;
62945: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
62946: if ((srca & 1) != 0) {
62947: last_fault_for_exception_3 = srca;
62948: last_op_for_exception_3 = opcode;
62949: last_addr_for_exception_3 = m68k_getpc() + 4;
62950: Exception(3, 0, M68000_EXC_SRC_CPU);
62951: goto endlabel3483;
62952: }
62953: {{ uae_s16 src = get_word(srca);
62954: { uae_s16 dst = m68k_dreg(regs, dstreg);
62955: src &= dst;
62956: CLEAR_CZNV;
62957: SET_ZFLG (((uae_s16)(src)) == 0);
62958: SET_NFLG (((uae_s16)(src)) < 0);
62959: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62960: }}}}}m68k_incpc(4);
62961: fill_prefetch_0 ();
62962: endlabel3483: ;
62963: return 12;
62964: }
62965: unsigned long REGPARAM2 CPUFUNC(op_c07b_5)(uae_u32 opcode) /* AND */
62966: {
62967: uae_u32 dstreg = (opcode >> 9) & 7;
62968: OpcodeFamily = 2; CurrentInstrCycles = 14;
62969: {{ uaecptr tmppc = m68k_getpc() + 2;
62970: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
62971: BusCyclePenalty += 2;
62972: if ((srca & 1) != 0) {
62973: last_fault_for_exception_3 = srca;
62974: last_op_for_exception_3 = opcode;
62975: last_addr_for_exception_3 = m68k_getpc() + 4;
62976: Exception(3, 0, M68000_EXC_SRC_CPU);
62977: goto endlabel3484;
62978: }
62979: {{ uae_s16 src = get_word(srca);
62980: { uae_s16 dst = m68k_dreg(regs, dstreg);
62981: src &= dst;
62982: CLEAR_CZNV;
62983: SET_ZFLG (((uae_s16)(src)) == 0);
62984: SET_NFLG (((uae_s16)(src)) < 0);
62985: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
62986: }}}}}m68k_incpc(4);
62987: fill_prefetch_0 ();
62988: endlabel3484: ;
62989: return 14;
62990: }
62991: unsigned long REGPARAM2 CPUFUNC(op_c07c_5)(uae_u32 opcode) /* AND */
62992: {
62993: uae_u32 dstreg = (opcode >> 9) & 7;
62994: OpcodeFamily = 2; CurrentInstrCycles = 8;
62995: {{ uae_s16 src = get_iword_prefetch(2);
62996: { uae_s16 dst = m68k_dreg(regs, dstreg);
62997: src &= dst;
62998: CLEAR_CZNV;
62999: SET_ZFLG (((uae_s16)(src)) == 0);
63000: SET_NFLG (((uae_s16)(src)) < 0);
63001: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
63002: }}}m68k_incpc(4);
63003: fill_prefetch_0 ();
63004: return 8;
63005: }
63006: unsigned long REGPARAM2 CPUFUNC(op_c080_5)(uae_u32 opcode) /* AND */
63007: {
63008: uae_u32 srcreg = (opcode & 7);
63009: uae_u32 dstreg = (opcode >> 9) & 7;
63010: OpcodeFamily = 2; CurrentInstrCycles = 8;
63011: {{ uae_s32 src = m68k_dreg(regs, srcreg);
63012: { uae_s32 dst = m68k_dreg(regs, dstreg);
63013: src &= dst;
63014: CLEAR_CZNV;
63015: SET_ZFLG (((uae_s32)(src)) == 0);
63016: SET_NFLG (((uae_s32)(src)) < 0);
63017: m68k_dreg(regs, dstreg) = (src);
63018: }}}m68k_incpc(2);
63019: fill_prefetch_2 ();
63020: return 8;
63021: }
63022: unsigned long REGPARAM2 CPUFUNC(op_c090_5)(uae_u32 opcode) /* AND */
63023: {
63024: uae_u32 srcreg = (opcode & 7);
63025: uae_u32 dstreg = (opcode >> 9) & 7;
63026: OpcodeFamily = 2; CurrentInstrCycles = 14;
63027: {{ uaecptr srca = m68k_areg(regs, srcreg);
63028: if ((srca & 1) != 0) {
63029: last_fault_for_exception_3 = srca;
63030: last_op_for_exception_3 = opcode;
63031: last_addr_for_exception_3 = m68k_getpc() + 2;
63032: Exception(3, 0, M68000_EXC_SRC_CPU);
63033: goto endlabel3487;
63034: }
63035: {{ uae_s32 src = get_long(srca);
63036: { uae_s32 dst = m68k_dreg(regs, dstreg);
63037: src &= dst;
63038: CLEAR_CZNV;
63039: SET_ZFLG (((uae_s32)(src)) == 0);
63040: SET_NFLG (((uae_s32)(src)) < 0);
63041: m68k_dreg(regs, dstreg) = (src);
63042: }}}}}m68k_incpc(2);
63043: fill_prefetch_2 ();
63044: endlabel3487: ;
63045: return 14;
63046: }
63047: unsigned long REGPARAM2 CPUFUNC(op_c098_5)(uae_u32 opcode) /* AND */
63048: {
63049: uae_u32 srcreg = (opcode & 7);
63050: uae_u32 dstreg = (opcode >> 9) & 7;
63051: OpcodeFamily = 2; CurrentInstrCycles = 14;
63052: {{ uaecptr srca = m68k_areg(regs, srcreg);
63053: if ((srca & 1) != 0) {
63054: last_fault_for_exception_3 = srca;
63055: last_op_for_exception_3 = opcode;
63056: last_addr_for_exception_3 = m68k_getpc() + 2;
63057: Exception(3, 0, M68000_EXC_SRC_CPU);
63058: goto endlabel3488;
63059: }
63060: {{ uae_s32 src = get_long(srca);
63061: m68k_areg(regs, srcreg) += 4;
63062: { uae_s32 dst = m68k_dreg(regs, dstreg);
63063: src &= dst;
63064: CLEAR_CZNV;
63065: SET_ZFLG (((uae_s32)(src)) == 0);
63066: SET_NFLG (((uae_s32)(src)) < 0);
63067: m68k_dreg(regs, dstreg) = (src);
63068: }}}}}m68k_incpc(2);
63069: fill_prefetch_2 ();
63070: endlabel3488: ;
63071: return 14;
63072: }
63073: unsigned long REGPARAM2 CPUFUNC(op_c0a0_5)(uae_u32 opcode) /* AND */
63074: {
63075: uae_u32 srcreg = (opcode & 7);
63076: uae_u32 dstreg = (opcode >> 9) & 7;
63077: OpcodeFamily = 2; CurrentInstrCycles = 16;
63078: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
63079: if ((srca & 1) != 0) {
63080: last_fault_for_exception_3 = srca;
63081: last_op_for_exception_3 = opcode;
63082: last_addr_for_exception_3 = m68k_getpc() + 2;
63083: Exception(3, 0, M68000_EXC_SRC_CPU);
63084: goto endlabel3489;
63085: }
63086: {{ uae_s32 src = get_long(srca);
63087: m68k_areg (regs, srcreg) = srca;
63088: { uae_s32 dst = m68k_dreg(regs, dstreg);
63089: src &= dst;
63090: CLEAR_CZNV;
63091: SET_ZFLG (((uae_s32)(src)) == 0);
63092: SET_NFLG (((uae_s32)(src)) < 0);
63093: m68k_dreg(regs, dstreg) = (src);
63094: }}}}}m68k_incpc(2);
63095: fill_prefetch_2 ();
63096: endlabel3489: ;
63097: return 16;
63098: }
63099: unsigned long REGPARAM2 CPUFUNC(op_c0a8_5)(uae_u32 opcode) /* AND */
63100: {
63101: uae_u32 srcreg = (opcode & 7);
63102: uae_u32 dstreg = (opcode >> 9) & 7;
63103: OpcodeFamily = 2; CurrentInstrCycles = 18;
63104: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
63105: if ((srca & 1) != 0) {
63106: last_fault_for_exception_3 = srca;
63107: last_op_for_exception_3 = opcode;
63108: last_addr_for_exception_3 = m68k_getpc() + 4;
63109: Exception(3, 0, M68000_EXC_SRC_CPU);
63110: goto endlabel3490;
63111: }
63112: {{ uae_s32 src = get_long(srca);
63113: { uae_s32 dst = m68k_dreg(regs, dstreg);
63114: src &= dst;
63115: CLEAR_CZNV;
63116: SET_ZFLG (((uae_s32)(src)) == 0);
63117: SET_NFLG (((uae_s32)(src)) < 0);
63118: m68k_dreg(regs, dstreg) = (src);
63119: }}}}}m68k_incpc(4);
63120: fill_prefetch_0 ();
63121: endlabel3490: ;
63122: return 18;
63123: }
63124: unsigned long REGPARAM2 CPUFUNC(op_c0b0_5)(uae_u32 opcode) /* AND */
63125: {
63126: uae_u32 srcreg = (opcode & 7);
63127: uae_u32 dstreg = (opcode >> 9) & 7;
63128: OpcodeFamily = 2; CurrentInstrCycles = 20;
63129: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
63130: BusCyclePenalty += 2;
63131: if ((srca & 1) != 0) {
63132: last_fault_for_exception_3 = srca;
63133: last_op_for_exception_3 = opcode;
63134: last_addr_for_exception_3 = m68k_getpc() + 4;
63135: Exception(3, 0, M68000_EXC_SRC_CPU);
63136: goto endlabel3491;
63137: }
63138: {{ uae_s32 src = get_long(srca);
63139: { uae_s32 dst = m68k_dreg(regs, dstreg);
63140: src &= dst;
63141: CLEAR_CZNV;
63142: SET_ZFLG (((uae_s32)(src)) == 0);
63143: SET_NFLG (((uae_s32)(src)) < 0);
63144: m68k_dreg(regs, dstreg) = (src);
63145: }}}}}m68k_incpc(4);
63146: fill_prefetch_0 ();
63147: endlabel3491: ;
63148: return 20;
63149: }
63150: unsigned long REGPARAM2 CPUFUNC(op_c0b8_5)(uae_u32 opcode) /* AND */
63151: {
63152: uae_u32 dstreg = (opcode >> 9) & 7;
63153: OpcodeFamily = 2; CurrentInstrCycles = 18;
63154: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
63155: if ((srca & 1) != 0) {
63156: last_fault_for_exception_3 = srca;
63157: last_op_for_exception_3 = opcode;
63158: last_addr_for_exception_3 = m68k_getpc() + 4;
63159: Exception(3, 0, M68000_EXC_SRC_CPU);
63160: goto endlabel3492;
63161: }
63162: {{ uae_s32 src = get_long(srca);
63163: { uae_s32 dst = m68k_dreg(regs, dstreg);
63164: src &= dst;
63165: CLEAR_CZNV;
63166: SET_ZFLG (((uae_s32)(src)) == 0);
63167: SET_NFLG (((uae_s32)(src)) < 0);
63168: m68k_dreg(regs, dstreg) = (src);
63169: }}}}}m68k_incpc(4);
63170: fill_prefetch_0 ();
63171: endlabel3492: ;
63172: return 18;
63173: }
63174: unsigned long REGPARAM2 CPUFUNC(op_c0b9_5)(uae_u32 opcode) /* AND */
63175: {
63176: uae_u32 dstreg = (opcode >> 9) & 7;
63177: OpcodeFamily = 2; CurrentInstrCycles = 22;
63178: {{ uaecptr srca = get_ilong_prefetch(2);
63179: if ((srca & 1) != 0) {
63180: last_fault_for_exception_3 = srca;
63181: last_op_for_exception_3 = opcode;
63182: last_addr_for_exception_3 = m68k_getpc() + 6;
63183: Exception(3, 0, M68000_EXC_SRC_CPU);
63184: goto endlabel3493;
63185: }
63186: {{ uae_s32 src = get_long(srca);
63187: { uae_s32 dst = m68k_dreg(regs, dstreg);
63188: src &= dst;
63189: CLEAR_CZNV;
63190: SET_ZFLG (((uae_s32)(src)) == 0);
63191: SET_NFLG (((uae_s32)(src)) < 0);
63192: m68k_dreg(regs, dstreg) = (src);
63193: }}}}}m68k_incpc(6);
63194: fill_prefetch_0 ();
63195: endlabel3493: ;
63196: return 22;
63197: }
63198: unsigned long REGPARAM2 CPUFUNC(op_c0ba_5)(uae_u32 opcode) /* AND */
63199: {
63200: uae_u32 dstreg = (opcode >> 9) & 7;
63201: OpcodeFamily = 2; CurrentInstrCycles = 18;
63202: {{ uaecptr srca = m68k_getpc () + 2;
63203: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
63204: if ((srca & 1) != 0) {
63205: last_fault_for_exception_3 = srca;
63206: last_op_for_exception_3 = opcode;
63207: last_addr_for_exception_3 = m68k_getpc() + 4;
63208: Exception(3, 0, M68000_EXC_SRC_CPU);
63209: goto endlabel3494;
63210: }
63211: {{ uae_s32 src = get_long(srca);
63212: { uae_s32 dst = m68k_dreg(regs, dstreg);
63213: src &= dst;
63214: CLEAR_CZNV;
63215: SET_ZFLG (((uae_s32)(src)) == 0);
63216: SET_NFLG (((uae_s32)(src)) < 0);
63217: m68k_dreg(regs, dstreg) = (src);
63218: }}}}}m68k_incpc(4);
63219: fill_prefetch_0 ();
63220: endlabel3494: ;
63221: return 18;
63222: }
63223: unsigned long REGPARAM2 CPUFUNC(op_c0bb_5)(uae_u32 opcode) /* AND */
63224: {
63225: uae_u32 dstreg = (opcode >> 9) & 7;
63226: OpcodeFamily = 2; CurrentInstrCycles = 20;
63227: {{ uaecptr tmppc = m68k_getpc() + 2;
63228: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
63229: BusCyclePenalty += 2;
63230: if ((srca & 1) != 0) {
63231: last_fault_for_exception_3 = srca;
63232: last_op_for_exception_3 = opcode;
63233: last_addr_for_exception_3 = m68k_getpc() + 4;
63234: Exception(3, 0, M68000_EXC_SRC_CPU);
63235: goto endlabel3495;
63236: }
63237: {{ uae_s32 src = get_long(srca);
63238: { uae_s32 dst = m68k_dreg(regs, dstreg);
63239: src &= dst;
63240: CLEAR_CZNV;
63241: SET_ZFLG (((uae_s32)(src)) == 0);
63242: SET_NFLG (((uae_s32)(src)) < 0);
63243: m68k_dreg(regs, dstreg) = (src);
63244: }}}}}m68k_incpc(4);
63245: fill_prefetch_0 ();
63246: endlabel3495: ;
63247: return 20;
63248: }
63249: unsigned long REGPARAM2 CPUFUNC(op_c0bc_5)(uae_u32 opcode) /* AND */
63250: {
63251: uae_u32 dstreg = (opcode >> 9) & 7;
63252: OpcodeFamily = 2; CurrentInstrCycles = 16;
63253: {{ uae_s32 src = get_ilong_prefetch(2);
63254: { uae_s32 dst = m68k_dreg(regs, dstreg);
63255: src &= dst;
63256: CLEAR_CZNV;
63257: SET_ZFLG (((uae_s32)(src)) == 0);
63258: SET_NFLG (((uae_s32)(src)) < 0);
63259: m68k_dreg(regs, dstreg) = (src);
63260: }}}m68k_incpc(6);
63261: fill_prefetch_0 ();
63262: return 16;
63263: }
63264: unsigned long REGPARAM2 CPUFUNC(op_c0c0_5)(uae_u32 opcode) /* MULU */
63265: {
63266: uae_u32 srcreg = (opcode & 7);
63267: uae_u32 dstreg = (opcode >> 9) & 7;
63268: unsigned int retcycles = 0;
63269: OpcodeFamily = 62; CurrentInstrCycles = 38;
63270: {{ uae_s16 src = m68k_dreg(regs, srcreg);
63271: { uae_s16 dst = m68k_dreg(regs, dstreg);
63272: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63273: CLEAR_CZNV;
63274: SET_ZFLG (((uae_s32)(newv)) == 0);
63275: SET_NFLG (((uae_s32)(newv)) < 0);
63276: m68k_dreg(regs, dstreg) = (newv);
63277: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63278: }}}}m68k_incpc(2);
63279: fill_prefetch_2 ();
63280: return (38+retcycles*2);
63281: }
63282: unsigned long REGPARAM2 CPUFUNC(op_c0d0_5)(uae_u32 opcode) /* MULU */
63283: {
63284: uae_u32 srcreg = (opcode & 7);
63285: uae_u32 dstreg = (opcode >> 9) & 7;
63286: unsigned int retcycles = 0;
63287: OpcodeFamily = 62; CurrentInstrCycles = 42;
63288: {{ uaecptr srca = m68k_areg(regs, srcreg);
63289: if ((srca & 1) != 0) {
63290: last_fault_for_exception_3 = srca;
63291: last_op_for_exception_3 = opcode;
63292: last_addr_for_exception_3 = m68k_getpc() + 2;
63293: Exception(3, 0, M68000_EXC_SRC_CPU);
63294: goto endlabel3498;
63295: }
63296: {{ uae_s16 src = get_word(srca);
63297: { uae_s16 dst = m68k_dreg(regs, dstreg);
63298: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63299: CLEAR_CZNV;
63300: SET_ZFLG (((uae_s32)(newv)) == 0);
63301: SET_NFLG (((uae_s32)(newv)) < 0);
63302: m68k_dreg(regs, dstreg) = (newv);
63303: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63304: }}}}}}m68k_incpc(2);
63305: fill_prefetch_2 ();
63306: endlabel3498: ;
63307: return (42+retcycles*2);
63308: }
63309: unsigned long REGPARAM2 CPUFUNC(op_c0d8_5)(uae_u32 opcode) /* MULU */
63310: {
63311: uae_u32 srcreg = (opcode & 7);
63312: uae_u32 dstreg = (opcode >> 9) & 7;
63313: unsigned int retcycles = 0;
63314: OpcodeFamily = 62; CurrentInstrCycles = 42;
63315: {{ uaecptr srca = m68k_areg(regs, srcreg);
63316: if ((srca & 1) != 0) {
63317: last_fault_for_exception_3 = srca;
63318: last_op_for_exception_3 = opcode;
63319: last_addr_for_exception_3 = m68k_getpc() + 2;
63320: Exception(3, 0, M68000_EXC_SRC_CPU);
63321: goto endlabel3499;
63322: }
63323: {{ uae_s16 src = get_word(srca);
63324: m68k_areg(regs, srcreg) += 2;
63325: { uae_s16 dst = m68k_dreg(regs, dstreg);
63326: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63327: CLEAR_CZNV;
63328: SET_ZFLG (((uae_s32)(newv)) == 0);
63329: SET_NFLG (((uae_s32)(newv)) < 0);
63330: m68k_dreg(regs, dstreg) = (newv);
63331: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63332: }}}}}}m68k_incpc(2);
63333: fill_prefetch_2 ();
63334: endlabel3499: ;
63335: return (42+retcycles*2);
63336: }
63337: unsigned long REGPARAM2 CPUFUNC(op_c0e0_5)(uae_u32 opcode) /* MULU */
63338: {
63339: uae_u32 srcreg = (opcode & 7);
63340: uae_u32 dstreg = (opcode >> 9) & 7;
63341: unsigned int retcycles = 0;
63342: OpcodeFamily = 62; CurrentInstrCycles = 44;
63343: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
63344: if ((srca & 1) != 0) {
63345: last_fault_for_exception_3 = srca;
63346: last_op_for_exception_3 = opcode;
63347: last_addr_for_exception_3 = m68k_getpc() + 2;
63348: Exception(3, 0, M68000_EXC_SRC_CPU);
63349: goto endlabel3500;
63350: }
63351: {{ uae_s16 src = get_word(srca);
63352: m68k_areg (regs, srcreg) = srca;
63353: { uae_s16 dst = m68k_dreg(regs, dstreg);
63354: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63355: CLEAR_CZNV;
63356: SET_ZFLG (((uae_s32)(newv)) == 0);
63357: SET_NFLG (((uae_s32)(newv)) < 0);
63358: m68k_dreg(regs, dstreg) = (newv);
63359: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63360: }}}}}}m68k_incpc(2);
63361: fill_prefetch_2 ();
63362: endlabel3500: ;
63363: return (44+retcycles*2);
63364: }
63365: unsigned long REGPARAM2 CPUFUNC(op_c0e8_5)(uae_u32 opcode) /* MULU */
63366: {
63367: uae_u32 srcreg = (opcode & 7);
63368: uae_u32 dstreg = (opcode >> 9) & 7;
63369: unsigned int retcycles = 0;
63370: OpcodeFamily = 62; CurrentInstrCycles = 46;
63371: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
63372: if ((srca & 1) != 0) {
63373: last_fault_for_exception_3 = srca;
63374: last_op_for_exception_3 = opcode;
63375: last_addr_for_exception_3 = m68k_getpc() + 4;
63376: Exception(3, 0, M68000_EXC_SRC_CPU);
63377: goto endlabel3501;
63378: }
63379: {{ uae_s16 src = get_word(srca);
63380: { uae_s16 dst = m68k_dreg(regs, dstreg);
63381: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63382: CLEAR_CZNV;
63383: SET_ZFLG (((uae_s32)(newv)) == 0);
63384: SET_NFLG (((uae_s32)(newv)) < 0);
63385: m68k_dreg(regs, dstreg) = (newv);
63386: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63387: }}}}}}m68k_incpc(4);
63388: fill_prefetch_0 ();
63389: endlabel3501: ;
63390: return (46+retcycles*2);
63391: }
63392: unsigned long REGPARAM2 CPUFUNC(op_c0f0_5)(uae_u32 opcode) /* MULU */
63393: {
63394: uae_u32 srcreg = (opcode & 7);
63395: uae_u32 dstreg = (opcode >> 9) & 7;
63396: unsigned int retcycles = 0;
63397: OpcodeFamily = 62; CurrentInstrCycles = 48;
63398: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
63399: BusCyclePenalty += 2;
63400: if ((srca & 1) != 0) {
63401: last_fault_for_exception_3 = srca;
63402: last_op_for_exception_3 = opcode;
63403: last_addr_for_exception_3 = m68k_getpc() + 4;
63404: Exception(3, 0, M68000_EXC_SRC_CPU);
63405: goto endlabel3502;
63406: }
63407: {{ uae_s16 src = get_word(srca);
63408: { uae_s16 dst = m68k_dreg(regs, dstreg);
63409: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63410: CLEAR_CZNV;
63411: SET_ZFLG (((uae_s32)(newv)) == 0);
63412: SET_NFLG (((uae_s32)(newv)) < 0);
63413: m68k_dreg(regs, dstreg) = (newv);
63414: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63415: }}}}}}m68k_incpc(4);
63416: fill_prefetch_0 ();
63417: endlabel3502: ;
63418: return (48+retcycles*2);
63419: }
63420: unsigned long REGPARAM2 CPUFUNC(op_c0f8_5)(uae_u32 opcode) /* MULU */
63421: {
63422: uae_u32 dstreg = (opcode >> 9) & 7;
63423: unsigned int retcycles = 0;
63424: OpcodeFamily = 62; CurrentInstrCycles = 46;
63425: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
63426: if ((srca & 1) != 0) {
63427: last_fault_for_exception_3 = srca;
63428: last_op_for_exception_3 = opcode;
63429: last_addr_for_exception_3 = m68k_getpc() + 4;
63430: Exception(3, 0, M68000_EXC_SRC_CPU);
63431: goto endlabel3503;
63432: }
63433: {{ uae_s16 src = get_word(srca);
63434: { uae_s16 dst = m68k_dreg(regs, dstreg);
63435: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63436: CLEAR_CZNV;
63437: SET_ZFLG (((uae_s32)(newv)) == 0);
63438: SET_NFLG (((uae_s32)(newv)) < 0);
63439: m68k_dreg(regs, dstreg) = (newv);
63440: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63441: }}}}}}m68k_incpc(4);
63442: fill_prefetch_0 ();
63443: endlabel3503: ;
63444: return (46+retcycles*2);
63445: }
63446: unsigned long REGPARAM2 CPUFUNC(op_c0f9_5)(uae_u32 opcode) /* MULU */
63447: {
63448: uae_u32 dstreg = (opcode >> 9) & 7;
63449: unsigned int retcycles = 0;
63450: OpcodeFamily = 62; CurrentInstrCycles = 50;
63451: {{ uaecptr srca = get_ilong_prefetch(2);
63452: if ((srca & 1) != 0) {
63453: last_fault_for_exception_3 = srca;
63454: last_op_for_exception_3 = opcode;
63455: last_addr_for_exception_3 = m68k_getpc() + 6;
63456: Exception(3, 0, M68000_EXC_SRC_CPU);
63457: goto endlabel3504;
63458: }
63459: {{ uae_s16 src = get_word(srca);
63460: { uae_s16 dst = m68k_dreg(regs, dstreg);
63461: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63462: CLEAR_CZNV;
63463: SET_ZFLG (((uae_s32)(newv)) == 0);
63464: SET_NFLG (((uae_s32)(newv)) < 0);
63465: m68k_dreg(regs, dstreg) = (newv);
63466: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63467: }}}}}}m68k_incpc(6);
63468: fill_prefetch_0 ();
63469: endlabel3504: ;
63470: return (50+retcycles*2);
63471: }
63472: unsigned long REGPARAM2 CPUFUNC(op_c0fa_5)(uae_u32 opcode) /* MULU */
63473: {
63474: uae_u32 dstreg = (opcode >> 9) & 7;
63475: unsigned int retcycles = 0;
63476: OpcodeFamily = 62; CurrentInstrCycles = 46;
63477: {{ uaecptr srca = m68k_getpc () + 2;
63478: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
63479: if ((srca & 1) != 0) {
63480: last_fault_for_exception_3 = srca;
63481: last_op_for_exception_3 = opcode;
63482: last_addr_for_exception_3 = m68k_getpc() + 4;
63483: Exception(3, 0, M68000_EXC_SRC_CPU);
63484: goto endlabel3505;
63485: }
63486: {{ uae_s16 src = get_word(srca);
63487: { uae_s16 dst = m68k_dreg(regs, dstreg);
63488: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63489: CLEAR_CZNV;
63490: SET_ZFLG (((uae_s32)(newv)) == 0);
63491: SET_NFLG (((uae_s32)(newv)) < 0);
63492: m68k_dreg(regs, dstreg) = (newv);
63493: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63494: }}}}}}m68k_incpc(4);
63495: fill_prefetch_0 ();
63496: endlabel3505: ;
63497: return (46+retcycles*2);
63498: }
63499: unsigned long REGPARAM2 CPUFUNC(op_c0fb_5)(uae_u32 opcode) /* MULU */
63500: {
63501: uae_u32 dstreg = (opcode >> 9) & 7;
63502: unsigned int retcycles = 0;
63503: OpcodeFamily = 62; CurrentInstrCycles = 48;
63504: {{ uaecptr tmppc = m68k_getpc() + 2;
63505: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
63506: BusCyclePenalty += 2;
63507: if ((srca & 1) != 0) {
63508: last_fault_for_exception_3 = srca;
63509: last_op_for_exception_3 = opcode;
63510: last_addr_for_exception_3 = m68k_getpc() + 4;
63511: Exception(3, 0, M68000_EXC_SRC_CPU);
63512: goto endlabel3506;
63513: }
63514: {{ uae_s16 src = get_word(srca);
63515: { uae_s16 dst = m68k_dreg(regs, dstreg);
63516: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63517: CLEAR_CZNV;
63518: SET_ZFLG (((uae_s32)(newv)) == 0);
63519: SET_NFLG (((uae_s32)(newv)) < 0);
63520: m68k_dreg(regs, dstreg) = (newv);
63521: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63522: }}}}}}m68k_incpc(4);
63523: fill_prefetch_0 ();
63524: endlabel3506: ;
63525: return (48+retcycles*2);
63526: }
63527: unsigned long REGPARAM2 CPUFUNC(op_c0fc_5)(uae_u32 opcode) /* MULU */
63528: {
63529: uae_u32 dstreg = (opcode >> 9) & 7;
63530: unsigned int retcycles = 0;
63531: OpcodeFamily = 62; CurrentInstrCycles = 42;
63532: {{ uae_s16 src = get_iword_prefetch(2);
63533: { uae_s16 dst = m68k_dreg(regs, dstreg);
63534: { uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
63535: CLEAR_CZNV;
63536: SET_ZFLG (((uae_s32)(newv)) == 0);
63537: SET_NFLG (((uae_s32)(newv)) < 0);
63538: m68k_dreg(regs, dstreg) = (newv);
63539: while (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }
63540: }}}}m68k_incpc(4);
63541: fill_prefetch_0 ();
63542: return (42+retcycles*2);
63543: }
63544: unsigned long REGPARAM2 CPUFUNC(op_c100_5)(uae_u32 opcode) /* ABCD */
63545: {
63546: uae_u32 srcreg = (opcode & 7);
63547: uae_u32 dstreg = (opcode >> 9) & 7;
63548: OpcodeFamily = 14; CurrentInstrCycles = 6;
63549: {{ uae_s8 src = m68k_dreg(regs, srcreg);
63550: { uae_s8 dst = m68k_dreg(regs, dstreg);
63551: { uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);
63552: uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
63553: uae_u16 newv, tmp_newv;
63554: int cflg;
63555: newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; }
63556: cflg = (newv & 0x3F0) > 0x90;
63557: if (cflg) newv += 0x60;
63558: SET_CFLG (cflg);
63559: COPY_CARRY;
63560: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
63561: SET_NFLG (((uae_s8)(newv)) < 0);
63562: SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
63563: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
63564: }}}}m68k_incpc(2);
63565: fill_prefetch_2 ();
63566: return 6;
63567: }
63568: unsigned long REGPARAM2 CPUFUNC(op_c108_5)(uae_u32 opcode) /* ABCD */
63569: {
63570: uae_u32 srcreg = (opcode & 7);
63571: uae_u32 dstreg = (opcode >> 9) & 7;
63572: OpcodeFamily = 14; CurrentInstrCycles = 18;
63573: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
63574: { uae_s8 src = get_byte(srca);
63575: m68k_areg (regs, srcreg) = srca;
63576: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
63577: { uae_s8 dst = get_byte(dsta);
63578: m68k_areg (regs, dstreg) = dsta;
63579: { uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);
63580: uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
63581: uae_u16 newv, tmp_newv;
63582: int cflg;
63583: newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; }
63584: cflg = (newv & 0x3F0) > 0x90;
63585: if (cflg) newv += 0x60;
63586: SET_CFLG (cflg);
63587: COPY_CARRY;
63588: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
63589: SET_NFLG (((uae_s8)(newv)) < 0);
63590: SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
63591: m68k_incpc(2);
63592: fill_prefetch_2 ();
63593: put_byte(dsta,newv);
63594: }}}}}}return 18;
63595: }
63596: unsigned long REGPARAM2 CPUFUNC(op_c110_5)(uae_u32 opcode) /* AND */
63597: {
63598: uae_u32 srcreg = ((opcode >> 9) & 7);
63599: uae_u32 dstreg = opcode & 7;
63600: OpcodeFamily = 2; CurrentInstrCycles = 12;
63601: {{ uae_s8 src = m68k_dreg(regs, srcreg);
63602: { uaecptr dsta = m68k_areg(regs, dstreg);
63603: { uae_s8 dst = get_byte(dsta);
63604: src &= dst;
63605: CLEAR_CZNV;
63606: SET_ZFLG (((uae_s8)(src)) == 0);
63607: SET_NFLG (((uae_s8)(src)) < 0);
63608: m68k_incpc(2);
63609: fill_prefetch_2 ();
63610: put_byte(dsta,src);
63611: }}}}return 12;
63612: }
63613: unsigned long REGPARAM2 CPUFUNC(op_c118_5)(uae_u32 opcode) /* AND */
63614: {
63615: uae_u32 srcreg = ((opcode >> 9) & 7);
63616: uae_u32 dstreg = opcode & 7;
63617: OpcodeFamily = 2; CurrentInstrCycles = 12;
63618: {{ uae_s8 src = m68k_dreg(regs, srcreg);
63619: { uaecptr dsta = m68k_areg(regs, dstreg);
63620: { uae_s8 dst = get_byte(dsta);
63621: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
63622: src &= dst;
63623: CLEAR_CZNV;
63624: SET_ZFLG (((uae_s8)(src)) == 0);
63625: SET_NFLG (((uae_s8)(src)) < 0);
63626: m68k_incpc(2);
63627: fill_prefetch_2 ();
63628: put_byte(dsta,src);
63629: }}}}return 12;
63630: }
63631: unsigned long REGPARAM2 CPUFUNC(op_c120_5)(uae_u32 opcode) /* AND */
63632: {
63633: uae_u32 srcreg = ((opcode >> 9) & 7);
63634: uae_u32 dstreg = opcode & 7;
63635: OpcodeFamily = 2; CurrentInstrCycles = 14;
63636: {{ uae_s8 src = m68k_dreg(regs, srcreg);
63637: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
63638: { uae_s8 dst = get_byte(dsta);
63639: m68k_areg (regs, dstreg) = dsta;
63640: src &= dst;
63641: CLEAR_CZNV;
63642: SET_ZFLG (((uae_s8)(src)) == 0);
63643: SET_NFLG (((uae_s8)(src)) < 0);
63644: m68k_incpc(2);
63645: fill_prefetch_2 ();
63646: put_byte(dsta,src);
63647: }}}}return 14;
63648: }
63649: unsigned long REGPARAM2 CPUFUNC(op_c128_5)(uae_u32 opcode) /* AND */
63650: {
63651: uae_u32 srcreg = ((opcode >> 9) & 7);
63652: uae_u32 dstreg = opcode & 7;
63653: OpcodeFamily = 2; CurrentInstrCycles = 16;
63654: {{ uae_s8 src = m68k_dreg(regs, srcreg);
63655: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
63656: { uae_s8 dst = get_byte(dsta);
63657: src &= dst;
63658: CLEAR_CZNV;
63659: SET_ZFLG (((uae_s8)(src)) == 0);
63660: SET_NFLG (((uae_s8)(src)) < 0);
63661: m68k_incpc(4);
63662: fill_prefetch_0 ();
63663: put_byte(dsta,src);
63664: }}}}return 16;
63665: }
63666: unsigned long REGPARAM2 CPUFUNC(op_c130_5)(uae_u32 opcode) /* AND */
63667: {
63668: uae_u32 srcreg = ((opcode >> 9) & 7);
63669: uae_u32 dstreg = opcode & 7;
63670: OpcodeFamily = 2; CurrentInstrCycles = 18;
63671: {{ uae_s8 src = m68k_dreg(regs, srcreg);
63672: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
63673: BusCyclePenalty += 2;
63674: { uae_s8 dst = get_byte(dsta);
63675: src &= dst;
63676: CLEAR_CZNV;
63677: SET_ZFLG (((uae_s8)(src)) == 0);
63678: SET_NFLG (((uae_s8)(src)) < 0);
63679: m68k_incpc(4);
63680: fill_prefetch_0 ();
63681: put_byte(dsta,src);
63682: }}}}return 18;
63683: }
63684: unsigned long REGPARAM2 CPUFUNC(op_c138_5)(uae_u32 opcode) /* AND */
63685: {
63686: uae_u32 srcreg = ((opcode >> 9) & 7);
63687: OpcodeFamily = 2; CurrentInstrCycles = 16;
63688: {{ uae_s8 src = m68k_dreg(regs, srcreg);
63689: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
63690: { uae_s8 dst = get_byte(dsta);
63691: src &= dst;
63692: CLEAR_CZNV;
63693: SET_ZFLG (((uae_s8)(src)) == 0);
63694: SET_NFLG (((uae_s8)(src)) < 0);
63695: m68k_incpc(4);
63696: fill_prefetch_0 ();
63697: put_byte(dsta,src);
63698: }}}}return 16;
63699: }
63700: unsigned long REGPARAM2 CPUFUNC(op_c139_5)(uae_u32 opcode) /* AND */
63701: {
63702: uae_u32 srcreg = ((opcode >> 9) & 7);
63703: OpcodeFamily = 2; CurrentInstrCycles = 20;
63704: {{ uae_s8 src = m68k_dreg(regs, srcreg);
63705: { uaecptr dsta = get_ilong_prefetch(2);
63706: { uae_s8 dst = get_byte(dsta);
63707: src &= dst;
63708: CLEAR_CZNV;
63709: SET_ZFLG (((uae_s8)(src)) == 0);
63710: SET_NFLG (((uae_s8)(src)) < 0);
63711: m68k_incpc(6);
63712: fill_prefetch_0 ();
63713: put_byte(dsta,src);
63714: }}}}return 20;
63715: }
63716: unsigned long REGPARAM2 CPUFUNC(op_c140_5)(uae_u32 opcode) /* EXG */
63717: {
63718: uae_u32 srcreg = ((opcode >> 9) & 7);
63719: uae_u32 dstreg = opcode & 7;
63720: OpcodeFamily = 35; CurrentInstrCycles = 6;
63721: {{ uae_s32 src = m68k_dreg(regs, srcreg);
63722: { uae_s32 dst = m68k_dreg(regs, dstreg);
63723: m68k_dreg(regs, srcreg) = (dst);
63724: m68k_dreg(regs, dstreg) = (src);
63725: }}}m68k_incpc(2);
63726: fill_prefetch_2 ();
63727: return 6;
63728: }
63729: unsigned long REGPARAM2 CPUFUNC(op_c148_5)(uae_u32 opcode) /* EXG */
63730: {
63731: uae_u32 srcreg = ((opcode >> 9) & 7);
63732: uae_u32 dstreg = opcode & 7;
63733: OpcodeFamily = 35; CurrentInstrCycles = 6;
63734: {{ uae_s32 src = m68k_areg(regs, srcreg);
63735: { uae_s32 dst = m68k_areg(regs, dstreg);
63736: m68k_areg(regs, srcreg) = (dst);
63737: m68k_areg(regs, dstreg) = (src);
63738: }}}m68k_incpc(2);
63739: fill_prefetch_2 ();
63740: return 6;
63741: }
63742: unsigned long REGPARAM2 CPUFUNC(op_c150_5)(uae_u32 opcode) /* AND */
63743: {
63744: uae_u32 srcreg = ((opcode >> 9) & 7);
63745: uae_u32 dstreg = opcode & 7;
63746: OpcodeFamily = 2; CurrentInstrCycles = 12;
63747: {{ uae_s16 src = m68k_dreg(regs, srcreg);
63748: { uaecptr dsta = m68k_areg(regs, dstreg);
63749: if ((dsta & 1) != 0) {
63750: last_fault_for_exception_3 = dsta;
63751: last_op_for_exception_3 = opcode;
63752: last_addr_for_exception_3 = m68k_getpc() + 2;
63753: Exception(3, 0, M68000_EXC_SRC_CPU);
63754: goto endlabel3519;
63755: }
63756: {{ uae_s16 dst = get_word(dsta);
63757: src &= dst;
63758: CLEAR_CZNV;
63759: SET_ZFLG (((uae_s16)(src)) == 0);
63760: SET_NFLG (((uae_s16)(src)) < 0);
63761: m68k_incpc(2);
63762: fill_prefetch_2 ();
63763: put_word(dsta,src);
63764: }}}}}endlabel3519: ;
63765: return 12;
63766: }
63767: unsigned long REGPARAM2 CPUFUNC(op_c158_5)(uae_u32 opcode) /* AND */
63768: {
63769: uae_u32 srcreg = ((opcode >> 9) & 7);
63770: uae_u32 dstreg = opcode & 7;
63771: OpcodeFamily = 2; CurrentInstrCycles = 12;
63772: {{ uae_s16 src = m68k_dreg(regs, srcreg);
63773: { uaecptr dsta = m68k_areg(regs, dstreg);
63774: if ((dsta & 1) != 0) {
63775: last_fault_for_exception_3 = dsta;
63776: last_op_for_exception_3 = opcode;
63777: last_addr_for_exception_3 = m68k_getpc() + 2;
63778: Exception(3, 0, M68000_EXC_SRC_CPU);
63779: goto endlabel3520;
63780: }
63781: {{ uae_s16 dst = get_word(dsta);
63782: m68k_areg(regs, dstreg) += 2;
63783: src &= dst;
63784: CLEAR_CZNV;
63785: SET_ZFLG (((uae_s16)(src)) == 0);
63786: SET_NFLG (((uae_s16)(src)) < 0);
63787: m68k_incpc(2);
63788: fill_prefetch_2 ();
63789: put_word(dsta,src);
63790: }}}}}endlabel3520: ;
63791: return 12;
63792: }
63793: unsigned long REGPARAM2 CPUFUNC(op_c160_5)(uae_u32 opcode) /* AND */
63794: {
63795: uae_u32 srcreg = ((opcode >> 9) & 7);
63796: uae_u32 dstreg = opcode & 7;
63797: OpcodeFamily = 2; CurrentInstrCycles = 14;
63798: {{ uae_s16 src = m68k_dreg(regs, srcreg);
63799: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
63800: if ((dsta & 1) != 0) {
63801: last_fault_for_exception_3 = dsta;
63802: last_op_for_exception_3 = opcode;
63803: last_addr_for_exception_3 = m68k_getpc() + 2;
63804: Exception(3, 0, M68000_EXC_SRC_CPU);
63805: goto endlabel3521;
63806: }
63807: {{ uae_s16 dst = get_word(dsta);
63808: m68k_areg (regs, dstreg) = dsta;
63809: src &= dst;
63810: CLEAR_CZNV;
63811: SET_ZFLG (((uae_s16)(src)) == 0);
63812: SET_NFLG (((uae_s16)(src)) < 0);
63813: m68k_incpc(2);
63814: fill_prefetch_2 ();
63815: put_word(dsta,src);
63816: }}}}}endlabel3521: ;
63817: return 14;
63818: }
63819: unsigned long REGPARAM2 CPUFUNC(op_c168_5)(uae_u32 opcode) /* AND */
63820: {
63821: uae_u32 srcreg = ((opcode >> 9) & 7);
63822: uae_u32 dstreg = opcode & 7;
63823: OpcodeFamily = 2; CurrentInstrCycles = 16;
63824: {{ uae_s16 src = m68k_dreg(regs, srcreg);
63825: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
63826: if ((dsta & 1) != 0) {
63827: last_fault_for_exception_3 = dsta;
63828: last_op_for_exception_3 = opcode;
63829: last_addr_for_exception_3 = m68k_getpc() + 4;
63830: Exception(3, 0, M68000_EXC_SRC_CPU);
63831: goto endlabel3522;
63832: }
63833: {{ uae_s16 dst = get_word(dsta);
63834: src &= dst;
63835: CLEAR_CZNV;
63836: SET_ZFLG (((uae_s16)(src)) == 0);
63837: SET_NFLG (((uae_s16)(src)) < 0);
63838: m68k_incpc(4);
63839: fill_prefetch_0 ();
63840: put_word(dsta,src);
63841: }}}}}endlabel3522: ;
63842: return 16;
63843: }
63844: unsigned long REGPARAM2 CPUFUNC(op_c170_5)(uae_u32 opcode) /* AND */
63845: {
63846: uae_u32 srcreg = ((opcode >> 9) & 7);
63847: uae_u32 dstreg = opcode & 7;
63848: OpcodeFamily = 2; CurrentInstrCycles = 18;
63849: {{ uae_s16 src = m68k_dreg(regs, srcreg);
63850: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
63851: BusCyclePenalty += 2;
63852: if ((dsta & 1) != 0) {
63853: last_fault_for_exception_3 = dsta;
63854: last_op_for_exception_3 = opcode;
63855: last_addr_for_exception_3 = m68k_getpc() + 4;
63856: Exception(3, 0, M68000_EXC_SRC_CPU);
63857: goto endlabel3523;
63858: }
63859: {{ uae_s16 dst = get_word(dsta);
63860: src &= dst;
63861: CLEAR_CZNV;
63862: SET_ZFLG (((uae_s16)(src)) == 0);
63863: SET_NFLG (((uae_s16)(src)) < 0);
63864: m68k_incpc(4);
63865: fill_prefetch_0 ();
63866: put_word(dsta,src);
63867: }}}}}endlabel3523: ;
63868: return 18;
63869: }
63870: unsigned long REGPARAM2 CPUFUNC(op_c178_5)(uae_u32 opcode) /* AND */
63871: {
63872: uae_u32 srcreg = ((opcode >> 9) & 7);
63873: OpcodeFamily = 2; CurrentInstrCycles = 16;
63874: {{ uae_s16 src = m68k_dreg(regs, srcreg);
63875: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
63876: if ((dsta & 1) != 0) {
63877: last_fault_for_exception_3 = dsta;
63878: last_op_for_exception_3 = opcode;
63879: last_addr_for_exception_3 = m68k_getpc() + 4;
63880: Exception(3, 0, M68000_EXC_SRC_CPU);
63881: goto endlabel3524;
63882: }
63883: {{ uae_s16 dst = get_word(dsta);
63884: src &= dst;
63885: CLEAR_CZNV;
63886: SET_ZFLG (((uae_s16)(src)) == 0);
63887: SET_NFLG (((uae_s16)(src)) < 0);
63888: m68k_incpc(4);
63889: fill_prefetch_0 ();
63890: put_word(dsta,src);
63891: }}}}}endlabel3524: ;
63892: return 16;
63893: }
63894: unsigned long REGPARAM2 CPUFUNC(op_c179_5)(uae_u32 opcode) /* AND */
63895: {
63896: uae_u32 srcreg = ((opcode >> 9) & 7);
63897: OpcodeFamily = 2; CurrentInstrCycles = 20;
63898: {{ uae_s16 src = m68k_dreg(regs, srcreg);
63899: { uaecptr dsta = get_ilong_prefetch(2);
63900: if ((dsta & 1) != 0) {
63901: last_fault_for_exception_3 = dsta;
63902: last_op_for_exception_3 = opcode;
63903: last_addr_for_exception_3 = m68k_getpc() + 6;
63904: Exception(3, 0, M68000_EXC_SRC_CPU);
63905: goto endlabel3525;
63906: }
63907: {{ uae_s16 dst = get_word(dsta);
63908: src &= dst;
63909: CLEAR_CZNV;
63910: SET_ZFLG (((uae_s16)(src)) == 0);
63911: SET_NFLG (((uae_s16)(src)) < 0);
63912: m68k_incpc(6);
63913: fill_prefetch_0 ();
63914: put_word(dsta,src);
63915: }}}}}endlabel3525: ;
63916: return 20;
63917: }
63918: unsigned long REGPARAM2 CPUFUNC(op_c188_5)(uae_u32 opcode) /* EXG */
63919: {
63920: uae_u32 srcreg = ((opcode >> 9) & 7);
63921: uae_u32 dstreg = opcode & 7;
63922: OpcodeFamily = 35; CurrentInstrCycles = 6;
63923: {{ uae_s32 src = m68k_dreg(regs, srcreg);
63924: { uae_s32 dst = m68k_areg(regs, dstreg);
63925: m68k_dreg(regs, srcreg) = (dst);
63926: m68k_areg(regs, dstreg) = (src);
63927: }}}m68k_incpc(2);
63928: fill_prefetch_2 ();
63929: return 6;
63930: }
63931: unsigned long REGPARAM2 CPUFUNC(op_c190_5)(uae_u32 opcode) /* AND */
63932: {
63933: uae_u32 srcreg = ((opcode >> 9) & 7);
63934: uae_u32 dstreg = opcode & 7;
63935: OpcodeFamily = 2; CurrentInstrCycles = 20;
63936: {{ uae_s32 src = m68k_dreg(regs, srcreg);
63937: { uaecptr dsta = m68k_areg(regs, dstreg);
63938: if ((dsta & 1) != 0) {
63939: last_fault_for_exception_3 = dsta;
63940: last_op_for_exception_3 = opcode;
63941: last_addr_for_exception_3 = m68k_getpc() + 2;
63942: Exception(3, 0, M68000_EXC_SRC_CPU);
63943: goto endlabel3527;
63944: }
63945: {{ uae_s32 dst = get_long(dsta);
63946: src &= dst;
63947: CLEAR_CZNV;
63948: SET_ZFLG (((uae_s32)(src)) == 0);
63949: SET_NFLG (((uae_s32)(src)) < 0);
63950: m68k_incpc(2);
63951: fill_prefetch_2 ();
63952: put_long(dsta,src);
63953: }}}}}endlabel3527: ;
63954: return 20;
63955: }
63956: unsigned long REGPARAM2 CPUFUNC(op_c198_5)(uae_u32 opcode) /* AND */
63957: {
63958: uae_u32 srcreg = ((opcode >> 9) & 7);
63959: uae_u32 dstreg = opcode & 7;
63960: OpcodeFamily = 2; CurrentInstrCycles = 20;
63961: {{ uae_s32 src = m68k_dreg(regs, srcreg);
63962: { uaecptr dsta = m68k_areg(regs, dstreg);
63963: if ((dsta & 1) != 0) {
63964: last_fault_for_exception_3 = dsta;
63965: last_op_for_exception_3 = opcode;
63966: last_addr_for_exception_3 = m68k_getpc() + 2;
63967: Exception(3, 0, M68000_EXC_SRC_CPU);
63968: goto endlabel3528;
63969: }
63970: {{ uae_s32 dst = get_long(dsta);
63971: m68k_areg(regs, dstreg) += 4;
63972: src &= dst;
63973: CLEAR_CZNV;
63974: SET_ZFLG (((uae_s32)(src)) == 0);
63975: SET_NFLG (((uae_s32)(src)) < 0);
63976: m68k_incpc(2);
63977: fill_prefetch_2 ();
63978: put_long(dsta,src);
63979: }}}}}endlabel3528: ;
63980: return 20;
63981: }
63982: unsigned long REGPARAM2 CPUFUNC(op_c1a0_5)(uae_u32 opcode) /* AND */
63983: {
63984: uae_u32 srcreg = ((opcode >> 9) & 7);
63985: uae_u32 dstreg = opcode & 7;
63986: OpcodeFamily = 2; CurrentInstrCycles = 22;
63987: {{ uae_s32 src = m68k_dreg(regs, srcreg);
63988: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
63989: if ((dsta & 1) != 0) {
63990: last_fault_for_exception_3 = dsta;
63991: last_op_for_exception_3 = opcode;
63992: last_addr_for_exception_3 = m68k_getpc() + 2;
63993: Exception(3, 0, M68000_EXC_SRC_CPU);
63994: goto endlabel3529;
63995: }
63996: {{ uae_s32 dst = get_long(dsta);
63997: m68k_areg (regs, dstreg) = dsta;
63998: src &= dst;
63999: CLEAR_CZNV;
64000: SET_ZFLG (((uae_s32)(src)) == 0);
64001: SET_NFLG (((uae_s32)(src)) < 0);
64002: m68k_incpc(2);
64003: fill_prefetch_2 ();
64004: put_long(dsta,src);
64005: }}}}}endlabel3529: ;
64006: return 22;
64007: }
64008: unsigned long REGPARAM2 CPUFUNC(op_c1a8_5)(uae_u32 opcode) /* AND */
64009: {
64010: uae_u32 srcreg = ((opcode >> 9) & 7);
64011: uae_u32 dstreg = opcode & 7;
64012: OpcodeFamily = 2; CurrentInstrCycles = 24;
64013: {{ uae_s32 src = m68k_dreg(regs, srcreg);
64014: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
64015: if ((dsta & 1) != 0) {
64016: last_fault_for_exception_3 = dsta;
64017: last_op_for_exception_3 = opcode;
64018: last_addr_for_exception_3 = m68k_getpc() + 4;
64019: Exception(3, 0, M68000_EXC_SRC_CPU);
64020: goto endlabel3530;
64021: }
64022: {{ uae_s32 dst = get_long(dsta);
64023: src &= dst;
64024: CLEAR_CZNV;
64025: SET_ZFLG (((uae_s32)(src)) == 0);
64026: SET_NFLG (((uae_s32)(src)) < 0);
64027: m68k_incpc(4);
64028: fill_prefetch_0 ();
64029: put_long(dsta,src);
64030: }}}}}endlabel3530: ;
64031: return 24;
64032: }
64033: unsigned long REGPARAM2 CPUFUNC(op_c1b0_5)(uae_u32 opcode) /* AND */
64034: {
64035: uae_u32 srcreg = ((opcode >> 9) & 7);
64036: uae_u32 dstreg = opcode & 7;
64037: OpcodeFamily = 2; CurrentInstrCycles = 26;
64038: {{ uae_s32 src = m68k_dreg(regs, srcreg);
64039: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
64040: BusCyclePenalty += 2;
64041: if ((dsta & 1) != 0) {
64042: last_fault_for_exception_3 = dsta;
64043: last_op_for_exception_3 = opcode;
64044: last_addr_for_exception_3 = m68k_getpc() + 4;
64045: Exception(3, 0, M68000_EXC_SRC_CPU);
64046: goto endlabel3531;
64047: }
64048: {{ uae_s32 dst = get_long(dsta);
64049: src &= dst;
64050: CLEAR_CZNV;
64051: SET_ZFLG (((uae_s32)(src)) == 0);
64052: SET_NFLG (((uae_s32)(src)) < 0);
64053: m68k_incpc(4);
64054: fill_prefetch_0 ();
64055: put_long(dsta,src);
64056: }}}}}endlabel3531: ;
64057: return 26;
64058: }
64059: unsigned long REGPARAM2 CPUFUNC(op_c1b8_5)(uae_u32 opcode) /* AND */
64060: {
64061: uae_u32 srcreg = ((opcode >> 9) & 7);
64062: OpcodeFamily = 2; CurrentInstrCycles = 24;
64063: {{ uae_s32 src = m68k_dreg(regs, srcreg);
64064: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
64065: if ((dsta & 1) != 0) {
64066: last_fault_for_exception_3 = dsta;
64067: last_op_for_exception_3 = opcode;
64068: last_addr_for_exception_3 = m68k_getpc() + 4;
64069: Exception(3, 0, M68000_EXC_SRC_CPU);
64070: goto endlabel3532;
64071: }
64072: {{ uae_s32 dst = get_long(dsta);
64073: src &= dst;
64074: CLEAR_CZNV;
64075: SET_ZFLG (((uae_s32)(src)) == 0);
64076: SET_NFLG (((uae_s32)(src)) < 0);
64077: m68k_incpc(4);
64078: fill_prefetch_0 ();
64079: put_long(dsta,src);
64080: }}}}}endlabel3532: ;
64081: return 24;
64082: }
64083: unsigned long REGPARAM2 CPUFUNC(op_c1b9_5)(uae_u32 opcode) /* AND */
64084: {
64085: uae_u32 srcreg = ((opcode >> 9) & 7);
64086: OpcodeFamily = 2; CurrentInstrCycles = 28;
64087: {{ uae_s32 src = m68k_dreg(regs, srcreg);
64088: { uaecptr dsta = get_ilong_prefetch(2);
64089: if ((dsta & 1) != 0) {
64090: last_fault_for_exception_3 = dsta;
64091: last_op_for_exception_3 = opcode;
64092: last_addr_for_exception_3 = m68k_getpc() + 6;
64093: Exception(3, 0, M68000_EXC_SRC_CPU);
64094: goto endlabel3533;
64095: }
64096: {{ uae_s32 dst = get_long(dsta);
64097: src &= dst;
64098: CLEAR_CZNV;
64099: SET_ZFLG (((uae_s32)(src)) == 0);
64100: SET_NFLG (((uae_s32)(src)) < 0);
64101: m68k_incpc(6);
64102: fill_prefetch_0 ();
64103: put_long(dsta,src);
64104: }}}}}endlabel3533: ;
64105: return 28;
64106: }
64107: unsigned long REGPARAM2 CPUFUNC(op_c1c0_5)(uae_u32 opcode) /* MULS */
64108: {
64109: uae_u32 srcreg = (opcode & 7);
64110: uae_u32 dstreg = (opcode >> 9) & 7;
64111: unsigned int retcycles = 0;
64112: OpcodeFamily = 63; CurrentInstrCycles = 38;
64113: {{ uae_s16 src = m68k_dreg(regs, srcreg);
64114: { uae_s16 dst = m68k_dreg(regs, dstreg);
64115: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64116: uae_u32 src2;
64117: CLEAR_CZNV;
64118: SET_ZFLG (((uae_s32)(newv)) == 0);
64119: SET_NFLG (((uae_s32)(newv)) < 0);
64120: m68k_dreg(regs, dstreg) = (newv);
64121: src2 = ((uae_u32)src) << 1;
64122: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64123: }}}}m68k_incpc(2);
64124: fill_prefetch_2 ();
64125: return (38+retcycles*2);
64126: }
64127: unsigned long REGPARAM2 CPUFUNC(op_c1d0_5)(uae_u32 opcode) /* MULS */
64128: {
64129: uae_u32 srcreg = (opcode & 7);
64130: uae_u32 dstreg = (opcode >> 9) & 7;
64131: unsigned int retcycles = 0;
64132: OpcodeFamily = 63; CurrentInstrCycles = 42;
64133: {{ uaecptr srca = m68k_areg(regs, srcreg);
64134: if ((srca & 1) != 0) {
64135: last_fault_for_exception_3 = srca;
64136: last_op_for_exception_3 = opcode;
64137: last_addr_for_exception_3 = m68k_getpc() + 2;
64138: Exception(3, 0, M68000_EXC_SRC_CPU);
64139: goto endlabel3535;
64140: }
64141: {{ uae_s16 src = get_word(srca);
64142: { uae_s16 dst = m68k_dreg(regs, dstreg);
64143: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64144: uae_u32 src2;
64145: CLEAR_CZNV;
64146: SET_ZFLG (((uae_s32)(newv)) == 0);
64147: SET_NFLG (((uae_s32)(newv)) < 0);
64148: m68k_dreg(regs, dstreg) = (newv);
64149: src2 = ((uae_u32)src) << 1;
64150: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64151: }}}}}}m68k_incpc(2);
64152: fill_prefetch_2 ();
64153: endlabel3535: ;
64154: return (42+retcycles*2);
64155: }
64156: unsigned long REGPARAM2 CPUFUNC(op_c1d8_5)(uae_u32 opcode) /* MULS */
64157: {
64158: uae_u32 srcreg = (opcode & 7);
64159: uae_u32 dstreg = (opcode >> 9) & 7;
64160: unsigned int retcycles = 0;
64161: OpcodeFamily = 63; CurrentInstrCycles = 42;
64162: {{ uaecptr srca = m68k_areg(regs, srcreg);
64163: if ((srca & 1) != 0) {
64164: last_fault_for_exception_3 = srca;
64165: last_op_for_exception_3 = opcode;
64166: last_addr_for_exception_3 = m68k_getpc() + 2;
64167: Exception(3, 0, M68000_EXC_SRC_CPU);
64168: goto endlabel3536;
64169: }
64170: {{ uae_s16 src = get_word(srca);
64171: m68k_areg(regs, srcreg) += 2;
64172: { uae_s16 dst = m68k_dreg(regs, dstreg);
64173: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64174: uae_u32 src2;
64175: CLEAR_CZNV;
64176: SET_ZFLG (((uae_s32)(newv)) == 0);
64177: SET_NFLG (((uae_s32)(newv)) < 0);
64178: m68k_dreg(regs, dstreg) = (newv);
64179: src2 = ((uae_u32)src) << 1;
64180: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64181: }}}}}}m68k_incpc(2);
64182: fill_prefetch_2 ();
64183: endlabel3536: ;
64184: return (42+retcycles*2);
64185: }
64186: unsigned long REGPARAM2 CPUFUNC(op_c1e0_5)(uae_u32 opcode) /* MULS */
64187: {
64188: uae_u32 srcreg = (opcode & 7);
64189: uae_u32 dstreg = (opcode >> 9) & 7;
64190: unsigned int retcycles = 0;
64191: OpcodeFamily = 63; CurrentInstrCycles = 44;
64192: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
64193: if ((srca & 1) != 0) {
64194: last_fault_for_exception_3 = srca;
64195: last_op_for_exception_3 = opcode;
64196: last_addr_for_exception_3 = m68k_getpc() + 2;
64197: Exception(3, 0, M68000_EXC_SRC_CPU);
64198: goto endlabel3537;
64199: }
64200: {{ uae_s16 src = get_word(srca);
64201: m68k_areg (regs, srcreg) = srca;
64202: { uae_s16 dst = m68k_dreg(regs, dstreg);
64203: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64204: uae_u32 src2;
64205: CLEAR_CZNV;
64206: SET_ZFLG (((uae_s32)(newv)) == 0);
64207: SET_NFLG (((uae_s32)(newv)) < 0);
64208: m68k_dreg(regs, dstreg) = (newv);
64209: src2 = ((uae_u32)src) << 1;
64210: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64211: }}}}}}m68k_incpc(2);
64212: fill_prefetch_2 ();
64213: endlabel3537: ;
64214: return (44+retcycles*2);
64215: }
64216: unsigned long REGPARAM2 CPUFUNC(op_c1e8_5)(uae_u32 opcode) /* MULS */
64217: {
64218: uae_u32 srcreg = (opcode & 7);
64219: uae_u32 dstreg = (opcode >> 9) & 7;
64220: unsigned int retcycles = 0;
64221: OpcodeFamily = 63; CurrentInstrCycles = 46;
64222: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
64223: if ((srca & 1) != 0) {
64224: last_fault_for_exception_3 = srca;
64225: last_op_for_exception_3 = opcode;
64226: last_addr_for_exception_3 = m68k_getpc() + 4;
64227: Exception(3, 0, M68000_EXC_SRC_CPU);
64228: goto endlabel3538;
64229: }
64230: {{ uae_s16 src = get_word(srca);
64231: { uae_s16 dst = m68k_dreg(regs, dstreg);
64232: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64233: uae_u32 src2;
64234: CLEAR_CZNV;
64235: SET_ZFLG (((uae_s32)(newv)) == 0);
64236: SET_NFLG (((uae_s32)(newv)) < 0);
64237: m68k_dreg(regs, dstreg) = (newv);
64238: src2 = ((uae_u32)src) << 1;
64239: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64240: }}}}}}m68k_incpc(4);
64241: fill_prefetch_0 ();
64242: endlabel3538: ;
64243: return (46+retcycles*2);
64244: }
64245: unsigned long REGPARAM2 CPUFUNC(op_c1f0_5)(uae_u32 opcode) /* MULS */
64246: {
64247: uae_u32 srcreg = (opcode & 7);
64248: uae_u32 dstreg = (opcode >> 9) & 7;
64249: unsigned int retcycles = 0;
64250: OpcodeFamily = 63; CurrentInstrCycles = 48;
64251: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
64252: BusCyclePenalty += 2;
64253: if ((srca & 1) != 0) {
64254: last_fault_for_exception_3 = srca;
64255: last_op_for_exception_3 = opcode;
64256: last_addr_for_exception_3 = m68k_getpc() + 4;
64257: Exception(3, 0, M68000_EXC_SRC_CPU);
64258: goto endlabel3539;
64259: }
64260: {{ uae_s16 src = get_word(srca);
64261: { uae_s16 dst = m68k_dreg(regs, dstreg);
64262: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64263: uae_u32 src2;
64264: CLEAR_CZNV;
64265: SET_ZFLG (((uae_s32)(newv)) == 0);
64266: SET_NFLG (((uae_s32)(newv)) < 0);
64267: m68k_dreg(regs, dstreg) = (newv);
64268: src2 = ((uae_u32)src) << 1;
64269: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64270: }}}}}}m68k_incpc(4);
64271: fill_prefetch_0 ();
64272: endlabel3539: ;
64273: return (48+retcycles*2);
64274: }
64275: unsigned long REGPARAM2 CPUFUNC(op_c1f8_5)(uae_u32 opcode) /* MULS */
64276: {
64277: uae_u32 dstreg = (opcode >> 9) & 7;
64278: unsigned int retcycles = 0;
64279: OpcodeFamily = 63; CurrentInstrCycles = 46;
64280: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
64281: if ((srca & 1) != 0) {
64282: last_fault_for_exception_3 = srca;
64283: last_op_for_exception_3 = opcode;
64284: last_addr_for_exception_3 = m68k_getpc() + 4;
64285: Exception(3, 0, M68000_EXC_SRC_CPU);
64286: goto endlabel3540;
64287: }
64288: {{ uae_s16 src = get_word(srca);
64289: { uae_s16 dst = m68k_dreg(regs, dstreg);
64290: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64291: uae_u32 src2;
64292: CLEAR_CZNV;
64293: SET_ZFLG (((uae_s32)(newv)) == 0);
64294: SET_NFLG (((uae_s32)(newv)) < 0);
64295: m68k_dreg(regs, dstreg) = (newv);
64296: src2 = ((uae_u32)src) << 1;
64297: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64298: }}}}}}m68k_incpc(4);
64299: fill_prefetch_0 ();
64300: endlabel3540: ;
64301: return (46+retcycles*2);
64302: }
64303: unsigned long REGPARAM2 CPUFUNC(op_c1f9_5)(uae_u32 opcode) /* MULS */
64304: {
64305: uae_u32 dstreg = (opcode >> 9) & 7;
64306: unsigned int retcycles = 0;
64307: OpcodeFamily = 63; CurrentInstrCycles = 50;
64308: {{ uaecptr srca = get_ilong_prefetch(2);
64309: if ((srca & 1) != 0) {
64310: last_fault_for_exception_3 = srca;
64311: last_op_for_exception_3 = opcode;
64312: last_addr_for_exception_3 = m68k_getpc() + 6;
64313: Exception(3, 0, M68000_EXC_SRC_CPU);
64314: goto endlabel3541;
64315: }
64316: {{ uae_s16 src = get_word(srca);
64317: { uae_s16 dst = m68k_dreg(regs, dstreg);
64318: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64319: uae_u32 src2;
64320: CLEAR_CZNV;
64321: SET_ZFLG (((uae_s32)(newv)) == 0);
64322: SET_NFLG (((uae_s32)(newv)) < 0);
64323: m68k_dreg(regs, dstreg) = (newv);
64324: src2 = ((uae_u32)src) << 1;
64325: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64326: }}}}}}m68k_incpc(6);
64327: fill_prefetch_0 ();
64328: endlabel3541: ;
64329: return (50+retcycles*2);
64330: }
64331: unsigned long REGPARAM2 CPUFUNC(op_c1fa_5)(uae_u32 opcode) /* MULS */
64332: {
64333: uae_u32 dstreg = (opcode >> 9) & 7;
64334: unsigned int retcycles = 0;
64335: OpcodeFamily = 63; CurrentInstrCycles = 46;
64336: {{ uaecptr srca = m68k_getpc () + 2;
64337: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
64338: if ((srca & 1) != 0) {
64339: last_fault_for_exception_3 = srca;
64340: last_op_for_exception_3 = opcode;
64341: last_addr_for_exception_3 = m68k_getpc() + 4;
64342: Exception(3, 0, M68000_EXC_SRC_CPU);
64343: goto endlabel3542;
64344: }
64345: {{ uae_s16 src = get_word(srca);
64346: { uae_s16 dst = m68k_dreg(regs, dstreg);
64347: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64348: uae_u32 src2;
64349: CLEAR_CZNV;
64350: SET_ZFLG (((uae_s32)(newv)) == 0);
64351: SET_NFLG (((uae_s32)(newv)) < 0);
64352: m68k_dreg(regs, dstreg) = (newv);
64353: src2 = ((uae_u32)src) << 1;
64354: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64355: }}}}}}m68k_incpc(4);
64356: fill_prefetch_0 ();
64357: endlabel3542: ;
64358: return (46+retcycles*2);
64359: }
64360: unsigned long REGPARAM2 CPUFUNC(op_c1fb_5)(uae_u32 opcode) /* MULS */
64361: {
64362: uae_u32 dstreg = (opcode >> 9) & 7;
64363: unsigned int retcycles = 0;
64364: OpcodeFamily = 63; CurrentInstrCycles = 48;
64365: {{ uaecptr tmppc = m68k_getpc() + 2;
64366: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
64367: BusCyclePenalty += 2;
64368: if ((srca & 1) != 0) {
64369: last_fault_for_exception_3 = srca;
64370: last_op_for_exception_3 = opcode;
64371: last_addr_for_exception_3 = m68k_getpc() + 4;
64372: Exception(3, 0, M68000_EXC_SRC_CPU);
64373: goto endlabel3543;
64374: }
64375: {{ uae_s16 src = get_word(srca);
64376: { uae_s16 dst = m68k_dreg(regs, dstreg);
64377: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64378: uae_u32 src2;
64379: CLEAR_CZNV;
64380: SET_ZFLG (((uae_s32)(newv)) == 0);
64381: SET_NFLG (((uae_s32)(newv)) < 0);
64382: m68k_dreg(regs, dstreg) = (newv);
64383: src2 = ((uae_u32)src) << 1;
64384: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64385: }}}}}}m68k_incpc(4);
64386: fill_prefetch_0 ();
64387: endlabel3543: ;
64388: return (48+retcycles*2);
64389: }
64390: unsigned long REGPARAM2 CPUFUNC(op_c1fc_5)(uae_u32 opcode) /* MULS */
64391: {
64392: uae_u32 dstreg = (opcode >> 9) & 7;
64393: unsigned int retcycles = 0;
64394: OpcodeFamily = 63; CurrentInstrCycles = 42;
64395: {{ uae_s16 src = get_iword_prefetch(2);
64396: { uae_s16 dst = m68k_dreg(regs, dstreg);
64397: { uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
64398: uae_u32 src2;
64399: CLEAR_CZNV;
64400: SET_ZFLG (((uae_s32)(newv)) == 0);
64401: SET_NFLG (((uae_s32)(newv)) < 0);
64402: m68k_dreg(regs, dstreg) = (newv);
64403: src2 = ((uae_u32)src) << 1;
64404: while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
64405: }}}}m68k_incpc(4);
64406: fill_prefetch_0 ();
64407: return (42+retcycles*2);
64408: }
64409: unsigned long REGPARAM2 CPUFUNC(op_d000_5)(uae_u32 opcode) /* ADD */
64410: {
64411: uae_u32 srcreg = (opcode & 7);
64412: uae_u32 dstreg = (opcode >> 9) & 7;
64413: OpcodeFamily = 11; CurrentInstrCycles = 4;
64414: {{ uae_s8 src = m68k_dreg(regs, srcreg);
64415: { uae_s8 dst = m68k_dreg(regs, dstreg);
64416: { refill_prefetch (m68k_getpc(), 2);
64417: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64418: { int flgs = ((uae_s8)(src)) < 0;
64419: int flgo = ((uae_s8)(dst)) < 0;
64420: int flgn = ((uae_s8)(newv)) < 0;
64421: SET_ZFLG (((uae_s8)(newv)) == 0);
64422: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64423: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64424: COPY_CARRY;
64425: SET_NFLG (flgn != 0);
64426: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64427: }}}}}}m68k_incpc(2);
64428: fill_prefetch_2 ();
64429: return 4;
64430: }
64431: unsigned long REGPARAM2 CPUFUNC(op_d010_5)(uae_u32 opcode) /* ADD */
64432: {
64433: uae_u32 srcreg = (opcode & 7);
64434: uae_u32 dstreg = (opcode >> 9) & 7;
64435: OpcodeFamily = 11; CurrentInstrCycles = 8;
64436: {{ uaecptr srca = m68k_areg(regs, srcreg);
64437: { uae_s8 src = get_byte(srca);
64438: { uae_s8 dst = m68k_dreg(regs, dstreg);
64439: { refill_prefetch (m68k_getpc(), 2);
64440: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64441: { int flgs = ((uae_s8)(src)) < 0;
64442: int flgo = ((uae_s8)(dst)) < 0;
64443: int flgn = ((uae_s8)(newv)) < 0;
64444: SET_ZFLG (((uae_s8)(newv)) == 0);
64445: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64446: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64447: COPY_CARRY;
64448: SET_NFLG (flgn != 0);
64449: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64450: }}}}}}}m68k_incpc(2);
64451: fill_prefetch_2 ();
64452: return 8;
64453: }
64454: unsigned long REGPARAM2 CPUFUNC(op_d018_5)(uae_u32 opcode) /* ADD */
64455: {
64456: uae_u32 srcreg = (opcode & 7);
64457: uae_u32 dstreg = (opcode >> 9) & 7;
64458: OpcodeFamily = 11; CurrentInstrCycles = 8;
64459: {{ uaecptr srca = m68k_areg(regs, srcreg);
64460: { uae_s8 src = get_byte(srca);
64461: m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
64462: { uae_s8 dst = m68k_dreg(regs, dstreg);
64463: { refill_prefetch (m68k_getpc(), 2);
64464: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64465: { int flgs = ((uae_s8)(src)) < 0;
64466: int flgo = ((uae_s8)(dst)) < 0;
64467: int flgn = ((uae_s8)(newv)) < 0;
64468: SET_ZFLG (((uae_s8)(newv)) == 0);
64469: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64470: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64471: COPY_CARRY;
64472: SET_NFLG (flgn != 0);
64473: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64474: }}}}}}}m68k_incpc(2);
64475: fill_prefetch_2 ();
64476: return 8;
64477: }
64478: unsigned long REGPARAM2 CPUFUNC(op_d020_5)(uae_u32 opcode) /* ADD */
64479: {
64480: uae_u32 srcreg = (opcode & 7);
64481: uae_u32 dstreg = (opcode >> 9) & 7;
64482: OpcodeFamily = 11; CurrentInstrCycles = 10;
64483: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
64484: { uae_s8 src = get_byte(srca);
64485: m68k_areg (regs, srcreg) = srca;
64486: { uae_s8 dst = m68k_dreg(regs, dstreg);
64487: { refill_prefetch (m68k_getpc(), 2);
64488: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64489: { int flgs = ((uae_s8)(src)) < 0;
64490: int flgo = ((uae_s8)(dst)) < 0;
64491: int flgn = ((uae_s8)(newv)) < 0;
64492: SET_ZFLG (((uae_s8)(newv)) == 0);
64493: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64494: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64495: COPY_CARRY;
64496: SET_NFLG (flgn != 0);
64497: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64498: }}}}}}}m68k_incpc(2);
64499: fill_prefetch_2 ();
64500: return 10;
64501: }
64502: unsigned long REGPARAM2 CPUFUNC(op_d028_5)(uae_u32 opcode) /* ADD */
64503: {
64504: uae_u32 srcreg = (opcode & 7);
64505: uae_u32 dstreg = (opcode >> 9) & 7;
64506: OpcodeFamily = 11; CurrentInstrCycles = 12;
64507: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
64508: { uae_s8 src = get_byte(srca);
64509: { uae_s8 dst = m68k_dreg(regs, dstreg);
64510: { refill_prefetch (m68k_getpc(), 2);
64511: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64512: { int flgs = ((uae_s8)(src)) < 0;
64513: int flgo = ((uae_s8)(dst)) < 0;
64514: int flgn = ((uae_s8)(newv)) < 0;
64515: SET_ZFLG (((uae_s8)(newv)) == 0);
64516: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64517: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64518: COPY_CARRY;
64519: SET_NFLG (flgn != 0);
64520: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64521: }}}}}}}m68k_incpc(4);
64522: fill_prefetch_0 ();
64523: return 12;
64524: }
64525: unsigned long REGPARAM2 CPUFUNC(op_d030_5)(uae_u32 opcode) /* ADD */
64526: {
64527: uae_u32 srcreg = (opcode & 7);
64528: uae_u32 dstreg = (opcode >> 9) & 7;
64529: OpcodeFamily = 11; CurrentInstrCycles = 14;
64530: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
64531: BusCyclePenalty += 2;
64532: { uae_s8 src = get_byte(srca);
64533: { uae_s8 dst = m68k_dreg(regs, dstreg);
64534: { refill_prefetch (m68k_getpc(), 2);
64535: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64536: { int flgs = ((uae_s8)(src)) < 0;
64537: int flgo = ((uae_s8)(dst)) < 0;
64538: int flgn = ((uae_s8)(newv)) < 0;
64539: SET_ZFLG (((uae_s8)(newv)) == 0);
64540: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64541: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64542: COPY_CARRY;
64543: SET_NFLG (flgn != 0);
64544: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64545: }}}}}}}m68k_incpc(4);
64546: fill_prefetch_0 ();
64547: return 14;
64548: }
64549: unsigned long REGPARAM2 CPUFUNC(op_d038_5)(uae_u32 opcode) /* ADD */
64550: {
64551: uae_u32 dstreg = (opcode >> 9) & 7;
64552: OpcodeFamily = 11; CurrentInstrCycles = 12;
64553: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
64554: { uae_s8 src = get_byte(srca);
64555: { uae_s8 dst = m68k_dreg(regs, dstreg);
64556: { refill_prefetch (m68k_getpc(), 2);
64557: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64558: { int flgs = ((uae_s8)(src)) < 0;
64559: int flgo = ((uae_s8)(dst)) < 0;
64560: int flgn = ((uae_s8)(newv)) < 0;
64561: SET_ZFLG (((uae_s8)(newv)) == 0);
64562: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64563: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64564: COPY_CARRY;
64565: SET_NFLG (flgn != 0);
64566: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64567: }}}}}}}m68k_incpc(4);
64568: fill_prefetch_0 ();
64569: return 12;
64570: }
64571: unsigned long REGPARAM2 CPUFUNC(op_d039_5)(uae_u32 opcode) /* ADD */
64572: {
64573: uae_u32 dstreg = (opcode >> 9) & 7;
64574: OpcodeFamily = 11; CurrentInstrCycles = 16;
64575: {{ uaecptr srca = get_ilong_prefetch(2);
64576: { uae_s8 src = get_byte(srca);
64577: { uae_s8 dst = m68k_dreg(regs, dstreg);
64578: { refill_prefetch (m68k_getpc(), 2);
64579: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64580: { int flgs = ((uae_s8)(src)) < 0;
64581: int flgo = ((uae_s8)(dst)) < 0;
64582: int flgn = ((uae_s8)(newv)) < 0;
64583: SET_ZFLG (((uae_s8)(newv)) == 0);
64584: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64585: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64586: COPY_CARRY;
64587: SET_NFLG (flgn != 0);
64588: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64589: }}}}}}}m68k_incpc(6);
64590: fill_prefetch_0 ();
64591: return 16;
64592: }
64593: unsigned long REGPARAM2 CPUFUNC(op_d03a_5)(uae_u32 opcode) /* ADD */
64594: {
64595: uae_u32 dstreg = (opcode >> 9) & 7;
64596: OpcodeFamily = 11; CurrentInstrCycles = 12;
64597: {{ uaecptr srca = m68k_getpc () + 2;
64598: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
64599: { uae_s8 src = get_byte(srca);
64600: { uae_s8 dst = m68k_dreg(regs, dstreg);
64601: { refill_prefetch (m68k_getpc(), 2);
64602: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64603: { int flgs = ((uae_s8)(src)) < 0;
64604: int flgo = ((uae_s8)(dst)) < 0;
64605: int flgn = ((uae_s8)(newv)) < 0;
64606: SET_ZFLG (((uae_s8)(newv)) == 0);
64607: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64608: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64609: COPY_CARRY;
64610: SET_NFLG (flgn != 0);
64611: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64612: }}}}}}}m68k_incpc(4);
64613: fill_prefetch_0 ();
64614: return 12;
64615: }
64616: unsigned long REGPARAM2 CPUFUNC(op_d03b_5)(uae_u32 opcode) /* ADD */
64617: {
64618: uae_u32 dstreg = (opcode >> 9) & 7;
64619: OpcodeFamily = 11; CurrentInstrCycles = 14;
64620: {{ uaecptr tmppc = m68k_getpc() + 2;
64621: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
64622: BusCyclePenalty += 2;
64623: { uae_s8 src = get_byte(srca);
64624: { uae_s8 dst = m68k_dreg(regs, dstreg);
64625: { refill_prefetch (m68k_getpc(), 2);
64626: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64627: { int flgs = ((uae_s8)(src)) < 0;
64628: int flgo = ((uae_s8)(dst)) < 0;
64629: int flgn = ((uae_s8)(newv)) < 0;
64630: SET_ZFLG (((uae_s8)(newv)) == 0);
64631: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64632: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64633: COPY_CARRY;
64634: SET_NFLG (flgn != 0);
64635: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64636: }}}}}}}m68k_incpc(4);
64637: fill_prefetch_0 ();
64638: return 14;
64639: }
64640: unsigned long REGPARAM2 CPUFUNC(op_d03c_5)(uae_u32 opcode) /* ADD */
64641: {
64642: uae_u32 dstreg = (opcode >> 9) & 7;
64643: OpcodeFamily = 11; CurrentInstrCycles = 8;
64644: {{ uae_s8 src = get_ibyte_prefetch(2);
64645: { uae_s8 dst = m68k_dreg(regs, dstreg);
64646: { refill_prefetch (m68k_getpc(), 2);
64647: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
64648: { int flgs = ((uae_s8)(src)) < 0;
64649: int flgo = ((uae_s8)(dst)) < 0;
64650: int flgn = ((uae_s8)(newv)) < 0;
64651: SET_ZFLG (((uae_s8)(newv)) == 0);
64652: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64653: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
64654: COPY_CARRY;
64655: SET_NFLG (flgn != 0);
64656: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
64657: }}}}}}m68k_incpc(4);
64658: fill_prefetch_0 ();
64659: return 8;
64660: }
64661: unsigned long REGPARAM2 CPUFUNC(op_d040_5)(uae_u32 opcode) /* ADD */
64662: {
64663: uae_u32 srcreg = (opcode & 7);
64664: uae_u32 dstreg = (opcode >> 9) & 7;
64665: OpcodeFamily = 11; CurrentInstrCycles = 4;
64666: {{ uae_s16 src = m68k_dreg(regs, srcreg);
64667: { uae_s16 dst = m68k_dreg(regs, dstreg);
64668: { refill_prefetch (m68k_getpc(), 2);
64669: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64670: { int flgs = ((uae_s16)(src)) < 0;
64671: int flgo = ((uae_s16)(dst)) < 0;
64672: int flgn = ((uae_s16)(newv)) < 0;
64673: SET_ZFLG (((uae_s16)(newv)) == 0);
64674: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64675: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64676: COPY_CARRY;
64677: SET_NFLG (flgn != 0);
64678: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64679: }}}}}}m68k_incpc(2);
64680: fill_prefetch_2 ();
64681: return 4;
64682: }
64683: unsigned long REGPARAM2 CPUFUNC(op_d048_5)(uae_u32 opcode) /* ADD */
64684: {
64685: uae_u32 srcreg = (opcode & 7);
64686: uae_u32 dstreg = (opcode >> 9) & 7;
64687: OpcodeFamily = 11; CurrentInstrCycles = 4;
64688: {{ uae_s16 src = m68k_areg(regs, srcreg);
64689: { uae_s16 dst = m68k_dreg(regs, dstreg);
64690: { refill_prefetch (m68k_getpc(), 2);
64691: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64692: { int flgs = ((uae_s16)(src)) < 0;
64693: int flgo = ((uae_s16)(dst)) < 0;
64694: int flgn = ((uae_s16)(newv)) < 0;
64695: SET_ZFLG (((uae_s16)(newv)) == 0);
64696: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64697: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64698: COPY_CARRY;
64699: SET_NFLG (flgn != 0);
64700: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64701: }}}}}}m68k_incpc(2);
64702: fill_prefetch_2 ();
64703: return 4;
64704: }
64705: unsigned long REGPARAM2 CPUFUNC(op_d050_5)(uae_u32 opcode) /* ADD */
64706: {
64707: uae_u32 srcreg = (opcode & 7);
64708: uae_u32 dstreg = (opcode >> 9) & 7;
64709: OpcodeFamily = 11; CurrentInstrCycles = 8;
64710: {{ uaecptr srca = m68k_areg(regs, srcreg);
64711: if ((srca & 1) != 0) {
64712: last_fault_for_exception_3 = srca;
64713: last_op_for_exception_3 = opcode;
64714: last_addr_for_exception_3 = m68k_getpc() + 2;
64715: Exception(3, 0, M68000_EXC_SRC_CPU);
64716: goto endlabel3558;
64717: }
64718: {{ uae_s16 src = get_word(srca);
64719: { uae_s16 dst = m68k_dreg(regs, dstreg);
64720: { refill_prefetch (m68k_getpc(), 2);
64721: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64722: { int flgs = ((uae_s16)(src)) < 0;
64723: int flgo = ((uae_s16)(dst)) < 0;
64724: int flgn = ((uae_s16)(newv)) < 0;
64725: SET_ZFLG (((uae_s16)(newv)) == 0);
64726: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64727: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64728: COPY_CARRY;
64729: SET_NFLG (flgn != 0);
64730: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64731: }}}}}}}}m68k_incpc(2);
64732: fill_prefetch_2 ();
64733: endlabel3558: ;
64734: return 8;
64735: }
64736: unsigned long REGPARAM2 CPUFUNC(op_d058_5)(uae_u32 opcode) /* ADD */
64737: {
64738: uae_u32 srcreg = (opcode & 7);
64739: uae_u32 dstreg = (opcode >> 9) & 7;
64740: OpcodeFamily = 11; CurrentInstrCycles = 8;
64741: {{ uaecptr srca = m68k_areg(regs, srcreg);
64742: if ((srca & 1) != 0) {
64743: last_fault_for_exception_3 = srca;
64744: last_op_for_exception_3 = opcode;
64745: last_addr_for_exception_3 = m68k_getpc() + 2;
64746: Exception(3, 0, M68000_EXC_SRC_CPU);
64747: goto endlabel3559;
64748: }
64749: {{ uae_s16 src = get_word(srca);
64750: m68k_areg(regs, srcreg) += 2;
64751: { uae_s16 dst = m68k_dreg(regs, dstreg);
64752: { refill_prefetch (m68k_getpc(), 2);
64753: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64754: { int flgs = ((uae_s16)(src)) < 0;
64755: int flgo = ((uae_s16)(dst)) < 0;
64756: int flgn = ((uae_s16)(newv)) < 0;
64757: SET_ZFLG (((uae_s16)(newv)) == 0);
64758: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64759: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64760: COPY_CARRY;
64761: SET_NFLG (flgn != 0);
64762: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64763: }}}}}}}}m68k_incpc(2);
64764: fill_prefetch_2 ();
64765: endlabel3559: ;
64766: return 8;
64767: }
64768: unsigned long REGPARAM2 CPUFUNC(op_d060_5)(uae_u32 opcode) /* ADD */
64769: {
64770: uae_u32 srcreg = (opcode & 7);
64771: uae_u32 dstreg = (opcode >> 9) & 7;
64772: OpcodeFamily = 11; CurrentInstrCycles = 10;
64773: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
64774: if ((srca & 1) != 0) {
64775: last_fault_for_exception_3 = srca;
64776: last_op_for_exception_3 = opcode;
64777: last_addr_for_exception_3 = m68k_getpc() + 2;
64778: Exception(3, 0, M68000_EXC_SRC_CPU);
64779: goto endlabel3560;
64780: }
64781: {{ uae_s16 src = get_word(srca);
64782: m68k_areg (regs, srcreg) = srca;
64783: { uae_s16 dst = m68k_dreg(regs, dstreg);
64784: { refill_prefetch (m68k_getpc(), 2);
64785: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64786: { int flgs = ((uae_s16)(src)) < 0;
64787: int flgo = ((uae_s16)(dst)) < 0;
64788: int flgn = ((uae_s16)(newv)) < 0;
64789: SET_ZFLG (((uae_s16)(newv)) == 0);
64790: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64791: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64792: COPY_CARRY;
64793: SET_NFLG (flgn != 0);
64794: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64795: }}}}}}}}m68k_incpc(2);
64796: fill_prefetch_2 ();
64797: endlabel3560: ;
64798: return 10;
64799: }
64800: unsigned long REGPARAM2 CPUFUNC(op_d068_5)(uae_u32 opcode) /* ADD */
64801: {
64802: uae_u32 srcreg = (opcode & 7);
64803: uae_u32 dstreg = (opcode >> 9) & 7;
64804: OpcodeFamily = 11; CurrentInstrCycles = 12;
64805: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
64806: if ((srca & 1) != 0) {
64807: last_fault_for_exception_3 = srca;
64808: last_op_for_exception_3 = opcode;
64809: last_addr_for_exception_3 = m68k_getpc() + 4;
64810: Exception(3, 0, M68000_EXC_SRC_CPU);
64811: goto endlabel3561;
64812: }
64813: {{ uae_s16 src = get_word(srca);
64814: { uae_s16 dst = m68k_dreg(regs, dstreg);
64815: { refill_prefetch (m68k_getpc(), 2);
64816: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64817: { int flgs = ((uae_s16)(src)) < 0;
64818: int flgo = ((uae_s16)(dst)) < 0;
64819: int flgn = ((uae_s16)(newv)) < 0;
64820: SET_ZFLG (((uae_s16)(newv)) == 0);
64821: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64822: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64823: COPY_CARRY;
64824: SET_NFLG (flgn != 0);
64825: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64826: }}}}}}}}m68k_incpc(4);
64827: fill_prefetch_0 ();
64828: endlabel3561: ;
64829: return 12;
64830: }
64831: unsigned long REGPARAM2 CPUFUNC(op_d070_5)(uae_u32 opcode) /* ADD */
64832: {
64833: uae_u32 srcreg = (opcode & 7);
64834: uae_u32 dstreg = (opcode >> 9) & 7;
64835: OpcodeFamily = 11; CurrentInstrCycles = 14;
64836: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
64837: BusCyclePenalty += 2;
64838: if ((srca & 1) != 0) {
64839: last_fault_for_exception_3 = srca;
64840: last_op_for_exception_3 = opcode;
64841: last_addr_for_exception_3 = m68k_getpc() + 4;
64842: Exception(3, 0, M68000_EXC_SRC_CPU);
64843: goto endlabel3562;
64844: }
64845: {{ uae_s16 src = get_word(srca);
64846: { uae_s16 dst = m68k_dreg(regs, dstreg);
64847: { refill_prefetch (m68k_getpc(), 2);
64848: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64849: { int flgs = ((uae_s16)(src)) < 0;
64850: int flgo = ((uae_s16)(dst)) < 0;
64851: int flgn = ((uae_s16)(newv)) < 0;
64852: SET_ZFLG (((uae_s16)(newv)) == 0);
64853: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64854: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64855: COPY_CARRY;
64856: SET_NFLG (flgn != 0);
64857: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64858: }}}}}}}}m68k_incpc(4);
64859: fill_prefetch_0 ();
64860: endlabel3562: ;
64861: return 14;
64862: }
64863: unsigned long REGPARAM2 CPUFUNC(op_d078_5)(uae_u32 opcode) /* ADD */
64864: {
64865: uae_u32 dstreg = (opcode >> 9) & 7;
64866: OpcodeFamily = 11; CurrentInstrCycles = 12;
64867: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
64868: if ((srca & 1) != 0) {
64869: last_fault_for_exception_3 = srca;
64870: last_op_for_exception_3 = opcode;
64871: last_addr_for_exception_3 = m68k_getpc() + 4;
64872: Exception(3, 0, M68000_EXC_SRC_CPU);
64873: goto endlabel3563;
64874: }
64875: {{ uae_s16 src = get_word(srca);
64876: { uae_s16 dst = m68k_dreg(regs, dstreg);
64877: { refill_prefetch (m68k_getpc(), 2);
64878: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64879: { int flgs = ((uae_s16)(src)) < 0;
64880: int flgo = ((uae_s16)(dst)) < 0;
64881: int flgn = ((uae_s16)(newv)) < 0;
64882: SET_ZFLG (((uae_s16)(newv)) == 0);
64883: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64884: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64885: COPY_CARRY;
64886: SET_NFLG (flgn != 0);
64887: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64888: }}}}}}}}m68k_incpc(4);
64889: fill_prefetch_0 ();
64890: endlabel3563: ;
64891: return 12;
64892: }
64893: unsigned long REGPARAM2 CPUFUNC(op_d079_5)(uae_u32 opcode) /* ADD */
64894: {
64895: uae_u32 dstreg = (opcode >> 9) & 7;
64896: OpcodeFamily = 11; CurrentInstrCycles = 16;
64897: {{ uaecptr srca = get_ilong_prefetch(2);
64898: if ((srca & 1) != 0) {
64899: last_fault_for_exception_3 = srca;
64900: last_op_for_exception_3 = opcode;
64901: last_addr_for_exception_3 = m68k_getpc() + 6;
64902: Exception(3, 0, M68000_EXC_SRC_CPU);
64903: goto endlabel3564;
64904: }
64905: {{ uae_s16 src = get_word(srca);
64906: { uae_s16 dst = m68k_dreg(regs, dstreg);
64907: { refill_prefetch (m68k_getpc(), 2);
64908: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64909: { int flgs = ((uae_s16)(src)) < 0;
64910: int flgo = ((uae_s16)(dst)) < 0;
64911: int flgn = ((uae_s16)(newv)) < 0;
64912: SET_ZFLG (((uae_s16)(newv)) == 0);
64913: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64914: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64915: COPY_CARRY;
64916: SET_NFLG (flgn != 0);
64917: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64918: }}}}}}}}m68k_incpc(6);
64919: fill_prefetch_0 ();
64920: endlabel3564: ;
64921: return 16;
64922: }
64923: unsigned long REGPARAM2 CPUFUNC(op_d07a_5)(uae_u32 opcode) /* ADD */
64924: {
64925: uae_u32 dstreg = (opcode >> 9) & 7;
64926: OpcodeFamily = 11; CurrentInstrCycles = 12;
64927: {{ uaecptr srca = m68k_getpc () + 2;
64928: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
64929: if ((srca & 1) != 0) {
64930: last_fault_for_exception_3 = srca;
64931: last_op_for_exception_3 = opcode;
64932: last_addr_for_exception_3 = m68k_getpc() + 4;
64933: Exception(3, 0, M68000_EXC_SRC_CPU);
64934: goto endlabel3565;
64935: }
64936: {{ uae_s16 src = get_word(srca);
64937: { uae_s16 dst = m68k_dreg(regs, dstreg);
64938: { refill_prefetch (m68k_getpc(), 2);
64939: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64940: { int flgs = ((uae_s16)(src)) < 0;
64941: int flgo = ((uae_s16)(dst)) < 0;
64942: int flgn = ((uae_s16)(newv)) < 0;
64943: SET_ZFLG (((uae_s16)(newv)) == 0);
64944: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64945: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64946: COPY_CARRY;
64947: SET_NFLG (flgn != 0);
64948: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64949: }}}}}}}}m68k_incpc(4);
64950: fill_prefetch_0 ();
64951: endlabel3565: ;
64952: return 12;
64953: }
64954: unsigned long REGPARAM2 CPUFUNC(op_d07b_5)(uae_u32 opcode) /* ADD */
64955: {
64956: uae_u32 dstreg = (opcode >> 9) & 7;
64957: OpcodeFamily = 11; CurrentInstrCycles = 14;
64958: {{ uaecptr tmppc = m68k_getpc() + 2;
64959: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
64960: BusCyclePenalty += 2;
64961: if ((srca & 1) != 0) {
64962: last_fault_for_exception_3 = srca;
64963: last_op_for_exception_3 = opcode;
64964: last_addr_for_exception_3 = m68k_getpc() + 4;
64965: Exception(3, 0, M68000_EXC_SRC_CPU);
64966: goto endlabel3566;
64967: }
64968: {{ uae_s16 src = get_word(srca);
64969: { uae_s16 dst = m68k_dreg(regs, dstreg);
64970: { refill_prefetch (m68k_getpc(), 2);
64971: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64972: { int flgs = ((uae_s16)(src)) < 0;
64973: int flgo = ((uae_s16)(dst)) < 0;
64974: int flgn = ((uae_s16)(newv)) < 0;
64975: SET_ZFLG (((uae_s16)(newv)) == 0);
64976: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64977: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
64978: COPY_CARRY;
64979: SET_NFLG (flgn != 0);
64980: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
64981: }}}}}}}}m68k_incpc(4);
64982: fill_prefetch_0 ();
64983: endlabel3566: ;
64984: return 14;
64985: }
64986: unsigned long REGPARAM2 CPUFUNC(op_d07c_5)(uae_u32 opcode) /* ADD */
64987: {
64988: uae_u32 dstreg = (opcode >> 9) & 7;
64989: OpcodeFamily = 11; CurrentInstrCycles = 8;
64990: {{ uae_s16 src = get_iword_prefetch(2);
64991: { uae_s16 dst = m68k_dreg(regs, dstreg);
64992: { refill_prefetch (m68k_getpc(), 2);
64993: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
64994: { int flgs = ((uae_s16)(src)) < 0;
64995: int flgo = ((uae_s16)(dst)) < 0;
64996: int flgn = ((uae_s16)(newv)) < 0;
64997: SET_ZFLG (((uae_s16)(newv)) == 0);
64998: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
64999: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
65000: COPY_CARRY;
65001: SET_NFLG (flgn != 0);
65002: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
65003: }}}}}}m68k_incpc(4);
65004: fill_prefetch_0 ();
65005: return 8;
65006: }
65007: unsigned long REGPARAM2 CPUFUNC(op_d080_5)(uae_u32 opcode) /* ADD */
65008: {
65009: uae_u32 srcreg = (opcode & 7);
65010: uae_u32 dstreg = (opcode >> 9) & 7;
65011: OpcodeFamily = 11; CurrentInstrCycles = 8;
65012: {{ uae_s32 src = m68k_dreg(regs, srcreg);
65013: { uae_s32 dst = m68k_dreg(regs, dstreg);
65014: { refill_prefetch (m68k_getpc(), 2);
65015: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65016: { int flgs = ((uae_s32)(src)) < 0;
65017: int flgo = ((uae_s32)(dst)) < 0;
65018: int flgn = ((uae_s32)(newv)) < 0;
65019: SET_ZFLG (((uae_s32)(newv)) == 0);
65020: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65021: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65022: COPY_CARRY;
65023: SET_NFLG (flgn != 0);
65024: m68k_dreg(regs, dstreg) = (newv);
65025: }}}}}}m68k_incpc(2);
65026: fill_prefetch_2 ();
65027: return 8;
65028: }
65029: unsigned long REGPARAM2 CPUFUNC(op_d088_5)(uae_u32 opcode) /* ADD */
65030: {
65031: uae_u32 srcreg = (opcode & 7);
65032: uae_u32 dstreg = (opcode >> 9) & 7;
65033: OpcodeFamily = 11; CurrentInstrCycles = 8;
65034: {{ uae_s32 src = m68k_areg(regs, srcreg);
65035: { uae_s32 dst = m68k_dreg(regs, dstreg);
65036: { refill_prefetch (m68k_getpc(), 2);
65037: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65038: { int flgs = ((uae_s32)(src)) < 0;
65039: int flgo = ((uae_s32)(dst)) < 0;
65040: int flgn = ((uae_s32)(newv)) < 0;
65041: SET_ZFLG (((uae_s32)(newv)) == 0);
65042: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65043: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65044: COPY_CARRY;
65045: SET_NFLG (flgn != 0);
65046: m68k_dreg(regs, dstreg) = (newv);
65047: }}}}}}m68k_incpc(2);
65048: fill_prefetch_2 ();
65049: return 8;
65050: }
65051: unsigned long REGPARAM2 CPUFUNC(op_d090_5)(uae_u32 opcode) /* ADD */
65052: {
65053: uae_u32 srcreg = (opcode & 7);
65054: uae_u32 dstreg = (opcode >> 9) & 7;
65055: OpcodeFamily = 11; CurrentInstrCycles = 14;
65056: {{ uaecptr srca = m68k_areg(regs, srcreg);
65057: if ((srca & 1) != 0) {
65058: last_fault_for_exception_3 = srca;
65059: last_op_for_exception_3 = opcode;
65060: last_addr_for_exception_3 = m68k_getpc() + 2;
65061: Exception(3, 0, M68000_EXC_SRC_CPU);
65062: goto endlabel3570;
65063: }
65064: {{ uae_s32 src = get_long(srca);
65065: { uae_s32 dst = m68k_dreg(regs, dstreg);
65066: { refill_prefetch (m68k_getpc(), 2);
65067: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65068: { int flgs = ((uae_s32)(src)) < 0;
65069: int flgo = ((uae_s32)(dst)) < 0;
65070: int flgn = ((uae_s32)(newv)) < 0;
65071: SET_ZFLG (((uae_s32)(newv)) == 0);
65072: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65073: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65074: COPY_CARRY;
65075: SET_NFLG (flgn != 0);
65076: m68k_dreg(regs, dstreg) = (newv);
65077: }}}}}}}}m68k_incpc(2);
65078: fill_prefetch_2 ();
65079: endlabel3570: ;
65080: return 14;
65081: }
65082: unsigned long REGPARAM2 CPUFUNC(op_d098_5)(uae_u32 opcode) /* ADD */
65083: {
65084: uae_u32 srcreg = (opcode & 7);
65085: uae_u32 dstreg = (opcode >> 9) & 7;
65086: OpcodeFamily = 11; CurrentInstrCycles = 14;
65087: {{ uaecptr srca = m68k_areg(regs, srcreg);
65088: if ((srca & 1) != 0) {
65089: last_fault_for_exception_3 = srca;
65090: last_op_for_exception_3 = opcode;
65091: last_addr_for_exception_3 = m68k_getpc() + 2;
65092: Exception(3, 0, M68000_EXC_SRC_CPU);
65093: goto endlabel3571;
65094: }
65095: {{ uae_s32 src = get_long(srca);
65096: m68k_areg(regs, srcreg) += 4;
65097: { uae_s32 dst = m68k_dreg(regs, dstreg);
65098: { refill_prefetch (m68k_getpc(), 2);
65099: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65100: { int flgs = ((uae_s32)(src)) < 0;
65101: int flgo = ((uae_s32)(dst)) < 0;
65102: int flgn = ((uae_s32)(newv)) < 0;
65103: SET_ZFLG (((uae_s32)(newv)) == 0);
65104: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65105: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65106: COPY_CARRY;
65107: SET_NFLG (flgn != 0);
65108: m68k_dreg(regs, dstreg) = (newv);
65109: }}}}}}}}m68k_incpc(2);
65110: fill_prefetch_2 ();
65111: endlabel3571: ;
65112: return 14;
65113: }
65114: unsigned long REGPARAM2 CPUFUNC(op_d0a0_5)(uae_u32 opcode) /* ADD */
65115: {
65116: uae_u32 srcreg = (opcode & 7);
65117: uae_u32 dstreg = (opcode >> 9) & 7;
65118: OpcodeFamily = 11; CurrentInstrCycles = 16;
65119: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
65120: if ((srca & 1) != 0) {
65121: last_fault_for_exception_3 = srca;
65122: last_op_for_exception_3 = opcode;
65123: last_addr_for_exception_3 = m68k_getpc() + 2;
65124: Exception(3, 0, M68000_EXC_SRC_CPU);
65125: goto endlabel3572;
65126: }
65127: {{ uae_s32 src = get_long(srca);
65128: m68k_areg (regs, srcreg) = srca;
65129: { uae_s32 dst = m68k_dreg(regs, dstreg);
65130: { refill_prefetch (m68k_getpc(), 2);
65131: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65132: { int flgs = ((uae_s32)(src)) < 0;
65133: int flgo = ((uae_s32)(dst)) < 0;
65134: int flgn = ((uae_s32)(newv)) < 0;
65135: SET_ZFLG (((uae_s32)(newv)) == 0);
65136: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65137: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65138: COPY_CARRY;
65139: SET_NFLG (flgn != 0);
65140: m68k_dreg(regs, dstreg) = (newv);
65141: }}}}}}}}m68k_incpc(2);
65142: fill_prefetch_2 ();
65143: endlabel3572: ;
65144: return 16;
65145: }
65146: unsigned long REGPARAM2 CPUFUNC(op_d0a8_5)(uae_u32 opcode) /* ADD */
65147: {
65148: uae_u32 srcreg = (opcode & 7);
65149: uae_u32 dstreg = (opcode >> 9) & 7;
65150: OpcodeFamily = 11; CurrentInstrCycles = 18;
65151: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
65152: if ((srca & 1) != 0) {
65153: last_fault_for_exception_3 = srca;
65154: last_op_for_exception_3 = opcode;
65155: last_addr_for_exception_3 = m68k_getpc() + 4;
65156: Exception(3, 0, M68000_EXC_SRC_CPU);
65157: goto endlabel3573;
65158: }
65159: {{ uae_s32 src = get_long(srca);
65160: { uae_s32 dst = m68k_dreg(regs, dstreg);
65161: { refill_prefetch (m68k_getpc(), 2);
65162: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65163: { int flgs = ((uae_s32)(src)) < 0;
65164: int flgo = ((uae_s32)(dst)) < 0;
65165: int flgn = ((uae_s32)(newv)) < 0;
65166: SET_ZFLG (((uae_s32)(newv)) == 0);
65167: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65168: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65169: COPY_CARRY;
65170: SET_NFLG (flgn != 0);
65171: m68k_dreg(regs, dstreg) = (newv);
65172: }}}}}}}}m68k_incpc(4);
65173: fill_prefetch_0 ();
65174: endlabel3573: ;
65175: return 18;
65176: }
65177: unsigned long REGPARAM2 CPUFUNC(op_d0b0_5)(uae_u32 opcode) /* ADD */
65178: {
65179: uae_u32 srcreg = (opcode & 7);
65180: uae_u32 dstreg = (opcode >> 9) & 7;
65181: OpcodeFamily = 11; CurrentInstrCycles = 20;
65182: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
65183: BusCyclePenalty += 2;
65184: if ((srca & 1) != 0) {
65185: last_fault_for_exception_3 = srca;
65186: last_op_for_exception_3 = opcode;
65187: last_addr_for_exception_3 = m68k_getpc() + 4;
65188: Exception(3, 0, M68000_EXC_SRC_CPU);
65189: goto endlabel3574;
65190: }
65191: {{ uae_s32 src = get_long(srca);
65192: { uae_s32 dst = m68k_dreg(regs, dstreg);
65193: { refill_prefetch (m68k_getpc(), 2);
65194: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65195: { int flgs = ((uae_s32)(src)) < 0;
65196: int flgo = ((uae_s32)(dst)) < 0;
65197: int flgn = ((uae_s32)(newv)) < 0;
65198: SET_ZFLG (((uae_s32)(newv)) == 0);
65199: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65200: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65201: COPY_CARRY;
65202: SET_NFLG (flgn != 0);
65203: m68k_dreg(regs, dstreg) = (newv);
65204: }}}}}}}}m68k_incpc(4);
65205: fill_prefetch_0 ();
65206: endlabel3574: ;
65207: return 20;
65208: }
65209: unsigned long REGPARAM2 CPUFUNC(op_d0b8_5)(uae_u32 opcode) /* ADD */
65210: {
65211: uae_u32 dstreg = (opcode >> 9) & 7;
65212: OpcodeFamily = 11; CurrentInstrCycles = 18;
65213: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
65214: if ((srca & 1) != 0) {
65215: last_fault_for_exception_3 = srca;
65216: last_op_for_exception_3 = opcode;
65217: last_addr_for_exception_3 = m68k_getpc() + 4;
65218: Exception(3, 0, M68000_EXC_SRC_CPU);
65219: goto endlabel3575;
65220: }
65221: {{ uae_s32 src = get_long(srca);
65222: { uae_s32 dst = m68k_dreg(regs, dstreg);
65223: { refill_prefetch (m68k_getpc(), 2);
65224: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65225: { int flgs = ((uae_s32)(src)) < 0;
65226: int flgo = ((uae_s32)(dst)) < 0;
65227: int flgn = ((uae_s32)(newv)) < 0;
65228: SET_ZFLG (((uae_s32)(newv)) == 0);
65229: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65230: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65231: COPY_CARRY;
65232: SET_NFLG (flgn != 0);
65233: m68k_dreg(regs, dstreg) = (newv);
65234: }}}}}}}}m68k_incpc(4);
65235: fill_prefetch_0 ();
65236: endlabel3575: ;
65237: return 18;
65238: }
65239: unsigned long REGPARAM2 CPUFUNC(op_d0b9_5)(uae_u32 opcode) /* ADD */
65240: {
65241: uae_u32 dstreg = (opcode >> 9) & 7;
65242: OpcodeFamily = 11; CurrentInstrCycles = 22;
65243: {{ uaecptr srca = get_ilong_prefetch(2);
65244: if ((srca & 1) != 0) {
65245: last_fault_for_exception_3 = srca;
65246: last_op_for_exception_3 = opcode;
65247: last_addr_for_exception_3 = m68k_getpc() + 6;
65248: Exception(3, 0, M68000_EXC_SRC_CPU);
65249: goto endlabel3576;
65250: }
65251: {{ uae_s32 src = get_long(srca);
65252: { uae_s32 dst = m68k_dreg(regs, dstreg);
65253: { refill_prefetch (m68k_getpc(), 2);
65254: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65255: { int flgs = ((uae_s32)(src)) < 0;
65256: int flgo = ((uae_s32)(dst)) < 0;
65257: int flgn = ((uae_s32)(newv)) < 0;
65258: SET_ZFLG (((uae_s32)(newv)) == 0);
65259: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65260: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65261: COPY_CARRY;
65262: SET_NFLG (flgn != 0);
65263: m68k_dreg(regs, dstreg) = (newv);
65264: }}}}}}}}m68k_incpc(6);
65265: fill_prefetch_0 ();
65266: endlabel3576: ;
65267: return 22;
65268: }
65269: unsigned long REGPARAM2 CPUFUNC(op_d0ba_5)(uae_u32 opcode) /* ADD */
65270: {
65271: uae_u32 dstreg = (opcode >> 9) & 7;
65272: OpcodeFamily = 11; CurrentInstrCycles = 18;
65273: {{ uaecptr srca = m68k_getpc () + 2;
65274: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
65275: if ((srca & 1) != 0) {
65276: last_fault_for_exception_3 = srca;
65277: last_op_for_exception_3 = opcode;
65278: last_addr_for_exception_3 = m68k_getpc() + 4;
65279: Exception(3, 0, M68000_EXC_SRC_CPU);
65280: goto endlabel3577;
65281: }
65282: {{ uae_s32 src = get_long(srca);
65283: { uae_s32 dst = m68k_dreg(regs, dstreg);
65284: { refill_prefetch (m68k_getpc(), 2);
65285: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65286: { int flgs = ((uae_s32)(src)) < 0;
65287: int flgo = ((uae_s32)(dst)) < 0;
65288: int flgn = ((uae_s32)(newv)) < 0;
65289: SET_ZFLG (((uae_s32)(newv)) == 0);
65290: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65291: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65292: COPY_CARRY;
65293: SET_NFLG (flgn != 0);
65294: m68k_dreg(regs, dstreg) = (newv);
65295: }}}}}}}}m68k_incpc(4);
65296: fill_prefetch_0 ();
65297: endlabel3577: ;
65298: return 18;
65299: }
65300: unsigned long REGPARAM2 CPUFUNC(op_d0bb_5)(uae_u32 opcode) /* ADD */
65301: {
65302: uae_u32 dstreg = (opcode >> 9) & 7;
65303: OpcodeFamily = 11; CurrentInstrCycles = 20;
65304: {{ uaecptr tmppc = m68k_getpc() + 2;
65305: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
65306: BusCyclePenalty += 2;
65307: if ((srca & 1) != 0) {
65308: last_fault_for_exception_3 = srca;
65309: last_op_for_exception_3 = opcode;
65310: last_addr_for_exception_3 = m68k_getpc() + 4;
65311: Exception(3, 0, M68000_EXC_SRC_CPU);
65312: goto endlabel3578;
65313: }
65314: {{ uae_s32 src = get_long(srca);
65315: { uae_s32 dst = m68k_dreg(regs, dstreg);
65316: { refill_prefetch (m68k_getpc(), 2);
65317: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65318: { int flgs = ((uae_s32)(src)) < 0;
65319: int flgo = ((uae_s32)(dst)) < 0;
65320: int flgn = ((uae_s32)(newv)) < 0;
65321: SET_ZFLG (((uae_s32)(newv)) == 0);
65322: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65323: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65324: COPY_CARRY;
65325: SET_NFLG (flgn != 0);
65326: m68k_dreg(regs, dstreg) = (newv);
65327: }}}}}}}}m68k_incpc(4);
65328: fill_prefetch_0 ();
65329: endlabel3578: ;
65330: return 20;
65331: }
65332: unsigned long REGPARAM2 CPUFUNC(op_d0bc_5)(uae_u32 opcode) /* ADD */
65333: {
65334: uae_u32 dstreg = (opcode >> 9) & 7;
65335: OpcodeFamily = 11; CurrentInstrCycles = 16;
65336: {{ uae_s32 src = get_ilong_prefetch(2);
65337: { uae_s32 dst = m68k_dreg(regs, dstreg);
65338: { refill_prefetch (m68k_getpc(), 2);
65339: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
65340: { int flgs = ((uae_s32)(src)) < 0;
65341: int flgo = ((uae_s32)(dst)) < 0;
65342: int flgn = ((uae_s32)(newv)) < 0;
65343: SET_ZFLG (((uae_s32)(newv)) == 0);
65344: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65345: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
65346: COPY_CARRY;
65347: SET_NFLG (flgn != 0);
65348: m68k_dreg(regs, dstreg) = (newv);
65349: }}}}}}m68k_incpc(6);
65350: fill_prefetch_0 ();
65351: return 16;
65352: }
65353: unsigned long REGPARAM2 CPUFUNC(op_d0c0_5)(uae_u32 opcode) /* ADDA */
65354: {
65355: uae_u32 srcreg = (opcode & 7);
65356: uae_u32 dstreg = (opcode >> 9) & 7;
65357: OpcodeFamily = 12; CurrentInstrCycles = 8;
65358: {{ uae_s16 src = m68k_dreg(regs, srcreg);
65359: { uae_s32 dst = m68k_areg(regs, dstreg);
65360: { uae_u32 newv = dst + src;
65361: m68k_areg(regs, dstreg) = (newv);
65362: }}}}m68k_incpc(2);
65363: fill_prefetch_2 ();
65364: return 8;
65365: }
65366: unsigned long REGPARAM2 CPUFUNC(op_d0c8_5)(uae_u32 opcode) /* ADDA */
65367: {
65368: uae_u32 srcreg = (opcode & 7);
65369: uae_u32 dstreg = (opcode >> 9) & 7;
65370: OpcodeFamily = 12; CurrentInstrCycles = 8;
65371: {{ uae_s16 src = m68k_areg(regs, srcreg);
65372: { uae_s32 dst = m68k_areg(regs, dstreg);
65373: { uae_u32 newv = dst + src;
65374: m68k_areg(regs, dstreg) = (newv);
65375: }}}}m68k_incpc(2);
65376: fill_prefetch_2 ();
65377: return 8;
65378: }
65379: unsigned long REGPARAM2 CPUFUNC(op_d0d0_5)(uae_u32 opcode) /* ADDA */
65380: {
65381: uae_u32 srcreg = (opcode & 7);
65382: uae_u32 dstreg = (opcode >> 9) & 7;
65383: OpcodeFamily = 12; CurrentInstrCycles = 12;
65384: {{ uaecptr srca = m68k_areg(regs, srcreg);
65385: if ((srca & 1) != 0) {
65386: last_fault_for_exception_3 = srca;
65387: last_op_for_exception_3 = opcode;
65388: last_addr_for_exception_3 = m68k_getpc() + 2;
65389: Exception(3, 0, M68000_EXC_SRC_CPU);
65390: goto endlabel3582;
65391: }
65392: {{ uae_s16 src = get_word(srca);
65393: { uae_s32 dst = m68k_areg(regs, dstreg);
65394: { uae_u32 newv = dst + src;
65395: m68k_areg(regs, dstreg) = (newv);
65396: }}}}}}m68k_incpc(2);
65397: fill_prefetch_2 ();
65398: endlabel3582: ;
65399: return 12;
65400: }
65401: unsigned long REGPARAM2 CPUFUNC(op_d0d8_5)(uae_u32 opcode) /* ADDA */
65402: {
65403: uae_u32 srcreg = (opcode & 7);
65404: uae_u32 dstreg = (opcode >> 9) & 7;
65405: OpcodeFamily = 12; CurrentInstrCycles = 12;
65406: {{ uaecptr srca = m68k_areg(regs, srcreg);
65407: if ((srca & 1) != 0) {
65408: last_fault_for_exception_3 = srca;
65409: last_op_for_exception_3 = opcode;
65410: last_addr_for_exception_3 = m68k_getpc() + 2;
65411: Exception(3, 0, M68000_EXC_SRC_CPU);
65412: goto endlabel3583;
65413: }
65414: {{ uae_s16 src = get_word(srca);
65415: m68k_areg(regs, srcreg) += 2;
65416: { uae_s32 dst = m68k_areg(regs, dstreg);
65417: { uae_u32 newv = dst + src;
65418: m68k_areg(regs, dstreg) = (newv);
65419: }}}}}}m68k_incpc(2);
65420: fill_prefetch_2 ();
65421: endlabel3583: ;
65422: return 12;
65423: }
65424: unsigned long REGPARAM2 CPUFUNC(op_d0e0_5)(uae_u32 opcode) /* ADDA */
65425: {
65426: uae_u32 srcreg = (opcode & 7);
65427: uae_u32 dstreg = (opcode >> 9) & 7;
65428: OpcodeFamily = 12; CurrentInstrCycles = 14;
65429: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
65430: if ((srca & 1) != 0) {
65431: last_fault_for_exception_3 = srca;
65432: last_op_for_exception_3 = opcode;
65433: last_addr_for_exception_3 = m68k_getpc() + 2;
65434: Exception(3, 0, M68000_EXC_SRC_CPU);
65435: goto endlabel3584;
65436: }
65437: {{ uae_s16 src = get_word(srca);
65438: m68k_areg (regs, srcreg) = srca;
65439: { uae_s32 dst = m68k_areg(regs, dstreg);
65440: { uae_u32 newv = dst + src;
65441: m68k_areg(regs, dstreg) = (newv);
65442: }}}}}}m68k_incpc(2);
65443: fill_prefetch_2 ();
65444: endlabel3584: ;
65445: return 14;
65446: }
65447: unsigned long REGPARAM2 CPUFUNC(op_d0e8_5)(uae_u32 opcode) /* ADDA */
65448: {
65449: uae_u32 srcreg = (opcode & 7);
65450: uae_u32 dstreg = (opcode >> 9) & 7;
65451: OpcodeFamily = 12; CurrentInstrCycles = 16;
65452: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
65453: if ((srca & 1) != 0) {
65454: last_fault_for_exception_3 = srca;
65455: last_op_for_exception_3 = opcode;
65456: last_addr_for_exception_3 = m68k_getpc() + 4;
65457: Exception(3, 0, M68000_EXC_SRC_CPU);
65458: goto endlabel3585;
65459: }
65460: {{ uae_s16 src = get_word(srca);
65461: { uae_s32 dst = m68k_areg(regs, dstreg);
65462: { uae_u32 newv = dst + src;
65463: m68k_areg(regs, dstreg) = (newv);
65464: }}}}}}m68k_incpc(4);
65465: fill_prefetch_0 ();
65466: endlabel3585: ;
65467: return 16;
65468: }
65469: unsigned long REGPARAM2 CPUFUNC(op_d0f0_5)(uae_u32 opcode) /* ADDA */
65470: {
65471: uae_u32 srcreg = (opcode & 7);
65472: uae_u32 dstreg = (opcode >> 9) & 7;
65473: OpcodeFamily = 12; CurrentInstrCycles = 18;
65474: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
65475: BusCyclePenalty += 2;
65476: if ((srca & 1) != 0) {
65477: last_fault_for_exception_3 = srca;
65478: last_op_for_exception_3 = opcode;
65479: last_addr_for_exception_3 = m68k_getpc() + 4;
65480: Exception(3, 0, M68000_EXC_SRC_CPU);
65481: goto endlabel3586;
65482: }
65483: {{ uae_s16 src = get_word(srca);
65484: { uae_s32 dst = m68k_areg(regs, dstreg);
65485: { uae_u32 newv = dst + src;
65486: m68k_areg(regs, dstreg) = (newv);
65487: }}}}}}m68k_incpc(4);
65488: fill_prefetch_0 ();
65489: endlabel3586: ;
65490: return 18;
65491: }
65492: unsigned long REGPARAM2 CPUFUNC(op_d0f8_5)(uae_u32 opcode) /* ADDA */
65493: {
65494: uae_u32 dstreg = (opcode >> 9) & 7;
65495: OpcodeFamily = 12; CurrentInstrCycles = 16;
65496: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
65497: if ((srca & 1) != 0) {
65498: last_fault_for_exception_3 = srca;
65499: last_op_for_exception_3 = opcode;
65500: last_addr_for_exception_3 = m68k_getpc() + 4;
65501: Exception(3, 0, M68000_EXC_SRC_CPU);
65502: goto endlabel3587;
65503: }
65504: {{ uae_s16 src = get_word(srca);
65505: { uae_s32 dst = m68k_areg(regs, dstreg);
65506: { uae_u32 newv = dst + src;
65507: m68k_areg(regs, dstreg) = (newv);
65508: }}}}}}m68k_incpc(4);
65509: fill_prefetch_0 ();
65510: endlabel3587: ;
65511: return 16;
65512: }
65513: unsigned long REGPARAM2 CPUFUNC(op_d0f9_5)(uae_u32 opcode) /* ADDA */
65514: {
65515: uae_u32 dstreg = (opcode >> 9) & 7;
65516: OpcodeFamily = 12; CurrentInstrCycles = 20;
65517: {{ uaecptr srca = get_ilong_prefetch(2);
65518: if ((srca & 1) != 0) {
65519: last_fault_for_exception_3 = srca;
65520: last_op_for_exception_3 = opcode;
65521: last_addr_for_exception_3 = m68k_getpc() + 6;
65522: Exception(3, 0, M68000_EXC_SRC_CPU);
65523: goto endlabel3588;
65524: }
65525: {{ uae_s16 src = get_word(srca);
65526: { uae_s32 dst = m68k_areg(regs, dstreg);
65527: { uae_u32 newv = dst + src;
65528: m68k_areg(regs, dstreg) = (newv);
65529: }}}}}}m68k_incpc(6);
65530: fill_prefetch_0 ();
65531: endlabel3588: ;
65532: return 20;
65533: }
65534: unsigned long REGPARAM2 CPUFUNC(op_d0fa_5)(uae_u32 opcode) /* ADDA */
65535: {
65536: uae_u32 dstreg = (opcode >> 9) & 7;
65537: OpcodeFamily = 12; CurrentInstrCycles = 16;
65538: {{ uaecptr srca = m68k_getpc () + 2;
65539: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
65540: if ((srca & 1) != 0) {
65541: last_fault_for_exception_3 = srca;
65542: last_op_for_exception_3 = opcode;
65543: last_addr_for_exception_3 = m68k_getpc() + 4;
65544: Exception(3, 0, M68000_EXC_SRC_CPU);
65545: goto endlabel3589;
65546: }
65547: {{ uae_s16 src = get_word(srca);
65548: { uae_s32 dst = m68k_areg(regs, dstreg);
65549: { uae_u32 newv = dst + src;
65550: m68k_areg(regs, dstreg) = (newv);
65551: }}}}}}m68k_incpc(4);
65552: fill_prefetch_0 ();
65553: endlabel3589: ;
65554: return 16;
65555: }
65556: unsigned long REGPARAM2 CPUFUNC(op_d0fb_5)(uae_u32 opcode) /* ADDA */
65557: {
65558: uae_u32 dstreg = (opcode >> 9) & 7;
65559: OpcodeFamily = 12; CurrentInstrCycles = 18;
65560: {{ uaecptr tmppc = m68k_getpc() + 2;
65561: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
65562: BusCyclePenalty += 2;
65563: if ((srca & 1) != 0) {
65564: last_fault_for_exception_3 = srca;
65565: last_op_for_exception_3 = opcode;
65566: last_addr_for_exception_3 = m68k_getpc() + 4;
65567: Exception(3, 0, M68000_EXC_SRC_CPU);
65568: goto endlabel3590;
65569: }
65570: {{ uae_s16 src = get_word(srca);
65571: { uae_s32 dst = m68k_areg(regs, dstreg);
65572: { uae_u32 newv = dst + src;
65573: m68k_areg(regs, dstreg) = (newv);
65574: }}}}}}m68k_incpc(4);
65575: fill_prefetch_0 ();
65576: endlabel3590: ;
65577: return 18;
65578: }
65579: unsigned long REGPARAM2 CPUFUNC(op_d0fc_5)(uae_u32 opcode) /* ADDA */
65580: {
65581: uae_u32 dstreg = (opcode >> 9) & 7;
65582: OpcodeFamily = 12; CurrentInstrCycles = 12;
65583: {{ uae_s16 src = get_iword_prefetch(2);
65584: { uae_s32 dst = m68k_areg(regs, dstreg);
65585: { uae_u32 newv = dst + src;
65586: m68k_areg(regs, dstreg) = (newv);
65587: }}}}m68k_incpc(4);
65588: fill_prefetch_0 ();
65589: return 12;
65590: }
65591: unsigned long REGPARAM2 CPUFUNC(op_d100_5)(uae_u32 opcode) /* ADDX */
65592: {
65593: uae_u32 srcreg = (opcode & 7);
65594: uae_u32 dstreg = (opcode >> 9) & 7;
65595: OpcodeFamily = 13; CurrentInstrCycles = 4;
65596: {{ uae_s8 src = m68k_dreg(regs, srcreg);
65597: { uae_s8 dst = m68k_dreg(regs, dstreg);
65598: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
65599: { int flgs = ((uae_s8)(src)) < 0;
65600: int flgo = ((uae_s8)(dst)) < 0;
65601: int flgn = ((uae_s8)(newv)) < 0;
65602: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65603: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
65604: COPY_CARRY;
65605: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
65606: SET_NFLG (((uae_s8)(newv)) < 0);
65607: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
65608: }}}}}m68k_incpc(2);
65609: fill_prefetch_2 ();
65610: return 4;
65611: }
65612: unsigned long REGPARAM2 CPUFUNC(op_d108_5)(uae_u32 opcode) /* ADDX */
65613: {
65614: uae_u32 srcreg = (opcode & 7);
65615: uae_u32 dstreg = (opcode >> 9) & 7;
65616: OpcodeFamily = 13; CurrentInstrCycles = 18;
65617: {{ uaecptr srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
65618: { uae_s8 src = get_byte(srca);
65619: m68k_areg (regs, srcreg) = srca;
65620: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
65621: { uae_s8 dst = get_byte(dsta);
65622: m68k_areg (regs, dstreg) = dsta;
65623: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
65624: { int flgs = ((uae_s8)(src)) < 0;
65625: int flgo = ((uae_s8)(dst)) < 0;
65626: int flgn = ((uae_s8)(newv)) < 0;
65627: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65628: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
65629: COPY_CARRY;
65630: SET_ZFLG (GET_ZFLG & (((uae_s8)(newv)) == 0));
65631: SET_NFLG (((uae_s8)(newv)) < 0);
65632: m68k_incpc(2);
65633: fill_prefetch_2 ();
65634: put_byte(dsta,newv);
65635: }}}}}}}return 18;
65636: }
65637: unsigned long REGPARAM2 CPUFUNC(op_d110_5)(uae_u32 opcode) /* ADD */
65638: {
65639: uae_u32 srcreg = ((opcode >> 9) & 7);
65640: uae_u32 dstreg = opcode & 7;
65641: OpcodeFamily = 11; CurrentInstrCycles = 12;
65642: {{ uae_s8 src = m68k_dreg(regs, srcreg);
65643: { uaecptr dsta = m68k_areg(regs, dstreg);
65644: { uae_s8 dst = get_byte(dsta);
65645: { refill_prefetch (m68k_getpc(), 2);
65646: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
65647: { int flgs = ((uae_s8)(src)) < 0;
65648: int flgo = ((uae_s8)(dst)) < 0;
65649: int flgn = ((uae_s8)(newv)) < 0;
65650: SET_ZFLG (((uae_s8)(newv)) == 0);
65651: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65652: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
65653: COPY_CARRY;
65654: SET_NFLG (flgn != 0);
65655: m68k_incpc(2);
65656: fill_prefetch_2 ();
65657: put_byte(dsta,newv);
65658: }}}}}}}return 12;
65659: }
65660: unsigned long REGPARAM2 CPUFUNC(op_d118_5)(uae_u32 opcode) /* ADD */
65661: {
65662: uae_u32 srcreg = ((opcode >> 9) & 7);
65663: uae_u32 dstreg = opcode & 7;
65664: OpcodeFamily = 11; CurrentInstrCycles = 12;
65665: {{ uae_s8 src = m68k_dreg(regs, srcreg);
65666: { uaecptr dsta = m68k_areg(regs, dstreg);
65667: { uae_s8 dst = get_byte(dsta);
65668: m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
65669: { refill_prefetch (m68k_getpc(), 2);
65670: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
65671: { int flgs = ((uae_s8)(src)) < 0;
65672: int flgo = ((uae_s8)(dst)) < 0;
65673: int flgn = ((uae_s8)(newv)) < 0;
65674: SET_ZFLG (((uae_s8)(newv)) == 0);
65675: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65676: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
65677: COPY_CARRY;
65678: SET_NFLG (flgn != 0);
65679: m68k_incpc(2);
65680: fill_prefetch_2 ();
65681: put_byte(dsta,newv);
65682: }}}}}}}return 12;
65683: }
65684: unsigned long REGPARAM2 CPUFUNC(op_d120_5)(uae_u32 opcode) /* ADD */
65685: {
65686: uae_u32 srcreg = ((opcode >> 9) & 7);
65687: uae_u32 dstreg = opcode & 7;
65688: OpcodeFamily = 11; CurrentInstrCycles = 14;
65689: {{ uae_s8 src = m68k_dreg(regs, srcreg);
65690: { uaecptr dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
65691: { uae_s8 dst = get_byte(dsta);
65692: m68k_areg (regs, dstreg) = dsta;
65693: { refill_prefetch (m68k_getpc(), 2);
65694: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
65695: { int flgs = ((uae_s8)(src)) < 0;
65696: int flgo = ((uae_s8)(dst)) < 0;
65697: int flgn = ((uae_s8)(newv)) < 0;
65698: SET_ZFLG (((uae_s8)(newv)) == 0);
65699: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65700: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
65701: COPY_CARRY;
65702: SET_NFLG (flgn != 0);
65703: m68k_incpc(2);
65704: fill_prefetch_2 ();
65705: put_byte(dsta,newv);
65706: }}}}}}}return 14;
65707: }
65708: unsigned long REGPARAM2 CPUFUNC(op_d128_5)(uae_u32 opcode) /* ADD */
65709: {
65710: uae_u32 srcreg = ((opcode >> 9) & 7);
65711: uae_u32 dstreg = opcode & 7;
65712: OpcodeFamily = 11; CurrentInstrCycles = 16;
65713: {{ uae_s8 src = m68k_dreg(regs, srcreg);
65714: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
65715: { uae_s8 dst = get_byte(dsta);
65716: { refill_prefetch (m68k_getpc(), 2);
65717: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
65718: { int flgs = ((uae_s8)(src)) < 0;
65719: int flgo = ((uae_s8)(dst)) < 0;
65720: int flgn = ((uae_s8)(newv)) < 0;
65721: SET_ZFLG (((uae_s8)(newv)) == 0);
65722: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65723: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
65724: COPY_CARRY;
65725: SET_NFLG (flgn != 0);
65726: m68k_incpc(4);
65727: fill_prefetch_0 ();
65728: put_byte(dsta,newv);
65729: }}}}}}}return 16;
65730: }
65731: unsigned long REGPARAM2 CPUFUNC(op_d130_5)(uae_u32 opcode) /* ADD */
65732: {
65733: uae_u32 srcreg = ((opcode >> 9) & 7);
65734: uae_u32 dstreg = opcode & 7;
65735: OpcodeFamily = 11; CurrentInstrCycles = 18;
65736: {{ uae_s8 src = m68k_dreg(regs, srcreg);
65737: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
65738: BusCyclePenalty += 2;
65739: { uae_s8 dst = get_byte(dsta);
65740: { refill_prefetch (m68k_getpc(), 2);
65741: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
65742: { int flgs = ((uae_s8)(src)) < 0;
65743: int flgo = ((uae_s8)(dst)) < 0;
65744: int flgn = ((uae_s8)(newv)) < 0;
65745: SET_ZFLG (((uae_s8)(newv)) == 0);
65746: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65747: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
65748: COPY_CARRY;
65749: SET_NFLG (flgn != 0);
65750: m68k_incpc(4);
65751: fill_prefetch_0 ();
65752: put_byte(dsta,newv);
65753: }}}}}}}return 18;
65754: }
65755: unsigned long REGPARAM2 CPUFUNC(op_d138_5)(uae_u32 opcode) /* ADD */
65756: {
65757: uae_u32 srcreg = ((opcode >> 9) & 7);
65758: OpcodeFamily = 11; CurrentInstrCycles = 16;
65759: {{ uae_s8 src = m68k_dreg(regs, srcreg);
65760: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
65761: { uae_s8 dst = get_byte(dsta);
65762: { refill_prefetch (m68k_getpc(), 2);
65763: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
65764: { int flgs = ((uae_s8)(src)) < 0;
65765: int flgo = ((uae_s8)(dst)) < 0;
65766: int flgn = ((uae_s8)(newv)) < 0;
65767: SET_ZFLG (((uae_s8)(newv)) == 0);
65768: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65769: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
65770: COPY_CARRY;
65771: SET_NFLG (flgn != 0);
65772: m68k_incpc(4);
65773: fill_prefetch_0 ();
65774: put_byte(dsta,newv);
65775: }}}}}}}return 16;
65776: }
65777: unsigned long REGPARAM2 CPUFUNC(op_d139_5)(uae_u32 opcode) /* ADD */
65778: {
65779: uae_u32 srcreg = ((opcode >> 9) & 7);
65780: OpcodeFamily = 11; CurrentInstrCycles = 20;
65781: {{ uae_s8 src = m68k_dreg(regs, srcreg);
65782: { uaecptr dsta = get_ilong_prefetch(2);
65783: { uae_s8 dst = get_byte(dsta);
65784: { refill_prefetch (m68k_getpc(), 2);
65785: {uae_u32 newv = ((uae_s8)(dst)) + ((uae_s8)(src));
65786: { int flgs = ((uae_s8)(src)) < 0;
65787: int flgo = ((uae_s8)(dst)) < 0;
65788: int flgn = ((uae_s8)(newv)) < 0;
65789: SET_ZFLG (((uae_s8)(newv)) == 0);
65790: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65791: SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
65792: COPY_CARRY;
65793: SET_NFLG (flgn != 0);
65794: m68k_incpc(6);
65795: fill_prefetch_0 ();
65796: put_byte(dsta,newv);
65797: }}}}}}}return 20;
65798: }
65799: unsigned long REGPARAM2 CPUFUNC(op_d140_5)(uae_u32 opcode) /* ADDX */
65800: {
65801: uae_u32 srcreg = (opcode & 7);
65802: uae_u32 dstreg = (opcode >> 9) & 7;
65803: OpcodeFamily = 13; CurrentInstrCycles = 4;
65804: {{ uae_s16 src = m68k_dreg(regs, srcreg);
65805: { uae_s16 dst = m68k_dreg(regs, dstreg);
65806: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
65807: { int flgs = ((uae_s16)(src)) < 0;
65808: int flgo = ((uae_s16)(dst)) < 0;
65809: int flgn = ((uae_s16)(newv)) < 0;
65810: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65811: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
65812: COPY_CARRY;
65813: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
65814: SET_NFLG (((uae_s16)(newv)) < 0);
65815: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
65816: }}}}}m68k_incpc(2);
65817: fill_prefetch_2 ();
65818: return 4;
65819: }
65820: unsigned long REGPARAM2 CPUFUNC(op_d148_5)(uae_u32 opcode) /* ADDX */
65821: {
65822: uae_u32 srcreg = (opcode & 7);
65823: uae_u32 dstreg = (opcode >> 9) & 7;
65824: OpcodeFamily = 13; CurrentInstrCycles = 18;
65825: {{ uaecptr srca = m68k_areg(regs, srcreg) - 2;
65826: if ((srca & 1) != 0) {
65827: last_fault_for_exception_3 = srca;
65828: last_op_for_exception_3 = opcode;
65829: last_addr_for_exception_3 = m68k_getpc() + 2;
65830: Exception(3, 0, M68000_EXC_SRC_CPU);
65831: goto endlabel3602;
65832: }
65833: {{ uae_s16 src = get_word(srca);
65834: m68k_areg (regs, srcreg) = srca;
65835: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
65836: if ((dsta & 1) != 0) {
65837: last_fault_for_exception_3 = dsta;
65838: last_op_for_exception_3 = opcode;
65839: last_addr_for_exception_3 = m68k_getpc() + 2;
65840: Exception(3, 0, M68000_EXC_SRC_CPU);
65841: goto endlabel3602;
65842: }
65843: {{ uae_s16 dst = get_word(dsta);
65844: m68k_areg (regs, dstreg) = dsta;
65845: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
65846: { int flgs = ((uae_s16)(src)) < 0;
65847: int flgo = ((uae_s16)(dst)) < 0;
65848: int flgn = ((uae_s16)(newv)) < 0;
65849: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65850: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
65851: COPY_CARRY;
65852: SET_ZFLG (GET_ZFLG & (((uae_s16)(newv)) == 0));
65853: SET_NFLG (((uae_s16)(newv)) < 0);
65854: m68k_incpc(2);
65855: fill_prefetch_2 ();
65856: put_word(dsta,newv);
65857: }}}}}}}}}endlabel3602: ;
65858: return 18;
65859: }
65860: unsigned long REGPARAM2 CPUFUNC(op_d150_5)(uae_u32 opcode) /* ADD */
65861: {
65862: uae_u32 srcreg = ((opcode >> 9) & 7);
65863: uae_u32 dstreg = opcode & 7;
65864: OpcodeFamily = 11; CurrentInstrCycles = 12;
65865: {{ uae_s16 src = m68k_dreg(regs, srcreg);
65866: { uaecptr dsta = m68k_areg(regs, dstreg);
65867: if ((dsta & 1) != 0) {
65868: last_fault_for_exception_3 = dsta;
65869: last_op_for_exception_3 = opcode;
65870: last_addr_for_exception_3 = m68k_getpc() + 2;
65871: Exception(3, 0, M68000_EXC_SRC_CPU);
65872: goto endlabel3603;
65873: }
65874: {{ uae_s16 dst = get_word(dsta);
65875: { refill_prefetch (m68k_getpc(), 2);
65876: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
65877: { int flgs = ((uae_s16)(src)) < 0;
65878: int flgo = ((uae_s16)(dst)) < 0;
65879: int flgn = ((uae_s16)(newv)) < 0;
65880: SET_ZFLG (((uae_s16)(newv)) == 0);
65881: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65882: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
65883: COPY_CARRY;
65884: SET_NFLG (flgn != 0);
65885: m68k_incpc(2);
65886: fill_prefetch_2 ();
65887: put_word(dsta,newv);
65888: }}}}}}}}endlabel3603: ;
65889: return 12;
65890: }
65891: unsigned long REGPARAM2 CPUFUNC(op_d158_5)(uae_u32 opcode) /* ADD */
65892: {
65893: uae_u32 srcreg = ((opcode >> 9) & 7);
65894: uae_u32 dstreg = opcode & 7;
65895: OpcodeFamily = 11; CurrentInstrCycles = 12;
65896: {{ uae_s16 src = m68k_dreg(regs, srcreg);
65897: { uaecptr dsta = m68k_areg(regs, dstreg);
65898: if ((dsta & 1) != 0) {
65899: last_fault_for_exception_3 = dsta;
65900: last_op_for_exception_3 = opcode;
65901: last_addr_for_exception_3 = m68k_getpc() + 2;
65902: Exception(3, 0, M68000_EXC_SRC_CPU);
65903: goto endlabel3604;
65904: }
65905: {{ uae_s16 dst = get_word(dsta);
65906: m68k_areg(regs, dstreg) += 2;
65907: { refill_prefetch (m68k_getpc(), 2);
65908: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
65909: { int flgs = ((uae_s16)(src)) < 0;
65910: int flgo = ((uae_s16)(dst)) < 0;
65911: int flgn = ((uae_s16)(newv)) < 0;
65912: SET_ZFLG (((uae_s16)(newv)) == 0);
65913: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65914: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
65915: COPY_CARRY;
65916: SET_NFLG (flgn != 0);
65917: m68k_incpc(2);
65918: fill_prefetch_2 ();
65919: put_word(dsta,newv);
65920: }}}}}}}}endlabel3604: ;
65921: return 12;
65922: }
65923: unsigned long REGPARAM2 CPUFUNC(op_d160_5)(uae_u32 opcode) /* ADD */
65924: {
65925: uae_u32 srcreg = ((opcode >> 9) & 7);
65926: uae_u32 dstreg = opcode & 7;
65927: OpcodeFamily = 11; CurrentInstrCycles = 14;
65928: {{ uae_s16 src = m68k_dreg(regs, srcreg);
65929: { uaecptr dsta = m68k_areg(regs, dstreg) - 2;
65930: if ((dsta & 1) != 0) {
65931: last_fault_for_exception_3 = dsta;
65932: last_op_for_exception_3 = opcode;
65933: last_addr_for_exception_3 = m68k_getpc() + 2;
65934: Exception(3, 0, M68000_EXC_SRC_CPU);
65935: goto endlabel3605;
65936: }
65937: {{ uae_s16 dst = get_word(dsta);
65938: m68k_areg (regs, dstreg) = dsta;
65939: { refill_prefetch (m68k_getpc(), 2);
65940: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
65941: { int flgs = ((uae_s16)(src)) < 0;
65942: int flgo = ((uae_s16)(dst)) < 0;
65943: int flgn = ((uae_s16)(newv)) < 0;
65944: SET_ZFLG (((uae_s16)(newv)) == 0);
65945: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65946: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
65947: COPY_CARRY;
65948: SET_NFLG (flgn != 0);
65949: m68k_incpc(2);
65950: fill_prefetch_2 ();
65951: put_word(dsta,newv);
65952: }}}}}}}}endlabel3605: ;
65953: return 14;
65954: }
65955: unsigned long REGPARAM2 CPUFUNC(op_d168_5)(uae_u32 opcode) /* ADD */
65956: {
65957: uae_u32 srcreg = ((opcode >> 9) & 7);
65958: uae_u32 dstreg = opcode & 7;
65959: OpcodeFamily = 11; CurrentInstrCycles = 16;
65960: {{ uae_s16 src = m68k_dreg(regs, srcreg);
65961: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
65962: if ((dsta & 1) != 0) {
65963: last_fault_for_exception_3 = dsta;
65964: last_op_for_exception_3 = opcode;
65965: last_addr_for_exception_3 = m68k_getpc() + 4;
65966: Exception(3, 0, M68000_EXC_SRC_CPU);
65967: goto endlabel3606;
65968: }
65969: {{ uae_s16 dst = get_word(dsta);
65970: { refill_prefetch (m68k_getpc(), 2);
65971: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
65972: { int flgs = ((uae_s16)(src)) < 0;
65973: int flgo = ((uae_s16)(dst)) < 0;
65974: int flgn = ((uae_s16)(newv)) < 0;
65975: SET_ZFLG (((uae_s16)(newv)) == 0);
65976: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
65977: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
65978: COPY_CARRY;
65979: SET_NFLG (flgn != 0);
65980: m68k_incpc(4);
65981: fill_prefetch_0 ();
65982: put_word(dsta,newv);
65983: }}}}}}}}endlabel3606: ;
65984: return 16;
65985: }
65986: unsigned long REGPARAM2 CPUFUNC(op_d170_5)(uae_u32 opcode) /* ADD */
65987: {
65988: uae_u32 srcreg = ((opcode >> 9) & 7);
65989: uae_u32 dstreg = opcode & 7;
65990: OpcodeFamily = 11; CurrentInstrCycles = 18;
65991: {{ uae_s16 src = m68k_dreg(regs, srcreg);
65992: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
65993: BusCyclePenalty += 2;
65994: if ((dsta & 1) != 0) {
65995: last_fault_for_exception_3 = dsta;
65996: last_op_for_exception_3 = opcode;
65997: last_addr_for_exception_3 = m68k_getpc() + 4;
65998: Exception(3, 0, M68000_EXC_SRC_CPU);
65999: goto endlabel3607;
66000: }
66001: {{ uae_s16 dst = get_word(dsta);
66002: { refill_prefetch (m68k_getpc(), 2);
66003: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
66004: { int flgs = ((uae_s16)(src)) < 0;
66005: int flgo = ((uae_s16)(dst)) < 0;
66006: int flgn = ((uae_s16)(newv)) < 0;
66007: SET_ZFLG (((uae_s16)(newv)) == 0);
66008: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66009: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
66010: COPY_CARRY;
66011: SET_NFLG (flgn != 0);
66012: m68k_incpc(4);
66013: fill_prefetch_0 ();
66014: put_word(dsta,newv);
66015: }}}}}}}}endlabel3607: ;
66016: return 18;
66017: }
66018: unsigned long REGPARAM2 CPUFUNC(op_d178_5)(uae_u32 opcode) /* ADD */
66019: {
66020: uae_u32 srcreg = ((opcode >> 9) & 7);
66021: OpcodeFamily = 11; CurrentInstrCycles = 16;
66022: {{ uae_s16 src = m68k_dreg(regs, srcreg);
66023: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
66024: if ((dsta & 1) != 0) {
66025: last_fault_for_exception_3 = dsta;
66026: last_op_for_exception_3 = opcode;
66027: last_addr_for_exception_3 = m68k_getpc() + 4;
66028: Exception(3, 0, M68000_EXC_SRC_CPU);
66029: goto endlabel3608;
66030: }
66031: {{ uae_s16 dst = get_word(dsta);
66032: { refill_prefetch (m68k_getpc(), 2);
66033: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
66034: { int flgs = ((uae_s16)(src)) < 0;
66035: int flgo = ((uae_s16)(dst)) < 0;
66036: int flgn = ((uae_s16)(newv)) < 0;
66037: SET_ZFLG (((uae_s16)(newv)) == 0);
66038: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66039: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
66040: COPY_CARRY;
66041: SET_NFLG (flgn != 0);
66042: m68k_incpc(4);
66043: fill_prefetch_0 ();
66044: put_word(dsta,newv);
66045: }}}}}}}}endlabel3608: ;
66046: return 16;
66047: }
66048: unsigned long REGPARAM2 CPUFUNC(op_d179_5)(uae_u32 opcode) /* ADD */
66049: {
66050: uae_u32 srcreg = ((opcode >> 9) & 7);
66051: OpcodeFamily = 11; CurrentInstrCycles = 20;
66052: {{ uae_s16 src = m68k_dreg(regs, srcreg);
66053: { uaecptr dsta = get_ilong_prefetch(2);
66054: if ((dsta & 1) != 0) {
66055: last_fault_for_exception_3 = dsta;
66056: last_op_for_exception_3 = opcode;
66057: last_addr_for_exception_3 = m68k_getpc() + 6;
66058: Exception(3, 0, M68000_EXC_SRC_CPU);
66059: goto endlabel3609;
66060: }
66061: {{ uae_s16 dst = get_word(dsta);
66062: { refill_prefetch (m68k_getpc(), 2);
66063: {uae_u32 newv = ((uae_s16)(dst)) + ((uae_s16)(src));
66064: { int flgs = ((uae_s16)(src)) < 0;
66065: int flgo = ((uae_s16)(dst)) < 0;
66066: int flgn = ((uae_s16)(newv)) < 0;
66067: SET_ZFLG (((uae_s16)(newv)) == 0);
66068: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66069: SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
66070: COPY_CARRY;
66071: SET_NFLG (flgn != 0);
66072: m68k_incpc(6);
66073: fill_prefetch_0 ();
66074: put_word(dsta,newv);
66075: }}}}}}}}endlabel3609: ;
66076: return 20;
66077: }
66078: unsigned long REGPARAM2 CPUFUNC(op_d180_5)(uae_u32 opcode) /* ADDX */
66079: {
66080: uae_u32 srcreg = (opcode & 7);
66081: uae_u32 dstreg = (opcode >> 9) & 7;
66082: OpcodeFamily = 13; CurrentInstrCycles = 8;
66083: {{ uae_s32 src = m68k_dreg(regs, srcreg);
66084: { uae_s32 dst = m68k_dreg(regs, dstreg);
66085: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
66086: { int flgs = ((uae_s32)(src)) < 0;
66087: int flgo = ((uae_s32)(dst)) < 0;
66088: int flgn = ((uae_s32)(newv)) < 0;
66089: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66090: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
66091: COPY_CARRY;
66092: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
66093: SET_NFLG (((uae_s32)(newv)) < 0);
66094: m68k_dreg(regs, dstreg) = (newv);
66095: }}}}}m68k_incpc(2);
66096: fill_prefetch_2 ();
66097: return 8;
66098: }
66099: unsigned long REGPARAM2 CPUFUNC(op_d188_5)(uae_u32 opcode) /* ADDX */
66100: {
66101: uae_u32 srcreg = (opcode & 7);
66102: uae_u32 dstreg = (opcode >> 9) & 7;
66103: OpcodeFamily = 13; CurrentInstrCycles = 30;
66104: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
66105: if ((srca & 1) != 0) {
66106: last_fault_for_exception_3 = srca;
66107: last_op_for_exception_3 = opcode;
66108: last_addr_for_exception_3 = m68k_getpc() + 2;
66109: Exception(3, 0, M68000_EXC_SRC_CPU);
66110: goto endlabel3611;
66111: }
66112: {{ uae_s32 src = get_long(srca);
66113: m68k_areg (regs, srcreg) = srca;
66114: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
66115: if ((dsta & 1) != 0) {
66116: last_fault_for_exception_3 = dsta;
66117: last_op_for_exception_3 = opcode;
66118: last_addr_for_exception_3 = m68k_getpc() + 2;
66119: Exception(3, 0, M68000_EXC_SRC_CPU);
66120: goto endlabel3611;
66121: }
66122: {{ uae_s32 dst = get_long(dsta);
66123: m68k_areg (regs, dstreg) = dsta;
66124: { uae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);
66125: { int flgs = ((uae_s32)(src)) < 0;
66126: int flgo = ((uae_s32)(dst)) < 0;
66127: int flgn = ((uae_s32)(newv)) < 0;
66128: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66129: SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
66130: COPY_CARRY;
66131: SET_ZFLG (GET_ZFLG & (((uae_s32)(newv)) == 0));
66132: SET_NFLG (((uae_s32)(newv)) < 0);
66133: m68k_incpc(2);
66134: fill_prefetch_2 ();
66135: put_long(dsta,newv);
66136: }}}}}}}}}endlabel3611: ;
66137: return 30;
66138: }
66139: unsigned long REGPARAM2 CPUFUNC(op_d190_5)(uae_u32 opcode) /* ADD */
66140: {
66141: uae_u32 srcreg = ((opcode >> 9) & 7);
66142: uae_u32 dstreg = opcode & 7;
66143: OpcodeFamily = 11; CurrentInstrCycles = 20;
66144: {{ uae_s32 src = m68k_dreg(regs, srcreg);
66145: { uaecptr dsta = m68k_areg(regs, dstreg);
66146: if ((dsta & 1) != 0) {
66147: last_fault_for_exception_3 = dsta;
66148: last_op_for_exception_3 = opcode;
66149: last_addr_for_exception_3 = m68k_getpc() + 2;
66150: Exception(3, 0, M68000_EXC_SRC_CPU);
66151: goto endlabel3612;
66152: }
66153: {{ uae_s32 dst = get_long(dsta);
66154: { refill_prefetch (m68k_getpc(), 2);
66155: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
66156: { int flgs = ((uae_s32)(src)) < 0;
66157: int flgo = ((uae_s32)(dst)) < 0;
66158: int flgn = ((uae_s32)(newv)) < 0;
66159: SET_ZFLG (((uae_s32)(newv)) == 0);
66160: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66161: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
66162: COPY_CARRY;
66163: SET_NFLG (flgn != 0);
66164: m68k_incpc(2);
66165: fill_prefetch_2 ();
66166: put_long(dsta,newv);
66167: }}}}}}}}endlabel3612: ;
66168: return 20;
66169: }
66170: unsigned long REGPARAM2 CPUFUNC(op_d198_5)(uae_u32 opcode) /* ADD */
66171: {
66172: uae_u32 srcreg = ((opcode >> 9) & 7);
66173: uae_u32 dstreg = opcode & 7;
66174: OpcodeFamily = 11; CurrentInstrCycles = 20;
66175: {{ uae_s32 src = m68k_dreg(regs, srcreg);
66176: { uaecptr dsta = m68k_areg(regs, dstreg);
66177: if ((dsta & 1) != 0) {
66178: last_fault_for_exception_3 = dsta;
66179: last_op_for_exception_3 = opcode;
66180: last_addr_for_exception_3 = m68k_getpc() + 2;
66181: Exception(3, 0, M68000_EXC_SRC_CPU);
66182: goto endlabel3613;
66183: }
66184: {{ uae_s32 dst = get_long(dsta);
66185: m68k_areg(regs, dstreg) += 4;
66186: { refill_prefetch (m68k_getpc(), 2);
66187: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
66188: { int flgs = ((uae_s32)(src)) < 0;
66189: int flgo = ((uae_s32)(dst)) < 0;
66190: int flgn = ((uae_s32)(newv)) < 0;
66191: SET_ZFLG (((uae_s32)(newv)) == 0);
66192: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66193: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
66194: COPY_CARRY;
66195: SET_NFLG (flgn != 0);
66196: m68k_incpc(2);
66197: fill_prefetch_2 ();
66198: put_long(dsta,newv);
66199: }}}}}}}}endlabel3613: ;
66200: return 20;
66201: }
66202: unsigned long REGPARAM2 CPUFUNC(op_d1a0_5)(uae_u32 opcode) /* ADD */
66203: {
66204: uae_u32 srcreg = ((opcode >> 9) & 7);
66205: uae_u32 dstreg = opcode & 7;
66206: OpcodeFamily = 11; CurrentInstrCycles = 22;
66207: {{ uae_s32 src = m68k_dreg(regs, srcreg);
66208: { uaecptr dsta = m68k_areg(regs, dstreg) - 4;
66209: if ((dsta & 1) != 0) {
66210: last_fault_for_exception_3 = dsta;
66211: last_op_for_exception_3 = opcode;
66212: last_addr_for_exception_3 = m68k_getpc() + 2;
66213: Exception(3, 0, M68000_EXC_SRC_CPU);
66214: goto endlabel3614;
66215: }
66216: {{ uae_s32 dst = get_long(dsta);
66217: m68k_areg (regs, dstreg) = dsta;
66218: { refill_prefetch (m68k_getpc(), 2);
66219: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
66220: { int flgs = ((uae_s32)(src)) < 0;
66221: int flgo = ((uae_s32)(dst)) < 0;
66222: int flgn = ((uae_s32)(newv)) < 0;
66223: SET_ZFLG (((uae_s32)(newv)) == 0);
66224: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66225: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
66226: COPY_CARRY;
66227: SET_NFLG (flgn != 0);
66228: m68k_incpc(2);
66229: fill_prefetch_2 ();
66230: put_long(dsta,newv);
66231: }}}}}}}}endlabel3614: ;
66232: return 22;
66233: }
66234: unsigned long REGPARAM2 CPUFUNC(op_d1a8_5)(uae_u32 opcode) /* ADD */
66235: {
66236: uae_u32 srcreg = ((opcode >> 9) & 7);
66237: uae_u32 dstreg = opcode & 7;
66238: OpcodeFamily = 11; CurrentInstrCycles = 24;
66239: {{ uae_s32 src = m68k_dreg(regs, srcreg);
66240: { uaecptr dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
66241: if ((dsta & 1) != 0) {
66242: last_fault_for_exception_3 = dsta;
66243: last_op_for_exception_3 = opcode;
66244: last_addr_for_exception_3 = m68k_getpc() + 4;
66245: Exception(3, 0, M68000_EXC_SRC_CPU);
66246: goto endlabel3615;
66247: }
66248: {{ uae_s32 dst = get_long(dsta);
66249: { refill_prefetch (m68k_getpc(), 2);
66250: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
66251: { int flgs = ((uae_s32)(src)) < 0;
66252: int flgo = ((uae_s32)(dst)) < 0;
66253: int flgn = ((uae_s32)(newv)) < 0;
66254: SET_ZFLG (((uae_s32)(newv)) == 0);
66255: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66256: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
66257: COPY_CARRY;
66258: SET_NFLG (flgn != 0);
66259: m68k_incpc(4);
66260: fill_prefetch_0 ();
66261: put_long(dsta,newv);
66262: }}}}}}}}endlabel3615: ;
66263: return 24;
66264: }
66265: unsigned long REGPARAM2 CPUFUNC(op_d1b0_5)(uae_u32 opcode) /* ADD */
66266: {
66267: uae_u32 srcreg = ((opcode >> 9) & 7);
66268: uae_u32 dstreg = opcode & 7;
66269: OpcodeFamily = 11; CurrentInstrCycles = 26;
66270: {{ uae_s32 src = m68k_dreg(regs, srcreg);
66271: { uaecptr dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2));
66272: BusCyclePenalty += 2;
66273: if ((dsta & 1) != 0) {
66274: last_fault_for_exception_3 = dsta;
66275: last_op_for_exception_3 = opcode;
66276: last_addr_for_exception_3 = m68k_getpc() + 4;
66277: Exception(3, 0, M68000_EXC_SRC_CPU);
66278: goto endlabel3616;
66279: }
66280: {{ uae_s32 dst = get_long(dsta);
66281: { refill_prefetch (m68k_getpc(), 2);
66282: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
66283: { int flgs = ((uae_s32)(src)) < 0;
66284: int flgo = ((uae_s32)(dst)) < 0;
66285: int flgn = ((uae_s32)(newv)) < 0;
66286: SET_ZFLG (((uae_s32)(newv)) == 0);
66287: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66288: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
66289: COPY_CARRY;
66290: SET_NFLG (flgn != 0);
66291: m68k_incpc(4);
66292: fill_prefetch_0 ();
66293: put_long(dsta,newv);
66294: }}}}}}}}endlabel3616: ;
66295: return 26;
66296: }
66297: unsigned long REGPARAM2 CPUFUNC(op_d1b8_5)(uae_u32 opcode) /* ADD */
66298: {
66299: uae_u32 srcreg = ((opcode >> 9) & 7);
66300: OpcodeFamily = 11; CurrentInstrCycles = 24;
66301: {{ uae_s32 src = m68k_dreg(regs, srcreg);
66302: { uaecptr dsta = (uae_s32)(uae_s16)get_iword_prefetch(2);
66303: if ((dsta & 1) != 0) {
66304: last_fault_for_exception_3 = dsta;
66305: last_op_for_exception_3 = opcode;
66306: last_addr_for_exception_3 = m68k_getpc() + 4;
66307: Exception(3, 0, M68000_EXC_SRC_CPU);
66308: goto endlabel3617;
66309: }
66310: {{ uae_s32 dst = get_long(dsta);
66311: { refill_prefetch (m68k_getpc(), 2);
66312: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
66313: { int flgs = ((uae_s32)(src)) < 0;
66314: int flgo = ((uae_s32)(dst)) < 0;
66315: int flgn = ((uae_s32)(newv)) < 0;
66316: SET_ZFLG (((uae_s32)(newv)) == 0);
66317: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66318: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
66319: COPY_CARRY;
66320: SET_NFLG (flgn != 0);
66321: m68k_incpc(4);
66322: fill_prefetch_0 ();
66323: put_long(dsta,newv);
66324: }}}}}}}}endlabel3617: ;
66325: return 24;
66326: }
66327: unsigned long REGPARAM2 CPUFUNC(op_d1b9_5)(uae_u32 opcode) /* ADD */
66328: {
66329: uae_u32 srcreg = ((opcode >> 9) & 7);
66330: OpcodeFamily = 11; CurrentInstrCycles = 28;
66331: {{ uae_s32 src = m68k_dreg(regs, srcreg);
66332: { uaecptr dsta = get_ilong_prefetch(2);
66333: if ((dsta & 1) != 0) {
66334: last_fault_for_exception_3 = dsta;
66335: last_op_for_exception_3 = opcode;
66336: last_addr_for_exception_3 = m68k_getpc() + 6;
66337: Exception(3, 0, M68000_EXC_SRC_CPU);
66338: goto endlabel3618;
66339: }
66340: {{ uae_s32 dst = get_long(dsta);
66341: { refill_prefetch (m68k_getpc(), 2);
66342: {uae_u32 newv = ((uae_s32)(dst)) + ((uae_s32)(src));
66343: { int flgs = ((uae_s32)(src)) < 0;
66344: int flgo = ((uae_s32)(dst)) < 0;
66345: int flgn = ((uae_s32)(newv)) < 0;
66346: SET_ZFLG (((uae_s32)(newv)) == 0);
66347: SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
66348: SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
66349: COPY_CARRY;
66350: SET_NFLG (flgn != 0);
66351: m68k_incpc(6);
66352: fill_prefetch_0 ();
66353: put_long(dsta,newv);
66354: }}}}}}}}endlabel3618: ;
66355: return 28;
66356: }
66357: unsigned long REGPARAM2 CPUFUNC(op_d1c0_5)(uae_u32 opcode) /* ADDA */
66358: {
66359: uae_u32 srcreg = (opcode & 7);
66360: uae_u32 dstreg = (opcode >> 9) & 7;
66361: OpcodeFamily = 12; CurrentInstrCycles = 8;
66362: {{ uae_s32 src = m68k_dreg(regs, srcreg);
66363: { uae_s32 dst = m68k_areg(regs, dstreg);
66364: { uae_u32 newv = dst + src;
66365: m68k_areg(regs, dstreg) = (newv);
66366: }}}}m68k_incpc(2);
66367: fill_prefetch_2 ();
66368: return 8;
66369: }
66370: unsigned long REGPARAM2 CPUFUNC(op_d1c8_5)(uae_u32 opcode) /* ADDA */
66371: {
66372: uae_u32 srcreg = (opcode & 7);
66373: uae_u32 dstreg = (opcode >> 9) & 7;
66374: OpcodeFamily = 12; CurrentInstrCycles = 8;
66375: {{ uae_s32 src = m68k_areg(regs, srcreg);
66376: { uae_s32 dst = m68k_areg(regs, dstreg);
66377: { uae_u32 newv = dst + src;
66378: m68k_areg(regs, dstreg) = (newv);
66379: }}}}m68k_incpc(2);
66380: fill_prefetch_2 ();
66381: return 8;
66382: }
66383: unsigned long REGPARAM2 CPUFUNC(op_d1d0_5)(uae_u32 opcode) /* ADDA */
66384: {
66385: uae_u32 srcreg = (opcode & 7);
66386: uae_u32 dstreg = (opcode >> 9) & 7;
66387: OpcodeFamily = 12; CurrentInstrCycles = 14;
66388: {{ uaecptr srca = m68k_areg(regs, srcreg);
66389: if ((srca & 1) != 0) {
66390: last_fault_for_exception_3 = srca;
66391: last_op_for_exception_3 = opcode;
66392: last_addr_for_exception_3 = m68k_getpc() + 2;
66393: Exception(3, 0, M68000_EXC_SRC_CPU);
66394: goto endlabel3621;
66395: }
66396: {{ uae_s32 src = get_long(srca);
66397: { uae_s32 dst = m68k_areg(regs, dstreg);
66398: { uae_u32 newv = dst + src;
66399: m68k_areg(regs, dstreg) = (newv);
66400: }}}}}}m68k_incpc(2);
66401: fill_prefetch_2 ();
66402: endlabel3621: ;
66403: return 14;
66404: }
66405: #endif
66406:
66407: #ifdef PART_8
66408: unsigned long REGPARAM2 CPUFUNC(op_d1d8_5)(uae_u32 opcode) /* ADDA */
66409: {
66410: uae_u32 srcreg = (opcode & 7);
66411: uae_u32 dstreg = (opcode >> 9) & 7;
66412: OpcodeFamily = 12; CurrentInstrCycles = 14;
66413: {{ uaecptr srca = m68k_areg(regs, srcreg);
66414: if ((srca & 1) != 0) {
66415: last_fault_for_exception_3 = srca;
66416: last_op_for_exception_3 = opcode;
66417: last_addr_for_exception_3 = m68k_getpc() + 2;
66418: Exception(3, 0, M68000_EXC_SRC_CPU);
66419: goto endlabel3622;
66420: }
66421: {{ uae_s32 src = get_long(srca);
66422: m68k_areg(regs, srcreg) += 4;
66423: { uae_s32 dst = m68k_areg(regs, dstreg);
66424: { uae_u32 newv = dst + src;
66425: m68k_areg(regs, dstreg) = (newv);
66426: }}}}}}m68k_incpc(2);
66427: fill_prefetch_2 ();
66428: endlabel3622: ;
66429: return 14;
66430: }
66431: unsigned long REGPARAM2 CPUFUNC(op_d1e0_5)(uae_u32 opcode) /* ADDA */
66432: {
66433: uae_u32 srcreg = (opcode & 7);
66434: uae_u32 dstreg = (opcode >> 9) & 7;
66435: OpcodeFamily = 12; CurrentInstrCycles = 16;
66436: {{ uaecptr srca = m68k_areg(regs, srcreg) - 4;
66437: if ((srca & 1) != 0) {
66438: last_fault_for_exception_3 = srca;
66439: last_op_for_exception_3 = opcode;
66440: last_addr_for_exception_3 = m68k_getpc() + 2;
66441: Exception(3, 0, M68000_EXC_SRC_CPU);
66442: goto endlabel3623;
66443: }
66444: {{ uae_s32 src = get_long(srca);
66445: m68k_areg (regs, srcreg) = srca;
66446: { uae_s32 dst = m68k_areg(regs, dstreg);
66447: { uae_u32 newv = dst + src;
66448: m68k_areg(regs, dstreg) = (newv);
66449: }}}}}}m68k_incpc(2);
66450: fill_prefetch_2 ();
66451: endlabel3623: ;
66452: return 16;
66453: }
66454: unsigned long REGPARAM2 CPUFUNC(op_d1e8_5)(uae_u32 opcode) /* ADDA */
66455: {
66456: uae_u32 srcreg = (opcode & 7);
66457: uae_u32 dstreg = (opcode >> 9) & 7;
66458: OpcodeFamily = 12; CurrentInstrCycles = 18;
66459: {{ uaecptr srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
66460: if ((srca & 1) != 0) {
66461: last_fault_for_exception_3 = srca;
66462: last_op_for_exception_3 = opcode;
66463: last_addr_for_exception_3 = m68k_getpc() + 4;
66464: Exception(3, 0, M68000_EXC_SRC_CPU);
66465: goto endlabel3624;
66466: }
66467: {{ uae_s32 src = get_long(srca);
66468: { uae_s32 dst = m68k_areg(regs, dstreg);
66469: { uae_u32 newv = dst + src;
66470: m68k_areg(regs, dstreg) = (newv);
66471: }}}}}}m68k_incpc(4);
66472: fill_prefetch_0 ();
66473: endlabel3624: ;
66474: return 18;
66475: }
66476: unsigned long REGPARAM2 CPUFUNC(op_d1f0_5)(uae_u32 opcode) /* ADDA */
66477: {
66478: uae_u32 srcreg = (opcode & 7);
66479: uae_u32 dstreg = (opcode >> 9) & 7;
66480: OpcodeFamily = 12; CurrentInstrCycles = 20;
66481: {{ uaecptr srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
66482: BusCyclePenalty += 2;
66483: if ((srca & 1) != 0) {
66484: last_fault_for_exception_3 = srca;
66485: last_op_for_exception_3 = opcode;
66486: last_addr_for_exception_3 = m68k_getpc() + 4;
66487: Exception(3, 0, M68000_EXC_SRC_CPU);
66488: goto endlabel3625;
66489: }
66490: {{ uae_s32 src = get_long(srca);
66491: { uae_s32 dst = m68k_areg(regs, dstreg);
66492: { uae_u32 newv = dst + src;
66493: m68k_areg(regs, dstreg) = (newv);
66494: }}}}}}m68k_incpc(4);
66495: fill_prefetch_0 ();
66496: endlabel3625: ;
66497: return 20;
66498: }
66499: unsigned long REGPARAM2 CPUFUNC(op_d1f8_5)(uae_u32 opcode) /* ADDA */
66500: {
66501: uae_u32 dstreg = (opcode >> 9) & 7;
66502: OpcodeFamily = 12; CurrentInstrCycles = 18;
66503: {{ uaecptr srca = (uae_s32)(uae_s16)get_iword_prefetch(2);
66504: if ((srca & 1) != 0) {
66505: last_fault_for_exception_3 = srca;
66506: last_op_for_exception_3 = opcode;
66507: last_addr_for_exception_3 = m68k_getpc() + 4;
66508: Exception(3, 0, M68000_EXC_SRC_CPU);
66509: goto endlabel3626;
66510: }
66511: {{ uae_s32 src = get_long(srca);
66512: { uae_s32 dst = m68k_areg(regs, dstreg);
66513: { uae_u32 newv = dst + src;
66514: m68k_areg(regs, dstreg) = (newv);
66515: }}}}}}m68k_incpc(4);
66516: fill_prefetch_0 ();
66517: endlabel3626: ;
66518: return 18;
66519: }
66520: unsigned long REGPARAM2 CPUFUNC(op_d1f9_5)(uae_u32 opcode) /* ADDA */
66521: {
66522: uae_u32 dstreg = (opcode >> 9) & 7;
66523: OpcodeFamily = 12; CurrentInstrCycles = 22;
66524: {{ uaecptr srca = get_ilong_prefetch(2);
66525: if ((srca & 1) != 0) {
66526: last_fault_for_exception_3 = srca;
66527: last_op_for_exception_3 = opcode;
66528: last_addr_for_exception_3 = m68k_getpc() + 6;
66529: Exception(3, 0, M68000_EXC_SRC_CPU);
66530: goto endlabel3627;
66531: }
66532: {{ uae_s32 src = get_long(srca);
66533: { uae_s32 dst = m68k_areg(regs, dstreg);
66534: { uae_u32 newv = dst + src;
66535: m68k_areg(regs, dstreg) = (newv);
66536: }}}}}}m68k_incpc(6);
66537: fill_prefetch_0 ();
66538: endlabel3627: ;
66539: return 22;
66540: }
66541: unsigned long REGPARAM2 CPUFUNC(op_d1fa_5)(uae_u32 opcode) /* ADDA */
66542: {
66543: uae_u32 dstreg = (opcode >> 9) & 7;
66544: OpcodeFamily = 12; CurrentInstrCycles = 18;
66545: {{ uaecptr srca = m68k_getpc () + 2;
66546: srca += (uae_s32)(uae_s16)get_iword_prefetch(2);
66547: if ((srca & 1) != 0) {
66548: last_fault_for_exception_3 = srca;
66549: last_op_for_exception_3 = opcode;
66550: last_addr_for_exception_3 = m68k_getpc() + 4;
66551: Exception(3, 0, M68000_EXC_SRC_CPU);
66552: goto endlabel3628;
66553: }
66554: {{ uae_s32 src = get_long(srca);
66555: { uae_s32 dst = m68k_areg(regs, dstreg);
66556: { uae_u32 newv = dst + src;
66557: m68k_areg(regs, dstreg) = (newv);
66558: }}}}}}m68k_incpc(4);
66559: fill_prefetch_0 ();
66560: endlabel3628: ;
66561: return 18;
66562: }
66563: unsigned long REGPARAM2 CPUFUNC(op_d1fb_5)(uae_u32 opcode) /* ADDA */
66564: {
66565: uae_u32 dstreg = (opcode >> 9) & 7;
66566: OpcodeFamily = 12; CurrentInstrCycles = 20;
66567: {{ uaecptr tmppc = m68k_getpc() + 2;
66568: uaecptr srca = get_disp_ea_000(tmppc, get_iword_prefetch(2));
66569: BusCyclePenalty += 2;
66570: if ((srca & 1) != 0) {
66571: last_fault_for_exception_3 = srca;
66572: last_op_for_exception_3 = opcode;
66573: last_addr_for_exception_3 = m68k_getpc() + 4;
66574: Exception(3, 0, M68000_EXC_SRC_CPU);
66575: goto endlabel3629;
66576: }
66577: {{ uae_s32 src = get_long(srca);
66578: { uae_s32 dst = m68k_areg(regs, dstreg);
66579: { uae_u32 newv = dst + src;
66580: m68k_areg(regs, dstreg) = (newv);
66581: }}}}}}m68k_incpc(4);
66582: fill_prefetch_0 ();
66583: endlabel3629: ;
66584: return 20;
66585: }
66586: unsigned long REGPARAM2 CPUFUNC(op_d1fc_5)(uae_u32 opcode) /* ADDA */
66587: {
66588: uae_u32 dstreg = (opcode >> 9) & 7;
66589: OpcodeFamily = 12; CurrentInstrCycles = 16;
66590: {{ uae_s32 src = get_ilong_prefetch(2);
66591: { uae_s32 dst = m68k_areg(regs, dstreg);
66592: { uae_u32 newv = dst + src;
66593: m68k_areg(regs, dstreg) = (newv);
66594: }}}}m68k_incpc(6);
66595: fill_prefetch_0 ();
66596: return 16;
66597: }
66598: unsigned long REGPARAM2 CPUFUNC(op_e000_5)(uae_u32 opcode) /* ASR */
66599: {
66600: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
66601: uae_u32 dstreg = opcode & 7;
66602: unsigned int retcycles = 0;
66603: OpcodeFamily = 64; CurrentInstrCycles = 4;
66604: {{ uae_u32 cnt = srcreg;
66605: { uae_s8 data = m68k_dreg(regs, dstreg);
66606: { uae_u32 val = (uae_u8)data;
66607: uae_u32 sign = (0x80 & val) >> 7;
66608: cnt &= 63;
66609: retcycles = cnt;
66610: CLEAR_CZNV;
66611: if (cnt >= 8) {
66612: val = 0xff & (uae_u32)-sign;
66613: SET_CFLG (sign);
66614: COPY_CARRY;
66615: } else {
66616: val >>= cnt - 1;
66617: SET_CFLG (val & 1);
66618: COPY_CARRY;
66619: val >>= 1;
66620: val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
66621: val &= 0xff;
66622: }
66623: SET_ZFLG (((uae_s8)(val)) == 0);
66624: SET_NFLG (((uae_s8)(val)) < 0);
66625: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
66626: }}}}m68k_incpc(2);
66627: fill_prefetch_2 ();
66628: return (6+retcycles*2);
66629: }
66630: unsigned long REGPARAM2 CPUFUNC(op_e008_5)(uae_u32 opcode) /* LSR */
66631: {
66632: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
66633: uae_u32 dstreg = opcode & 7;
66634: unsigned int retcycles = 0;
66635: OpcodeFamily = 66; CurrentInstrCycles = 4;
66636: {{ uae_u32 cnt = srcreg;
66637: { uae_s8 data = m68k_dreg(regs, dstreg);
66638: { uae_u32 val = (uae_u8)data;
66639: cnt &= 63;
66640: retcycles = cnt;
66641: CLEAR_CZNV;
66642: if (cnt >= 8) {
66643: SET_CFLG ((cnt == 8) & (val >> 7));
66644: COPY_CARRY;
66645: val = 0;
66646: } else {
66647: val >>= cnt - 1;
66648: SET_CFLG (val & 1);
66649: COPY_CARRY;
66650: val >>= 1;
66651: }
66652: SET_ZFLG (((uae_s8)(val)) == 0);
66653: SET_NFLG (((uae_s8)(val)) < 0);
66654: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
66655: }}}}m68k_incpc(2);
66656: fill_prefetch_2 ();
66657: return (6+retcycles*2);
66658: }
66659: unsigned long REGPARAM2 CPUFUNC(op_e010_5)(uae_u32 opcode) /* ROXR */
66660: {
66661: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
66662: uae_u32 dstreg = opcode & 7;
66663: unsigned int retcycles = 0;
66664: OpcodeFamily = 71; CurrentInstrCycles = 4;
66665: {{ uae_u32 cnt = srcreg;
66666: { uae_s8 data = m68k_dreg(regs, dstreg);
66667: { uae_u32 val = (uae_u8)data;
66668: cnt &= 63;
66669: retcycles = cnt;
66670: CLEAR_CZNV;
66671: { cnt--;
66672: {
66673: uae_u32 carry;
66674: uae_u32 hival = (val << 1) | GET_XFLG;
66675: hival <<= (7 - cnt);
66676: val >>= cnt;
66677: carry = val & 1;
66678: val >>= 1;
66679: val |= hival;
66680: SET_XFLG (carry);
66681: val &= 0xff;
66682: } }
66683: SET_CFLG (GET_XFLG);
66684: SET_ZFLG (((uae_s8)(val)) == 0);
66685: SET_NFLG (((uae_s8)(val)) < 0);
66686: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
66687: }}}}m68k_incpc(2);
66688: fill_prefetch_2 ();
66689: return (6+retcycles*2);
66690: }
66691: unsigned long REGPARAM2 CPUFUNC(op_e018_5)(uae_u32 opcode) /* ROR */
66692: {
66693: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
66694: uae_u32 dstreg = opcode & 7;
66695: unsigned int retcycles = 0;
66696: OpcodeFamily = 69; CurrentInstrCycles = 4;
66697: {{ uae_u32 cnt = srcreg;
66698: { uae_s8 data = m68k_dreg(regs, dstreg);
66699: { uae_u32 val = (uae_u8)data;
66700: cnt &= 63;
66701: retcycles = cnt;
66702: CLEAR_CZNV;
66703: { uae_u32 hival;
66704: cnt &= 7;
66705: hival = val << (8 - cnt);
66706: val >>= cnt;
66707: val |= hival;
66708: val &= 0xff;
66709: SET_CFLG ((val & 0x80) >> 7);
66710: }
66711: SET_ZFLG (((uae_s8)(val)) == 0);
66712: SET_NFLG (((uae_s8)(val)) < 0);
66713: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
66714: }}}}m68k_incpc(2);
66715: fill_prefetch_2 ();
66716: return (6+retcycles*2);
66717: }
66718: unsigned long REGPARAM2 CPUFUNC(op_e020_5)(uae_u32 opcode) /* ASR */
66719: {
66720: uae_u32 srcreg = ((opcode >> 9) & 7);
66721: uae_u32 dstreg = opcode & 7;
66722: unsigned int retcycles = 0;
66723: OpcodeFamily = 64; CurrentInstrCycles = 4;
66724: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
66725: { uae_s8 data = m68k_dreg(regs, dstreg);
66726: { uae_u32 val = (uae_u8)data;
66727: uae_u32 sign = (0x80 & val) >> 7;
66728: cnt &= 63;
66729: retcycles = cnt;
66730: CLEAR_CZNV;
66731: if (cnt >= 8) {
66732: val = 0xff & (uae_u32)-sign;
66733: SET_CFLG (sign);
66734: COPY_CARRY;
66735: } else if (cnt > 0) {
66736: val >>= cnt - 1;
66737: SET_CFLG (val & 1);
66738: COPY_CARRY;
66739: val >>= 1;
66740: val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
66741: val &= 0xff;
66742: }
66743: SET_ZFLG (((uae_s8)(val)) == 0);
66744: SET_NFLG (((uae_s8)(val)) < 0);
66745: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
66746: }}}}m68k_incpc(2);
66747: fill_prefetch_2 ();
66748: return (6+retcycles*2);
66749: }
66750: unsigned long REGPARAM2 CPUFUNC(op_e028_5)(uae_u32 opcode) /* LSR */
66751: {
66752: uae_u32 srcreg = ((opcode >> 9) & 7);
66753: uae_u32 dstreg = opcode & 7;
66754: unsigned int retcycles = 0;
66755: OpcodeFamily = 66; CurrentInstrCycles = 4;
66756: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
66757: { uae_s8 data = m68k_dreg(regs, dstreg);
66758: { uae_u32 val = (uae_u8)data;
66759: cnt &= 63;
66760: retcycles = cnt;
66761: CLEAR_CZNV;
66762: if (cnt >= 8) {
66763: SET_CFLG ((cnt == 8) & (val >> 7));
66764: COPY_CARRY;
66765: val = 0;
66766: } else if (cnt > 0) {
66767: val >>= cnt - 1;
66768: SET_CFLG (val & 1);
66769: COPY_CARRY;
66770: val >>= 1;
66771: }
66772: SET_ZFLG (((uae_s8)(val)) == 0);
66773: SET_NFLG (((uae_s8)(val)) < 0);
66774: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
66775: }}}}m68k_incpc(2);
66776: fill_prefetch_2 ();
66777: return (6+retcycles*2);
66778: }
66779: unsigned long REGPARAM2 CPUFUNC(op_e030_5)(uae_u32 opcode) /* ROXR */
66780: {
66781: uae_u32 srcreg = ((opcode >> 9) & 7);
66782: uae_u32 dstreg = opcode & 7;
66783: unsigned int retcycles = 0;
66784: OpcodeFamily = 71; CurrentInstrCycles = 4;
66785: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
66786: { uae_s8 data = m68k_dreg(regs, dstreg);
66787: { uae_u32 val = (uae_u8)data;
66788: cnt &= 63;
66789: retcycles = cnt;
66790: CLEAR_CZNV;
66791: if (cnt >= 36) cnt -= 36;
66792: if (cnt >= 18) cnt -= 18;
66793: if (cnt >= 9) cnt -= 9;
66794: if (cnt > 0) {
66795: cnt--;
66796: {
66797: uae_u32 carry;
66798: uae_u32 hival = (val << 1) | GET_XFLG;
66799: hival <<= (7 - cnt);
66800: val >>= cnt;
66801: carry = val & 1;
66802: val >>= 1;
66803: val |= hival;
66804: SET_XFLG (carry);
66805: val &= 0xff;
66806: } }
66807: SET_CFLG (GET_XFLG);
66808: SET_ZFLG (((uae_s8)(val)) == 0);
66809: SET_NFLG (((uae_s8)(val)) < 0);
66810: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
66811: }}}}m68k_incpc(2);
66812: fill_prefetch_2 ();
66813: return (6+retcycles*2);
66814: }
66815: unsigned long REGPARAM2 CPUFUNC(op_e038_5)(uae_u32 opcode) /* ROR */
66816: {
66817: uae_u32 srcreg = ((opcode >> 9) & 7);
66818: uae_u32 dstreg = opcode & 7;
66819: unsigned int retcycles = 0;
66820: OpcodeFamily = 69; CurrentInstrCycles = 4;
66821: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
66822: { uae_s8 data = m68k_dreg(regs, dstreg);
66823: { uae_u32 val = (uae_u8)data;
66824: cnt &= 63;
66825: retcycles = cnt;
66826: CLEAR_CZNV;
66827: if (cnt > 0) { uae_u32 hival;
66828: cnt &= 7;
66829: hival = val << (8 - cnt);
66830: val >>= cnt;
66831: val |= hival;
66832: val &= 0xff;
66833: SET_CFLG ((val & 0x80) >> 7);
66834: }
66835: SET_ZFLG (((uae_s8)(val)) == 0);
66836: SET_NFLG (((uae_s8)(val)) < 0);
66837: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
66838: }}}}m68k_incpc(2);
66839: fill_prefetch_2 ();
66840: return (6+retcycles*2);
66841: }
66842: unsigned long REGPARAM2 CPUFUNC(op_e040_5)(uae_u32 opcode) /* ASR */
66843: {
66844: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
66845: uae_u32 dstreg = opcode & 7;
66846: unsigned int retcycles = 0;
66847: OpcodeFamily = 64; CurrentInstrCycles = 4;
66848: {{ uae_u32 cnt = srcreg;
66849: { uae_s16 data = m68k_dreg(regs, dstreg);
66850: { uae_u32 val = (uae_u16)data;
66851: uae_u32 sign = (0x8000 & val) >> 15;
66852: cnt &= 63;
66853: retcycles = cnt;
66854: CLEAR_CZNV;
66855: if (cnt >= 16) {
66856: val = 0xffff & (uae_u32)-sign;
66857: SET_CFLG (sign);
66858: COPY_CARRY;
66859: } else {
66860: val >>= cnt - 1;
66861: SET_CFLG (val & 1);
66862: COPY_CARRY;
66863: val >>= 1;
66864: val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
66865: val &= 0xffff;
66866: }
66867: SET_ZFLG (((uae_s16)(val)) == 0);
66868: SET_NFLG (((uae_s16)(val)) < 0);
66869: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
66870: }}}}m68k_incpc(2);
66871: fill_prefetch_2 ();
66872: return (6+retcycles*2);
66873: }
66874: unsigned long REGPARAM2 CPUFUNC(op_e048_5)(uae_u32 opcode) /* LSR */
66875: {
66876: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
66877: uae_u32 dstreg = opcode & 7;
66878: unsigned int retcycles = 0;
66879: OpcodeFamily = 66; CurrentInstrCycles = 4;
66880: {{ uae_u32 cnt = srcreg;
66881: { uae_s16 data = m68k_dreg(regs, dstreg);
66882: { uae_u32 val = (uae_u16)data;
66883: cnt &= 63;
66884: retcycles = cnt;
66885: CLEAR_CZNV;
66886: if (cnt >= 16) {
66887: SET_CFLG ((cnt == 16) & (val >> 15));
66888: COPY_CARRY;
66889: val = 0;
66890: } else {
66891: val >>= cnt - 1;
66892: SET_CFLG (val & 1);
66893: COPY_CARRY;
66894: val >>= 1;
66895: }
66896: SET_ZFLG (((uae_s16)(val)) == 0);
66897: SET_NFLG (((uae_s16)(val)) < 0);
66898: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
66899: }}}}m68k_incpc(2);
66900: fill_prefetch_2 ();
66901: return (6+retcycles*2);
66902: }
66903: unsigned long REGPARAM2 CPUFUNC(op_e050_5)(uae_u32 opcode) /* ROXR */
66904: {
66905: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
66906: uae_u32 dstreg = opcode & 7;
66907: unsigned int retcycles = 0;
66908: OpcodeFamily = 71; CurrentInstrCycles = 4;
66909: {{ uae_u32 cnt = srcreg;
66910: { uae_s16 data = m68k_dreg(regs, dstreg);
66911: { uae_u32 val = (uae_u16)data;
66912: cnt &= 63;
66913: retcycles = cnt;
66914: CLEAR_CZNV;
66915: { cnt--;
66916: {
66917: uae_u32 carry;
66918: uae_u32 hival = (val << 1) | GET_XFLG;
66919: hival <<= (15 - cnt);
66920: val >>= cnt;
66921: carry = val & 1;
66922: val >>= 1;
66923: val |= hival;
66924: SET_XFLG (carry);
66925: val &= 0xffff;
66926: } }
66927: SET_CFLG (GET_XFLG);
66928: SET_ZFLG (((uae_s16)(val)) == 0);
66929: SET_NFLG (((uae_s16)(val)) < 0);
66930: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
66931: }}}}m68k_incpc(2);
66932: fill_prefetch_2 ();
66933: return (6+retcycles*2);
66934: }
66935: unsigned long REGPARAM2 CPUFUNC(op_e058_5)(uae_u32 opcode) /* ROR */
66936: {
66937: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
66938: uae_u32 dstreg = opcode & 7;
66939: unsigned int retcycles = 0;
66940: OpcodeFamily = 69; CurrentInstrCycles = 4;
66941: {{ uae_u32 cnt = srcreg;
66942: { uae_s16 data = m68k_dreg(regs, dstreg);
66943: { uae_u32 val = (uae_u16)data;
66944: cnt &= 63;
66945: retcycles = cnt;
66946: CLEAR_CZNV;
66947: { uae_u32 hival;
66948: cnt &= 15;
66949: hival = val << (16 - cnt);
66950: val >>= cnt;
66951: val |= hival;
66952: val &= 0xffff;
66953: SET_CFLG ((val & 0x8000) >> 15);
66954: }
66955: SET_ZFLG (((uae_s16)(val)) == 0);
66956: SET_NFLG (((uae_s16)(val)) < 0);
66957: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
66958: }}}}m68k_incpc(2);
66959: fill_prefetch_2 ();
66960: return (6+retcycles*2);
66961: }
66962: unsigned long REGPARAM2 CPUFUNC(op_e060_5)(uae_u32 opcode) /* ASR */
66963: {
66964: uae_u32 srcreg = ((opcode >> 9) & 7);
66965: uae_u32 dstreg = opcode & 7;
66966: unsigned int retcycles = 0;
66967: OpcodeFamily = 64; CurrentInstrCycles = 4;
66968: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
66969: { uae_s16 data = m68k_dreg(regs, dstreg);
66970: { uae_u32 val = (uae_u16)data;
66971: uae_u32 sign = (0x8000 & val) >> 15;
66972: cnt &= 63;
66973: retcycles = cnt;
66974: CLEAR_CZNV;
66975: if (cnt >= 16) {
66976: val = 0xffff & (uae_u32)-sign;
66977: SET_CFLG (sign);
66978: COPY_CARRY;
66979: } else if (cnt > 0) {
66980: val >>= cnt - 1;
66981: SET_CFLG (val & 1);
66982: COPY_CARRY;
66983: val >>= 1;
66984: val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
66985: val &= 0xffff;
66986: }
66987: SET_ZFLG (((uae_s16)(val)) == 0);
66988: SET_NFLG (((uae_s16)(val)) < 0);
66989: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
66990: }}}}m68k_incpc(2);
66991: fill_prefetch_2 ();
66992: return (6+retcycles*2);
66993: }
66994: unsigned long REGPARAM2 CPUFUNC(op_e068_5)(uae_u32 opcode) /* LSR */
66995: {
66996: uae_u32 srcreg = ((opcode >> 9) & 7);
66997: uae_u32 dstreg = opcode & 7;
66998: unsigned int retcycles = 0;
66999: OpcodeFamily = 66; CurrentInstrCycles = 4;
67000: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
67001: { uae_s16 data = m68k_dreg(regs, dstreg);
67002: { uae_u32 val = (uae_u16)data;
67003: cnt &= 63;
67004: retcycles = cnt;
67005: CLEAR_CZNV;
67006: if (cnt >= 16) {
67007: SET_CFLG ((cnt == 16) & (val >> 15));
67008: COPY_CARRY;
67009: val = 0;
67010: } else if (cnt > 0) {
67011: val >>= cnt - 1;
67012: SET_CFLG (val & 1);
67013: COPY_CARRY;
67014: val >>= 1;
67015: }
67016: SET_ZFLG (((uae_s16)(val)) == 0);
67017: SET_NFLG (((uae_s16)(val)) < 0);
67018: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67019: }}}}m68k_incpc(2);
67020: fill_prefetch_2 ();
67021: return (6+retcycles*2);
67022: }
67023: unsigned long REGPARAM2 CPUFUNC(op_e070_5)(uae_u32 opcode) /* ROXR */
67024: {
67025: uae_u32 srcreg = ((opcode >> 9) & 7);
67026: uae_u32 dstreg = opcode & 7;
67027: unsigned int retcycles = 0;
67028: OpcodeFamily = 71; CurrentInstrCycles = 4;
67029: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
67030: { uae_s16 data = m68k_dreg(regs, dstreg);
67031: { uae_u32 val = (uae_u16)data;
67032: cnt &= 63;
67033: retcycles = cnt;
67034: CLEAR_CZNV;
67035: if (cnt >= 34) cnt -= 34;
67036: if (cnt >= 17) cnt -= 17;
67037: if (cnt > 0) {
67038: cnt--;
67039: {
67040: uae_u32 carry;
67041: uae_u32 hival = (val << 1) | GET_XFLG;
67042: hival <<= (15 - cnt);
67043: val >>= cnt;
67044: carry = val & 1;
67045: val >>= 1;
67046: val |= hival;
67047: SET_XFLG (carry);
67048: val &= 0xffff;
67049: } }
67050: SET_CFLG (GET_XFLG);
67051: SET_ZFLG (((uae_s16)(val)) == 0);
67052: SET_NFLG (((uae_s16)(val)) < 0);
67053: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67054: }}}}m68k_incpc(2);
67055: fill_prefetch_2 ();
67056: return (6+retcycles*2);
67057: }
67058: unsigned long REGPARAM2 CPUFUNC(op_e078_5)(uae_u32 opcode) /* ROR */
67059: {
67060: uae_u32 srcreg = ((opcode >> 9) & 7);
67061: uae_u32 dstreg = opcode & 7;
67062: unsigned int retcycles = 0;
67063: OpcodeFamily = 69; CurrentInstrCycles = 4;
67064: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
67065: { uae_s16 data = m68k_dreg(regs, dstreg);
67066: { uae_u32 val = (uae_u16)data;
67067: cnt &= 63;
67068: retcycles = cnt;
67069: CLEAR_CZNV;
67070: if (cnt > 0) { uae_u32 hival;
67071: cnt &= 15;
67072: hival = val << (16 - cnt);
67073: val >>= cnt;
67074: val |= hival;
67075: val &= 0xffff;
67076: SET_CFLG ((val & 0x8000) >> 15);
67077: }
67078: SET_ZFLG (((uae_s16)(val)) == 0);
67079: SET_NFLG (((uae_s16)(val)) < 0);
67080: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67081: }}}}m68k_incpc(2);
67082: fill_prefetch_2 ();
67083: return (6+retcycles*2);
67084: }
67085: unsigned long REGPARAM2 CPUFUNC(op_e080_5)(uae_u32 opcode) /* ASR */
67086: {
67087: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67088: uae_u32 dstreg = opcode & 7;
67089: unsigned int retcycles = 0;
67090: OpcodeFamily = 64; CurrentInstrCycles = 4;
67091: {{ uae_u32 cnt = srcreg;
67092: { uae_s32 data = m68k_dreg(regs, dstreg);
67093: { uae_u32 val = data;
67094: uae_u32 sign = (0x80000000 & val) >> 31;
67095: cnt &= 63;
67096: retcycles = cnt;
67097: CLEAR_CZNV;
67098: if (cnt >= 32) {
67099: val = 0xffffffff & (uae_u32)-sign;
67100: SET_CFLG (sign);
67101: COPY_CARRY;
67102: } else {
67103: val >>= cnt - 1;
67104: SET_CFLG (val & 1);
67105: COPY_CARRY;
67106: val >>= 1;
67107: val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
67108: val &= 0xffffffff;
67109: }
67110: SET_ZFLG (((uae_s32)(val)) == 0);
67111: SET_NFLG (((uae_s32)(val)) < 0);
67112: m68k_dreg(regs, dstreg) = (val);
67113: }}}}m68k_incpc(2);
67114: fill_prefetch_2 ();
67115: return (8+retcycles*2);
67116: }
67117: unsigned long REGPARAM2 CPUFUNC(op_e088_5)(uae_u32 opcode) /* LSR */
67118: {
67119: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67120: uae_u32 dstreg = opcode & 7;
67121: unsigned int retcycles = 0;
67122: OpcodeFamily = 66; CurrentInstrCycles = 4;
67123: {{ uae_u32 cnt = srcreg;
67124: { uae_s32 data = m68k_dreg(regs, dstreg);
67125: { uae_u32 val = data;
67126: cnt &= 63;
67127: retcycles = cnt;
67128: CLEAR_CZNV;
67129: if (cnt >= 32) {
67130: SET_CFLG ((cnt == 32) & (val >> 31));
67131: COPY_CARRY;
67132: val = 0;
67133: } else {
67134: val >>= cnt - 1;
67135: SET_CFLG (val & 1);
67136: COPY_CARRY;
67137: val >>= 1;
67138: }
67139: SET_ZFLG (((uae_s32)(val)) == 0);
67140: SET_NFLG (((uae_s32)(val)) < 0);
67141: m68k_dreg(regs, dstreg) = (val);
67142: }}}}m68k_incpc(2);
67143: fill_prefetch_2 ();
67144: return (8+retcycles*2);
67145: }
67146: unsigned long REGPARAM2 CPUFUNC(op_e090_5)(uae_u32 opcode) /* ROXR */
67147: {
67148: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67149: uae_u32 dstreg = opcode & 7;
67150: unsigned int retcycles = 0;
67151: OpcodeFamily = 71; CurrentInstrCycles = 4;
67152: {{ uae_u32 cnt = srcreg;
67153: { uae_s32 data = m68k_dreg(regs, dstreg);
67154: { uae_u32 val = data;
67155: cnt &= 63;
67156: retcycles = cnt;
67157: CLEAR_CZNV;
67158: { cnt--;
67159: {
67160: uae_u32 carry;
67161: uae_u32 hival = (val << 1) | GET_XFLG;
67162: hival <<= (31 - cnt);
67163: val >>= cnt;
67164: carry = val & 1;
67165: val >>= 1;
67166: val |= hival;
67167: SET_XFLG (carry);
67168: val &= 0xffffffff;
67169: } }
67170: SET_CFLG (GET_XFLG);
67171: SET_ZFLG (((uae_s32)(val)) == 0);
67172: SET_NFLG (((uae_s32)(val)) < 0);
67173: m68k_dreg(regs, dstreg) = (val);
67174: }}}}m68k_incpc(2);
67175: fill_prefetch_2 ();
67176: return (8+retcycles*2);
67177: }
67178: unsigned long REGPARAM2 CPUFUNC(op_e098_5)(uae_u32 opcode) /* ROR */
67179: {
67180: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67181: uae_u32 dstreg = opcode & 7;
67182: unsigned int retcycles = 0;
67183: OpcodeFamily = 69; CurrentInstrCycles = 4;
67184: {{ uae_u32 cnt = srcreg;
67185: { uae_s32 data = m68k_dreg(regs, dstreg);
67186: { uae_u32 val = data;
67187: cnt &= 63;
67188: retcycles = cnt;
67189: CLEAR_CZNV;
67190: { uae_u32 hival;
67191: cnt &= 31;
67192: hival = val << (32 - cnt);
67193: val >>= cnt;
67194: val |= hival;
67195: val &= 0xffffffff;
67196: SET_CFLG ((val & 0x80000000) >> 31);
67197: }
67198: SET_ZFLG (((uae_s32)(val)) == 0);
67199: SET_NFLG (((uae_s32)(val)) < 0);
67200: m68k_dreg(regs, dstreg) = (val);
67201: }}}}m68k_incpc(2);
67202: fill_prefetch_2 ();
67203: return (8+retcycles*2);
67204: }
67205: unsigned long REGPARAM2 CPUFUNC(op_e0a0_5)(uae_u32 opcode) /* ASR */
67206: {
67207: uae_u32 srcreg = ((opcode >> 9) & 7);
67208: uae_u32 dstreg = opcode & 7;
67209: unsigned int retcycles = 0;
67210: OpcodeFamily = 64; CurrentInstrCycles = 4;
67211: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
67212: { uae_s32 data = m68k_dreg(regs, dstreg);
67213: { uae_u32 val = data;
67214: uae_u32 sign = (0x80000000 & val) >> 31;
67215: cnt &= 63;
67216: retcycles = cnt;
67217: CLEAR_CZNV;
67218: if (cnt >= 32) {
67219: val = 0xffffffff & (uae_u32)-sign;
67220: SET_CFLG (sign);
67221: COPY_CARRY;
67222: } else if (cnt > 0) {
67223: val >>= cnt - 1;
67224: SET_CFLG (val & 1);
67225: COPY_CARRY;
67226: val >>= 1;
67227: val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
67228: val &= 0xffffffff;
67229: }
67230: SET_ZFLG (((uae_s32)(val)) == 0);
67231: SET_NFLG (((uae_s32)(val)) < 0);
67232: m68k_dreg(regs, dstreg) = (val);
67233: }}}}m68k_incpc(2);
67234: fill_prefetch_2 ();
67235: return (8+retcycles*2);
67236: }
67237: unsigned long REGPARAM2 CPUFUNC(op_e0a8_5)(uae_u32 opcode) /* LSR */
67238: {
67239: uae_u32 srcreg = ((opcode >> 9) & 7);
67240: uae_u32 dstreg = opcode & 7;
67241: unsigned int retcycles = 0;
67242: OpcodeFamily = 66; CurrentInstrCycles = 4;
67243: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
67244: { uae_s32 data = m68k_dreg(regs, dstreg);
67245: { uae_u32 val = data;
67246: cnt &= 63;
67247: retcycles = cnt;
67248: CLEAR_CZNV;
67249: if (cnt >= 32) {
67250: SET_CFLG ((cnt == 32) & (val >> 31));
67251: COPY_CARRY;
67252: val = 0;
67253: } else if (cnt > 0) {
67254: val >>= cnt - 1;
67255: SET_CFLG (val & 1);
67256: COPY_CARRY;
67257: val >>= 1;
67258: }
67259: SET_ZFLG (((uae_s32)(val)) == 0);
67260: SET_NFLG (((uae_s32)(val)) < 0);
67261: m68k_dreg(regs, dstreg) = (val);
67262: }}}}m68k_incpc(2);
67263: fill_prefetch_2 ();
67264: return (8+retcycles*2);
67265: }
67266: unsigned long REGPARAM2 CPUFUNC(op_e0b0_5)(uae_u32 opcode) /* ROXR */
67267: {
67268: uae_u32 srcreg = ((opcode >> 9) & 7);
67269: uae_u32 dstreg = opcode & 7;
67270: unsigned int retcycles = 0;
67271: OpcodeFamily = 71; CurrentInstrCycles = 4;
67272: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
67273: { uae_s32 data = m68k_dreg(regs, dstreg);
67274: { uae_u32 val = data;
67275: cnt &= 63;
67276: retcycles = cnt;
67277: CLEAR_CZNV;
67278: if (cnt >= 33) cnt -= 33;
67279: if (cnt > 0) {
67280: cnt--;
67281: {
67282: uae_u32 carry;
67283: uae_u32 hival = (val << 1) | GET_XFLG;
67284: hival <<= (31 - cnt);
67285: val >>= cnt;
67286: carry = val & 1;
67287: val >>= 1;
67288: val |= hival;
67289: SET_XFLG (carry);
67290: val &= 0xffffffff;
67291: } }
67292: SET_CFLG (GET_XFLG);
67293: SET_ZFLG (((uae_s32)(val)) == 0);
67294: SET_NFLG (((uae_s32)(val)) < 0);
67295: m68k_dreg(regs, dstreg) = (val);
67296: }}}}m68k_incpc(2);
67297: fill_prefetch_2 ();
67298: return (8+retcycles*2);
67299: }
67300: unsigned long REGPARAM2 CPUFUNC(op_e0b8_5)(uae_u32 opcode) /* ROR */
67301: {
67302: uae_u32 srcreg = ((opcode >> 9) & 7);
67303: uae_u32 dstreg = opcode & 7;
67304: unsigned int retcycles = 0;
67305: OpcodeFamily = 69; CurrentInstrCycles = 4;
67306: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
67307: { uae_s32 data = m68k_dreg(regs, dstreg);
67308: { uae_u32 val = data;
67309: cnt &= 63;
67310: retcycles = cnt;
67311: CLEAR_CZNV;
67312: if (cnt > 0) { uae_u32 hival;
67313: cnt &= 31;
67314: hival = val << (32 - cnt);
67315: val >>= cnt;
67316: val |= hival;
67317: val &= 0xffffffff;
67318: SET_CFLG ((val & 0x80000000) >> 31);
67319: }
67320: SET_ZFLG (((uae_s32)(val)) == 0);
67321: SET_NFLG (((uae_s32)(val)) < 0);
67322: m68k_dreg(regs, dstreg) = (val);
67323: }}}}m68k_incpc(2);
67324: fill_prefetch_2 ();
67325: return (8+retcycles*2);
67326: }
67327: unsigned long REGPARAM2 CPUFUNC(op_e0d0_5)(uae_u32 opcode) /* ASRW */
67328: {
67329: uae_u32 srcreg = (opcode & 7);
67330: OpcodeFamily = 72; CurrentInstrCycles = 12;
67331: {{ uaecptr dataa = m68k_areg(regs, srcreg);
67332: if ((dataa & 1) != 0) {
67333: last_fault_for_exception_3 = dataa;
67334: last_op_for_exception_3 = opcode;
67335: last_addr_for_exception_3 = m68k_getpc() + 2;
67336: Exception(3, 0, M68000_EXC_SRC_CPU);
67337: goto endlabel3655;
67338: }
67339: {{ uae_s16 data = get_word(dataa);
67340: { uae_u32 val = (uae_u16)data;
67341: uae_u32 sign = 0x8000 & val;
67342: uae_u32 cflg = val & 1;
67343: val = (val >> 1) | sign;
67344: CLEAR_CZNV;
67345: SET_ZFLG (((uae_s16)(val)) == 0);
67346: SET_NFLG (((uae_s16)(val)) < 0);
67347: SET_CFLG (cflg);
67348: COPY_CARRY;
67349: m68k_incpc(2);
67350: fill_prefetch_2 ();
67351: put_word(dataa,val);
67352: }}}}}endlabel3655: ;
67353: return 12;
67354: }
67355: unsigned long REGPARAM2 CPUFUNC(op_e0d8_5)(uae_u32 opcode) /* ASRW */
67356: {
67357: uae_u32 srcreg = (opcode & 7);
67358: OpcodeFamily = 72; CurrentInstrCycles = 12;
67359: {{ uaecptr dataa = m68k_areg(regs, srcreg);
67360: if ((dataa & 1) != 0) {
67361: last_fault_for_exception_3 = dataa;
67362: last_op_for_exception_3 = opcode;
67363: last_addr_for_exception_3 = m68k_getpc() + 2;
67364: Exception(3, 0, M68000_EXC_SRC_CPU);
67365: goto endlabel3656;
67366: }
67367: {{ uae_s16 data = get_word(dataa);
67368: m68k_areg(regs, srcreg) += 2;
67369: { uae_u32 val = (uae_u16)data;
67370: uae_u32 sign = 0x8000 & val;
67371: uae_u32 cflg = val & 1;
67372: val = (val >> 1) | sign;
67373: CLEAR_CZNV;
67374: SET_ZFLG (((uae_s16)(val)) == 0);
67375: SET_NFLG (((uae_s16)(val)) < 0);
67376: SET_CFLG (cflg);
67377: COPY_CARRY;
67378: m68k_incpc(2);
67379: fill_prefetch_2 ();
67380: put_word(dataa,val);
67381: }}}}}endlabel3656: ;
67382: return 12;
67383: }
67384: unsigned long REGPARAM2 CPUFUNC(op_e0e0_5)(uae_u32 opcode) /* ASRW */
67385: {
67386: uae_u32 srcreg = (opcode & 7);
67387: OpcodeFamily = 72; CurrentInstrCycles = 14;
67388: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
67389: if ((dataa & 1) != 0) {
67390: last_fault_for_exception_3 = dataa;
67391: last_op_for_exception_3 = opcode;
67392: last_addr_for_exception_3 = m68k_getpc() + 2;
67393: Exception(3, 0, M68000_EXC_SRC_CPU);
67394: goto endlabel3657;
67395: }
67396: {{ uae_s16 data = get_word(dataa);
67397: m68k_areg (regs, srcreg) = dataa;
67398: { uae_u32 val = (uae_u16)data;
67399: uae_u32 sign = 0x8000 & val;
67400: uae_u32 cflg = val & 1;
67401: val = (val >> 1) | sign;
67402: CLEAR_CZNV;
67403: SET_ZFLG (((uae_s16)(val)) == 0);
67404: SET_NFLG (((uae_s16)(val)) < 0);
67405: SET_CFLG (cflg);
67406: COPY_CARRY;
67407: m68k_incpc(2);
67408: fill_prefetch_2 ();
67409: put_word(dataa,val);
67410: }}}}}endlabel3657: ;
67411: return 14;
67412: }
67413: unsigned long REGPARAM2 CPUFUNC(op_e0e8_5)(uae_u32 opcode) /* ASRW */
67414: {
67415: uae_u32 srcreg = (opcode & 7);
67416: OpcodeFamily = 72; CurrentInstrCycles = 16;
67417: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
67418: if ((dataa & 1) != 0) {
67419: last_fault_for_exception_3 = dataa;
67420: last_op_for_exception_3 = opcode;
67421: last_addr_for_exception_3 = m68k_getpc() + 4;
67422: Exception(3, 0, M68000_EXC_SRC_CPU);
67423: goto endlabel3658;
67424: }
67425: {{ uae_s16 data = get_word(dataa);
67426: { uae_u32 val = (uae_u16)data;
67427: uae_u32 sign = 0x8000 & val;
67428: uae_u32 cflg = val & 1;
67429: val = (val >> 1) | sign;
67430: CLEAR_CZNV;
67431: SET_ZFLG (((uae_s16)(val)) == 0);
67432: SET_NFLG (((uae_s16)(val)) < 0);
67433: SET_CFLG (cflg);
67434: COPY_CARRY;
67435: m68k_incpc(4);
67436: fill_prefetch_0 ();
67437: put_word(dataa,val);
67438: }}}}}endlabel3658: ;
67439: return 16;
67440: }
67441: unsigned long REGPARAM2 CPUFUNC(op_e0f0_5)(uae_u32 opcode) /* ASRW */
67442: {
67443: uae_u32 srcreg = (opcode & 7);
67444: OpcodeFamily = 72; CurrentInstrCycles = 18;
67445: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
67446: BusCyclePenalty += 2;
67447: if ((dataa & 1) != 0) {
67448: last_fault_for_exception_3 = dataa;
67449: last_op_for_exception_3 = opcode;
67450: last_addr_for_exception_3 = m68k_getpc() + 4;
67451: Exception(3, 0, M68000_EXC_SRC_CPU);
67452: goto endlabel3659;
67453: }
67454: {{ uae_s16 data = get_word(dataa);
67455: { uae_u32 val = (uae_u16)data;
67456: uae_u32 sign = 0x8000 & val;
67457: uae_u32 cflg = val & 1;
67458: val = (val >> 1) | sign;
67459: CLEAR_CZNV;
67460: SET_ZFLG (((uae_s16)(val)) == 0);
67461: SET_NFLG (((uae_s16)(val)) < 0);
67462: SET_CFLG (cflg);
67463: COPY_CARRY;
67464: m68k_incpc(4);
67465: fill_prefetch_0 ();
67466: put_word(dataa,val);
67467: }}}}}endlabel3659: ;
67468: return 18;
67469: }
67470: unsigned long REGPARAM2 CPUFUNC(op_e0f8_5)(uae_u32 opcode) /* ASRW */
67471: {
67472: OpcodeFamily = 72; CurrentInstrCycles = 16;
67473: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword_prefetch(2);
67474: if ((dataa & 1) != 0) {
67475: last_fault_for_exception_3 = dataa;
67476: last_op_for_exception_3 = opcode;
67477: last_addr_for_exception_3 = m68k_getpc() + 4;
67478: Exception(3, 0, M68000_EXC_SRC_CPU);
67479: goto endlabel3660;
67480: }
67481: {{ uae_s16 data = get_word(dataa);
67482: { uae_u32 val = (uae_u16)data;
67483: uae_u32 sign = 0x8000 & val;
67484: uae_u32 cflg = val & 1;
67485: val = (val >> 1) | sign;
67486: CLEAR_CZNV;
67487: SET_ZFLG (((uae_s16)(val)) == 0);
67488: SET_NFLG (((uae_s16)(val)) < 0);
67489: SET_CFLG (cflg);
67490: COPY_CARRY;
67491: m68k_incpc(4);
67492: fill_prefetch_0 ();
67493: put_word(dataa,val);
67494: }}}}}endlabel3660: ;
67495: return 16;
67496: }
67497: unsigned long REGPARAM2 CPUFUNC(op_e0f9_5)(uae_u32 opcode) /* ASRW */
67498: {
67499: OpcodeFamily = 72; CurrentInstrCycles = 20;
67500: {{ uaecptr dataa = get_ilong_prefetch(2);
67501: if ((dataa & 1) != 0) {
67502: last_fault_for_exception_3 = dataa;
67503: last_op_for_exception_3 = opcode;
67504: last_addr_for_exception_3 = m68k_getpc() + 6;
67505: Exception(3, 0, M68000_EXC_SRC_CPU);
67506: goto endlabel3661;
67507: }
67508: {{ uae_s16 data = get_word(dataa);
67509: { uae_u32 val = (uae_u16)data;
67510: uae_u32 sign = 0x8000 & val;
67511: uae_u32 cflg = val & 1;
67512: val = (val >> 1) | sign;
67513: CLEAR_CZNV;
67514: SET_ZFLG (((uae_s16)(val)) == 0);
67515: SET_NFLG (((uae_s16)(val)) < 0);
67516: SET_CFLG (cflg);
67517: COPY_CARRY;
67518: m68k_incpc(6);
67519: fill_prefetch_0 ();
67520: put_word(dataa,val);
67521: }}}}}endlabel3661: ;
67522: return 20;
67523: }
67524: unsigned long REGPARAM2 CPUFUNC(op_e100_5)(uae_u32 opcode) /* ASL */
67525: {
67526: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67527: uae_u32 dstreg = opcode & 7;
67528: unsigned int retcycles = 0;
67529: OpcodeFamily = 65; CurrentInstrCycles = 4;
67530: {{ uae_u32 cnt = srcreg;
67531: { uae_s8 data = m68k_dreg(regs, dstreg);
67532: { uae_u32 val = (uae_u8)data;
67533: cnt &= 63;
67534: retcycles = cnt;
67535: CLEAR_CZNV;
67536: if (cnt >= 8) {
67537: SET_VFLG (val != 0);
67538: SET_CFLG (cnt == 8 ? val & 1 : 0);
67539: COPY_CARRY;
67540: val = 0;
67541: } else {
67542: uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
67543: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
67544: val <<= cnt - 1;
67545: SET_CFLG ((val & 0x80) >> 7);
67546: COPY_CARRY;
67547: val <<= 1;
67548: val &= 0xff;
67549: }
67550: SET_ZFLG (((uae_s8)(val)) == 0);
67551: SET_NFLG (((uae_s8)(val)) < 0);
67552: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
67553: }}}}m68k_incpc(2);
67554: fill_prefetch_2 ();
67555: return (6+retcycles*2);
67556: }
67557: unsigned long REGPARAM2 CPUFUNC(op_e108_5)(uae_u32 opcode) /* LSL */
67558: {
67559: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67560: uae_u32 dstreg = opcode & 7;
67561: unsigned int retcycles = 0;
67562: OpcodeFamily = 67; CurrentInstrCycles = 4;
67563: {{ uae_u32 cnt = srcreg;
67564: { uae_s8 data = m68k_dreg(regs, dstreg);
67565: { uae_u32 val = (uae_u8)data;
67566: cnt &= 63;
67567: retcycles = cnt;
67568: CLEAR_CZNV;
67569: if (cnt >= 8) {
67570: SET_CFLG (cnt == 8 ? val & 1 : 0);
67571: COPY_CARRY;
67572: val = 0;
67573: } else {
67574: val <<= (cnt - 1);
67575: SET_CFLG ((val & 0x80) >> 7);
67576: COPY_CARRY;
67577: val <<= 1;
67578: val &= 0xff;
67579: }
67580: SET_ZFLG (((uae_s8)(val)) == 0);
67581: SET_NFLG (((uae_s8)(val)) < 0);
67582: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
67583: }}}}m68k_incpc(2);
67584: fill_prefetch_2 ();
67585: return (6+retcycles*2);
67586: }
67587: unsigned long REGPARAM2 CPUFUNC(op_e110_5)(uae_u32 opcode) /* ROXL */
67588: {
67589: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67590: uae_u32 dstreg = opcode & 7;
67591: unsigned int retcycles = 0;
67592: OpcodeFamily = 70; CurrentInstrCycles = 4;
67593: {{ uae_u32 cnt = srcreg;
67594: { uae_s8 data = m68k_dreg(regs, dstreg);
67595: { uae_u32 val = (uae_u8)data;
67596: cnt &= 63;
67597: retcycles = cnt;
67598: CLEAR_CZNV;
67599: { cnt--;
67600: {
67601: uae_u32 carry;
67602: uae_u32 loval = val >> (7 - cnt);
67603: carry = loval & 1;
67604: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
67605: SET_XFLG (carry);
67606: val &= 0xff;
67607: } }
67608: SET_CFLG (GET_XFLG);
67609: SET_ZFLG (((uae_s8)(val)) == 0);
67610: SET_NFLG (((uae_s8)(val)) < 0);
67611: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
67612: }}}}m68k_incpc(2);
67613: fill_prefetch_2 ();
67614: return (6+retcycles*2);
67615: }
67616: unsigned long REGPARAM2 CPUFUNC(op_e118_5)(uae_u32 opcode) /* ROL */
67617: {
67618: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67619: uae_u32 dstreg = opcode & 7;
67620: unsigned int retcycles = 0;
67621: OpcodeFamily = 68; CurrentInstrCycles = 4;
67622: {{ uae_u32 cnt = srcreg;
67623: { uae_s8 data = m68k_dreg(regs, dstreg);
67624: { uae_u32 val = (uae_u8)data;
67625: cnt &= 63;
67626: retcycles = cnt;
67627: CLEAR_CZNV;
67628: { uae_u32 loval;
67629: cnt &= 7;
67630: loval = val >> (8 - cnt);
67631: val <<= cnt;
67632: val |= loval;
67633: val &= 0xff;
67634: SET_CFLG (val & 1);
67635: }
67636: SET_ZFLG (((uae_s8)(val)) == 0);
67637: SET_NFLG (((uae_s8)(val)) < 0);
67638: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
67639: }}}}m68k_incpc(2);
67640: fill_prefetch_2 ();
67641: return (6+retcycles*2);
67642: }
67643: unsigned long REGPARAM2 CPUFUNC(op_e120_5)(uae_u32 opcode) /* ASL */
67644: {
67645: uae_u32 srcreg = ((opcode >> 9) & 7);
67646: uae_u32 dstreg = opcode & 7;
67647: unsigned int retcycles = 0;
67648: OpcodeFamily = 65; CurrentInstrCycles = 4;
67649: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
67650: { uae_s8 data = m68k_dreg(regs, dstreg);
67651: { uae_u32 val = (uae_u8)data;
67652: cnt &= 63;
67653: retcycles = cnt;
67654: CLEAR_CZNV;
67655: if (cnt >= 8) {
67656: SET_VFLG (val != 0);
67657: SET_CFLG (cnt == 8 ? val & 1 : 0);
67658: COPY_CARRY;
67659: val = 0;
67660: } else if (cnt > 0) {
67661: uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
67662: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
67663: val <<= cnt - 1;
67664: SET_CFLG ((val & 0x80) >> 7);
67665: COPY_CARRY;
67666: val <<= 1;
67667: val &= 0xff;
67668: }
67669: SET_ZFLG (((uae_s8)(val)) == 0);
67670: SET_NFLG (((uae_s8)(val)) < 0);
67671: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
67672: }}}}m68k_incpc(2);
67673: fill_prefetch_2 ();
67674: return (6+retcycles*2);
67675: }
67676: unsigned long REGPARAM2 CPUFUNC(op_e128_5)(uae_u32 opcode) /* LSL */
67677: {
67678: uae_u32 srcreg = ((opcode >> 9) & 7);
67679: uae_u32 dstreg = opcode & 7;
67680: unsigned int retcycles = 0;
67681: OpcodeFamily = 67; CurrentInstrCycles = 4;
67682: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
67683: { uae_s8 data = m68k_dreg(regs, dstreg);
67684: { uae_u32 val = (uae_u8)data;
67685: cnt &= 63;
67686: retcycles = cnt;
67687: CLEAR_CZNV;
67688: if (cnt >= 8) {
67689: SET_CFLG (cnt == 8 ? val & 1 : 0);
67690: COPY_CARRY;
67691: val = 0;
67692: } else if (cnt > 0) {
67693: val <<= (cnt - 1);
67694: SET_CFLG ((val & 0x80) >> 7);
67695: COPY_CARRY;
67696: val <<= 1;
67697: val &= 0xff;
67698: }
67699: SET_ZFLG (((uae_s8)(val)) == 0);
67700: SET_NFLG (((uae_s8)(val)) < 0);
67701: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
67702: }}}}m68k_incpc(2);
67703: fill_prefetch_2 ();
67704: return (6+retcycles*2);
67705: }
67706: unsigned long REGPARAM2 CPUFUNC(op_e130_5)(uae_u32 opcode) /* ROXL */
67707: {
67708: uae_u32 srcreg = ((opcode >> 9) & 7);
67709: uae_u32 dstreg = opcode & 7;
67710: unsigned int retcycles = 0;
67711: OpcodeFamily = 70; CurrentInstrCycles = 4;
67712: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
67713: { uae_s8 data = m68k_dreg(regs, dstreg);
67714: { uae_u32 val = (uae_u8)data;
67715: cnt &= 63;
67716: retcycles = cnt;
67717: CLEAR_CZNV;
67718: if (cnt >= 36) cnt -= 36;
67719: if (cnt >= 18) cnt -= 18;
67720: if (cnt >= 9) cnt -= 9;
67721: if (cnt > 0) {
67722: cnt--;
67723: {
67724: uae_u32 carry;
67725: uae_u32 loval = val >> (7 - cnt);
67726: carry = loval & 1;
67727: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
67728: SET_XFLG (carry);
67729: val &= 0xff;
67730: } }
67731: SET_CFLG (GET_XFLG);
67732: SET_ZFLG (((uae_s8)(val)) == 0);
67733: SET_NFLG (((uae_s8)(val)) < 0);
67734: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
67735: }}}}m68k_incpc(2);
67736: fill_prefetch_2 ();
67737: return (6+retcycles*2);
67738: }
67739: unsigned long REGPARAM2 CPUFUNC(op_e138_5)(uae_u32 opcode) /* ROL */
67740: {
67741: uae_u32 srcreg = ((opcode >> 9) & 7);
67742: uae_u32 dstreg = opcode & 7;
67743: unsigned int retcycles = 0;
67744: OpcodeFamily = 68; CurrentInstrCycles = 4;
67745: {{ uae_s8 cnt = m68k_dreg(regs, srcreg);
67746: { uae_s8 data = m68k_dreg(regs, dstreg);
67747: { uae_u32 val = (uae_u8)data;
67748: cnt &= 63;
67749: retcycles = cnt;
67750: CLEAR_CZNV;
67751: if (cnt > 0) {
67752: uae_u32 loval;
67753: cnt &= 7;
67754: loval = val >> (8 - cnt);
67755: val <<= cnt;
67756: val |= loval;
67757: val &= 0xff;
67758: SET_CFLG (val & 1);
67759: }
67760: SET_ZFLG (((uae_s8)(val)) == 0);
67761: SET_NFLG (((uae_s8)(val)) < 0);
67762: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
67763: }}}}m68k_incpc(2);
67764: fill_prefetch_2 ();
67765: return (6+retcycles*2);
67766: }
67767: unsigned long REGPARAM2 CPUFUNC(op_e140_5)(uae_u32 opcode) /* ASL */
67768: {
67769: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67770: uae_u32 dstreg = opcode & 7;
67771: unsigned int retcycles = 0;
67772: OpcodeFamily = 65; CurrentInstrCycles = 4;
67773: {{ uae_u32 cnt = srcreg;
67774: { uae_s16 data = m68k_dreg(regs, dstreg);
67775: { uae_u32 val = (uae_u16)data;
67776: cnt &= 63;
67777: retcycles = cnt;
67778: CLEAR_CZNV;
67779: if (cnt >= 16) {
67780: SET_VFLG (val != 0);
67781: SET_CFLG (cnt == 16 ? val & 1 : 0);
67782: COPY_CARRY;
67783: val = 0;
67784: } else {
67785: uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
67786: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
67787: val <<= cnt - 1;
67788: SET_CFLG ((val & 0x8000) >> 15);
67789: COPY_CARRY;
67790: val <<= 1;
67791: val &= 0xffff;
67792: }
67793: SET_ZFLG (((uae_s16)(val)) == 0);
67794: SET_NFLG (((uae_s16)(val)) < 0);
67795: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67796: }}}}m68k_incpc(2);
67797: fill_prefetch_2 ();
67798: return (6+retcycles*2);
67799: }
67800: unsigned long REGPARAM2 CPUFUNC(op_e148_5)(uae_u32 opcode) /* LSL */
67801: {
67802: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67803: uae_u32 dstreg = opcode & 7;
67804: unsigned int retcycles = 0;
67805: OpcodeFamily = 67; CurrentInstrCycles = 4;
67806: {{ uae_u32 cnt = srcreg;
67807: { uae_s16 data = m68k_dreg(regs, dstreg);
67808: { uae_u32 val = (uae_u16)data;
67809: cnt &= 63;
67810: retcycles = cnt;
67811: CLEAR_CZNV;
67812: if (cnt >= 16) {
67813: SET_CFLG (cnt == 16 ? val & 1 : 0);
67814: COPY_CARRY;
67815: val = 0;
67816: } else {
67817: val <<= (cnt - 1);
67818: SET_CFLG ((val & 0x8000) >> 15);
67819: COPY_CARRY;
67820: val <<= 1;
67821: val &= 0xffff;
67822: }
67823: SET_ZFLG (((uae_s16)(val)) == 0);
67824: SET_NFLG (((uae_s16)(val)) < 0);
67825: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67826: }}}}m68k_incpc(2);
67827: fill_prefetch_2 ();
67828: return (6+retcycles*2);
67829: }
67830: unsigned long REGPARAM2 CPUFUNC(op_e150_5)(uae_u32 opcode) /* ROXL */
67831: {
67832: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67833: uae_u32 dstreg = opcode & 7;
67834: unsigned int retcycles = 0;
67835: OpcodeFamily = 70; CurrentInstrCycles = 4;
67836: {{ uae_u32 cnt = srcreg;
67837: { uae_s16 data = m68k_dreg(regs, dstreg);
67838: { uae_u32 val = (uae_u16)data;
67839: cnt &= 63;
67840: retcycles = cnt;
67841: CLEAR_CZNV;
67842: { cnt--;
67843: {
67844: uae_u32 carry;
67845: uae_u32 loval = val >> (15 - cnt);
67846: carry = loval & 1;
67847: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
67848: SET_XFLG (carry);
67849: val &= 0xffff;
67850: } }
67851: SET_CFLG (GET_XFLG);
67852: SET_ZFLG (((uae_s16)(val)) == 0);
67853: SET_NFLG (((uae_s16)(val)) < 0);
67854: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67855: }}}}m68k_incpc(2);
67856: fill_prefetch_2 ();
67857: return (6+retcycles*2);
67858: }
67859: unsigned long REGPARAM2 CPUFUNC(op_e158_5)(uae_u32 opcode) /* ROL */
67860: {
67861: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
67862: uae_u32 dstreg = opcode & 7;
67863: unsigned int retcycles = 0;
67864: OpcodeFamily = 68; CurrentInstrCycles = 4;
67865: {{ uae_u32 cnt = srcreg;
67866: { uae_s16 data = m68k_dreg(regs, dstreg);
67867: { uae_u32 val = (uae_u16)data;
67868: cnt &= 63;
67869: retcycles = cnt;
67870: CLEAR_CZNV;
67871: { uae_u32 loval;
67872: cnt &= 15;
67873: loval = val >> (16 - cnt);
67874: val <<= cnt;
67875: val |= loval;
67876: val &= 0xffff;
67877: SET_CFLG (val & 1);
67878: }
67879: SET_ZFLG (((uae_s16)(val)) == 0);
67880: SET_NFLG (((uae_s16)(val)) < 0);
67881: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67882: }}}}m68k_incpc(2);
67883: fill_prefetch_2 ();
67884: return (6+retcycles*2);
67885: }
67886: unsigned long REGPARAM2 CPUFUNC(op_e160_5)(uae_u32 opcode) /* ASL */
67887: {
67888: uae_u32 srcreg = ((opcode >> 9) & 7);
67889: uae_u32 dstreg = opcode & 7;
67890: unsigned int retcycles = 0;
67891: OpcodeFamily = 65; CurrentInstrCycles = 4;
67892: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
67893: { uae_s16 data = m68k_dreg(regs, dstreg);
67894: { uae_u32 val = (uae_u16)data;
67895: cnt &= 63;
67896: retcycles = cnt;
67897: CLEAR_CZNV;
67898: if (cnt >= 16) {
67899: SET_VFLG (val != 0);
67900: SET_CFLG (cnt == 16 ? val & 1 : 0);
67901: COPY_CARRY;
67902: val = 0;
67903: } else if (cnt > 0) {
67904: uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
67905: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
67906: val <<= cnt - 1;
67907: SET_CFLG ((val & 0x8000) >> 15);
67908: COPY_CARRY;
67909: val <<= 1;
67910: val &= 0xffff;
67911: }
67912: SET_ZFLG (((uae_s16)(val)) == 0);
67913: SET_NFLG (((uae_s16)(val)) < 0);
67914: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67915: }}}}m68k_incpc(2);
67916: fill_prefetch_2 ();
67917: return (6+retcycles*2);
67918: }
67919: unsigned long REGPARAM2 CPUFUNC(op_e168_5)(uae_u32 opcode) /* LSL */
67920: {
67921: uae_u32 srcreg = ((opcode >> 9) & 7);
67922: uae_u32 dstreg = opcode & 7;
67923: unsigned int retcycles = 0;
67924: OpcodeFamily = 67; CurrentInstrCycles = 4;
67925: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
67926: { uae_s16 data = m68k_dreg(regs, dstreg);
67927: { uae_u32 val = (uae_u16)data;
67928: cnt &= 63;
67929: retcycles = cnt;
67930: CLEAR_CZNV;
67931: if (cnt >= 16) {
67932: SET_CFLG (cnt == 16 ? val & 1 : 0);
67933: COPY_CARRY;
67934: val = 0;
67935: } else if (cnt > 0) {
67936: val <<= (cnt - 1);
67937: SET_CFLG ((val & 0x8000) >> 15);
67938: COPY_CARRY;
67939: val <<= 1;
67940: val &= 0xffff;
67941: }
67942: SET_ZFLG (((uae_s16)(val)) == 0);
67943: SET_NFLG (((uae_s16)(val)) < 0);
67944: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67945: }}}}m68k_incpc(2);
67946: fill_prefetch_2 ();
67947: return (6+retcycles*2);
67948: }
67949: unsigned long REGPARAM2 CPUFUNC(op_e170_5)(uae_u32 opcode) /* ROXL */
67950: {
67951: uae_u32 srcreg = ((opcode >> 9) & 7);
67952: uae_u32 dstreg = opcode & 7;
67953: unsigned int retcycles = 0;
67954: OpcodeFamily = 70; CurrentInstrCycles = 4;
67955: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
67956: { uae_s16 data = m68k_dreg(regs, dstreg);
67957: { uae_u32 val = (uae_u16)data;
67958: cnt &= 63;
67959: retcycles = cnt;
67960: CLEAR_CZNV;
67961: if (cnt >= 34) cnt -= 34;
67962: if (cnt >= 17) cnt -= 17;
67963: if (cnt > 0) {
67964: cnt--;
67965: {
67966: uae_u32 carry;
67967: uae_u32 loval = val >> (15 - cnt);
67968: carry = loval & 1;
67969: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
67970: SET_XFLG (carry);
67971: val &= 0xffff;
67972: } }
67973: SET_CFLG (GET_XFLG);
67974: SET_ZFLG (((uae_s16)(val)) == 0);
67975: SET_NFLG (((uae_s16)(val)) < 0);
67976: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
67977: }}}}m68k_incpc(2);
67978: fill_prefetch_2 ();
67979: return (6+retcycles*2);
67980: }
67981: unsigned long REGPARAM2 CPUFUNC(op_e178_5)(uae_u32 opcode) /* ROL */
67982: {
67983: uae_u32 srcreg = ((opcode >> 9) & 7);
67984: uae_u32 dstreg = opcode & 7;
67985: unsigned int retcycles = 0;
67986: OpcodeFamily = 68; CurrentInstrCycles = 4;
67987: {{ uae_s16 cnt = m68k_dreg(regs, srcreg);
67988: { uae_s16 data = m68k_dreg(regs, dstreg);
67989: { uae_u32 val = (uae_u16)data;
67990: cnt &= 63;
67991: retcycles = cnt;
67992: CLEAR_CZNV;
67993: if (cnt > 0) {
67994: uae_u32 loval;
67995: cnt &= 15;
67996: loval = val >> (16 - cnt);
67997: val <<= cnt;
67998: val |= loval;
67999: val &= 0xffff;
68000: SET_CFLG (val & 1);
68001: }
68002: SET_ZFLG (((uae_s16)(val)) == 0);
68003: SET_NFLG (((uae_s16)(val)) < 0);
68004: m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
68005: }}}}m68k_incpc(2);
68006: fill_prefetch_2 ();
68007: return (6+retcycles*2);
68008: }
68009: unsigned long REGPARAM2 CPUFUNC(op_e180_5)(uae_u32 opcode) /* ASL */
68010: {
68011: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
68012: uae_u32 dstreg = opcode & 7;
68013: unsigned int retcycles = 0;
68014: OpcodeFamily = 65; CurrentInstrCycles = 4;
68015: {{ uae_u32 cnt = srcreg;
68016: { uae_s32 data = m68k_dreg(regs, dstreg);
68017: { uae_u32 val = data;
68018: cnt &= 63;
68019: retcycles = cnt;
68020: CLEAR_CZNV;
68021: if (cnt >= 32) {
68022: SET_VFLG (val != 0);
68023: SET_CFLG (cnt == 32 ? val & 1 : 0);
68024: COPY_CARRY;
68025: val = 0;
68026: } else {
68027: uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
68028: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
68029: val <<= cnt - 1;
68030: SET_CFLG ((val & 0x80000000) >> 31);
68031: COPY_CARRY;
68032: val <<= 1;
68033: val &= 0xffffffff;
68034: }
68035: SET_ZFLG (((uae_s32)(val)) == 0);
68036: SET_NFLG (((uae_s32)(val)) < 0);
68037: m68k_dreg(regs, dstreg) = (val);
68038: }}}}m68k_incpc(2);
68039: fill_prefetch_2 ();
68040: return (8+retcycles*2);
68041: }
68042: unsigned long REGPARAM2 CPUFUNC(op_e188_5)(uae_u32 opcode) /* LSL */
68043: {
68044: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
68045: uae_u32 dstreg = opcode & 7;
68046: unsigned int retcycles = 0;
68047: OpcodeFamily = 67; CurrentInstrCycles = 4;
68048: {{ uae_u32 cnt = srcreg;
68049: { uae_s32 data = m68k_dreg(regs, dstreg);
68050: { uae_u32 val = data;
68051: cnt &= 63;
68052: retcycles = cnt;
68053: CLEAR_CZNV;
68054: if (cnt >= 32) {
68055: SET_CFLG (cnt == 32 ? val & 1 : 0);
68056: COPY_CARRY;
68057: val = 0;
68058: } else {
68059: val <<= (cnt - 1);
68060: SET_CFLG ((val & 0x80000000) >> 31);
68061: COPY_CARRY;
68062: val <<= 1;
68063: val &= 0xffffffff;
68064: }
68065: SET_ZFLG (((uae_s32)(val)) == 0);
68066: SET_NFLG (((uae_s32)(val)) < 0);
68067: m68k_dreg(regs, dstreg) = (val);
68068: }}}}m68k_incpc(2);
68069: fill_prefetch_2 ();
68070: return (8+retcycles*2);
68071: }
68072: unsigned long REGPARAM2 CPUFUNC(op_e190_5)(uae_u32 opcode) /* ROXL */
68073: {
68074: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
68075: uae_u32 dstreg = opcode & 7;
68076: unsigned int retcycles = 0;
68077: OpcodeFamily = 70; CurrentInstrCycles = 4;
68078: {{ uae_u32 cnt = srcreg;
68079: { uae_s32 data = m68k_dreg(regs, dstreg);
68080: { uae_u32 val = data;
68081: cnt &= 63;
68082: retcycles = cnt;
68083: CLEAR_CZNV;
68084: { cnt--;
68085: {
68086: uae_u32 carry;
68087: uae_u32 loval = val >> (31 - cnt);
68088: carry = loval & 1;
68089: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
68090: SET_XFLG (carry);
68091: val &= 0xffffffff;
68092: } }
68093: SET_CFLG (GET_XFLG);
68094: SET_ZFLG (((uae_s32)(val)) == 0);
68095: SET_NFLG (((uae_s32)(val)) < 0);
68096: m68k_dreg(regs, dstreg) = (val);
68097: }}}}m68k_incpc(2);
68098: fill_prefetch_2 ();
68099: return (8+retcycles*2);
68100: }
68101: unsigned long REGPARAM2 CPUFUNC(op_e198_5)(uae_u32 opcode) /* ROL */
68102: {
68103: uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
68104: uae_u32 dstreg = opcode & 7;
68105: unsigned int retcycles = 0;
68106: OpcodeFamily = 68; CurrentInstrCycles = 4;
68107: {{ uae_u32 cnt = srcreg;
68108: { uae_s32 data = m68k_dreg(regs, dstreg);
68109: { uae_u32 val = data;
68110: cnt &= 63;
68111: retcycles = cnt;
68112: CLEAR_CZNV;
68113: { uae_u32 loval;
68114: cnt &= 31;
68115: loval = val >> (32 - cnt);
68116: val <<= cnt;
68117: val |= loval;
68118: val &= 0xffffffff;
68119: SET_CFLG (val & 1);
68120: }
68121: SET_ZFLG (((uae_s32)(val)) == 0);
68122: SET_NFLG (((uae_s32)(val)) < 0);
68123: m68k_dreg(regs, dstreg) = (val);
68124: }}}}m68k_incpc(2);
68125: fill_prefetch_2 ();
68126: return (8+retcycles*2);
68127: }
68128: unsigned long REGPARAM2 CPUFUNC(op_e1a0_5)(uae_u32 opcode) /* ASL */
68129: {
68130: uae_u32 srcreg = ((opcode >> 9) & 7);
68131: uae_u32 dstreg = opcode & 7;
68132: unsigned int retcycles = 0;
68133: OpcodeFamily = 65; CurrentInstrCycles = 4;
68134: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
68135: { uae_s32 data = m68k_dreg(regs, dstreg);
68136: { uae_u32 val = data;
68137: cnt &= 63;
68138: retcycles = cnt;
68139: CLEAR_CZNV;
68140: if (cnt >= 32) {
68141: SET_VFLG (val != 0);
68142: SET_CFLG (cnt == 32 ? val & 1 : 0);
68143: COPY_CARRY;
68144: val = 0;
68145: } else if (cnt > 0) {
68146: uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
68147: SET_VFLG ((val & mask) != mask && (val & mask) != 0);
68148: val <<= cnt - 1;
68149: SET_CFLG ((val & 0x80000000) >> 31);
68150: COPY_CARRY;
68151: val <<= 1;
68152: val &= 0xffffffff;
68153: }
68154: SET_ZFLG (((uae_s32)(val)) == 0);
68155: SET_NFLG (((uae_s32)(val)) < 0);
68156: m68k_dreg(regs, dstreg) = (val);
68157: }}}}m68k_incpc(2);
68158: fill_prefetch_2 ();
68159: return (8+retcycles*2);
68160: }
68161: unsigned long REGPARAM2 CPUFUNC(op_e1a8_5)(uae_u32 opcode) /* LSL */
68162: {
68163: uae_u32 srcreg = ((opcode >> 9) & 7);
68164: uae_u32 dstreg = opcode & 7;
68165: unsigned int retcycles = 0;
68166: OpcodeFamily = 67; CurrentInstrCycles = 4;
68167: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
68168: { uae_s32 data = m68k_dreg(regs, dstreg);
68169: { uae_u32 val = data;
68170: cnt &= 63;
68171: retcycles = cnt;
68172: CLEAR_CZNV;
68173: if (cnt >= 32) {
68174: SET_CFLG (cnt == 32 ? val & 1 : 0);
68175: COPY_CARRY;
68176: val = 0;
68177: } else if (cnt > 0) {
68178: val <<= (cnt - 1);
68179: SET_CFLG ((val & 0x80000000) >> 31);
68180: COPY_CARRY;
68181: val <<= 1;
68182: val &= 0xffffffff;
68183: }
68184: SET_ZFLG (((uae_s32)(val)) == 0);
68185: SET_NFLG (((uae_s32)(val)) < 0);
68186: m68k_dreg(regs, dstreg) = (val);
68187: }}}}m68k_incpc(2);
68188: fill_prefetch_2 ();
68189: return (8+retcycles*2);
68190: }
68191: unsigned long REGPARAM2 CPUFUNC(op_e1b0_5)(uae_u32 opcode) /* ROXL */
68192: {
68193: uae_u32 srcreg = ((opcode >> 9) & 7);
68194: uae_u32 dstreg = opcode & 7;
68195: unsigned int retcycles = 0;
68196: OpcodeFamily = 70; CurrentInstrCycles = 4;
68197: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
68198: { uae_s32 data = m68k_dreg(regs, dstreg);
68199: { uae_u32 val = data;
68200: cnt &= 63;
68201: retcycles = cnt;
68202: CLEAR_CZNV;
68203: if (cnt >= 33) cnt -= 33;
68204: if (cnt > 0) {
68205: cnt--;
68206: {
68207: uae_u32 carry;
68208: uae_u32 loval = val >> (31 - cnt);
68209: carry = loval & 1;
68210: val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
68211: SET_XFLG (carry);
68212: val &= 0xffffffff;
68213: } }
68214: SET_CFLG (GET_XFLG);
68215: SET_ZFLG (((uae_s32)(val)) == 0);
68216: SET_NFLG (((uae_s32)(val)) < 0);
68217: m68k_dreg(regs, dstreg) = (val);
68218: }}}}m68k_incpc(2);
68219: fill_prefetch_2 ();
68220: return (8+retcycles*2);
68221: }
68222: unsigned long REGPARAM2 CPUFUNC(op_e1b8_5)(uae_u32 opcode) /* ROL */
68223: {
68224: uae_u32 srcreg = ((opcode >> 9) & 7);
68225: uae_u32 dstreg = opcode & 7;
68226: unsigned int retcycles = 0;
68227: OpcodeFamily = 68; CurrentInstrCycles = 4;
68228: {{ uae_s32 cnt = m68k_dreg(regs, srcreg);
68229: { uae_s32 data = m68k_dreg(regs, dstreg);
68230: { uae_u32 val = data;
68231: cnt &= 63;
68232: retcycles = cnt;
68233: CLEAR_CZNV;
68234: if (cnt > 0) {
68235: uae_u32 loval;
68236: cnt &= 31;
68237: loval = val >> (32 - cnt);
68238: val <<= cnt;
68239: val |= loval;
68240: val &= 0xffffffff;
68241: SET_CFLG (val & 1);
68242: }
68243: SET_ZFLG (((uae_s32)(val)) == 0);
68244: SET_NFLG (((uae_s32)(val)) < 0);
68245: m68k_dreg(regs, dstreg) = (val);
68246: }}}}m68k_incpc(2);
68247: fill_prefetch_2 ();
68248: return (8+retcycles*2);
68249: }
68250: unsigned long REGPARAM2 CPUFUNC(op_e1d0_5)(uae_u32 opcode) /* ASLW */
68251: {
68252: uae_u32 srcreg = (opcode & 7);
68253: OpcodeFamily = 73; CurrentInstrCycles = 12;
68254: {{ uaecptr dataa = m68k_areg(regs, srcreg);
68255: if ((dataa & 1) != 0) {
68256: last_fault_for_exception_3 = dataa;
68257: last_op_for_exception_3 = opcode;
68258: last_addr_for_exception_3 = m68k_getpc() + 2;
68259: Exception(3, 0, M68000_EXC_SRC_CPU);
68260: goto endlabel3686;
68261: }
68262: {{ uae_s16 data = get_word(dataa);
68263: { uae_u32 val = (uae_u16)data;
68264: uae_u32 sign = 0x8000 & val;
68265: uae_u32 sign2;
68266: val <<= 1;
68267: CLEAR_CZNV;
68268: SET_ZFLG (((uae_s16)(val)) == 0);
68269: SET_NFLG (((uae_s16)(val)) < 0);
68270: sign2 = 0x8000 & val;
68271: SET_CFLG (sign != 0);
68272: COPY_CARRY;
68273: SET_VFLG (GET_VFLG | (sign2 != sign));
68274: m68k_incpc(2);
68275: fill_prefetch_2 ();
68276: put_word(dataa,val);
68277: }}}}}endlabel3686: ;
68278: return 12;
68279: }
68280: unsigned long REGPARAM2 CPUFUNC(op_e1d8_5)(uae_u32 opcode) /* ASLW */
68281: {
68282: uae_u32 srcreg = (opcode & 7);
68283: OpcodeFamily = 73; CurrentInstrCycles = 12;
68284: {{ uaecptr dataa = m68k_areg(regs, srcreg);
68285: if ((dataa & 1) != 0) {
68286: last_fault_for_exception_3 = dataa;
68287: last_op_for_exception_3 = opcode;
68288: last_addr_for_exception_3 = m68k_getpc() + 2;
68289: Exception(3, 0, M68000_EXC_SRC_CPU);
68290: goto endlabel3687;
68291: }
68292: {{ uae_s16 data = get_word(dataa);
68293: m68k_areg(regs, srcreg) += 2;
68294: { uae_u32 val = (uae_u16)data;
68295: uae_u32 sign = 0x8000 & val;
68296: uae_u32 sign2;
68297: val <<= 1;
68298: CLEAR_CZNV;
68299: SET_ZFLG (((uae_s16)(val)) == 0);
68300: SET_NFLG (((uae_s16)(val)) < 0);
68301: sign2 = 0x8000 & val;
68302: SET_CFLG (sign != 0);
68303: COPY_CARRY;
68304: SET_VFLG (GET_VFLG | (sign2 != sign));
68305: m68k_incpc(2);
68306: fill_prefetch_2 ();
68307: put_word(dataa,val);
68308: }}}}}endlabel3687: ;
68309: return 12;
68310: }
68311: unsigned long REGPARAM2 CPUFUNC(op_e1e0_5)(uae_u32 opcode) /* ASLW */
68312: {
68313: uae_u32 srcreg = (opcode & 7);
68314: OpcodeFamily = 73; CurrentInstrCycles = 14;
68315: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
68316: if ((dataa & 1) != 0) {
68317: last_fault_for_exception_3 = dataa;
68318: last_op_for_exception_3 = opcode;
68319: last_addr_for_exception_3 = m68k_getpc() + 2;
68320: Exception(3, 0, M68000_EXC_SRC_CPU);
68321: goto endlabel3688;
68322: }
68323: {{ uae_s16 data = get_word(dataa);
68324: m68k_areg (regs, srcreg) = dataa;
68325: { uae_u32 val = (uae_u16)data;
68326: uae_u32 sign = 0x8000 & val;
68327: uae_u32 sign2;
68328: val <<= 1;
68329: CLEAR_CZNV;
68330: SET_ZFLG (((uae_s16)(val)) == 0);
68331: SET_NFLG (((uae_s16)(val)) < 0);
68332: sign2 = 0x8000 & val;
68333: SET_CFLG (sign != 0);
68334: COPY_CARRY;
68335: SET_VFLG (GET_VFLG | (sign2 != sign));
68336: m68k_incpc(2);
68337: fill_prefetch_2 ();
68338: put_word(dataa,val);
68339: }}}}}endlabel3688: ;
68340: return 14;
68341: }
68342: unsigned long REGPARAM2 CPUFUNC(op_e1e8_5)(uae_u32 opcode) /* ASLW */
68343: {
68344: uae_u32 srcreg = (opcode & 7);
68345: OpcodeFamily = 73; CurrentInstrCycles = 16;
68346: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
68347: if ((dataa & 1) != 0) {
68348: last_fault_for_exception_3 = dataa;
68349: last_op_for_exception_3 = opcode;
68350: last_addr_for_exception_3 = m68k_getpc() + 4;
68351: Exception(3, 0, M68000_EXC_SRC_CPU);
68352: goto endlabel3689;
68353: }
68354: {{ uae_s16 data = get_word(dataa);
68355: { uae_u32 val = (uae_u16)data;
68356: uae_u32 sign = 0x8000 & val;
68357: uae_u32 sign2;
68358: val <<= 1;
68359: CLEAR_CZNV;
68360: SET_ZFLG (((uae_s16)(val)) == 0);
68361: SET_NFLG (((uae_s16)(val)) < 0);
68362: sign2 = 0x8000 & val;
68363: SET_CFLG (sign != 0);
68364: COPY_CARRY;
68365: SET_VFLG (GET_VFLG | (sign2 != sign));
68366: m68k_incpc(4);
68367: fill_prefetch_0 ();
68368: put_word(dataa,val);
68369: }}}}}endlabel3689: ;
68370: return 16;
68371: }
68372: unsigned long REGPARAM2 CPUFUNC(op_e1f0_5)(uae_u32 opcode) /* ASLW */
68373: {
68374: uae_u32 srcreg = (opcode & 7);
68375: OpcodeFamily = 73; CurrentInstrCycles = 18;
68376: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
68377: BusCyclePenalty += 2;
68378: if ((dataa & 1) != 0) {
68379: last_fault_for_exception_3 = dataa;
68380: last_op_for_exception_3 = opcode;
68381: last_addr_for_exception_3 = m68k_getpc() + 4;
68382: Exception(3, 0, M68000_EXC_SRC_CPU);
68383: goto endlabel3690;
68384: }
68385: {{ uae_s16 data = get_word(dataa);
68386: { uae_u32 val = (uae_u16)data;
68387: uae_u32 sign = 0x8000 & val;
68388: uae_u32 sign2;
68389: val <<= 1;
68390: CLEAR_CZNV;
68391: SET_ZFLG (((uae_s16)(val)) == 0);
68392: SET_NFLG (((uae_s16)(val)) < 0);
68393: sign2 = 0x8000 & val;
68394: SET_CFLG (sign != 0);
68395: COPY_CARRY;
68396: SET_VFLG (GET_VFLG | (sign2 != sign));
68397: m68k_incpc(4);
68398: fill_prefetch_0 ();
68399: put_word(dataa,val);
68400: }}}}}endlabel3690: ;
68401: return 18;
68402: }
68403: unsigned long REGPARAM2 CPUFUNC(op_e1f8_5)(uae_u32 opcode) /* ASLW */
68404: {
68405: OpcodeFamily = 73; CurrentInstrCycles = 16;
68406: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword_prefetch(2);
68407: if ((dataa & 1) != 0) {
68408: last_fault_for_exception_3 = dataa;
68409: last_op_for_exception_3 = opcode;
68410: last_addr_for_exception_3 = m68k_getpc() + 4;
68411: Exception(3, 0, M68000_EXC_SRC_CPU);
68412: goto endlabel3691;
68413: }
68414: {{ uae_s16 data = get_word(dataa);
68415: { uae_u32 val = (uae_u16)data;
68416: uae_u32 sign = 0x8000 & val;
68417: uae_u32 sign2;
68418: val <<= 1;
68419: CLEAR_CZNV;
68420: SET_ZFLG (((uae_s16)(val)) == 0);
68421: SET_NFLG (((uae_s16)(val)) < 0);
68422: sign2 = 0x8000 & val;
68423: SET_CFLG (sign != 0);
68424: COPY_CARRY;
68425: SET_VFLG (GET_VFLG | (sign2 != sign));
68426: m68k_incpc(4);
68427: fill_prefetch_0 ();
68428: put_word(dataa,val);
68429: }}}}}endlabel3691: ;
68430: return 16;
68431: }
68432: unsigned long REGPARAM2 CPUFUNC(op_e1f9_5)(uae_u32 opcode) /* ASLW */
68433: {
68434: OpcodeFamily = 73; CurrentInstrCycles = 20;
68435: {{ uaecptr dataa = get_ilong_prefetch(2);
68436: if ((dataa & 1) != 0) {
68437: last_fault_for_exception_3 = dataa;
68438: last_op_for_exception_3 = opcode;
68439: last_addr_for_exception_3 = m68k_getpc() + 6;
68440: Exception(3, 0, M68000_EXC_SRC_CPU);
68441: goto endlabel3692;
68442: }
68443: {{ uae_s16 data = get_word(dataa);
68444: { uae_u32 val = (uae_u16)data;
68445: uae_u32 sign = 0x8000 & val;
68446: uae_u32 sign2;
68447: val <<= 1;
68448: CLEAR_CZNV;
68449: SET_ZFLG (((uae_s16)(val)) == 0);
68450: SET_NFLG (((uae_s16)(val)) < 0);
68451: sign2 = 0x8000 & val;
68452: SET_CFLG (sign != 0);
68453: COPY_CARRY;
68454: SET_VFLG (GET_VFLG | (sign2 != sign));
68455: m68k_incpc(6);
68456: fill_prefetch_0 ();
68457: put_word(dataa,val);
68458: }}}}}endlabel3692: ;
68459: return 20;
68460: }
68461: unsigned long REGPARAM2 CPUFUNC(op_e2d0_5)(uae_u32 opcode) /* LSRW */
68462: {
68463: uae_u32 srcreg = (opcode & 7);
68464: OpcodeFamily = 74; CurrentInstrCycles = 12;
68465: {{ uaecptr dataa = m68k_areg(regs, srcreg);
68466: if ((dataa & 1) != 0) {
68467: last_fault_for_exception_3 = dataa;
68468: last_op_for_exception_3 = opcode;
68469: last_addr_for_exception_3 = m68k_getpc() + 2;
68470: Exception(3, 0, M68000_EXC_SRC_CPU);
68471: goto endlabel3693;
68472: }
68473: {{ uae_s16 data = get_word(dataa);
68474: { uae_u32 val = (uae_u16)data;
68475: uae_u32 carry = val & 1;
68476: val >>= 1;
68477: CLEAR_CZNV;
68478: SET_ZFLG (((uae_s16)(val)) == 0);
68479: SET_NFLG (((uae_s16)(val)) < 0);
68480: SET_CFLG (carry);
68481: COPY_CARRY;
68482: m68k_incpc(2);
68483: fill_prefetch_2 ();
68484: put_word(dataa,val);
68485: }}}}}endlabel3693: ;
68486: return 12;
68487: }
68488: unsigned long REGPARAM2 CPUFUNC(op_e2d8_5)(uae_u32 opcode) /* LSRW */
68489: {
68490: uae_u32 srcreg = (opcode & 7);
68491: OpcodeFamily = 74; CurrentInstrCycles = 12;
68492: {{ uaecptr dataa = m68k_areg(regs, srcreg);
68493: if ((dataa & 1) != 0) {
68494: last_fault_for_exception_3 = dataa;
68495: last_op_for_exception_3 = opcode;
68496: last_addr_for_exception_3 = m68k_getpc() + 2;
68497: Exception(3, 0, M68000_EXC_SRC_CPU);
68498: goto endlabel3694;
68499: }
68500: {{ uae_s16 data = get_word(dataa);
68501: m68k_areg(regs, srcreg) += 2;
68502: { uae_u32 val = (uae_u16)data;
68503: uae_u32 carry = val & 1;
68504: val >>= 1;
68505: CLEAR_CZNV;
68506: SET_ZFLG (((uae_s16)(val)) == 0);
68507: SET_NFLG (((uae_s16)(val)) < 0);
68508: SET_CFLG (carry);
68509: COPY_CARRY;
68510: m68k_incpc(2);
68511: fill_prefetch_2 ();
68512: put_word(dataa,val);
68513: }}}}}endlabel3694: ;
68514: return 12;
68515: }
68516: unsigned long REGPARAM2 CPUFUNC(op_e2e0_5)(uae_u32 opcode) /* LSRW */
68517: {
68518: uae_u32 srcreg = (opcode & 7);
68519: OpcodeFamily = 74; CurrentInstrCycles = 14;
68520: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
68521: if ((dataa & 1) != 0) {
68522: last_fault_for_exception_3 = dataa;
68523: last_op_for_exception_3 = opcode;
68524: last_addr_for_exception_3 = m68k_getpc() + 2;
68525: Exception(3, 0, M68000_EXC_SRC_CPU);
68526: goto endlabel3695;
68527: }
68528: {{ uae_s16 data = get_word(dataa);
68529: m68k_areg (regs, srcreg) = dataa;
68530: { uae_u32 val = (uae_u16)data;
68531: uae_u32 carry = val & 1;
68532: val >>= 1;
68533: CLEAR_CZNV;
68534: SET_ZFLG (((uae_s16)(val)) == 0);
68535: SET_NFLG (((uae_s16)(val)) < 0);
68536: SET_CFLG (carry);
68537: COPY_CARRY;
68538: m68k_incpc(2);
68539: fill_prefetch_2 ();
68540: put_word(dataa,val);
68541: }}}}}endlabel3695: ;
68542: return 14;
68543: }
68544: unsigned long REGPARAM2 CPUFUNC(op_e2e8_5)(uae_u32 opcode) /* LSRW */
68545: {
68546: uae_u32 srcreg = (opcode & 7);
68547: OpcodeFamily = 74; CurrentInstrCycles = 16;
68548: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
68549: if ((dataa & 1) != 0) {
68550: last_fault_for_exception_3 = dataa;
68551: last_op_for_exception_3 = opcode;
68552: last_addr_for_exception_3 = m68k_getpc() + 4;
68553: Exception(3, 0, M68000_EXC_SRC_CPU);
68554: goto endlabel3696;
68555: }
68556: {{ uae_s16 data = get_word(dataa);
68557: { uae_u32 val = (uae_u16)data;
68558: uae_u32 carry = val & 1;
68559: val >>= 1;
68560: CLEAR_CZNV;
68561: SET_ZFLG (((uae_s16)(val)) == 0);
68562: SET_NFLG (((uae_s16)(val)) < 0);
68563: SET_CFLG (carry);
68564: COPY_CARRY;
68565: m68k_incpc(4);
68566: fill_prefetch_0 ();
68567: put_word(dataa,val);
68568: }}}}}endlabel3696: ;
68569: return 16;
68570: }
68571: unsigned long REGPARAM2 CPUFUNC(op_e2f0_5)(uae_u32 opcode) /* LSRW */
68572: {
68573: uae_u32 srcreg = (opcode & 7);
68574: OpcodeFamily = 74; CurrentInstrCycles = 18;
68575: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
68576: BusCyclePenalty += 2;
68577: if ((dataa & 1) != 0) {
68578: last_fault_for_exception_3 = dataa;
68579: last_op_for_exception_3 = opcode;
68580: last_addr_for_exception_3 = m68k_getpc() + 4;
68581: Exception(3, 0, M68000_EXC_SRC_CPU);
68582: goto endlabel3697;
68583: }
68584: {{ uae_s16 data = get_word(dataa);
68585: { uae_u32 val = (uae_u16)data;
68586: uae_u32 carry = val & 1;
68587: val >>= 1;
68588: CLEAR_CZNV;
68589: SET_ZFLG (((uae_s16)(val)) == 0);
68590: SET_NFLG (((uae_s16)(val)) < 0);
68591: SET_CFLG (carry);
68592: COPY_CARRY;
68593: m68k_incpc(4);
68594: fill_prefetch_0 ();
68595: put_word(dataa,val);
68596: }}}}}endlabel3697: ;
68597: return 18;
68598: }
68599: unsigned long REGPARAM2 CPUFUNC(op_e2f8_5)(uae_u32 opcode) /* LSRW */
68600: {
68601: OpcodeFamily = 74; CurrentInstrCycles = 16;
68602: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword_prefetch(2);
68603: if ((dataa & 1) != 0) {
68604: last_fault_for_exception_3 = dataa;
68605: last_op_for_exception_3 = opcode;
68606: last_addr_for_exception_3 = m68k_getpc() + 4;
68607: Exception(3, 0, M68000_EXC_SRC_CPU);
68608: goto endlabel3698;
68609: }
68610: {{ uae_s16 data = get_word(dataa);
68611: { uae_u32 val = (uae_u16)data;
68612: uae_u32 carry = val & 1;
68613: val >>= 1;
68614: CLEAR_CZNV;
68615: SET_ZFLG (((uae_s16)(val)) == 0);
68616: SET_NFLG (((uae_s16)(val)) < 0);
68617: SET_CFLG (carry);
68618: COPY_CARRY;
68619: m68k_incpc(4);
68620: fill_prefetch_0 ();
68621: put_word(dataa,val);
68622: }}}}}endlabel3698: ;
68623: return 16;
68624: }
68625: unsigned long REGPARAM2 CPUFUNC(op_e2f9_5)(uae_u32 opcode) /* LSRW */
68626: {
68627: OpcodeFamily = 74; CurrentInstrCycles = 20;
68628: {{ uaecptr dataa = get_ilong_prefetch(2);
68629: if ((dataa & 1) != 0) {
68630: last_fault_for_exception_3 = dataa;
68631: last_op_for_exception_3 = opcode;
68632: last_addr_for_exception_3 = m68k_getpc() + 6;
68633: Exception(3, 0, M68000_EXC_SRC_CPU);
68634: goto endlabel3699;
68635: }
68636: {{ uae_s16 data = get_word(dataa);
68637: { uae_u32 val = (uae_u16)data;
68638: uae_u32 carry = val & 1;
68639: val >>= 1;
68640: CLEAR_CZNV;
68641: SET_ZFLG (((uae_s16)(val)) == 0);
68642: SET_NFLG (((uae_s16)(val)) < 0);
68643: SET_CFLG (carry);
68644: COPY_CARRY;
68645: m68k_incpc(6);
68646: fill_prefetch_0 ();
68647: put_word(dataa,val);
68648: }}}}}endlabel3699: ;
68649: return 20;
68650: }
68651: unsigned long REGPARAM2 CPUFUNC(op_e3d0_5)(uae_u32 opcode) /* LSLW */
68652: {
68653: uae_u32 srcreg = (opcode & 7);
68654: OpcodeFamily = 75; CurrentInstrCycles = 12;
68655: {{ uaecptr dataa = m68k_areg(regs, srcreg);
68656: if ((dataa & 1) != 0) {
68657: last_fault_for_exception_3 = dataa;
68658: last_op_for_exception_3 = opcode;
68659: last_addr_for_exception_3 = m68k_getpc() + 2;
68660: Exception(3, 0, M68000_EXC_SRC_CPU);
68661: goto endlabel3700;
68662: }
68663: {{ uae_s16 data = get_word(dataa);
68664: { uae_u16 val = data;
68665: uae_u32 carry = val & 0x8000;
68666: val <<= 1;
68667: CLEAR_CZNV;
68668: SET_ZFLG (((uae_s16)(val)) == 0);
68669: SET_NFLG (((uae_s16)(val)) < 0);
68670: SET_CFLG (carry >> 15);
68671: COPY_CARRY;
68672: m68k_incpc(2);
68673: fill_prefetch_2 ();
68674: put_word(dataa,val);
68675: }}}}}endlabel3700: ;
68676: return 12;
68677: }
68678: unsigned long REGPARAM2 CPUFUNC(op_e3d8_5)(uae_u32 opcode) /* LSLW */
68679: {
68680: uae_u32 srcreg = (opcode & 7);
68681: OpcodeFamily = 75; CurrentInstrCycles = 12;
68682: {{ uaecptr dataa = m68k_areg(regs, srcreg);
68683: if ((dataa & 1) != 0) {
68684: last_fault_for_exception_3 = dataa;
68685: last_op_for_exception_3 = opcode;
68686: last_addr_for_exception_3 = m68k_getpc() + 2;
68687: Exception(3, 0, M68000_EXC_SRC_CPU);
68688: goto endlabel3701;
68689: }
68690: {{ uae_s16 data = get_word(dataa);
68691: m68k_areg(regs, srcreg) += 2;
68692: { uae_u16 val = data;
68693: uae_u32 carry = val & 0x8000;
68694: val <<= 1;
68695: CLEAR_CZNV;
68696: SET_ZFLG (((uae_s16)(val)) == 0);
68697: SET_NFLG (((uae_s16)(val)) < 0);
68698: SET_CFLG (carry >> 15);
68699: COPY_CARRY;
68700: m68k_incpc(2);
68701: fill_prefetch_2 ();
68702: put_word(dataa,val);
68703: }}}}}endlabel3701: ;
68704: return 12;
68705: }
68706: unsigned long REGPARAM2 CPUFUNC(op_e3e0_5)(uae_u32 opcode) /* LSLW */
68707: {
68708: uae_u32 srcreg = (opcode & 7);
68709: OpcodeFamily = 75; CurrentInstrCycles = 14;
68710: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
68711: if ((dataa & 1) != 0) {
68712: last_fault_for_exception_3 = dataa;
68713: last_op_for_exception_3 = opcode;
68714: last_addr_for_exception_3 = m68k_getpc() + 2;
68715: Exception(3, 0, M68000_EXC_SRC_CPU);
68716: goto endlabel3702;
68717: }
68718: {{ uae_s16 data = get_word(dataa);
68719: m68k_areg (regs, srcreg) = dataa;
68720: { uae_u16 val = data;
68721: uae_u32 carry = val & 0x8000;
68722: val <<= 1;
68723: CLEAR_CZNV;
68724: SET_ZFLG (((uae_s16)(val)) == 0);
68725: SET_NFLG (((uae_s16)(val)) < 0);
68726: SET_CFLG (carry >> 15);
68727: COPY_CARRY;
68728: m68k_incpc(2);
68729: fill_prefetch_2 ();
68730: put_word(dataa,val);
68731: }}}}}endlabel3702: ;
68732: return 14;
68733: }
68734: unsigned long REGPARAM2 CPUFUNC(op_e3e8_5)(uae_u32 opcode) /* LSLW */
68735: {
68736: uae_u32 srcreg = (opcode & 7);
68737: OpcodeFamily = 75; CurrentInstrCycles = 16;
68738: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
68739: if ((dataa & 1) != 0) {
68740: last_fault_for_exception_3 = dataa;
68741: last_op_for_exception_3 = opcode;
68742: last_addr_for_exception_3 = m68k_getpc() + 4;
68743: Exception(3, 0, M68000_EXC_SRC_CPU);
68744: goto endlabel3703;
68745: }
68746: {{ uae_s16 data = get_word(dataa);
68747: { uae_u16 val = data;
68748: uae_u32 carry = val & 0x8000;
68749: val <<= 1;
68750: CLEAR_CZNV;
68751: SET_ZFLG (((uae_s16)(val)) == 0);
68752: SET_NFLG (((uae_s16)(val)) < 0);
68753: SET_CFLG (carry >> 15);
68754: COPY_CARRY;
68755: m68k_incpc(4);
68756: fill_prefetch_0 ();
68757: put_word(dataa,val);
68758: }}}}}endlabel3703: ;
68759: return 16;
68760: }
68761: unsigned long REGPARAM2 CPUFUNC(op_e3f0_5)(uae_u32 opcode) /* LSLW */
68762: {
68763: uae_u32 srcreg = (opcode & 7);
68764: OpcodeFamily = 75; CurrentInstrCycles = 18;
68765: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
68766: BusCyclePenalty += 2;
68767: if ((dataa & 1) != 0) {
68768: last_fault_for_exception_3 = dataa;
68769: last_op_for_exception_3 = opcode;
68770: last_addr_for_exception_3 = m68k_getpc() + 4;
68771: Exception(3, 0, M68000_EXC_SRC_CPU);
68772: goto endlabel3704;
68773: }
68774: {{ uae_s16 data = get_word(dataa);
68775: { uae_u16 val = data;
68776: uae_u32 carry = val & 0x8000;
68777: val <<= 1;
68778: CLEAR_CZNV;
68779: SET_ZFLG (((uae_s16)(val)) == 0);
68780: SET_NFLG (((uae_s16)(val)) < 0);
68781: SET_CFLG (carry >> 15);
68782: COPY_CARRY;
68783: m68k_incpc(4);
68784: fill_prefetch_0 ();
68785: put_word(dataa,val);
68786: }}}}}endlabel3704: ;
68787: return 18;
68788: }
68789: unsigned long REGPARAM2 CPUFUNC(op_e3f8_5)(uae_u32 opcode) /* LSLW */
68790: {
68791: OpcodeFamily = 75; CurrentInstrCycles = 16;
68792: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword_prefetch(2);
68793: if ((dataa & 1) != 0) {
68794: last_fault_for_exception_3 = dataa;
68795: last_op_for_exception_3 = opcode;
68796: last_addr_for_exception_3 = m68k_getpc() + 4;
68797: Exception(3, 0, M68000_EXC_SRC_CPU);
68798: goto endlabel3705;
68799: }
68800: {{ uae_s16 data = get_word(dataa);
68801: { uae_u16 val = data;
68802: uae_u32 carry = val & 0x8000;
68803: val <<= 1;
68804: CLEAR_CZNV;
68805: SET_ZFLG (((uae_s16)(val)) == 0);
68806: SET_NFLG (((uae_s16)(val)) < 0);
68807: SET_CFLG (carry >> 15);
68808: COPY_CARRY;
68809: m68k_incpc(4);
68810: fill_prefetch_0 ();
68811: put_word(dataa,val);
68812: }}}}}endlabel3705: ;
68813: return 16;
68814: }
68815: unsigned long REGPARAM2 CPUFUNC(op_e3f9_5)(uae_u32 opcode) /* LSLW */
68816: {
68817: OpcodeFamily = 75; CurrentInstrCycles = 20;
68818: {{ uaecptr dataa = get_ilong_prefetch(2);
68819: if ((dataa & 1) != 0) {
68820: last_fault_for_exception_3 = dataa;
68821: last_op_for_exception_3 = opcode;
68822: last_addr_for_exception_3 = m68k_getpc() + 6;
68823: Exception(3, 0, M68000_EXC_SRC_CPU);
68824: goto endlabel3706;
68825: }
68826: {{ uae_s16 data = get_word(dataa);
68827: { uae_u16 val = data;
68828: uae_u32 carry = val & 0x8000;
68829: val <<= 1;
68830: CLEAR_CZNV;
68831: SET_ZFLG (((uae_s16)(val)) == 0);
68832: SET_NFLG (((uae_s16)(val)) < 0);
68833: SET_CFLG (carry >> 15);
68834: COPY_CARRY;
68835: m68k_incpc(6);
68836: fill_prefetch_0 ();
68837: put_word(dataa,val);
68838: }}}}}endlabel3706: ;
68839: return 20;
68840: }
68841: unsigned long REGPARAM2 CPUFUNC(op_e4d0_5)(uae_u32 opcode) /* ROXRW */
68842: {
68843: uae_u32 srcreg = (opcode & 7);
68844: OpcodeFamily = 79; CurrentInstrCycles = 12;
68845: {{ uaecptr dataa = m68k_areg(regs, srcreg);
68846: if ((dataa & 1) != 0) {
68847: last_fault_for_exception_3 = dataa;
68848: last_op_for_exception_3 = opcode;
68849: last_addr_for_exception_3 = m68k_getpc() + 2;
68850: Exception(3, 0, M68000_EXC_SRC_CPU);
68851: goto endlabel3707;
68852: }
68853: {{ uae_s16 data = get_word(dataa);
68854: { uae_u16 val = data;
68855: uae_u32 carry = val & 1;
68856: val >>= 1;
68857: if (GET_XFLG) val |= 0x8000;
68858: CLEAR_CZNV;
68859: SET_ZFLG (((uae_s16)(val)) == 0);
68860: SET_NFLG (((uae_s16)(val)) < 0);
68861: SET_CFLG (carry);
68862: COPY_CARRY;
68863: m68k_incpc(2);
68864: fill_prefetch_2 ();
68865: put_word(dataa,val);
68866: }}}}}endlabel3707: ;
68867: return 12;
68868: }
68869: unsigned long REGPARAM2 CPUFUNC(op_e4d8_5)(uae_u32 opcode) /* ROXRW */
68870: {
68871: uae_u32 srcreg = (opcode & 7);
68872: OpcodeFamily = 79; CurrentInstrCycles = 12;
68873: {{ uaecptr dataa = m68k_areg(regs, srcreg);
68874: if ((dataa & 1) != 0) {
68875: last_fault_for_exception_3 = dataa;
68876: last_op_for_exception_3 = opcode;
68877: last_addr_for_exception_3 = m68k_getpc() + 2;
68878: Exception(3, 0, M68000_EXC_SRC_CPU);
68879: goto endlabel3708;
68880: }
68881: {{ uae_s16 data = get_word(dataa);
68882: m68k_areg(regs, srcreg) += 2;
68883: { uae_u16 val = data;
68884: uae_u32 carry = val & 1;
68885: val >>= 1;
68886: if (GET_XFLG) val |= 0x8000;
68887: CLEAR_CZNV;
68888: SET_ZFLG (((uae_s16)(val)) == 0);
68889: SET_NFLG (((uae_s16)(val)) < 0);
68890: SET_CFLG (carry);
68891: COPY_CARRY;
68892: m68k_incpc(2);
68893: fill_prefetch_2 ();
68894: put_word(dataa,val);
68895: }}}}}endlabel3708: ;
68896: return 12;
68897: }
68898: unsigned long REGPARAM2 CPUFUNC(op_e4e0_5)(uae_u32 opcode) /* ROXRW */
68899: {
68900: uae_u32 srcreg = (opcode & 7);
68901: OpcodeFamily = 79; CurrentInstrCycles = 14;
68902: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
68903: if ((dataa & 1) != 0) {
68904: last_fault_for_exception_3 = dataa;
68905: last_op_for_exception_3 = opcode;
68906: last_addr_for_exception_3 = m68k_getpc() + 2;
68907: Exception(3, 0, M68000_EXC_SRC_CPU);
68908: goto endlabel3709;
68909: }
68910: {{ uae_s16 data = get_word(dataa);
68911: m68k_areg (regs, srcreg) = dataa;
68912: { uae_u16 val = data;
68913: uae_u32 carry = val & 1;
68914: val >>= 1;
68915: if (GET_XFLG) val |= 0x8000;
68916: CLEAR_CZNV;
68917: SET_ZFLG (((uae_s16)(val)) == 0);
68918: SET_NFLG (((uae_s16)(val)) < 0);
68919: SET_CFLG (carry);
68920: COPY_CARRY;
68921: m68k_incpc(2);
68922: fill_prefetch_2 ();
68923: put_word(dataa,val);
68924: }}}}}endlabel3709: ;
68925: return 14;
68926: }
68927: unsigned long REGPARAM2 CPUFUNC(op_e4e8_5)(uae_u32 opcode) /* ROXRW */
68928: {
68929: uae_u32 srcreg = (opcode & 7);
68930: OpcodeFamily = 79; CurrentInstrCycles = 16;
68931: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
68932: if ((dataa & 1) != 0) {
68933: last_fault_for_exception_3 = dataa;
68934: last_op_for_exception_3 = opcode;
68935: last_addr_for_exception_3 = m68k_getpc() + 4;
68936: Exception(3, 0, M68000_EXC_SRC_CPU);
68937: goto endlabel3710;
68938: }
68939: {{ uae_s16 data = get_word(dataa);
68940: { uae_u16 val = data;
68941: uae_u32 carry = val & 1;
68942: val >>= 1;
68943: if (GET_XFLG) val |= 0x8000;
68944: CLEAR_CZNV;
68945: SET_ZFLG (((uae_s16)(val)) == 0);
68946: SET_NFLG (((uae_s16)(val)) < 0);
68947: SET_CFLG (carry);
68948: COPY_CARRY;
68949: m68k_incpc(4);
68950: fill_prefetch_0 ();
68951: put_word(dataa,val);
68952: }}}}}endlabel3710: ;
68953: return 16;
68954: }
68955: unsigned long REGPARAM2 CPUFUNC(op_e4f0_5)(uae_u32 opcode) /* ROXRW */
68956: {
68957: uae_u32 srcreg = (opcode & 7);
68958: OpcodeFamily = 79; CurrentInstrCycles = 18;
68959: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
68960: BusCyclePenalty += 2;
68961: if ((dataa & 1) != 0) {
68962: last_fault_for_exception_3 = dataa;
68963: last_op_for_exception_3 = opcode;
68964: last_addr_for_exception_3 = m68k_getpc() + 4;
68965: Exception(3, 0, M68000_EXC_SRC_CPU);
68966: goto endlabel3711;
68967: }
68968: {{ uae_s16 data = get_word(dataa);
68969: { uae_u16 val = data;
68970: uae_u32 carry = val & 1;
68971: val >>= 1;
68972: if (GET_XFLG) val |= 0x8000;
68973: CLEAR_CZNV;
68974: SET_ZFLG (((uae_s16)(val)) == 0);
68975: SET_NFLG (((uae_s16)(val)) < 0);
68976: SET_CFLG (carry);
68977: COPY_CARRY;
68978: m68k_incpc(4);
68979: fill_prefetch_0 ();
68980: put_word(dataa,val);
68981: }}}}}endlabel3711: ;
68982: return 18;
68983: }
68984: unsigned long REGPARAM2 CPUFUNC(op_e4f8_5)(uae_u32 opcode) /* ROXRW */
68985: {
68986: OpcodeFamily = 79; CurrentInstrCycles = 16;
68987: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword_prefetch(2);
68988: if ((dataa & 1) != 0) {
68989: last_fault_for_exception_3 = dataa;
68990: last_op_for_exception_3 = opcode;
68991: last_addr_for_exception_3 = m68k_getpc() + 4;
68992: Exception(3, 0, M68000_EXC_SRC_CPU);
68993: goto endlabel3712;
68994: }
68995: {{ uae_s16 data = get_word(dataa);
68996: { uae_u16 val = data;
68997: uae_u32 carry = val & 1;
68998: val >>= 1;
68999: if (GET_XFLG) val |= 0x8000;
69000: CLEAR_CZNV;
69001: SET_ZFLG (((uae_s16)(val)) == 0);
69002: SET_NFLG (((uae_s16)(val)) < 0);
69003: SET_CFLG (carry);
69004: COPY_CARRY;
69005: m68k_incpc(4);
69006: fill_prefetch_0 ();
69007: put_word(dataa,val);
69008: }}}}}endlabel3712: ;
69009: return 16;
69010: }
69011: unsigned long REGPARAM2 CPUFUNC(op_e4f9_5)(uae_u32 opcode) /* ROXRW */
69012: {
69013: OpcodeFamily = 79; CurrentInstrCycles = 20;
69014: {{ uaecptr dataa = get_ilong_prefetch(2);
69015: if ((dataa & 1) != 0) {
69016: last_fault_for_exception_3 = dataa;
69017: last_op_for_exception_3 = opcode;
69018: last_addr_for_exception_3 = m68k_getpc() + 6;
69019: Exception(3, 0, M68000_EXC_SRC_CPU);
69020: goto endlabel3713;
69021: }
69022: {{ uae_s16 data = get_word(dataa);
69023: { uae_u16 val = data;
69024: uae_u32 carry = val & 1;
69025: val >>= 1;
69026: if (GET_XFLG) val |= 0x8000;
69027: CLEAR_CZNV;
69028: SET_ZFLG (((uae_s16)(val)) == 0);
69029: SET_NFLG (((uae_s16)(val)) < 0);
69030: SET_CFLG (carry);
69031: COPY_CARRY;
69032: m68k_incpc(6);
69033: fill_prefetch_0 ();
69034: put_word(dataa,val);
69035: }}}}}endlabel3713: ;
69036: return 20;
69037: }
69038: unsigned long REGPARAM2 CPUFUNC(op_e5d0_5)(uae_u32 opcode) /* ROXLW */
69039: {
69040: uae_u32 srcreg = (opcode & 7);
69041: OpcodeFamily = 78; CurrentInstrCycles = 12;
69042: {{ uaecptr dataa = m68k_areg(regs, srcreg);
69043: if ((dataa & 1) != 0) {
69044: last_fault_for_exception_3 = dataa;
69045: last_op_for_exception_3 = opcode;
69046: last_addr_for_exception_3 = m68k_getpc() + 2;
69047: Exception(3, 0, M68000_EXC_SRC_CPU);
69048: goto endlabel3714;
69049: }
69050: {{ uae_s16 data = get_word(dataa);
69051: { uae_u16 val = data;
69052: uae_u32 carry = val & 0x8000;
69053: val <<= 1;
69054: if (GET_XFLG) val |= 1;
69055: CLEAR_CZNV;
69056: SET_ZFLG (((uae_s16)(val)) == 0);
69057: SET_NFLG (((uae_s16)(val)) < 0);
69058: SET_CFLG (carry >> 15);
69059: COPY_CARRY;
69060: m68k_incpc(2);
69061: fill_prefetch_2 ();
69062: put_word(dataa,val);
69063: }}}}}endlabel3714: ;
69064: return 12;
69065: }
69066: unsigned long REGPARAM2 CPUFUNC(op_e5d8_5)(uae_u32 opcode) /* ROXLW */
69067: {
69068: uae_u32 srcreg = (opcode & 7);
69069: OpcodeFamily = 78; CurrentInstrCycles = 12;
69070: {{ uaecptr dataa = m68k_areg(regs, srcreg);
69071: if ((dataa & 1) != 0) {
69072: last_fault_for_exception_3 = dataa;
69073: last_op_for_exception_3 = opcode;
69074: last_addr_for_exception_3 = m68k_getpc() + 2;
69075: Exception(3, 0, M68000_EXC_SRC_CPU);
69076: goto endlabel3715;
69077: }
69078: {{ uae_s16 data = get_word(dataa);
69079: m68k_areg(regs, srcreg) += 2;
69080: { uae_u16 val = data;
69081: uae_u32 carry = val & 0x8000;
69082: val <<= 1;
69083: if (GET_XFLG) val |= 1;
69084: CLEAR_CZNV;
69085: SET_ZFLG (((uae_s16)(val)) == 0);
69086: SET_NFLG (((uae_s16)(val)) < 0);
69087: SET_CFLG (carry >> 15);
69088: COPY_CARRY;
69089: m68k_incpc(2);
69090: fill_prefetch_2 ();
69091: put_word(dataa,val);
69092: }}}}}endlabel3715: ;
69093: return 12;
69094: }
69095: unsigned long REGPARAM2 CPUFUNC(op_e5e0_5)(uae_u32 opcode) /* ROXLW */
69096: {
69097: uae_u32 srcreg = (opcode & 7);
69098: OpcodeFamily = 78; CurrentInstrCycles = 14;
69099: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
69100: if ((dataa & 1) != 0) {
69101: last_fault_for_exception_3 = dataa;
69102: last_op_for_exception_3 = opcode;
69103: last_addr_for_exception_3 = m68k_getpc() + 2;
69104: Exception(3, 0, M68000_EXC_SRC_CPU);
69105: goto endlabel3716;
69106: }
69107: {{ uae_s16 data = get_word(dataa);
69108: m68k_areg (regs, srcreg) = dataa;
69109: { uae_u16 val = data;
69110: uae_u32 carry = val & 0x8000;
69111: val <<= 1;
69112: if (GET_XFLG) val |= 1;
69113: CLEAR_CZNV;
69114: SET_ZFLG (((uae_s16)(val)) == 0);
69115: SET_NFLG (((uae_s16)(val)) < 0);
69116: SET_CFLG (carry >> 15);
69117: COPY_CARRY;
69118: m68k_incpc(2);
69119: fill_prefetch_2 ();
69120: put_word(dataa,val);
69121: }}}}}endlabel3716: ;
69122: return 14;
69123: }
69124: unsigned long REGPARAM2 CPUFUNC(op_e5e8_5)(uae_u32 opcode) /* ROXLW */
69125: {
69126: uae_u32 srcreg = (opcode & 7);
69127: OpcodeFamily = 78; CurrentInstrCycles = 16;
69128: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
69129: if ((dataa & 1) != 0) {
69130: last_fault_for_exception_3 = dataa;
69131: last_op_for_exception_3 = opcode;
69132: last_addr_for_exception_3 = m68k_getpc() + 4;
69133: Exception(3, 0, M68000_EXC_SRC_CPU);
69134: goto endlabel3717;
69135: }
69136: {{ uae_s16 data = get_word(dataa);
69137: { uae_u16 val = data;
69138: uae_u32 carry = val & 0x8000;
69139: val <<= 1;
69140: if (GET_XFLG) val |= 1;
69141: CLEAR_CZNV;
69142: SET_ZFLG (((uae_s16)(val)) == 0);
69143: SET_NFLG (((uae_s16)(val)) < 0);
69144: SET_CFLG (carry >> 15);
69145: COPY_CARRY;
69146: m68k_incpc(4);
69147: fill_prefetch_0 ();
69148: put_word(dataa,val);
69149: }}}}}endlabel3717: ;
69150: return 16;
69151: }
69152: unsigned long REGPARAM2 CPUFUNC(op_e5f0_5)(uae_u32 opcode) /* ROXLW */
69153: {
69154: uae_u32 srcreg = (opcode & 7);
69155: OpcodeFamily = 78; CurrentInstrCycles = 18;
69156: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
69157: BusCyclePenalty += 2;
69158: if ((dataa & 1) != 0) {
69159: last_fault_for_exception_3 = dataa;
69160: last_op_for_exception_3 = opcode;
69161: last_addr_for_exception_3 = m68k_getpc() + 4;
69162: Exception(3, 0, M68000_EXC_SRC_CPU);
69163: goto endlabel3718;
69164: }
69165: {{ uae_s16 data = get_word(dataa);
69166: { uae_u16 val = data;
69167: uae_u32 carry = val & 0x8000;
69168: val <<= 1;
69169: if (GET_XFLG) val |= 1;
69170: CLEAR_CZNV;
69171: SET_ZFLG (((uae_s16)(val)) == 0);
69172: SET_NFLG (((uae_s16)(val)) < 0);
69173: SET_CFLG (carry >> 15);
69174: COPY_CARRY;
69175: m68k_incpc(4);
69176: fill_prefetch_0 ();
69177: put_word(dataa,val);
69178: }}}}}endlabel3718: ;
69179: return 18;
69180: }
69181: unsigned long REGPARAM2 CPUFUNC(op_e5f8_5)(uae_u32 opcode) /* ROXLW */
69182: {
69183: OpcodeFamily = 78; CurrentInstrCycles = 16;
69184: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword_prefetch(2);
69185: if ((dataa & 1) != 0) {
69186: last_fault_for_exception_3 = dataa;
69187: last_op_for_exception_3 = opcode;
69188: last_addr_for_exception_3 = m68k_getpc() + 4;
69189: Exception(3, 0, M68000_EXC_SRC_CPU);
69190: goto endlabel3719;
69191: }
69192: {{ uae_s16 data = get_word(dataa);
69193: { uae_u16 val = data;
69194: uae_u32 carry = val & 0x8000;
69195: val <<= 1;
69196: if (GET_XFLG) val |= 1;
69197: CLEAR_CZNV;
69198: SET_ZFLG (((uae_s16)(val)) == 0);
69199: SET_NFLG (((uae_s16)(val)) < 0);
69200: SET_CFLG (carry >> 15);
69201: COPY_CARRY;
69202: m68k_incpc(4);
69203: fill_prefetch_0 ();
69204: put_word(dataa,val);
69205: }}}}}endlabel3719: ;
69206: return 16;
69207: }
69208: unsigned long REGPARAM2 CPUFUNC(op_e5f9_5)(uae_u32 opcode) /* ROXLW */
69209: {
69210: OpcodeFamily = 78; CurrentInstrCycles = 20;
69211: {{ uaecptr dataa = get_ilong_prefetch(2);
69212: if ((dataa & 1) != 0) {
69213: last_fault_for_exception_3 = dataa;
69214: last_op_for_exception_3 = opcode;
69215: last_addr_for_exception_3 = m68k_getpc() + 6;
69216: Exception(3, 0, M68000_EXC_SRC_CPU);
69217: goto endlabel3720;
69218: }
69219: {{ uae_s16 data = get_word(dataa);
69220: { uae_u16 val = data;
69221: uae_u32 carry = val & 0x8000;
69222: val <<= 1;
69223: if (GET_XFLG) val |= 1;
69224: CLEAR_CZNV;
69225: SET_ZFLG (((uae_s16)(val)) == 0);
69226: SET_NFLG (((uae_s16)(val)) < 0);
69227: SET_CFLG (carry >> 15);
69228: COPY_CARRY;
69229: m68k_incpc(6);
69230: fill_prefetch_0 ();
69231: put_word(dataa,val);
69232: }}}}}endlabel3720: ;
69233: return 20;
69234: }
69235: unsigned long REGPARAM2 CPUFUNC(op_e6d0_5)(uae_u32 opcode) /* RORW */
69236: {
69237: uae_u32 srcreg = (opcode & 7);
69238: OpcodeFamily = 77; CurrentInstrCycles = 12;
69239: {{ uaecptr dataa = m68k_areg(regs, srcreg);
69240: if ((dataa & 1) != 0) {
69241: last_fault_for_exception_3 = dataa;
69242: last_op_for_exception_3 = opcode;
69243: last_addr_for_exception_3 = m68k_getpc() + 2;
69244: Exception(3, 0, M68000_EXC_SRC_CPU);
69245: goto endlabel3721;
69246: }
69247: {{ uae_s16 data = get_word(dataa);
69248: { uae_u16 val = data;
69249: uae_u32 carry = val & 1;
69250: val >>= 1;
69251: if (carry) val |= 0x8000;
69252: CLEAR_CZNV;
69253: SET_ZFLG (((uae_s16)(val)) == 0);
69254: SET_NFLG (((uae_s16)(val)) < 0);
69255: SET_CFLG (carry);
69256: m68k_incpc(2);
69257: fill_prefetch_2 ();
69258: put_word(dataa,val);
69259: }}}}}endlabel3721: ;
69260: return 12;
69261: }
69262: unsigned long REGPARAM2 CPUFUNC(op_e6d8_5)(uae_u32 opcode) /* RORW */
69263: {
69264: uae_u32 srcreg = (opcode & 7);
69265: OpcodeFamily = 77; CurrentInstrCycles = 12;
69266: {{ uaecptr dataa = m68k_areg(regs, srcreg);
69267: if ((dataa & 1) != 0) {
69268: last_fault_for_exception_3 = dataa;
69269: last_op_for_exception_3 = opcode;
69270: last_addr_for_exception_3 = m68k_getpc() + 2;
69271: Exception(3, 0, M68000_EXC_SRC_CPU);
69272: goto endlabel3722;
69273: }
69274: {{ uae_s16 data = get_word(dataa);
69275: m68k_areg(regs, srcreg) += 2;
69276: { uae_u16 val = data;
69277: uae_u32 carry = val & 1;
69278: val >>= 1;
69279: if (carry) val |= 0x8000;
69280: CLEAR_CZNV;
69281: SET_ZFLG (((uae_s16)(val)) == 0);
69282: SET_NFLG (((uae_s16)(val)) < 0);
69283: SET_CFLG (carry);
69284: m68k_incpc(2);
69285: fill_prefetch_2 ();
69286: put_word(dataa,val);
69287: }}}}}endlabel3722: ;
69288: return 12;
69289: }
69290: unsigned long REGPARAM2 CPUFUNC(op_e6e0_5)(uae_u32 opcode) /* RORW */
69291: {
69292: uae_u32 srcreg = (opcode & 7);
69293: OpcodeFamily = 77; CurrentInstrCycles = 14;
69294: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
69295: if ((dataa & 1) != 0) {
69296: last_fault_for_exception_3 = dataa;
69297: last_op_for_exception_3 = opcode;
69298: last_addr_for_exception_3 = m68k_getpc() + 2;
69299: Exception(3, 0, M68000_EXC_SRC_CPU);
69300: goto endlabel3723;
69301: }
69302: {{ uae_s16 data = get_word(dataa);
69303: m68k_areg (regs, srcreg) = dataa;
69304: { uae_u16 val = data;
69305: uae_u32 carry = val & 1;
69306: val >>= 1;
69307: if (carry) val |= 0x8000;
69308: CLEAR_CZNV;
69309: SET_ZFLG (((uae_s16)(val)) == 0);
69310: SET_NFLG (((uae_s16)(val)) < 0);
69311: SET_CFLG (carry);
69312: m68k_incpc(2);
69313: fill_prefetch_2 ();
69314: put_word(dataa,val);
69315: }}}}}endlabel3723: ;
69316: return 14;
69317: }
69318: unsigned long REGPARAM2 CPUFUNC(op_e6e8_5)(uae_u32 opcode) /* RORW */
69319: {
69320: uae_u32 srcreg = (opcode & 7);
69321: OpcodeFamily = 77; CurrentInstrCycles = 16;
69322: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
69323: if ((dataa & 1) != 0) {
69324: last_fault_for_exception_3 = dataa;
69325: last_op_for_exception_3 = opcode;
69326: last_addr_for_exception_3 = m68k_getpc() + 4;
69327: Exception(3, 0, M68000_EXC_SRC_CPU);
69328: goto endlabel3724;
69329: }
69330: {{ uae_s16 data = get_word(dataa);
69331: { uae_u16 val = data;
69332: uae_u32 carry = val & 1;
69333: val >>= 1;
69334: if (carry) val |= 0x8000;
69335: CLEAR_CZNV;
69336: SET_ZFLG (((uae_s16)(val)) == 0);
69337: SET_NFLG (((uae_s16)(val)) < 0);
69338: SET_CFLG (carry);
69339: m68k_incpc(4);
69340: fill_prefetch_0 ();
69341: put_word(dataa,val);
69342: }}}}}endlabel3724: ;
69343: return 16;
69344: }
69345: unsigned long REGPARAM2 CPUFUNC(op_e6f0_5)(uae_u32 opcode) /* RORW */
69346: {
69347: uae_u32 srcreg = (opcode & 7);
69348: OpcodeFamily = 77; CurrentInstrCycles = 18;
69349: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
69350: BusCyclePenalty += 2;
69351: if ((dataa & 1) != 0) {
69352: last_fault_for_exception_3 = dataa;
69353: last_op_for_exception_3 = opcode;
69354: last_addr_for_exception_3 = m68k_getpc() + 4;
69355: Exception(3, 0, M68000_EXC_SRC_CPU);
69356: goto endlabel3725;
69357: }
69358: {{ uae_s16 data = get_word(dataa);
69359: { uae_u16 val = data;
69360: uae_u32 carry = val & 1;
69361: val >>= 1;
69362: if (carry) val |= 0x8000;
69363: CLEAR_CZNV;
69364: SET_ZFLG (((uae_s16)(val)) == 0);
69365: SET_NFLG (((uae_s16)(val)) < 0);
69366: SET_CFLG (carry);
69367: m68k_incpc(4);
69368: fill_prefetch_0 ();
69369: put_word(dataa,val);
69370: }}}}}endlabel3725: ;
69371: return 18;
69372: }
69373: unsigned long REGPARAM2 CPUFUNC(op_e6f8_5)(uae_u32 opcode) /* RORW */
69374: {
69375: OpcodeFamily = 77; CurrentInstrCycles = 16;
69376: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword_prefetch(2);
69377: if ((dataa & 1) != 0) {
69378: last_fault_for_exception_3 = dataa;
69379: last_op_for_exception_3 = opcode;
69380: last_addr_for_exception_3 = m68k_getpc() + 4;
69381: Exception(3, 0, M68000_EXC_SRC_CPU);
69382: goto endlabel3726;
69383: }
69384: {{ uae_s16 data = get_word(dataa);
69385: { uae_u16 val = data;
69386: uae_u32 carry = val & 1;
69387: val >>= 1;
69388: if (carry) val |= 0x8000;
69389: CLEAR_CZNV;
69390: SET_ZFLG (((uae_s16)(val)) == 0);
69391: SET_NFLG (((uae_s16)(val)) < 0);
69392: SET_CFLG (carry);
69393: m68k_incpc(4);
69394: fill_prefetch_0 ();
69395: put_word(dataa,val);
69396: }}}}}endlabel3726: ;
69397: return 16;
69398: }
69399: unsigned long REGPARAM2 CPUFUNC(op_e6f9_5)(uae_u32 opcode) /* RORW */
69400: {
69401: OpcodeFamily = 77; CurrentInstrCycles = 20;
69402: {{ uaecptr dataa = get_ilong_prefetch(2);
69403: if ((dataa & 1) != 0) {
69404: last_fault_for_exception_3 = dataa;
69405: last_op_for_exception_3 = opcode;
69406: last_addr_for_exception_3 = m68k_getpc() + 6;
69407: Exception(3, 0, M68000_EXC_SRC_CPU);
69408: goto endlabel3727;
69409: }
69410: {{ uae_s16 data = get_word(dataa);
69411: { uae_u16 val = data;
69412: uae_u32 carry = val & 1;
69413: val >>= 1;
69414: if (carry) val |= 0x8000;
69415: CLEAR_CZNV;
69416: SET_ZFLG (((uae_s16)(val)) == 0);
69417: SET_NFLG (((uae_s16)(val)) < 0);
69418: SET_CFLG (carry);
69419: m68k_incpc(6);
69420: fill_prefetch_0 ();
69421: put_word(dataa,val);
69422: }}}}}endlabel3727: ;
69423: return 20;
69424: }
69425: unsigned long REGPARAM2 CPUFUNC(op_e7d0_5)(uae_u32 opcode) /* ROLW */
69426: {
69427: uae_u32 srcreg = (opcode & 7);
69428: OpcodeFamily = 76; CurrentInstrCycles = 12;
69429: {{ uaecptr dataa = m68k_areg(regs, srcreg);
69430: if ((dataa & 1) != 0) {
69431: last_fault_for_exception_3 = dataa;
69432: last_op_for_exception_3 = opcode;
69433: last_addr_for_exception_3 = m68k_getpc() + 2;
69434: Exception(3, 0, M68000_EXC_SRC_CPU);
69435: goto endlabel3728;
69436: }
69437: {{ uae_s16 data = get_word(dataa);
69438: { uae_u16 val = data;
69439: uae_u32 carry = val & 0x8000;
69440: val <<= 1;
69441: if (carry) val |= 1;
69442: CLEAR_CZNV;
69443: SET_ZFLG (((uae_s16)(val)) == 0);
69444: SET_NFLG (((uae_s16)(val)) < 0);
69445: SET_CFLG (carry >> 15);
69446: m68k_incpc(2);
69447: fill_prefetch_2 ();
69448: put_word(dataa,val);
69449: }}}}}endlabel3728: ;
69450: return 12;
69451: }
69452: unsigned long REGPARAM2 CPUFUNC(op_e7d8_5)(uae_u32 opcode) /* ROLW */
69453: {
69454: uae_u32 srcreg = (opcode & 7);
69455: OpcodeFamily = 76; CurrentInstrCycles = 12;
69456: {{ uaecptr dataa = m68k_areg(regs, srcreg);
69457: if ((dataa & 1) != 0) {
69458: last_fault_for_exception_3 = dataa;
69459: last_op_for_exception_3 = opcode;
69460: last_addr_for_exception_3 = m68k_getpc() + 2;
69461: Exception(3, 0, M68000_EXC_SRC_CPU);
69462: goto endlabel3729;
69463: }
69464: {{ uae_s16 data = get_word(dataa);
69465: m68k_areg(regs, srcreg) += 2;
69466: { uae_u16 val = data;
69467: uae_u32 carry = val & 0x8000;
69468: val <<= 1;
69469: if (carry) val |= 1;
69470: CLEAR_CZNV;
69471: SET_ZFLG (((uae_s16)(val)) == 0);
69472: SET_NFLG (((uae_s16)(val)) < 0);
69473: SET_CFLG (carry >> 15);
69474: m68k_incpc(2);
69475: fill_prefetch_2 ();
69476: put_word(dataa,val);
69477: }}}}}endlabel3729: ;
69478: return 12;
69479: }
69480: unsigned long REGPARAM2 CPUFUNC(op_e7e0_5)(uae_u32 opcode) /* ROLW */
69481: {
69482: uae_u32 srcreg = (opcode & 7);
69483: OpcodeFamily = 76; CurrentInstrCycles = 14;
69484: {{ uaecptr dataa = m68k_areg(regs, srcreg) - 2;
69485: if ((dataa & 1) != 0) {
69486: last_fault_for_exception_3 = dataa;
69487: last_op_for_exception_3 = opcode;
69488: last_addr_for_exception_3 = m68k_getpc() + 2;
69489: Exception(3, 0, M68000_EXC_SRC_CPU);
69490: goto endlabel3730;
69491: }
69492: {{ uae_s16 data = get_word(dataa);
69493: m68k_areg (regs, srcreg) = dataa;
69494: { uae_u16 val = data;
69495: uae_u32 carry = val & 0x8000;
69496: val <<= 1;
69497: if (carry) val |= 1;
69498: CLEAR_CZNV;
69499: SET_ZFLG (((uae_s16)(val)) == 0);
69500: SET_NFLG (((uae_s16)(val)) < 0);
69501: SET_CFLG (carry >> 15);
69502: m68k_incpc(2);
69503: fill_prefetch_2 ();
69504: put_word(dataa,val);
69505: }}}}}endlabel3730: ;
69506: return 14;
69507: }
69508: unsigned long REGPARAM2 CPUFUNC(op_e7e8_5)(uae_u32 opcode) /* ROLW */
69509: {
69510: uae_u32 srcreg = (opcode & 7);
69511: OpcodeFamily = 76; CurrentInstrCycles = 16;
69512: {{ uaecptr dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_prefetch(2);
69513: if ((dataa & 1) != 0) {
69514: last_fault_for_exception_3 = dataa;
69515: last_op_for_exception_3 = opcode;
69516: last_addr_for_exception_3 = m68k_getpc() + 4;
69517: Exception(3, 0, M68000_EXC_SRC_CPU);
69518: goto endlabel3731;
69519: }
69520: {{ uae_s16 data = get_word(dataa);
69521: { uae_u16 val = data;
69522: uae_u32 carry = val & 0x8000;
69523: val <<= 1;
69524: if (carry) val |= 1;
69525: CLEAR_CZNV;
69526: SET_ZFLG (((uae_s16)(val)) == 0);
69527: SET_NFLG (((uae_s16)(val)) < 0);
69528: SET_CFLG (carry >> 15);
69529: m68k_incpc(4);
69530: fill_prefetch_0 ();
69531: put_word(dataa,val);
69532: }}}}}endlabel3731: ;
69533: return 16;
69534: }
69535: unsigned long REGPARAM2 CPUFUNC(op_e7f0_5)(uae_u32 opcode) /* ROLW */
69536: {
69537: uae_u32 srcreg = (opcode & 7);
69538: OpcodeFamily = 76; CurrentInstrCycles = 18;
69539: {{ uaecptr dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2));
69540: BusCyclePenalty += 2;
69541: if ((dataa & 1) != 0) {
69542: last_fault_for_exception_3 = dataa;
69543: last_op_for_exception_3 = opcode;
69544: last_addr_for_exception_3 = m68k_getpc() + 4;
69545: Exception(3, 0, M68000_EXC_SRC_CPU);
69546: goto endlabel3732;
69547: }
69548: {{ uae_s16 data = get_word(dataa);
69549: { uae_u16 val = data;
69550: uae_u32 carry = val & 0x8000;
69551: val <<= 1;
69552: if (carry) val |= 1;
69553: CLEAR_CZNV;
69554: SET_ZFLG (((uae_s16)(val)) == 0);
69555: SET_NFLG (((uae_s16)(val)) < 0);
69556: SET_CFLG (carry >> 15);
69557: m68k_incpc(4);
69558: fill_prefetch_0 ();
69559: put_word(dataa,val);
69560: }}}}}endlabel3732: ;
69561: return 18;
69562: }
69563: unsigned long REGPARAM2 CPUFUNC(op_e7f8_5)(uae_u32 opcode) /* ROLW */
69564: {
69565: OpcodeFamily = 76; CurrentInstrCycles = 16;
69566: {{ uaecptr dataa = (uae_s32)(uae_s16)get_iword_prefetch(2);
69567: if ((dataa & 1) != 0) {
69568: last_fault_for_exception_3 = dataa;
69569: last_op_for_exception_3 = opcode;
69570: last_addr_for_exception_3 = m68k_getpc() + 4;
69571: Exception(3, 0, M68000_EXC_SRC_CPU);
69572: goto endlabel3733;
69573: }
69574: {{ uae_s16 data = get_word(dataa);
69575: { uae_u16 val = data;
69576: uae_u32 carry = val & 0x8000;
69577: val <<= 1;
69578: if (carry) val |= 1;
69579: CLEAR_CZNV;
69580: SET_ZFLG (((uae_s16)(val)) == 0);
69581: SET_NFLG (((uae_s16)(val)) < 0);
69582: SET_CFLG (carry >> 15);
69583: m68k_incpc(4);
69584: fill_prefetch_0 ();
69585: put_word(dataa,val);
69586: }}}}}endlabel3733: ;
69587: return 16;
69588: }
69589: unsigned long REGPARAM2 CPUFUNC(op_e7f9_5)(uae_u32 opcode) /* ROLW */
69590: {
69591: OpcodeFamily = 76; CurrentInstrCycles = 20;
69592: {{ uaecptr dataa = get_ilong_prefetch(2);
69593: if ((dataa & 1) != 0) {
69594: last_fault_for_exception_3 = dataa;
69595: last_op_for_exception_3 = opcode;
69596: last_addr_for_exception_3 = m68k_getpc() + 6;
69597: Exception(3, 0, M68000_EXC_SRC_CPU);
69598: goto endlabel3734;
69599: }
69600: {{ uae_s16 data = get_word(dataa);
69601: { uae_u16 val = data;
69602: uae_u32 carry = val & 0x8000;
69603: val <<= 1;
69604: if (carry) val |= 1;
69605: CLEAR_CZNV;
69606: SET_ZFLG (((uae_s16)(val)) == 0);
69607: SET_NFLG (((uae_s16)(val)) < 0);
69608: SET_CFLG (carry >> 15);
69609: m68k_incpc(6);
69610: fill_prefetch_0 ();
69611: put_word(dataa,val);
69612: }}}}}endlabel3734: ;
69613: return 20;
69614: }
69615: #endif
69616:
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