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1.1 root 1: /*
2: * UAE - The Un*x Amiga Emulator - CPU core
3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
12: */
13:
14:
15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
18: /* will not point to the opcode that generated the bus error. */
19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
22: /* Cwik, [email protected]). */
23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
24: /* because it doesn't necessarily point to the next instruction after the one that */
25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
28: /* This should be fixed with a real model. */
29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
30: /* handler should be called after the group 2's handler. If a bus error, address */
31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
35: /* trace handler one last time with the PC set to the CHK's handler (even if */
36: /* trace mode is internally turned off while processing an exception). Once trace */
37: /* handler is finished (RTE), we return to the CHK's handler. */
38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
40: /* Transbeauce 2 demo). */
41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
42: /* instruction (Transbeauce 2 demo). */
43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
45: /* built-in cartridge image is loaded. */
46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after intruction 'n' was processed, the */
50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
57: /* default $40 (this could be a problem with programs requiring a precise cycles */
58: /* calculation while changing VR, but no such programs were encountered so far). */
59: /* -> FIXED, see 2008/10/05 */
60: /* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */
61: /* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/
62: /* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */
63: /* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */
64: /* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/
65: /* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */
66: /* FIXME : Others exception cycles may be wrong too. */
67: /* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/
68: /* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */
69: /* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */
70: /* the 'normal' 68000 ones and the exception number is not enough to decide. */
71: /* We need ExceptionSource to remove the ambiguity. */
72: /* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */
73: /* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */
74: /* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/
75: /* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */
76: /* possible int handlers while PendingInterruptCount <= 0 without increasing the */
77: /* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */
78: /* same time for example, the HBL was delayed by 4 cycles if no MFP exception */
79: /* was triggered, which was wrong (this happened mainly with the TOS timer D that */
80: /* expires very often). Such precision is required for very recent hardscroll */
81: /* techniques that use 'stop' to stay in sync with the video shifter. */
82: /* 2008/11/23 [NP] In 'do_specialties()', when in STOP state, we must first test for a pending */
83: /* interrupt that would exit the STOP state immediatly, without doing a 'while' */
84: /* loop until 'SPCFLAG_INT' or 'SPCFLAG_DOINT' are set. */
85: /* 2008/11/29 [NP] Call 'InterruptAddJitter()' when a video interrupt happens to precisely emulate */
86: /* the jitter happening on the Atari (see video.c for the jitter patterns). */
87: /* FIXME : Pattern is not always correct when handling pending interrupt in STOP */
88: /* state, but this should be harmless as no program has been found using this. */
89: /* 2008/12/05 [NP] On Atari it takes 56 cycles to process an interrupt. During that time, a higher */
90: /* level interrupt could happen and we must execute it before the previous int */
91: /* (see m68k_run_1()). */
92: /* This is the case for the VBL which can interrupt the last HBL of a screen */
93: /* (end of line 312) at various point (from 0 to 8 cycles). */
94: /* This fixes the fullscreen tunnel in Suretrip 49% by Checkpoint, which uses a */
95: /* really buggy vbl/hbl combination, even on a real ST. Also fixes sample sound */
96: /* in Swedish New Year's TCB screen. */
97: /* 2008/12/11 [NP] Extract interrupt handling from do_specialties() in do_specialties_interrupt() */
98: /* and factorize some code. In m68k_run_1 when testing for multiple interrupts at */
99: /* the same time, call do_specialties_interrupt() to check only the special flags */
100: /* related to interrupts (MFP and video) (else, this caused problem when the TRACE */
101: /* flag was set). */
102: /* 2008/12/14 [NP] In m68k_run_1(), we should check for simultaneous ints only if the cpu is not */
103: /* in the STOP state after the last instruction was executed. Else, the call to */
104: /* do_specialties_interrupt() could acknowledge the interrupt and we would never */
105: /* exit the STOP state in do_specialties() just after (the problem can happen if */
106: /* the TOS timer D expires just at the same time as the STOP instruction). */
107: /* Fix regression since 2008/12/11 in the hidden screen from ULM in Oh Crickey... */
108: /* 2008/12/20 [NP] In m68k_run_1(), when checking interrupts and STOP mode, we should test */
109: /* PendingInterruptCount before regs.spcflags to have a faster evaluation of the */
110: /* 'while' condition (PendingInterruptCount <= 0 is true less often than STOP==0) */
1.1.1.2 ! root 111: /* 2011/04/29 [NP] In Exception(), check the new PC is not on odd address ; raise an address error */
! 112: /* exception if it's the case. */
1.1 root 113:
114:
115: const char NewCpu_fileid[] = "Hatari newcpu.c : " __DATE__ " " __TIME__;
116:
117: #include "sysdeps.h"
118: #include "hatari-glue.h"
119: #include "maccess.h"
120: #include "memory.h"
121: #include "newcpu.h"
122: #include "main.h"
123: #include "m68000.h"
124: #include "cycInt.h"
125: #include "mfp.h"
126: #include "cart.h"
127: #include "dialog.h"
1.1.1.2 ! root 128: #include "screen.h"
1.1 root 129: #include "video.h"
130: #include "options.h"
131: #include "log.h"
132: #include "debugui.h"
133: #include "debugcpu.h"
1.1.1.2 ! root 134: #include "68kDisass.h"
1.1 root 135:
136: //#define DEBUG_PREFETCH
137:
138: struct flag_struct regflags;
139:
140: /* Opcode of faulting instruction */
141: uae_u16 last_op_for_exception_3;
142: /* PC at fault time */
143: uaecptr last_addr_for_exception_3;
144: /* Address that generated the exception */
145: uaecptr last_fault_for_exception_3;
146:
147: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
148: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
149:
150: int movem_index1[256];
151: int movem_index2[256];
152: int movem_next[256];
153:
154: int fpp_movem_index1[256];
155: int fpp_movem_index2[256];
156: int fpp_movem_next[256];
157:
158: cpuop_func *cpufunctbl[65536];
159:
160: int OpcodeFamily;
161: int BusCyclePenalty = 0;
162:
163: #define COUNT_INSTRS 0
164:
165: #if COUNT_INSTRS
166: static unsigned long int instrcount[65536];
167: static uae_u16 opcodenums[65536];
168:
169: static int compfn (const void *el1, const void *el2)
170: {
171: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
172: }
173:
174: static char *icountfilename (void)
175: {
176: char *name = getenv ("INSNCOUNT");
177: if (name)
178: return name;
179: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
180: }
181:
182: void dump_counts (void)
183: {
184: FILE *f = fopen (icountfilename (), "w");
185: unsigned long int total;
186: int i;
187:
188: write_log ("Writing instruction count file...\n");
189: for (i = 0; i < 65536; i++) {
190: opcodenums[i] = i;
191: total += instrcount[i];
192: }
193: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
194:
195: fprintf (f, "Total: %lu\n", total);
196: for (i=0; i < 65536; i++) {
197: unsigned long int cnt = instrcount[opcodenums[i]];
198: struct instr *dp;
199: struct mnemolookup *lookup;
200: if (!cnt)
201: break;
202: dp = table68k + opcodenums[i];
203: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
204: ;
205: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
206: }
207: fclose (f);
208: }
209: #else
210: void dump_counts (void)
211: {
212: }
213: #endif
214:
215:
216: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
217:
218: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
219: {
220: op_illg (opcode);
221: return 4;
222: }
223:
224:
225: void build_cpufunctbl(void)
226: {
227: int i;
228: unsigned long opcode;
229: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
230: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
231: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
232: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
233: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
234: : op_smalltbl_5_ff);
235:
236: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
237: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
238:
239: for (opcode = 0; opcode < 65536; opcode++)
240: cpufunctbl[opcode] = op_illg_1;
241: for (i = 0; tbl[i].handler != NULL; i++) {
242: if (! tbl[i].specific)
243: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
244: }
245: for (opcode = 0; opcode < 65536; opcode++) {
246: cpuop_func *f;
247:
248: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
249: continue;
250:
251: if (table68k[opcode].handler != -1) {
252: f = cpufunctbl[table68k[opcode].handler];
253: if (f == op_illg_1)
254: abort();
255: cpufunctbl[opcode] = f;
256: }
257: }
258: for (i = 0; tbl[i].handler != NULL; i++) {
259: if (tbl[i].specific)
260: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
261: }
262: }
263:
264:
265:
266: void init_m68k (void)
267: {
268: int i;
269:
270: for (i = 0 ; i < 256 ; i++) {
271: int j;
272: for (j = 0 ; j < 8 ; j++) {
273: if (i & (1 << j)) break;
274: }
275: movem_index1[i] = j;
276: movem_index2[i] = 7-j;
277: movem_next[i] = i & (~(1 << j));
278: }
279: for (i = 0 ; i < 256 ; i++) {
280: int j;
281: for (j = 7 ; j >= 0 ; j--) {
282: if (i & (1 << j)) break;
283: }
284: fpp_movem_index1[i] = 7-j;
285: fpp_movem_index2[i] = j;
286: fpp_movem_next[i] = i & (~(1 << j));
287: }
288: #if COUNT_INSTRS
289: {
290: FILE *f = fopen (icountfilename (), "r");
291: memset (instrcount, 0, sizeof instrcount);
292: if (f) {
293: uae_u32 opcode, count, total;
294: char name[20];
295: write_log ("Reading instruction count file...\n");
296: fscanf (f, "Total: %lu\n", &total);
297: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
298: instrcount[opcode] = count;
299: }
300: fclose(f);
301: }
302: }
303: #endif
304: write_log ("Building CPU table for configuration: 68");
305: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
306: write_log ("EC");
307: switch (currprefs.cpu_level) {
308: case 1:
309: write_log ("010");
310: break;
311: case 2:
312: write_log ("020");
313: break;
314: case 3:
315: write_log ("020/881");
316: break;
317: case 4:
318: /* Who is going to miss the MMU anyway...? :-) */
319: write_log ("040");
320: break;
321: default:
322: write_log ("000");
323: break;
324: }
325: if (currprefs.cpu_compatible)
326: write_log (" (compatible mode)");
327: write_log ("\n");
328:
329: read_table68k ();
330: do_merges ();
331:
332: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
333:
334: build_cpufunctbl ();
335: }
336:
337:
338: /* not used ATM:
339: static struct regstruct regs_backup[16];
340: static int backup_pointer = 0;
341: struct regstruct lastint_regs;
342: int lastint_no;
343: */
344: struct regstruct regs;
345: static long int m68kpc_offset;
346:
347:
348: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
349: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
350: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
351:
352: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
353: {
354: uae_u16 dp;
355: uae_s8 disp8;
356: uae_s16 disp16;
357: int r;
358: uae_u32 dispreg;
359: uaecptr addr;
360: uae_s32 offset = 0;
361: char buffer[80];
362:
363: switch (mode){
364: case Dreg:
365: sprintf (buffer,"D%d", reg);
366: break;
367: case Areg:
368: sprintf (buffer,"A%d", reg);
369: break;
370: case Aind:
371: sprintf (buffer,"(A%d)", reg);
372: break;
373: case Aipi:
374: sprintf (buffer,"(A%d)+", reg);
375: break;
376: case Apdi:
377: sprintf (buffer,"-(A%d)", reg);
378: break;
379: case Ad16:
380: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
381: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
382: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
383: (unsigned long)addr);
384: break;
385: case Ad8r:
386: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
387: disp8 = dp & 0xFF;
388: r = (dp & 0x7000) >> 12;
389: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
390: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
391: dispreg <<= (dp >> 9) & 3;
392:
393: if (dp & 0x100) {
394: uae_s32 outer = 0, disp = 0;
395: uae_s32 base = m68k_areg(regs,reg);
396: char name[10];
397: sprintf (name,"A%d, ",reg);
398: if (dp & 0x80) { base = 0; name[0] = 0; }
399: if (dp & 0x40) dispreg = 0;
400: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
401: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
402: base += disp;
403:
404: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
405: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
406:
407: if (!(dp & 4)) base += dispreg;
408: if (dp & 3) base = get_long (base);
409: if (dp & 4) base += dispreg;
410:
411: addr = base + outer;
412: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
413: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
414: 1 << ((dp >> 9) & 3),
415: (long)disp, (long)outer, (unsigned long)addr);
416: } else {
417: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
418: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
419: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
420: 1 << ((dp >> 9) & 3), disp8,
421: (unsigned long)addr);
422: }
423: break;
424: case PC16:
425: addr = m68k_getpc () + m68kpc_offset;
426: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
427: addr += (uae_s16)disp16;
428: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
429: break;
430: case PC8r:
431: addr = m68k_getpc () + m68kpc_offset;
432: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
433: disp8 = dp & 0xFF;
434: r = (dp & 0x7000) >> 12;
435: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
436: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
437: dispreg <<= (dp >> 9) & 3;
438:
439: if (dp & 0x100) {
440: uae_s32 outer = 0,disp = 0;
441: uae_s32 base = addr;
442: char name[10];
443: sprintf (name,"PC, ");
444: if (dp & 0x80) { base = 0; name[0] = 0; }
445: if (dp & 0x40) dispreg = 0;
446: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
447: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
448: base += disp;
449:
450: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
451: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
452:
453: if (!(dp & 4)) base += dispreg;
454: if (dp & 3) base = get_long (base);
455: if (dp & 4) base += dispreg;
456:
457: addr = base + outer;
458: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
459: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
460: 1 << ((dp >> 9) & 3),
461: (long)disp, (long)outer, (unsigned long)addr);
462: } else {
463: addr += (uae_s32)((uae_s8)disp8) + dispreg;
464: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
465: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
466: disp8, (unsigned long)addr);
467: }
468: break;
469: case absw:
470: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
471: m68kpc_offset += 2;
472: break;
473: case absl:
474: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
475: m68kpc_offset += 4;
476: break;
477: case imm:
478: switch (size){
479: case sz_byte:
480: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
481: m68kpc_offset += 2;
482: break;
483: case sz_word:
484: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
485: m68kpc_offset += 2;
486: break;
487: case sz_long:
488: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
489: m68kpc_offset += 4;
490: break;
491: default:
492: break;
493: }
494: break;
495: case imm0:
496: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
497: m68kpc_offset += 2;
498: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
499: break;
500: case imm1:
501: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
502: m68kpc_offset += 2;
503: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
504: break;
505: case imm2:
506: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
507: m68kpc_offset += 4;
508: sprintf (buffer,"#$%08lx", (unsigned long)offset);
509: break;
510: case immi:
511: offset = (uae_s32)(uae_s8)(reg & 0xff);
512: sprintf (buffer,"#$%08lx", (unsigned long)offset);
513: break;
514: default:
515: break;
516: }
517: if (buf == 0)
518: fprintf (f, "%s", buffer);
519: else
520: strcat (buf, buffer);
521: return offset;
522: }
523:
524:
525: /* The plan is that this will take over the job of exception 3 handling -
526: * the CPU emulation functions will just do a longjmp to m68k_go whenever
527: * they hit an odd address. */
528: #if 0
529: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
530: {
531: uae_u16 dp;
532: uae_s8 disp8;
533: uae_s16 disp16;
534: int r;
535: uae_u32 dispreg;
536: uaecptr addr;
537: /*uae_s32 offset = 0;*/
538:
539: switch (mode){
540: case Dreg:
541: *val = m68k_dreg (regs, reg);
542: return 1;
543: case Areg:
544: *val = m68k_areg (regs, reg);
545: return 1;
546:
547: case Aind:
548: case Aipi:
549: addr = m68k_areg (regs, reg);
550: break;
551: case Apdi:
552: addr = m68k_areg (regs, reg);
553: break;
554: case Ad16:
555: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
556: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
557: break;
558: case Ad8r:
559: addr = m68k_areg (regs, reg);
560: d8r_common:
561: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
562: disp8 = dp & 0xFF;
563: r = (dp & 0x7000) >> 12;
564: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
565: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
566: dispreg <<= (dp >> 9) & 3;
567:
568: if (dp & 0x100) {
569: uae_s32 outer = 0, disp = 0;
570: uae_s32 base = addr;
571: if (dp & 0x80) base = 0;
572: if (dp & 0x40) dispreg = 0;
573: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
574: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
575: base += disp;
576:
577: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
578: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
579:
580: if (!(dp & 4)) base += dispreg;
581: if (dp & 3) base = get_long (base);
582: if (dp & 4) base += dispreg;
583:
584: addr = base + outer;
585: } else {
586: addr += (uae_s32)((uae_s8)disp8) + dispreg;
587: }
588: break;
589: case PC16:
590: addr = m68k_getpc () + m68kpc_offset;
591: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
592: addr += (uae_s16)disp16;
593: break;
594: case PC8r:
595: addr = m68k_getpc () + m68kpc_offset;
596: goto d8r_common;
597: case absw:
598: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
599: m68kpc_offset += 2;
600: break;
601: case absl:
602: addr = get_ilong_1 (m68kpc_offset);
603: m68kpc_offset += 4;
604: break;
605: case imm:
606: switch (size){
607: case sz_byte:
608: *val = get_iword_1 (m68kpc_offset) & 0xff;
609: m68kpc_offset += 2;
610: break;
611: case sz_word:
612: *val = get_iword_1 (m68kpc_offset) & 0xffff;
613: m68kpc_offset += 2;
614: break;
615: case sz_long:
616: *val = get_ilong_1 (m68kpc_offset);
617: m68kpc_offset += 4;
618: break;
619: default:
620: break;
621: }
622: return 1;
623: case imm0:
624: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
625: m68kpc_offset += 2;
626: return 1;
627: case imm1:
628: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
629: m68kpc_offset += 2;
630: return 1;
631: case imm2:
632: *val = get_ilong_1 (m68kpc_offset);
633: m68kpc_offset += 4;
634: return 1;
635: case immi:
636: *val = (uae_s32)(uae_s8)(reg & 0xff);
637: return 1;
638: default:
639: addr = 0;
640: break;
641: }
642: if ((addr & 1) == 0)
643: return 1;
644:
645: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
646: last_fault_for_exception_3 = addr;
647: return 0;
648: }
649: #endif
650:
651:
652: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
653: {
654: int reg = (dp >> 12) & 15;
655: uae_s32 regd = regs.regs[reg];
656: if ((dp & 0x800) == 0)
657: regd = (uae_s32)(uae_s16)regd;
658: regd <<= (dp >> 9) & 3;
659: if (dp & 0x100) {
660: uae_s32 outer = 0;
661: if (dp & 0x80) base = 0;
662: if (dp & 0x40) regd = 0;
663:
664: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
665: if ((dp & 0x30) == 0x30) base += next_ilong();
666:
667: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
668: if ((dp & 0x3) == 0x3) outer = next_ilong();
669:
670: if ((dp & 0x4) == 0) base += regd;
671: if (dp & 0x3) base = get_long (base);
672: if (dp & 0x4) base += regd;
673:
674: return base + outer;
675: } else {
676: return base + (uae_s32)((uae_s8)dp) + regd;
677: }
678: }
679:
680: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
681: {
682: int reg = (dp >> 12) & 15;
683: uae_s32 regd = regs.regs[reg];
684: #if 1
685: if ((dp & 0x800) == 0)
686: regd = (uae_s32)(uae_s16)regd;
687: return base + (uae_s8)dp + regd;
688: #else
689: /* Branch-free code... benchmark this again now that
690: * things are no longer inline. */
691: uae_s32 regd16;
692: uae_u32 mask;
693: mask = ((dp & 0x800) >> 11) - 1;
694: regd16 = (uae_s32)(uae_s16)regd;
695: regd16 &= mask;
696: mask = ~mask;
697: base += (uae_s8)dp;
698: regd &= mask;
699: regd |= regd16;
700: return base + regd;
701: #endif
702: }
703:
704:
705: /* Create the Status Register from the flags */
706: void MakeSR (void)
707: {
708: #if 0
709: assert((regs.t1 & 1) == regs.t1);
710: assert((regs.t0 & 1) == regs.t0);
711: assert((regs.s & 1) == regs.s);
712: assert((regs.m & 1) == regs.m);
713: assert((XFLG & 1) == XFLG);
714: assert((NFLG & 1) == NFLG);
715: assert((ZFLG & 1) == ZFLG);
716: assert((VFLG & 1) == VFLG);
717: assert((CFLG & 1) == CFLG);
718: #endif
719: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
720: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
721: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
722: | GET_CFLG);
723: }
724:
725:
726: /* Set up the flags from Status Register */
727: void MakeFromSR (void)
728: {
729: int oldm = regs.m;
730: int olds = regs.s;
731:
732: regs.t1 = (regs.sr >> 15) & 1;
733: regs.t0 = (regs.sr >> 14) & 1;
734: regs.s = (regs.sr >> 13) & 1;
735: regs.m = (regs.sr >> 12) & 1;
736: regs.intmask = (regs.sr >> 8) & 7;
737: SET_XFLG ((regs.sr >> 4) & 1);
738: SET_NFLG ((regs.sr >> 3) & 1);
739: SET_ZFLG ((regs.sr >> 2) & 1);
740: SET_VFLG ((regs.sr >> 1) & 1);
741: SET_CFLG (regs.sr & 1);
742: if (currprefs.cpu_level >= 2) {
743: if (olds != regs.s) {
744: if (olds) {
745: if (oldm)
746: regs.msp = m68k_areg(regs, 7);
747: else
748: regs.isp = m68k_areg(regs, 7);
749: m68k_areg(regs, 7) = regs.usp;
750: } else {
751: regs.usp = m68k_areg(regs, 7);
752: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
753: }
754: } else if (olds && oldm != regs.m) {
755: if (oldm) {
756: regs.msp = m68k_areg(regs, 7);
757: m68k_areg(regs, 7) = regs.isp;
758: } else {
759: regs.isp = m68k_areg(regs, 7);
760: m68k_areg(regs, 7) = regs.msp;
761: }
762: }
763: } else {
764: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
765: regs.t0 = 0;
766: regs.m = 0;
767:
768: if (olds != regs.s) {
769: if (olds) {
770: regs.isp = m68k_areg(regs, 7);
771: m68k_areg(regs, 7) = regs.usp;
772: } else {
773: regs.usp = m68k_areg(regs, 7);
774: m68k_areg(regs, 7) = regs.isp;
775: }
776: }
777: }
778:
779: /* Pending interrupts can occur again after a write to the SR: */
780: set_special (SPCFLAG_DOINT);
781: if (regs.t1 || regs.t0)
782: set_special (SPCFLAG_TRACE);
783: else
784: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
785: SR-modifying instructions (including STOP). */
786: unset_special (SPCFLAG_TRACE);
787: }
788:
789:
790: static void exception_trace (int nr)
791: {
792: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
793: if (regs.t1 && !regs.t0) {
794: /* trace stays pending if exception is div by zero, chk,
795: * trapv or trap #x
796: */
797: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
798: set_special (SPCFLAG_DOTRACE);
799: }
800: regs.t1 = regs.t0 = regs.m = 0;
801: }
802:
803:
804: /*
805: * Compute the number of jitter cycles to add when a video interrupt occurs
806: * (this is specific to the Atari ST)
807: */
808: static void InterruptAddJitter (int Level , int Pending)
809: {
810: }
811:
812:
813: /* Handle exceptions. We need a special case to handle MFP exceptions */
814: /* on Atari ST, because it's possible to change the MFP's vector base */
815: /* and get a conflict with 'normal' cpu exceptions. */
816: void Exception(int nr, uaecptr oldpc, int ExceptionSource)
817: {
1.1.1.2 ! root 818: uae_u32 currpc = m68k_getpc () , newpc;
1.1 root 819:
820: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
821:
822:
823: MakeSR();
824:
825: /* Change to supervisor mode if necessary */
826: if (!regs.s) {
827: regs.usp = m68k_areg(regs, 7);
828: if (currprefs.cpu_level >= 2)
829: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
830: else
831: m68k_areg(regs, 7) = regs.isp;
832: regs.s = 1;
833: }
834:
835: /* Build additional exception stack frame for 68010 and higher */
836: /* (special case for MFP) */
837: if (currprefs.cpu_level > 0) {
838: if (nr == 2 || nr == 3) {
839: int i;
840: /* @@@ this is probably wrong (?) */
841: for (i = 0 ; i < 12 ; i++) {
842: m68k_areg(regs, 7) -= 2;
843: put_word (m68k_areg(regs, 7), 0);
844: }
845: m68k_areg(regs, 7) -= 2;
846: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
847: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
848: m68k_areg(regs, 7) -= 4;
849: put_long (m68k_areg(regs, 7), oldpc);
850: m68k_areg(regs, 7) -= 2;
851: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
852: } else if (regs.m && nr >= 24 && nr < 32) {
853: m68k_areg(regs, 7) -= 2;
854: put_word (m68k_areg(regs, 7), nr * 4);
855: m68k_areg(regs, 7) -= 4;
856: put_long (m68k_areg(regs, 7), currpc);
857: m68k_areg(regs, 7) -= 2;
858: put_word (m68k_areg(regs, 7), regs.sr);
859: regs.sr |= (1 << 13);
860: regs.msp = m68k_areg(regs, 7);
861: m68k_areg(regs, 7) = regs.isp;
862: m68k_areg(regs, 7) -= 2;
863: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
864: } else {
865: m68k_areg(regs, 7) -= 2;
866: put_word (m68k_areg(regs, 7), nr * 4);
867: }
868: }
869:
870: /* Push PC on stack: */
871: m68k_areg(regs, 7) -= 4;
872: put_long (m68k_areg(regs, 7), currpc);
873: /* Push SR on stack: */
874: m68k_areg(regs, 7) -= 2;
875: put_word (m68k_areg(regs, 7), regs.sr);
876:
877: LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n",
878: nr, currpc, BusErrorPC, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3);
879:
880: /* 68000 bus/address errors: */
881: if (currprefs.cpu_level==0 && (nr==2 || nr==3) && ExceptionSource == M68000_EXC_SRC_CPU) {
882: uae_u16 specialstatus = 1;
883:
884: /* Special status word emulation isn't perfect yet... :-( */
885: if (regs.sr & 0x2000)
886: specialstatus |= 0x4;
887: m68k_areg(regs, 7) -= 8;
888: if (nr == 3) { /* Address error */
889: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
890: put_word (m68k_areg(regs, 7), specialstatus);
891: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
892: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
893: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
894: if (bExceptionDebugging) {
895: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
896: DebugUI();
897: }
898: }
899: else { /* Bus error */
900: specialstatus |= ( get_word(BusErrorPC) & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
901: if (bBusErrorReadWrite)
902: specialstatus |= 0x10;
903: put_word (m68k_areg(regs, 7), specialstatus);
904: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
905: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
906:
907: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
908: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
909: if ( get_word(BusErrorPC) == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
910: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
911: /* Check for double bus errors: */
912: if (regs.spcflags & SPCFLAG_BUSERROR) {
913: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
914: BusErrorAddress, (long)currpc);
915: unset_special(SPCFLAG_BUSERROR);
916: if (bExceptionDebugging)
917: DebugUI();
918: else
1.1.1.2 ! root 919: DlgAlert_Notice("Detected double bus error => CPU halted!\nEmulation needs to be reset.\n");
1.1 root 920: regs.intmask = 7;
921: m68k_setstopped(true);
922: return;
923: }
924: if (bExceptionDebugging && BusErrorAddress!=0xff8a00) {
925: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
926: DebugUI();
927: }
928: }
929: }
930:
931: /* Set PC and flags */
932: if (bExceptionDebugging && get_long (regs.vbr + 4*nr) == 0) {
933: write_log("Uninitialized exception handler #%i!\n", nr);
934: DebugUI();
935: }
1.1.1.2 ! root 936: newpc = get_long (regs.vbr + 4*nr);
! 937: if ( newpc & 1) /* check new pc is even */
! 938: {
! 939: if ( nr==2 || nr==3 ) /* address error during bus/address error -> stop emulation */
! 940: {
! 941: fprintf(stderr,"Address Error during exception 2/3, aborting new PC=$%x\n",newpc);
! 942: DebugUI();
! 943: }
! 944: else
! 945: {
! 946: fprintf(stderr,"Address Error during exception, new PC=$%x\n",newpc);
! 947: Exception ( 3 , m68k_getpc() , M68000_EXC_SRC_CPU );
! 948: }
! 949: return;
! 950: }
! 951:
1.1 root 952: m68k_setpc (get_long (regs.vbr + 4*nr));
953: fill_prefetch_0 ();
954: /* Handle trace flags depending on current state */
955: exception_trace (nr);
956:
957: /* Handle exception cycles (special case for MFP) */
958: if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
959: {
960: M68000_AddCycles(44+12); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
961: }
962: else if (nr >= 24 && nr <= 31)
963: {
964: if ( nr == 26 ) /* HBL */
965: {
966: /* store current cycle pos when then interrupt was received (see video.c) */
967: // LastCycleHblException = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);
968: M68000_AddCycles(44+12); /* Video Interrupt */
969: }
970: else if ( nr == 28 ) /* VBL */
971: M68000_AddCycles(44+12); /* Video Interrupt */
972: else
973: M68000_AddCycles(44+4); /* Other Interrupts */
974: }
975: else if(nr >= 32 && nr <= 47)
976: {
977: M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */
978: }
979: else switch(nr)
980: {
981: case 2: M68000_AddCycles(50); break; /* Bus error */
982: case 3: M68000_AddCycles(50); break; /* Address error */
983: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
984: case 5: M68000_AddCycles(38); break; /* Div by zero */
985: case 6: M68000_AddCycles(40); break; /* CHK */
986: case 7: M68000_AddCycles(34); break; /* TRAPV */
987: case 8: M68000_AddCycles(34); break; /* Privilege violation */
988: case 9: M68000_AddCycles(34); break; /* Trace */
989: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
990: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
991: default:
992: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
993: if(nr < 64)
994: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
995: else
996: M68000_AddCycles(44+12); /* Must be a MFP or DSP interrupt */
997: break;
998: }
999:
1000: }
1001:
1002:
1003: static void Interrupt(int nr , int Pending)
1004: {
1005: assert(nr < 8 && nr >= 0);
1006: /*lastint_regs = regs;*/
1007: /*lastint_no = nr;*/
1008:
1009: /* On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */
1010: Exception(nr+24, 0, M68000_EXC_SRC_AUTOVEC);
1011:
1012: regs.intmask = nr;
1013: set_special (SPCFLAG_INT);
1014:
1015: /* Handle Atari ST's specific jitter for hbl/vbl */
1016: InterruptAddJitter ( nr , Pending );
1017: }
1018:
1019:
1020: uae_u32 caar, cacr;
1021: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1022:
1023:
1024: static int movec_illg (int regno)
1025: {
1026: int regno2 = regno & 0x7ff;
1027: if (currprefs.cpu_level == 1) { /* 68010 */
1028: if (regno2 < 2)
1029: return 0;
1030: return 1;
1031: }
1032: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
1033: if (regno == 3) return 1; /* 68040 only */
1034: /* 4 is >=68040, but 0x804 is in 68020 */
1035: if (regno2 < 4 || regno == 0x804)
1036: return 0;
1037: return 1;
1038: }
1039: if (currprefs.cpu_level >= 4) { /* 68040 */
1040: if (regno == 0x802) return 1; /* 68020 only */
1041: if (regno2 < 8) return 0;
1042: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
1043: return 0;
1044: return 1;
1045: }
1046: return 1;
1047: }
1048:
1049: int m68k_move2c (int regno, uae_u32 *regp)
1050: {
1051: if (movec_illg (regno)) {
1052: op_illg (0x4E7B);
1053: return 0;
1054: } else {
1055: switch (regno) {
1056: case 0: regs.sfc = *regp & 7; break;
1057: case 1: regs.dfc = *regp & 7; break;
1058: case 2:
1059: {
1060: uae_u32 cacr_mask = 0;
1061: if (currprefs.cpu_level == 2) // 68020
1062: cacr_mask = 0x0000000f;
1063: else if (currprefs.cpu_level == 3) // Fake 68030
1064: cacr_mask = 0x00003f1f;
1065: else if (currprefs.cpu_level == 4) // 68040
1066: cacr_mask = 0x80008000;
1067: cacr = *regp & cacr_mask;
1068: }
1069: case 3: tc = *regp & 0xc000; break;
1070: /* Mask out fields that should be zero. */
1071: case 4: itt0 = *regp & 0xffffe364; break;
1072: case 5: itt1 = *regp & 0xffffe364; break;
1073: case 6: dtt0 = *regp & 0xffffe364; break;
1074: case 7: dtt1 = *regp & 0xffffe364; break;
1075:
1076: case 0x800: regs.usp = *regp; break;
1077: case 0x801: regs.vbr = *regp; break;
1078: case 0x802: caar = *regp & 0xfc; break;
1079: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
1080: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1081: case 0x805: mmusr = *regp; break;
1082: case 0x806: urp = *regp; break;
1083: case 0x807: srp = *regp; break;
1084: default:
1085: op_illg (0x4E7B);
1086: return 0;
1087: }
1088: }
1089: return 1;
1090: }
1091:
1092: int m68k_movec2 (int regno, uae_u32 *regp)
1093: {
1094: if (movec_illg (regno)) {
1095: op_illg (0x4E7A);
1096: return 0;
1097: } else {
1098: switch (regno) {
1099: case 0: *regp = regs.sfc; break;
1100: case 1: *regp = regs.dfc; break;
1101: case 2: *regp = cacr; break;
1102: case 3: *regp = tc; break;
1103: case 4: *regp = itt0; break;
1104: case 5: *regp = itt1; break;
1105: case 6: *regp = dtt0; break;
1106: case 7: *regp = dtt1; break;
1107: case 0x800: *regp = regs.usp; break;
1108: case 0x801: *regp = regs.vbr; break;
1109: case 0x802: *regp = caar; break;
1110: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1111: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1112: case 0x805: *regp = mmusr; break;
1113: case 0x806: *regp = urp; break;
1114: case 0x807: *regp = srp; break;
1115: default:
1116: op_illg (0x4E7A);
1117: return 0;
1118: }
1119: }
1120: return 1;
1121: }
1122:
1123: STATIC_INLINE int
1124: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1125: {
1126: uae_u32 q = 0, cbit = 0;
1127: int i;
1128:
1129: if (ndiv <= src_hi) {
1130: return 1;
1131: }
1132: for (i = 0 ; i < 32 ; i++) {
1133: cbit = src_hi & 0x80000000ul;
1134: src_hi <<= 1;
1135: if (src_lo & 0x80000000ul) src_hi++;
1136: src_lo <<= 1;
1137: q = q << 1;
1138: if (cbit || ndiv <= src_hi) {
1139: q |= 1;
1140: src_hi -= ndiv;
1141: }
1142: }
1143: *quot = q;
1144: *rem = src_hi;
1145: return 0;
1146: }
1147:
1148: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1149: {
1150: #if defined(uae_s64)
1151: if (src == 0) {
1152: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1153: return;
1154: }
1155: if (extra & 0x800) {
1156: /* signed variant */
1157: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1158: uae_s64 quot, rem;
1159:
1160: if (extra & 0x400) {
1161: a &= 0xffffffffu;
1162: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1163: }
1164: rem = a % (uae_s64)(uae_s32)src;
1165: quot = a / (uae_s64)(uae_s32)src;
1166: if ((quot & UVAL64(0xffffffff80000000)) != 0
1167: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1168: {
1169: SET_VFLG (1);
1170: SET_NFLG (1);
1171: SET_CFLG (0);
1172: } else {
1173: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1174: SET_VFLG (0);
1175: SET_CFLG (0);
1176: SET_ZFLG (((uae_s32)quot) == 0);
1177: SET_NFLG (((uae_s32)quot) < 0);
1178: m68k_dreg(regs, extra & 7) = rem;
1179: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1180: }
1181: } else {
1182: /* unsigned */
1183: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1184: uae_u64 quot, rem;
1185:
1186: if (extra & 0x400) {
1187: a &= 0xffffffffu;
1188: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1189: }
1190: rem = a % (uae_u64)src;
1191: quot = a / (uae_u64)src;
1192: if (quot > 0xffffffffu) {
1193: SET_VFLG (1);
1194: SET_NFLG (1);
1195: SET_CFLG (0);
1196: } else {
1197: SET_VFLG (0);
1198: SET_CFLG (0);
1199: SET_ZFLG (((uae_s32)quot) == 0);
1200: SET_NFLG (((uae_s32)quot) < 0);
1201: m68k_dreg(regs, extra & 7) = rem;
1202: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1203: }
1204: }
1205: #else
1206: if (src == 0) {
1207: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1208: return;
1209: }
1210: if (extra & 0x800) {
1211: /* signed variant */
1212: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1213: uae_s32 hi = lo < 0 ? -1 : 0;
1214: uae_s32 save_high;
1215: uae_u32 quot, rem;
1216: uae_u32 sign;
1217:
1218: if (extra & 0x400) {
1219: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1220: }
1221: save_high = hi;
1222: sign = (hi ^ src);
1223: if (hi < 0) {
1224: hi = ~hi;
1225: lo = -lo;
1226: if (lo == 0) hi++;
1227: }
1228: if ((uae_s32)src < 0) src = -src;
1229: if (div_unsigned(hi, lo, src, ", &rem) ||
1230: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1231: SET_VFLG (1);
1232: SET_NFLG (1);
1233: SET_CFLG (0);
1234: } else {
1235: if (sign & 0x80000000) quot = -quot;
1236: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1237: SET_VFLG (0);
1238: SET_CFLG (0);
1239: SET_ZFLG (((uae_s32)quot) == 0);
1240: SET_NFLG (((uae_s32)quot) < 0);
1241: m68k_dreg(regs, extra & 7) = rem;
1242: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1243: }
1244: } else {
1245: /* unsigned */
1246: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1247: uae_u32 hi = 0;
1248: uae_u32 quot, rem;
1249:
1250: if (extra & 0x400) {
1251: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1252: }
1253: if (div_unsigned(hi, lo, src, ", &rem)) {
1254: SET_VFLG (1);
1255: SET_NFLG (1);
1256: SET_CFLG (0);
1257: } else {
1258: SET_VFLG (0);
1259: SET_CFLG (0);
1260: SET_ZFLG (((uae_s32)quot) == 0);
1261: SET_NFLG (((uae_s32)quot) < 0);
1262: m68k_dreg(regs, extra & 7) = rem;
1263: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1264: }
1265: }
1266: #endif
1267: }
1268:
1269: STATIC_INLINE void
1270: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1271: {
1272: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1273: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1274: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1275: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1276: uae_u32 lo;
1277:
1278: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1279: if (lo < r0) r3++;
1280: r0 = lo;
1281: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1282: if (lo < r0) r3++;
1283: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1284: *dst_lo = lo;
1285: *dst_hi = r3;
1286: }
1287:
1288: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1289: {
1290: #if defined(uae_s64)
1291: if (extra & 0x800) {
1292: /* signed variant */
1293: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1294:
1295: a *= (uae_s64)(uae_s32)src;
1296: SET_VFLG (0);
1297: SET_CFLG (0);
1298: SET_ZFLG (a == 0);
1299: SET_NFLG (a < 0);
1300: if (extra & 0x400)
1301: m68k_dreg(regs, extra & 7) = a >> 32;
1302: else if ((a & UVAL64(0xffffffff80000000)) != 0
1303: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1304: {
1305: SET_VFLG (1);
1306: }
1307: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1308: } else {
1309: /* unsigned */
1310: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1311:
1312: a *= (uae_u64)src;
1313: SET_VFLG (0);
1314: SET_CFLG (0);
1315: SET_ZFLG (a == 0);
1316: SET_NFLG (((uae_s64)a) < 0);
1317: if (extra & 0x400)
1318: m68k_dreg(regs, extra & 7) = a >> 32;
1319: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1320: SET_VFLG (1);
1321: }
1322: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1323: }
1324: #else
1325: if (extra & 0x800) {
1326: /* signed variant */
1327: uae_s32 src1,src2;
1328: uae_u32 dst_lo,dst_hi;
1329: uae_u32 sign;
1330:
1331: src1 = (uae_s32)src;
1332: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1333: sign = (src1 ^ src2);
1334: if (src1 < 0) src1 = -src1;
1335: if (src2 < 0) src2 = -src2;
1336: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1337: if (sign & 0x80000000) {
1338: dst_hi = ~dst_hi;
1339: dst_lo = -dst_lo;
1340: if (dst_lo == 0) dst_hi++;
1341: }
1342: SET_VFLG (0);
1343: SET_CFLG (0);
1344: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1345: SET_NFLG (((uae_s32)dst_hi) < 0);
1346: if (extra & 0x400)
1347: m68k_dreg(regs, extra & 7) = dst_hi;
1348: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1349: && ((dst_hi & 0xffffffff) != 0xffffffff
1350: || (dst_lo & 0x80000000) != 0x80000000))
1351: {
1352: SET_VFLG (1);
1353: }
1354: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1355: } else {
1356: /* unsigned */
1357: uae_u32 dst_lo,dst_hi;
1358:
1359: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1360:
1361: SET_VFLG (0);
1362: SET_CFLG (0);
1363: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1364: SET_NFLG (((uae_s32)dst_hi) < 0);
1365: if (extra & 0x400)
1366: m68k_dreg(regs, extra & 7) = dst_hi;
1367: else if (dst_hi != 0) {
1368: SET_VFLG (1);
1369: }
1370: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1371: }
1372: #endif
1373: }
1374:
1375:
1376: void m68k_reset (void)
1377: {
1378: regs.s = 1;
1379: regs.m = 0;
1380: regs.stopped = 0;
1381: regs.t1 = 0;
1382: regs.t0 = 0;
1383: SET_ZFLG (0);
1384: SET_XFLG (0);
1385: SET_CFLG (0);
1386: SET_VFLG (0);
1387: SET_NFLG (0);
1388: regs.spcflags &= ( SPCFLAG_MODE_CHANGE | SPCFLAG_DEBUGGER ); /* Clear specialflags except mode-change and debugger */
1389: regs.intmask = 7;
1390: regs.vbr = regs.sfc = regs.dfc = 0;
1391: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1392:
1393: m68k_areg(regs, 7) = get_long(0);
1394: m68k_setpc(get_long(4));
1395: refill_prefetch (m68k_getpc(), 0);
1396: }
1397:
1398:
1399: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1400: {
1401: #if 0
1402: uaecptr pc = m68k_getpc ();
1403: #endif
1404: if ((opcode & 0xF000) == 0xF000) {
1405: Exception(0xB,0,M68000_EXC_SRC_CPU);
1406: return 4;
1407: }
1408: if ((opcode & 0xF000) == 0xA000) {
1409: Exception(0xA,0,M68000_EXC_SRC_CPU);
1410: return 4;
1411: }
1412: #if 0
1413: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1414: #endif
1415: Exception (4,0,M68000_EXC_SRC_CPU);
1416: return 4;
1417: }
1418:
1419:
1420: void mmu_op(uae_u32 opcode, uae_u16 extra)
1421: {
1422: if ((opcode & 0xFE0) == 0x0500) {
1423: /* PFLUSH */
1424: mmusr = 0;
1425: write_log ("PFLUSH\n");
1426: } else if ((opcode & 0x0FD8) == 0x548) {
1427: /* PTEST */
1428: write_log ("PTEST\n");
1429: } else
1430: op_illg (opcode);
1431: }
1432:
1433:
1434: static uaecptr last_trace_ad = 0;
1435:
1436: static void do_trace (void)
1437: {
1438: if (regs.t0 && currprefs.cpu_level >= 2) {
1439: uae_u16 opcode;
1440: /* should also include TRAP, CHK, SR modification FPcc */
1441: /* probably never used so why bother */
1442: /* We can afford this to be inefficient... */
1443: m68k_setpc (m68k_getpc ());
1444: fill_prefetch_0 ();
1445: opcode = get_word (regs.pc);
1446: if (opcode == 0x4e72 /* RTE */
1447: || opcode == 0x4e74 /* RTD */
1448: || opcode == 0x4e75 /* RTS */
1449: || opcode == 0x4e77 /* RTR */
1450: || opcode == 0x4e76 /* TRAPV */
1451: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1452: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1453: || (opcode & 0xff00) == 0x6100 /* BSR */
1454: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1455: && cctrue((opcode >> 8) & 0xf))
1456: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1457: && !cctrue((opcode >> 8) & 0xf)
1458: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1459: {
1460: last_trace_ad = m68k_getpc ();
1461: unset_special (SPCFLAG_TRACE);
1462: set_special (SPCFLAG_DOTRACE);
1463: }
1464: } else if (regs.t1) {
1465: last_trace_ad = m68k_getpc ();
1466: unset_special (SPCFLAG_TRACE);
1467: set_special (SPCFLAG_DOTRACE);
1468: }
1469: }
1470:
1471:
1472: /*
1473: * Handle special flags
1474: */
1475:
1476: static bool do_specialties_interrupt (int Pending)
1477: {
1478: return false; /* no interrupt was found */
1479: }
1480:
1481:
1482: static int do_specialties (void)
1483: {
1484: if(regs.spcflags & SPCFLAG_BUSERROR) {
1485: /* We can not execute bus errors directly in the memory handler
1486: * functions since the PC should point to the address of the next
1487: * instruction, so we're executing the bus errors here: */
1488: unset_special(SPCFLAG_BUSERROR);
1489: Exception(2,0,M68000_EXC_SRC_CPU);
1490: }
1491:
1492: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1493: /* Add some extra cycles to simulate a wait state */
1494: unset_special(SPCFLAG_EXTRA_CYCLES);
1495: M68000_AddCycles(nWaitStateCycles);
1496: nWaitStateCycles = 0;
1497: }
1498:
1499: if (regs.spcflags & SPCFLAG_DOTRACE) {
1500: Exception (9,last_trace_ad,M68000_EXC_SRC_CPU);
1501: }
1502:
1503:
1504: /* Handle the STOP instruction */
1505: if ( regs.spcflags & SPCFLAG_STOP ) {
1506: /* We first test if there's a pending interrupt that would */
1507: /* allow to immediatly leave the STOP state */
1508: if ( do_specialties_interrupt(true) ) { /* test if there's an interrupt and add pending jitter */
1509: regs.stopped = 0;
1510: unset_special (SPCFLAG_STOP);
1511: }
1512:
1513: /* No pending int, we have to wait for the next matching int */
1514: while (regs.spcflags & SPCFLAG_STOP) {
1515:
1516: /* Take care of quit event if needed */
1517: if (regs.spcflags & SPCFLAG_BRK)
1518: return 1;
1519:
1520: M68000_AddCycles(4);
1521:
1522: /* It is possible one or more ints happen at the same time */
1523: /* We must process them during the same cpu cycle until the special INT flag is set */
1524: while (PendingInterruptCount<=0 && PendingInterruptFunction) {
1525: /* 1st, we call the interrupt handler */
1526: CALL_VAR(PendingInterruptFunction);
1527:
1528: /* Then we check if this handler triggered an interrupt to process */
1529: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1530: regs.stopped = 0;
1531: unset_special (SPCFLAG_STOP);
1532: break;
1533: }
1534: }
1535: }
1536: }
1537:
1538:
1539: if (regs.spcflags & SPCFLAG_TRACE)
1540: do_trace ();
1541:
1542: // if (regs.spcflags & SPCFLAG_DOINT) {
1543: /* [NP] pending int should be processed now, not after the current instr */
1544: /* so we check for (SPCFLAG_INT | SPCFLAG_DOINT), not just for SPCFLAG_DOINT */
1545:
1546: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1547: regs.stopped = 0; /* [NP] useless ? */
1548: }
1549: if (regs.spcflags & SPCFLAG_INT) {
1550: unset_special (SPCFLAG_INT);
1551: set_special (SPCFLAG_DOINT);
1552: }
1553:
1554: if (regs.spcflags & SPCFLAG_DEBUGGER)
1555: DebugCpu_Check();
1556:
1557: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1558: unset_special(SPCFLAG_MODE_CHANGE);
1559: return 1;
1560: }
1561:
1562: return 0;
1563: }
1564:
1565:
1566: /* It's really sad to have two almost identical functions for this, but we
1567: do it all for performance... :( */
1568: static void m68k_run_1 (void)
1569: {
1570: #ifdef DEBUG_PREFETCH
1571: uae_u8 saved_bytes[20];
1572: uae_u16 *oldpcp;
1573: #endif
1574:
1575: for (;;) {
1576: int cycles;
1577: uae_u32 opcode = get_iword_prefetch (0);
1578:
1579: #ifdef DEBUG_PREFETCH
1580: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1581: fprintf (stderr, "Prefetch differs from memory.\n");
1582: debugging = 1;
1583: return;
1584: }
1585: oldpcp = regs.pc_p;
1586: memcpy (saved_bytes, regs.pc_p, 20);
1587: #endif
1588:
1589: /*m68k_dumpstate(stderr, NULL);*/
1590: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1591: {
1592: int FrameCycles, HblCounterVideo, LineCycles;
1593:
1594: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1595:
1596: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.2 ! root 1597: Disasm(stderr, m68k_getpc (), NULL, 1, DISASM_ENGINE_EXT);
1.1 root 1598: }
1599:
1600: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1601: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1602: #if COUNT_INSTRS == 2
1603: if (table68k[opcode].handler != -1)
1604: instrcount[table68k[opcode].handler]++;
1605: #elif COUNT_INSTRS == 1
1606: instrcount[opcode]++;
1607: #endif
1608:
1609: /* In case of a Bus Error, we need the PC of the instruction that caused */
1610: /* the error to build the exception stack frame */
1611: BusErrorPC = m68k_getpc();
1612:
1613: cycles = (*cpufunctbl[opcode])(opcode);
1614:
1615: #ifdef DEBUG_PREFETCH
1616: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1617: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1618: set_special (SPCFLAG_BRK);
1619: debugging = 1;
1620: }
1621: #endif
1622:
1623:
1624: M68000_AddCyclesWithPairing(cycles);
1625: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1626: /* Add some extra cycles to simulate a wait state */
1627: unset_special(SPCFLAG_EXTRA_CYCLES);
1628: M68000_AddCycles(nWaitStateCycles);
1629: nWaitStateCycles = 0;
1630: }
1631:
1632: #if 0
1633: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1634: CALL_VAR(PendingInterruptFunction);
1635: #else
1636: /* We can have several interrupts at the same time before the next CPU instruction */
1637: /* We must check for pending interrupt and call do_specialties_interrupt() only */
1638: /* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
1639: /* and prevent exiting the STOP state when calling do_specialties() after. */
1640: /* For performance, we first test PendingInterruptCount, then regs.spcflags */
1641: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
1642: {
1643: CALL_VAR(PendingInterruptFunction); /* call the interrupt handler */
1644: do_specialties_interrupt(false); /* test if there's an mfp/video interrupt and add non pending jitter */
1645: #if 0
1646: if ( regs.spcflags & ( SPCFLAG_MFP | SPCFLAG_INT ) ) { /* only check mfp/video interrupts */
1647: if (do_specialties ()) /* check if this latest int has higher priority */
1648: return;
1649: }
1650: #endif
1651: }
1652: #endif
1653:
1654: if (regs.spcflags) {
1655: if (do_specialties ())
1656: return;
1657: }
1658:
1659: }
1660: }
1661:
1662:
1663: /* Same thing, but don't use prefetch to get opcode. */
1664: static void m68k_run_2 (void)
1665: {
1666: for (;;) {
1667: int cycles;
1668: uae_u32 opcode = get_iword (0);
1669:
1670: /*m68k_dumpstate(stderr, NULL);*/
1671: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1672: {
1673: int FrameCycles, HblCounterVideo, LineCycles;
1674:
1675: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1676:
1677: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.2 ! root 1678: Disasm(stderr, m68k_getpc (), NULL, 1, DISASM_ENGINE_EXT);
1.1 root 1679: }
1680:
1681: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1682: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1683: #if COUNT_INSTRS == 2
1684: if (table68k[opcode].handler != -1)
1685: instrcount[table68k[opcode].handler]++;
1686: #elif COUNT_INSTRS == 1
1687: instrcount[opcode]++;
1688: #endif
1689:
1.1.1.2 ! root 1690: /* In case of a Bus Error, we need the PC of the instruction that caused */
! 1691: /* the error to build the exception stack frame */
! 1692: BusErrorPC = m68k_getpc();
! 1693:
1.1 root 1694: cycles = (*cpufunctbl[opcode])(opcode);
1695:
1696:
1697: M68000_AddCycles(cycles);
1698: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1699: /* Add some extra cycles to simulate a wait state */
1700: unset_special(SPCFLAG_EXTRA_CYCLES);
1701: M68000_AddCycles(nWaitStateCycles);
1702: nWaitStateCycles = 0;
1703: }
1704:
1705: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1706: CALL_VAR(PendingInterruptFunction);
1707:
1708: if (regs.spcflags) {
1709: if (do_specialties ())
1710: return;
1711: }
1712:
1713: }
1714: }
1715:
1716:
1717: void m68k_go (int may_quit)
1718: {
1719: static int in_m68k_go = 0;
1720:
1721: if (in_m68k_go || !may_quit) {
1722: write_log ("Bug! m68k_go is not reentrant.\n");
1723: abort ();
1724: }
1725:
1726: in_m68k_go++;
1727: while (!(regs.spcflags & SPCFLAG_BRK)) {
1728: if(currprefs.cpu_compatible)
1729: m68k_run_1();
1730: else
1731: m68k_run_2();
1732: }
1733: unset_special(SPCFLAG_BRK);
1734: in_m68k_go--;
1735: }
1736:
1737:
1738: /*
1739: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1740: {
1741: uae_u32 opcode, val;
1742: struct instr *dp;
1743:
1744: opcode = get_iword_1(0);
1745: last_op_for_exception_3 = opcode;
1746: m68kpc_offset = 2;
1747:
1748: if (cpufunctbl[opcode] == op_illg_1) {
1749: opcode = 0x4AFC;
1750: }
1751: dp = table68k + opcode;
1752:
1753: if (dp->suse) {
1754: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1755: Exception (3, 0,M68000_EXC_SRC_CPU);
1756: return;
1757: }
1758: }
1759: if (dp->duse) {
1760: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1761: Exception (3, 0,M68000_EXC_SRC_CPU);
1762: return;
1763: }
1764: }
1765: }
1766: */
1767:
1768:
1769: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1770: {
1771: static const char * const ccnames[] =
1772: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1773: "VC","VS","PL","MI","GE","LT","GT","LE" };
1774:
1775: uaecptr newpc = 0;
1776: m68kpc_offset = addr - m68k_getpc ();
1777: while (cnt-- > 0) {
1778: char instrname[20],*ccpt;
1779: int opwords;
1780: uae_u32 opcode;
1781: const struct mnemolookup *lookup;
1782: struct instr *dp;
1783: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1784: for (opwords = 0; opwords < 5; opwords++){
1785: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1786: }
1787: opcode = get_iword_1 (m68kpc_offset);
1788: m68kpc_offset += 2;
1789: if (cpufunctbl[opcode] == op_illg_1) {
1790: opcode = 0x4AFC;
1791: }
1792: dp = table68k + opcode;
1793: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1794: ;
1795:
1796: strcpy (instrname, lookup->name);
1797: ccpt = strstr (instrname, "cc");
1798: if (ccpt != 0) {
1799: strncpy (ccpt, ccnames[dp->cc], 2);
1800: }
1801: fprintf (f, "%s", instrname);
1802: switch (dp->size){
1803: case sz_byte: fprintf (f, ".B "); break;
1804: case sz_word: fprintf (f, ".W "); break;
1805: case sz_long: fprintf (f, ".L "); break;
1806: default: fprintf (f, " "); break;
1807: }
1808:
1809: if (dp->suse) {
1810: newpc = m68k_getpc () + m68kpc_offset;
1811: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1812: }
1813: if (dp->suse && dp->duse)
1814: fprintf (f, ",");
1815: if (dp->duse) {
1816: newpc = m68k_getpc () + m68kpc_offset;
1817: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1818: }
1819: if (ccpt != 0) {
1820: if (cctrue(dp->cc))
1821: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1822: else
1823: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1824: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1825: fprintf (f, " == %08lx", (long)newpc);
1826: fprintf (f, "\n");
1827: }
1828: if (nextpc)
1829: *nextpc = m68k_getpc () + m68kpc_offset;
1830: }
1831:
1832: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1833: {
1834: int i;
1835: for (i = 0; i < 8; i++){
1836: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1837: if ((i & 3) == 3) fprintf (f, "\n");
1838: }
1839: for (i = 0; i < 8; i++){
1840: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1841: if ((i & 3) == 3) fprintf (f, "\n");
1842: }
1843: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1844: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1845: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1846: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1847: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1848: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1849: regs.t1, regs.t0, regs.s, regs.m,
1850: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1851: for (i = 0; i < 8; i++){
1852: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1853: if ((i & 3) == 3) fprintf (f, "\n");
1854: }
1855: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1856: (regs.fpsr & 0x8000000) != 0,
1857: (regs.fpsr & 0x4000000) != 0,
1858: (regs.fpsr & 0x2000000) != 0,
1859: (regs.fpsr & 0x1000000) != 0);
1860: if (currprefs.cpu_compatible)
1861: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1862:
1863: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1864: if (nextpc)
1865: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1866: }
1867:
1868:
1869: /*
1870:
1871: The routines below take dividend and divisor as parameters.
1872: They return 0 if division by zero, or exact number of cycles otherwise.
1873:
1874: The number of cycles returned assumes a register operand.
1875: Effective address time must be added if memory operand.
1876:
1877: For 68000 only (not 68010, 68012, 68020, etc).
1878: Probably valid for 68008 after adding the extra prefetch cycle.
1879:
1880:
1881: Best and worst cases are for register operand:
1882: (Note the difference with the documented range.)
1883:
1884:
1885: DIVU:
1886:
1887: Overflow (always): 10 cycles.
1888: Worst case: 136 cycles.
1889: Best case: 76 cycles.
1890:
1891:
1892: DIVS:
1893:
1894: Absolute overflow: 16-18 cycles.
1895: Signed overflow is not detected prematurely.
1896:
1897: Worst case: 156 cycles.
1898: Best case without signed overflow: 122 cycles.
1899: Best case with signed overflow: 120 cycles
1900:
1901:
1902: */
1903:
1904:
1905: //
1906: // DIVU
1907: // Unsigned division
1908: //
1909:
1910: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
1911: {
1912: int mcycles;
1913: uae_u32 hdivisor;
1914: int i;
1915:
1916: if (divisor == 0)
1917: return 0;
1918:
1919: // Overflow
1920: if ((dividend >> 16) >= divisor)
1921: return (mcycles = 5) * 2;
1922:
1923: mcycles = 38;
1924: hdivisor = divisor << 16;
1925:
1926: for (i = 0; i < 15; i++) {
1927: uae_u32 temp;
1928: temp = dividend;
1929:
1930: dividend <<= 1;
1931:
1932: // If carry from shift
1933: if ((uae_s32)temp < 0)
1934: dividend -= hdivisor;
1935: else {
1936: mcycles += 2;
1937: if (dividend >= hdivisor) {
1938: dividend -= hdivisor;
1939: mcycles--;
1940: }
1941: }
1942: }
1943: return mcycles * 2;
1944: }
1945: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
1946: {
1947: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
1948: // write_log ("U%d ", v);
1949: return v;
1950: }
1951:
1952: //
1953: // DIVS
1954: // Signed division
1955: //
1956:
1957: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
1958: {
1959: int mcycles;
1960: uae_u32 aquot;
1961: int i;
1962:
1963: if (divisor == 0)
1964: return 0;
1965:
1966: mcycles = 6;
1967:
1968: if (dividend < 0)
1969: mcycles++;
1970:
1971: // Check for absolute overflow
1972: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
1973: return (mcycles + 2) * 2;
1974:
1975: // Absolute quotient
1976: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
1977:
1978: mcycles += 55;
1979:
1980: if (divisor >= 0) {
1981: if (dividend >= 0)
1982: mcycles--;
1983: else
1984: mcycles++;
1985: }
1986:
1987: // Count 15 msbits in absolute of quotient
1988:
1989: for (i = 0; i < 15; i++) {
1990: if ((uae_s16)aquot >= 0)
1991: mcycles++;
1992: aquot <<= 1;
1993: }
1994:
1995: return mcycles * 2;
1996: }
1997: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
1998: {
1999: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
2000: // write_log ("S%d ", v);
2001: return v;
2002: }
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