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1.1 ! root 1: /* ! 2: * UAE - The Un*x Amiga Emulator ! 3: * ! 4: * MC68000 emulation ! 5: * ! 6: * Copyright 1995 Bernd Schmidt ! 7: */ ! 8: ! 9: #ifndef UAE_NEWCPU_H ! 10: #define UAE_NEWCPU_H ! 11: ! 12: #include "readcpu.h" ! 13: #include "compat.h" ! 14: #include "maccess.h" ! 15: #include "memory.h" ! 16: ! 17: /* Possible exceptions sources for M68000_Exception() and Exception() */ ! 18: // TODO : remove when not used anymore in m68000.c ! 19: #define M68000_EXC_SRC_CPU 1 /* Direct CPU exception */ ! 20: #define M68000_EXC_SRC_AUTOVEC 2 /* Auto-vector exception (e.g. VBL) */ ! 21: #define M68000_EXC_SRC_INT_MFP 3 /* MFP interrupt exception */ ! 22: #define M68000_EXC_SRC_INT_DSP 4 /* DSP interrupt exception */ ! 23: ! 24: ! 25: /* Special flags */ ! 26: #define SPCFLAG_DEBUGGER 1 ! 27: #define SPCFLAG_STOP 2 ! 28: #define SPCFLAG_BUSERROR 4 ! 29: #define SPCFLAG_INT 8 ! 30: #define SPCFLAG_BRK 0x10 ! 31: #define SPCFLAG_EXTRA_CYCLES 0x20 ! 32: #define SPCFLAG_TRACE 0x40 ! 33: #define SPCFLAG_DOTRACE 0x80 ! 34: #define SPCFLAG_DOINT 0x100 ! 35: #define SPCFLAG_MFP 0x200 ! 36: #define SPCFLAG_EXEC 0x400 ! 37: #define SPCFLAG_MODE_CHANGE 0x800 ! 38: #define SPCFLAG_DSP 0x1000 ! 39: ! 40: #if 0 ! 41: #ifndef SET_CFLG ! 42: ! 43: #define SET_CFLG(x) (CFLG() = (x)) ! 44: #define SET_NFLG(x) (NFLG() = (x)) ! 45: #define SET_VFLG(x) (VFLG() = (x)) ! 46: #define SET_ZFLG(x) (ZFLG() = (x)) ! 47: #define SET_XFLG(x) (XFLG() = (x)) ! 48: ! 49: #define GET_CFLG() CFLG() ! 50: #define GET_NFLG() NFLG() ! 51: #define GET_VFLG() VFLG() ! 52: #define GET_ZFLG() ZFLG() ! 53: #define GET_XFLG() XFLG() ! 54: ! 55: #define CLEAR_CZNV() do { \ ! 56: SET_CFLG (0); \ ! 57: SET_ZFLG (0); \ ! 58: SET_NFLG (0); \ ! 59: SET_VFLG (0); \ ! 60: } while (0) ! 61: ! 62: #define COPY_CARRY() (SET_XFLG (GET_CFLG ())) ! 63: #endif ! 64: #endif ! 65: extern const int areg_byteinc[]; ! 66: extern const int imm8_table[]; ! 67: ! 68: extern int movem_index1[256]; ! 69: extern int movem_index2[256]; ! 70: extern int movem_next[256]; ! 71: ! 72: #ifdef FPUEMU ! 73: extern int fpp_movem_index1[256]; ! 74: extern int fpp_movem_index2[256]; ! 75: extern int fpp_movem_next[256]; ! 76: #endif ! 77: ! 78: extern int bus_error_offset; ! 79: ! 80: typedef uae_u32 REGPARAM3 cpuop_func (uae_u32) REGPARAM; ! 81: typedef void REGPARAM3 cpuop_func_ce (uae_u32) REGPARAM; ! 82: ! 83: struct cputbl { ! 84: cpuop_func *handler; ! 85: uae_u16 opcode; ! 86: uae_s8 length; ! 87: uae_s8 disp020[2]; ! 88: uae_u8 branch; ! 89: }; ! 90: ! 91: #ifdef JIT ! 92: #define MAX_JIT_CACHE 16384 ! 93: typedef uae_u32 REGPARAM3 compop_func (uae_u32) REGPARAM; ! 94: ! 95: #define COMP_OPCODE_ISJUMP 0x0001 ! 96: #define COMP_OPCODE_LONG_OPCODE 0x0002 ! 97: #define COMP_OPCODE_CMOV 0x0004 ! 98: #define COMP_OPCODE_ISADDX 0x0008 ! 99: #define COMP_OPCODE_ISCJUMP 0x0010 ! 100: #define COMP_OPCODE_USES_FPU 0x0020 ! 101: ! 102: struct comptbl { ! 103: compop_func *handler; ! 104: uae_u32 opcode; ! 105: int specific; ! 106: }; ! 107: #endif ! 108: ! 109: extern uae_u32 REGPARAM3 op_illg (uae_u32) REGPARAM; ! 110: extern void REGPARAM3 op_unimpl (uae_u16) REGPARAM; ! 111: ! 112: typedef uae_u8 flagtype; ! 113: ! 114: #ifdef FPUEMU ! 115: ! 116: #define WITH_SOFTFLOAT ! 117: #define USE_LONG_DOUBLE ! 118: ! 119: #ifdef WITH_SOFTFLOAT ! 120: #include <softfloat.h> ! 121: typedef floatx80 fptype; ! 122: #else // !WITH_SOFTFLOAT ! 123: #ifdef USE_LONG_DOUBLE ! 124: typedef long double fptype; ! 125: #define LDPTR tbyte ptr ! 126: #else ! 127: typedef double fptype; ! 128: #define LDPTR qword ptr ! 129: #endif ! 130: #endif // !WITH_SOFTFLOAT ! 131: ! 132: #endif // FPUEMU ! 133: ! 134: #define MAX68020CYCLES 4 ! 135: ! 136: #define CPU_PIPELINE_MAX 4 ! 137: #define CPU000_MEM_CYCLE 4 ! 138: #define CPU000_CLOCK_MULT 2 ! 139: #define CPU020_MEM_CYCLE 3 ! 140: #define CPU020_CLOCK_MULT 4 ! 141: ! 142: #define CACHELINES020 64 ! 143: struct cache020 ! 144: { ! 145: uae_u32 data; ! 146: uae_u32 tag; ! 147: bool valid; ! 148: }; ! 149: ! 150: #define CACHELINES030 16 ! 151: struct cache030 ! 152: { ! 153: uae_u32 data[4]; ! 154: bool valid[4]; ! 155: uae_u32 tag; ! 156: }; ! 157: ! 158: #define CACHESETS040 64 ! 159: #define CACHELINES040 4 ! 160: struct cache040 ! 161: { ! 162: uae_u32 data[CACHELINES040][4]; ! 163: bool dirty[CACHELINES040][4]; ! 164: bool valid[CACHELINES040]; ! 165: uae_u32 tag[CACHELINES040]; ! 166: }; ! 167: ! 168: struct mmufixup ! 169: { ! 170: int reg; ! 171: uae_u32 value; ! 172: }; ! 173: extern struct mmufixup mmufixup[2]; ! 174: ! 175: struct regstruct ! 176: { ! 177: uae_u32 regs[16]; ! 178: ! 179: uae_u32 pc; ! 180: uae_u8 *pc_p; ! 181: uae_u8 *pc_oldp; ! 182: uae_u16 opcode; ! 183: uae_u32 instruction_pc; ! 184: ! 185: uae_u16 irc, ir, db; ! 186: uae_u32 spcflags; ! 187: uae_u32 last_prefetch; ! 188: uae_u32 chipset_latch_rw; ! 189: uae_u32 chipset_latch_read; ! 190: uae_u32 chipset_latch_write; ! 191: ! 192: uaecptr usp, isp, msp; ! 193: uae_u16 sr; ! 194: flagtype t1; ! 195: flagtype t0; ! 196: flagtype s; ! 197: flagtype m; ! 198: flagtype x; ! 199: flagtype stopped; ! 200: int halted; ! 201: int exception; ! 202: int intmask; ! 203: int ipl, ipl_pin; ! 204: ! 205: uae_u32 vbr, sfc, dfc; ! 206: ! 207: #ifdef FPUEMU ! 208: fptype fp[8]; ! 209: uae_u32 fpcr, fpsr, fpiar; ! 210: uae_u32 fpu_state; ! 211: uae_u32 fpu_exp_state; ! 212: uae_u16 fp_opword; ! 213: uaecptr fp_ea; ! 214: uae_u32 fp_exp_pend, fp_unimp_pend; ! 215: bool fpu_exp_pre; ! 216: bool fp_unimp_ins; ! 217: bool fp_exception; ! 218: bool fp_branch; ! 219: #endif ! 220: #ifndef CPUEMU_68000_ONLY ! 221: uae_u32 cacr, caar; ! 222: uae_u32 itt0, itt1, dtt0, dtt1; ! 223: uae_u32 tcr, mmusr, urp, srp, buscr; ! 224: uae_u32 mmu_fslw; ! 225: uae_u32 mmu_fault_addr, mmu_effective_addr; ! 226: uae_u16 mmu_ssw; ! 227: uae_u32 wb2_address; ! 228: uae_u32 wb3_data; ! 229: uae_u8 wb3_status, wb2_status; ! 230: int mmu_enabled; ! 231: int mmu_page_size; ! 232: #endif ! 233: ! 234: uae_u32 pcr; ! 235: uae_u32 address_space_mask; ! 236: ! 237: uae_u32 prefetch020[CPU_PIPELINE_MAX]; ! 238: uae_u32 prefetch020addr; ! 239: uae_u32 cacheholdingdata020; ! 240: uae_u32 cacheholdingaddr020; ! 241: int pipeline_pos; ! 242: int pipeline_r8[2]; ! 243: int pipeline_stop; ! 244: int memory_waitstate_cycles; ! 245: }; ! 246: ! 247: extern struct regstruct regs; ! 248: ! 249: /* ! 250: * UAE - The Un*x Amiga Emulator ! 251: * ! 252: * MC68000 emulation - machine dependent bits ! 253: * ! 254: * Copyright 1996 Bernd Schmidt ! 255: * Copyright 2004-2005 Richard Drummond ! 256: */ ! 257: ! 258: /* ! 259: * Machine dependent structure for holding the 68k CCR flags ! 260: */ ! 261: struct flag_struct { ! 262: unsigned int cznv; ! 263: unsigned int x; ! 264: }; ! 265: ! 266: extern struct flag_struct regflags; ! 267: ! 268: /* ! 269: * The bits in the cznv field in the above structure are assigned to ! 270: * allow the easy mirroring of the x86 condition flags. (For example, ! 271: * from the AX register - the x86 overflow flag can be copied to AL ! 272: * with a setto %AL instr and the other flags copied to AH with an ! 273: * lahf instr). ! 274: * ! 275: * The 68k CZNV flags are thus assinged in cznv as: ! 276: * ! 277: * <--AL--> <--AH--> ! 278: * 76543210 FEDCBA98 --------- --------- ! 279: * xxxxxxxV NZxxxxxC xxxxxxxxx xxxxxxxxx ! 280: */ ! 281: ! 282: #define FLAGBIT_N 15 ! 283: #define FLAGBIT_Z 14 ! 284: #define FLAGBIT_C 8 ! 285: #define FLAGBIT_V 0 ! 286: #define FLAGBIT_X 8 ! 287: ! 288: #define FLAGVAL_N (1 << FLAGBIT_N) ! 289: #define FLAGVAL_Z (1 << FLAGBIT_Z) ! 290: #define FLAGVAL_C (1 << FLAGBIT_C) ! 291: #define FLAGVAL_V (1 << FLAGBIT_V) ! 292: #define FLAGVAL_X (1 << FLAGBIT_X) ! 293: ! 294: #define SET_ZFLG(y) (regflags.cznv = (regflags.cznv & ~FLAGVAL_Z) | (((y) ? 1 : 0) << FLAGBIT_Z)) ! 295: #define SET_CFLG(y) (regflags.cznv = (regflags.cznv & ~FLAGVAL_C) | (((y) ? 1 : 0) << FLAGBIT_C)) ! 296: #define SET_VFLG(y) (regflags.cznv = (regflags.cznv & ~FLAGVAL_V) | (((y) ? 1 : 0) << FLAGBIT_V)) ! 297: #define SET_NFLG(y) (regflags.cznv = (regflags.cznv & ~FLAGVAL_N) | (((y) ? 1 : 0) << FLAGBIT_N)) ! 298: #define SET_XFLG(y) (regflags.x = ((y) ? 1 : 0) << FLAGBIT_X) ! 299: ! 300: #define GET_ZFLG() ((regflags.cznv >> FLAGBIT_Z) & 1) ! 301: #define GET_CFLG() ((regflags.cznv >> FLAGBIT_C) & 1) ! 302: #define GET_VFLG() ((regflags.cznv >> FLAGBIT_V) & 1) ! 303: #define GET_NFLG() ((regflags.cznv >> FLAGBIT_N) & 1) ! 304: #define GET_XFLG() ((regflags.x >> FLAGBIT_X) & 1) ! 305: ! 306: #define CLEAR_CZNV() (regflags.cznv = 0) ! 307: #define GET_CZNV() (regflags.cznv) ! 308: #define IOR_CZNV(X) (regflags.cznv |= (X)) ! 309: #define SET_CZNV(X) (regflags.cznv = (X)) ! 310: ! 311: #define COPY_CARRY() (regflags.x = regflags.cznv) ! 312: ! 313: ! 314: /* ! 315: * Test CCR condition ! 316: */ ! 317: STATIC_INLINE int cctrue (int cc) ! 318: { ! 319: uae_u32 cznv = regflags.cznv; ! 320: ! 321: switch (cc) { ! 322: case 0: return 1; /* T */ ! 323: case 1: return 0; /* F */ ! 324: case 2: return (cznv & (FLAGVAL_C | FLAGVAL_Z)) == 0; /* !CFLG && !ZFLG HI */ ! 325: case 3: return (cznv & (FLAGVAL_C | FLAGVAL_Z)) != 0; /* CFLG || ZFLG LS */ ! 326: case 4: return (cznv & FLAGVAL_C) == 0; /* !CFLG CC */ ! 327: case 5: return (cznv & FLAGVAL_C) != 0; /* CFLG CS */ ! 328: case 6: return (cznv & FLAGVAL_Z) == 0; /* !ZFLG NE */ ! 329: case 7: return (cznv & FLAGVAL_Z) != 0; /* ZFLG EQ */ ! 330: case 8: return (cznv & FLAGVAL_V) == 0; /* !VFLG VC */ ! 331: case 9: return (cznv & FLAGVAL_V) != 0; /* VFLG VS */ ! 332: case 10: return (cznv & FLAGVAL_N) == 0; /* !NFLG PL */ ! 333: case 11: return (cznv & FLAGVAL_N) != 0; /* NFLG MI */ ! 334: case 12: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) == 0; /* NFLG == VFLG GE */ ! 335: case 13: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) != 0; /* NFLG != VFLG LT */ ! 336: case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* ZFLG && (NFLG == VFLG) GT */ ! 337: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) == 0; ! 338: case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* ZFLG && (NFLG != VFLG) LE */ ! 339: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) != 0; ! 340: } ! 341: return 0; ! 342: } ! 343: ! 344: #define MAX_CPUTRACESIZE 128 ! 345: struct cputracememory ! 346: { ! 347: uae_u32 addr; ! 348: uae_u32 data; ! 349: int mode; ! 350: }; ! 351: ! 352: struct cputracestruct ! 353: { ! 354: uae_u32 regs[16]; ! 355: uae_u32 usp, isp, pc; ! 356: uae_u16 ir, irc, sr, opcode; ! 357: int intmask, stopped, state; ! 358: ! 359: uae_u32 msp, vbr; ! 360: uae_u32 cacr, caar; ! 361: uae_u32 prefetch020[CPU_PIPELINE_MAX]; ! 362: uae_u32 prefetch020addr; ! 363: uae_u32 cacheholdingdata020; ! 364: uae_u32 cacheholdingaddr020; ! 365: struct cache020 caches020[CACHELINES020]; ! 366: ! 367: uae_u32 startcycles; ! 368: int needendcycles; ! 369: int memoryoffset; ! 370: int cyclecounter, cyclecounter_pre, cyclecounter_post; ! 371: int readcounter, writecounter; ! 372: struct cputracememory ctm[MAX_CPUTRACESIZE]; ! 373: }; ! 374: ! 375: STATIC_INLINE uae_u32 munge24 (uae_u32 x) ! 376: { ! 377: return x & regs.address_space_mask; ! 378: } ! 379: ! 380: extern int mmu_enabled, mmu_triggered; ! 381: extern int cpu_cycles; ! 382: extern int cpucycleunit; ! 383: extern int m68k_pc_indirect; ! 384: ! 385: STATIC_INLINE void set_special (uae_u32 x) ! 386: { ! 387: regs.spcflags |= x; ! 388: } ! 389: ! 390: STATIC_INLINE void unset_special (uae_u32 x) ! 391: { ! 392: regs.spcflags &= ~x; ! 393: } ! 394: ! 395: ! 396: #define m68k_dreg(r,num) ((r).regs[(num)]) ! 397: #define m68k_areg(r,num) (((r).regs + 8)[(num)]) ! 398: ! 399: extern uae_u32(*x_prefetch)(int); ! 400: extern uae_u32(*x_get_byte)(uaecptr addr); ! 401: extern uae_u32(*x_get_word)(uaecptr addr); ! 402: extern uae_u32(*x_get_long)(uaecptr addr); ! 403: extern void(*x_put_byte)(uaecptr addr, uae_u32 v); ! 404: extern void(*x_put_word)(uaecptr addr, uae_u32 v); ! 405: extern void(*x_put_long)(uaecptr addr, uae_u32 v); ! 406: extern uae_u32(*x_next_iword)(void); ! 407: extern uae_u32(*x_next_ilong)(void); ! 408: extern uae_u32(*x_get_ilong)(int); ! 409: extern uae_u32(*x_get_iword)(int); ! 410: extern uae_u32(*x_get_ibyte)(int); ! 411: ! 412: extern uae_u32(*x_cp_get_byte)(uaecptr addr); ! 413: extern uae_u32(*x_cp_get_word)(uaecptr addr); ! 414: extern uae_u32(*x_cp_get_long)(uaecptr addr); ! 415: extern void(*x_cp_put_byte)(uaecptr addr, uae_u32 v); ! 416: extern void(*x_cp_put_word)(uaecptr addr, uae_u32 v); ! 417: extern void(*x_cp_put_long)(uaecptr addr, uae_u32 v); ! 418: extern uae_u32(*x_cp_next_iword)(void); ! 419: extern uae_u32(*x_cp_next_ilong)(void); ! 420: ! 421: extern uae_u32(REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM; ! 422: ! 423: /* direct (regs.pc_p) access */ ! 424: ! 425: STATIC_INLINE void m68k_setpc(uaecptr newpc) ! 426: { ! 427: regs.pc_p = regs.pc_oldp = 0; ! 428: regs.instruction_pc = regs.pc = newpc; ! 429: } ! 430: STATIC_INLINE uaecptr m68k_getpc(void) ! 431: { ! 432: return (uaecptr)(regs.pc + ((uae_u8*)regs.pc_p - (uae_u8*)regs.pc_oldp)); ! 433: } ! 434: #define M68K_GETPC m68k_getpc() ! 435: STATIC_INLINE uaecptr m68k_getpc_p(uae_u8 *p) ! 436: { ! 437: return (uaecptr)(regs.pc + ((uae_u8*)p - (uae_u8*)regs.pc_oldp)); ! 438: } ! 439: STATIC_INLINE void m68k_incpc(int o) ! 440: { ! 441: regs.pc_p += o; ! 442: } ! 443: ! 444: STATIC_INLINE uae_u32 get_dibyte(int o) ! 445: { ! 446: return do_get_mem_byte((uae_u8 *)((regs).pc_p + (o) + 1)); ! 447: } ! 448: STATIC_INLINE uae_u32 get_diword(int o) ! 449: { ! 450: return do_get_mem_word((uae_u16 *)((regs).pc_p + (o))); ! 451: } ! 452: STATIC_INLINE uae_u32 get_dilong(int o) ! 453: { ! 454: return do_get_mem_long((uae_u32 *)((regs).pc_p + (o))); ! 455: } ! 456: STATIC_INLINE uae_u32 next_diword(void) ! 457: { ! 458: uae_u32 r = do_get_mem_word((uae_u16 *)((regs).pc_p)); ! 459: m68k_incpc(2); ! 460: return r; ! 461: } ! 462: STATIC_INLINE uae_u32 next_dilong(void) ! 463: { ! 464: uae_u32 r = do_get_mem_long((uae_u32 *)((regs).pc_p)); ! 465: m68k_incpc(4); ! 466: return r; ! 467: } ! 468: ! 469: STATIC_INLINE void m68k_do_bsr(uaecptr oldpc, uae_s32 offset) ! 470: { ! 471: m68k_areg(regs, 7) -= 4; ! 472: put_long(m68k_areg(regs, 7), oldpc); ! 473: m68k_incpc(offset); ! 474: } ! 475: STATIC_INLINE void m68k_do_rts(void) ! 476: { ! 477: uae_u32 newpc = get_long(m68k_areg(regs, 7)); ! 478: m68k_setpc(newpc); ! 479: m68k_areg(regs, 7) += 4; ! 480: } ! 481: ! 482: /* indirect (regs.pc) access */ ! 483: ! 484: STATIC_INLINE void m68k_setpci(uaecptr newpc) ! 485: { ! 486: regs.instruction_pc = regs.pc = newpc; ! 487: } ! 488: STATIC_INLINE uaecptr m68k_getpci(void) ! 489: { ! 490: return regs.pc; ! 491: } ! 492: STATIC_INLINE void m68k_incpci(int o) ! 493: { ! 494: regs.pc += o; ! 495: } ! 496: ! 497: STATIC_INLINE uae_u32 get_iibyte(int o) ! 498: { ! 499: return get_wordi(m68k_getpci() + (o)) & 0xff; ! 500: } ! 501: STATIC_INLINE uae_u32 get_iiword(int o) ! 502: { ! 503: return get_wordi(m68k_getpci() + (o)); ! 504: } ! 505: STATIC_INLINE uae_u32 get_iilong(int o) ! 506: { ! 507: return get_longi(m68k_getpci () + (o)); ! 508: } ! 509: ! 510: STATIC_INLINE uae_u32 next_iibyte (void) ! 511: { ! 512: uae_u32 r = get_iibyte (0); ! 513: m68k_incpci (2); ! 514: return r; ! 515: } ! 516: STATIC_INLINE uae_u32 next_iiword (void) ! 517: { ! 518: uae_u32 r = get_iiword (0); ! 519: m68k_incpci (2); ! 520: return r; ! 521: } ! 522: STATIC_INLINE uae_u32 next_iiwordi (void) ! 523: { ! 524: uae_u32 r = get_wordi(m68k_getpci()); ! 525: m68k_incpci (2); ! 526: return r; ! 527: } ! 528: STATIC_INLINE uae_u32 next_iilong (void) ! 529: { ! 530: uae_u32 r = get_iilong(0); ! 531: m68k_incpci (4); ! 532: return r; ! 533: } ! 534: STATIC_INLINE uae_u32 next_iilongi (void) ! 535: { ! 536: uae_u32 r = get_longi (m68k_getpci ()); ! 537: m68k_incpci (4); ! 538: return r; ! 539: } ! 540: ! 541: STATIC_INLINE void m68k_do_bsri(uaecptr oldpc, uae_s32 offset) ! 542: { ! 543: m68k_areg(regs, 7) -= 4; ! 544: put_long(m68k_areg(regs, 7), oldpc); ! 545: m68k_incpci(offset); ! 546: } ! 547: STATIC_INLINE void m68k_do_rtsi(void) ! 548: { ! 549: uae_u32 newpc = get_long(m68k_areg(regs, 7)); ! 550: m68k_setpci(newpc); ! 551: m68k_areg(regs, 7) += 4; ! 552: } ! 553: ! 554: /* indirect jit friendly versions */ ! 555: ! 556: STATIC_INLINE uae_u32 get_iibyte_jit(int o) ! 557: { ! 558: return get_wordi(m68k_getpc() + (o)) & 0xff; ! 559: } ! 560: STATIC_INLINE uae_u32 get_iiword_jit(int o) ! 561: { ! 562: return get_wordi(m68k_getpc() + (o)); ! 563: } ! 564: STATIC_INLINE uae_u32 get_iilong_jit(int o) ! 565: { ! 566: return get_longi(m68k_getpc() + (o)); ! 567: } ! 568: STATIC_INLINE uae_u32 next_iiword_jit(void) ! 569: { ! 570: uae_u32 r = get_wordi(m68k_getpc()); ! 571: m68k_incpc(2); ! 572: return r; ! 573: } ! 574: STATIC_INLINE uae_u32 next_iilong_jit(void) ! 575: { ! 576: uae_u32 r = get_longi(m68k_getpc()); ! 577: m68k_incpc(4); ! 578: return r; ! 579: } ! 580: STATIC_INLINE void m68k_do_bsri_jit(uaecptr oldpc, uae_s32 offset) ! 581: { ! 582: m68k_areg(regs, 7) -= 4; ! 583: x_put_long(m68k_areg(regs, 7), oldpc); ! 584: m68k_incpc(offset); ! 585: } ! 586: STATIC_INLINE void m68k_do_rtsi_jit(void) ! 587: { ! 588: uae_u32 newpc = x_get_long(m68k_areg(regs, 7)); ! 589: m68k_setpc(newpc); ! 590: m68k_areg(regs, 7) += 4; ! 591: } ! 592: ! 593: /* common access */ ! 594: ! 595: STATIC_INLINE void m68k_incpc_normal(int o) ! 596: { ! 597: if (m68k_pc_indirect > 0) ! 598: m68k_incpci(o); ! 599: else ! 600: m68k_incpc(o); ! 601: } ! 602: ! 603: STATIC_INLINE void m68k_setpc_normal(uaecptr pc) ! 604: { ! 605: if (m68k_pc_indirect > 0) { ! 606: regs.pc_p = regs.pc_oldp = 0; ! 607: m68k_setpci(pc); ! 608: } else { ! 609: m68k_setpc(pc); ! 610: } ! 611: } ! 612: ! 613: extern void check_t0_trace(void); ! 614: extern void write_dcache030(uaecptr, uae_u32, int); ! 615: extern uae_u32 read_dcache030(uaecptr, int); ! 616: extern uae_u32 get_word_icache030(uaecptr addr); ! 617: extern uae_u32 get_long_icache030(uaecptr addr); ! 618: ! 619: uae_u32 fill_icache040(uae_u32 addr); ! 620: extern void put_long_cache_040(uaecptr, uae_u32); ! 621: extern void put_word_cache_040(uaecptr, uae_u32); ! 622: extern void put_byte_cache_040(uaecptr, uae_u32); ! 623: extern uae_u32 get_ilong_cache_040(int); ! 624: extern uae_u32 get_iword_cache_040(int); ! 625: extern uae_u32 get_long_cache_040(uaecptr); ! 626: extern uae_u32 get_word_cache_040(uaecptr); ! 627: extern uae_u32 get_byte_cache_040(uaecptr); ! 628: extern uae_u32 next_iword_cache040(void); ! 629: extern uae_u32 next_ilong_cache040(void); ! 630: extern uae_u32 get_word_icache040(uaecptr addr); ! 631: extern uae_u32 get_long_icache040(uaecptr addr); ! 632: ! 633: extern void (*x_do_cycles)(unsigned long); ! 634: extern void (*x_do_cycles_pre)(unsigned long); ! 635: extern void (*x_do_cycles_post)(unsigned long, uae_u32); ! 636: ! 637: extern uae_u32 REGPARAM3 x_get_disp_ea_020 (uae_u32 base, int idx) REGPARAM; ! 638: extern uae_u32 REGPARAM3 x_get_disp_ea_ce020 (uae_u32 base, int idx) REGPARAM; ! 639: extern uae_u32 REGPARAM3 x_get_disp_ea_ce030 (uae_u32 base, int idx) REGPARAM; ! 640: extern uae_u32 REGPARAM3 x_get_disp_ea_040(uae_u32 base, int idx) REGPARAM; ! 641: extern uae_u32 REGPARAM3 x_get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM; ! 642: extern void REGPARAM3 x_put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM; ! 643: ! 644: extern void m68k_setstopped (void); ! 645: extern void m68k_resumestopped (void); ! 646: ! 647: extern uae_u32 REGPARAM3 get_disp_ea_020 (uae_u32 base, int idx) REGPARAM; ! 648: extern uae_u32 REGPARAM3 get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM; ! 649: extern void REGPARAM3 put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM; ! 650: ! 651: extern void m68k_disasm_ea (uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr); ! 652: extern void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt); ! 653: extern void m68k_disasm_2 (TCHAR *buf, int bufsize, uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr, int safemode); ! 654: extern void sm68k_disasm (TCHAR*, TCHAR*, uaecptr addr, uaecptr *nextpc); ! 655: extern int get_cpu_model (void); ! 656: ! 657: extern void set_cpu_caches (bool flush); ! 658: extern void flush_cpu_caches(bool flush); ! 659: extern void flush_cpu_caches_040(uae_u16 opcode); ! 660: extern void REGPARAM3 MakeSR (void) REGPARAM; ! 661: extern void REGPARAM3 MakeFromSR(void) REGPARAM; ! 662: extern void REGPARAM3 MakeFromSR_T0(void) REGPARAM; ! 663: extern void MakeSR (void); ! 664: extern void MakeFromSR (void); ! 665: extern void REGPARAM3 Exception (int) REGPARAM; ! 666: extern void REGPARAM3 Exception_cpu(int) REGPARAM; ! 667: extern void REGPARAM3 ExceptionL (int, uaecptr) REGPARAM; ! 668: extern void NMI (void); ! 669: extern void NMI_delayed (void); ! 670: extern void prepare_interrupt (uae_u32); ! 671: extern void doint (void); ! 672: extern void dump_counts (void); ! 673: extern int m68k_move2c (int, uae_u32 *); ! 674: extern int m68k_movec2 (int, uae_u32 *); ! 675: extern bool m68k_divl (uae_u32, uae_u32, uae_u16); ! 676: extern bool m68k_mull (uae_u32, uae_u32, uae_u16); ! 677: extern void init_m68k (void); ! 678: extern void init_m68k_full (void); ! 679: extern void m68k_go (int); ! 680: extern void m68k_dumpstate (uaecptr *); ! 681: extern void m68k_dumpstate_2 (uaecptr, uaecptr *); ! 682: extern void m68k_dumpstate_file (FILE *f, uaecptr *); ! 683: extern void m68k_dumpcache (void); ! 684: extern int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor); ! 685: extern int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor); ! 686: extern void divbyzero_special(bool issigned, uae_s32 dst); ! 687: extern void setdivuoverflowflags(uae_u32 dividend, uae_u16 divisor); ! 688: extern void setdivsoverflowflags(uae_s32 dividend, uae_s16 divisor); ! 689: extern void m68k_do_rte (void); ! 690: extern void protect_roms (bool); ! 691: extern void unprotect_maprom (void); ! 692: extern bool is_hardreset(void); ! 693: extern bool is_keyboardreset(void); ! 694: ! 695: extern void mmu_op (uae_u32, uae_u32); ! 696: extern bool mmu_op30 (uaecptr, uae_u32, uae_u16, uaecptr); ! 697: ! 698: extern void fpuop_arithmetic(uae_u32, uae_u16); ! 699: extern void fpuop_dbcc(uae_u32, uae_u16); ! 700: extern void fpuop_scc(uae_u32, uae_u16); ! 701: extern void fpuop_trapcc(uae_u32, uaecptr, uae_u16); ! 702: extern void fpuop_bcc(uae_u32, uaecptr, uae_u32); ! 703: extern void fpuop_save(uae_u32); ! 704: extern void fpuop_restore(uae_u32); ! 705: extern uae_u32 fpp_get_fpsr (void); ! 706: extern void fpu_reset (void); ! 707: extern void fpux_save (int*); ! 708: extern void fpux_restore (int*); ! 709: extern bool fpu_get_constant(fptype *fp, int cr); ! 710: extern int fpp_cond(int condition); ! 711: ! 712: extern void exception3_read(uae_u32 opcode, uaecptr addr); ! 713: extern void exception3_write(uae_u32 opcode, uaecptr addr); ! 714: extern void exception3_notinstruction(uae_u32 opcode, uaecptr addr); ! 715: extern void exception3i (uae_u32 opcode, uaecptr addr); ! 716: extern void exception3b (uae_u32 opcode, uaecptr addr, bool w, bool i, uaecptr pc); ! 717: extern void exception2 (uaecptr addr, bool read, int size, uae_u32 fc); ! 718: extern void m68k_reset (int hardreset); ! 719: extern void cpureset (void); ! 720: extern void cpu_halt (int id); ! 721: extern int cpu_sleep_millis(int ms); ! 722: extern void cpu_change(int newmodel); ! 723: extern void cpu_fallback(int mode); ! 724: ! 725: extern void fill_prefetch (void); ! 726: extern void fill_prefetch_020_ntx(void); ! 727: extern void fill_prefetch_030_ntx(void); ! 728: extern void fill_prefetch_020(void); ! 729: extern void fill_prefetch_030(void); ! 730: ! 731: #define CPU_OP_NAME(a) op ## a ! 732: ! 733: /* 68060 */ ! 734: extern const struct cputbl op_smalltbl_0_ff[]; ! 735: extern const struct cputbl op_smalltbl_40_ff[]; ! 736: extern const struct cputbl op_smalltbl_50_ff[]; ! 737: extern const struct cputbl op_smalltbl_24_ff[]; // CE ! 738: extern const struct cputbl op_smalltbl_33_ff[]; // MMU ! 739: /* 68040 */ ! 740: extern const struct cputbl op_smalltbl_1_ff[]; ! 741: extern const struct cputbl op_smalltbl_41_ff[]; ! 742: extern const struct cputbl op_smalltbl_51_ff[]; ! 743: extern const struct cputbl op_smalltbl_25_ff[]; // CE ! 744: extern const struct cputbl op_smalltbl_31_ff[]; // MMU ! 745: /* 68030 */ ! 746: extern const struct cputbl op_smalltbl_2_ff[]; ! 747: extern const struct cputbl op_smalltbl_42_ff[]; ! 748: extern const struct cputbl op_smalltbl_52_ff[]; ! 749: extern const struct cputbl op_smalltbl_22_ff[]; // prefetch ! 750: extern const struct cputbl op_smalltbl_23_ff[]; // CE ! 751: extern const struct cputbl op_smalltbl_32_ff[]; // MMU ! 752: /* 68020 */ ! 753: extern const struct cputbl op_smalltbl_3_ff[]; ! 754: extern const struct cputbl op_smalltbl_43_ff[]; ! 755: extern const struct cputbl op_smalltbl_53_ff[]; ! 756: extern const struct cputbl op_smalltbl_20_ff[]; // prefetch ! 757: extern const struct cputbl op_smalltbl_21_ff[]; // CE ! 758: /* 68010 */ ! 759: extern const struct cputbl op_smalltbl_4_ff[]; ! 760: extern const struct cputbl op_smalltbl_44_ff[]; ! 761: extern const struct cputbl op_smalltbl_54_ff[]; ! 762: extern const struct cputbl op_smalltbl_11_ff[]; // prefetch ! 763: extern const struct cputbl op_smalltbl_13_ff[]; // CE ! 764: /* 68000 */ ! 765: extern const struct cputbl op_smalltbl_5_ff[]; ! 766: extern const struct cputbl op_smalltbl_45_ff[]; ! 767: extern const struct cputbl op_smalltbl_55_ff[]; ! 768: extern const struct cputbl op_smalltbl_12_ff[]; // prefetch ! 769: extern const struct cputbl op_smalltbl_14_ff[]; // CE ! 770: ! 771: extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl"); ! 772: ! 773: #ifdef JIT ! 774: extern void flush_icache(int); ! 775: extern void flush_icache_hard(int); ! 776: extern void compemu_reset(void); ! 777: #else ! 778: #define flush_icache(int) do {} while (0) ! 779: #define flush_icache_hard(int) do {} while (0) ! 780: #endif ! 781: bool check_prefs_changed_comp (bool); ! 782: extern void flush_dcache (uaecptr, int); ! 783: extern void flush_mmu (uaecptr, int); ! 784: ! 785: extern int movec_illg (int regno); ! 786: extern uae_u32 val_move2c (int regno); ! 787: extern void val_move2c2 (int regno, uae_u32 val); ! 788: struct cpum2c { ! 789: int regno; ! 790: const TCHAR *regname; ! 791: }; ! 792: extern struct cpum2c m2cregs[]; ! 793: ! 794: extern bool is_cpu_tracer (void); ! 795: extern bool set_cpu_tracer (bool force); ! 796: extern bool can_cpu_tracer (void); ! 797: ! 798: #define CPU_HALT_PPC_ONLY -1 ! 799: #define CPU_HALT_BUS_ERROR_DOUBLE_FAULT 1 ! 800: #define CPU_HALT_DOUBLE_FAULT 2 ! 801: #define CPU_HALT_OPCODE_FETCH_FROM_NON_EXISTING_ADDRESS 3 ! 802: #define CPU_HALT_ACCELERATOR_CPU_FALLBACK 4 ! 803: #define CPU_HALT_ALL_CPUS_STOPPED 5 ! 804: #define CPU_HALT_FAKE_DMA 6 ! 805: #define CPU_HALT_AUTOCONFIG_CONFLICT 7 ! 806: #define CPU_HALT_PCI_CONFLICT 8 ! 807: #define CPU_HALT_CPU_STUCK 9 ! 808: #define CPU_HALT_SSP_IN_NON_EXISTING_ADDRESS 10 ! 809: ! 810: void cpu_semaphore_get(void); ! 811: void cpu_semaphore_release(void); ! 812: bool execute_other_cpu(int until); ! 813: void execute_other_cpu_single(void); ! 814: ! 815: #endif /* UAE_NEWCPU_H */
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