|
|
1.1 root 1: #pragma once
2:
3: #ifndef __DIMENSION_H__
4: #define __DIMENSION_H__
5:
6: #include <SDL_stdinc.h>
7: #include "nd_sdl.hpp"
8:
9: /* NeXTdimension memory controller revision (0 and 1 allowed) */
10: #define ND_STEP 1
11:
12: #define ND_SLOT(num) ((num)*2+2)
13: #define ND_NUM(slot) ((slot)/2-1)
14:
15: #ifdef __cplusplus
16: extern "C" {
17: #endif /* __cplusplus */
18:
19: typedef void (*i860_run_func)(int);
20: extern i860_run_func i860_Run;
21: void nd_start_debugger(void);
22: const char* nd_reports(int num, double realTime, double hostTime);
23: Uint32* nd_vram_for_slot(int slot);
24:
25: #define ND_LOG_IO_RD LOG_NONE
26: #define ND_LOG_IO_WR LOG_NONE
27:
28: #ifdef __cplusplus
29: }
30: #endif /* __cplusplus */
31:
32: #ifdef __cplusplus
33:
34: #include "NextBus.hpp"
35: #include "i860.hpp"
36: #include "nd_nbic.hpp"
37: #include "nd_mem.hpp"
38: #include "ramdac.h"
39:
40: class NextDimension;
41:
42: class MC {
43: NextDimension* nd;
44: public:
45: Uint32 csr0;
46: Uint32 csr1;
47: Uint32 csr2;
48: Uint32 sid;
49: Uint32 dma_csr;
50: Uint32 dma_start;
51: Uint32 dma_width;
52: Uint32 dma_pstart;
53: Uint32 dma_pwidth;
54: Uint32 dma_sstart;
55: Uint32 dma_swidth;
56: Uint32 dma_bsstart;
57: Uint32 dma_bswidth;
58: Uint32 dma_top;
59: Uint32 dma_bottom;
60: Uint32 dma_line_a;
61: Uint32 dma_curr_a;
62: Uint32 dma_scurr_a;
63: Uint32 dma_out_a;
64: Uint32 vram;
65: Uint32 dram;
66:
67: MC(NextDimension* nd);
68: void init(void);
69: Uint32 read(Uint32 addr);
70: void write(Uint32 addr, Uint32 val);
71: };
72:
73: class DP {
74: NextDimension* nd;
75: public:
76: Uint8 iic_addr;
77: Uint8 iic_msg;
78: Uint32 iic_msgsz;
79: int iic_busy;
80: Uint32 doff; // (SC) wild guess - vram offset in pixels?
81: Uint32 csr;
82: Uint32 alpha;
83: Uint32 dma;
84: Uint32 cpu_x;
85: Uint32 cpu_y;
86: Uint32 dma_x;
87: Uint32 dma_y;
88: Uint32 iic_stat_addr;
89: Uint32 iic_data;
90:
91: DP(NextDimension* nd);
92: void init(void);
93: Uint32 lget(Uint32 addr);
94: void lput(Uint32 addr, Uint32 val);
95: void iicmsg(void);
96: };
97:
98: #define ND_DMCD_NUM_REG 25
99: class DMCD {
100: NextDimension* nd;
101: public:
102: Uint8 addr;
103: Uint8 reg[ND_DMCD_NUM_REG];
104:
105: DMCD(NextDimension* nd);
106:
107: void write(Uint32 step, Uint8 data);
108: };
109:
110: class DCSC {
111: NextDimension* nd;
112: int dev;
113: public:
114: Uint8 addr;
115: Uint8 ctrl;
116: Uint8 lut[256];
117:
118: DCSC(NextDimension* nd, int dev);
119:
120: void write(Uint32 step, Uint8 data);
121: };
122:
123: class NextDimension : public NextBusBoard {
124: /* Message port for host->dimension communication */
125: volatile int m_port;
126: lock_t m_port_lock;
127: public:
128: NDSDL sdl;
129: i860_cpu_device i860;
130: NBIC nbic;
131: MC mc;
132: DP dp;
133: DMCD dmcd;
134: DCSC dcsc0;
135: DCSC dcsc1;
136: bt463 ramdac;
137:
138: ND_Addrbank* mem_banks[65536];
139: Uint8 ram[64*1024*1024];
140: Uint8 vram[4*1024*1024];
141: Uint8 rom[128*1024];
142: Uint8 rom_command;
143: Uint32 rom_last_addr;;
144: Uint8 dmem[512];
145: Uint32 bankmask[4];
146:
147: NextDimension(int slot);
148: void mem_init(void);
149: void init_mem_banks(void);
150: void map_banks (ND_Addrbank *bank, int start, int size);
151:
152: virtual Uint32 board_lget(Uint32 addr);
153: virtual Uint16 board_wget(Uint32 addr);
154: virtual Uint8 board_bget(Uint32 addr);
155: virtual void board_lput(Uint32 addr, Uint32 val);
156: virtual void board_wput(Uint32 addr, Uint16 val);
157: virtual void board_bput(Uint32 addr, Uint8 val);
158:
159: virtual Uint32 slot_lget(Uint32 addr);
160: virtual Uint16 slot_wget(Uint32 addr);
161: virtual Uint8 slot_bget(Uint32 addr);
162: virtual void slot_lput(Uint32 addr, Uint32 val);
163: virtual void slot_wput(Uint32 addr, Uint16 val);
164: virtual void slot_bput(Uint32 addr, Uint8 val);
165:
166: virtual void reset(void);
167: virtual void pause(bool pause);
168:
169: static Uint8 i860_cs8get (NextDimension* nd, Uint32 addr);
170: static void i860_rd8_be (NextDimension* nd, Uint32 addr, Uint32* val);
171: static void i860_rd16_be (NextDimension* nd, Uint32 addr, Uint32* val);
172: static void i860_rd32_be (NextDimension* nd, Uint32 addr, Uint32* val);
173: static void i860_rd64_be (NextDimension* nd, Uint32 addr, Uint32* val);
174: static void i860_rd128_be(NextDimension* nd, Uint32 addr, Uint32* val);
175: static void i860_wr8_be (NextDimension* nd, Uint32 addr, const Uint32* val);
176: static void i860_wr16_be (NextDimension* nd, Uint32 addr, const Uint32* val);
177: static void i860_wr32_be (NextDimension* nd, Uint32 addr, const Uint32* val);
178: static void i860_wr64_be (NextDimension* nd, Uint32 addr, const Uint32* val);
179: static void i860_wr128_be(NextDimension* nd, Uint32 addr, const Uint32* val);
180: static void i860_rd8_le (NextDimension* nd, Uint32 addr, Uint32* val);
181: static void i860_rd16_le (NextDimension* nd, Uint32 addr, Uint32* val);
182: static void i860_rd32_le (NextDimension* nd, Uint32 addr, Uint32* val);
183: static void i860_rd64_le (NextDimension* nd, Uint32 addr, Uint32* val);
184: static void i860_rd128_le(NextDimension* nd, Uint32 addr, Uint32* val);
185: static void i860_wr8_le (NextDimension* nd, Uint32 addr, const Uint32* val);
186: static void i860_wr16_le (NextDimension* nd, Uint32 addr, const Uint32* val);
187: static void i860_wr32_le (NextDimension* nd, Uint32 addr, const Uint32* val);
188: static void i860_wr64_le (NextDimension* nd, Uint32 addr, const Uint32* val);
189: static void i860_wr128_le(NextDimension* nd, Uint32 addr, const Uint32* val);
190:
191: Uint8 rom_read(Uint32 addr);
192: void rom_write(Uint32 addr, Uint8 val);
193: void rom_load();
194:
195: bool handle_msgs(void); /* i860 thread message handler */
196: void send_msg(int msg);
197:
198: void set_blank_state(int src, bool state);
199: void video_dev_write(Uint8 addr, Uint32 step, Uint8 data);
200:
201: bool dbg_cmd(const char* buf);
202:
203: virtual ~NextDimension();
204: };
205:
206: #endif /* __cplusplus */
207:
208: #endif /* __DIMENSION_H__ */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.