![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to nd_devs.cpp CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Previous NeXT emulator] / previous_trunk / src / dimension|
Return to nd_devs.cpp CVS log | Up to [Previous NeXT emulator] / previous_trunk / src / dimension |
1.1 root 1: #include <stdio.h>
2: #include <limits.h>
3: #include <stdlib.h>
4:
5: #include "main.h"
6: #include "configuration.h"
7: #include "m68000.h"
8: #include "sysdeps.h"
9: #include "dimension.hpp"
10: #include "nd_mem.hpp"
11: #include "nd_nbic.hpp"
12: #include "i860cfg.h"
13: #include "nd_sdl.hpp"
14: #include "ramdac.h"
15: #include "host.h"
16:
17: /* --------- NEXTDIMENSION DEVICES ---------- */
18:
19: /* Device registers */
20:
21: /* Memory controller */
22: #define ND_MC_CSR0 0xFF800000
23: #define ND_MC_CSR1 0xFF800010
24: #define ND_MC_CSR2 0xFF800020
25: #define ND_MC_SID 0xFF800030
26:
27: #define ND_MC_DMA_CSR 0xFF801000
28:
29: #define ND_MC_VRAM_TIMING 0xFF802000
30: #define ND_MC_DRAM_SIZE 0xFF803000
31:
32: /* CSR bits */
33: #define CSR0_i860PIN_RESET 0x00000001
34: #define CSR0_i860PIN_CS8 0x00000002
35: #define CSR0_i860_IMASK 0x00000004
36: #define CSR0_i860_INT 0x00000008
37: #define CSR0_BE_IMASK 0x00000010
38: #define CSR0_BE_INT 0x00000020
39: #define CSR0_VBL_IMASK 0x00000040
40: #define CSR0_VBL_INT 0x00000080
41: #define CSR0_VBLANK 0x00000100 /* ro */
42: #define CSR0_VIOVBL_IMASK 0x00000200
43: #define CSR0_VIOVBL_INT 0x00000400
44: #define CSR0_VIOBLANK 0x00000800 /* ro */
45: #define CSR0_i860_CACHE_EN 0x00001000
46:
47: #define CSR1_CPU_INT 0x00000001
48:
49: #define CSR2_GLOBAL_ACCESS 0x00000001
50:
51: #define SID_SID_MASK 0x0000000F
52: #define SID_STEP_MASK 0x000000F0
53:
54: #define CSRDMA_VISIBLE_EN 0x00000001
55: #define CSRDMA_BLANKED_EN 0x00000002
56: #define CSRDMA_READ_EN 0x00000004
57:
58: #define CSRVRAM_VBLANK 0x00000001
59: #define CSRVRAM_60HZ 0x00000002
60: #define CSRVRAM_EXT_SYNC 0x00000004
61:
62: #define CSRDRAM_4MBIT 0x00000001
63:
64: #define DP_IIC_MORE 0x20000000
65: #define DP_IIC_BUSY 0x80000000
66:
67: #define DP_CSR_MASK_DIS 0x01
68: #define DP_CSR_NTSC 0x02 /* 0 = NTSC, 1 = PAL */
69: #define DP_CSR_JPEG_MASK 0xFC
70:
71: MC::MC(NextDimension* nd) : nd(nd) {}
72:
73: void MC::init(void) {
74: csr0 = CSR0_i860PIN_CS8;
75: csr1 = 0;
76: csr2 = 0;
77: sid = nd->slot|(ND_STEP<<4);
78: dma_csr = 0;
79: dma_start = 0;
80: dma_width = 0;
81: dma_pstart = 0;
82: dma_pwidth = 0;
83: dma_sstart = 0;
84: dma_swidth = 0;
85: dma_bsstart = 0;
86: dma_bswidth = 0;
87: dma_top = 0;
88: dma_bottom = 0;
89: dma_line_a = 0;
90: dma_curr_a = 0;
91: dma_scurr_a = 0;
92: dma_out_a = 0;
93: vram = 0;
94: dram = 0;
95: }
96:
97: DP::DP(NextDimension* nd) : nd(nd) {}
98:
99: void DP::init(void) {
100: iic_msgsz = 0;
101: iic_addr = 0;
102: csr = 0;
103: alpha = 0;
104: dma = 0;
105: cpu_x = 0xc;
106: cpu_y = 0xc;
107: dma_x = 0xd;
108: dma_y = 0xd;
109: iic_stat_addr = 0;
110: iic_data = 0;
111: }
112:
113:
114: static const char* ND_CSR0_BITS[] = {
115: "i860PIN_RESET", "i860PIN_CS8", "i860_IMASK", "i860_INT",
116: "BE_IMASK", "BE_INT", "VBL_IMASK", "VBL_INT",
117: "VBLANK", "VIOVBL_IMASK", "VIOVBL_INT", "VIOBLANK",
118: "i860_CACHE_EN", "00002000", "00004000", "00008000",
119: "00010000", "00020000", "00040000", "00080000",
120: "00100000", "00200000", "00400000", "00800000",
121: "01000000", "02000000", "04000000", "08000000",
122: "10000000", "20000000", "40000000", "80000000",
123: };
124:
125: static const char* ND_CSR1_BITS[] = {
126: "CPU_INT", "00000002", "00000004", "00000008",
127: "00000010", "00000020", "00000040", "00000080",
128: "00000100", "00000200", "00000400", "00000800",
129: "00001000", "00002000", "00004000", "00008000",
130: "00010000", "00020000", "00040000", "00080000",
131: "00100000", "00200000", "00400000", "00800000",
132: "01000000", "02000000", "04000000", "08000000",
133: "10000000", "20000000", "40000000", "80000000",
134: };
135:
136: static const char* ND_CSR2_BITS[] = {
137: "GLOBAL_ACCESS", "00000002", "00000004", "00000008",
138: "00000010", "00000020", "00000040", "00000080",
139: "00000100", "00000200", "00000400", "00000800",
140: "00001000", "00002000", "00004000", "00008000",
141: "00010000", "00020000", "00040000", "00080000",
142: "00100000", "00200000", "00400000", "00800000",
143: "01000000", "02000000", "04000000", "08000000",
144: "10000000", "20000000", "40000000", "80000000",
145: };
146:
147: static const char* ND_DMA_CSR_BITS[] = {
148: "VISIBLE_EN", "BLANKED_EN", "READ_EN", "00000008",
149: "00000010", "00000020", "00000040", "00000080",
150: "00000100", "00000200", "00000400", "00000800",
151: "00001000", "00002000", "00004000", "00008000",
152: "00010000", "00020000", "00040000", "00080000",
153: "00100000", "00200000", "00400000", "00800000",
154: "01000000", "02000000", "04000000", "08000000",
155: "10000000", "20000000", "40000000", "80000000",
156: };
157:
158: static const char* ND_VRAM_BITS[] = {
159: "VBLANK", "60HZ", "EXT_SYNC", "00000008",
160: "00000010", "00000020", "00000040", "00000080",
161: "00000100", "00000200", "00000400", "00000800",
162: "00001000", "00002000", "00004000", "00008000",
163: "00010000", "00020000", "00040000", "00080000",
164: "00100000", "00200000", "00400000", "00800000",
165: "01000000", "02000000", "04000000", "08000000",
166: "10000000", "20000000", "40000000", "80000000",
167: };
168:
169: static const char* ND_DRAM_BITS[] = {
170: "4MBIT", "00000002", "00000004", "00000008",
171: "00000010", "00000020", "00000040", "00000080",
172: "00000100", "00000200", "00000400", "00000800",
173: "00001000", "00002000", "00004000", "00008000",
174: "00010000", "00020000", "00040000", "00080000",
175: "00100000", "00200000", "00400000", "00800000",
176: "01000000", "02000000", "04000000", "08000000",
177: "10000000", "20000000", "40000000", "80000000",
178: };
179:
180: static const char* decodeBits(const char** bits, uae_u32 val) {
181: static char buffer[512];
182: char* result = buffer;
183:
184: if(bits) {
185: *result = 0;
186: for(int i = 0; i < 32; i++) {
187: if(val & (1 << i)) {
188: const char* str = bits[i];
189: while(*str) *result++ = *str++;
190: *result++ = '|';
191: }
192: }
193: if(result != buffer)
194: *--result = 0;
195: }
196: else
197: sprintf(buffer, "%08X", val);
198: return buffer;
199: }
200:
201: static const char* MC_RD_FORMAT = "[ND] Memory controller %s read %08X at %08X";
202: static const char* MC_RD_FORMAT_S = "[ND] Memory controller %s read (%s) at %08X";
203:
204: Uint32 MC::read(Uint32 addr) {
205: switch (addr&0x3FFF) {
206: case 0x0000:
207: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr0", decodeBits(ND_CSR0_BITS, csr0),addr);
208: return csr0;
209: case 0x0010:
210: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr1", decodeBits(ND_CSR1_BITS, csr1),addr);
211: return csr1;
212: case 0x0020:
213: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"csr2", decodeBits(ND_CSR2_BITS, csr2),addr);
214: return csr2;
215: case 0x0030:
216: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"sid", sid,addr);
217: return sid;
218: case 0x1000:
219: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"dma_csr", decodeBits(ND_DMA_CSR_BITS, dma_csr),addr);
220: return dma_csr;
221: case 0x1010:
222: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_start", dma_start,addr);
223: return dma_start;
224: case 0x1020:
225: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_width", dma_width,addr);
226: return dma_width;
227: case 0x1030:
228: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_pstart", dma_pstart,addr);
229: return dma_pstart;
230: case 0x1040:
231: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_pwidth", dma_pwidth,addr);
232: return dma_pwidth;
233: case 0x1050:
234: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_sstart", dma_sstart,addr);
235: return dma_sstart;
236: case 0x1060:
237: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_swidth", dma_swidth,addr);
238: return dma_swidth;
239: case 0x1070:
240: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_bsstart", dma_bsstart,addr);
241: return dma_bsstart;
242: case 0x1080:
243: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_bswidth", dma_bswidth,addr);
244: return dma_bswidth;
245: case 0x1090:
246: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_top", dma_top,addr);
247: return dma_top;
248: case 0x10A0:
249: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_bottom", dma_bottom,addr);
250: return dma_bottom;
251: case 0x10B0:
252: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_line_a", dma_line_a,addr);
253: return dma_line_a;
254: case 0x10C0:
255: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_curr_a", dma_curr_a,addr);
256: return dma_curr_a;
257: case 0x10D0:
258: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_line_a", dma_line_a,addr);
259: return dma_line_a;
260: case 0x10E0:
261: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_scurr_a", dma_scurr_a,addr);
262: return dma_scurr_a;
263: case 0x10F0:
264: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT,"dma_out_a", dma_out_a,addr);
265: return dma_out_a;
266: case 0x2000:
267: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"vram", decodeBits(ND_VRAM_BITS, vram),addr);
268: return vram;
269: case 0x3000:
270: Log_Printf(ND_LOG_IO_RD, MC_RD_FORMAT_S,"dram", decodeBits(ND_DRAM_BITS, dram),addr);
271: return dram;
272: default:
273: Log_Printf(LOG_WARN, "[ND] Memory controller UNKNOWN read at %08X",addr);
274: break;
275: }
276: return 0;
277: }
278:
279: static const char* MC_WR_FORMAT = "[ND] Memory controller %s write %08X at %08X";
280: static const char* MC_WR_FORMAT_S = "[ND] Memory controller %s write (%s) at %08X";
281:
282: void MC::write(Uint32 addr, Uint32 val) {
283: switch (addr&0x3FFF) {
284: case 0x0000:
285: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr0", decodeBits(ND_CSR0_BITS, val), addr);
286: if(val & CSR0_i860PIN_RESET) {
287: nd->send_msg(MSG_I860_RESET);
288: val &= ~CSR0_i860PIN_RESET;
289: }
290: if ((val & CSR0_i860_INT) && (val & CSR0_i860_IMASK))
291: nd->send_msg(MSG_INTR);
292:
293: if((val & CSR0_BE_INT) && (val & CSR0_BE_IMASK))
294: nd->send_msg(MSG_INTR);
295:
296: csr0 = val;
297: break;
298: case 0x0010:
299: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr1", decodeBits(ND_CSR1_BITS, val),addr);
300: csr1 = val;
301: if (csr1&CSR1_CPU_INT) {
302: nd->nbic.set_intstatus(true);
303: } else {
304: nd->nbic.set_intstatus(false);
305: }
306: break;
307: case 0x0020:
308: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"csr2", decodeBits(ND_CSR2_BITS, val),addr);
309: csr2 = val;
310: break;
311: case 0x0030:
312: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"sid", val,addr);
313: sid = val;
314: break;
315: case 0x1000:
316: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"dma_csr", decodeBits(ND_DMA_CSR_BITS, val),addr);
317: dma_csr = val;
318: break;
319: case 0x1010:
320: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_start", val,addr);
321: dma_start = val;
322: break;
323: case 0x1020:
324: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_width", val,addr);
325: dma_width = val;
326: break;
327: case 0x1030:
328: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_pstart", val,addr);
329: dma_pstart = val;
330: break;
331: case 0x1040:
332: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_pwidth", val,addr);
333: dma_pwidth = val;
334: break;
335: case 0x1050:
336: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_sstart", val,addr);
337: dma_sstart = val;
338: break;
339: case 0x1060:
340: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_swidth", val,addr);
341: dma_swidth = val;
342: break;
343: case 0x1070:
344: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_bsstart", val,addr);
345: dma_bsstart = val;
346: break;
347: case 0x1080:
348: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_bswidth", val,addr);
349: dma_bswidth = val;
350: break;
351: case 0x1090:
352: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_top", val,addr);
353: dma_top = val;
354: break;
355: case 0x10A0:
356: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_bottom", val,addr);
357: dma_bottom = val;
358: break;
359: case 0x10B0:
360: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_line_a", val,addr);
361: dma_line_a = val;
362: break;
363: case 0x10C0:
364: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_curr_a", val,addr);
365: dma_curr_a = val;
366: break;
367: case 0x10D0:
368: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_line_a", val,addr);
369: dma_line_a = val;
370: break;
371: case 0x10E0:
372: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_scurr_a", val,addr);
373: dma_scurr_a = val;
374: break;
375: case 0x10F0:
376: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT,"dma_out_a", val,addr);
377: dma_out_a = val;
378: break;
379: case 0x2000:
380: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"vram", decodeBits(ND_VRAM_BITS, val),addr);
381: vram = val;
382: break;
383: case 0x3000:
384: Log_Printf(ND_LOG_IO_WR, MC_WR_FORMAT_S,"dram", decodeBits(ND_DRAM_BITS, val),addr);
385: dram = val;
386: break;
387: default:
388: Log_Printf(LOG_WARN, "[ND] Memory controller UNKNOWN write at %08X",addr);
389: break;
390: }
391: }
392:
393: /* NeXTdimension data path */
394:
395: void DP::iicmsg(void) {
396: Log_Printf(LOG_NONE, "[ND] data path IIC msg addr:%02X msg[%d]=%02X",
397: iic_addr, iic_msgsz-1, iic_msg);
398:
399: nd->video_dev_write(iic_addr, iic_msgsz-1, iic_msg);
400: }
401:
402: Uint32 DP::lget(Uint32 addr) {
403: switch(addr) {
404: case 0x300: case 0x304: case 0x308: case 0x30C:
405: case 0x310: case 0x314: case 0x318: case 0x31C:
406: case 0x320: case 0x324: case 0x328: case 0x32C:
407: case 0x330: case 0x334: case 0x338: case 0x33C:
408: return doff;
409: case 0x340:
410: return csr;
411: case 0x344:
412: return alpha;
413: case 0x348:
414: return dma;
415: case 0x350:
416: return cpu_x;
417: case 0x354:
418: return cpu_y;
419: case 0x358:
420: return dma_x;
421: case 0x35C:
422: return dma_y;
423: case 0x360:
424: if(iic_busy <= 0)
425: iic_stat_addr &= ~DP_IIC_BUSY;
426: else
427: iic_busy--;
428: return iic_stat_addr;
429: case 0x364:
430: return 0;
431: default:
432: Log_Printf(LOG_WARN, "[ND] data path UNKNOWN read at %08X",addr);
433: }
434: return 0;
435: }
436:
437: void DP::lput(Uint32 addr, Uint32 v) {
438: switch(addr) {
439: case 0x300: case 0x304: case 0x308: case 0x30C:
440: case 0x310: case 0x314: case 0x318: case 0x31C:
441: case 0x320: case 0x324: case 0x328: case 0x32C:
442: case 0x330: case 0x334: case 0x338: case 0x33C:
443: doff = v;
444: break;
445: case 0x340:
446: csr = v;
447: break;
448: case 0x344:
449: alpha = v;
450: break;
451: case 0x348:
452: dma = v;
453: break;
454: case 0x350:
455: cpu_x = v;
456: break;
457: case 0x354:
458: cpu_y = v;
459: break;
460: case 0x358:
461: dma_x = v;
462: break;
463: case 0x35C:
464: dma_y = v;
465: break;
466: case 0x360:
467: iic_msgsz = 0;
468: iic_addr = (v >> 8) & 0xFF;
469: iic_msg = v;
470: iic_msgsz++;
471: iic_stat_addr |= DP_IIC_BUSY;
472: iic_busy = 10;
473: iicmsg();
474: break;
475: case 0x364:
476: iic_msg = v;
477: iic_msgsz++;
478: iic_stat_addr |= DP_IIC_BUSY;
479: iic_busy = 10;
480: iicmsg();
481: break;
482: default:
483: Log_Printf(LOG_WARN, "[ND] data path UNKNOWN write at %08X %08X",addr,v);
484: }
485: }
486:
487: void NextDimension::set_blank_state(int src, bool state) {
488: switch (src) {
489: case ND_DISPLAY:
490: if(state) {
491: mc.csr0 |= CSR0_VBL_INT | CSR0_VBLANK;
492: if (mc.csr0 & CSR0_VBL_IMASK) {
493: send_msg(MSG_INTR);
494: }
495: } else {
496: mc.csr0 &= ~CSR0_VBLANK;
497: }
498: break;
499: case ND_VIDEO:
500: if(state) {
501: mc.csr0 |= CSR0_VIOVBL_INT | CSR0_VIOBLANK;
502: if (mc.csr0 & CSR0_VIOVBL_IMASK) {
503: send_msg(MSG_INTR);
504: }
505: } else {
506: mc.csr0 &= ~CSR0_VIOBLANK;
507: }
508: break;
509: }
510: }
511:
512: static const char* nd_dump_path = "nd_memory.bin";
513:
514: /* debugger stuff */
515: bool NextDimension::dbg_cmd(const char* buf) {
516: if(!(buf)) {
517: fprintf(stderr,
518: " w: write NeXTdimension DRAM to file '%s'\n"
519: " n: dump NeXTdimension registers\n"
520: , nd_dump_path);
521: return false;
522: }
523:
524: switch(buf[0]) {
525: case 'w': {
526: FILE* fp = fopen(nd_dump_path, "wb");
527: size_t size = ConfigureParams.Dimension.board[ND_NUM(slot)].nMemoryBankSize[0];
528: size += ConfigureParams.Dimension.board[ND_NUM(slot)].nMemoryBankSize[1];
529: size += ConfigureParams.Dimension.board[ND_NUM(slot)].nMemoryBankSize[2];
530: size += ConfigureParams.Dimension.board[ND_NUM(slot)].nMemoryBankSize[3];
531: fprintf(stderr, "Writing %"FMT_zu"MB to '%s'...", size, nd_dump_path);
532: size <<= 20;
533: fwrite(ram, sizeof(Uint8), size, fp);
534: fclose(fp);
535: fprintf(stderr, "done.");
536: return true;
537: }
538: case 'n': {
539: fprintf(stderr, "csr0 (%s)\n", decodeBits(ND_CSR0_BITS, mc.csr0));
540: fprintf(stderr, "csr1 (%s)\n", decodeBits(ND_CSR1_BITS, mc.csr1));
541: fprintf(stderr, "csr2 (%s)\n", decodeBits(ND_CSR2_BITS, mc.csr2));
542: fprintf(stderr, "sid (%s)\n", decodeBits(0, mc.sid));
543: fprintf(stderr, "dma_csr (%s)\n", decodeBits(ND_DMA_CSR_BITS, mc.dma_csr));
544: fprintf(stderr, "dma_start (%s)\n", decodeBits(0, mc.dma_start));
545: fprintf(stderr, "dma_width (%s)\n", decodeBits(0, mc.dma_width));
546: fprintf(stderr, "dma_pstart (%s)\n", decodeBits(0, mc.dma_pstart));
547: fprintf(stderr, "dma_pwidth (%s)\n", decodeBits(0, mc.dma_pwidth));
548: fprintf(stderr, "dma_sstart (%s)\n", decodeBits(0, mc.dma_sstart));
549: fprintf(stderr, "dma_swidth (%s)\n", decodeBits(0, mc.dma_swidth));
550: fprintf(stderr, "dma_bsstart (%s)\n", decodeBits(0, mc.dma_bsstart));
551: fprintf(stderr, "dma_bswidth (%s)\n", decodeBits(0, mc.dma_bswidth));
552: fprintf(stderr, "dma_top (%s)\n", decodeBits(0, mc.dma_top));
553: fprintf(stderr, "dma_bottom (%s)\n", decodeBits(0, mc.dma_bottom));
554: fprintf(stderr, "dma_line_a (%s)\n", decodeBits(0, mc.dma_line_a));
555: fprintf(stderr, "dma_curr_a (%s)\n", decodeBits(0, mc.dma_curr_a));
556: fprintf(stderr, "dma_scurr_a (%s)\n", decodeBits(0, mc.dma_scurr_a));
557: fprintf(stderr, "dma_out_a (%s)\n", decodeBits(0, mc.dma_out_a));
558: fprintf(stderr, "vram (%s)\n", decodeBits(ND_VRAM_BITS, mc.vram));
559: fprintf(stderr, "dram (%s)\n", decodeBits(ND_DRAM_BITS, mc.dram));
560: return true;
561: }
562: default:
563: return false;
564: }
565: }
566:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.