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1.1 root 1: /*
2: DSP M56001 emulation
3: Instructions interpreter
4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this program; if not, write to the Free Software
19: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
22: /*
23: DSP memory mapping (FIXME: This is mostly a guess)
24: ------------------
25:
26: The memory map is configured as follows :
27:
28: 0x0000 to 0x7fff:
29: Program space P and data spaces X and Y are contiguous
30: 8k dsp Word blocks. They overlap in physical memory.
31:
32: 0x8000 to 0xffff:
33: X and Y data spaces are physically separate 4k dsp Word
34: blocks. Program space P is a contiguous 8k dsp Word block
35: and phyically overlaps X and Y data space.
36: Y: memory is mapped at address $8000 in P memory
37: X: memory is mapped at address $9000 in P memory
38:
39: FIXME: Is this true for NeXT?:
40: The DSP external RAM is zero waitstate, but there is a penalty for
41: accessing it twice or more in a single instruction, because there is only
42: one external data bus. The extra access costs 2 cycles penalty.
43:
44: The internal buses are all separate (0 waitstate)
45:
46: X: Y: P:
47: $ffff |--------------+--------------+--------------|
48: | Int. I/O | Ext. I/O | |
49: $ffc0 |--------------+--------------+ |
50: | | | |
51: | Mirror(8) | Mirror(8) | Mirror(4) |
52: | | | |
53: $A000 | | |--------------|
54: | | | |
55: | | | |
56: | | | 8k |
57: $9000 |--------------+--------------| External |
58: | 4k | 4k | RAM |
59: | External | External | |
60: | RAM | RAM | |
61: $8000 |--------------+--------------+--------------|
62: | | | |
63: | Mirror(4) | Mirror(4) | Mirror(4) |
64: | | | |
65: $2000 |--------------+--------------+--------------|
66: | 8k | 8k | 8k |
67: | External | External | External |
68: | RAM | RAM | RAM |
69: $0200 |--------------+--------------+--------------|
70: | Log table or | Sin table or | |
71: | external mem | external mem | Internal |
72: $0100 |--------------+--------------+ program |
73: | Internal X | Internal Y | memory |
74: | memory | memory | |
75: $0000 |--------------+--------------+--------------|
76:
77:
78: FIXME (NeXT): Special Note : As the Falcon DSP is a 0 waitstate access memory, I've simplified a little the cycle counting.
79: If this DSP emulator code is used in another project, one should take into account the bus control register (BCR) waitstates.
80: */
81:
82: #ifdef HAVE_CONFIG_H
83: #include "config.h"
84: #endif
85:
86: #include <stdbool.h>
87:
88: #include "main.h"
89: #include "dsp_core.h"
90: #include "dsp_cpu.h"
91: #include "dsp_disasm.h"
92: #include "log.h"
93: #include "debugui.h"
94:
95: #define DSP_COUNT_IPS 0 /* Count instruction per seconds */
96:
97:
98: /**********************************
99: * Defines
100: **********************************/
101:
102: #define SIGN_PLUS 0
103: #define SIGN_MINUS 1
104:
105: /* Defines some bits values for access to external memory (X, Y, P) */
106: /* These values will set/unset the corresponding bits in the variable access_to_ext_memory */
107: /* to detect how many access to the external memory were done for a single instruction */
108: #define EXT_X_MEMORY 0
109: #define EXT_Y_MEMORY 1
110: #define EXT_P_MEMORY 2
111:
112:
113: /**********************************
114: * Variables
115: **********************************/
116:
117: /* Instructions per second */
118: static Uint32 start_time;
119: static Uint32 num_inst;
120:
121: /* Length of current instruction */
122: static Uint32 cur_inst_len; /* =0:jump, >0:increment */
123:
124: /* Current instruction */
125: static Uint32 cur_inst;
126:
127: /* Counts the number of access to the external memory for one instruction */
128: static Uint16 access_to_ext_memory;
129:
130: /* DSP is in disasm mode ? */
131: /* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
132: static bool isDsp_in_disasm_mode;
133:
134: static char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
135: static Uint16 disasm_memory_ptr; /* Pointer for memory change in disasm mode */
136:
137: /**********************************
138: * Functions
139: **********************************/
140:
141: typedef void (*dsp_emul_t)(void);
142:
143: static void dsp_postexecute_update_pc(void);
144: static void dsp_postexecute_interrupts(void);
145:
146: static void dsp_setInterruptIPL(Uint32 value);
147:
148: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2);
149:
150: static Uint32 read_memory(int space, Uint16 address);
151: static inline Uint32 read_memory_p(Uint16 address);
152: static Uint32 read_memory_disasm(int space, Uint16 address);
153:
154: static inline void write_memory(int space, Uint16 address, Uint32 value);
155: static void write_memory_raw(int space, Uint16 address, Uint32 value);
156: static void write_memory_disasm(int space, Uint16 address, Uint32 value);
157:
158: static void dsp_write_reg(Uint32 numreg, Uint32 value);
159:
160: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly);
161: static void dsp_stack_pop(Uint32 *curpc, Uint32 *cursr);
162: static void dsp_compute_ssh_ssl(void);
163:
164: static void opcode8h_0(void);
165:
166: static void dsp_update_rn(Uint32 numreg, Sint16 modifier);
167: static void dsp_update_rn_bitreverse(Uint32 numreg);
168: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier);
169: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr);
170: static int dsp_calc_cc(Uint32 cc_code);
171:
172: static void dsp_undefined(void);
173:
174: /* Instructions without parallel moves */
175: static void dsp_andi(void);
176: static void dsp_bchg_aa(void);
177: static void dsp_bchg_ea(void);
178: static void dsp_bchg_pp(void);
179: static void dsp_bchg_reg(void);
180: static void dsp_bclr_aa(void);
181: static void dsp_bclr_ea(void);
182: static void dsp_bclr_pp(void);
183: static void dsp_bclr_reg(void);
184: static void dsp_bset_aa(void);
185: static void dsp_bset_ea(void);
186: static void dsp_bset_pp(void);
187: static void dsp_bset_reg(void);
188: static void dsp_btst_aa(void);
189: static void dsp_btst_ea(void);
190: static void dsp_btst_pp(void);
191: static void dsp_btst_reg(void);
192: static void dsp_div(void);
193: static void dsp_enddo(void);
194: static void dsp_illegal(void);
195: static void dsp_jcc_imm(void);
196: static void dsp_jcc_ea(void);
197: static void dsp_jclr_aa(void);
198: static void dsp_jclr_ea(void);
199: static void dsp_jclr_pp(void);
200: static void dsp_jclr_reg(void);
201: static void dsp_jmp_ea(void);
202: static void dsp_jmp_imm(void);
203: static void dsp_jscc_ea(void);
204: static void dsp_jscc_imm(void);
205: static void dsp_jsclr_aa(void);
206: static void dsp_jsclr_ea(void);
207: static void dsp_jsclr_pp(void);
208: static void dsp_jsclr_reg(void);
209: static void dsp_jset_aa(void);
210: static void dsp_jset_ea(void);
211: static void dsp_jset_pp(void);
212: static void dsp_jset_reg(void);
213: static void dsp_jsr_ea(void);
214: static void dsp_jsr_imm(void);
215: static void dsp_jsset_aa(void);
216: static void dsp_jsset_ea(void);
217: static void dsp_jsset_pp(void);
218: static void dsp_jsset_reg(void);
219: static void dsp_lua(void);
220: static void dsp_movem_ea(void);
221: static void dsp_movem_aa(void);
222: static void dsp_nop(void);
223: static void dsp_norm(void);
224: static void dsp_ori(void);
225: static void dsp_reset(void);
226: static void dsp_rti(void);
227: static void dsp_rts(void);
228: static void dsp_stop(void);
229: static void dsp_swi(void);
230: static void dsp_tcc(void);
231: static void dsp_wait(void);
232:
233: static void dsp_do_ea(void);
234: static void dsp_do_aa(void);
235: static void dsp_do_imm(void);
236: static void dsp_do_reg(void);
237: static void dsp_rep_aa(void);
238: static void dsp_rep_ea(void);
239: static void dsp_rep_imm(void);
240: static void dsp_rep_reg(void);
241: static void dsp_movec_aa(void);
242: static void dsp_movec_ea(void);
243: static void dsp_movec_imm(void);
244: static void dsp_movec_reg(void);
245: static void dsp_movep_0(void);
246: static void dsp_movep_1(void);
247: static void dsp_movep_23(void);
248:
249: /* Parallel move analyzer */
250: static int dsp_pm_read_accu24(int numreg, Uint32 *dest);
251: static void dsp_pm_0(void);
252: static void dsp_pm_1(void);
253: static void dsp_pm_2(void);
254: static void dsp_pm_2_2(void);
255: static void dsp_pm_3(void);
256: static void dsp_pm_4(void);
257: static void dsp_pm_4x(void);
258: static void dsp_pm_5(void);
259: static void dsp_pm_8(void);
260:
261: /* 56bits arithmetic */
262: static Uint16 dsp_abs56(Uint32 *dest);
263: static Uint16 dsp_asl56(Uint32 *dest);
264: static Uint16 dsp_asr56(Uint32 *dest);
265: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest);
266: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest);
267: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe);
268: static void dsp_rnd56(Uint32 *dest);
269:
270: /* Instructions with parallel moves */
271: static void dsp_abs_a(void);
272: static void dsp_abs_b(void);
273: static void dsp_adc_x_a(void);
274: static void dsp_adc_x_b(void);
275: static void dsp_adc_y_a(void);
276: static void dsp_adc_y_b(void);
277: static void dsp_add_b_a(void);
278: static void dsp_add_a_b(void);
279: static void dsp_add_x_a(void);
280: static void dsp_add_x_b(void);
281: static void dsp_add_y_a(void);
282: static void dsp_add_y_b(void);
283: static void dsp_add_x0_a(void);
284: static void dsp_add_x0_b(void);
285: static void dsp_add_y0_a(void);
286: static void dsp_add_y0_b(void);
287: static void dsp_add_x1_a(void);
288: static void dsp_add_x1_b(void);
289: static void dsp_add_y1_a(void);
290: static void dsp_add_y1_b(void);
291: static void dsp_addl_b_a(void);
292: static void dsp_addl_b_a(void);
293: static void dsp_addl_a_b(void);
294: static void dsp_addr_b_a(void);
295: static void dsp_addr_a_b(void);
296: static void dsp_and_x0_a(void);
297: static void dsp_and_x0_b(void);
298: static void dsp_and_y0_a(void);
299: static void dsp_and_y0_b(void);
300: static void dsp_and_x1_a(void);
301: static void dsp_and_x1_b(void);
302: static void dsp_and_y1_a(void);
303: static void dsp_and_y1_b(void);
304: static void dsp_asl_a(void);
305: static void dsp_asl_b(void);
306: static void dsp_asr_a(void);
307: static void dsp_asr_b(void);
308: static void dsp_clr_a(void);
309: static void dsp_clr_b(void);
310: static void dsp_cmp_b_a(void);
311: static void dsp_cmp_a_b(void);
312: static void dsp_cmp_x0_a(void);
313: static void dsp_cmp_x0_b(void);
314: static void dsp_cmp_y0_a(void);
315: static void dsp_cmp_y0_b(void);
316: static void dsp_cmp_x1_a(void);
317: static void dsp_cmp_x1_b(void);
318: static void dsp_cmp_y1_a(void);
319: static void dsp_cmp_y1_b(void);
320: static void dsp_cmpm_b_a(void);
321: static void dsp_cmpm_a_b(void);
322: static void dsp_cmpm_x0_a(void);
323: static void dsp_cmpm_x0_b(void);
324: static void dsp_cmpm_y0_a(void);
325: static void dsp_cmpm_y0_b(void);
326: static void dsp_cmpm_x1_a(void);
327: static void dsp_cmpm_x1_b(void);
328: static void dsp_cmpm_y1_a(void);
329: static void dsp_cmpm_y1_b(void);
330: static void dsp_eor_x0_a(void);
331: static void dsp_eor_x0_b(void);
332: static void dsp_eor_y0_a(void);
333: static void dsp_eor_y0_b(void);
334: static void dsp_eor_x1_a(void);
335: static void dsp_eor_x1_b(void);
336: static void dsp_eor_y1_a(void);
337: static void dsp_eor_y1_b(void);
338: static void dsp_lsl_a(void);
339: static void dsp_lsl_b(void);
340: static void dsp_lsr_a(void);
341: static void dsp_lsr_b(void);
342: static void dsp_mac_p_x0_x0_a(void);
343: static void dsp_mac_m_x0_x0_a(void);
344: static void dsp_mac_p_x0_x0_b(void);
345: static void dsp_mac_m_x0_x0_b(void);
346: static void dsp_mac_p_y0_y0_a(void);
347: static void dsp_mac_m_y0_y0_a(void);
348: static void dsp_mac_p_y0_y0_b(void);
349: static void dsp_mac_m_y0_y0_b(void);
350: static void dsp_mac_p_x1_x0_a(void);
351: static void dsp_mac_m_x1_x0_a(void);
352: static void dsp_mac_p_x1_x0_b(void);
353: static void dsp_mac_m_x1_x0_b(void);
354: static void dsp_mac_p_y1_y0_a(void);
355: static void dsp_mac_m_y1_y0_a(void);
356: static void dsp_mac_p_y1_y0_b(void);
357: static void dsp_mac_m_y1_y0_b(void);
358: static void dsp_mac_p_x0_y1_a(void);
359: static void dsp_mac_m_x0_y1_a(void);
360: static void dsp_mac_p_x0_y1_b(void);
361: static void dsp_mac_m_x0_y1_b(void);
362: static void dsp_mac_p_y0_x0_a(void);
363: static void dsp_mac_m_y0_x0_a(void);
364: static void dsp_mac_p_y0_x0_b(void);
365: static void dsp_mac_m_y0_x0_b(void);
366: static void dsp_mac_p_x1_y0_a(void);
367: static void dsp_mac_m_x1_y0_a(void);
368: static void dsp_mac_p_x1_y0_b(void);
369: static void dsp_mac_m_x1_y0_b(void);
370: static void dsp_mac_p_y1_x1_a(void);
371: static void dsp_mac_m_y1_x1_a(void);
372: static void dsp_mac_p_y1_x1_b(void);
373: static void dsp_mac_m_y1_x1_b(void);
374: static void dsp_macr_p_x0_x0_a(void);
375: static void dsp_macr_m_x0_x0_a(void);
376: static void dsp_macr_p_x0_x0_b(void);
377: static void dsp_macr_m_x0_x0_b(void);
378: static void dsp_macr_p_y0_y0_a(void);
379: static void dsp_macr_m_y0_y0_a(void);
380: static void dsp_macr_p_y0_y0_b(void);
381: static void dsp_macr_m_y0_y0_b(void);
382: static void dsp_macr_p_x1_x0_a(void);
383: static void dsp_macr_m_x1_x0_a(void);
384: static void dsp_macr_p_x1_x0_b(void);
385: static void dsp_macr_m_x1_x0_b(void);
386: static void dsp_macr_p_y1_y0_a(void);
387: static void dsp_macr_m_y1_y0_a(void);
388: static void dsp_macr_p_y1_y0_b(void);
389: static void dsp_macr_m_y1_y0_b(void);
390: static void dsp_macr_p_x0_y1_a(void);
391: static void dsp_macr_m_x0_y1_a(void);
392: static void dsp_macr_p_x0_y1_b(void);
393: static void dsp_macr_m_x0_y1_b(void);
394: static void dsp_macr_p_y0_x0_a(void);
395: static void dsp_macr_m_y0_x0_a(void);
396: static void dsp_macr_p_y0_x0_b(void);
397: static void dsp_macr_m_y0_x0_b(void);
398: static void dsp_macr_p_x1_y0_a(void);
399: static void dsp_macr_m_x1_y0_a(void);
400: static void dsp_macr_p_x1_y0_b(void);
401: static void dsp_macr_m_x1_y0_b(void);
402: static void dsp_macr_p_y1_x1_a(void);
403: static void dsp_macr_m_y1_x1_a(void);
404: static void dsp_macr_p_y1_x1_b(void);
405: static void dsp_macr_m_y1_x1_b(void);
406: static void dsp_move(void);
407: static void dsp_mpy_p_x0_x0_a(void);
408: static void dsp_mpy_m_x0_x0_a(void);
409: static void dsp_mpy_p_x0_x0_b(void);
410: static void dsp_mpy_m_x0_x0_b(void);
411: static void dsp_mpy_p_y0_y0_a(void);
412: static void dsp_mpy_m_y0_y0_a(void);
413: static void dsp_mpy_p_y0_y0_b(void);
414: static void dsp_mpy_m_y0_y0_b(void);
415: static void dsp_mpy_p_x1_x0_a(void);
416: static void dsp_mpy_m_x1_x0_a(void);
417: static void dsp_mpy_p_x1_x0_b(void);
418: static void dsp_mpy_m_x1_x0_b(void);
419: static void dsp_mpy_p_y1_y0_a(void);
420: static void dsp_mpy_m_y1_y0_a(void);
421: static void dsp_mpy_p_y1_y0_b(void);
422: static void dsp_mpy_m_y1_y0_b(void);
423: static void dsp_mpy_p_x0_y1_a(void);
424: static void dsp_mpy_m_x0_y1_a(void);
425: static void dsp_mpy_p_x0_y1_b(void);
426: static void dsp_mpy_m_x0_y1_b(void);
427: static void dsp_mpy_p_y0_x0_a(void);
428: static void dsp_mpy_m_y0_x0_a(void);
429: static void dsp_mpy_p_y0_x0_b(void);
430: static void dsp_mpy_m_y0_x0_b(void);
431: static void dsp_mpy_p_x1_y0_a(void);
432: static void dsp_mpy_m_x1_y0_a(void);
433: static void dsp_mpy_p_x1_y0_b(void);
434: static void dsp_mpy_m_x1_y0_b(void);
435: static void dsp_mpy_p_y1_x1_a(void);
436: static void dsp_mpy_m_y1_x1_a(void);
437: static void dsp_mpy_p_y1_x1_b(void);
438: static void dsp_mpy_m_y1_x1_b(void);
439: static void dsp_mpyr_p_x0_x0_a(void);
440: static void dsp_mpyr_m_x0_x0_a(void);
441: static void dsp_mpyr_p_x0_x0_b(void);
442: static void dsp_mpyr_m_x0_x0_b(void);
443: static void dsp_mpyr_p_y0_y0_a(void);
444: static void dsp_mpyr_m_y0_y0_a(void);
445: static void dsp_mpyr_p_y0_y0_b(void);
446: static void dsp_mpyr_m_y0_y0_b(void);
447: static void dsp_mpyr_p_x1_x0_a(void);
448: static void dsp_mpyr_m_x1_x0_a(void);
449: static void dsp_mpyr_p_x1_x0_b(void);
450: static void dsp_mpyr_m_x1_x0_b(void);
451: static void dsp_mpyr_p_y1_y0_a(void);
452: static void dsp_mpyr_m_y1_y0_a(void);
453: static void dsp_mpyr_p_y1_y0_b(void);
454: static void dsp_mpyr_m_y1_y0_b(void);
455: static void dsp_mpyr_p_x0_y1_a(void);
456: static void dsp_mpyr_m_x0_y1_a(void);
457: static void dsp_mpyr_p_x0_y1_b(void);
458: static void dsp_mpyr_m_x0_y1_b(void);
459: static void dsp_mpyr_p_y0_x0_a(void);
460: static void dsp_mpyr_m_y0_x0_a(void);
461: static void dsp_mpyr_p_y0_x0_b(void);
462: static void dsp_mpyr_m_y0_x0_b(void);
463: static void dsp_mpyr_p_x1_y0_a(void);
464: static void dsp_mpyr_m_x1_y0_a(void);
465: static void dsp_mpyr_p_x1_y0_b(void);
466: static void dsp_mpyr_m_x1_y0_b(void);
467: static void dsp_mpyr_p_y1_x1_a(void);
468: static void dsp_mpyr_m_y1_x1_a(void);
469: static void dsp_mpyr_p_y1_x1_b(void);
470: static void dsp_mpyr_m_y1_x1_b(void);
471: static void dsp_neg_a(void);
472: static void dsp_neg_b(void);
473: static void dsp_not_a(void);
474: static void dsp_not_b(void);
475: static void dsp_or_x0_a(void);
476: static void dsp_or_x0_b(void);
477: static void dsp_or_y0_a(void);
478: static void dsp_or_y0_b(void);
479: static void dsp_or_x1_a(void);
480: static void dsp_or_x1_b(void);
481: static void dsp_or_y1_a(void);
482: static void dsp_or_y1_b(void);
483: static void dsp_rnd_a(void);
484: static void dsp_rnd_b(void);
485: static void dsp_rol_a(void);
486: static void dsp_rol_b(void);
487: static void dsp_ror_a(void);
488: static void dsp_ror_b(void);
489: static void dsp_sbc_x_a(void);
490: static void dsp_sbc_x_b(void);
491: static void dsp_sbc_y_a(void);
492: static void dsp_sbc_y_b(void);
493: static void dsp_sub_b_a(void);
494: static void dsp_sub_a_b(void);
495: static void dsp_sub_x_a(void);
496: static void dsp_sub_x_b(void);
497: static void dsp_sub_y_a(void);
498: static void dsp_sub_y_b(void);
499: static void dsp_sub_x0_a(void);
500: static void dsp_sub_x0_b(void);
501: static void dsp_sub_y0_a(void);
502: static void dsp_sub_y0_b(void);
503: static void dsp_sub_x1_a(void);
504: static void dsp_sub_x1_b(void);
505: static void dsp_sub_y1_a(void);
506: static void dsp_sub_y1_b(void);
507: static void dsp_subl_a(void);
508: static void dsp_subl_b(void);
509: static void dsp_subr_a(void);
510: static void dsp_subr_b(void);
511: static void dsp_tfr_b_a(void);
512: static void dsp_tfr_a_b(void);
513: static void dsp_tfr_x0_a(void);
514: static void dsp_tfr_x0_b(void);
515: static void dsp_tfr_y0_a(void);
516: static void dsp_tfr_y0_b(void);
517: static void dsp_tfr_x1_a(void);
518: static void dsp_tfr_x1_b(void);
519: static void dsp_tfr_y1_a(void);
520: static void dsp_tfr_y1_b(void);
521: static void dsp_tst_a(void);
522: static void dsp_tst_b(void);
523:
524: static const dsp_emul_t opcodes8h[512] = {
525: /* 0x00 - 0x3f */
526: opcode8h_0, dsp_undefined, dsp_undefined, dsp_undefined, opcode8h_0, dsp_andi, dsp_undefined, dsp_ori,
527: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
528: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
529: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
530: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
531: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
532: dsp_undefined, dsp_undefined, dsp_div, dsp_div, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
533: dsp_norm, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
534:
535: /* 0x40 - 0x7f */
536: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
537: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
538: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
539: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
540: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
541: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
542: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
543: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
544:
545: /* 0x80 - 0xbf */
546: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
547: dsp_lua, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
548: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
549: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
550: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
551: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
552: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
553: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
554:
555: /* 0xc0 - 0xff */
556: dsp_do_aa, dsp_rep_aa, dsp_do_aa, dsp_rep_aa, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
557: dsp_do_ea, dsp_rep_ea, dsp_do_ea, dsp_rep_ea, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
558: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
559: dsp_do_reg, dsp_rep_reg, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
560: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
561: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
562: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
563: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
564:
565: /* 0x100 - 0x13f */
566: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
567: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
568: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
569: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
570: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
571: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
572: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
573: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
574:
575: /* 0x140 - 0x17f */
576: dsp_bclr_aa, dsp_bset_aa, dsp_bclr_aa, dsp_bset_aa, dsp_jclr_aa, dsp_jset_aa, dsp_jclr_aa, dsp_jset_aa,
577: dsp_bclr_ea, dsp_bset_ea, dsp_bclr_ea, dsp_bset_ea, dsp_jclr_ea, dsp_jset_ea, dsp_jclr_ea, dsp_jset_ea,
578: dsp_bclr_pp, dsp_bset_pp, dsp_bclr_pp, dsp_bset_pp, dsp_jclr_pp, dsp_jset_pp, dsp_jclr_pp, dsp_jset_pp,
579: dsp_jclr_reg, dsp_jset_reg, dsp_bclr_reg, dsp_bset_reg, dsp_jmp_ea, dsp_jcc_ea, dsp_undefined, dsp_undefined,
580: dsp_bchg_aa, dsp_btst_aa, dsp_bchg_aa, dsp_btst_aa, dsp_jsclr_aa, dsp_jsset_aa, dsp_jsclr_aa, dsp_jsset_aa,
581: dsp_bchg_ea, dsp_btst_ea, dsp_bchg_ea, dsp_btst_ea, dsp_jsclr_ea, dsp_jsset_ea, dsp_jsclr_ea, dsp_jsset_ea,
582: dsp_bchg_pp, dsp_btst_pp, dsp_bchg_pp, dsp_btst_pp, dsp_jsclr_pp, dsp_jsset_pp, dsp_jsclr_pp, dsp_jsset_pp,
583: dsp_jsclr_reg, dsp_jsset_reg, dsp_bchg_reg, dsp_btst_reg, dsp_jsr_ea, dsp_jscc_ea, dsp_undefined, dsp_undefined,
584:
585: /* 0x180 - 0x1bf */
586: dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm,
587: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
588: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
589: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
590: dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm,
591: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
592: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
593: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
594:
595: /* 0x1c0 - 0x1ff */
596: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
597: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
598: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
599: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
600: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
601: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
602: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
603: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
604: };
605:
606: static const dsp_emul_t opcodes_parmove[16] = {
607: dsp_pm_0, dsp_pm_1, dsp_pm_2, dsp_pm_3, dsp_pm_4, dsp_pm_5, dsp_pm_5, dsp_pm_5,
608: dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8
609: };
610:
611: static const dsp_emul_t opcodes_alu[256] = {
612: /* 0x00 - 0x3f */
613: dsp_move , dsp_tfr_b_a, dsp_addr_b_a, dsp_tst_a, dsp_undefined, dsp_cmp_b_a, dsp_subr_a, dsp_cmpm_b_a,
614: dsp_undefined, dsp_tfr_a_b, dsp_addr_a_b, dsp_tst_b, dsp_undefined, dsp_cmp_a_b, dsp_subr_b, dsp_cmpm_a_b,
615: dsp_add_b_a, dsp_rnd_a, dsp_addl_b_a, dsp_clr_a, dsp_sub_b_a, dsp_undefined, dsp_subl_a, dsp_not_a,
616: dsp_add_a_b, dsp_rnd_b, dsp_addl_a_b, dsp_clr_b, dsp_sub_a_b, dsp_undefined, dsp_subl_b, dsp_not_b,
617: dsp_add_x_a, dsp_adc_x_a, dsp_asr_a, dsp_lsr_a, dsp_sub_x_a, dsp_sbc_x_a, dsp_abs_a, dsp_ror_a,
618: dsp_add_x_b, dsp_adc_x_b, dsp_asr_b, dsp_lsr_b, dsp_sub_x_b, dsp_sbc_x_b, dsp_abs_b, dsp_ror_b,
619: dsp_add_y_a, dsp_adc_y_a, dsp_asl_a, dsp_lsl_a, dsp_sub_y_a, dsp_sbc_y_a, dsp_neg_a, dsp_rol_a,
620: dsp_add_y_b, dsp_adc_y_b, dsp_asl_b, dsp_lsl_b, dsp_sub_y_b, dsp_sbc_y_b, dsp_neg_b, dsp_rol_b,
621:
622: /* 0x40 - 0x7f */
623: dsp_add_x0_a, dsp_tfr_x0_a, dsp_or_x0_a, dsp_eor_x0_a, dsp_sub_x0_a, dsp_cmp_x0_a, dsp_and_x0_a, dsp_cmpm_x0_a,
624: dsp_add_x0_b, dsp_tfr_x0_b, dsp_or_x0_b, dsp_eor_x0_b, dsp_sub_x0_b, dsp_cmp_x0_b, dsp_and_x0_b, dsp_cmpm_x0_b,
625: dsp_add_y0_a, dsp_tfr_y0_a, dsp_or_y0_a, dsp_eor_y0_a, dsp_sub_y0_a, dsp_cmp_y0_a, dsp_and_y0_a, dsp_cmpm_y0_a,
626: dsp_add_y0_b, dsp_tfr_y0_b, dsp_or_y0_b, dsp_eor_y0_b, dsp_sub_y0_b, dsp_cmp_y0_b, dsp_and_y0_b, dsp_cmpm_y0_b,
627: dsp_add_x1_a, dsp_tfr_x1_a, dsp_or_x1_a, dsp_eor_x1_a, dsp_sub_x1_a, dsp_cmp_x1_a, dsp_and_x1_a, dsp_cmpm_x1_a,
628: dsp_add_x1_b, dsp_tfr_x1_b, dsp_or_x1_b, dsp_eor_x1_b, dsp_sub_x1_b, dsp_cmp_x1_b, dsp_and_x1_b, dsp_cmpm_x1_b,
629: dsp_add_y1_a, dsp_tfr_y1_a, dsp_or_y1_a, dsp_eor_y1_a, dsp_sub_y1_a, dsp_cmp_y1_a, dsp_and_y1_a, dsp_cmpm_y1_a,
630: dsp_add_y1_b, dsp_tfr_y1_b, dsp_or_y1_b, dsp_eor_y1_b, dsp_sub_y1_b, dsp_cmp_y1_b, dsp_and_y1_b, dsp_cmpm_y1_b,
631:
632: /* 0x80 - 0xbf */
633: dsp_mpy_p_x0_x0_a, dsp_mpyr_p_x0_x0_a, dsp_mac_p_x0_x0_a, dsp_macr_p_x0_x0_a, dsp_mpy_m_x0_x0_a, dsp_mpyr_m_x0_x0_a, dsp_mac_m_x0_x0_a, dsp_macr_m_x0_x0_a,
634: dsp_mpy_p_x0_x0_b, dsp_mpyr_p_x0_x0_b, dsp_mac_p_x0_x0_b, dsp_macr_p_x0_x0_b, dsp_mpy_m_x0_x0_b, dsp_mpyr_m_x0_x0_b, dsp_mac_m_x0_x0_b, dsp_macr_m_x0_x0_b,
635: dsp_mpy_p_y0_y0_a, dsp_mpyr_p_y0_y0_a, dsp_mac_p_y0_y0_a, dsp_macr_p_y0_y0_a, dsp_mpy_m_y0_y0_a, dsp_mpyr_m_y0_y0_a, dsp_mac_m_y0_y0_a, dsp_macr_m_y0_y0_a,
636: dsp_mpy_p_y0_y0_b, dsp_mpyr_p_y0_y0_b, dsp_mac_p_y0_y0_b, dsp_macr_p_y0_y0_b, dsp_mpy_m_y0_y0_b, dsp_mpyr_m_y0_y0_b, dsp_mac_m_y0_y0_b, dsp_macr_m_y0_y0_b,
637: dsp_mpy_p_x1_x0_a, dsp_mpyr_p_x1_x0_a, dsp_mac_p_x1_x0_a, dsp_macr_p_x1_x0_a, dsp_mpy_m_x1_x0_a, dsp_mpyr_m_x1_x0_a, dsp_mac_m_x1_x0_a, dsp_macr_m_x1_x0_a,
638: dsp_mpy_p_x1_x0_b, dsp_mpyr_p_x1_x0_b, dsp_mac_p_x1_x0_b, dsp_macr_p_x1_x0_b, dsp_mpy_m_x1_x0_b, dsp_mpyr_m_x1_x0_b, dsp_mac_m_x1_x0_b, dsp_macr_m_x1_x0_b,
639: dsp_mpy_p_y1_y0_a, dsp_mpyr_p_y1_y0_a, dsp_mac_p_y1_y0_a, dsp_macr_p_y1_y0_a, dsp_mpy_m_y1_y0_a, dsp_mpyr_m_y1_y0_a, dsp_mac_m_y1_y0_a, dsp_macr_m_y1_y0_a,
640: dsp_mpy_p_y1_y0_b, dsp_mpyr_p_y1_y0_b, dsp_mac_p_y1_y0_b, dsp_macr_p_y1_y0_b, dsp_mpy_m_y1_y0_b, dsp_mpyr_m_y1_y0_b, dsp_mac_m_y1_y0_b, dsp_macr_m_y1_y0_b,
641:
642: /* 0xc0_m_ 0xff */
643: dsp_mpy_p_x0_y1_a, dsp_mpyr_p_x0_y1_a, dsp_mac_p_x0_y1_a, dsp_macr_p_x0_y1_a, dsp_mpy_m_x0_y1_a, dsp_mpyr_m_x0_y1_a, dsp_mac_m_x0_y1_a, dsp_macr_m_x0_y1_a,
644: dsp_mpy_p_x0_y1_b, dsp_mpyr_p_x0_y1_b, dsp_mac_p_x0_y1_b, dsp_macr_p_x0_y1_b, dsp_mpy_m_x0_y1_b, dsp_mpyr_m_x0_y1_b, dsp_mac_m_x0_y1_b, dsp_macr_m_x0_y1_b,
645: dsp_mpy_p_y0_x0_a, dsp_mpyr_p_y0_x0_a, dsp_mac_p_y0_x0_a, dsp_macr_p_y0_x0_a, dsp_mpy_m_y0_x0_a, dsp_mpyr_m_y0_x0_a, dsp_mac_m_y0_x0_a, dsp_macr_m_y0_x0_a,
646: dsp_mpy_p_y0_x0_b, dsp_mpyr_p_y0_x0_b, dsp_mac_p_y0_x0_b, dsp_macr_p_y0_x0_b, dsp_mpy_m_y0_x0_b, dsp_mpyr_m_y0_x0_b, dsp_mac_m_y0_x0_b, dsp_macr_m_y0_x0_b,
647: dsp_mpy_p_x1_y0_a, dsp_mpyr_p_x1_y0_a, dsp_mac_p_x1_y0_a, dsp_macr_p_x1_y0_a, dsp_mpy_m_x1_y0_a, dsp_mpyr_m_x1_y0_a, dsp_mac_m_x1_y0_a, dsp_macr_m_x1_y0_a,
648: dsp_mpy_p_x1_y0_b, dsp_mpyr_p_x1_y0_b, dsp_mac_p_x1_y0_b, dsp_macr_p_x1_y0_b, dsp_mpy_m_x1_y0_b, dsp_mpyr_m_x1_y0_b, dsp_mac_m_x1_y0_b, dsp_macr_m_x1_y0_b,
649: dsp_mpy_p_y1_x1_a, dsp_mpyr_p_y1_x1_a, dsp_mac_p_y1_x1_a, dsp_macr_p_y1_x1_a, dsp_mpy_m_y1_x1_a, dsp_mpyr_m_y1_x1_a, dsp_mac_m_y1_x1_a, dsp_macr_m_y1_x1_a,
650: dsp_mpy_p_y1_x1_b, dsp_mpyr_p_y1_x1_b, dsp_mac_p_y1_x1_b, dsp_macr_p_y1_x1_b, dsp_mpy_m_y1_x1_b, dsp_mpyr_m_y1_x1_b, dsp_mac_m_y1_x1_b, dsp_macr_m_y1_x1_b
651: };
652:
653: static const int registers_tcc[16][2] = {
654: {DSP_REG_B,DSP_REG_A},
655: {DSP_REG_A,DSP_REG_B},
656: {DSP_REG_NULL,DSP_REG_NULL},
657: {DSP_REG_NULL,DSP_REG_NULL},
658:
659: {DSP_REG_NULL,DSP_REG_NULL},
660: {DSP_REG_NULL,DSP_REG_NULL},
661: {DSP_REG_NULL,DSP_REG_NULL},
662: {DSP_REG_NULL,DSP_REG_NULL},
663:
664: {DSP_REG_X0,DSP_REG_A},
665: {DSP_REG_X0,DSP_REG_B},
666: {DSP_REG_Y0,DSP_REG_A},
667: {DSP_REG_Y0,DSP_REG_B},
668:
669: {DSP_REG_X1,DSP_REG_A},
670: {DSP_REG_X1,DSP_REG_B},
671: {DSP_REG_Y1,DSP_REG_A},
672: {DSP_REG_Y1,DSP_REG_B}
673: };
674:
675: static const int registers_mask[64] = {
676: 0, 0, 0, 0,
677: 24, 24, 24, 24,
678: 24, 24, 8, 8,
679: 24, 24, 24, 24,
680:
681: 16, 16, 16, 16,
682: 16, 16, 16, 16,
683: 16, 16, 16, 16,
684: 16, 16, 16, 16,
685:
686: 16, 16, 16, 16,
687: 16, 16, 16, 16,
688: 0, 0, 0, 0,
689: 0, 0, 0, 0,
690:
691: 0, 0, 0, 0,
692: 0, 0, 0, 0,
693: 0, 16, 8, 6,
694: 16, 16, 16, 16
695: };
696:
697: const char dsp_inter_priority_list[32] = {
698: DSP_INTER_ILLEGAL, DSP_INTER_TRACE, DSP_INTER_SWI, DSP_INTER_IRQA, /* 0 */
699: DSP_INTER_IRQB, DSP_INTER_HOST_COMMAND, DSP_INTER_SSI_TRX_DATA_E, DSP_INTER_SSI_RCV_DATA, /* 4 */
700: DSP_INTER_SCI_RCV_DATA_E, DSP_INTER_SSI_TRX_DATA, DSP_INTER_SCI_TRX_DATA, DSP_INTER_SCI_RCV_DATA, /* 8 */
701: DSP_INTER_SCI_IDLE_LINE, DSP_INTER_SCI_TIMER, DSP_PRIORITY_LIST_EXIT, DSP_INTER_STACK_ERROR, /* 12 */
702: DSP_INTER_HOST_TRX_DATA, DSP_INTER_SSI_RCV_DATA_E, DSP_INTER_HOST_RCV_DATA, 0, /* 16 */
703: 0, 0, 0, 0, /* 20 */
704: 0, 0, 0, 0, /* 24 */
705: 0, 0, 0, DSP_INTER_NMI, /* 28 */
706: };
707:
708: const char *dsp_interrupt_name[32] = {
709: "Reset", "Stack Error", "Trace", "SWI",
710: "IRQA", "IRQB", "SSI Receive Data", "SSI Receive Data with Exception",
711: "SSI Transmit Data", "SSI Transmit Data with Exception", "SCI Receive Data", "SCI Receive Data with Exception",
712: "SCI Transmit Data", "SCI Idle Line", "SCI Timer", "NMI",
713: "Host Receive Data", "Host Transmit Data", "Host Command", "Unknown",
714: "Unknown", "Unknown", "Unknown", "Unknown",
715: "Unknown", "Unknown", "Unknown", "Unknown",
716: "Unknown", "Unknown", "Unknown", "Illegal"
717: };
718:
719:
720: /**********************************
721: * Emulator kernel
722: **********************************/
723:
724: void dsp56k_init_cpu(void)
725: {
726: dsp56k_disasm_init();
727: isDsp_in_disasm_mode = false;
728: start_time = SDL_GetTicks();
729: num_inst = 0;
730: }
731:
732: /**
733: * Execute one instruction in trace mode at a given PC address.
734: * */
735: Uint16 dsp56k_execute_one_disasm_instruction(FILE *out, Uint16 pc)
736: {
737: dsp_core_t *ptr1, *ptr2;
738: static dsp_core_t dsp_core_save;
739: Uint16 instruction_length;
740:
741: ptr1 = &dsp_core;
742: ptr2 = &dsp_core_save;
743:
744: /* Set DSP in disasm mode */
745: isDsp_in_disasm_mode = true;
746:
747: /* Save DSP context before executing instruction */
748: memcpy(ptr2, ptr1, sizeof(dsp_core));
749:
750: /* execute and disasm instruction */
751: dsp_core.pc = pc;
752:
753: /* Disasm instruction */
754: instruction_length = dsp56k_disasm(DSP_DISASM_MODE) - 1;
755:
756: /* Execute instruction at address given in parameter to get the number of cycles it takes */
757: dsp56k_execute_instruction();
758:
759: fprintf(out, "%s", dsp56k_getInstructionText());
760:
761: /* Restore DSP context after executing instruction */
762: memcpy(ptr1, ptr2, sizeof(dsp_core));
763:
764: /* Unset DSP in disasm mode */
765: isDsp_in_disasm_mode = false;
766:
767: return instruction_length;
768: }
769:
770: void dsp56k_execute_instruction(void)
771: {
772: Uint32 value;
773: Uint32 disasm_return = 0;
774: disasm_memory_ptr = 0;
775:
776: /* Initialise the number of access to the external memory for this instruction */
777: access_to_ext_memory = 0;
778:
779: /* Trace Interrupt at end of instruction? */
780: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_T)) {
781: dsp_set_interrupt(DSP_INTER_TRACE, 1);
782: }
783:
784: /* Decode and execute current instruction */
785: cur_inst = read_memory_p(dsp_core.pc);
786:
787: /* Initialize instruction size and cycle counter */
788: cur_inst_len = 1;
789: dsp_core.instr_cycle = 2;
790:
791: /* Disasm current instruction ? (trace mode only) */
792: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
793: /* Call dsp56k_disasm only when DSP is called in trace mode */
794: if (isDsp_in_disasm_mode == false) {
795: disasm_return = dsp56k_disasm(DSP_TRACE_MODE);
796:
797: if (disasm_return != 0 && LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG)) {
798: /* DSP regs trace enabled only if DSP DISASM is enabled */
799: dsp56k_disasm_reg_save();
800: }
801: }
802: }
803:
804: if (cur_inst < 0x100000) {
805: value = (cur_inst >> 11) & (BITMASK(6) << 3);
806: value += (cur_inst >> 5) & BITMASK(3);
807: opcodes8h[value]();
808: } else {
809: /* Do parallel move read */
810: opcodes_parmove[(cur_inst>>20) & BITMASK(4)]();
811: }
812:
813: /* Add the waitstate due to external memory access */
814: /* (2 extra cycles per extra access to the external memory after the first one */
815: if (access_to_ext_memory != 0) {
816: value = access_to_ext_memory & 1;
817: value += (access_to_ext_memory & 2) >> 1;
818: value += (access_to_ext_memory & 4) >> 2;
819:
820: if (value > 1)
821: dsp_core.instr_cycle += (value - 1) * 2;
822: }
823:
824: /* Disasm current instruction ? (trace mode only) */
825: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
826: /* Display only when DSP is called in trace mode */
827: if (isDsp_in_disasm_mode == false) {
828: if (disasm_return != 0) {
829: fprintf(stderr, "%s", dsp56k_getInstructionText());
830:
831: /* DSP regs trace enabled only if DSP DISASM is enabled */
832: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG))
833: dsp56k_disasm_reg_compare();
834:
835: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)) {
836: /* 1 memory change to display ? */
837: if (disasm_memory_ptr == 1)
838: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
839: /* 2 memory changes to display ? */
840: else if (disasm_memory_ptr == 2) {
841: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
842: fprintf(stderr, "\t%s\n", str_disasm_memory[1]);
843: }
844: }
845: }
846: }
847: }
848:
849: /* Process the PC */
850: dsp_postexecute_update_pc();
851:
852: /* Process Interrupts */
853: dsp_postexecute_interrupts();
854:
855: #if DSP_COUNT_IPS
856: ++num_inst;
857: if ((num_inst & 63) == 0) {
858: /* Evaluate time after <N> instructions have been executed to avoid asking too frequently */
859: Uint32 cur_time = SDL_GetTicks();
860: if (cur_time-start_time>1000) {
861: fprintf(stderr, "Dsp: %d i/s\n", (num_inst*1000)/(cur_time-start_time));
862: start_time=cur_time;
863: num_inst=0;
864: }
865: }
866: #endif
867: }
868:
869: /**********************************
870: * Update the PC
871: **********************************/
872:
873: static void dsp_postexecute_update_pc(void)
874: {
875: /* When running a REP, PC must stay on the current instruction */
876: if (dsp_core.loop_rep) {
877: /* Is PC on the instruction to repeat ? */
878: if (dsp_core.pc_on_rep==0) {
879: --dsp_core.registers[DSP_REG_LC];
880: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
881:
882: if (dsp_core.registers[DSP_REG_LC] > 0) {
883: cur_inst_len = 0; /* Stay on this instruction */
884: } else {
885: dsp_core.loop_rep = 0;
886: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[DSP_REG_LCSAVE];
887: }
888: } else {
889: /* Init LC at right value */
890: if (dsp_core.registers[DSP_REG_LC] == 0) {
891: dsp_core.registers[DSP_REG_LC] = 0x010000;
892: }
893: dsp_core.pc_on_rep = 0;
894: }
895: }
896:
897: /* Normal execution, go to next instruction */
898: dsp_core.pc += cur_inst_len;
899:
900: /* When running a DO loop, we test the end of loop with the */
901: /* updated PC, pointing to last instruction of the loop */
902: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_LF)) {
903:
904: /* Did we execute the last instruction in loop ? */
905: if (dsp_core.pc == dsp_core.registers[DSP_REG_LA] + 1) {
906: --dsp_core.registers[DSP_REG_LC];
907: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
908:
909: if (dsp_core.registers[DSP_REG_LC] == 0) {
910: /* end of loop */
911: Uint32 saved_pc, saved_sr;
912:
913: dsp_stack_pop(&saved_pc, &saved_sr);
914: dsp_core.registers[DSP_REG_SR] &= 0x7fff;
915: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
916: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
917: } else {
918: /* Loop one more time */
919: dsp_core.pc = dsp_core.registers[DSP_REG_SSH];
920: }
921: }
922: }
923: }
924:
925: /**********************************
926: * Interrupts
927: **********************************/
928:
929: /* Set the status of an interrupt */
930: void dsp_set_interrupt(Uint32 intr, Uint32 set)
931: {
932: if (set) {
933: dsp_core.interrupt_status |= (1<<intr);
934: } else {
935: dsp_core.interrupt_status &= ~(1<<intr);
936: }
937: }
938:
939: /* Mask or unmask an interrupt */
940: void dsp_set_interrupt_mask(Uint32 intr, Uint32 set)
941: {
942: if (set) {
943: dsp_core.interrupt_mask |= (1<<intr);
944: } else {
945: dsp_core.interrupt_mask &= ~(1<<intr);
946: }
947: }
948:
949: static void dsp_setInterruptIPL(Uint32 value)
950: {
951: Uint32 ipl_irqa, ipl_irqb, ipl_hi, ipl_ssi, ipl_sci;
952:
953: ipl_irqa = (value & 3);
954: ipl_irqb = ((value >> 3) & 3);
955: ipl_hi = ((value >> 10) & 3);
956: ipl_ssi = ((value >> 12) & 3);
957: ipl_sci = ((value >> 14) & 3);
958:
959: /* Reset all masks */
960: dsp_core.interrupt_enable = 0;
961: dsp_core.interrupt_mask_level[0] = 0;
962: dsp_core.interrupt_mask_level[1] = 0;
963: dsp_core.interrupt_mask_level[2] = 0;
964: dsp_core.interrupt_edgetriggered_mask = DSP_INTER_EDGE_MASK;
965:
966: /* Set masks to programmed values */
967: if (ipl_irqa) {
968: dsp_core.interrupt_enable |= DSP_INTER_IRQA_MASK;
969: dsp_core.interrupt_mask_level[ipl_irqa-1] |= DSP_INTER_IRQA_MASK;
970: }
971: if (ipl_irqb) {
972: dsp_core.interrupt_enable |= DSP_INTER_IRQB_MASK;
973: dsp_core.interrupt_mask_level[ipl_irqb-1] |= DSP_INTER_IRQB_MASK;
974: }
975: if (ipl_hi) {
976: dsp_core.interrupt_enable |= DSP_INTER_HOST_MASK;
977: dsp_core.interrupt_mask_level[ipl_hi-1] |= DSP_INTER_HOST_MASK;
978: }
979: if (ipl_ssi) {
980: dsp_core.interrupt_enable |= DSP_INTER_SSI_MASK;
981: dsp_core.interrupt_mask_level[ipl_ssi-1] |= DSP_INTER_SSI_MASK;
982: }
983: if (ipl_sci) {
984: dsp_core.interrupt_enable |= DSP_INTER_SCI_MASK;
985: dsp_core.interrupt_mask_level[ipl_sci-1] |= DSP_INTER_SCI_MASK;
986: }
987:
988: /* Add IRQA, IRQB as edge triggered, if configured */
989: if (value & 0x04) {
990: dsp_core.interrupt_edgetriggered_mask |= DSP_INTER_IRQA_MASK;
991: }
992: if (value & 0x20) {
993: dsp_core.interrupt_edgetriggered_mask |= DSP_INTER_IRQB_MASK;
994: }
995: }
996:
997: static void dsp_postexecute_interrupts(void)
998: {
999: int i;
1000: Uint32 interrupt, inter;
1001: Uint32 priority_list_start;
1002: Uint32 instr;
1003: Sint32 ipl_sr;
1004:
1005: /* REP is not interruptible */
1006: if (dsp_core.loop_rep) {
1007: return;
1008: }
1009:
1010: /* A fast interrupt can not be interrupted. */
1011: if (dsp_core.interrupt_state == DSP_INTERRUPT_DISABLED) {
1012:
1013: switch (dsp_core.interrupt_pipeline_count) {
1014: case 5:
1015: dsp_core.interrupt_pipeline_count --;
1016: return;
1017: case 4:
1018: /* Prefetch interrupt instruction 1 */
1019: dsp_core.interrupt_save_pc = dsp_core.pc;
1020: dsp_core.pc = dsp_core.interrupt_instr_fetch;
1021:
1022: /* is it a LONG interrupt ? */
1023: instr = read_memory_p(dsp_core.interrupt_instr_fetch);
1024: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1025: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1026: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1027: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1028: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
1029: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1030: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1031: }
1032: dsp_core.interrupt_pipeline_count --;
1033: return;
1034: case 3:
1035: /* Prefetch interrupt instruction 2, if first one was single word */
1036: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+1) {
1037: instr = read_memory_p(dsp_core.pc);
1038: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1039: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1040: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1041: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1042: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
1043: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1044: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1045: }
1046: dsp_core.interrupt_pipeline_count --;
1047: return;
1048: }
1049: dsp_core.interrupt_pipeline_count --;
1050: /* First instruction was 2 word. Fall through */
1051: case 2:
1052: /* 1 instruction executed after interrupt */
1053: /* before re enable interrupts */
1054: /* Was it a FAST interrupt ? */
1055: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+2) {
1056: dsp_core.pc = dsp_core.interrupt_save_pc;
1057: }
1058: dsp_core.interrupt_pipeline_count --;
1059: return;
1060: case 1:
1061: /* Last instruction executed after interrupt */
1062: /* before re enable interrupts */
1063: dsp_core.interrupt_pipeline_count --;
1064: return;
1065: case 0:
1066: /* Re enable interrupts */
1067: /* All 6 instruction are done, Interrupts can be enabled again */
1068: dsp_core.interrupt_save_pc = -1;
1069: dsp_core.interrupt_instr_fetch = -1;
1070: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
1071: break;
1072: }
1073: }
1074:
1075: /* See if there is an interrupt pending */
1076: if (dsp_core.interrupt_status & DSP_INTER_NMI_MASK) {
1077: interrupt = dsp_core.interrupt_status & DSP_INTER_NMI_MASK;
1078: dsp_core.interrupt_IplToRaise = 3;
1079: priority_list_start = DSP_INTER_RESET;
1080: } else {
1081: interrupt = 0;
1082: inter = dsp_core.interrupt_status & dsp_core.interrupt_enable & dsp_core.interrupt_mask;
1083:
1084: /* If there is no enabled interrupt, stop here */
1085: if (!inter) {
1086: return;
1087: }
1088:
1089: /* Find out the interrupt priority level */
1090: ipl_sr = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_I0) & BITMASK(2);
1091: for (i = 2; i >= ipl_sr; i--) {
1092: if (inter & dsp_core.interrupt_mask_level[i]) {
1093: dsp_core.interrupt_IplToRaise = i+1;
1094: interrupt = inter & dsp_core.interrupt_mask_level[i];
1095: break;
1096: }
1097: }
1098: priority_list_start = DSP_INTER_IRQA;
1099: }
1100:
1101: /* If there is no unmasked interrupt, stop here */
1102: if (!interrupt) {
1103: return;
1104: }
1105:
1106: /* Find out which interrupt is pending, using priorities */
1107: for (i = priority_list_start; i != DSP_PRIORITY_LIST_EXIT; i = dsp_inter_priority_list[i]) {
1108: if (interrupt & (1<<i)) {
1109: interrupt = i;
1110: break;
1111: }
1112: }
1113:
1114: LOG_TRACE(TRACE_DSP_INTERRUPT, "Dsp interrupt: %s\n", dsp_interrupt_name[interrupt]);
1115:
1116: /* Auto-release edge triggered interrupts (IRQB simplified for NeXT) */
1117: if ((1<<interrupt) & (dsp_core.interrupt_edgetriggered_mask|DSP_INTER_IRQB_MASK)) {
1118: dsp_set_interrupt(interrupt, 0);
1119: }
1120:
1121: /* Host command interrupt */
1122: if (interrupt == DSP_INTER_HOST_COMMAND) {
1123: interrupt = dsp_core.hostport[CPU_HOST_CVR] & BITMASK(5);
1124:
1125: /* Clear HC and HCP interrupt */
1126: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1127: dsp_core.hostport[CPU_HOST_CVR] &= 0xff - (1<<CPU_HOST_CVR_HC);
1128: }
1129:
1130: /* Set variables for interrupt routine */
1131: dsp_core.interrupt_pipeline_count = 5;
1132: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1133:
1134: /* Set the interrupt vector */
1135: dsp_core.interrupt_instr_fetch = interrupt * 2;
1136: }
1137:
1138: /**********************************
1139: * Set/clear ccr bits
1140: **********************************/
1141:
1142: /* reg0 has bits 55..48 */
1143: /* reg1 has bits 47..24 */
1144: /* reg2 has bits 23..0 */
1145:
1146: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2)
1147: {
1148: Uint32 scaling, value_e, value_u;
1149:
1150: /* Initialize SR register */
1151: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E) | (1<<DSP_SR_U) | (1<<DSP_SR_N) | (1<<DSP_SR_Z));
1152:
1153: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1154: switch(scaling) {
1155: case 0:
1156: /* Extension Bit (E) */
1157: value_e = (reg0<<1) + (reg1>>23);
1158: if ((value_e != 0) && (value_e != BITMASK(9)))
1159: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1160:
1161: /* Unnormalized bit (U) */
1162: if ((reg1 & 0xc00000) == 0 || (reg1 & 0xc00000) == 0xc00000)
1163: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1164: break;
1165: case 1:
1166: /* Extension Bit (E) */
1167: if ((reg0 != 0) && (reg0 != BITMASK(8)))
1168: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1169:
1170: /* Unnormalized bit (U) */
1171: value_u = ((reg0<<1) + (reg1>>23)) & 3;
1172: if (value_u == 0 || value_u == 3)
1173: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1174: break;
1175: case 2:
1176: /* Extension Bit (E) */
1177: value_e = (reg0<<2) + (reg1>>22);
1178: if ((value_e != 0) && (value_e != BITMASK(10)))
1179: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1180:
1181: /* Unnormalized bit (U) */
1182: if ((reg1 & 0x600000) == 0 || (reg1 & 0x600000) == 0x600000)
1183: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1184: break;
1185: default:
1186: return;
1187: break;
1188: }
1189:
1190: /* Zero Flag (Z) */
1191: if ((reg1 == 0) && (reg2 == 0) && (reg0 == 0))
1192: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_Z;
1193:
1194: /* Negative Flag (N) */
1195: dsp_core.registers[DSP_REG_SR] |= (reg0>>4) & 0x8;
1196: }
1197:
1198: /**********************************
1199: * Read/Write memory functions
1200: **********************************/
1201:
1202: static Uint32 read_memory_disasm(int space, Uint16 address)
1203: {
1204: /* Internal RAM ? */
1205: if (address<0x100) {
1206: return dsp_core.ramint[space][address] & BITMASK(24);
1207: }
1208:
1209: if (space==DSP_SPACE_P) {
1210: return read_memory_p(address);
1211: }
1212:
1213: /* Internal ROM? */
1214: if ((dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) &&
1215: (address<0x200)) {
1216: return dsp_core.rom[space][address] & BITMASK(24);
1217: }
1218:
1219: /* Peripheral address ? */
1220: if (address >= 0xffc0) {
1221: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_HOST_HTX)) {
1222: return dsp_core.dsp_host_htx;
1223: }
1224: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_SSI_TX)) {
1225: return dsp_core.ssi.transmit_value;
1226: }
1227: return dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1228: }
1229:
1230: /* NeXT: Upper external X and Y memory are physically separate */
1231: if (address&0x8000) {
1232: address &= (DSP_RAMSIZE>>1) - 1;
1233: /* NeXT: External RAM, map X to upper 4K of matching space in P */
1234: if (space == DSP_SPACE_X) {
1235: address += DSP_RAMSIZE>>1;
1236: }
1237: }
1238:
1239: /* NeXT: External RAM, finally map X,Y to P */
1240: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1241: }
1242:
1243: static inline Uint32 read_memory_p(Uint16 address)
1244: {
1245: /* Internal RAM ? */
1246: if (address < 0x200) {
1247: return dsp_core.ramint[DSP_SPACE_P][address] & BITMASK(24);
1248: }
1249:
1250: /* Access to the external P memory */
1251: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1252:
1253: /* External RAM, mask address to available ram size */
1254: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1255: }
1256:
1257: static inline Uint32 read_memory_x(Uint16 address)
1258: {
1259: Uint32 value;
1260:
1261: /* Internal RAM ? */
1262: if (address < 0x100) {
1263: return dsp_core.ramint[DSP_SPACE_X][address] & BITMASK(24);
1264: }
1265:
1266: /* Internal ROM ? */
1267: if (address < 0x200) {
1268: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1269: return dsp_core.rom[DSP_SPACE_X][address] & BITMASK(24);
1270: }
1271: }
1272:
1273: /* Peripheral address ? */
1274: if (address >= 0xffc0) {
1275: value = dsp_core.periph[DSP_SPACE_X][address-0xffc0] & BITMASK(24);
1276: if (address == 0xffc0+DSP_HOST_HRX) {
1277: value = dsp_core.dsp_host_rtx;
1278: dsp_core_hostport_dspread();
1279: }
1280: else if (address == 0xffc0+DSP_SSI_RX) {
1281: value = dsp_core_ssi_readRX();
1282: }
1283: return value;
1284: }
1285:
1286: /* Access to X external RAM */
1287: access_to_ext_memory |= 1 << EXT_X_MEMORY;
1288:
1289: /* Access to contiguous or separated space ? */
1290: if (address&0x8000) {
1291: /* Map X to upper half of available ram size */
1292: address &= (DSP_RAMSIZE>>1)-1;
1293: address += DSP_RAMSIZE>>1;
1294: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1295: } else {
1296: /* Mask address to available ram size */
1297: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1298: }
1299: }
1300:
1301: static inline Uint32 read_memory_y(Uint16 address)
1302: {
1303: /* Internal RAM ? */
1304: if (address < 0x100) {
1305: return dsp_core.ramint[DSP_SPACE_Y][address] & BITMASK(24);
1306: }
1307:
1308: /* Internal ROM ? */
1309: if (address < 0x200) {
1310: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1311: return dsp_core.rom[DSP_SPACE_Y][address] & BITMASK(24);
1312: }
1313: }
1314:
1315: /* Peripheral address ? */
1316: if (address >= 0xffc0) {
1317: return dsp_core.periph[DSP_SPACE_Y][address-0xffc0] & BITMASK(24);
1318: }
1319:
1320: /* Access to Y external RAM */
1321: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1322:
1323: /* Access to contiguous or separated space ? */
1324: if (address&0x8000) {
1325: /* Map Y to lower half of available ram size */
1326: return dsp_core.ramext[address & ((DSP_RAMSIZE>>1)-1)] & BITMASK(24);
1327: } else {
1328: /* Mask address to available ram size */
1329: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1330: }
1331: }
1332:
1333: static Uint32 read_memory(int space, Uint16 address)
1334: {
1335: switch (space) {
1336: case DSP_SPACE_P:
1337: return read_memory_p(address);
1338: case DSP_SPACE_X:
1339: return read_memory_x(address);
1340: case DSP_SPACE_Y:
1341: return read_memory_y(address);
1342:
1343: default: abort();
1344: }
1345: }
1346:
1347: static inline void write_memory(int space, Uint16 address, Uint32 value)
1348: {
1349: if (unlikely(LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)))
1350: write_memory_disasm(space, address, value);
1351: else
1352: write_memory_raw(space, address, value);
1353: }
1354:
1355: static void write_memory_p(Uint16 address, Uint32 value)
1356: {
1357: /* Internal P RAM ? */
1358: if (address < 0x200) {
1359: dsp_core.ramint[DSP_SPACE_P][address] = value;
1360: return;
1361: }
1362:
1363: /* Access to the P external RAM */
1364: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1365:
1366: /* Mask address to available ram size */
1367: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1368: }
1369:
1370: static void write_memory_x(Uint16 address, Uint32 value)
1371: {
1372: /* Peripheral address ? */
1373: if (address >= 0xffc0) {
1374: switch(address-0xffc0) {
1375: case DSP_HOST_HTX:
1376: dsp_core.dsp_host_htx = value;
1377: dsp_core_hostport_dspwrite();
1378: break;
1379: case DSP_HOST_HCR:
1380: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value;
1381: /* Set HF3 and HF2 accordingly on the host side */
1382: dsp_core.hostport[CPU_HOST_ISR] &=
1383: BITMASK(8)-((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1384: dsp_core.hostport[CPU_HOST_ISR] |=
1385: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & ((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1386: /* Handle interrupt mask */
1387: dsp_set_interrupt_mask(DSP_INTER_HOST_RCV_DATA, dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR]&(1<<DSP_HOST_HCR_HRIE));
1388: dsp_set_interrupt_mask(DSP_INTER_HOST_TRX_DATA, dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR]&(1<<DSP_HOST_HCR_HTIE));
1389: dsp_set_interrupt_mask(DSP_INTER_HOST_COMMAND, dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR]&(1<<DSP_HOST_HCR_HCIE));
1390: break;
1391: case DSP_HOST_HSR:
1392: /* Read only */
1393: break;
1394: case DSP_SSI_CRA:
1395: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1396: dsp_core_ssi_configure(address-0xffc0, value);
1397: break;
1398: case DSP_SSI_CRB:
1399: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1400: dsp_core_ssi_configure(address-0xffc0, value);
1401: dsp_set_interrupt_mask(DSP_INTER_SSI_RCV_DATA_E, dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB]&(1<<DSP_SSI_CRB_RIE));
1402: dsp_set_interrupt_mask(DSP_INTER_SSI_RCV_DATA, dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB]&(1<<DSP_SSI_CRB_RIE));
1403: dsp_set_interrupt_mask(DSP_INTER_SSI_TRX_DATA_E, dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB]&(1<<DSP_SSI_CRB_TIE));
1404: dsp_set_interrupt_mask(DSP_INTER_SSI_TRX_DATA, dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB]&(1<<DSP_SSI_CRB_TIE));
1405: break;
1406: case DSP_SSI_TSR:
1407: dsp_core_ssi_writeTSR();
1408: break;
1409: case DSP_SSI_TX:
1410: dsp_core_ssi_writeTX(value);
1411: break;
1412: case DSP_IPR:
1413: dsp_core.periph[DSP_SPACE_X][DSP_IPR] = value;
1414: dsp_setInterruptIPL(value);
1415: break;
1416: case DSP_PCD:
1417: dsp_core.periph[DSP_SPACE_X][DSP_PCD] = value;
1418: dsp_core_setPortCDataRegister(value);
1419: break;
1420: case DSP_PBC:
1421: dsp_core.periph[DSP_SPACE_X][DSP_PBC] = value;
1422: dsp_set_interrupt_mask(DSP_INTER_SCI_RCV_DATA_E, dsp_core.periph[DSP_SPACE_X][DSP_PBC]&(1<<11));
1423: dsp_set_interrupt_mask(DSP_INTER_SCI_RCV_DATA, dsp_core.periph[DSP_SPACE_X][DSP_PBC]&(1<<11));
1424: dsp_set_interrupt_mask(DSP_INTER_SCI_TRX_DATA, dsp_core.periph[DSP_SPACE_X][DSP_PBC]&(1<<12));
1425: dsp_set_interrupt_mask(DSP_INTER_SCI_IDLE_LINE, dsp_core.periph[DSP_SPACE_X][DSP_PBC]&(1<<10));
1426: dsp_set_interrupt_mask(DSP_INTER_SCI_TIMER, dsp_core.periph[DSP_SPACE_X][DSP_PBC]&(1<<13));
1427: break;
1428: default:
1429: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1430: break;
1431: }
1432: return;
1433: }
1434:
1435: /* Internal RAM ? */
1436: if (address < 0x100) {
1437: dsp_core.ramint[DSP_SPACE_X][address] = value;
1438: return;
1439: }
1440:
1441: /* Access to X external RAM */
1442: access_to_ext_memory |= 1 << EXT_X_MEMORY;
1443:
1444: /* Access to contiguous or separated space ? */
1445: if (address&0x8000) {
1446: /* Map X to upper half of available ram size */
1447: address &= (DSP_RAMSIZE>>1)-1;
1448: address += DSP_RAMSIZE>>1;
1449: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1450: } else {
1451: /* Mask address to available ram size */
1452: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1453: }
1454: }
1455:
1456: static void write_memory_y(Uint16 address, Uint32 value)
1457: {
1458: /* Peripheral address ? */
1459: if (address >= 0xffc0) {
1460: dsp_core.periph[DSP_SPACE_Y][address-0xffc0] = value;
1461: return;
1462: }
1463:
1464: /* Internal RAM ? */
1465: if (address < 0x100) {
1466: dsp_core.ramint[DSP_SPACE_Y][address] = value;
1467: return;
1468: }
1469:
1470: /* Access to Y external RAM */
1471: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1472:
1473: /* Access to contiguous or separated space ? */
1474: if (address&0x8000) {
1475: /* Map Y to lower half of available ram size */
1476: dsp_core.ramext[address & ((DSP_RAMSIZE>>1)-1)] = value;
1477: } else {
1478: /* Mask address to available ram size */
1479: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1480: }
1481: }
1482:
1483: static void write_memory_raw(int space, Uint16 address, Uint32 value)
1484: {
1485: value &= BITMASK(24);
1486:
1487: switch (space) {
1488: case DSP_SPACE_P:
1489: write_memory_p(address, value);
1490: break;
1491: case DSP_SPACE_X:
1492: write_memory_x(address, value);
1493: break;
1494: case DSP_SPACE_Y:
1495: write_memory_y(address, value);
1496: break;
1497:
1498: default:
1499: break;
1500: }
1501: }
1502:
1503: static void write_memory_disasm(int space, Uint16 address, Uint32 value)
1504: {
1505: Uint32 oldvalue, curvalue;
1506: Uint8 space_c = 'p';
1507:
1508: value &= BITMASK(24);
1509: oldvalue = read_memory_disasm(space, address);
1510:
1511: write_memory_raw(space,address,value);
1512:
1513: switch(space) {
1514: case DSP_SPACE_X:
1515: space_c = 'x';
1516: break;
1517: case DSP_SPACE_Y:
1518: space_c = 'y';
1519: break;
1520: default:
1521: break;
1522: }
1523:
1524: curvalue = read_memory_disasm(space, address);
1525: sprintf(str_disasm_memory[disasm_memory_ptr],"Mem: %c:0x%04x 0x%06x -> 0x%06x", space_c, address, oldvalue, curvalue);
1526: disasm_memory_ptr ++;
1527: }
1528:
1529: static void dsp_write_reg(Uint32 numreg, Uint32 value)
1530: {
1531: Uint32 stack_error;
1532:
1533: switch (numreg) {
1534: case DSP_REG_A:
1535: dsp_core.registers[DSP_REG_A0] = 0;
1536: dsp_core.registers[DSP_REG_A1] = value;
1537: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
1538: break;
1539: case DSP_REG_B:
1540: dsp_core.registers[DSP_REG_B0] = 0;
1541: dsp_core.registers[DSP_REG_B1] = value;
1542: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
1543: break;
1544: case DSP_REG_OMR:
1545: dsp_core.registers[DSP_REG_OMR] = value & 0xc7;
1546: break;
1547: case DSP_REG_SR:
1548: dsp_core.registers[DSP_REG_SR] = value & 0xaf7f;
1549: break;
1550: case DSP_REG_SP:
1551: stack_error = dsp_core.registers[DSP_REG_SP] & (3<<DSP_SP_SE);
1552: if ((stack_error==0) && (value & (3<<DSP_SP_SE))) {
1553: /* Stack underflow or overflow detected, raise interrupt */
1554: dsp_set_interrupt(DSP_INTER_STACK_ERROR, 1);
1555: dsp_core.registers[DSP_REG_SP] = value & (3<<DSP_SP_SE);
1556: if (!isDsp_in_disasm_mode)
1557: fprintf(stderr,"Dsp: Stack Overflow or Underflow\n");
1558: if (ExceptionDebugMask & EXCEPT_DSP)
1559: DebugUI(REASON_DSP_EXCEPTION);
1560: }
1561: else
1562: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
1563: dsp_compute_ssh_ssl();
1564: break;
1565: case DSP_REG_SSH:
1566: dsp_stack_push(value, 0, 1);
1567: break;
1568: case DSP_REG_SSL:
1569: numreg = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
1570: if (numreg == 0) {
1571: value = 0;
1572: }
1573: dsp_core.stack[1][numreg] = value & BITMASK(16);
1574: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
1575: break;
1576: default:
1577: dsp_core.registers[numreg] = value;
1578: dsp_core.registers[numreg] &= BITMASK(registers_mask[numreg]);
1579: break;
1580: }
1581: }
1582:
1583: /**********************************
1584: * Stack push/pop
1585: **********************************/
1586:
1587: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly)
1588: {
1589: Uint32 stack_error, underflow, stack;
1590:
1591: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1592: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1593: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) + 1;
1594:
1595:
1596: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1597: /* Stack full, raise interrupt */
1598: dsp_set_interrupt(DSP_INTER_STACK_ERROR, 1);
1599: if (!isDsp_in_disasm_mode)
1600: fprintf(stderr,"Dsp: Stack Overflow\n");
1601: if (ExceptionDebugMask & EXCEPT_DSP)
1602: DebugUI(REASON_DSP_EXCEPTION);
1603: }
1604:
1605: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1606: stack &= BITMASK(4);
1607:
1608: if (stack) {
1609: /* SSH part */
1610: dsp_core.stack[0][stack] = curpc & BITMASK(16);
1611: /* SSL part, if instruction is not like "MOVEC xx, SSH" */
1612: if (sshOnly == 0) {
1613: dsp_core.stack[1][stack] = cursr & BITMASK(16);
1614: }
1615: } else {
1616: dsp_core.stack[0][0] = 0;
1617: dsp_core.stack[1][0] = 0;
1618: }
1619:
1620: /* Update SSH and SSL registers */
1621: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1622: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1623: }
1624:
1625: static void dsp_stack_pop(Uint32 *newpc, Uint32 *newsr)
1626: {
1627: Uint32 stack_error, underflow, stack;
1628:
1629: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1630: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1631: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) - 1;
1632:
1633: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1634: /* Stack empty*/
1635: dsp_set_interrupt(DSP_INTER_STACK_ERROR, 1);
1636: if (!isDsp_in_disasm_mode)
1637: fprintf(stderr,"Dsp: Stack underflow\n");
1638: if (ExceptionDebugMask & EXCEPT_DSP)
1639: DebugUI(REASON_DSP_EXCEPTION);
1640: }
1641:
1642: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1643: stack &= BITMASK(4);
1644: *newpc = dsp_core.registers[DSP_REG_SSH];
1645: *newsr = dsp_core.registers[DSP_REG_SSL];
1646:
1647: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1648: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1649: }
1650:
1651: static void dsp_compute_ssh_ssl(void)
1652: {
1653: Uint32 stack;
1654:
1655: stack = dsp_core.registers[DSP_REG_SP];
1656: stack &= BITMASK(4);
1657: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1658: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1659: }
1660:
1661: /**********************************
1662: * Effective address calculation
1663: **********************************/
1664:
1665: static void dsp_update_rn(Uint32 numreg, Sint16 modifier)
1666: {
1667: Uint32 value;
1668: Uint16 m_reg;
1669:
1670: m_reg = (Uint16) dsp_core.registers[DSP_REG_M0+numreg];
1671: if (m_reg == 65535) {
1672: /* Linear addressing mode */
1673: value = dsp_core.registers[DSP_REG_R0+numreg]|0x10000;
1674: value += modifier;
1675: dsp_core.registers[DSP_REG_R0+numreg] = value & BITMASK(16);
1676: } else if (m_reg == 0) {
1677: /* Bit reversed carry update */
1678: dsp_update_rn_bitreverse(numreg);
1679: } else if (m_reg<=32767) {
1680: /* Modulo update */
1681: dsp_update_rn_modulo(numreg, modifier);
1682: } else {
1683: /* Undefined */
1684: }
1685: }
1686:
1687: static void dsp_update_rn_bitreverse(Uint32 numreg)
1688: {
1689: int revbits, i;
1690: Uint32 value, r_reg;
1691:
1692: /* Check how many bits to reverse */
1693: value = dsp_core.registers[DSP_REG_N0+numreg];
1694: for (revbits=0;revbits<16;revbits++) {
1695: if (value & (1<<revbits)) {
1696: break;
1697: }
1698: }
1699: revbits++;
1700:
1701: /* Reverse Rn bits */
1702: r_reg = dsp_core.registers[DSP_REG_R0+numreg];
1703: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1704: for (i=0;i<revbits;i++) {
1705: if (r_reg & (1<<i)) {
1706: value |= 1<<(revbits-i-1);
1707: }
1708: }
1709:
1710: /* Increment */
1711: value++;
1712: value &= BITMASK(revbits);
1713:
1714: /* Reverse Rn bits */
1715: r_reg &= (BITMASK(16)-BITMASK(revbits));
1716: r_reg |= value;
1717:
1718: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1719: for (i=0;i<revbits;i++) {
1720: if (r_reg & (1<<i)) {
1721: value |= 1<<(revbits-i-1);
1722: }
1723: }
1724:
1725: dsp_core.registers[DSP_REG_R0+numreg] = value;
1726: }
1727:
1728: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier)
1729: {
1730: Uint16 bufsize, bufmask, modulo, abs_modifier;
1731: Uint32 r_reg, lobound, hibound;
1732:
1733: r_reg = dsp_core.registers[DSP_REG_R0+numreg]|0x10000;
1734: modulo = dsp_core.registers[DSP_REG_M0+numreg]+1;
1735:
1736: bufsize = 1;
1737: while (bufsize < modulo) {
1738: bufsize <<= 1;
1739: }
1740: bufmask = bufsize - 1;
1741:
1742: lobound = r_reg - (r_reg&bufmask);
1743: hibound = lobound + modulo - 1;
1744:
1745: if (modifier<0) {
1746: abs_modifier = -modifier;
1747: } else {
1748: abs_modifier = modifier;
1749: }
1750:
1751: if (abs_modifier>modulo) {
1752: if (abs_modifier&bufmask) {
1753: fprintf(stderr,"Dsp: Modulo addressing result unpredictable\n");
1754: } else {
1755: r_reg += modifier;
1756: }
1757: } else {
1758: r_reg += modifier;
1759:
1760: if (r_reg>hibound) {
1761: r_reg -= modulo;
1762: } else if (r_reg<lobound) {
1763: r_reg += modulo;
1764: }
1765: }
1766:
1767: dsp_core.registers[DSP_REG_R0+numreg] = r_reg & BITMASK(16);
1768: }
1769:
1770: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr)
1771: {
1772: Uint32 value, numreg, curreg;
1773:
1774: value = (ea_mode >> 3) & BITMASK(3);
1775: numreg = ea_mode & BITMASK(3);
1776: switch (value) {
1777: case 0:
1778: /* (Rx)-Nx */
1779: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1780: dsp_update_rn(numreg, -dsp_core.registers[DSP_REG_N0+numreg]);
1781: break;
1782: case 1:
1783: /* (Rx)+Nx */
1784: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1785: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1786: break;
1787: case 2:
1788: /* (Rx)- */
1789: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1790: dsp_update_rn(numreg, -1);
1791: break;
1792: case 3:
1793: /* (Rx)+ */
1794: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1795: dsp_update_rn(numreg, +1);
1796: break;
1797: case 4:
1798: /* (Rx) */
1799: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1800: break;
1801: case 5:
1802: /* (Rx+Nx) */
1803: dsp_core.instr_cycle += 2;
1804: curreg = dsp_core.registers[DSP_REG_R0+numreg];
1805: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1806: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1807: dsp_core.registers[DSP_REG_R0+numreg] = curreg;
1808: break;
1809: case 6:
1810: /* aa */
1811: dsp_core.instr_cycle += 2;
1812: *dst_addr = read_memory_p(dsp_core.pc+1);
1813: cur_inst_len++;
1814: if (numreg != 0) {
1815: return 1; /* immediate value */
1816: }
1817: break;
1818: case 7:
1819: /* -(Rx) */
1820: dsp_core.instr_cycle += 2;
1821: dsp_update_rn(numreg, -1);
1822: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1823: break;
1824: }
1825: /* address */
1826: return 0;
1827: }
1828:
1829: /**********************************
1830: * Condition code test
1831: **********************************/
1832:
1833: static int dsp_calc_cc(Uint32 cc_code)
1834: {
1835: Uint16 value1, value2, value3;
1836:
1837: switch (cc_code) {
1838: case 0: /* CC (HS) */
1839: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1840: return (value1==0);
1841: case 1: /* GE */
1842: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1843: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1844: return ((value1 ^ value2) == 0);
1845: case 2: /* NE */
1846: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_Z);
1847: return (value1==0);
1848: case 3: /* PL */
1849: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_N);
1850: return (value1==0);
1851: case 4: /* NN */
1852: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1853: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1854: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1855: return ((value1 | (value2 & value3)) == 0);
1856: case 5: /* EC */
1857: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_E);
1858: return (value1==0);
1859: case 6: /* LC */
1860: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_L);
1861: return (value1==0);
1862: case 7: /* GT */
1863: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1864: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1865: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1866: return ((value3 | (value1 ^ value2)) == 0);
1867: case 8: /* CS (LO) */
1868: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1869: return (value1==1);
1870: case 9: /* LT */
1871: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1872: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1873: return ((value1 ^ value2) == 1);
1874: case 10: /* EQ */
1875: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1876: return (value1==1);
1877: case 11: /* MI */
1878: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1879: return (value1==1);
1880: case 12: /* NR */
1881: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1882: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1883: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1884: return ((value1 | (value2 & value3)) == 1);
1885: case 13: /* ES */
1886: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_E) & 1;
1887: return (value1==1);
1888: case 14: /* LS */
1889: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_L) & 1;
1890: return (value1==1);
1891: case 15: /* LE */
1892: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1893: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1894: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1895: return ((value3 | (value1 ^ value2)) == 1);
1896: }
1897: return 0;
1898: }
1899:
1900: /**********************************
1901: * Highbyte opcodes dispatchers
1902: **********************************/
1903:
1904: static void opcode8h_0(void)
1905: {
1906: switch(cur_inst) {
1907: case 0x000000:
1908: dsp_nop();
1909: break;
1910: case 0x000004:
1911: dsp_rti();
1912: break;
1913: case 0x000005:
1914: dsp_illegal();
1915: break;
1916: case 0x000006:
1917: dsp_swi();
1918: break;
1919: case 0x00000c:
1920: dsp_rts();
1921: break;
1922: case 0x000084:
1923: dsp_reset();
1924: break;
1925: case 0x000086:
1926: dsp_wait();
1927: break;
1928: case 0x000087:
1929: dsp_stop();
1930: break;
1931: case 0x00008c:
1932: dsp_enddo();
1933: break;
1934: default:
1935: dsp_undefined();
1936: break;
1937: }
1938: }
1939:
1940: /**********************************
1941: * Non-parallel moves instructions
1942: **********************************/
1943:
1944: static void dsp_undefined(void)
1945: {
1946: if (isDsp_in_disasm_mode == false) {
1947: cur_inst_len = 0;
1948: fprintf(stderr, "Dsp: 0x%04x: 0x%06x Illegal instruction\n",dsp_core.pc, cur_inst);
1949: /* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
1950: dsp_core.instr_cycle += 100;
1951: }
1952: else {
1953: cur_inst_len = 1;
1954: dsp_core.instr_cycle = 0;
1955: }
1956: if (ExceptionDebugMask & EXCEPT_DSP) {
1957: DebugUI(REASON_DSP_EXCEPTION);
1958: }
1959: }
1960:
1961: static void dsp_andi(void)
1962: {
1963: Uint32 regnum, value;
1964:
1965: value = (cur_inst >> 8) & BITMASK(8);
1966: regnum = cur_inst & BITMASK(2);
1967: switch(regnum) {
1968: case 0:
1969: /* mr */
1970: dsp_core.registers[DSP_REG_SR] &= (value<<8)|BITMASK(8);
1971: break;
1972: case 1:
1973: /* ccr */
1974: dsp_core.registers[DSP_REG_SR] &= (BITMASK(8)<<8)|value;
1975: break;
1976: case 2:
1977: /* omr */
1978: dsp_core.registers[DSP_REG_OMR] &= value;
1979: break;
1980: }
1981: }
1982:
1983: static void dsp_bchg_aa(void)
1984: {
1985: Uint32 memspace, addr, value, newcarry, numbit;
1986:
1987: memspace = (cur_inst>>6) & 1;
1988: value = (cur_inst>>8) & BITMASK(6);
1989: numbit = cur_inst & BITMASK(5);
1990:
1991: addr = value;
1992: value = read_memory(memspace, addr);
1993: newcarry = (value>>numbit) & 1;
1994: if (newcarry) {
1995: value -= (1<<numbit);
1996: } else {
1997: value += (1<<numbit);
1998: }
1999: write_memory(memspace, addr, value);
2000:
2001: /* Set carry */
2002: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2003: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2004:
2005: dsp_core.instr_cycle += 2;
2006: }
2007:
2008: static void dsp_bchg_ea(void)
2009: {
2010: Uint32 memspace, addr, value, newcarry, numbit;
2011:
2012: memspace = (cur_inst>>6) & 1;
2013: value = (cur_inst>>8) & BITMASK(6);
2014: numbit = cur_inst & BITMASK(5);
2015:
2016: dsp_calc_ea(value, &addr);
2017: value = read_memory(memspace, addr);
2018: newcarry = (value>>numbit) & 1;
2019: if (newcarry) {
2020: value -= (1<<numbit);
2021: } else {
2022: value += (1<<numbit);
2023: }
2024: write_memory(memspace, addr, value);
2025:
2026: /* Set carry */
2027: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2028: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2029:
2030: dsp_core.instr_cycle += 2;
2031: }
2032:
2033: static void dsp_bchg_pp(void)
2034: {
2035: Uint32 memspace, addr, value, newcarry, numbit;
2036:
2037: memspace = (cur_inst>>6) & 1;
2038: value = (cur_inst>>8) & BITMASK(6);
2039: numbit = cur_inst & BITMASK(5);
2040:
2041: addr = 0xffc0 + value;
2042: value = read_memory(memspace, addr);
2043: newcarry = (value>>numbit) & 1;
2044: if (newcarry) {
2045: value -= (1<<numbit);
2046: } else {
2047: value += (1<<numbit);
2048: }
2049: write_memory(memspace, addr, value);
2050:
2051: /* Set carry */
2052: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2053: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2054:
2055: dsp_core.instr_cycle += 2;
2056: }
2057:
2058: static void dsp_bchg_reg(void)
2059: {
2060: Uint32 value, numreg, newcarry, numbit;
2061:
2062: numreg = (cur_inst>>8) & BITMASK(6);
2063: numbit = cur_inst & BITMASK(5);
2064:
2065: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2066: dsp_pm_read_accu24(numreg, &value);
2067: } else {
2068: value = dsp_core.registers[numreg];
2069: }
2070:
2071: newcarry = (value>>numbit) & 1;
2072: if (newcarry) {
2073: value -= (1<<numbit);
2074: } else {
2075: value += (1<<numbit);
2076: }
2077:
2078: dsp_write_reg(numreg, value);
2079:
2080: /* Set carry */
2081: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2082: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2083:
2084: dsp_core.instr_cycle += 2;
2085: }
2086:
2087: static void dsp_bclr_aa(void)
2088: {
2089: Uint32 memspace, addr, value, newcarry, numbit;
2090:
2091: memspace = (cur_inst>>6) & 1;
2092: addr = (cur_inst>>8) & BITMASK(6);
2093: numbit = cur_inst & BITMASK(5);
2094:
2095: value = read_memory(memspace, addr);
2096: newcarry = (value>>numbit) & 1;
2097: value &= 0xffffffff-(1<<numbit);
2098: write_memory(memspace, addr, value);
2099:
2100: /* Set carry */
2101: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2102: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2103:
2104: dsp_core.instr_cycle += 2;
2105: }
2106:
2107: static void dsp_bclr_ea(void)
2108: {
2109: Uint32 memspace, addr, value, newcarry, numbit;
2110:
2111: memspace = (cur_inst>>6) & 1;
2112: value = (cur_inst>>8) & BITMASK(6);
2113: numbit = cur_inst & BITMASK(5);
2114:
2115: dsp_calc_ea(value, &addr);
2116: value = read_memory(memspace, addr);
2117: newcarry = (value>>numbit) & 1;
2118: value &= 0xffffffff-(1<<numbit);
2119: write_memory(memspace, addr, value);
2120:
2121: /* Set carry */
2122: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2123: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2124:
2125: dsp_core.instr_cycle += 2;
2126: }
2127:
2128: static void dsp_bclr_pp(void)
2129: {
2130: Uint32 memspace, addr, value, newcarry, numbit;
2131:
2132: memspace = (cur_inst>>6) & 1;
2133: value = (cur_inst>>8) & BITMASK(6);
2134: numbit = cur_inst & BITMASK(5);
2135:
2136: addr = 0xffc0 + value;
2137: value = read_memory(memspace, addr);
2138: newcarry = (value>>numbit) & 1;
2139: value &= 0xffffffff-(1<<numbit);
2140: write_memory(memspace, addr, value);
2141:
2142: /* Set carry */
2143: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2144: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2145:
2146: dsp_core.instr_cycle += 2;
2147: }
2148:
2149: static void dsp_bclr_reg(void)
2150: {
2151: Uint32 value, numreg, newcarry, numbit;
2152:
2153: numreg = (cur_inst>>8) & BITMASK(6);
2154: numbit = cur_inst & BITMASK(5);
2155:
2156: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2157: dsp_pm_read_accu24(numreg, &value);
2158: } else {
2159: value = dsp_core.registers[numreg];
2160: }
2161:
2162: newcarry = (value>>numbit) & 1;
2163: value &= 0xffffffff-(1<<numbit);
2164:
2165: dsp_write_reg(numreg, value);
2166:
2167: /* Set carry */
2168: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2169: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2170:
2171: dsp_core.instr_cycle += 2;
2172: }
2173:
2174: static void dsp_bset_aa(void)
2175: {
2176: Uint32 memspace, addr, value, newcarry, numbit;
2177:
2178: memspace = (cur_inst>>6) & 1;
2179: value = (cur_inst>>8) & BITMASK(6);
2180: numbit = cur_inst & BITMASK(5);
2181:
2182: addr = value;
2183: value = read_memory(memspace, addr);
2184: newcarry = (value>>numbit) & 1;
2185: value |= (1<<numbit);
2186: write_memory(memspace, addr, value);
2187:
2188: /* Set carry */
2189: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2190: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2191:
2192: dsp_core.instr_cycle += 2;
2193: }
2194:
2195: static void dsp_bset_ea(void)
2196: {
2197: Uint32 memspace, addr, value, newcarry, numbit;
2198:
2199: memspace = (cur_inst>>6) & 1;
2200: value = (cur_inst>>8) & BITMASK(6);
2201: numbit = cur_inst & BITMASK(5);
2202:
2203: dsp_calc_ea(value, &addr);
2204: value = read_memory(memspace, addr);
2205: newcarry = (value>>numbit) & 1;
2206: value |= (1<<numbit);
2207: write_memory(memspace, addr, value);
2208:
2209: /* Set carry */
2210: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2211: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2212:
2213: dsp_core.instr_cycle += 2;
2214: }
2215:
2216: static void dsp_bset_pp(void)
2217: {
2218: Uint32 memspace, addr, value, newcarry, numbit;
2219:
2220: memspace = (cur_inst>>6) & 1;
2221: value = (cur_inst>>8) & BITMASK(6);
2222: numbit = cur_inst & BITMASK(5);
2223: addr = 0xffc0 + value;
2224: value = read_memory(memspace, addr);
2225: newcarry = (value>>numbit) & 1;
2226: value |= (1<<numbit);
2227: write_memory(memspace, addr, value);
2228:
2229: /* Set carry */
2230: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2231: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2232:
2233: dsp_core.instr_cycle += 2;
2234: }
2235:
2236: static void dsp_bset_reg(void)
2237: {
2238: Uint32 value, numreg, newcarry, numbit;
2239:
2240: numreg = (cur_inst>>8) & BITMASK(6);
2241: numbit = cur_inst & BITMASK(5);
2242:
2243: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2244: dsp_pm_read_accu24(numreg, &value);
2245: } else {
2246: value = dsp_core.registers[numreg];
2247: }
2248:
2249: newcarry = (value>>numbit) & 1;
2250: value |= (1<<numbit);
2251:
2252: dsp_write_reg(numreg, value);
2253:
2254: /* Set carry */
2255: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2256: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2257:
2258: dsp_core.instr_cycle += 2;
2259: }
2260:
2261: static void dsp_btst_aa(void)
2262: {
2263: Uint32 memspace, addr, value, newcarry, numbit;
2264:
2265: memspace = (cur_inst>>6) & 1;
2266: value = (cur_inst>>8) & BITMASK(6);
2267: numbit = cur_inst & BITMASK(5);
2268:
2269: addr = value;
2270: value = read_memory(memspace, addr);
2271: newcarry = (value>>numbit) & 1;
2272:
2273: /* Set carry */
2274: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2275: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2276:
2277: dsp_core.instr_cycle += 2;
2278: }
2279:
2280: static void dsp_btst_ea(void)
2281: {
2282: Uint32 memspace, addr, value, newcarry, numbit;
2283:
2284: memspace = (cur_inst>>6) & 1;
2285: value = (cur_inst>>8) & BITMASK(6);
2286: numbit = cur_inst & BITMASK(5);
2287:
2288: dsp_calc_ea(value, &addr);
2289: value = read_memory(memspace, addr);
2290: newcarry = (value>>numbit) & 1;
2291:
2292: /* Set carry */
2293: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2294: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2295:
2296: dsp_core.instr_cycle += 2;
2297: }
2298:
2299: static void dsp_btst_pp(void)
2300: {
2301: Uint32 memspace, addr, value, newcarry, numbit;
2302:
2303: memspace = (cur_inst>>6) & 1;
2304: value = (cur_inst>>8) & BITMASK(6);
2305: numbit = cur_inst & BITMASK(5);
2306:
2307: addr = 0xffc0 + value;
2308: value = read_memory(memspace, addr);
2309: newcarry = (value>>numbit) & 1;
2310:
2311: /* Set carry */
2312: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2313: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2314:
2315: dsp_core.instr_cycle += 2;
2316: }
2317:
2318: static void dsp_btst_reg(void)
2319: {
2320: Uint32 value, numreg, newcarry, numbit;
2321:
2322: numreg = (cur_inst>>8) & BITMASK(6);
2323: numbit = cur_inst & BITMASK(5);
2324:
2325: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2326: dsp_pm_read_accu24(numreg, &value);
2327: } else {
2328: value = dsp_core.registers[numreg];
2329: }
2330:
2331: newcarry = (value>>numbit) & 1;
2332:
2333: /* Set carry */
2334: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2335: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
2336:
2337: dsp_core.instr_cycle += 2;
2338: }
2339:
2340: static void dsp_div(void)
2341: {
2342: Uint32 srcreg, destreg, source[3], dest[3];
2343: Uint16 newsr;
2344:
2345: srcreg = DSP_REG_NULL;
2346: switch((cur_inst>>4) & BITMASK(2)) {
2347: case 0: srcreg = DSP_REG_X0; break;
2348: case 1: srcreg = DSP_REG_Y0; break;
2349: case 2: srcreg = DSP_REG_X1; break;
2350: case 3: srcreg = DSP_REG_Y1; break;
2351: }
2352: source[2] = 0;
2353: source[1] = dsp_core.registers[srcreg];
2354: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
2355:
2356: destreg = DSP_REG_A + ((cur_inst>>3) & 1);
2357: if (destreg == DSP_REG_A) {
2358: dest[0] = dsp_core.registers[DSP_REG_A2];
2359: dest[1] = dsp_core.registers[DSP_REG_A1];
2360: dest[2] = dsp_core.registers[DSP_REG_A0];
2361: }
2362: else {
2363: dest[0] = dsp_core.registers[DSP_REG_B2];
2364: dest[1] = dsp_core.registers[DSP_REG_B1];
2365: dest[2] = dsp_core.registers[DSP_REG_B0];
2366: }
2367:
2368: if (((dest[0]>>7) & 1) ^ ((source[1]>>23) & 1)) {
2369: /* D += S */
2370: newsr = dsp_asl56(dest);
2371: dsp_add56(source, dest);
2372: } else {
2373: /* D -= S */
2374: newsr = dsp_asl56(dest);
2375: dsp_sub56(source, dest);
2376: }
2377:
2378: dest[2] |= (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
2379:
2380: if (destreg == DSP_REG_A) {
2381: dsp_core.registers[DSP_REG_A2] = dest[0];
2382: dsp_core.registers[DSP_REG_A1] = dest[1];
2383: dsp_core.registers[DSP_REG_A0] = dest[2];
2384: }
2385: else {
2386: dsp_core.registers[DSP_REG_B2] = dest[0];
2387: dsp_core.registers[DSP_REG_B1] = dest[1];
2388: dsp_core.registers[DSP_REG_B0] = dest[2];
2389: }
2390:
2391: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
2392: dsp_core.registers[DSP_REG_SR] |= (1-((dest[0]>>7) & 1))<<DSP_SR_C;
2393: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_L);
2394: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_V);
2395: }
2396:
2397: /*
2398: DO instruction parameter encoding
2399:
2400: xxxxxxxx 00xxxxxx 0xxxxxxx aa
2401: xxxxxxxx 01xxxxxx 0xxxxxxx ea
2402: xxxxxxxx YYxxxxxx 1xxxxxxx imm
2403: xxxxxxxx 11xxxxxx 0xxxxxxx reg
2404: */
2405:
2406: static void dsp_do_aa(void)
2407: {
2408: Uint32 memspace, addr;
2409:
2410: /* x:aa */
2411: /* y:aa */
2412:
2413: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2414: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
2415: cur_inst_len++;
2416: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2417: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
2418:
2419: memspace = (cur_inst>>6) & 1;
2420: addr = (cur_inst>>8) & BITMASK(6);
2421: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
2422:
2423: dsp_core.instr_cycle += 4;
2424: }
2425:
2426: static void dsp_do_imm(void)
2427: {
2428: /* #xx */
2429:
2430: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2431: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
2432: cur_inst_len++;
2433: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2434: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
2435:
2436: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
2437: + ((cur_inst & BITMASK(4))<<8);
2438:
2439: dsp_core.instr_cycle += 4;
2440: }
2441:
2442: static void dsp_do_ea(void)
2443: {
2444: Uint32 memspace, ea_mode, addr;
2445:
2446: /* x:ea */
2447: /* y:ea */
2448:
2449: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2450: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
2451: cur_inst_len++;
2452: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2453: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
2454:
2455: memspace = (cur_inst>>6) & 1;
2456: ea_mode = (cur_inst>>8) & BITMASK(6);
2457: dsp_calc_ea(ea_mode, &addr);
2458: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
2459:
2460: dsp_core.instr_cycle += 4;
2461: }
2462:
2463: static void dsp_do_reg(void)
2464: {
2465: Uint32 numreg;
2466:
2467: /* S */
2468:
2469: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2470: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
2471: cur_inst_len++;
2472:
2473: numreg = (cur_inst>>8) & BITMASK(6);
2474: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
2475: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
2476: } else {
2477: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
2478: }
2479: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
2480:
2481: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2482: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
2483:
2484: dsp_core.instr_cycle += 4;
2485: }
2486:
2487: static void dsp_enddo(void)
2488: {
2489: Uint32 saved_pc, saved_sr;
2490:
2491: dsp_stack_pop(&saved_pc, &saved_sr);
2492: dsp_core.registers[DSP_REG_SR] &= 0x7f;
2493: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
2494: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
2495: }
2496:
2497: static void dsp_illegal(void)
2498: {
2499: /* Raise interrupt p:0x003e */
2500: dsp_set_interrupt(DSP_INTER_ILLEGAL, 1);
2501: if (ExceptionDebugMask & EXCEPT_DSP) {
2502: DebugUI(REASON_DSP_EXCEPTION);
2503: }
2504: }
2505:
2506: static void dsp_jcc_imm(void)
2507: {
2508: Uint32 cc_code, newpc;
2509:
2510: newpc = cur_inst & BITMASK(12);
2511: cc_code=(cur_inst>>12) & BITMASK(4);
2512: if (dsp_calc_cc(cc_code)) {
2513: dsp_core.pc = newpc;
2514: cur_inst_len = 0;
2515: }
2516:
2517: dsp_core.instr_cycle += 2;
2518: }
2519:
2520: static void dsp_jcc_ea(void)
2521: {
2522: Uint32 newpc, cc_code;
2523:
2524: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2525: cc_code=cur_inst & BITMASK(4);
2526:
2527: if (dsp_calc_cc(cc_code)) {
2528: dsp_core.pc = newpc;
2529: cur_inst_len = 0;
2530: }
2531:
2532: dsp_core.instr_cycle += 2;
2533: }
2534:
2535: static void dsp_jclr_aa(void)
2536: {
2537: Uint32 memspace, addr, value, numbit, newaddr;
2538:
2539: memspace = (cur_inst>>6) & 1;
2540: addr = (cur_inst>>8) & BITMASK(6);
2541: numbit = cur_inst & BITMASK(5);
2542: value = read_memory(memspace, addr);
2543: newaddr = read_memory_p(dsp_core.pc+1);
2544:
2545: dsp_core.instr_cycle += 4;
2546:
2547: if ((value & (1<<numbit))==0) {
2548: dsp_core.pc = newaddr;
2549: cur_inst_len = 0;
2550: return;
2551: }
2552: ++cur_inst_len;
2553: }
2554:
2555: static void dsp_jclr_ea(void)
2556: {
2557: Uint32 memspace, addr, value, numbit, newaddr;
2558:
2559: memspace = (cur_inst>>6) & 1;
2560: value = (cur_inst>>8) & BITMASK(6);
2561: numbit = cur_inst & BITMASK(5);
2562: newaddr = read_memory_p(dsp_core.pc+1);
2563:
2564: dsp_calc_ea(value, &addr);
2565: value = read_memory(memspace, addr);
2566:
2567: dsp_core.instr_cycle += 4;
2568:
2569: if ((value & (1<<numbit))==0) {
2570: dsp_core.pc = newaddr;
2571: cur_inst_len = 0;
2572: return;
2573: }
2574: ++cur_inst_len;
2575: }
2576:
2577: static void dsp_jclr_pp(void)
2578: {
2579: Uint32 memspace, addr, value, numbit, newaddr;
2580:
2581: memspace = (cur_inst>>6) & 1;
2582: value = (cur_inst>>8) & BITMASK(6);
2583: numbit = cur_inst & BITMASK(5);
2584: addr = 0xffc0 + value;
2585: value = read_memory(memspace, addr);
2586: newaddr = read_memory_p(dsp_core.pc+1);
2587:
2588: dsp_core.instr_cycle += 4;
2589:
2590: if ((value & (1<<numbit))==0) {
2591: dsp_core.pc = newaddr;
2592: cur_inst_len = 0;
2593: return;
2594: }
2595: ++cur_inst_len;
2596: }
2597:
2598: static void dsp_jclr_reg(void)
2599: {
2600: Uint32 value, numreg, numbit, newaddr;
2601:
2602: numreg = (cur_inst>>8) & BITMASK(6);
2603: numbit = cur_inst & BITMASK(5);
2604: newaddr = read_memory_p(dsp_core.pc+1);
2605:
2606: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2607: dsp_pm_read_accu24(numreg, &value);
2608: } else {
2609: value = dsp_core.registers[numreg];
2610: }
2611:
2612: dsp_core.instr_cycle += 4;
2613:
2614: if ((value & (1<<numbit))==0) {
2615: dsp_core.pc = newaddr;
2616: cur_inst_len = 0;
2617: return;
2618: }
2619: ++cur_inst_len;
2620: }
2621:
2622: static void dsp_jmp_ea(void)
2623: {
2624: Uint32 newpc;
2625:
2626: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &newpc);
2627: cur_inst_len = 0;
2628: dsp_core.pc = newpc;
2629:
2630: dsp_core.instr_cycle += 2;
2631: }
2632:
2633: static void dsp_jmp_imm(void)
2634: {
2635: Uint32 newpc;
2636:
2637: newpc = cur_inst & BITMASK(12);
2638: cur_inst_len = 0;
2639: dsp_core.pc = newpc;
2640:
2641: dsp_core.instr_cycle += 2;
2642: }
2643:
2644: static void dsp_jscc_ea(void)
2645: {
2646: Uint32 newpc, cc_code;
2647:
2648: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2649: cc_code=cur_inst & BITMASK(4);
2650:
2651: if (dsp_calc_cc(cc_code)) {
2652: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2653: dsp_core.pc = newpc;
2654: cur_inst_len = 0;
2655: }
2656:
2657: dsp_core.instr_cycle += 2;
2658: }
2659:
2660: static void dsp_jscc_imm(void)
2661: {
2662: Uint32 cc_code, newpc;
2663:
2664: newpc = cur_inst & BITMASK(12);
2665: cc_code=(cur_inst>>12) & BITMASK(4);
2666: if (dsp_calc_cc(cc_code)) {
2667: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2668: dsp_core.pc = newpc;
2669: cur_inst_len = 0;
2670: }
2671:
2672: dsp_core.instr_cycle += 2;
2673: }
2674:
2675: static void dsp_jsclr_aa(void)
2676: {
2677: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2678:
2679: memspace = (cur_inst>>6) & 1;
2680: addr = (cur_inst>>8) & BITMASK(6);
2681: numbit = cur_inst & BITMASK(5);
2682: value = read_memory(memspace, addr);
2683: newaddr = read_memory_p(dsp_core.pc+1);
2684:
2685: dsp_core.instr_cycle += 4;
2686:
2687: if ((value & (1<<numbit))==0) {
2688: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
2689: newpc = newaddr;
2690: dsp_core.pc = newpc;
2691: cur_inst_len = 0;
2692: return;
2693: }
2694: ++cur_inst_len;
2695: }
2696:
2697: static void dsp_jsclr_ea(void)
2698: {
2699: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2700:
2701: memspace = (cur_inst>>6) & 1;
2702: value = (cur_inst>>8) & BITMASK(6);
2703: numbit = cur_inst & BITMASK(5);
2704: dsp_calc_ea(value, &addr);
2705: value = read_memory(memspace, addr);
2706: newaddr = read_memory_p(dsp_core.pc+1);
2707:
2708: dsp_core.instr_cycle += 4;
2709:
2710: if ((value & (1<<numbit))==0) {
2711: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
2712: newpc = newaddr;
2713: dsp_core.pc = newpc;
2714: cur_inst_len = 0;
2715: return;
2716: }
2717: ++cur_inst_len;
2718: }
2719:
2720: static void dsp_jsclr_pp(void)
2721: {
2722: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2723:
2724: memspace = (cur_inst>>6) & 1;
2725: value = (cur_inst>>8) & BITMASK(6);
2726: numbit = cur_inst & BITMASK(5);
2727: addr = 0xffc0 + value;
2728: value = read_memory(memspace, addr);
2729: newaddr = read_memory_p(dsp_core.pc+1);
2730:
2731: dsp_core.instr_cycle += 4;
2732:
2733: if ((value & (1<<numbit))==0) {
2734: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
2735: newpc = newaddr;
2736: dsp_core.pc = newpc;
2737: cur_inst_len = 0;
2738: return;
2739: }
2740: ++cur_inst_len;
2741: }
2742:
2743: static void dsp_jsclr_reg(void)
2744: {
2745: Uint32 value, numreg, newpc, numbit, newaddr;
2746:
2747: numreg = (cur_inst>>8) & BITMASK(6);
2748: numbit = cur_inst & BITMASK(5);
2749: newaddr = read_memory_p(dsp_core.pc+1);
2750:
2751: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2752: dsp_pm_read_accu24(numreg, &value);
2753: } else {
2754: value = dsp_core.registers[numreg];
2755: }
2756:
2757: dsp_core.instr_cycle += 4;
2758:
2759: if ((value & (1<<numbit))==0) {
2760: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
2761: newpc = newaddr;
2762: dsp_core.pc = newpc;
2763: cur_inst_len = 0;
2764: return;
2765: }
2766: ++cur_inst_len;
2767: }
2768:
2769: static void dsp_jset_aa(void)
2770: {
2771: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2772:
2773: memspace = (cur_inst>>6) & 1;
2774: addr = (cur_inst>>8) & BITMASK(6);
2775: numbit = cur_inst & BITMASK(5);
2776: value = read_memory(memspace, addr);
2777: newaddr = read_memory_p(dsp_core.pc+1);
2778:
2779: dsp_core.instr_cycle += 4;
2780:
2781: if (value & (1<<numbit)) {
2782: newpc = newaddr;
2783: dsp_core.pc = newpc;
2784: cur_inst_len=0;
2785: return;
2786: }
2787: ++cur_inst_len;
2788: }
2789:
2790: static void dsp_jset_ea(void)
2791: {
2792: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2793:
2794: memspace = (cur_inst>>6) & 1;
2795: value = (cur_inst>>8) & BITMASK(6);
2796: numbit = cur_inst & BITMASK(5);
2797: dsp_calc_ea(value, &addr);
2798: value = read_memory(memspace, addr);
2799: newaddr = read_memory_p(dsp_core.pc+1);
2800:
2801: dsp_core.instr_cycle += 4;
2802:
2803: if (value & (1<<numbit)) {
2804: newpc = newaddr;
2805: dsp_core.pc = newpc;
2806: cur_inst_len=0;
2807: return;
2808: }
2809: ++cur_inst_len;
2810: }
2811:
2812: static void dsp_jset_pp(void)
2813: {
2814: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2815:
2816: memspace = (cur_inst>>6) & 1;
2817: value = (cur_inst>>8) & BITMASK(6);
2818: numbit = cur_inst & BITMASK(5);
2819: addr = 0xffc0 + value;
2820: value = read_memory(memspace, addr);
2821: newaddr = read_memory_p(dsp_core.pc+1);
2822:
2823: dsp_core.instr_cycle += 4;
2824:
2825: if (value & (1<<numbit)) {
2826: newpc = newaddr;
2827: dsp_core.pc = newpc;
2828: cur_inst_len=0;
2829: return;
2830: }
2831: ++cur_inst_len;
2832: }
2833:
2834: static void dsp_jset_reg(void)
2835: {
2836: Uint32 value, numreg, numbit, newpc, newaddr;
2837:
2838: numreg = (cur_inst>>8) & BITMASK(6);
2839: numbit = cur_inst & BITMASK(5);
2840: newaddr = read_memory_p(dsp_core.pc+1);
2841:
2842: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2843: dsp_pm_read_accu24(numreg, &value);
2844: } else {
2845: value = dsp_core.registers[numreg];
2846: }
2847:
2848: dsp_core.instr_cycle += 4;
2849:
2850: if (value & (1<<numbit)) {
2851: newpc = newaddr;
2852: dsp_core.pc = newpc;
2853: cur_inst_len=0;
2854: return;
2855: }
2856: ++cur_inst_len;
2857: }
2858:
2859: static void dsp_jsr_imm(void)
2860: {
2861: Uint32 newpc;
2862:
2863: newpc = cur_inst & BITMASK(12);
2864:
2865: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2866: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2867: }
2868: else {
2869: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
2870: }
2871:
2872: dsp_core.pc = newpc;
2873: cur_inst_len = 0;
2874:
2875: dsp_core.instr_cycle += 2;
2876: }
2877:
2878: static void dsp_jsr_ea(void)
2879: {
2880: Uint32 newpc;
2881:
2882: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&newpc);
2883:
2884: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2885: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2886: }
2887: else {
2888: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
2889: }
2890:
2891: dsp_core.pc = newpc;
2892: cur_inst_len = 0;
2893:
2894: dsp_core.instr_cycle += 2;
2895: }
2896:
2897: static void dsp_jsset_aa(void)
2898: {
2899: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2900:
2901: memspace = (cur_inst>>6) & 1;
2902: addr = (cur_inst>>8) & BITMASK(6);
2903: numbit = cur_inst & BITMASK(5);
2904: value = read_memory(memspace, addr);
2905: newaddr = read_memory_p(dsp_core.pc+1);
2906:
2907: dsp_core.instr_cycle += 4;
2908:
2909: if (value & (1<<numbit)) {
2910: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
2911: newpc = newaddr;
2912: dsp_core.pc = newpc;
2913: cur_inst_len = 0;
2914: return;
2915: }
2916: ++cur_inst_len;
2917: }
2918:
2919: static void dsp_jsset_ea(void)
2920: {
2921: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2922:
2923: memspace = (cur_inst>>6) & 1;
2924: value = (cur_inst>>8) & BITMASK(6);
2925: numbit = cur_inst & BITMASK(5);
2926: dsp_calc_ea(value, &addr);
2927: value = read_memory(memspace, addr);
2928: newaddr = read_memory_p(dsp_core.pc+1);
2929:
2930: dsp_core.instr_cycle += 4;
2931:
2932: if (value & (1<<numbit)) {
2933: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
2934: newpc = newaddr;
2935: dsp_core.pc = newpc;
2936: cur_inst_len = 0;
2937: return;
2938: }
2939: ++cur_inst_len;
2940: }
2941:
2942: static void dsp_jsset_pp(void)
2943: {
2944: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2945:
2946: memspace = (cur_inst>>6) & 1;
2947: value = (cur_inst>>8) & BITMASK(6);
2948: numbit = cur_inst & BITMASK(5);
2949: addr = 0xffc0 + value;
2950: value = read_memory(memspace, addr);
2951: newaddr = read_memory_p(dsp_core.pc+1);
2952:
2953: dsp_core.instr_cycle += 4;
2954:
2955: if (value & (1<<numbit)) {
2956: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
2957: newpc = newaddr;
2958: dsp_core.pc = newpc;
2959: cur_inst_len = 0;
2960: return;
2961: }
2962: ++cur_inst_len;
2963: }
2964:
2965: static void dsp_jsset_reg(void)
2966: {
2967: Uint32 value, numreg, newpc, numbit, newaddr;
2968:
2969: numreg = (cur_inst>>8) & BITMASK(6);
2970: numbit = cur_inst & BITMASK(5);
2971: newaddr = read_memory_p(dsp_core.pc+1);
2972:
2973: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2974: dsp_pm_read_accu24(numreg, &value);
2975: } else {
2976: value = dsp_core.registers[numreg];
2977: }
2978:
2979: dsp_core.instr_cycle += 4;
2980:
2981: if (value & (1<<numbit)) {
2982: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
2983: newpc = newaddr;
2984: dsp_core.pc = newpc;
2985: cur_inst_len = 0;
2986: return;
2987: }
2988: ++cur_inst_len;
2989: }
2990:
2991: static void dsp_lua(void)
2992: {
2993: Uint32 value, srcreg, dstreg, srcsave, srcnew;
2994:
2995: srcreg = (cur_inst>>8) & BITMASK(3);
2996:
2997: srcsave = dsp_core.registers[DSP_REG_R0+srcreg];
2998: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &value);
2999: srcnew = dsp_core.registers[DSP_REG_R0+srcreg];
3000: dsp_core.registers[DSP_REG_R0+srcreg] = srcsave;
3001:
3002: dstreg = cur_inst & BITMASK(3);
3003:
3004: if (cur_inst & (1<<3)) {
3005: dsp_core.registers[DSP_REG_N0+dstreg] = srcnew;
3006: } else {
3007: dsp_core.registers[DSP_REG_R0+dstreg] = srcnew;
3008: }
3009:
3010: dsp_core.instr_cycle += 2;
3011: }
3012:
3013: static void dsp_movec_reg(void)
3014: {
3015: Uint32 numreg1, numreg2, value, dummy;
3016:
3017: /* S1,D2 */
3018: /* S2,D1 */
3019:
3020: numreg2 = (cur_inst>>8) & BITMASK(6);
3021: numreg1 = cur_inst & BITMASK(6);
3022:
3023: if (cur_inst & (1<<15)) {
3024: /* Write D1 */
3025:
3026: if ((numreg2 == DSP_REG_A) || (numreg2 == DSP_REG_B)) {
3027: dsp_pm_read_accu24(numreg2, &value);
3028: } else {
3029: value = dsp_core.registers[numreg2];
3030: }
3031: value &= BITMASK(registers_mask[numreg1]);
3032: dsp_write_reg(numreg1, value);
3033: } else {
3034: /* Read S1 */
3035: if (numreg1 == DSP_REG_SSH) {
3036: dsp_stack_pop(&value, &dummy);
3037: }
3038: else {
3039: value = dsp_core.registers[numreg1];
3040: }
3041:
3042: if (numreg2 == DSP_REG_A) {
3043: dsp_core.registers[DSP_REG_A0] = 0;
3044: dsp_core.registers[DSP_REG_A1] = value & BITMASK(24);
3045: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
3046: }
3047: else if (numreg2 == DSP_REG_B) {
3048: dsp_core.registers[DSP_REG_B0] = 0;
3049: dsp_core.registers[DSP_REG_B1] = value & BITMASK(24);
3050: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
3051: }
3052: else {
3053: dsp_core.registers[numreg2] = value & BITMASK(registers_mask[numreg2]);
3054: }
3055: }
3056: }
3057:
3058: static void dsp_movec_aa(void)
3059: {
3060: Uint32 numreg, addr, memspace, value, dummy;
3061:
3062: /* x:aa,D1 */
3063: /* S1,x:aa */
3064: /* y:aa,D1 */
3065: /* S1,y:aa */
3066:
3067: numreg = cur_inst & BITMASK(6);
3068: addr = (cur_inst>>8) & BITMASK(6);
3069: memspace = (cur_inst>>6) & 1;
3070:
3071: if (cur_inst & (1<<15)) {
3072: /* Write D1 */
3073: value = read_memory(memspace, addr);
3074: value &= BITMASK(registers_mask[numreg]);
3075: dsp_write_reg(numreg, value);
3076: } else {
3077: /* Read S1 */
3078: if (numreg == DSP_REG_SSH) {
3079: dsp_stack_pop(&value, &dummy);
3080: }
3081: else {
3082: value = dsp_core.registers[numreg];
3083: }
3084: write_memory(memspace, addr, value);
3085: }
3086: }
3087:
3088: static void dsp_movec_imm(void)
3089: {
3090: Uint32 numreg, value;
3091:
3092: /* #xx,D1 */
3093: numreg = cur_inst & BITMASK(6);
3094: value = (cur_inst>>8) & BITMASK(8);
3095: value &= BITMASK(registers_mask[numreg]);
3096: dsp_write_reg(numreg, value);
3097: }
3098:
3099: static void dsp_movec_ea(void)
3100: {
3101: Uint32 numreg, addr, memspace, ea_mode, value, dummy;
3102: int retour;
3103:
3104: /* x:ea,D1 */
3105: /* S1,x:ea */
3106: /* y:ea,D1 */
3107: /* S1,y:ea */
3108: /* #xxxx,D1 */
3109:
3110: numreg = cur_inst & BITMASK(6);
3111: ea_mode = (cur_inst>>8) & BITMASK(6);
3112: memspace = (cur_inst>>6) & 1;
3113:
3114: if (cur_inst & (1<<15)) {
3115: /* Write D1 */
3116: retour = dsp_calc_ea(ea_mode, &addr);
3117: if (retour) {
3118: value = addr;
3119: } else {
3120: value = read_memory(memspace, addr);
3121: }
3122: value &= BITMASK(registers_mask[numreg]);
3123: dsp_write_reg(numreg, value);
3124: } else {
3125: /* Read S1 */
3126: dsp_calc_ea(ea_mode, &addr);
3127: if (numreg == DSP_REG_SSH) {
3128: dsp_stack_pop(&value, &dummy);
3129: }
3130: else {
3131: value = dsp_core.registers[numreg];
3132: }
3133: write_memory(memspace, addr, value);
3134: }
3135: }
3136:
3137: static void dsp_movem_aa(void)
3138: {
3139: Uint32 numreg, addr, value, dummy;
3140:
3141: numreg = cur_inst & BITMASK(6);
3142: addr = (cur_inst>>8) & BITMASK(6);
3143:
3144: if (cur_inst & (1<<15)) {
3145: /* Write D */
3146: value = read_memory_p(addr);
3147: value &= BITMASK(registers_mask[numreg]);
3148: dsp_write_reg(numreg, value);
3149: } else {
3150: /* Read S */
3151: if (numreg == DSP_REG_SSH) {
3152: dsp_stack_pop(&value, &dummy);
3153: }
3154: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3155: dsp_pm_read_accu24(numreg, &value);
3156: }
3157: else {
3158: value = dsp_core.registers[numreg];
3159: }
3160: write_memory(DSP_SPACE_P, addr, value);
3161: }
3162:
3163: dsp_core.instr_cycle += 4;
3164: }
3165:
3166: static void dsp_movem_ea(void)
3167: {
3168: Uint32 numreg, addr, ea_mode, value, dummy;
3169:
3170: numreg = cur_inst & BITMASK(6);
3171: ea_mode = (cur_inst>>8) & BITMASK(6);
3172: dsp_calc_ea(ea_mode, &addr);
3173:
3174: if (cur_inst & (1<<15)) {
3175: /* Write D */
3176: value = read_memory_p(addr);
3177: value &= BITMASK(registers_mask[numreg]);
3178: dsp_write_reg(numreg, value);
3179: } else {
3180: /* Read S */
3181: if (numreg == DSP_REG_SSH) {
3182: dsp_stack_pop(&value, &dummy);
3183: }
3184: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3185: dsp_pm_read_accu24(numreg, &value);
3186: }
3187: else {
3188: value = dsp_core.registers[numreg];
3189: }
3190: write_memory(DSP_SPACE_P, addr, value);
3191: }
3192:
3193: dsp_core.instr_cycle += 4;
3194: }
3195:
3196: static void dsp_movep_0(void)
3197: {
3198: /* S,x:pp */
3199: /* x:pp,D */
3200: /* S,y:pp */
3201: /* y:pp,D */
3202:
3203: Uint32 addr, memspace, numreg, value, dummy;
3204:
3205: addr = 0xffc0 + (cur_inst & BITMASK(6));
3206: memspace = (cur_inst>>16) & 1;
3207: numreg = (cur_inst>>8) & BITMASK(6);
3208:
3209: if (cur_inst & (1<<15)) {
3210: /* Write pp */
3211: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3212: dsp_pm_read_accu24(numreg, &value);
3213: }
3214: else if (numreg == DSP_REG_SSH) {
3215: dsp_stack_pop(&value, &dummy);
3216: }
3217: else {
3218: value = dsp_core.registers[numreg];
3219: }
3220: write_memory(memspace, addr, value);
3221: } else {
3222: /* Read pp */
3223: value = read_memory(memspace, addr);
3224: value &= BITMASK(registers_mask[numreg]);
3225: dsp_write_reg(numreg, value);
3226: }
3227:
3228: dsp_core.instr_cycle += 2;
3229: }
3230:
3231: static void dsp_movep_1(void)
3232: {
3233: /* p:ea,x:pp */
3234: /* x:pp,p:ea */
3235: /* p:ea,y:pp */
3236: /* y:pp,p:ea */
3237:
3238: Uint32 xyaddr, memspace, paddr;
3239:
3240: xyaddr = 0xffc0 + (cur_inst & BITMASK(6));
3241: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &paddr);
3242: memspace = (cur_inst>>16) & 1;
3243:
3244: if (cur_inst & (1<<15)) {
3245: /* Write pp */
3246: write_memory(memspace, xyaddr, read_memory_p(paddr));
3247: } else {
3248: /* Read pp */
3249: write_memory(DSP_SPACE_P, paddr, read_memory(memspace, xyaddr));
3250: }
3251:
3252: /* Movep is 4 cycles, but according to the motorola doc, */
3253: /* movep from p memory to x or y peripheral memory takes */
3254: /* 2 more cycles, so +4 cycles at total */
3255: dsp_core.instr_cycle += 4;
3256: }
3257:
3258: static void dsp_movep_23(void)
3259: {
3260: /* x:ea,x:pp */
3261: /* y:ea,x:pp */
3262: /* #xxxxxx,x:pp */
3263: /* x:pp,x:ea */
3264: /* x:pp,y:pp */
3265: /* x:ea,y:pp */
3266: /* y:ea,y:pp */
3267: /* #xxxxxx,y:pp */
3268: /* y:pp,y:ea */
3269: /* y:pp,x:ea */
3270:
3271: Uint32 addr, peraddr, easpace, perspace, ea_mode;
3272: int retour;
3273:
3274: peraddr = 0xffc0 + (cur_inst & BITMASK(6));
3275: perspace = (cur_inst>>16) & 1;
3276:
3277: ea_mode = (cur_inst>>8) & BITMASK(6);
3278: easpace = (cur_inst>>6) & 1;
3279: retour = dsp_calc_ea(ea_mode, &addr);
3280:
3281: if (cur_inst & (1<<15)) {
3282: /* Write pp */
3283:
3284: if (retour) {
3285: write_memory(perspace, peraddr, addr);
3286: } else {
3287: write_memory(perspace, peraddr, read_memory(easpace, addr));
3288: }
3289: } else {
3290: /* Read pp */
3291: write_memory(easpace, addr, read_memory(perspace, peraddr));
3292: }
3293:
3294: dsp_core.instr_cycle += 2;
3295: }
3296:
3297: static void dsp_norm(void)
3298: {
3299: Uint32 cursr,cur_e, cur_euz, dest[3], numreg, rreg;
3300: Uint16 newsr;
3301:
3302: cursr = dsp_core.registers[DSP_REG_SR];
3303: cur_e = (cursr>>DSP_SR_E) & 1; /* E */
3304: cur_euz = ~cur_e; /* (not E) and U and (not Z) */
3305: cur_euz &= (cursr>>DSP_SR_U) & 1;
3306: cur_euz &= ~((cursr>>DSP_SR_Z) & 1);
3307: cur_euz &= 1;
3308:
3309: numreg = (cur_inst>>3) & 1;
3310: dest[0] = dsp_core.registers[DSP_REG_A2+numreg];
3311: dest[1] = dsp_core.registers[DSP_REG_A1+numreg];
3312: dest[2] = dsp_core.registers[DSP_REG_A0+numreg];
3313: rreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3314:
3315: if (cur_euz) {
3316: newsr = dsp_asl56(dest);
3317: --dsp_core.registers[rreg];
3318: dsp_core.registers[rreg] &= BITMASK(16);
3319: } else if (cur_e) {
3320: newsr = dsp_asr56(dest);
3321: ++dsp_core.registers[rreg];
3322: dsp_core.registers[rreg] &= BITMASK(16);
3323: } else {
3324: newsr = 0;
3325: }
3326:
3327: dsp_core.registers[DSP_REG_A2+numreg] = dest[0];
3328: dsp_core.registers[DSP_REG_A1+numreg] = dest[1];
3329: dsp_core.registers[DSP_REG_A0+numreg] = dest[2];
3330:
3331: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
3332:
3333: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
3334: dsp_core.registers[DSP_REG_SR] |= newsr;
3335: }
3336:
3337: static void dsp_ori(void)
3338: {
3339: Uint32 regnum, value;
3340:
3341: value = (cur_inst >> 8) & BITMASK(8);
3342: regnum = cur_inst & BITMASK(2);
3343: switch(regnum) {
3344: case 0:
3345: /* mr */
3346: dsp_core.registers[DSP_REG_SR] |= value<<8;
3347: break;
3348: case 1:
3349: /* ccr */
3350: dsp_core.registers[DSP_REG_SR] |= value;
3351: break;
3352: case 2:
3353: /* omr */
3354: dsp_core.registers[DSP_REG_OMR] |= value;
3355: break;
3356: }
3357: }
3358:
3359: /*
3360: REP instruction parameter encoding
3361:
3362: xxxxxxxx 00xxxxxx 0xxxxxxx aa
3363: xxxxxxxx 01xxxxxx 0xxxxxxx ea
3364: xxxxxxxx YYxxxxxx 1xxxxxxx imm
3365: xxxxxxxx 11xxxxxx 0xxxxxxx reg
3366: */
3367:
3368: static void dsp_rep_aa(void)
3369: {
3370: /* x:aa */
3371: /* y:aa */
3372: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3373: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3374: dsp_core.loop_rep = 1; /* We are now running rep */
3375:
3376: dsp_core.registers[DSP_REG_LC]=read_memory((cur_inst>>6) & 1,(cur_inst>>8) & BITMASK(6));
3377:
3378: dsp_core.instr_cycle += 2;
3379: }
3380:
3381: static void dsp_rep_imm(void)
3382: {
3383: /* #xxx */
3384:
3385: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3386: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3387: dsp_core.loop_rep = 1; /* We are now running rep */
3388:
3389: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
3390: + ((cur_inst & BITMASK(4))<<8);
3391:
3392: dsp_core.instr_cycle += 2;
3393: }
3394:
3395: static void dsp_rep_ea(void)
3396: {
3397: Uint32 value;
3398:
3399: /* x:ea */
3400: /* y:ea */
3401:
3402: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3403: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3404: dsp_core.loop_rep = 1; /* We are now running rep */
3405:
3406: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&value);
3407: dsp_core.registers[DSP_REG_LC]= read_memory((cur_inst>>6) & 1, value);
3408:
3409: dsp_core.instr_cycle += 2;
3410: }
3411:
3412: static void dsp_rep_reg(void)
3413: {
3414: Uint32 numreg;
3415:
3416: /* R */
3417:
3418: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3419: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3420: dsp_core.loop_rep = 1; /* We are now running rep */
3421:
3422: numreg = (cur_inst>>8) & BITMASK(6);
3423: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3424: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
3425: } else {
3426: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
3427: }
3428: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
3429:
3430: dsp_core.instr_cycle += 2;
3431: }
3432:
3433: static void dsp_reset(void)
3434: {
3435: /* Reset external peripherals */
3436: dsp_core.instr_cycle += 2;
3437: }
3438:
3439: static void dsp_rti(void)
3440: {
3441: Uint32 newpc = 0, newsr = 0;
3442:
3443: dsp_stack_pop(&newpc, &newsr);
3444: dsp_core.pc = newpc;
3445: dsp_core.registers[DSP_REG_SR] = newsr;
3446: cur_inst_len = 0;
3447:
3448: dsp_core.instr_cycle += 2;
3449: }
3450:
3451: static void dsp_rts(void)
3452: {
3453: Uint32 newpc = 0, newsr;
3454:
3455: dsp_stack_pop(&newpc, &newsr);
3456: dsp_core.pc = newpc;
3457: cur_inst_len = 0;
3458:
3459: dsp_core.instr_cycle += 2;
3460: }
3461:
3462: static void dsp_stop(void)
3463: {
3464: LOG_TRACE(TRACE_DSP_STATE, "Dsp: STOP instruction\n");
3465: }
3466:
3467: static void dsp_swi(void)
3468: {
3469: /* Raise interrupt p:0x0006 */
3470: dsp_core.instr_cycle += 6;
3471: }
3472:
3473: static void dsp_tcc(void)
3474: {
3475: Uint32 cc_code, regsrc1, regdest1;
3476: Uint32 regsrc2, regdest2;
3477: Uint32 val0, val1, val2;
3478:
3479: cc_code = (cur_inst>>12) & BITMASK(4);
3480:
3481: if (dsp_calc_cc(cc_code)) {
3482: regsrc1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
3483: regdest1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
3484:
3485: /* Read S1 */
3486: if (regsrc1 == DSP_REG_A) {
3487: val0 = dsp_core.registers[DSP_REG_A0];
3488: val1 = dsp_core.registers[DSP_REG_A1];
3489: val2 = dsp_core.registers[DSP_REG_A2];
3490: }
3491: else if (regsrc1 == DSP_REG_B) {
3492: val0 = dsp_core.registers[DSP_REG_B0];
3493: val1 = dsp_core.registers[DSP_REG_B1];
3494: val2 = dsp_core.registers[DSP_REG_B2];
3495: }
3496: else {
3497: val0 = 0;
3498: val1 = dsp_core.registers[regsrc1];
3499: val2 = val1 & (1<<23) ? 0xff : 0x0;
3500: }
3501:
3502: /* Write D1 */
3503: if (regdest1 == DSP_REG_A) {
3504: dsp_core.registers[DSP_REG_A2] = val2;
3505: dsp_core.registers[DSP_REG_A1] = val1;
3506: dsp_core.registers[DSP_REG_A0] = val0;
3507: }
3508: else {
3509: dsp_core.registers[DSP_REG_B2] = val2;
3510: dsp_core.registers[DSP_REG_B1] = val1;
3511: dsp_core.registers[DSP_REG_B0] = val0;
3512: }
3513:
3514: /* S2,D2 transfer */
3515: if (cur_inst & (1<<16)) {
3516: regsrc2 = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3517: regdest2 = DSP_REG_R0+(cur_inst & BITMASK(3));
3518:
3519: dsp_core.registers[regdest2] = dsp_core.registers[regsrc2];
3520: }
3521: }
3522: }
3523:
3524: static void dsp_wait(void)
3525: {
3526: LOG_TRACE(TRACE_DSP_STATE, "Dsp: WAIT instruction\n");
3527: }
3528:
3529: static int dsp_pm_read_accu24(int numreg, Uint32 *dest)
3530: {
3531: Uint32 scaling, value, reg;
3532: int got_limited = 0;
3533:
3534: /* Read an accumulator, stores it limited */
3535:
3536: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
3537: reg = numreg & 1;
3538:
3539: value = (dsp_core.registers[DSP_REG_A2+reg]) << 24;
3540: value += dsp_core.registers[DSP_REG_A1+reg];
3541:
3542: switch(scaling) {
3543: case 0:
3544: /* No scaling */
3545: break;
3546: case 1:
3547: /* scaling down */
3548: value >>= 1;
3549: break;
3550: case 2:
3551: /* scaling up */
3552: value <<= 1;
3553: value |= (dsp_core.registers[DSP_REG_A0+reg]>>23) & 1;
3554: break;
3555: /* indeterminate */
3556: case 3:
3557: break;
3558: }
3559:
3560: /* limiting ? */
3561: value &= BITMASK(24);
3562:
3563: if (dsp_core.registers[DSP_REG_A2+reg] == 0) {
3564: if (value <= 0x007fffff) {
3565: /* No limiting */
3566: *dest=value;
3567: return 0;
3568: }
3569: }
3570:
3571: if (dsp_core.registers[DSP_REG_A2+reg] == 0xff) {
3572: if (value >= 0x00800000) {
3573: /* No limiting */
3574: *dest=value;
3575: return 0;
3576: }
3577: }
3578:
3579: if (dsp_core.registers[DSP_REG_A2+reg] & (1<<7)) {
3580: /* Limited to maximum negative value */
3581: *dest=0x00800000;
3582: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
3583: got_limited=1;
3584: } else {
3585: /* Limited to maximal positive value */
3586: *dest=0x007fffff;
3587: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
3588: got_limited=1;
3589: }
3590:
3591: return got_limited;
3592: }
3593:
3594: static void dsp_pm_0(void)
3595: {
3596: Uint32 memspace, numreg, addr, save_accu, save_xy0;
3597: /*
3598: 0000 100d 00mm mrrr S,x:ea x0,D
3599: 0000 100d 10mm mrrr S,y:ea y0,D
3600: */
3601: memspace = (cur_inst>>15) & 1;
3602: numreg = (cur_inst>>16) & 1;
3603: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &addr);
3604:
3605: /* Save A or B */
3606: dsp_pm_read_accu24(numreg, &save_accu);
3607:
3608: /* Save X0 or Y0 */
3609: save_xy0 = dsp_core.registers[DSP_REG_X0+(memspace<<1)];
3610:
3611: /* Execute parallel instruction */
3612: opcodes_alu[cur_inst & BITMASK(8)]();
3613:
3614: /* Move [A|B] to [x|y]:ea */
3615: write_memory(memspace, addr, save_accu);
3616:
3617: /* Move [x|y]0 to [A|B] */
3618: dsp_core.registers[DSP_REG_A0+numreg] = 0;
3619: dsp_core.registers[DSP_REG_A1+numreg] = save_xy0;
3620: dsp_core.registers[DSP_REG_A2+numreg] = save_xy0 & (1<<23) ? 0xff : 0x0;
3621: }
3622:
3623: static void dsp_pm_1(void)
3624: {
3625: Uint32 memspace, numreg1, numreg2, value, xy_addr, retour, save_1, save_2;
3626: /*
3627: 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
3628: S1,x:ea S2,D2
3629: #xxxxxx,D1 S2,D2
3630: 0001 deff w1mm mrrr S1,D1 y:ea,D2
3631: S1,D1 S2,y:ea
3632: S1,D1 #xxxxxx,D2
3633: */
3634: value = (cur_inst>>8) & BITMASK(6);
3635: retour = dsp_calc_ea(value, &xy_addr);
3636: memspace = (cur_inst>>14) & 1;
3637: numreg1 = numreg2 = DSP_REG_NULL;
3638:
3639: if (memspace) {
3640: /* Y: */
3641: switch((cur_inst>>16) & BITMASK(2)) {
3642: case 0: numreg1 = DSP_REG_Y0; break;
3643: case 1: numreg1 = DSP_REG_Y1; break;
3644: case 2: numreg1 = DSP_REG_A; break;
3645: case 3: numreg1 = DSP_REG_B; break;
3646: }
3647: } else {
3648: /* X: */
3649: switch((cur_inst>>18) & BITMASK(2)) {
3650: case 0: numreg1 = DSP_REG_X0; break;
3651: case 1: numreg1 = DSP_REG_X1; break;
3652: case 2: numreg1 = DSP_REG_A; break;
3653: case 3: numreg1 = DSP_REG_B; break;
3654: }
3655: }
3656:
3657: if (cur_inst & (1<<15)) {
3658: /* Write D1 */
3659: if (retour)
3660: save_1 = xy_addr;
3661: else
3662: save_1 = read_memory(memspace, xy_addr);
3663: } else {
3664: /* Read S1 */
3665: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3666: dsp_pm_read_accu24(numreg1, &save_1);
3667: else
3668: save_1 = dsp_core.registers[numreg1];
3669: }
3670:
3671: /* S2 */
3672: if (memspace) {
3673: /* Y: */
3674: numreg2 = DSP_REG_A + ((cur_inst>>19) & 1);
3675: } else {
3676: /* X: */
3677: numreg2 = DSP_REG_A + ((cur_inst>>17) & 1);
3678: }
3679: dsp_pm_read_accu24(numreg2, &save_2);
3680:
3681:
3682: /* Execute parallel instruction */
3683: opcodes_alu[cur_inst & BITMASK(8)]();
3684:
3685:
3686: /* Write parallel move values */
3687: if (cur_inst & (1<<15)) {
3688: /* Write D1 */
3689: if (numreg1 == DSP_REG_A) {
3690: dsp_core.registers[DSP_REG_A0] = 0x0;
3691: dsp_core.registers[DSP_REG_A1] = save_1;
3692: dsp_core.registers[DSP_REG_A2] = save_1 & (1<<23) ? 0xff : 0x0;
3693: }
3694: else if (numreg1 == DSP_REG_B) {
3695: dsp_core.registers[DSP_REG_B0] = 0x0;
3696: dsp_core.registers[DSP_REG_B1] = save_1;
3697: dsp_core.registers[DSP_REG_B2] = save_1 & (1<<23) ? 0xff : 0x0;
3698: }
3699: else {
3700: } dsp_core.registers[numreg1] = save_1;
3701: } else {
3702: /* Read S1 */
3703: write_memory(memspace, xy_addr, save_1);
3704: }
3705:
3706: /* S2 -> D2 */
3707: if (memspace) {
3708: /* Y: */
3709: numreg2 = DSP_REG_X0 + ((cur_inst>>18) & 1);
3710: } else {
3711: /* X: */
3712: numreg2 = DSP_REG_Y0 + ((cur_inst>>16) & 1);
3713: }
3714: dsp_core.registers[numreg2] = save_2;
3715: }
3716:
3717: static void dsp_pm_2(void)
3718: {
3719: Uint32 dummy;
3720: /*
3721: 0010 0000 0000 0000 nop
3722: 0010 0000 010m mrrr R update
3723: 0010 00ee eeed dddd S,D
3724: 001d dddd iiii iiii #xx,D
3725: */
3726: if ((cur_inst & 0xffff00) == 0x200000) {
3727: /* Execute parallel instruction */
3728: opcodes_alu[cur_inst & BITMASK(8)]();
3729: return;
3730: }
3731:
3732: if ((cur_inst & 0xffe000) == 0x204000) {
3733: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &dummy);
3734: /* Execute parallel instruction */
3735: opcodes_alu[cur_inst & BITMASK(8)]();
3736: return;
3737: }
3738:
3739: if ((cur_inst & 0xfc0000) == 0x200000) {
3740: dsp_pm_2_2();
3741: return;
3742: }
3743:
3744: dsp_pm_3();
3745: }
3746:
3747: static void dsp_pm_2_2(void)
3748: {
3749: /*
3750: 0010 00ee eeed dddd S,D
3751: */
3752: Uint32 srcreg, dstreg, save_reg;
3753:
3754: srcreg = (cur_inst >> 13) & BITMASK(5);
3755: dstreg = (cur_inst >> 8) & BITMASK(5);
3756:
3757: if ((srcreg == DSP_REG_A) || (srcreg == DSP_REG_B))
3758: /* Accu to register: limited 24 bits */
3759: dsp_pm_read_accu24(srcreg, &save_reg);
3760: else
3761: save_reg = dsp_core.registers[srcreg];
3762:
3763: /* Execute parallel instruction */
3764: opcodes_alu[cur_inst & BITMASK(8)]();
3765:
3766: /* Write reg */
3767: if (dstreg == DSP_REG_A) {
3768: dsp_core.registers[DSP_REG_A0] = 0x0;
3769: dsp_core.registers[DSP_REG_A1] = save_reg;
3770: dsp_core.registers[DSP_REG_A2] = save_reg & (1<<23) ? 0xff : 0x0;
3771: }
3772: else if (dstreg == DSP_REG_B) {
3773: dsp_core.registers[DSP_REG_B0] = 0x0;
3774: dsp_core.registers[DSP_REG_B1] = save_reg;
3775: dsp_core.registers[DSP_REG_B2] = save_reg & (1<<23) ? 0xff : 0x0;
3776: }
3777: else {
3778: dsp_core.registers[dstreg] = save_reg & BITMASK(registers_mask[dstreg]);
3779: }
3780: }
3781:
3782: static void dsp_pm_3(void)
3783: {
3784: Uint32 dstreg, srcvalue;
3785: /*
3786: 001d dddd iiii iiii #xx,R
3787: */
3788:
3789: /* Execute parallel instruction */
3790: opcodes_alu[cur_inst & BITMASK(8)]();
3791:
3792: /* Write reg */
3793: dstreg = (cur_inst >> 16) & BITMASK(5);
3794: srcvalue = (cur_inst >> 8) & BITMASK(8);
3795:
3796: switch(dstreg) {
3797: case DSP_REG_X0:
3798: case DSP_REG_X1:
3799: case DSP_REG_Y0:
3800: case DSP_REG_Y1:
3801: case DSP_REG_A:
3802: case DSP_REG_B:
3803: srcvalue <<= 16;
3804: break;
3805: }
3806:
3807: if (dstreg == DSP_REG_A) {
3808: dsp_core.registers[DSP_REG_A0] = 0x0;
3809: dsp_core.registers[DSP_REG_A1] = srcvalue;
3810: dsp_core.registers[DSP_REG_A2] = srcvalue & (1<<23) ? 0xff : 0x0;
3811: }
3812: else if (dstreg == DSP_REG_B) {
3813: dsp_core.registers[DSP_REG_B0] = 0x0;
3814: dsp_core.registers[DSP_REG_B1] = srcvalue;
3815: dsp_core.registers[DSP_REG_B2] = srcvalue & (1<<23) ? 0xff : 0x0;
3816: }
3817: else {
3818: dsp_core.registers[dstreg] = srcvalue & BITMASK(registers_mask[dstreg]);
3819: }
3820: }
3821:
3822: static void dsp_pm_4(void)
3823: {
3824: /*
3825: 0100 l0ll w0aa aaaa l:aa,D
3826: S,l:aa
3827: 0100 l0ll w1mm mrrr l:ea,D
3828: S,l:ea
3829: 01dd 0ddd w0aa aaaa x:aa,D
3830: S,x:aa
3831: 01dd 0ddd w1mm mrrr x:ea,D
3832: S,x:ea
3833: #xxxxxx,D
3834: 01dd 1ddd w0aa aaaa y:aa,D
3835: S,y:aa
3836: 01dd 1ddd w1mm mrrr y:ea,D
3837: S,y:ea
3838: #xxxxxx,D
3839: */
3840: if ((cur_inst & 0xf40000)==0x400000) {
3841: dsp_pm_4x();
3842: return;
3843: }
3844:
3845: dsp_pm_5();
3846: }
3847:
3848: static void dsp_pm_4x(void)
3849: {
3850: Uint32 value, numreg, l_addr, save_lx, save_ly;
3851: /*
3852: 0100 l0ll w0aa aaaa l:aa,D
3853: S,l:aa
3854: 0100 l0ll w1mm mrrr l:ea,D
3855: S,l:ea
3856: */
3857: value = (cur_inst>>8) & BITMASK(6);
3858: if (cur_inst & (1<<14)) {
3859: dsp_calc_ea(value, &l_addr);
3860: } else {
3861: l_addr = value;
3862: }
3863:
3864: numreg = (cur_inst>>16) & BITMASK(2);
3865: numreg |= (cur_inst>>17) & (1<<2);
3866:
3867: if (cur_inst & (1<<15)) {
3868: /* Write D */
3869: save_lx = read_memory(DSP_SPACE_X,l_addr);
3870: save_ly = read_memory(DSP_SPACE_Y,l_addr);
3871: }
3872: else {
3873: /* Read S */
3874: switch(numreg) {
3875: case 0:
3876: /* A10 */
3877: save_lx = dsp_core.registers[DSP_REG_A1];
3878: save_ly = dsp_core.registers[DSP_REG_A0];
3879: break;
3880: case 1:
3881: /* B10 */
3882: save_lx = dsp_core.registers[DSP_REG_B1];
3883: save_ly = dsp_core.registers[DSP_REG_B0];
3884: break;
3885: case 2:
3886: /* X */
3887: save_lx = dsp_core.registers[DSP_REG_X1];
3888: save_ly = dsp_core.registers[DSP_REG_X0];
3889: break;
3890: case 3:
3891: /* Y */
3892: save_lx = dsp_core.registers[DSP_REG_Y1];
3893: save_ly = dsp_core.registers[DSP_REG_Y0];
3894: break;
3895: case 4:
3896: /* A */
3897: if (dsp_pm_read_accu24(DSP_REG_A, &save_lx)) {
3898: /* Was limited, set lower part */
3899: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3900: } else {
3901: /* Not limited */
3902: save_ly = dsp_core.registers[DSP_REG_A0];
3903: }
3904: break;
3905: case 5:
3906: /* B */
3907: if (dsp_pm_read_accu24(DSP_REG_B, &save_lx)) {
3908: /* Was limited, set lower part */
3909: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3910: } else {
3911: /* Not limited */
3912: save_ly = dsp_core.registers[DSP_REG_B0];
3913: }
3914: break;
3915: case 6:
3916: /* AB */
3917: dsp_pm_read_accu24(DSP_REG_A, &save_lx);
3918: dsp_pm_read_accu24(DSP_REG_B, &save_ly);
3919: break;
3920: case 7:
3921: /* BA */
3922: dsp_pm_read_accu24(DSP_REG_B, &save_lx);
3923: dsp_pm_read_accu24(DSP_REG_A, &save_ly);
3924: break;
3925: }
3926: }
3927:
3928: /* Execute parallel instruction */
3929: opcodes_alu[cur_inst & BITMASK(8)]();
3930:
3931:
3932: if (cur_inst & (1<<15)) {
3933: /* Write D */
3934: switch(numreg) {
3935: case 0: /* A10 */
3936: dsp_core.registers[DSP_REG_A1] = save_lx;
3937: dsp_core.registers[DSP_REG_A0] = save_ly;
3938: break;
3939: case 1: /* B10 */
3940: dsp_core.registers[DSP_REG_B1] = save_lx;
3941: dsp_core.registers[DSP_REG_B0] = save_ly;
3942: break;
3943: case 2: /* X */
3944: dsp_core.registers[DSP_REG_X1] = save_lx;
3945: dsp_core.registers[DSP_REG_X0] = save_ly;
3946: break;
3947: case 3: /* Y */
3948: dsp_core.registers[DSP_REG_Y1] = save_lx;
3949: dsp_core.registers[DSP_REG_Y0] = save_ly;
3950: break;
3951: case 4: /* A */
3952: dsp_core.registers[DSP_REG_A0] = save_ly;
3953: dsp_core.registers[DSP_REG_A1] = save_lx;
3954: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3955: break;
3956: case 5: /* B */
3957: dsp_core.registers[DSP_REG_B0] = save_ly;
3958: dsp_core.registers[DSP_REG_B1] = save_lx;
3959: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3960: break;
3961: case 6: /* AB */
3962: dsp_core.registers[DSP_REG_A0] = 0;
3963: dsp_core.registers[DSP_REG_A1] = save_lx;
3964: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3965: dsp_core.registers[DSP_REG_B0] = 0;
3966: dsp_core.registers[DSP_REG_B1] = save_ly;
3967: dsp_core.registers[DSP_REG_B2] = save_ly & (1<<23) ? 0xff : 0;
3968: break;
3969: case 7: /* BA */
3970: dsp_core.registers[DSP_REG_B0] = 0;
3971: dsp_core.registers[DSP_REG_B1] = save_lx;
3972: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3973: dsp_core.registers[DSP_REG_A0] = 0;
3974: dsp_core.registers[DSP_REG_A1] = save_ly;
3975: dsp_core.registers[DSP_REG_A2] = save_ly & (1<<23) ? 0xff : 0;
3976: break;
3977: }
3978: }
3979: else {
3980: /* Read S */
3981: write_memory(DSP_SPACE_X, l_addr, save_lx);
3982: write_memory(DSP_SPACE_Y, l_addr, save_ly);
3983: }
3984: }
3985:
3986: static void dsp_pm_5(void)
3987: {
3988: Uint32 memspace, numreg, value, xy_addr, retour;
3989: /*
3990: 01dd 0ddd w0aa aaaa x:aa,D
3991: S,x:aa
3992: 01dd 0ddd w1mm mrrr x:ea,D
3993: S,x:ea
3994: #xxxxxx,D
3995: 01dd 1ddd w0aa aaaa y:aa,D
3996: S,y:aa
3997: 01dd 1ddd w1mm mrrr y:ea,D
3998: S,y:ea
3999: #xxxxxx,D
4000: */
4001:
4002: value = (cur_inst>>8) & BITMASK(6);
4003:
4004: if (cur_inst & (1<<14)) {
4005: retour = dsp_calc_ea(value, &xy_addr);
4006: } else {
4007: xy_addr = value;
4008: retour = 0;
4009: }
4010:
4011: memspace = (cur_inst>>19) & 1;
4012: numreg = (cur_inst>>16) & BITMASK(3);
4013: numreg |= (cur_inst>>17) & (BITMASK(2)<<3);
4014:
4015: if (cur_inst & (1<<15)) {
4016: /* Write D */
4017: if (retour)
4018: value = xy_addr;
4019: else
4020: value = read_memory(memspace, xy_addr);
4021: }
4022: else {
4023: /* Read S */
4024: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B))
4025: dsp_pm_read_accu24(numreg, &value);
4026: else
4027: value = dsp_core.registers[numreg];
4028: }
4029:
4030:
4031: /* Execute parallel instruction */
4032: opcodes_alu[cur_inst & BITMASK(8)]();
4033:
4034: if (cur_inst & (1<<15)) {
4035: /* Write D */
4036: if (numreg == DSP_REG_A) {
4037: dsp_core.registers[DSP_REG_A0] = 0x0;
4038: dsp_core.registers[DSP_REG_A1] = value;
4039: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
4040: }
4041: else if (numreg == DSP_REG_B) {
4042: dsp_core.registers[DSP_REG_B0] = 0x0;
4043: dsp_core.registers[DSP_REG_B1] = value;
4044: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
4045: }
4046: else {
4047: dsp_core.registers[numreg] = value & BITMASK(registers_mask[numreg]);
4048: }
4049: }
4050: else {
4051: /* Read S */
4052: write_memory(memspace, xy_addr, value);
4053: }
4054: }
4055:
4056: static void dsp_pm_8(void)
4057: {
4058: Uint32 ea1, ea2;
4059: Uint32 numreg1, numreg2;
4060: Uint32 save_reg1, save_reg2, x_addr, y_addr;
4061: /*
4062: 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
4063: x:ea,D1 S2,y:ea
4064: S1,x:ea y:ea,D2
4065: S1,x:ea S2,y:ea
4066: */
4067: numreg1 = numreg2 = DSP_REG_NULL;
4068:
4069: ea1 = (cur_inst>>8) & BITMASK(5);
4070: if ((ea1>>3) == 0) {
4071: ea1 |= (1<<5);
4072: }
4073: ea2 = (cur_inst>>13) & BITMASK(2);
4074: ea2 |= (cur_inst>>17) & (BITMASK(2)<<3);
4075: if ((ea1 & (1<<2))==0) {
4076: ea2 |= 1<<2;
4077: }
4078: if ((ea2>>3) == 0) {
4079: ea2 |= (1<<5);
4080: }
4081:
4082: dsp_calc_ea(ea1, &x_addr);
4083: dsp_calc_ea(ea2, &y_addr);
4084:
4085: switch((cur_inst>>18) & BITMASK(2)) {
4086: case 0: numreg1=DSP_REG_X0; break;
4087: case 1: numreg1=DSP_REG_X1; break;
4088: case 2: numreg1=DSP_REG_A; break;
4089: case 3: numreg1=DSP_REG_B; break;
4090: }
4091: switch((cur_inst>>16) & BITMASK(2)) {
4092: case 0: numreg2=DSP_REG_Y0; break;
4093: case 1: numreg2=DSP_REG_Y1; break;
4094: case 2: numreg2=DSP_REG_A; break;
4095: case 3: numreg2=DSP_REG_B; break;
4096: }
4097:
4098: if (cur_inst & (1<<15)) {
4099: /* Write D1 */
4100: save_reg1 = read_memory(DSP_SPACE_X, x_addr);
4101: } else {
4102: /* Read S1 */
4103: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
4104: dsp_pm_read_accu24(numreg1, &save_reg1);
4105: else
4106: save_reg1 = dsp_core.registers[numreg1];
4107: }
4108:
4109: if (cur_inst & (1<<22)) {
4110: /* Write D2 */
4111: save_reg2 = read_memory(DSP_SPACE_Y, y_addr);
4112: } else {
4113: /* Read S2 */
4114: if ((numreg2==DSP_REG_A) || (numreg2==DSP_REG_B))
4115: dsp_pm_read_accu24(numreg2, &save_reg2);
4116: else
4117: save_reg2 = dsp_core.registers[numreg2];
4118: }
4119:
4120:
4121: /* Execute parallel instruction */
4122: opcodes_alu[cur_inst & BITMASK(8)]();
4123:
4124: /* Write first parallel move */
4125: if (cur_inst & (1<<15)) {
4126: /* Write D1 */
4127: if (numreg1 == DSP_REG_A) {
4128: dsp_core.registers[DSP_REG_A0] = 0x0;
4129: dsp_core.registers[DSP_REG_A1] = save_reg1;
4130: dsp_core.registers[DSP_REG_A2] = save_reg1 & (1<<23) ? 0xff : 0x0;
4131: }
4132: else if (numreg1 == DSP_REG_B) {
4133: dsp_core.registers[DSP_REG_B0] = 0x0;
4134: dsp_core.registers[DSP_REG_B1] = save_reg1;
4135: dsp_core.registers[DSP_REG_B2] = save_reg1 & (1<<23) ? 0xff : 0x0;
4136: }
4137: else {
4138: dsp_core.registers[numreg1] = save_reg1;
4139: }
4140: } else {
4141: /* Read S1 */
4142: write_memory(DSP_SPACE_X, x_addr, save_reg1);
4143: }
4144:
4145: /* Write second parallel move */
4146: if (cur_inst & (1<<22)) {
4147: /* Write D2 */
4148: if (numreg2 == DSP_REG_A) {
4149: dsp_core.registers[DSP_REG_A0] = 0x0;
4150: dsp_core.registers[DSP_REG_A1] = save_reg2;
4151: dsp_core.registers[DSP_REG_A2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4152: }
4153: else if (numreg2 == DSP_REG_B) {
4154: dsp_core.registers[DSP_REG_B0] = 0x0;
4155: dsp_core.registers[DSP_REG_B1] = save_reg2;
4156: dsp_core.registers[DSP_REG_B2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4157: }
4158: else {
4159: dsp_core.registers[numreg2] = save_reg2;
4160: }
4161: } else {
4162: /* Read S2 */
4163: write_memory(DSP_SPACE_Y, y_addr, save_reg2);
4164: }
4165: }
4166:
4167: /**********************************
4168: * 56bit arithmetic
4169: **********************************/
4170:
4171: /* source,dest[0] is 55:48 */
4172: /* source,dest[1] is 47:24 */
4173: /* source,dest[2] is 23:00 */
4174:
4175: static Uint16 dsp_abs56(Uint32 *dest)
4176: {
4177: Uint32 zerodest[3];
4178: Uint16 newsr;
4179:
4180: /* D=|D| */
4181:
4182: if (dest[0] & (1<<7)) {
4183: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4184:
4185: newsr = dsp_sub56(dest, zerodest);
4186:
4187: dest[0] = zerodest[0];
4188: dest[1] = zerodest[1];
4189: dest[2] = zerodest[2];
4190: } else {
4191: newsr = 0;
4192: }
4193:
4194: return newsr;
4195: }
4196:
4197: static Uint16 dsp_asl56(Uint32 *dest)
4198: {
4199: Uint16 overflow, carry;
4200:
4201: /* Shift left dest 1 bit: D<<=1 */
4202:
4203: carry = (dest[0]>>7) & 1;
4204:
4205: dest[0] <<= 1;
4206: dest[0] |= (dest[1]>>23) & 1;
4207: dest[0] &= BITMASK(8);
4208:
4209: dest[1] <<= 1;
4210: dest[1] |= (dest[2]>>23) & 1;
4211: dest[1] &= BITMASK(24);
4212:
4213: dest[2] <<= 1;
4214: dest[2] &= BITMASK(24);
4215:
4216: overflow = (carry != ((dest[0]>>7) & 1));
4217:
4218: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4219: }
4220:
4221: static Uint16 dsp_asr56(Uint32 *dest)
4222: {
4223: Uint16 carry;
4224:
4225: /* Shift right dest 1 bit: D>>=1 */
4226:
4227: carry = dest[2] & 1;
4228:
4229: dest[2] >>= 1;
4230: dest[2] |= (dest[1] & 1)<<23;
4231:
4232: dest[1] >>= 1;
4233: dest[1] |= (dest[0] & 1)<<23;
4234:
4235: dest[0] >>= 1;
4236: dest[0] |= (dest[0] & (1<<6))<<1;
4237:
4238: return (carry<<DSP_SR_C);
4239: }
4240:
4241: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest)
4242: {
4243: Uint16 overflow, carry, flg_s, flg_d, flg_r;
4244:
4245: flg_s = (source[0]>>7) & 1;
4246: flg_d = (dest[0]>>7) & 1;
4247:
4248: /* Add source to dest: D = D+S */
4249: dest[2] += source[2];
4250: dest[1] += source[1]+((dest[2]>>24) & 1);
4251: dest[0] += source[0]+((dest[1]>>24) & 1);
4252:
4253: carry = (dest[0]>>8) & 1;
4254:
4255: dest[2] &= BITMASK(24);
4256: dest[1] &= BITMASK(24);
4257: dest[0] &= BITMASK(8);
4258:
4259: flg_r = (dest[0]>>7) & 1;
4260:
4261: /*set overflow*/
4262: overflow = (flg_s ^ flg_r) & (flg_d ^ flg_r);
4263:
4264: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4265: }
4266:
4267: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest)
4268: {
4269: Uint16 overflow, carry, flg_s, flg_d, flg_r, dest_save;
4270:
4271: dest_save = dest[0];
4272:
4273: /* Subtract source from dest: D = D-S */
4274: dest[2] -= source[2];
4275: dest[1] -= source[1]+((dest[2]>>24) & 1);
4276: dest[0] -= source[0]+((dest[1]>>24) & 1);
4277:
4278: carry = (dest[0]>>8) & 1;
4279:
4280: dest[2] &= BITMASK(24);
4281: dest[1] &= BITMASK(24);
4282: dest[0] &= BITMASK(8);
4283:
4284: flg_s = (source[0]>>7) & 1;
4285: flg_d = (dest_save>>7) & 1;
4286: flg_r = (dest[0]>>7) & 1;
4287:
4288: /* set overflow */
4289: overflow = (flg_s ^ flg_d) & (flg_r ^ flg_d);
4290:
4291: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4292: }
4293:
4294: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe)
4295: {
4296: Uint32 part[4], zerodest[3], value;
4297:
4298: /* Multiply: D = S1*S2 */
4299: if (source1 & (1<<23)) {
4300: signe ^= 1;
4301: source1 = (1<<24) - source1;
4302: }
4303: if (source2 & (1<<23)) {
4304: signe ^= 1;
4305: source2 = (1<<24) - source2;
4306: }
4307:
4308: /* bits 0-11 * bits 0-11 */
4309: part[0]=(source1 & BITMASK(12))*(source2 & BITMASK(12));
4310: /* bits 12-23 * bits 0-11 */
4311: part[1]=((source1>>12) & BITMASK(12))*(source2 & BITMASK(12));
4312: /* bits 0-11 * bits 12-23 */
4313: part[2]=(source1 & BITMASK(12))*((source2>>12) & BITMASK(12));
4314: /* bits 12-23 * bits 12-23 */
4315: part[3]=((source1>>12) & BITMASK(12))*((source2>>12) & BITMASK(12));
4316:
4317: /* Calc dest 2 */
4318: dest[2] = part[0];
4319: dest[2] += (part[1] & BITMASK(12)) << 12;
4320: dest[2] += (part[2] & BITMASK(12)) << 12;
4321:
4322: /* Calc dest 1 */
4323: dest[1] = (part[1]>>12) & BITMASK(12);
4324: dest[1] += (part[2]>>12) & BITMASK(12);
4325: dest[1] += part[3];
4326:
4327: /* Calc dest 0 */
4328: dest[0] = 0;
4329:
4330: /* Add carries */
4331: value = (dest[2]>>24) & BITMASK(8);
4332: if (value) {
4333: dest[1] += value;
4334: dest[2] &= BITMASK(24);
4335: }
4336: value = (dest[1]>>24) & BITMASK(8);
4337: if (value) {
4338: dest[0] += value;
4339: dest[1] &= BITMASK(24);
4340: }
4341:
4342: /* Get rid of extra sign bit */
4343: dsp_asl56(dest);
4344:
4345: if (signe) {
4346: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4347:
4348: dsp_sub56(dest, zerodest);
4349:
4350: dest[0] = zerodest[0];
4351: dest[1] = zerodest[1];
4352: dest[2] = zerodest[2];
4353: }
4354: }
4355:
4356: static void dsp_rnd56(Uint32 *dest)
4357: {
4358: Uint32 rnd_const[3];
4359:
4360: rnd_const[0] = 0;
4361:
4362: /* Scaling mode S0 */
4363: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S0)) {
4364: rnd_const[1] = 1;
4365: rnd_const[2] = 0;
4366: dsp_add56(rnd_const, dest);
4367:
4368: if ((dest[2]==0) && ((dest[1] & 1) == 0)) {
4369: dest[1] &= (0xffffff - 0x3);
4370: }
4371: dest[1] &= 0xfffffe;
4372: dest[2]=0;
4373: }
4374: /* Scaling mode S1 */
4375: else if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S1)) {
4376: rnd_const[1] = 0;
4377: rnd_const[2] = (1<<22);
4378: dsp_add56(rnd_const, dest);
4379:
4380: if ((dest[2] & 0x7fffff) == 0){
4381: dest[2] = 0;
4382: }
4383: dest[2] &= 0x800000;
4384: }
4385: /* No Scaling */
4386: else {
4387: rnd_const[1] = 0;
4388: rnd_const[2] = (1<<23);
4389: dsp_add56(rnd_const, dest);
4390:
4391: if (dest[2] == 0) {
4392: dest[1] &= 0xfffffe;
4393: }
4394: dest[2]=0;
4395: }
4396: }
4397:
4398: /**********************************
4399: * Parallel moves instructions
4400: **********************************/
4401:
4402: static void dsp_abs_a(void)
4403: {
4404: Uint32 dest[3], overflowed;
4405:
4406: dest[0] = dsp_core.registers[DSP_REG_A2];
4407: dest[1] = dsp_core.registers[DSP_REG_A1];
4408: dest[2] = dsp_core.registers[DSP_REG_A0];
4409:
4410: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4411:
4412: dsp_abs56(dest);
4413:
4414: dsp_core.registers[DSP_REG_A2] = dest[0];
4415: dsp_core.registers[DSP_REG_A1] = dest[1];
4416: dsp_core.registers[DSP_REG_A0] = dest[2];
4417:
4418: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4419: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4420:
4421: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4422: }
4423:
4424: static void dsp_abs_b(void)
4425: {
4426: Uint32 dest[3], overflowed;
4427:
4428: dest[0] = dsp_core.registers[DSP_REG_B2];
4429: dest[1] = dsp_core.registers[DSP_REG_B1];
4430: dest[2] = dsp_core.registers[DSP_REG_B0];
4431:
4432: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4433:
4434: dsp_abs56(dest);
4435:
4436: dsp_core.registers[DSP_REG_B2] = dest[0];
4437: dsp_core.registers[DSP_REG_B1] = dest[1];
4438: dsp_core.registers[DSP_REG_B0] = dest[2];
4439:
4440: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4441: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4442:
4443: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4444: }
4445:
4446: static void dsp_adc_x_a(void)
4447: {
4448: Uint32 source[3], dest[3], curcarry;
4449: Uint16 newsr;
4450:
4451: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4452:
4453: dest[0] = dsp_core.registers[DSP_REG_A2];
4454: dest[1] = dsp_core.registers[DSP_REG_A1];
4455: dest[2] = dsp_core.registers[DSP_REG_A0];
4456:
4457: source[2] = dsp_core.registers[DSP_REG_X0];
4458: source[1] = dsp_core.registers[DSP_REG_X1];
4459: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4460:
4461: newsr = dsp_add56(source, dest);
4462:
4463: if (curcarry) {
4464: source[0]=0; source[1]=0; source[2]=1;
4465: newsr |= dsp_add56(source, dest);
4466: }
4467:
4468: dsp_core.registers[DSP_REG_A2] = dest[0];
4469: dsp_core.registers[DSP_REG_A1] = dest[1];
4470: dsp_core.registers[DSP_REG_A0] = dest[2];
4471:
4472: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4473:
4474: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4475: dsp_core.registers[DSP_REG_SR] |= newsr;
4476: }
4477:
4478: static void dsp_adc_x_b(void)
4479: {
4480: Uint32 source[3], dest[3], curcarry;
4481: Uint16 newsr;
4482:
4483: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4484:
4485: dest[0] = dsp_core.registers[DSP_REG_B2];
4486: dest[1] = dsp_core.registers[DSP_REG_B1];
4487: dest[2] = dsp_core.registers[DSP_REG_B0];
4488:
4489: source[2] = dsp_core.registers[DSP_REG_X0];
4490: source[1] = dsp_core.registers[DSP_REG_X1];
4491: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4492:
4493: newsr = dsp_add56(source, dest);
4494:
4495: if (curcarry) {
4496: source[0]=0; source[1]=0; source[2]=1;
4497: newsr |= dsp_add56(source, dest);
4498: }
4499:
4500: dsp_core.registers[DSP_REG_B2] = dest[0];
4501: dsp_core.registers[DSP_REG_B1] = dest[1];
4502: dsp_core.registers[DSP_REG_B0] = dest[2];
4503:
4504: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4505:
4506: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4507: dsp_core.registers[DSP_REG_SR] |= newsr;
4508: }
4509:
4510: static void dsp_adc_y_a(void)
4511: {
4512: Uint32 source[3], dest[3], curcarry;
4513: Uint16 newsr;
4514:
4515: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4516:
4517: dest[0] = dsp_core.registers[DSP_REG_A2];
4518: dest[1] = dsp_core.registers[DSP_REG_A1];
4519: dest[2] = dsp_core.registers[DSP_REG_A0];
4520:
4521: source[2] = dsp_core.registers[DSP_REG_Y0];
4522: source[1] = dsp_core.registers[DSP_REG_Y1];
4523: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4524:
4525: newsr = dsp_add56(source, dest);
4526:
4527: if (curcarry) {
4528: source[0]=0; source[1]=0; source[2]=1;
4529: newsr |= dsp_add56(source, dest);
4530: }
4531:
4532: dsp_core.registers[DSP_REG_A2] = dest[0];
4533: dsp_core.registers[DSP_REG_A1] = dest[1];
4534: dsp_core.registers[DSP_REG_A0] = dest[2];
4535:
4536: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4537:
4538: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4539: dsp_core.registers[DSP_REG_SR] |= newsr;
4540: }
4541:
4542: static void dsp_adc_y_b(void)
4543: {
4544: Uint32 source[3], dest[3], curcarry;
4545: Uint16 newsr;
4546:
4547: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4548:
4549: dest[0] = dsp_core.registers[DSP_REG_B2];
4550: dest[1] = dsp_core.registers[DSP_REG_B1];
4551: dest[2] = dsp_core.registers[DSP_REG_B0];
4552:
4553: source[2] = dsp_core.registers[DSP_REG_Y0];
4554: source[1] = dsp_core.registers[DSP_REG_Y1];
4555: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4556:
4557: newsr = dsp_add56(source, dest);
4558:
4559: if (curcarry) {
4560: source[0]=0; source[1]=0; source[2]=1;
4561: newsr |= dsp_add56(source, dest);
4562: }
4563:
4564: dsp_core.registers[DSP_REG_B2] = dest[0];
4565: dsp_core.registers[DSP_REG_B1] = dest[1];
4566: dsp_core.registers[DSP_REG_B0] = dest[2];
4567:
4568: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4569:
4570: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4571: dsp_core.registers[DSP_REG_SR] |= newsr;
4572: }
4573:
4574: static void dsp_add_b_a(void)
4575: {
4576: Uint32 source[3], dest[3];
4577: Uint16 newsr;
4578:
4579: dest[0] = dsp_core.registers[DSP_REG_A2];
4580: dest[1] = dsp_core.registers[DSP_REG_A1];
4581: dest[2] = dsp_core.registers[DSP_REG_A0];
4582:
4583: source[0] = dsp_core.registers[DSP_REG_B2];
4584: source[1] = dsp_core.registers[DSP_REG_B1];
4585: source[2] = dsp_core.registers[DSP_REG_B0];
4586:
4587: newsr = dsp_add56(source, dest);
4588:
4589: dsp_core.registers[DSP_REG_A2] = dest[0];
4590: dsp_core.registers[DSP_REG_A1] = dest[1];
4591: dsp_core.registers[DSP_REG_A0] = dest[2];
4592:
4593: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4594:
4595: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4596: dsp_core.registers[DSP_REG_SR] |= newsr;
4597: }
4598:
4599: static void dsp_add_a_b(void)
4600: {
4601: Uint32 source[3], dest[3];
4602: Uint16 newsr;
4603:
4604: dest[0] = dsp_core.registers[DSP_REG_B2];
4605: dest[1] = dsp_core.registers[DSP_REG_B1];
4606: dest[2] = dsp_core.registers[DSP_REG_B0];
4607:
4608: source[0] = dsp_core.registers[DSP_REG_A2];
4609: source[1] = dsp_core.registers[DSP_REG_A1];
4610: source[2] = dsp_core.registers[DSP_REG_A0];
4611:
4612: newsr = dsp_add56(source, dest);
4613:
4614: dsp_core.registers[DSP_REG_B2] = dest[0];
4615: dsp_core.registers[DSP_REG_B1] = dest[1];
4616: dsp_core.registers[DSP_REG_B0] = dest[2];
4617:
4618: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4619:
4620: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4621: dsp_core.registers[DSP_REG_SR] |= newsr;
4622: }
4623:
4624: static void dsp_add_x_a(void)
4625: {
4626: Uint32 source[3], dest[3];
4627: Uint16 newsr;
4628:
4629: dest[0] = dsp_core.registers[DSP_REG_A2];
4630: dest[1] = dsp_core.registers[DSP_REG_A1];
4631: dest[2] = dsp_core.registers[DSP_REG_A0];
4632:
4633: source[1] = dsp_core.registers[DSP_REG_X1];
4634: source[2] = dsp_core.registers[DSP_REG_X0];
4635: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4636:
4637: newsr = dsp_add56(source, dest);
4638:
4639: dsp_core.registers[DSP_REG_A2] = dest[0];
4640: dsp_core.registers[DSP_REG_A1] = dest[1];
4641: dsp_core.registers[DSP_REG_A0] = dest[2];
4642:
4643: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4644:
4645: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4646: dsp_core.registers[DSP_REG_SR] |= newsr;
4647: }
4648:
4649: static void dsp_add_x_b(void)
4650: {
4651: Uint32 source[3], dest[3];
4652: Uint16 newsr;
4653:
4654: dest[0] = dsp_core.registers[DSP_REG_B2];
4655: dest[1] = dsp_core.registers[DSP_REG_B1];
4656: dest[2] = dsp_core.registers[DSP_REG_B0];
4657:
4658: source[1] = dsp_core.registers[DSP_REG_X1];
4659: source[2] = dsp_core.registers[DSP_REG_X0];
4660: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4661:
4662: newsr = dsp_add56(source, dest);
4663:
4664: dsp_core.registers[DSP_REG_B2] = dest[0];
4665: dsp_core.registers[DSP_REG_B1] = dest[1];
4666: dsp_core.registers[DSP_REG_B0] = dest[2];
4667:
4668: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4669:
4670: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4671: dsp_core.registers[DSP_REG_SR] |= newsr;
4672: }
4673:
4674: static void dsp_add_y_a(void)
4675: {
4676: Uint32 source[3], dest[3];
4677: Uint16 newsr;
4678:
4679: dest[0] = dsp_core.registers[DSP_REG_A2];
4680: dest[1] = dsp_core.registers[DSP_REG_A1];
4681: dest[2] = dsp_core.registers[DSP_REG_A0];
4682:
4683: source[1] = dsp_core.registers[DSP_REG_Y1];
4684: source[2] = dsp_core.registers[DSP_REG_Y0];
4685: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4686:
4687: newsr = dsp_add56(source, dest);
4688:
4689: dsp_core.registers[DSP_REG_A2] = dest[0];
4690: dsp_core.registers[DSP_REG_A1] = dest[1];
4691: dsp_core.registers[DSP_REG_A0] = dest[2];
4692:
4693: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4694:
4695: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4696: dsp_core.registers[DSP_REG_SR] |= newsr;
4697: }
4698:
4699: static void dsp_add_y_b(void)
4700: {
4701: Uint32 source[3], dest[3];
4702: Uint16 newsr;
4703:
4704: dest[0] = dsp_core.registers[DSP_REG_B2];
4705: dest[1] = dsp_core.registers[DSP_REG_B1];
4706: dest[2] = dsp_core.registers[DSP_REG_B0];
4707:
4708: source[1] = dsp_core.registers[DSP_REG_Y1];
4709: source[2] = dsp_core.registers[DSP_REG_Y0];
4710: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4711:
4712: newsr = dsp_add56(source, dest);
4713:
4714: dsp_core.registers[DSP_REG_B2] = dest[0];
4715: dsp_core.registers[DSP_REG_B1] = dest[1];
4716: dsp_core.registers[DSP_REG_B0] = dest[2];
4717:
4718: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4719:
4720: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4721: dsp_core.registers[DSP_REG_SR] |= newsr;
4722: }
4723:
4724: static void dsp_add_x0_a(void)
4725: {
4726: Uint32 source[3], dest[3];
4727: Uint16 newsr;
4728:
4729: dest[0] = dsp_core.registers[DSP_REG_A2];
4730: dest[1] = dsp_core.registers[DSP_REG_A1];
4731: dest[2] = dsp_core.registers[DSP_REG_A0];
4732:
4733: source[2] = 0;
4734: source[1] = dsp_core.registers[DSP_REG_X0];
4735: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4736:
4737: newsr = dsp_add56(source, dest);
4738:
4739: dsp_core.registers[DSP_REG_A2] = dest[0];
4740: dsp_core.registers[DSP_REG_A1] = dest[1];
4741: dsp_core.registers[DSP_REG_A0] = dest[2];
4742:
4743: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4744:
4745: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4746: dsp_core.registers[DSP_REG_SR] |= newsr;
4747: }
4748:
4749: static void dsp_add_x0_b(void)
4750: {
4751: Uint32 source[3], dest[3];
4752: Uint16 newsr;
4753:
4754: dest[0] = dsp_core.registers[DSP_REG_B2];
4755: dest[1] = dsp_core.registers[DSP_REG_B1];
4756: dest[2] = dsp_core.registers[DSP_REG_B0];
4757:
4758: source[2] = 0;
4759: source[1] = dsp_core.registers[DSP_REG_X0];
4760: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4761:
4762: newsr = dsp_add56(source, dest);
4763:
4764: dsp_core.registers[DSP_REG_B2] = dest[0];
4765: dsp_core.registers[DSP_REG_B1] = dest[1];
4766: dsp_core.registers[DSP_REG_B0] = dest[2];
4767:
4768: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4769:
4770: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4771: dsp_core.registers[DSP_REG_SR] |= newsr;
4772: }
4773:
4774: static void dsp_add_y0_a(void)
4775: {
4776: Uint32 source[3], dest[3];
4777: Uint16 newsr;
4778:
4779: dest[0] = dsp_core.registers[DSP_REG_A2];
4780: dest[1] = dsp_core.registers[DSP_REG_A1];
4781: dest[2] = dsp_core.registers[DSP_REG_A0];
4782:
4783: source[2] = 0;
4784: source[1] = dsp_core.registers[DSP_REG_Y0];
4785: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4786:
4787: newsr = dsp_add56(source, dest);
4788:
4789: dsp_core.registers[DSP_REG_A2] = dest[0];
4790: dsp_core.registers[DSP_REG_A1] = dest[1];
4791: dsp_core.registers[DSP_REG_A0] = dest[2];
4792:
4793: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4794:
4795: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4796: dsp_core.registers[DSP_REG_SR] |= newsr;
4797: }
4798:
4799: static void dsp_add_y0_b(void)
4800: {
4801: Uint32 source[3], dest[3];
4802: Uint16 newsr;
4803:
4804: dest[0] = dsp_core.registers[DSP_REG_B2];
4805: dest[1] = dsp_core.registers[DSP_REG_B1];
4806: dest[2] = dsp_core.registers[DSP_REG_B0];
4807:
4808: source[2] = 0;
4809: source[1] = dsp_core.registers[DSP_REG_Y0];
4810: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4811:
4812: newsr = dsp_add56(source, dest);
4813:
4814: dsp_core.registers[DSP_REG_B2] = dest[0];
4815: dsp_core.registers[DSP_REG_B1] = dest[1];
4816: dsp_core.registers[DSP_REG_B0] = dest[2];
4817:
4818: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4819:
4820: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4821: dsp_core.registers[DSP_REG_SR] |= newsr;
4822: }
4823:
4824: static void dsp_add_x1_a(void)
4825: {
4826: Uint32 source[3], dest[3];
4827: Uint16 newsr;
4828:
4829: dest[0] = dsp_core.registers[DSP_REG_A2];
4830: dest[1] = dsp_core.registers[DSP_REG_A1];
4831: dest[2] = dsp_core.registers[DSP_REG_A0];
4832:
4833: source[2] = 0;
4834: source[1] = dsp_core.registers[DSP_REG_X1];
4835: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4836:
4837: newsr = dsp_add56(source, dest);
4838:
4839: dsp_core.registers[DSP_REG_A2] = dest[0];
4840: dsp_core.registers[DSP_REG_A1] = dest[1];
4841: dsp_core.registers[DSP_REG_A0] = dest[2];
4842:
4843: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4844:
4845: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4846: dsp_core.registers[DSP_REG_SR] |= newsr;
4847: }
4848:
4849: static void dsp_add_x1_b(void)
4850: {
4851: Uint32 source[3], dest[3];
4852: Uint16 newsr;
4853:
4854: dest[0] = dsp_core.registers[DSP_REG_B2];
4855: dest[1] = dsp_core.registers[DSP_REG_B1];
4856: dest[2] = dsp_core.registers[DSP_REG_B0];
4857:
4858: source[2] = 0;
4859: source[1] = dsp_core.registers[DSP_REG_X1];
4860: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4861:
4862: newsr = dsp_add56(source, dest);
4863:
4864: dsp_core.registers[DSP_REG_B2] = dest[0];
4865: dsp_core.registers[DSP_REG_B1] = dest[1];
4866: dsp_core.registers[DSP_REG_B0] = dest[2];
4867:
4868: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4869:
4870: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4871: dsp_core.registers[DSP_REG_SR] |= newsr;
4872: }
4873:
4874: static void dsp_add_y1_a(void)
4875: {
4876: Uint32 source[3], dest[3];
4877: Uint16 newsr;
4878:
4879: dest[0] = dsp_core.registers[DSP_REG_A2];
4880: dest[1] = dsp_core.registers[DSP_REG_A1];
4881: dest[2] = dsp_core.registers[DSP_REG_A0];
4882:
4883: source[2] = 0;
4884: source[1] = dsp_core.registers[DSP_REG_Y1];
4885: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4886:
4887: newsr = dsp_add56(source, dest);
4888:
4889: dsp_core.registers[DSP_REG_A2] = dest[0];
4890: dsp_core.registers[DSP_REG_A1] = dest[1];
4891: dsp_core.registers[DSP_REG_A0] = dest[2];
4892:
4893: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4894:
4895: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4896: dsp_core.registers[DSP_REG_SR] |= newsr;
4897: }
4898:
4899: static void dsp_add_y1_b(void)
4900: {
4901: Uint32 source[3], dest[3];
4902: Uint16 newsr;
4903:
4904: dest[0] = dsp_core.registers[DSP_REG_B2];
4905: dest[1] = dsp_core.registers[DSP_REG_B1];
4906: dest[2] = dsp_core.registers[DSP_REG_B0];
4907:
4908: source[2] = 0;
4909: source[1] = dsp_core.registers[DSP_REG_Y1];
4910: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
4911:
4912: newsr = dsp_add56(source, dest);
4913:
4914: dsp_core.registers[DSP_REG_B2] = dest[0];
4915: dsp_core.registers[DSP_REG_B1] = dest[1];
4916: dsp_core.registers[DSP_REG_B0] = dest[2];
4917:
4918: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4919:
4920: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4921: dsp_core.registers[DSP_REG_SR] |= newsr;
4922: }
4923:
4924: static void dsp_addl_b_a(void)
4925: {
4926: Uint32 source[3], dest[3];
4927: Uint16 newsr;
4928:
4929: dest[0] = dsp_core.registers[DSP_REG_A2];
4930: dest[1] = dsp_core.registers[DSP_REG_A1];
4931: dest[2] = dsp_core.registers[DSP_REG_A0];
4932: newsr = dsp_asl56(dest);
4933:
4934: source[0] = dsp_core.registers[DSP_REG_B2];
4935: source[1] = dsp_core.registers[DSP_REG_B1];
4936: source[2] = dsp_core.registers[DSP_REG_B0];
4937: newsr |= dsp_add56(source, dest);
4938:
4939: dsp_core.registers[DSP_REG_A2] = dest[0];
4940: dsp_core.registers[DSP_REG_A1] = dest[1];
4941: dsp_core.registers[DSP_REG_A0] = dest[2];
4942:
4943: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4944:
4945: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4946: dsp_core.registers[DSP_REG_SR] |= newsr;
4947: }
4948:
4949: static void dsp_addl_a_b(void)
4950: {
4951: Uint32 source[3], dest[3];
4952: Uint16 newsr;
4953:
4954: dest[0] = dsp_core.registers[DSP_REG_B2];
4955: dest[1] = dsp_core.registers[DSP_REG_B1];
4956: dest[2] = dsp_core.registers[DSP_REG_B0];
4957: newsr = dsp_asl56(dest);
4958:
4959: source[0] = dsp_core.registers[DSP_REG_A2];
4960: source[1] = dsp_core.registers[DSP_REG_A1];
4961: source[2] = dsp_core.registers[DSP_REG_A0];
4962: newsr |= dsp_add56(source, dest);
4963:
4964: dsp_core.registers[DSP_REG_B2] = dest[0];
4965: dsp_core.registers[DSP_REG_B1] = dest[1];
4966: dsp_core.registers[DSP_REG_B0] = dest[2];
4967:
4968: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4969:
4970: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4971: dsp_core.registers[DSP_REG_SR] |= newsr;
4972: }
4973:
4974: static void dsp_addr_b_a(void)
4975: {
4976: Uint32 source[3], dest[3];
4977: Uint16 newsr;
4978:
4979: dest[0] = dsp_core.registers[DSP_REG_A2];
4980: dest[1] = dsp_core.registers[DSP_REG_A1];
4981: dest[2] = dsp_core.registers[DSP_REG_A0];
4982: newsr = dsp_asr56(dest);
4983:
4984: source[0] = dsp_core.registers[DSP_REG_B2];
4985: source[1] = dsp_core.registers[DSP_REG_B1];
4986: source[2] = dsp_core.registers[DSP_REG_B0];
4987: newsr |= dsp_add56(source, dest);
4988:
4989: dsp_core.registers[DSP_REG_A2] = dest[0];
4990: dsp_core.registers[DSP_REG_A1] = dest[1];
4991: dsp_core.registers[DSP_REG_A0] = dest[2];
4992:
4993: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4994:
4995: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4996: dsp_core.registers[DSP_REG_SR] |= newsr;
4997: }
4998:
4999: static void dsp_addr_a_b(void)
5000: {
5001: Uint32 source[3], dest[3];
5002: Uint16 newsr;
5003:
5004: dest[0] = dsp_core.registers[DSP_REG_B2];
5005: dest[1] = dsp_core.registers[DSP_REG_B1];
5006: dest[2] = dsp_core.registers[DSP_REG_B0];
5007: newsr = dsp_asr56(dest);
5008:
5009: source[0] = dsp_core.registers[DSP_REG_A2];
5010: source[1] = dsp_core.registers[DSP_REG_A1];
5011: source[2] = dsp_core.registers[DSP_REG_A0];
5012: newsr |= dsp_add56(source, dest);
5013:
5014: dsp_core.registers[DSP_REG_B2] = dest[0];
5015: dsp_core.registers[DSP_REG_B1] = dest[1];
5016: dsp_core.registers[DSP_REG_B0] = dest[2];
5017:
5018: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5019:
5020: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5021: dsp_core.registers[DSP_REG_SR] |= newsr;
5022: }
5023:
5024: static void dsp_and_x0_a(void)
5025: {
5026: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X0];
5027:
5028: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5029: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5030: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5031: }
5032:
5033: static void dsp_and_x0_b(void)
5034: {
5035: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X0];
5036:
5037: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5038: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5039: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5040: }
5041:
5042: static void dsp_and_y0_a(void)
5043: {
5044: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y0];
5045:
5046: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5047: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5048: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5049: }
5050:
5051: static void dsp_and_y0_b(void)
5052: {
5053: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y0];
5054:
5055: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5056: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5057: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5058: }
5059:
5060: static void dsp_and_x1_a(void)
5061: {
5062: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X1];
5063:
5064: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5065: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5066: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5067: }
5068:
5069: static void dsp_and_x1_b(void)
5070: {
5071: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X1];
5072:
5073: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5074: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5075: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5076: }
5077:
5078: static void dsp_and_y1_a(void)
5079: {
5080: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y1];
5081:
5082: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5083: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5084: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5085: }
5086:
5087: static void dsp_and_y1_b(void)
5088: {
5089: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y1];
5090:
5091: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5092: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5093: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5094: }
5095:
5096: static void dsp_asl_a(void)
5097: {
5098: Uint32 dest[3];
5099: Uint16 newsr;
5100:
5101: dest[0] = dsp_core.registers[DSP_REG_A2];
5102: dest[1] = dsp_core.registers[DSP_REG_A1];
5103: dest[2] = dsp_core.registers[DSP_REG_A0];
5104:
5105: newsr = dsp_asl56(dest);
5106:
5107: dsp_core.registers[DSP_REG_A2] = dest[0];
5108: dsp_core.registers[DSP_REG_A1] = dest[1];
5109: dsp_core.registers[DSP_REG_A0] = dest[2];
5110:
5111: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5112: dsp_core.registers[DSP_REG_SR] |= newsr;
5113:
5114: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5115: }
5116:
5117: static void dsp_asl_b(void)
5118: {
5119: Uint32 dest[3];
5120: Uint16 newsr;
5121:
5122: dest[0] = dsp_core.registers[DSP_REG_B2];
5123: dest[1] = dsp_core.registers[DSP_REG_B1];
5124: dest[2] = dsp_core.registers[DSP_REG_B0];
5125:
5126: newsr = dsp_asl56(dest);
5127:
5128: dsp_core.registers[DSP_REG_B2] = dest[0];
5129: dsp_core.registers[DSP_REG_B1] = dest[1];
5130: dsp_core.registers[DSP_REG_B0] = dest[2];
5131:
5132: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5133: dsp_core.registers[DSP_REG_SR] |= newsr;
5134:
5135: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5136: }
5137:
5138: static void dsp_asr_a(void)
5139: {
5140: Uint32 dest[3];
5141: Uint16 newsr;
5142:
5143: dest[0] = dsp_core.registers[DSP_REG_A2];
5144: dest[1] = dsp_core.registers[DSP_REG_A1];
5145: dest[2] = dsp_core.registers[DSP_REG_A0];
5146:
5147: newsr = dsp_asr56(dest);
5148:
5149: dsp_core.registers[DSP_REG_A2] = dest[0];
5150: dsp_core.registers[DSP_REG_A1] = dest[1];
5151: dsp_core.registers[DSP_REG_A0] = dest[2];
5152:
5153: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5154: dsp_core.registers[DSP_REG_SR] |= newsr;
5155:
5156: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5157: }
5158:
5159: static void dsp_asr_b(void)
5160: {
5161: Uint32 dest[3];
5162: Uint16 newsr;
5163:
5164: dest[0] = dsp_core.registers[DSP_REG_B2];
5165: dest[1] = dsp_core.registers[DSP_REG_B1];
5166: dest[2] = dsp_core.registers[DSP_REG_B0];
5167:
5168: newsr = dsp_asr56(dest);
5169:
5170: dsp_core.registers[DSP_REG_B2] = dest[0];
5171: dsp_core.registers[DSP_REG_B1] = dest[1];
5172: dsp_core.registers[DSP_REG_B0] = dest[2];
5173:
5174: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5175: dsp_core.registers[DSP_REG_SR] |= newsr;
5176:
5177: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5178: }
5179:
5180: static void dsp_clr_a(void)
5181: {
5182: dsp_core.registers[DSP_REG_A2] = 0;
5183: dsp_core.registers[DSP_REG_A1] = 0;
5184: dsp_core.registers[DSP_REG_A0] = 0;
5185:
5186: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5187: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5188: }
5189:
5190: static void dsp_clr_b(void)
5191: {
5192: dsp_core.registers[DSP_REG_B2] = 0;
5193: dsp_core.registers[DSP_REG_B1] = 0;
5194: dsp_core.registers[DSP_REG_B0] = 0;
5195:
5196: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5197: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5198: }
5199:
5200: static void dsp_cmp_b_a(void)
5201: {
5202: Uint32 source[3], dest[3];
5203: Uint16 newsr;
5204:
5205: dest[0] = dsp_core.registers[DSP_REG_A2];
5206: dest[1] = dsp_core.registers[DSP_REG_A1];
5207: dest[2] = dsp_core.registers[DSP_REG_A0];
5208:
5209: source[0] = dsp_core.registers[DSP_REG_B2];
5210: source[1] = dsp_core.registers[DSP_REG_B1];
5211: source[2] = dsp_core.registers[DSP_REG_B0];
5212:
5213: newsr = dsp_sub56(source, dest);
5214:
5215: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5216:
5217: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5218: dsp_core.registers[DSP_REG_SR] |= newsr;
5219: }
5220:
5221: static void dsp_cmp_a_b(void)
5222: {
5223: Uint32 source[3], dest[3];
5224: Uint16 newsr;
5225:
5226: dest[0] = dsp_core.registers[DSP_REG_B2];
5227: dest[1] = dsp_core.registers[DSP_REG_B1];
5228: dest[2] = dsp_core.registers[DSP_REG_B0];
5229:
5230: source[0] = dsp_core.registers[DSP_REG_A2];
5231: source[1] = dsp_core.registers[DSP_REG_A1];
5232: source[2] = dsp_core.registers[DSP_REG_A0];
5233:
5234: newsr = dsp_sub56(source, dest);
5235:
5236: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5237:
5238: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5239: dsp_core.registers[DSP_REG_SR] |= newsr;
5240: }
5241:
5242: static void dsp_cmp_x0_a(void)
5243: {
5244: Uint32 source[3], dest[3];
5245: Uint16 newsr;
5246:
5247: dest[2] = dsp_core.registers[DSP_REG_A0];
5248: dest[1] = dsp_core.registers[DSP_REG_A1];
5249: dest[0] = dsp_core.registers[DSP_REG_A2];
5250:
5251: source[2] = 0;
5252: source[1] = dsp_core.registers[DSP_REG_X0];
5253: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5254:
5255: newsr = dsp_sub56(source, dest);
5256:
5257: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5258:
5259: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5260: dsp_core.registers[DSP_REG_SR] |= newsr;
5261: }
5262:
5263: static void dsp_cmp_x0_b(void)
5264: {
5265: Uint32 source[3], dest[3];
5266: Uint16 newsr;
5267:
5268: dest[0] = dsp_core.registers[DSP_REG_B2];
5269: dest[1] = dsp_core.registers[DSP_REG_B1];
5270: dest[2] = dsp_core.registers[DSP_REG_B0];
5271:
5272: source[2] = 0;
5273: source[1] = dsp_core.registers[DSP_REG_X0];
5274: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5275:
5276: newsr = dsp_sub56(source, dest);
5277:
5278: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5279:
5280: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5281: dsp_core.registers[DSP_REG_SR] |= newsr;
5282: }
5283:
5284: static void dsp_cmp_y0_a(void)
5285: {
5286: Uint32 source[3], dest[3];
5287: Uint16 newsr;
5288:
5289: dest[2] = dsp_core.registers[DSP_REG_A0];
5290: dest[1] = dsp_core.registers[DSP_REG_A1];
5291: dest[0] = dsp_core.registers[DSP_REG_A2];
5292:
5293: source[2] = 0;
5294: source[1] = dsp_core.registers[DSP_REG_Y0];
5295: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5296:
5297: newsr = dsp_sub56(source, dest);
5298:
5299: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5300:
5301: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5302: dsp_core.registers[DSP_REG_SR] |= newsr;
5303: }
5304:
5305: static void dsp_cmp_y0_b(void)
5306: {
5307: Uint32 source[3], dest[3];
5308: Uint16 newsr;
5309:
5310: dest[0] = dsp_core.registers[DSP_REG_B2];
5311: dest[1] = dsp_core.registers[DSP_REG_B1];
5312: dest[2] = dsp_core.registers[DSP_REG_B0];
5313:
5314: source[2] = 0;
5315: source[1] = dsp_core.registers[DSP_REG_Y0];
5316: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5317:
5318: newsr = dsp_sub56(source, dest);
5319:
5320: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5321:
5322: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5323: dsp_core.registers[DSP_REG_SR] |= newsr;
5324: }
5325: static void dsp_cmp_x1_a(void)
5326: {
5327: Uint32 source[3], dest[3];
5328: Uint16 newsr;
5329:
5330: dest[2] = dsp_core.registers[DSP_REG_A0];
5331: dest[1] = dsp_core.registers[DSP_REG_A1];
5332: dest[0] = dsp_core.registers[DSP_REG_A2];
5333:
5334: source[2] = 0;
5335: source[1] = dsp_core.registers[DSP_REG_X1];
5336: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5337:
5338: newsr = dsp_sub56(source, dest);
5339:
5340: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5341:
5342: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5343: dsp_core.registers[DSP_REG_SR] |= newsr;
5344: }
5345:
5346: static void dsp_cmp_x1_b(void)
5347: {
5348: Uint32 source[3], dest[3];
5349: Uint16 newsr;
5350:
5351: dest[0] = dsp_core.registers[DSP_REG_B2];
5352: dest[1] = dsp_core.registers[DSP_REG_B1];
5353: dest[2] = dsp_core.registers[DSP_REG_B0];
5354:
5355: source[2] = 0;
5356: source[1] = dsp_core.registers[DSP_REG_X1];
5357: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5358:
5359: newsr = dsp_sub56(source, dest);
5360:
5361: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5362:
5363: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5364: dsp_core.registers[DSP_REG_SR] |= newsr;
5365: }
5366:
5367: static void dsp_cmp_y1_a(void)
5368: {
5369: Uint32 source[3], dest[3];
5370: Uint16 newsr;
5371:
5372: dest[2] = dsp_core.registers[DSP_REG_A0];
5373: dest[1] = dsp_core.registers[DSP_REG_A1];
5374: dest[0] = dsp_core.registers[DSP_REG_A2];
5375:
5376: source[2] = 0;
5377: source[1] = dsp_core.registers[DSP_REG_Y1];
5378: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5379:
5380: newsr = dsp_sub56(source, dest);
5381:
5382: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5383:
5384: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5385: dsp_core.registers[DSP_REG_SR] |= newsr;
5386: }
5387:
5388: static void dsp_cmp_y1_b(void)
5389: {
5390: Uint32 source[3], dest[3];
5391: Uint16 newsr;
5392:
5393: dest[0] = dsp_core.registers[DSP_REG_B2];
5394: dest[1] = dsp_core.registers[DSP_REG_B1];
5395: dest[2] = dsp_core.registers[DSP_REG_B0];
5396:
5397: source[2] = 0;
5398: source[1] = dsp_core.registers[DSP_REG_Y1];
5399: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5400:
5401: newsr = dsp_sub56(source, dest);
5402:
5403: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5404:
5405: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5406: dsp_core.registers[DSP_REG_SR] |= newsr;
5407: }
5408:
5409: static void dsp_cmpm_b_a(void)
5410: {
5411: Uint32 source[3], dest[3];
5412: Uint16 newsr;
5413:
5414: dest[0] = dsp_core.registers[DSP_REG_A2];
5415: dest[1] = dsp_core.registers[DSP_REG_A1];
5416: dest[2] = dsp_core.registers[DSP_REG_A0];
5417: dsp_abs56(dest);
5418:
5419: source[0] = dsp_core.registers[DSP_REG_B2];
5420: source[1] = dsp_core.registers[DSP_REG_B1];
5421: source[2] = dsp_core.registers[DSP_REG_B0];
5422: dsp_abs56(source);
5423:
5424: newsr = dsp_sub56(source, dest);
5425:
5426: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5427:
5428: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5429: dsp_core.registers[DSP_REG_SR] |= newsr;
5430: }
5431:
5432: static void dsp_cmpm_a_b(void)
5433: {
5434: Uint32 source[3], dest[3];
5435: Uint16 newsr;
5436:
5437: dest[0] = dsp_core.registers[DSP_REG_B2];
5438: dest[1] = dsp_core.registers[DSP_REG_B1];
5439: dest[2] = dsp_core.registers[DSP_REG_B0];
5440: dsp_abs56(dest);
5441:
5442: source[0] = dsp_core.registers[DSP_REG_A2];
5443: source[1] = dsp_core.registers[DSP_REG_A1];
5444: source[2] = dsp_core.registers[DSP_REG_A0];
5445: dsp_abs56(source);
5446:
5447: newsr = dsp_sub56(source, dest);
5448:
5449: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5450:
5451: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5452: dsp_core.registers[DSP_REG_SR] |= newsr;
5453: }
5454:
5455: static void dsp_cmpm_x0_a(void)
5456: {
5457: Uint32 source[3], dest[3];
5458: Uint16 newsr;
5459:
5460: dest[2] = dsp_core.registers[DSP_REG_A0];
5461: dest[1] = dsp_core.registers[DSP_REG_A1];
5462: dest[0] = dsp_core.registers[DSP_REG_A2];
5463: dsp_abs56(dest);
5464:
5465: source[2] = 0;
5466: source[1] = dsp_core.registers[DSP_REG_X0];
5467: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5468: dsp_abs56(source);
5469:
5470: newsr = dsp_sub56(source, dest);
5471:
5472: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5473:
5474: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5475: dsp_core.registers[DSP_REG_SR] |= newsr;
5476: }
5477:
5478: static void dsp_cmpm_x0_b(void)
5479: {
5480: Uint32 source[3], dest[3];
5481: Uint16 newsr;
5482:
5483: dest[0] = dsp_core.registers[DSP_REG_B2];
5484: dest[1] = dsp_core.registers[DSP_REG_B1];
5485: dest[2] = dsp_core.registers[DSP_REG_B0];
5486: dsp_abs56(dest);
5487:
5488: source[2] = 0;
5489: source[1] = dsp_core.registers[DSP_REG_X0];
5490: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5491: dsp_abs56(source);
5492:
5493: newsr = dsp_sub56(source, dest);
5494:
5495: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5496:
5497: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5498: dsp_core.registers[DSP_REG_SR] |= newsr;
5499: }
5500:
5501: static void dsp_cmpm_y0_a(void)
5502: {
5503: Uint32 source[3], dest[3];
5504: Uint16 newsr;
5505:
5506: dest[2] = dsp_core.registers[DSP_REG_A0];
5507: dest[1] = dsp_core.registers[DSP_REG_A1];
5508: dest[0] = dsp_core.registers[DSP_REG_A2];
5509: dsp_abs56(dest);
5510:
5511: source[2] = 0;
5512: source[1] = dsp_core.registers[DSP_REG_Y0];
5513: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5514: dsp_abs56(source);
5515:
5516: newsr = dsp_sub56(source, dest);
5517:
5518: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5519:
5520: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5521: dsp_core.registers[DSP_REG_SR] |= newsr;
5522: }
5523:
5524: static void dsp_cmpm_y0_b(void)
5525: {
5526: Uint32 source[3], dest[3];
5527: Uint16 newsr;
5528:
5529: dest[0] = dsp_core.registers[DSP_REG_B2];
5530: dest[1] = dsp_core.registers[DSP_REG_B1];
5531: dest[2] = dsp_core.registers[DSP_REG_B0];
5532: dsp_abs56(dest);
5533:
5534: source[2] = 0;
5535: source[1] = dsp_core.registers[DSP_REG_Y0];
5536: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5537: dsp_abs56(source);
5538:
5539: newsr = dsp_sub56(source, dest);
5540:
5541: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5542:
5543: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5544: dsp_core.registers[DSP_REG_SR] |= newsr;
5545: }
5546:
5547: static void dsp_cmpm_x1_a(void)
5548: {
5549: Uint32 source[3], dest[3];
5550: Uint16 newsr;
5551:
5552: dest[2] = dsp_core.registers[DSP_REG_A0];
5553: dest[1] = dsp_core.registers[DSP_REG_A1];
5554: dest[0] = dsp_core.registers[DSP_REG_A2];
5555: dsp_abs56(dest);
5556:
5557: source[2] = 0;
5558: source[1] = dsp_core.registers[DSP_REG_X1];
5559: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5560: dsp_abs56(source);
5561:
5562: newsr = dsp_sub56(source, dest);
5563:
5564: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5565:
5566: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5567: dsp_core.registers[DSP_REG_SR] |= newsr;
5568: }
5569:
5570: static void dsp_cmpm_x1_b(void)
5571: {
5572: Uint32 source[3], dest[3];
5573: Uint16 newsr;
5574:
5575: dest[0] = dsp_core.registers[DSP_REG_B2];
5576: dest[1] = dsp_core.registers[DSP_REG_B1];
5577: dest[2] = dsp_core.registers[DSP_REG_B0];
5578: dsp_abs56(dest);
5579:
5580: source[2] = 0;
5581: source[1] = dsp_core.registers[DSP_REG_X1];
5582: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5583: dsp_abs56(source);
5584:
5585: newsr = dsp_sub56(source, dest);
5586:
5587: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5588:
5589: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5590: dsp_core.registers[DSP_REG_SR] |= newsr;
5591: }
5592:
5593: static void dsp_cmpm_y1_a(void)
5594: {
5595: Uint32 source[3], dest[3];
5596: Uint16 newsr;
5597:
5598: dest[2] = dsp_core.registers[DSP_REG_A0];
5599: dest[1] = dsp_core.registers[DSP_REG_A1];
5600: dest[0] = dsp_core.registers[DSP_REG_A2];
5601: dsp_abs56(dest);
5602:
5603: source[2] = 0;
5604: source[1] = dsp_core.registers[DSP_REG_Y1];
5605: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5606: dsp_abs56(source);
5607:
5608: newsr = dsp_sub56(source, dest);
5609:
5610: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5611:
5612: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5613: dsp_core.registers[DSP_REG_SR] |= newsr;
5614: }
5615:
5616: static void dsp_cmpm_y1_b(void)
5617: {
5618: Uint32 source[3], dest[3];
5619: Uint16 newsr;
5620:
5621: dest[0] = dsp_core.registers[DSP_REG_B2];
5622: dest[1] = dsp_core.registers[DSP_REG_B1];
5623: dest[2] = dsp_core.registers[DSP_REG_B0];
5624: dsp_abs56(dest);
5625:
5626: source[2] = 0;
5627: source[1] = dsp_core.registers[DSP_REG_Y1];
5628: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
5629: dsp_abs56(source);
5630:
5631: newsr = dsp_sub56(source, dest);
5632:
5633: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5634:
5635: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5636: dsp_core.registers[DSP_REG_SR] |= newsr;
5637: }
5638:
5639: static void dsp_eor_x0_a(void)
5640: {
5641: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X0];
5642: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5643:
5644: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5645: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5646: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5647: }
5648:
5649: static void dsp_eor_x0_b(void)
5650: {
5651: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X0];
5652: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5653:
5654: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5655: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5656: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5657: }
5658:
5659: static void dsp_eor_y0_a(void)
5660: {
5661: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y0];
5662: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5663:
5664: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5665: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5666: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5667: }
5668:
5669: static void dsp_eor_y0_b(void)
5670: {
5671: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y0];
5672: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5673:
5674: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5675: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5676: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5677: }
5678:
5679: static void dsp_eor_x1_a(void)
5680: {
5681: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X1];
5682: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5683:
5684: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5685: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5686: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5687: }
5688:
5689: static void dsp_eor_x1_b(void)
5690: {
5691: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X1];
5692: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5693:
5694: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5695: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5696: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5697: }
5698:
5699: static void dsp_eor_y1_a(void)
5700: {
5701: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y1];
5702: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5703:
5704: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5705: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5706: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5707: }
5708:
5709: static void dsp_eor_y1_b(void)
5710: {
5711: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y1];
5712: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5713:
5714: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5715: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5716: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5717: }
5718:
5719: static void dsp_lsl_a(void)
5720: {
5721: Uint32 newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
5722:
5723: dsp_core.registers[DSP_REG_A1] <<= 1;
5724: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
5725:
5726: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5727: dsp_core.registers[DSP_REG_SR] |= newcarry;
5728: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5729: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5730: }
5731:
5732: static void dsp_lsl_b(void)
5733: {
5734: Uint32 newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
5735:
5736: dsp_core.registers[DSP_REG_B1] <<= 1;
5737: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
5738:
5739: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5740: dsp_core.registers[DSP_REG_SR] |= newcarry;
5741: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5742: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5743: }
5744:
5745: static void dsp_lsr_a(void)
5746: {
5747: Uint32 newcarry = dsp_core.registers[DSP_REG_A1] & 1;
5748: dsp_core.registers[DSP_REG_A1] >>= 1;
5749:
5750: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5751: dsp_core.registers[DSP_REG_SR] |= newcarry;
5752: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5753: }
5754:
5755: static void dsp_lsr_b(void)
5756: {
5757: Uint32 newcarry = dsp_core.registers[DSP_REG_B1] & 1;
5758: dsp_core.registers[DSP_REG_B1] >>= 1;
5759:
5760: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5761: dsp_core.registers[DSP_REG_SR] |= newcarry;
5762: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5763: }
5764:
5765: static void dsp_mac_p_x0_x0_a(void)
5766: {
5767: Uint32 source[3], dest[3];
5768: Uint16 newsr;
5769:
5770: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5771:
5772: dest[0] = dsp_core.registers[DSP_REG_A2];
5773: dest[1] = dsp_core.registers[DSP_REG_A1];
5774: dest[2] = dsp_core.registers[DSP_REG_A0];
5775: newsr = dsp_add56(source, dest);
5776:
5777: dsp_core.registers[DSP_REG_A2] = dest[0];
5778: dsp_core.registers[DSP_REG_A1] = dest[1];
5779: dsp_core.registers[DSP_REG_A0] = dest[2];
5780:
5781: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5782:
5783: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5784: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5785: }
5786:
5787: static void dsp_mac_m_x0_x0_a(void)
5788: {
5789: Uint32 source[3], dest[3];
5790: Uint16 newsr;
5791:
5792: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5793:
5794: dest[0] = dsp_core.registers[DSP_REG_A2];
5795: dest[1] = dsp_core.registers[DSP_REG_A1];
5796: dest[2] = dsp_core.registers[DSP_REG_A0];
5797: newsr = dsp_add56(source, dest);
5798:
5799: dsp_core.registers[DSP_REG_A2] = dest[0];
5800: dsp_core.registers[DSP_REG_A1] = dest[1];
5801: dsp_core.registers[DSP_REG_A0] = dest[2];
5802:
5803: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5804:
5805: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5806: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5807: }
5808: static void dsp_mac_p_x0_x0_b(void)
5809: {
5810: Uint32 source[3], dest[3];
5811: Uint16 newsr;
5812:
5813: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5814:
5815: dest[0] = dsp_core.registers[DSP_REG_B2];
5816: dest[1] = dsp_core.registers[DSP_REG_B1];
5817: dest[2] = dsp_core.registers[DSP_REG_B0];
5818: newsr = dsp_add56(source, dest);
5819:
5820: dsp_core.registers[DSP_REG_B2] = dest[0];
5821: dsp_core.registers[DSP_REG_B1] = dest[1];
5822: dsp_core.registers[DSP_REG_B0] = dest[2];
5823:
5824: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5825:
5826: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5827: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5828: }
5829:
5830: static void dsp_mac_m_x0_x0_b(void)
5831: {
5832: Uint32 source[3], dest[3];
5833: Uint16 newsr;
5834:
5835: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5836:
5837: dest[0] = dsp_core.registers[DSP_REG_B2];
5838: dest[1] = dsp_core.registers[DSP_REG_B1];
5839: dest[2] = dsp_core.registers[DSP_REG_B0];
5840: newsr = dsp_add56(source, dest);
5841:
5842: dsp_core.registers[DSP_REG_B2] = dest[0];
5843: dsp_core.registers[DSP_REG_B1] = dest[1];
5844: dsp_core.registers[DSP_REG_B0] = dest[2];
5845:
5846: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5847:
5848: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5849: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5850: }
5851:
5852: static void dsp_mac_p_y0_y0_a(void)
5853: {
5854: Uint32 source[3], dest[3];
5855: Uint16 newsr;
5856:
5857: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5858:
5859: dest[0] = dsp_core.registers[DSP_REG_A2];
5860: dest[1] = dsp_core.registers[DSP_REG_A1];
5861: dest[2] = dsp_core.registers[DSP_REG_A0];
5862: newsr = dsp_add56(source, dest);
5863:
5864: dsp_core.registers[DSP_REG_A2] = dest[0];
5865: dsp_core.registers[DSP_REG_A1] = dest[1];
5866: dsp_core.registers[DSP_REG_A0] = dest[2];
5867:
5868: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5869:
5870: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5871: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5872: }
5873:
5874: static void dsp_mac_m_y0_y0_a(void)
5875: {
5876: Uint32 source[3], dest[3];
5877: Uint16 newsr;
5878:
5879: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5880:
5881: dest[0] = dsp_core.registers[DSP_REG_A2];
5882: dest[1] = dsp_core.registers[DSP_REG_A1];
5883: dest[2] = dsp_core.registers[DSP_REG_A0];
5884: newsr = dsp_add56(source, dest);
5885:
5886: dsp_core.registers[DSP_REG_A2] = dest[0];
5887: dsp_core.registers[DSP_REG_A1] = dest[1];
5888: dsp_core.registers[DSP_REG_A0] = dest[2];
5889:
5890: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5891:
5892: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5893: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5894: }
5895: static void dsp_mac_p_y0_y0_b(void)
5896: {
5897: Uint32 source[3], dest[3];
5898: Uint16 newsr;
5899:
5900: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5901:
5902: dest[0] = dsp_core.registers[DSP_REG_B2];
5903: dest[1] = dsp_core.registers[DSP_REG_B1];
5904: dest[2] = dsp_core.registers[DSP_REG_B0];
5905: newsr = dsp_add56(source, dest);
5906:
5907: dsp_core.registers[DSP_REG_B2] = dest[0];
5908: dsp_core.registers[DSP_REG_B1] = dest[1];
5909: dsp_core.registers[DSP_REG_B0] = dest[2];
5910:
5911: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5912:
5913: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5914: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5915: }
5916:
5917: static void dsp_mac_m_y0_y0_b(void)
5918: {
5919: Uint32 source[3], dest[3];
5920: Uint16 newsr;
5921:
5922: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5923:
5924: dest[0] = dsp_core.registers[DSP_REG_B2];
5925: dest[1] = dsp_core.registers[DSP_REG_B1];
5926: dest[2] = dsp_core.registers[DSP_REG_B0];
5927: newsr = dsp_add56(source, dest);
5928:
5929: dsp_core.registers[DSP_REG_B2] = dest[0];
5930: dsp_core.registers[DSP_REG_B1] = dest[1];
5931: dsp_core.registers[DSP_REG_B0] = dest[2];
5932:
5933: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5934:
5935: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5936: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5937: }
5938:
5939: static void dsp_mac_p_x1_x0_a(void)
5940: {
5941: Uint32 source[3], dest[3];
5942: Uint16 newsr;
5943:
5944: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5945:
5946: dest[0] = dsp_core.registers[DSP_REG_A2];
5947: dest[1] = dsp_core.registers[DSP_REG_A1];
5948: dest[2] = dsp_core.registers[DSP_REG_A0];
5949: newsr = dsp_add56(source, dest);
5950:
5951: dsp_core.registers[DSP_REG_A2] = dest[0];
5952: dsp_core.registers[DSP_REG_A1] = dest[1];
5953: dsp_core.registers[DSP_REG_A0] = dest[2];
5954:
5955: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5956:
5957: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5958: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5959: }
5960:
5961: static void dsp_mac_m_x1_x0_a(void)
5962: {
5963: Uint32 source[3], dest[3];
5964: Uint16 newsr;
5965:
5966: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5967:
5968: dest[0] = dsp_core.registers[DSP_REG_A2];
5969: dest[1] = dsp_core.registers[DSP_REG_A1];
5970: dest[2] = dsp_core.registers[DSP_REG_A0];
5971: newsr = dsp_add56(source, dest);
5972:
5973: dsp_core.registers[DSP_REG_A2] = dest[0];
5974: dsp_core.registers[DSP_REG_A1] = dest[1];
5975: dsp_core.registers[DSP_REG_A0] = dest[2];
5976:
5977: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5978:
5979: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5980: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5981: }
5982:
5983: static void dsp_mac_p_x1_x0_b(void)
5984: {
5985: Uint32 source[3], dest[3];
5986: Uint16 newsr;
5987:
5988: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5989:
5990: dest[0] = dsp_core.registers[DSP_REG_B2];
5991: dest[1] = dsp_core.registers[DSP_REG_B1];
5992: dest[2] = dsp_core.registers[DSP_REG_B0];
5993: newsr = dsp_add56(source, dest);
5994:
5995: dsp_core.registers[DSP_REG_B2] = dest[0];
5996: dsp_core.registers[DSP_REG_B1] = dest[1];
5997: dsp_core.registers[DSP_REG_B0] = dest[2];
5998:
5999: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6000:
6001: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6002: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6003: }
6004:
6005: static void dsp_mac_m_x1_x0_b(void)
6006: {
6007: Uint32 source[3], dest[3];
6008: Uint16 newsr;
6009:
6010: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6011:
6012: dest[0] = dsp_core.registers[DSP_REG_B2];
6013: dest[1] = dsp_core.registers[DSP_REG_B1];
6014: dest[2] = dsp_core.registers[DSP_REG_B0];
6015: newsr = dsp_add56(source, dest);
6016:
6017: dsp_core.registers[DSP_REG_B2] = dest[0];
6018: dsp_core.registers[DSP_REG_B1] = dest[1];
6019: dsp_core.registers[DSP_REG_B0] = dest[2];
6020:
6021: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6022:
6023: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6024: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6025: }
6026:
6027: static void dsp_mac_p_y1_y0_a(void)
6028: {
6029: Uint32 source[3], dest[3];
6030: Uint16 newsr;
6031:
6032: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6033:
6034: dest[0] = dsp_core.registers[DSP_REG_A2];
6035: dest[1] = dsp_core.registers[DSP_REG_A1];
6036: dest[2] = dsp_core.registers[DSP_REG_A0];
6037: newsr = dsp_add56(source, dest);
6038:
6039: dsp_core.registers[DSP_REG_A2] = dest[0];
6040: dsp_core.registers[DSP_REG_A1] = dest[1];
6041: dsp_core.registers[DSP_REG_A0] = dest[2];
6042:
6043: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6044:
6045: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6046: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6047: }
6048:
6049: static void dsp_mac_m_y1_y0_a(void)
6050: {
6051: Uint32 source[3], dest[3];
6052: Uint16 newsr;
6053:
6054: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6055:
6056: dest[0] = dsp_core.registers[DSP_REG_A2];
6057: dest[1] = dsp_core.registers[DSP_REG_A1];
6058: dest[2] = dsp_core.registers[DSP_REG_A0];
6059: newsr = dsp_add56(source, dest);
6060:
6061: dsp_core.registers[DSP_REG_A2] = dest[0];
6062: dsp_core.registers[DSP_REG_A1] = dest[1];
6063: dsp_core.registers[DSP_REG_A0] = dest[2];
6064:
6065: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6066:
6067: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6068: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6069: }
6070:
6071: static void dsp_mac_p_y1_y0_b(void)
6072: {
6073: Uint32 source[3], dest[3];
6074: Uint16 newsr;
6075:
6076: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6077:
6078: dest[0] = dsp_core.registers[DSP_REG_B2];
6079: dest[1] = dsp_core.registers[DSP_REG_B1];
6080: dest[2] = dsp_core.registers[DSP_REG_B0];
6081: newsr = dsp_add56(source, dest);
6082:
6083: dsp_core.registers[DSP_REG_B2] = dest[0];
6084: dsp_core.registers[DSP_REG_B1] = dest[1];
6085: dsp_core.registers[DSP_REG_B0] = dest[2];
6086:
6087: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6088:
6089: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6090: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6091: }
6092:
6093: static void dsp_mac_m_y1_y0_b(void)
6094: {
6095: Uint32 source[3], dest[3];
6096: Uint16 newsr;
6097:
6098: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6099:
6100: dest[0] = dsp_core.registers[DSP_REG_B2];
6101: dest[1] = dsp_core.registers[DSP_REG_B1];
6102: dest[2] = dsp_core.registers[DSP_REG_B0];
6103: newsr = dsp_add56(source, dest);
6104:
6105: dsp_core.registers[DSP_REG_B2] = dest[0];
6106: dsp_core.registers[DSP_REG_B1] = dest[1];
6107: dsp_core.registers[DSP_REG_B0] = dest[2];
6108:
6109: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6110:
6111: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6112: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6113: }
6114:
6115: static void dsp_mac_p_x0_y1_a(void)
6116: {
6117: Uint32 source[3], dest[3];
6118: Uint16 newsr;
6119:
6120: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6121:
6122: dest[0] = dsp_core.registers[DSP_REG_A2];
6123: dest[1] = dsp_core.registers[DSP_REG_A1];
6124: dest[2] = dsp_core.registers[DSP_REG_A0];
6125: newsr = dsp_add56(source, dest);
6126:
6127: dsp_core.registers[DSP_REG_A2] = dest[0];
6128: dsp_core.registers[DSP_REG_A1] = dest[1];
6129: dsp_core.registers[DSP_REG_A0] = dest[2];
6130:
6131: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6132:
6133: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6134: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6135: }
6136:
6137: static void dsp_mac_m_x0_y1_a(void)
6138: {
6139: Uint32 source[3], dest[3];
6140: Uint16 newsr;
6141:
6142: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6143:
6144: dest[0] = dsp_core.registers[DSP_REG_A2];
6145: dest[1] = dsp_core.registers[DSP_REG_A1];
6146: dest[2] = dsp_core.registers[DSP_REG_A0];
6147: newsr = dsp_add56(source, dest);
6148:
6149: dsp_core.registers[DSP_REG_A2] = dest[0];
6150: dsp_core.registers[DSP_REG_A1] = dest[1];
6151: dsp_core.registers[DSP_REG_A0] = dest[2];
6152:
6153: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6154:
6155: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6156: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6157: }
6158:
6159: static void dsp_mac_p_x0_y1_b(void)
6160: {
6161: Uint32 source[3], dest[3];
6162: Uint16 newsr;
6163:
6164: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6165:
6166: dest[0] = dsp_core.registers[DSP_REG_B2];
6167: dest[1] = dsp_core.registers[DSP_REG_B1];
6168: dest[2] = dsp_core.registers[DSP_REG_B0];
6169: newsr = dsp_add56(source, dest);
6170:
6171: dsp_core.registers[DSP_REG_B2] = dest[0];
6172: dsp_core.registers[DSP_REG_B1] = dest[1];
6173: dsp_core.registers[DSP_REG_B0] = dest[2];
6174:
6175: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6176:
6177: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6178: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6179: }
6180:
6181: static void dsp_mac_m_x0_y1_b(void)
6182: {
6183: Uint32 source[3], dest[3];
6184: Uint16 newsr;
6185:
6186: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6187:
6188: dest[0] = dsp_core.registers[DSP_REG_B2];
6189: dest[1] = dsp_core.registers[DSP_REG_B1];
6190: dest[2] = dsp_core.registers[DSP_REG_B0];
6191: newsr = dsp_add56(source, dest);
6192:
6193: dsp_core.registers[DSP_REG_B2] = dest[0];
6194: dsp_core.registers[DSP_REG_B1] = dest[1];
6195: dsp_core.registers[DSP_REG_B0] = dest[2];
6196:
6197: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6198:
6199: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6200: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6201: }
6202:
6203: static void dsp_mac_p_y0_x0_a(void)
6204: {
6205: Uint32 source[3], dest[3];
6206: Uint16 newsr;
6207:
6208: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6209:
6210: dest[0] = dsp_core.registers[DSP_REG_A2];
6211: dest[1] = dsp_core.registers[DSP_REG_A1];
6212: dest[2] = dsp_core.registers[DSP_REG_A0];
6213: newsr = dsp_add56(source, dest);
6214:
6215: dsp_core.registers[DSP_REG_A2] = dest[0];
6216: dsp_core.registers[DSP_REG_A1] = dest[1];
6217: dsp_core.registers[DSP_REG_A0] = dest[2];
6218:
6219: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6220:
6221: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6222: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6223: }
6224:
6225: static void dsp_mac_m_y0_x0_a(void)
6226: {
6227: Uint32 source[3], dest[3];
6228: Uint16 newsr;
6229:
6230: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6231:
6232: dest[0] = dsp_core.registers[DSP_REG_A2];
6233: dest[1] = dsp_core.registers[DSP_REG_A1];
6234: dest[2] = dsp_core.registers[DSP_REG_A0];
6235: newsr = dsp_add56(source, dest);
6236:
6237: dsp_core.registers[DSP_REG_A2] = dest[0];
6238: dsp_core.registers[DSP_REG_A1] = dest[1];
6239: dsp_core.registers[DSP_REG_A0] = dest[2];
6240:
6241: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6242:
6243: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6244: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6245: }
6246:
6247: static void dsp_mac_p_y0_x0_b(void)
6248: {
6249: Uint32 source[3], dest[3];
6250: Uint16 newsr;
6251:
6252: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6253:
6254: dest[0] = dsp_core.registers[DSP_REG_B2];
6255: dest[1] = dsp_core.registers[DSP_REG_B1];
6256: dest[2] = dsp_core.registers[DSP_REG_B0];
6257: newsr = dsp_add56(source, dest);
6258:
6259: dsp_core.registers[DSP_REG_B2] = dest[0];
6260: dsp_core.registers[DSP_REG_B1] = dest[1];
6261: dsp_core.registers[DSP_REG_B0] = dest[2];
6262:
6263: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6264:
6265: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6266: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6267: }
6268:
6269: static void dsp_mac_m_y0_x0_b(void)
6270: {
6271: Uint32 source[3], dest[3];
6272: Uint16 newsr;
6273:
6274: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6275:
6276: dest[0] = dsp_core.registers[DSP_REG_B2];
6277: dest[1] = dsp_core.registers[DSP_REG_B1];
6278: dest[2] = dsp_core.registers[DSP_REG_B0];
6279: newsr = dsp_add56(source, dest);
6280:
6281: dsp_core.registers[DSP_REG_B2] = dest[0];
6282: dsp_core.registers[DSP_REG_B1] = dest[1];
6283: dsp_core.registers[DSP_REG_B0] = dest[2];
6284:
6285: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6286:
6287: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6288: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6289: }
6290:
6291: static void dsp_mac_p_x1_y0_a(void)
6292: {
6293: Uint32 source[3], dest[3];
6294: Uint16 newsr;
6295:
6296: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6297:
6298: dest[0] = dsp_core.registers[DSP_REG_A2];
6299: dest[1] = dsp_core.registers[DSP_REG_A1];
6300: dest[2] = dsp_core.registers[DSP_REG_A0];
6301: newsr = dsp_add56(source, dest);
6302:
6303: dsp_core.registers[DSP_REG_A2] = dest[0];
6304: dsp_core.registers[DSP_REG_A1] = dest[1];
6305: dsp_core.registers[DSP_REG_A0] = dest[2];
6306:
6307: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6308:
6309: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6310: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6311: }
6312:
6313: static void dsp_mac_m_x1_y0_a(void)
6314: {
6315: Uint32 source[3], dest[3];
6316: Uint16 newsr;
6317:
6318: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6319:
6320: dest[0] = dsp_core.registers[DSP_REG_A2];
6321: dest[1] = dsp_core.registers[DSP_REG_A1];
6322: dest[2] = dsp_core.registers[DSP_REG_A0];
6323: newsr = dsp_add56(source, dest);
6324:
6325: dsp_core.registers[DSP_REG_A2] = dest[0];
6326: dsp_core.registers[DSP_REG_A1] = dest[1];
6327: dsp_core.registers[DSP_REG_A0] = dest[2];
6328:
6329: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6330:
6331: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6332: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6333: }
6334:
6335: static void dsp_mac_p_x1_y0_b(void)
6336: {
6337: Uint32 source[3], dest[3];
6338: Uint16 newsr;
6339:
6340: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6341:
6342: dest[0] = dsp_core.registers[DSP_REG_B2];
6343: dest[1] = dsp_core.registers[DSP_REG_B1];
6344: dest[2] = dsp_core.registers[DSP_REG_B0];
6345: newsr = dsp_add56(source, dest);
6346:
6347: dsp_core.registers[DSP_REG_B2] = dest[0];
6348: dsp_core.registers[DSP_REG_B1] = dest[1];
6349: dsp_core.registers[DSP_REG_B0] = dest[2];
6350:
6351: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6352:
6353: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6354: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6355: }
6356:
6357: static void dsp_mac_m_x1_y0_b(void)
6358: {
6359: Uint32 source[3], dest[3];
6360: Uint16 newsr;
6361:
6362: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6363:
6364: dest[0] = dsp_core.registers[DSP_REG_B2];
6365: dest[1] = dsp_core.registers[DSP_REG_B1];
6366: dest[2] = dsp_core.registers[DSP_REG_B0];
6367: newsr = dsp_add56(source, dest);
6368:
6369: dsp_core.registers[DSP_REG_B2] = dest[0];
6370: dsp_core.registers[DSP_REG_B1] = dest[1];
6371: dsp_core.registers[DSP_REG_B0] = dest[2];
6372:
6373: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6374:
6375: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6376: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6377: }
6378:
6379: static void dsp_mac_p_y1_x1_a(void)
6380: {
6381: Uint32 source[3], dest[3];
6382: Uint16 newsr;
6383:
6384: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6385:
6386: dest[0] = dsp_core.registers[DSP_REG_A2];
6387: dest[1] = dsp_core.registers[DSP_REG_A1];
6388: dest[2] = dsp_core.registers[DSP_REG_A0];
6389: newsr = dsp_add56(source, dest);
6390:
6391: dsp_core.registers[DSP_REG_A2] = dest[0];
6392: dsp_core.registers[DSP_REG_A1] = dest[1];
6393: dsp_core.registers[DSP_REG_A0] = dest[2];
6394:
6395: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6396:
6397: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6398: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6399: }
6400:
6401: static void dsp_mac_m_y1_x1_a(void)
6402: {
6403: Uint32 source[3], dest[3];
6404: Uint16 newsr;
6405:
6406: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6407:
6408: dest[0] = dsp_core.registers[DSP_REG_A2];
6409: dest[1] = dsp_core.registers[DSP_REG_A1];
6410: dest[2] = dsp_core.registers[DSP_REG_A0];
6411: newsr = dsp_add56(source, dest);
6412:
6413: dsp_core.registers[DSP_REG_A2] = dest[0];
6414: dsp_core.registers[DSP_REG_A1] = dest[1];
6415: dsp_core.registers[DSP_REG_A0] = dest[2];
6416:
6417: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6418:
6419: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6420: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6421: }
6422:
6423: static void dsp_mac_p_y1_x1_b(void)
6424: {
6425: Uint32 source[3], dest[3];
6426: Uint16 newsr;
6427:
6428: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6429:
6430: dest[0] = dsp_core.registers[DSP_REG_B2];
6431: dest[1] = dsp_core.registers[DSP_REG_B1];
6432: dest[2] = dsp_core.registers[DSP_REG_B0];
6433: newsr = dsp_add56(source, dest);
6434:
6435: dsp_core.registers[DSP_REG_B2] = dest[0];
6436: dsp_core.registers[DSP_REG_B1] = dest[1];
6437: dsp_core.registers[DSP_REG_B0] = dest[2];
6438:
6439: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6440:
6441: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6442: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6443: }
6444:
6445: static void dsp_mac_m_y1_x1_b(void)
6446: {
6447: Uint32 source[3], dest[3];
6448: Uint16 newsr;
6449:
6450: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6451:
6452: dest[0] = dsp_core.registers[DSP_REG_B2];
6453: dest[1] = dsp_core.registers[DSP_REG_B1];
6454: dest[2] = dsp_core.registers[DSP_REG_B0];
6455: newsr = dsp_add56(source, dest);
6456:
6457: dsp_core.registers[DSP_REG_B2] = dest[0];
6458: dsp_core.registers[DSP_REG_B1] = dest[1];
6459: dsp_core.registers[DSP_REG_B0] = dest[2];
6460:
6461: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6462:
6463: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6464: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6465: }
6466:
6467: static void dsp_macr_p_x0_x0_a(void)
6468: {
6469: Uint32 source[3], dest[3];
6470: Uint16 newsr;
6471:
6472: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6473:
6474: dest[0] = dsp_core.registers[DSP_REG_A2];
6475: dest[1] = dsp_core.registers[DSP_REG_A1];
6476: dest[2] = dsp_core.registers[DSP_REG_A0];
6477: newsr = dsp_add56(source, dest);
6478:
6479: dsp_rnd56(dest);
6480:
6481: dsp_core.registers[DSP_REG_A2] = dest[0];
6482: dsp_core.registers[DSP_REG_A1] = dest[1];
6483: dsp_core.registers[DSP_REG_A0] = dest[2];
6484:
6485: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6486:
6487: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6488: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6489: }
6490:
6491: static void dsp_macr_m_x0_x0_a(void)
6492: {
6493: Uint32 source[3], dest[3];
6494: Uint16 newsr;
6495:
6496: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6497:
6498: dest[0] = dsp_core.registers[DSP_REG_A2];
6499: dest[1] = dsp_core.registers[DSP_REG_A1];
6500: dest[2] = dsp_core.registers[DSP_REG_A0];
6501: newsr = dsp_add56(source, dest);
6502:
6503: dsp_rnd56(dest);
6504:
6505: dsp_core.registers[DSP_REG_A2] = dest[0];
6506: dsp_core.registers[DSP_REG_A1] = dest[1];
6507: dsp_core.registers[DSP_REG_A0] = dest[2];
6508:
6509: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6510:
6511: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6512: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6513: }
6514: static void dsp_macr_p_x0_x0_b(void)
6515: {
6516: Uint32 source[3], dest[3];
6517: Uint16 newsr;
6518:
6519: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6520:
6521: dest[0] = dsp_core.registers[DSP_REG_B2];
6522: dest[1] = dsp_core.registers[DSP_REG_B1];
6523: dest[2] = dsp_core.registers[DSP_REG_B0];
6524: newsr = dsp_add56(source, dest);
6525:
6526: dsp_rnd56(dest);
6527:
6528: dsp_core.registers[DSP_REG_B2] = dest[0];
6529: dsp_core.registers[DSP_REG_B1] = dest[1];
6530: dsp_core.registers[DSP_REG_B0] = dest[2];
6531:
6532: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6533:
6534: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6535: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6536: }
6537:
6538: static void dsp_macr_m_x0_x0_b(void)
6539: {
6540: Uint32 source[3], dest[3];
6541: Uint16 newsr;
6542:
6543: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6544:
6545: dest[0] = dsp_core.registers[DSP_REG_B2];
6546: dest[1] = dsp_core.registers[DSP_REG_B1];
6547: dest[2] = dsp_core.registers[DSP_REG_B0];
6548: newsr = dsp_add56(source, dest);
6549:
6550: dsp_rnd56(dest);
6551:
6552: dsp_core.registers[DSP_REG_B2] = dest[0];
6553: dsp_core.registers[DSP_REG_B1] = dest[1];
6554: dsp_core.registers[DSP_REG_B0] = dest[2];
6555:
6556: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6557:
6558: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6559: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6560: }
6561:
6562: static void dsp_macr_p_y0_y0_a(void)
6563: {
6564: Uint32 source[3], dest[3];
6565: Uint16 newsr;
6566:
6567: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6568:
6569: dest[0] = dsp_core.registers[DSP_REG_A2];
6570: dest[1] = dsp_core.registers[DSP_REG_A1];
6571: dest[2] = dsp_core.registers[DSP_REG_A0];
6572: newsr = dsp_add56(source, dest);
6573:
6574: dsp_rnd56(dest);
6575:
6576: dsp_core.registers[DSP_REG_A2] = dest[0];
6577: dsp_core.registers[DSP_REG_A1] = dest[1];
6578: dsp_core.registers[DSP_REG_A0] = dest[2];
6579:
6580: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6581:
6582: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6583: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6584: }
6585:
6586: static void dsp_macr_m_y0_y0_a(void)
6587: {
6588: Uint32 source[3], dest[3];
6589: Uint16 newsr;
6590:
6591: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6592:
6593: dest[0] = dsp_core.registers[DSP_REG_A2];
6594: dest[1] = dsp_core.registers[DSP_REG_A1];
6595: dest[2] = dsp_core.registers[DSP_REG_A0];
6596: newsr = dsp_add56(source, dest);
6597:
6598: dsp_rnd56(dest);
6599:
6600: dsp_core.registers[DSP_REG_A2] = dest[0];
6601: dsp_core.registers[DSP_REG_A1] = dest[1];
6602: dsp_core.registers[DSP_REG_A0] = dest[2];
6603:
6604: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6605:
6606: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6607: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6608: }
6609: static void dsp_macr_p_y0_y0_b(void)
6610: {
6611: Uint32 source[3], dest[3];
6612: Uint16 newsr;
6613:
6614: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6615:
6616: dest[0] = dsp_core.registers[DSP_REG_B2];
6617: dest[1] = dsp_core.registers[DSP_REG_B1];
6618: dest[2] = dsp_core.registers[DSP_REG_B0];
6619: newsr = dsp_add56(source, dest);
6620:
6621: dsp_rnd56(dest);
6622:
6623: dsp_core.registers[DSP_REG_B2] = dest[0];
6624: dsp_core.registers[DSP_REG_B1] = dest[1];
6625: dsp_core.registers[DSP_REG_B0] = dest[2];
6626:
6627: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6628:
6629: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6630: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6631: }
6632:
6633: static void dsp_macr_m_y0_y0_b(void)
6634: {
6635: Uint32 source[3], dest[3];
6636: Uint16 newsr;
6637:
6638: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6639:
6640: dest[0] = dsp_core.registers[DSP_REG_B2];
6641: dest[1] = dsp_core.registers[DSP_REG_B1];
6642: dest[2] = dsp_core.registers[DSP_REG_B0];
6643: newsr = dsp_add56(source, dest);
6644:
6645: dsp_rnd56(dest);
6646:
6647: dsp_core.registers[DSP_REG_B2] = dest[0];
6648: dsp_core.registers[DSP_REG_B1] = dest[1];
6649: dsp_core.registers[DSP_REG_B0] = dest[2];
6650:
6651: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6652:
6653: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6654: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6655: }
6656:
6657: static void dsp_macr_p_x1_x0_a(void)
6658: {
6659: Uint32 source[3], dest[3];
6660: Uint16 newsr;
6661:
6662: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6663:
6664: dest[0] = dsp_core.registers[DSP_REG_A2];
6665: dest[1] = dsp_core.registers[DSP_REG_A1];
6666: dest[2] = dsp_core.registers[DSP_REG_A0];
6667: newsr = dsp_add56(source, dest);
6668:
6669: dsp_rnd56(dest);
6670:
6671: dsp_core.registers[DSP_REG_A2] = dest[0];
6672: dsp_core.registers[DSP_REG_A1] = dest[1];
6673: dsp_core.registers[DSP_REG_A0] = dest[2];
6674:
6675: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6676:
6677: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6678: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6679: }
6680:
6681: static void dsp_macr_m_x1_x0_a(void)
6682: {
6683: Uint32 source[3], dest[3];
6684: Uint16 newsr;
6685:
6686: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6687:
6688: dest[0] = dsp_core.registers[DSP_REG_A2];
6689: dest[1] = dsp_core.registers[DSP_REG_A1];
6690: dest[2] = dsp_core.registers[DSP_REG_A0];
6691: newsr = dsp_add56(source, dest);
6692:
6693: dsp_rnd56(dest);
6694:
6695: dsp_core.registers[DSP_REG_A2] = dest[0];
6696: dsp_core.registers[DSP_REG_A1] = dest[1];
6697: dsp_core.registers[DSP_REG_A0] = dest[2];
6698:
6699: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6700:
6701: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6702: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6703: }
6704:
6705: static void dsp_macr_p_x1_x0_b(void)
6706: {
6707: Uint32 source[3], dest[3];
6708: Uint16 newsr;
6709:
6710: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6711:
6712: dest[0] = dsp_core.registers[DSP_REG_B2];
6713: dest[1] = dsp_core.registers[DSP_REG_B1];
6714: dest[2] = dsp_core.registers[DSP_REG_B0];
6715: newsr = dsp_add56(source, dest);
6716:
6717: dsp_rnd56(dest);
6718:
6719: dsp_core.registers[DSP_REG_B2] = dest[0];
6720: dsp_core.registers[DSP_REG_B1] = dest[1];
6721: dsp_core.registers[DSP_REG_B0] = dest[2];
6722:
6723: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6724:
6725: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6726: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6727: }
6728:
6729: static void dsp_macr_m_x1_x0_b(void)
6730: {
6731: Uint32 source[3], dest[3];
6732: Uint16 newsr;
6733:
6734: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6735:
6736: dest[0] = dsp_core.registers[DSP_REG_B2];
6737: dest[1] = dsp_core.registers[DSP_REG_B1];
6738: dest[2] = dsp_core.registers[DSP_REG_B0];
6739: newsr = dsp_add56(source, dest);
6740:
6741: dsp_rnd56(dest);
6742:
6743: dsp_core.registers[DSP_REG_B2] = dest[0];
6744: dsp_core.registers[DSP_REG_B1] = dest[1];
6745: dsp_core.registers[DSP_REG_B0] = dest[2];
6746:
6747: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6748:
6749: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6750: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6751: }
6752:
6753: static void dsp_macr_p_y1_y0_a(void)
6754: {
6755: Uint32 source[3], dest[3];
6756: Uint16 newsr;
6757:
6758: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6759:
6760: dest[0] = dsp_core.registers[DSP_REG_A2];
6761: dest[1] = dsp_core.registers[DSP_REG_A1];
6762: dest[2] = dsp_core.registers[DSP_REG_A0];
6763: newsr = dsp_add56(source, dest);
6764:
6765: dsp_rnd56(dest);
6766:
6767: dsp_core.registers[DSP_REG_A2] = dest[0];
6768: dsp_core.registers[DSP_REG_A1] = dest[1];
6769: dsp_core.registers[DSP_REG_A0] = dest[2];
6770:
6771: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6772:
6773: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6774: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6775: }
6776:
6777: static void dsp_macr_m_y1_y0_a(void)
6778: {
6779: Uint32 source[3], dest[3];
6780: Uint16 newsr;
6781:
6782: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6783:
6784: dest[0] = dsp_core.registers[DSP_REG_A2];
6785: dest[1] = dsp_core.registers[DSP_REG_A1];
6786: dest[2] = dsp_core.registers[DSP_REG_A0];
6787: newsr = dsp_add56(source, dest);
6788:
6789: dsp_rnd56(dest);
6790:
6791: dsp_core.registers[DSP_REG_A2] = dest[0];
6792: dsp_core.registers[DSP_REG_A1] = dest[1];
6793: dsp_core.registers[DSP_REG_A0] = dest[2];
6794:
6795: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6796:
6797: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6798: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6799: }
6800:
6801: static void dsp_macr_p_y1_y0_b(void)
6802: {
6803: Uint32 source[3], dest[3];
6804: Uint16 newsr;
6805:
6806: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6807:
6808: dest[0] = dsp_core.registers[DSP_REG_B2];
6809: dest[1] = dsp_core.registers[DSP_REG_B1];
6810: dest[2] = dsp_core.registers[DSP_REG_B0];
6811: newsr = dsp_add56(source, dest);
6812:
6813: dsp_rnd56(dest);
6814:
6815: dsp_core.registers[DSP_REG_B2] = dest[0];
6816: dsp_core.registers[DSP_REG_B1] = dest[1];
6817: dsp_core.registers[DSP_REG_B0] = dest[2];
6818:
6819: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6820:
6821: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6822: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6823: }
6824:
6825: static void dsp_macr_m_y1_y0_b(void)
6826: {
6827: Uint32 source[3], dest[3];
6828: Uint16 newsr;
6829:
6830: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6831:
6832: dest[0] = dsp_core.registers[DSP_REG_B2];
6833: dest[1] = dsp_core.registers[DSP_REG_B1];
6834: dest[2] = dsp_core.registers[DSP_REG_B0];
6835: newsr = dsp_add56(source, dest);
6836:
6837: dsp_rnd56(dest);
6838:
6839: dsp_core.registers[DSP_REG_B2] = dest[0];
6840: dsp_core.registers[DSP_REG_B1] = dest[1];
6841: dsp_core.registers[DSP_REG_B0] = dest[2];
6842:
6843: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6844:
6845: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6846: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6847: }
6848:
6849: static void dsp_macr_p_x0_y1_a(void)
6850: {
6851: Uint32 source[3], dest[3];
6852: Uint16 newsr;
6853:
6854: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6855:
6856: dest[0] = dsp_core.registers[DSP_REG_A2];
6857: dest[1] = dsp_core.registers[DSP_REG_A1];
6858: dest[2] = dsp_core.registers[DSP_REG_A0];
6859: newsr = dsp_add56(source, dest);
6860:
6861: dsp_rnd56(dest);
6862:
6863: dsp_core.registers[DSP_REG_A2] = dest[0];
6864: dsp_core.registers[DSP_REG_A1] = dest[1];
6865: dsp_core.registers[DSP_REG_A0] = dest[2];
6866:
6867: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6868:
6869: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6870: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6871: }
6872:
6873: static void dsp_macr_m_x0_y1_a(void)
6874: {
6875: Uint32 source[3], dest[3];
6876: Uint16 newsr;
6877:
6878: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6879:
6880: dest[0] = dsp_core.registers[DSP_REG_A2];
6881: dest[1] = dsp_core.registers[DSP_REG_A1];
6882: dest[2] = dsp_core.registers[DSP_REG_A0];
6883: newsr = dsp_add56(source, dest);
6884:
6885: dsp_rnd56(dest);
6886:
6887: dsp_core.registers[DSP_REG_A2] = dest[0];
6888: dsp_core.registers[DSP_REG_A1] = dest[1];
6889: dsp_core.registers[DSP_REG_A0] = dest[2];
6890:
6891: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6892:
6893: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6894: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6895: }
6896:
6897: static void dsp_macr_p_x0_y1_b(void)
6898: {
6899: Uint32 source[3], dest[3];
6900: Uint16 newsr;
6901:
6902: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6903:
6904: dest[0] = dsp_core.registers[DSP_REG_B2];
6905: dest[1] = dsp_core.registers[DSP_REG_B1];
6906: dest[2] = dsp_core.registers[DSP_REG_B0];
6907: newsr = dsp_add56(source, dest);
6908:
6909: dsp_rnd56(dest);
6910:
6911: dsp_core.registers[DSP_REG_B2] = dest[0];
6912: dsp_core.registers[DSP_REG_B1] = dest[1];
6913: dsp_core.registers[DSP_REG_B0] = dest[2];
6914:
6915: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6916:
6917: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6918: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6919: }
6920:
6921: static void dsp_macr_m_x0_y1_b(void)
6922: {
6923: Uint32 source[3], dest[3];
6924: Uint16 newsr;
6925:
6926: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6927:
6928: dest[0] = dsp_core.registers[DSP_REG_B2];
6929: dest[1] = dsp_core.registers[DSP_REG_B1];
6930: dest[2] = dsp_core.registers[DSP_REG_B0];
6931: newsr = dsp_add56(source, dest);
6932:
6933: dsp_rnd56(dest);
6934:
6935: dsp_core.registers[DSP_REG_B2] = dest[0];
6936: dsp_core.registers[DSP_REG_B1] = dest[1];
6937: dsp_core.registers[DSP_REG_B0] = dest[2];
6938:
6939: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6940:
6941: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6942: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6943: }
6944:
6945: static void dsp_macr_p_y0_x0_a(void)
6946: {
6947: Uint32 source[3], dest[3];
6948: Uint16 newsr;
6949:
6950: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6951:
6952: dest[0] = dsp_core.registers[DSP_REG_A2];
6953: dest[1] = dsp_core.registers[DSP_REG_A1];
6954: dest[2] = dsp_core.registers[DSP_REG_A0];
6955: newsr = dsp_add56(source, dest);
6956:
6957: dsp_rnd56(dest);
6958:
6959: dsp_core.registers[DSP_REG_A2] = dest[0];
6960: dsp_core.registers[DSP_REG_A1] = dest[1];
6961: dsp_core.registers[DSP_REG_A0] = dest[2];
6962:
6963: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6964:
6965: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6966: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6967: }
6968:
6969: static void dsp_macr_m_y0_x0_a(void)
6970: {
6971: Uint32 source[3], dest[3];
6972: Uint16 newsr;
6973:
6974: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6975:
6976: dest[0] = dsp_core.registers[DSP_REG_A2];
6977: dest[1] = dsp_core.registers[DSP_REG_A1];
6978: dest[2] = dsp_core.registers[DSP_REG_A0];
6979: newsr = dsp_add56(source, dest);
6980:
6981: dsp_rnd56(dest);
6982:
6983: dsp_core.registers[DSP_REG_A2] = dest[0];
6984: dsp_core.registers[DSP_REG_A1] = dest[1];
6985: dsp_core.registers[DSP_REG_A0] = dest[2];
6986:
6987: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6988:
6989: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6990: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6991: }
6992:
6993: static void dsp_macr_p_y0_x0_b(void)
6994: {
6995: Uint32 source[3], dest[3];
6996: Uint16 newsr;
6997:
6998: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6999:
7000: dest[0] = dsp_core.registers[DSP_REG_B2];
7001: dest[1] = dsp_core.registers[DSP_REG_B1];
7002: dest[2] = dsp_core.registers[DSP_REG_B0];
7003: newsr = dsp_add56(source, dest);
7004:
7005: dsp_rnd56(dest);
7006:
7007: dsp_core.registers[DSP_REG_B2] = dest[0];
7008: dsp_core.registers[DSP_REG_B1] = dest[1];
7009: dsp_core.registers[DSP_REG_B0] = dest[2];
7010:
7011: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7012:
7013: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7014: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7015: }
7016:
7017: static void dsp_macr_m_y0_x0_b(void)
7018: {
7019: Uint32 source[3], dest[3];
7020: Uint16 newsr;
7021:
7022: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7023:
7024: dest[0] = dsp_core.registers[DSP_REG_B2];
7025: dest[1] = dsp_core.registers[DSP_REG_B1];
7026: dest[2] = dsp_core.registers[DSP_REG_B0];
7027: newsr = dsp_add56(source, dest);
7028:
7029: dsp_rnd56(dest);
7030:
7031: dsp_core.registers[DSP_REG_B2] = dest[0];
7032: dsp_core.registers[DSP_REG_B1] = dest[1];
7033: dsp_core.registers[DSP_REG_B0] = dest[2];
7034:
7035: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7036:
7037: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7038: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7039: }
7040:
7041: static void dsp_macr_p_x1_y0_a(void)
7042: {
7043: Uint32 source[3], dest[3];
7044: Uint16 newsr;
7045:
7046: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7047:
7048: dest[0] = dsp_core.registers[DSP_REG_A2];
7049: dest[1] = dsp_core.registers[DSP_REG_A1];
7050: dest[2] = dsp_core.registers[DSP_REG_A0];
7051: newsr = dsp_add56(source, dest);
7052:
7053: dsp_rnd56(dest);
7054:
7055: dsp_core.registers[DSP_REG_A2] = dest[0];
7056: dsp_core.registers[DSP_REG_A1] = dest[1];
7057: dsp_core.registers[DSP_REG_A0] = dest[2];
7058:
7059: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7060:
7061: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7062: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7063: }
7064:
7065: static void dsp_macr_m_x1_y0_a(void)
7066: {
7067: Uint32 source[3], dest[3];
7068: Uint16 newsr;
7069:
7070: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7071:
7072: dest[0] = dsp_core.registers[DSP_REG_A2];
7073: dest[1] = dsp_core.registers[DSP_REG_A1];
7074: dest[2] = dsp_core.registers[DSP_REG_A0];
7075: newsr = dsp_add56(source, dest);
7076:
7077: dsp_rnd56(dest);
7078:
7079: dsp_core.registers[DSP_REG_A2] = dest[0];
7080: dsp_core.registers[DSP_REG_A1] = dest[1];
7081: dsp_core.registers[DSP_REG_A0] = dest[2];
7082:
7083: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7084:
7085: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7086: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7087: }
7088:
7089: static void dsp_macr_p_x1_y0_b(void)
7090: {
7091: Uint32 source[3], dest[3];
7092: Uint16 newsr;
7093:
7094: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7095:
7096: dest[0] = dsp_core.registers[DSP_REG_B2];
7097: dest[1] = dsp_core.registers[DSP_REG_B1];
7098: dest[2] = dsp_core.registers[DSP_REG_B0];
7099: newsr = dsp_add56(source, dest);
7100:
7101: dsp_rnd56(dest);
7102:
7103: dsp_core.registers[DSP_REG_B2] = dest[0];
7104: dsp_core.registers[DSP_REG_B1] = dest[1];
7105: dsp_core.registers[DSP_REG_B0] = dest[2];
7106:
7107: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7108:
7109: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7110: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7111: }
7112:
7113: static void dsp_macr_m_x1_y0_b(void)
7114: {
7115: Uint32 source[3], dest[3];
7116: Uint16 newsr;
7117:
7118: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7119:
7120: dest[0] = dsp_core.registers[DSP_REG_B2];
7121: dest[1] = dsp_core.registers[DSP_REG_B1];
7122: dest[2] = dsp_core.registers[DSP_REG_B0];
7123: newsr = dsp_add56(source, dest);
7124:
7125: dsp_rnd56(dest);
7126:
7127: dsp_core.registers[DSP_REG_B2] = dest[0];
7128: dsp_core.registers[DSP_REG_B1] = dest[1];
7129: dsp_core.registers[DSP_REG_B0] = dest[2];
7130:
7131: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7132:
7133: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7134: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7135: }
7136:
7137: static void dsp_macr_p_y1_x1_a(void)
7138: {
7139: Uint32 source[3], dest[3];
7140: Uint16 newsr;
7141:
7142: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7143:
7144: dest[0] = dsp_core.registers[DSP_REG_A2];
7145: dest[1] = dsp_core.registers[DSP_REG_A1];
7146: dest[2] = dsp_core.registers[DSP_REG_A0];
7147: newsr = dsp_add56(source, dest);
7148:
7149: dsp_rnd56(dest);
7150:
7151: dsp_core.registers[DSP_REG_A2] = dest[0];
7152: dsp_core.registers[DSP_REG_A1] = dest[1];
7153: dsp_core.registers[DSP_REG_A0] = dest[2];
7154:
7155: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7156:
7157: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7158: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7159: }
7160:
7161: static void dsp_macr_m_y1_x1_a(void)
7162: {
7163: Uint32 source[3], dest[3];
7164: Uint16 newsr;
7165:
7166: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7167:
7168: dest[0] = dsp_core.registers[DSP_REG_A2];
7169: dest[1] = dsp_core.registers[DSP_REG_A1];
7170: dest[2] = dsp_core.registers[DSP_REG_A0];
7171: newsr = dsp_add56(source, dest);
7172:
7173: dsp_rnd56(dest);
7174:
7175: dsp_core.registers[DSP_REG_A2] = dest[0];
7176: dsp_core.registers[DSP_REG_A1] = dest[1];
7177: dsp_core.registers[DSP_REG_A0] = dest[2];
7178:
7179: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7180:
7181: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7182: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7183: }
7184:
7185: static void dsp_macr_p_y1_x1_b(void)
7186: {
7187: Uint32 source[3], dest[3];
7188: Uint16 newsr;
7189:
7190: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7191:
7192: dest[0] = dsp_core.registers[DSP_REG_B2];
7193: dest[1] = dsp_core.registers[DSP_REG_B1];
7194: dest[2] = dsp_core.registers[DSP_REG_B0];
7195: newsr = dsp_add56(source, dest);
7196:
7197: dsp_rnd56(dest);
7198:
7199: dsp_core.registers[DSP_REG_B2] = dest[0];
7200: dsp_core.registers[DSP_REG_B1] = dest[1];
7201: dsp_core.registers[DSP_REG_B0] = dest[2];
7202:
7203: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7204:
7205: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7206: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7207: }
7208:
7209: static void dsp_macr_m_y1_x1_b(void)
7210: {
7211: Uint32 source[3], dest[3];
7212: Uint16 newsr;
7213:
7214: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7215:
7216: dest[0] = dsp_core.registers[DSP_REG_B2];
7217: dest[1] = dsp_core.registers[DSP_REG_B1];
7218: dest[2] = dsp_core.registers[DSP_REG_B0];
7219: newsr = dsp_add56(source, dest);
7220:
7221: dsp_rnd56(dest);
7222:
7223: dsp_core.registers[DSP_REG_B2] = dest[0];
7224: dsp_core.registers[DSP_REG_B1] = dest[1];
7225: dsp_core.registers[DSP_REG_B0] = dest[2];
7226:
7227: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7228:
7229: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7230: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7231: }
7232:
7233:
7234: static void dsp_move(void)
7235: {
7236: /* move instruction inside alu opcodes
7237: taken care of by parallel move dispatcher */
7238: }
7239:
7240: static void dsp_mpy_p_x0_x0_a(void)
7241: {
7242: Uint32 source[3];
7243:
7244: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7245:
7246: dsp_core.registers[DSP_REG_A2] = source[0];
7247: dsp_core.registers[DSP_REG_A1] = source[1];
7248: dsp_core.registers[DSP_REG_A0] = source[2];
7249:
7250: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7251: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7252: }
7253:
7254: static void dsp_mpy_m_x0_x0_a(void)
7255: {
7256: Uint32 source[3];
7257:
7258: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7259:
7260: dsp_core.registers[DSP_REG_A2] = source[0];
7261: dsp_core.registers[DSP_REG_A1] = source[1];
7262: dsp_core.registers[DSP_REG_A0] = source[2];
7263:
7264: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7265: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7266: }
7267:
7268: static void dsp_mpy_p_x0_x0_b(void)
7269: {
7270: Uint32 source[3];
7271:
7272: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7273:
7274: dsp_core.registers[DSP_REG_B2] = source[0];
7275: dsp_core.registers[DSP_REG_B1] = source[1];
7276: dsp_core.registers[DSP_REG_B0] = source[2];
7277:
7278: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7279: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7280: }
7281:
7282: static void dsp_mpy_m_x0_x0_b(void)
7283: {
7284: Uint32 source[3];
7285:
7286:
7287: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7288:
7289: dsp_core.registers[DSP_REG_B2] = source[0];
7290: dsp_core.registers[DSP_REG_B1] = source[1];
7291: dsp_core.registers[DSP_REG_B0] = source[2];
7292:
7293: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7294: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7295: }
7296:
7297: static void dsp_mpy_p_y0_y0_a(void)
7298: {
7299: Uint32 source[3];
7300:
7301: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7302:
7303: dsp_core.registers[DSP_REG_A2] = source[0];
7304: dsp_core.registers[DSP_REG_A1] = source[1];
7305: dsp_core.registers[DSP_REG_A0] = source[2];
7306:
7307: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7308: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7309: }
7310:
7311: static void dsp_mpy_m_y0_y0_a(void)
7312: {
7313: Uint32 source[3];
7314:
7315: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7316:
7317: dsp_core.registers[DSP_REG_A2] = source[0];
7318: dsp_core.registers[DSP_REG_A1] = source[1];
7319: dsp_core.registers[DSP_REG_A0] = source[2];
7320:
7321: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7322: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7323: }
7324:
7325: static void dsp_mpy_p_y0_y0_b(void)
7326: {
7327: Uint32 source[3];
7328:
7329: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7330:
7331: dsp_core.registers[DSP_REG_B2] = source[0];
7332: dsp_core.registers[DSP_REG_B1] = source[1];
7333: dsp_core.registers[DSP_REG_B0] = source[2];
7334:
7335: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7336: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7337: }
7338:
7339: static void dsp_mpy_m_y0_y0_b(void)
7340: {
7341: Uint32 source[3];
7342:
7343: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7344:
7345: dsp_core.registers[DSP_REG_B2] = source[0];
7346: dsp_core.registers[DSP_REG_B1] = source[1];
7347: dsp_core.registers[DSP_REG_B0] = source[2];
7348:
7349: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7350: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7351: }
7352:
7353: static void dsp_mpy_p_x1_x0_a(void)
7354: {
7355: Uint32 source[3];
7356:
7357: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7358:
7359: dsp_core.registers[DSP_REG_A2] = source[0];
7360: dsp_core.registers[DSP_REG_A1] = source[1];
7361: dsp_core.registers[DSP_REG_A0] = source[2];
7362:
7363: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7364: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7365: }
7366:
7367: static void dsp_mpy_m_x1_x0_a(void)
7368: {
7369: Uint32 source[3];
7370:
7371: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7372:
7373: dsp_core.registers[DSP_REG_A2] = source[0];
7374: dsp_core.registers[DSP_REG_A1] = source[1];
7375: dsp_core.registers[DSP_REG_A0] = source[2];
7376:
7377: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7378: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7379: }
7380:
7381: static void dsp_mpy_p_x1_x0_b(void)
7382: {
7383: Uint32 source[3];
7384:
7385: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7386:
7387: dsp_core.registers[DSP_REG_B2] = source[0];
7388: dsp_core.registers[DSP_REG_B1] = source[1];
7389: dsp_core.registers[DSP_REG_B0] = source[2];
7390:
7391: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7392: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7393: }
7394:
7395: static void dsp_mpy_m_x1_x0_b(void)
7396: {
7397: Uint32 source[3];
7398:
7399: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7400:
7401: dsp_core.registers[DSP_REG_B2] = source[0];
7402: dsp_core.registers[DSP_REG_B1] = source[1];
7403: dsp_core.registers[DSP_REG_B0] = source[2];
7404:
7405: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7406: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7407: }
7408:
7409: static void dsp_mpy_p_y1_y0_a(void)
7410: {
7411: Uint32 source[3];
7412:
7413: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7414:
7415: dsp_core.registers[DSP_REG_A2] = source[0];
7416: dsp_core.registers[DSP_REG_A1] = source[1];
7417: dsp_core.registers[DSP_REG_A0] = source[2];
7418:
7419: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7420: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7421: }
7422:
7423: static void dsp_mpy_m_y1_y0_a(void)
7424: {
7425: Uint32 source[3];
7426:
7427: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7428:
7429: dsp_core.registers[DSP_REG_A2] = source[0];
7430: dsp_core.registers[DSP_REG_A1] = source[1];
7431: dsp_core.registers[DSP_REG_A0] = source[2];
7432:
7433: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7434: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7435: }
7436:
7437: static void dsp_mpy_p_y1_y0_b(void)
7438: {
7439: Uint32 source[3];
7440:
7441: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7442:
7443: dsp_core.registers[DSP_REG_B2] = source[0];
7444: dsp_core.registers[DSP_REG_B1] = source[1];
7445: dsp_core.registers[DSP_REG_B0] = source[2];
7446:
7447: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7448: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7449: }
7450:
7451: static void dsp_mpy_m_y1_y0_b(void)
7452: {
7453: Uint32 source[3];
7454:
7455: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7456:
7457: dsp_core.registers[DSP_REG_B2] = source[0];
7458: dsp_core.registers[DSP_REG_B1] = source[1];
7459: dsp_core.registers[DSP_REG_B0] = source[2];
7460:
7461: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7462: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7463: }
7464:
7465: static void dsp_mpy_p_x0_y1_a(void)
7466: {
7467: Uint32 source[3];
7468:
7469: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7470:
7471: dsp_core.registers[DSP_REG_A2] = source[0];
7472: dsp_core.registers[DSP_REG_A1] = source[1];
7473: dsp_core.registers[DSP_REG_A0] = source[2];
7474:
7475: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7476: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7477: }
7478:
7479: static void dsp_mpy_m_x0_y1_a(void)
7480: {
7481: Uint32 source[3];
7482:
7483: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7484:
7485: dsp_core.registers[DSP_REG_A2] = source[0];
7486: dsp_core.registers[DSP_REG_A1] = source[1];
7487: dsp_core.registers[DSP_REG_A0] = source[2];
7488:
7489: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7490: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7491: }
7492:
7493: static void dsp_mpy_p_x0_y1_b(void)
7494: {
7495: Uint32 source[3];
7496:
7497: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7498:
7499: dsp_core.registers[DSP_REG_B2] = source[0];
7500: dsp_core.registers[DSP_REG_B1] = source[1];
7501: dsp_core.registers[DSP_REG_B0] = source[2];
7502:
7503: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7504: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7505: }
7506:
7507: static void dsp_mpy_m_x0_y1_b(void)
7508: {
7509: Uint32 source[3];
7510:
7511: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7512:
7513: dsp_core.registers[DSP_REG_B2] = source[0];
7514: dsp_core.registers[DSP_REG_B1] = source[1];
7515: dsp_core.registers[DSP_REG_B0] = source[2];
7516:
7517: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7518: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7519: }
7520:
7521: static void dsp_mpy_p_y0_x0_a(void)
7522: {
7523: Uint32 source[3];
7524:
7525: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7526:
7527: dsp_core.registers[DSP_REG_A2] = source[0];
7528: dsp_core.registers[DSP_REG_A1] = source[1];
7529: dsp_core.registers[DSP_REG_A0] = source[2];
7530:
7531: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7532: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7533: }
7534:
7535: static void dsp_mpy_m_y0_x0_a(void)
7536: {
7537: Uint32 source[3];
7538:
7539: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7540:
7541: dsp_core.registers[DSP_REG_A2] = source[0];
7542: dsp_core.registers[DSP_REG_A1] = source[1];
7543: dsp_core.registers[DSP_REG_A0] = source[2];
7544:
7545: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7546: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7547: }
7548:
7549: static void dsp_mpy_p_y0_x0_b(void)
7550: {
7551: Uint32 source[3];
7552:
7553: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7554:
7555: dsp_core.registers[DSP_REG_B2] = source[0];
7556: dsp_core.registers[DSP_REG_B1] = source[1];
7557: dsp_core.registers[DSP_REG_B0] = source[2];
7558:
7559: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7560: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7561: }
7562:
7563: static void dsp_mpy_m_y0_x0_b(void)
7564: {
7565: Uint32 source[3];
7566:
7567: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7568:
7569: dsp_core.registers[DSP_REG_B2] = source[0];
7570: dsp_core.registers[DSP_REG_B1] = source[1];
7571: dsp_core.registers[DSP_REG_B0] = source[2];
7572:
7573: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7574: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7575: }
7576:
7577: static void dsp_mpy_p_x1_y0_a(void)
7578: {
7579: Uint32 source[3];
7580:
7581: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7582:
7583: dsp_core.registers[DSP_REG_A2] = source[0];
7584: dsp_core.registers[DSP_REG_A1] = source[1];
7585: dsp_core.registers[DSP_REG_A0] = source[2];
7586:
7587: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7588: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7589: }
7590:
7591: static void dsp_mpy_m_x1_y0_a(void)
7592: {
7593: Uint32 source[3];
7594:
7595: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7596:
7597: dsp_core.registers[DSP_REG_A2] = source[0];
7598: dsp_core.registers[DSP_REG_A1] = source[1];
7599: dsp_core.registers[DSP_REG_A0] = source[2];
7600:
7601: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7602: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7603: }
7604:
7605: static void dsp_mpy_p_x1_y0_b(void)
7606: {
7607: Uint32 source[3];
7608:
7609: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7610:
7611: dsp_core.registers[DSP_REG_B2] = source[0];
7612: dsp_core.registers[DSP_REG_B1] = source[1];
7613: dsp_core.registers[DSP_REG_B0] = source[2];
7614:
7615: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7616: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7617: }
7618:
7619: static void dsp_mpy_m_x1_y0_b(void)
7620: {
7621: Uint32 source[3];
7622:
7623: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7624:
7625: dsp_core.registers[DSP_REG_B2] = source[0];
7626: dsp_core.registers[DSP_REG_B1] = source[1];
7627: dsp_core.registers[DSP_REG_B0] = source[2];
7628:
7629: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7630: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7631: }
7632:
7633: static void dsp_mpy_p_y1_x1_a(void)
7634: {
7635: Uint32 source[3];
7636:
7637: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7638:
7639: dsp_core.registers[DSP_REG_A2] = source[0];
7640: dsp_core.registers[DSP_REG_A1] = source[1];
7641: dsp_core.registers[DSP_REG_A0] = source[2];
7642:
7643: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7644: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7645: }
7646:
7647: static void dsp_mpy_m_y1_x1_a(void)
7648: {
7649: Uint32 source[3];
7650:
7651: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7652:
7653: dsp_core.registers[DSP_REG_A2] = source[0];
7654: dsp_core.registers[DSP_REG_A1] = source[1];
7655: dsp_core.registers[DSP_REG_A0] = source[2];
7656:
7657: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7658: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7659: }
7660:
7661: static void dsp_mpy_p_y1_x1_b(void)
7662: {
7663: Uint32 source[3];
7664:
7665: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7666:
7667: dsp_core.registers[DSP_REG_B2] = source[0];
7668: dsp_core.registers[DSP_REG_B1] = source[1];
7669: dsp_core.registers[DSP_REG_B0] = source[2];
7670:
7671: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7672: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7673: }
7674:
7675: static void dsp_mpy_m_y1_x1_b(void)
7676: {
7677: Uint32 source[3];
7678:
7679: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7680:
7681: dsp_core.registers[DSP_REG_B2] = source[0];
7682: dsp_core.registers[DSP_REG_B1] = source[1];
7683: dsp_core.registers[DSP_REG_B0] = source[2];
7684:
7685: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7686: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7687: }
7688:
7689: static void dsp_mpyr_p_x0_x0_a(void)
7690: {
7691: Uint32 source[3];
7692:
7693: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7694: dsp_rnd56(source);
7695:
7696: dsp_core.registers[DSP_REG_A2] = source[0];
7697: dsp_core.registers[DSP_REG_A1] = source[1];
7698: dsp_core.registers[DSP_REG_A0] = source[2];
7699:
7700: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7701: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7702: }
7703:
7704: static void dsp_mpyr_m_x0_x0_a(void)
7705: {
7706: Uint32 source[3];
7707:
7708: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7709: dsp_rnd56(source);
7710:
7711: dsp_core.registers[DSP_REG_A2] = source[0];
7712: dsp_core.registers[DSP_REG_A1] = source[1];
7713: dsp_core.registers[DSP_REG_A0] = source[2];
7714:
7715: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7716: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7717: }
7718:
7719: static void dsp_mpyr_p_x0_x0_b(void)
7720: {
7721: Uint32 source[3];
7722:
7723: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7724: dsp_rnd56(source);
7725:
7726: dsp_core.registers[DSP_REG_B2] = source[0];
7727: dsp_core.registers[DSP_REG_B1] = source[1];
7728: dsp_core.registers[DSP_REG_B0] = source[2];
7729:
7730: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7731: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7732: }
7733:
7734: static void dsp_mpyr_m_x0_x0_b(void)
7735: {
7736: Uint32 source[3];
7737:
7738:
7739: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7740: dsp_rnd56(source);
7741:
7742: dsp_core.registers[DSP_REG_B2] = source[0];
7743: dsp_core.registers[DSP_REG_B1] = source[1];
7744: dsp_core.registers[DSP_REG_B0] = source[2];
7745:
7746: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7747: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7748: }
7749:
7750: static void dsp_mpyr_p_y0_y0_a(void)
7751: {
7752: Uint32 source[3];
7753:
7754: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7755: dsp_rnd56(source);
7756:
7757: dsp_core.registers[DSP_REG_A2] = source[0];
7758: dsp_core.registers[DSP_REG_A1] = source[1];
7759: dsp_core.registers[DSP_REG_A0] = source[2];
7760:
7761: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7762: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7763: }
7764:
7765: static void dsp_mpyr_m_y0_y0_a(void)
7766: {
7767: Uint32 source[3];
7768:
7769: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7770: dsp_rnd56(source);
7771:
7772: dsp_core.registers[DSP_REG_A2] = source[0];
7773: dsp_core.registers[DSP_REG_A1] = source[1];
7774: dsp_core.registers[DSP_REG_A0] = source[2];
7775:
7776: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7777: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7778: }
7779:
7780: static void dsp_mpyr_p_y0_y0_b(void)
7781: {
7782: Uint32 source[3];
7783:
7784: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7785: dsp_rnd56(source);
7786:
7787: dsp_core.registers[DSP_REG_B2] = source[0];
7788: dsp_core.registers[DSP_REG_B1] = source[1];
7789: dsp_core.registers[DSP_REG_B0] = source[2];
7790:
7791: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7792: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7793: }
7794:
7795: static void dsp_mpyr_m_y0_y0_b(void)
7796: {
7797: Uint32 source[3];
7798:
7799: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7800: dsp_rnd56(source);
7801:
7802: dsp_core.registers[DSP_REG_B2] = source[0];
7803: dsp_core.registers[DSP_REG_B1] = source[1];
7804: dsp_core.registers[DSP_REG_B0] = source[2];
7805:
7806: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7807: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7808: }
7809:
7810: static void dsp_mpyr_p_x1_x0_a(void)
7811: {
7812: Uint32 source[3];
7813:
7814: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7815: dsp_rnd56(source);
7816:
7817: dsp_core.registers[DSP_REG_A2] = source[0];
7818: dsp_core.registers[DSP_REG_A1] = source[1];
7819: dsp_core.registers[DSP_REG_A0] = source[2];
7820:
7821: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7822: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7823: }
7824:
7825: static void dsp_mpyr_m_x1_x0_a(void)
7826: {
7827: Uint32 source[3];
7828:
7829: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7830: dsp_rnd56(source);
7831:
7832: dsp_core.registers[DSP_REG_A2] = source[0];
7833: dsp_core.registers[DSP_REG_A1] = source[1];
7834: dsp_core.registers[DSP_REG_A0] = source[2];
7835:
7836: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7837: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7838: }
7839:
7840: static void dsp_mpyr_p_x1_x0_b(void)
7841: {
7842: Uint32 source[3];
7843:
7844: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7845: dsp_rnd56(source);
7846:
7847: dsp_core.registers[DSP_REG_B2] = source[0];
7848: dsp_core.registers[DSP_REG_B1] = source[1];
7849: dsp_core.registers[DSP_REG_B0] = source[2];
7850:
7851: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7852: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7853: }
7854:
7855: static void dsp_mpyr_m_x1_x0_b(void)
7856: {
7857: Uint32 source[3];
7858:
7859: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7860: dsp_rnd56(source);
7861:
7862: dsp_core.registers[DSP_REG_B2] = source[0];
7863: dsp_core.registers[DSP_REG_B1] = source[1];
7864: dsp_core.registers[DSP_REG_B0] = source[2];
7865:
7866: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7867: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7868: }
7869:
7870: static void dsp_mpyr_p_y1_y0_a(void)
7871: {
7872: Uint32 source[3];
7873:
7874: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7875: dsp_rnd56(source);
7876:
7877: dsp_core.registers[DSP_REG_A2] = source[0];
7878: dsp_core.registers[DSP_REG_A1] = source[1];
7879: dsp_core.registers[DSP_REG_A0] = source[2];
7880:
7881: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7882: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7883: }
7884:
7885: static void dsp_mpyr_m_y1_y0_a(void)
7886: {
7887: Uint32 source[3];
7888:
7889: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7890: dsp_rnd56(source);
7891:
7892: dsp_core.registers[DSP_REG_A2] = source[0];
7893: dsp_core.registers[DSP_REG_A1] = source[1];
7894: dsp_core.registers[DSP_REG_A0] = source[2];
7895:
7896: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7897: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7898: }
7899:
7900: static void dsp_mpyr_p_y1_y0_b(void)
7901: {
7902: Uint32 source[3];
7903:
7904: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7905: dsp_rnd56(source);
7906:
7907: dsp_core.registers[DSP_REG_B2] = source[0];
7908: dsp_core.registers[DSP_REG_B1] = source[1];
7909: dsp_core.registers[DSP_REG_B0] = source[2];
7910:
7911: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7912: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7913: }
7914:
7915: static void dsp_mpyr_m_y1_y0_b(void)
7916: {
7917: Uint32 source[3];
7918:
7919: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7920: dsp_rnd56(source);
7921:
7922: dsp_core.registers[DSP_REG_B2] = source[0];
7923: dsp_core.registers[DSP_REG_B1] = source[1];
7924: dsp_core.registers[DSP_REG_B0] = source[2];
7925:
7926: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7927: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7928: }
7929:
7930: static void dsp_mpyr_p_x0_y1_a(void)
7931: {
7932: Uint32 source[3];
7933:
7934: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7935: dsp_rnd56(source);
7936:
7937: dsp_core.registers[DSP_REG_A2] = source[0];
7938: dsp_core.registers[DSP_REG_A1] = source[1];
7939: dsp_core.registers[DSP_REG_A0] = source[2];
7940:
7941: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7942: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7943: }
7944:
7945: static void dsp_mpyr_m_x0_y1_a(void)
7946: {
7947: Uint32 source[3];
7948:
7949: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7950: dsp_rnd56(source);
7951:
7952: dsp_core.registers[DSP_REG_A2] = source[0];
7953: dsp_core.registers[DSP_REG_A1] = source[1];
7954: dsp_core.registers[DSP_REG_A0] = source[2];
7955:
7956: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7957: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7958: }
7959:
7960: static void dsp_mpyr_p_x0_y1_b(void)
7961: {
7962: Uint32 source[3];
7963:
7964: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7965: dsp_rnd56(source);
7966:
7967: dsp_core.registers[DSP_REG_B2] = source[0];
7968: dsp_core.registers[DSP_REG_B1] = source[1];
7969: dsp_core.registers[DSP_REG_B0] = source[2];
7970:
7971: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7972: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7973: }
7974:
7975: static void dsp_mpyr_m_x0_y1_b(void)
7976: {
7977: Uint32 source[3];
7978:
7979: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7980: dsp_rnd56(source);
7981:
7982: dsp_core.registers[DSP_REG_B2] = source[0];
7983: dsp_core.registers[DSP_REG_B1] = source[1];
7984: dsp_core.registers[DSP_REG_B0] = source[2];
7985:
7986: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7987: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7988: }
7989:
7990: static void dsp_mpyr_p_y0_x0_a(void)
7991: {
7992: Uint32 source[3];
7993:
7994: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7995: dsp_rnd56(source);
7996:
7997: dsp_core.registers[DSP_REG_A2] = source[0];
7998: dsp_core.registers[DSP_REG_A1] = source[1];
7999: dsp_core.registers[DSP_REG_A0] = source[2];
8000:
8001: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8002: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8003: }
8004:
8005: static void dsp_mpyr_m_y0_x0_a(void)
8006: {
8007: Uint32 source[3];
8008:
8009: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
8010: dsp_rnd56(source);
8011:
8012: dsp_core.registers[DSP_REG_A2] = source[0];
8013: dsp_core.registers[DSP_REG_A1] = source[1];
8014: dsp_core.registers[DSP_REG_A0] = source[2];
8015:
8016: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8017: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8018: }
8019:
8020: static void dsp_mpyr_p_y0_x0_b(void)
8021: {
8022: Uint32 source[3];
8023:
8024: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
8025: dsp_rnd56(source);
8026:
8027: dsp_core.registers[DSP_REG_B2] = source[0];
8028: dsp_core.registers[DSP_REG_B1] = source[1];
8029: dsp_core.registers[DSP_REG_B0] = source[2];
8030:
8031: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8032: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8033: }
8034:
8035: static void dsp_mpyr_m_y0_x0_b(void)
8036: {
8037: Uint32 source[3];
8038:
8039: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
8040: dsp_rnd56(source);
8041:
8042: dsp_core.registers[DSP_REG_B2] = source[0];
8043: dsp_core.registers[DSP_REG_B1] = source[1];
8044: dsp_core.registers[DSP_REG_B0] = source[2];
8045:
8046: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8047: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8048: }
8049:
8050: static void dsp_mpyr_p_x1_y0_a(void)
8051: {
8052: Uint32 source[3];
8053:
8054: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
8055: dsp_rnd56(source);
8056:
8057: dsp_core.registers[DSP_REG_A2] = source[0];
8058: dsp_core.registers[DSP_REG_A1] = source[1];
8059: dsp_core.registers[DSP_REG_A0] = source[2];
8060:
8061: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8062: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8063: }
8064:
8065: static void dsp_mpyr_m_x1_y0_a(void)
8066: {
8067: Uint32 source[3];
8068:
8069: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
8070: dsp_rnd56(source);
8071:
8072: dsp_core.registers[DSP_REG_A2] = source[0];
8073: dsp_core.registers[DSP_REG_A1] = source[1];
8074: dsp_core.registers[DSP_REG_A0] = source[2];
8075:
8076: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8077: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8078: }
8079:
8080: static void dsp_mpyr_p_x1_y0_b(void)
8081: {
8082: Uint32 source[3];
8083:
8084: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
8085: dsp_rnd56(source);
8086:
8087: dsp_core.registers[DSP_REG_B2] = source[0];
8088: dsp_core.registers[DSP_REG_B1] = source[1];
8089: dsp_core.registers[DSP_REG_B0] = source[2];
8090:
8091: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8092: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8093: }
8094:
8095: static void dsp_mpyr_m_x1_y0_b(void)
8096: {
8097: Uint32 source[3];
8098:
8099: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
8100: dsp_rnd56(source);
8101:
8102: dsp_core.registers[DSP_REG_B2] = source[0];
8103: dsp_core.registers[DSP_REG_B1] = source[1];
8104: dsp_core.registers[DSP_REG_B0] = source[2];
8105:
8106: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8107: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8108: }
8109:
8110: static void dsp_mpyr_p_y1_x1_a(void)
8111: {
8112: Uint32 source[3];
8113:
8114: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
8115: dsp_rnd56(source);
8116:
8117: dsp_core.registers[DSP_REG_A2] = source[0];
8118: dsp_core.registers[DSP_REG_A1] = source[1];
8119: dsp_core.registers[DSP_REG_A0] = source[2];
8120:
8121: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8122: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8123: }
8124:
8125: static void dsp_mpyr_m_y1_x1_a(void)
8126: {
8127: Uint32 source[3];
8128:
8129: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8130: dsp_rnd56(source);
8131:
8132: dsp_core.registers[DSP_REG_A2] = source[0];
8133: dsp_core.registers[DSP_REG_A1] = source[1];
8134: dsp_core.registers[DSP_REG_A0] = source[2];
8135:
8136: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8137: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8138: }
8139:
8140: static void dsp_mpyr_p_y1_x1_b(void)
8141: {
8142: Uint32 source[3];
8143:
8144: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
8145: dsp_rnd56(source);
8146:
8147: dsp_core.registers[DSP_REG_B2] = source[0];
8148: dsp_core.registers[DSP_REG_B1] = source[1];
8149: dsp_core.registers[DSP_REG_B0] = source[2];
8150:
8151: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8152: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8153: }
8154:
8155: static void dsp_mpyr_m_y1_x1_b(void)
8156: {
8157: Uint32 source[3];
8158:
8159: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8160: dsp_rnd56(source);
8161:
8162: dsp_core.registers[DSP_REG_B2] = source[0];
8163: dsp_core.registers[DSP_REG_B1] = source[1];
8164: dsp_core.registers[DSP_REG_B0] = source[2];
8165:
8166: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8167: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8168: }
8169:
8170: static void dsp_neg_a(void)
8171: {
8172: Uint32 source[3], dest[3], overflowed;
8173:
8174: source[0] = dsp_core.registers[DSP_REG_A2];
8175: source[1] = dsp_core.registers[DSP_REG_A1];
8176: source[2] = dsp_core.registers[DSP_REG_A0];
8177:
8178: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8179:
8180: dest[0] = dest[1] = dest[2] = 0;
8181:
8182: dsp_sub56(source, dest);
8183:
8184: dsp_core.registers[DSP_REG_A2] = dest[0];
8185: dsp_core.registers[DSP_REG_A1] = dest[1];
8186: dsp_core.registers[DSP_REG_A0] = dest[2];
8187:
8188: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8189: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8190:
8191: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8192: }
8193:
8194: static void dsp_neg_b(void)
8195: {
8196: Uint32 source[3], dest[3], overflowed;
8197:
8198: source[0] = dsp_core.registers[DSP_REG_B2];
8199: source[1] = dsp_core.registers[DSP_REG_B1];
8200: source[2] = dsp_core.registers[DSP_REG_B0];
8201:
8202: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8203:
8204: dest[0] = dest[1] = dest[2] = 0;
8205:
8206: dsp_sub56(source, dest);
8207:
8208: dsp_core.registers[DSP_REG_B2] = dest[0];
8209: dsp_core.registers[DSP_REG_B1] = dest[1];
8210: dsp_core.registers[DSP_REG_B0] = dest[2];
8211:
8212: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8213: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8214:
8215: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8216: }
8217:
8218: static void dsp_nop(void)
8219: {
8220: }
8221:
8222: static void dsp_not_a(void)
8223: {
8224: dsp_core.registers[DSP_REG_A1] = ~dsp_core.registers[DSP_REG_A1];
8225: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8226:
8227: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8228: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8229: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8230: }
8231:
8232: static void dsp_not_b(void)
8233: {
8234: dsp_core.registers[DSP_REG_B1] = ~dsp_core.registers[DSP_REG_B1];
8235: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8236:
8237: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8238: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8239: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8240: }
8241:
8242: static void dsp_or_x0_a(void)
8243: {
8244: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X0];
8245: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8246:
8247: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8248: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8249: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8250: }
8251:
8252: static void dsp_or_x0_b(void)
8253: {
8254: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X0];
8255: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8256:
8257: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8258: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8259: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8260: }
8261:
8262: static void dsp_or_y0_a(void)
8263: {
8264: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y0];
8265: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8266:
8267: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8268: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8269: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8270: }
8271:
8272: static void dsp_or_y0_b(void)
8273: {
8274: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y0];
8275: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8276:
8277: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8278: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8279: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8280: }
8281:
8282: static void dsp_or_x1_a(void)
8283: {
8284: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X1];
8285: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8286:
8287: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8288: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8289: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8290: }
8291:
8292: static void dsp_or_x1_b(void)
8293: {
8294: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X1];
8295: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8296:
8297: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8298: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8299: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8300: }
8301:
8302: static void dsp_or_y1_a(void)
8303: {
8304: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y1];
8305: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8306:
8307: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8308: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8309: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8310: }
8311:
8312: static void dsp_or_y1_b(void)
8313: {
8314: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y1];
8315: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8316:
8317: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8318: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8319: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8320: }
8321:
8322: static void dsp_rnd_a(void)
8323: {
8324: Uint32 dest[3];
8325:
8326: dest[0] = dsp_core.registers[DSP_REG_A2];
8327: dest[1] = dsp_core.registers[DSP_REG_A1];
8328: dest[2] = dsp_core.registers[DSP_REG_A0];
8329:
8330: dsp_rnd56(dest);
8331:
8332: dsp_core.registers[DSP_REG_A2] = dest[0];
8333: dsp_core.registers[DSP_REG_A1] = dest[1];
8334: dsp_core.registers[DSP_REG_A0] = dest[2];
8335:
8336: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8337: }
8338:
8339: static void dsp_rnd_b(void)
8340: {
8341: Uint32 dest[3];
8342:
8343: dest[0] = dsp_core.registers[DSP_REG_B2];
8344: dest[1] = dsp_core.registers[DSP_REG_B1];
8345: dest[2] = dsp_core.registers[DSP_REG_B0];
8346:
8347: dsp_rnd56(dest);
8348:
8349: dsp_core.registers[DSP_REG_B2] = dest[0];
8350: dsp_core.registers[DSP_REG_B1] = dest[1];
8351: dsp_core.registers[DSP_REG_B0] = dest[2];
8352:
8353: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8354: }
8355:
8356: static void dsp_rol_a(void)
8357: {
8358: Uint32 newcarry;
8359:
8360: newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
8361:
8362: dsp_core.registers[DSP_REG_A1] <<= 1;
8363: dsp_core.registers[DSP_REG_A1] |= newcarry;
8364: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
8365:
8366: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8367: dsp_core.registers[DSP_REG_SR] |= newcarry;
8368: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8369: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8370: }
8371:
8372: static void dsp_rol_b(void)
8373: {
8374: Uint32 newcarry;
8375:
8376: newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
8377:
8378: dsp_core.registers[DSP_REG_B1] <<= 1;
8379: dsp_core.registers[DSP_REG_B1] |= newcarry;
8380: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
8381:
8382: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8383: dsp_core.registers[DSP_REG_SR] |= newcarry;
8384: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8385: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8386: }
8387:
8388: static void dsp_ror_a(void)
8389: {
8390: Uint32 newcarry;
8391:
8392: newcarry = dsp_core.registers[DSP_REG_A1] & 1;
8393:
8394: dsp_core.registers[DSP_REG_A1] >>= 1;
8395: dsp_core.registers[DSP_REG_A1] |= newcarry<<23;
8396:
8397: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8398: dsp_core.registers[DSP_REG_SR] |= newcarry;
8399: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8400: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8401: }
8402:
8403: static void dsp_ror_b(void)
8404: {
8405: Uint32 newcarry;
8406:
8407: newcarry = dsp_core.registers[DSP_REG_B1] & 1;
8408:
8409: dsp_core.registers[DSP_REG_B1] >>= 1;
8410: dsp_core.registers[DSP_REG_B1] |= newcarry<<23;
8411:
8412: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8413: dsp_core.registers[DSP_REG_SR] |= newcarry;
8414: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8415: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8416: }
8417:
8418: static void dsp_sbc_x_a(void)
8419: {
8420: Uint32 source[3], dest[3], curcarry;
8421: Uint16 newsr;
8422:
8423: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8424:
8425: dest[2] = dsp_core.registers[DSP_REG_A0];
8426: dest[1] = dsp_core.registers[DSP_REG_A1];
8427: dest[0] = dsp_core.registers[DSP_REG_A2];
8428:
8429: source[2] = dsp_core.registers[DSP_REG_X0];
8430: source[1] = dsp_core.registers[DSP_REG_X1];
8431: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8432:
8433: newsr = dsp_sub56(source, dest);
8434:
8435: if (curcarry) {
8436: source[0]=0; source[1]=0; source[2]=1;
8437: newsr |= dsp_sub56(source, dest);
8438: }
8439:
8440: dsp_core.registers[DSP_REG_A2] = dest[0];
8441: dsp_core.registers[DSP_REG_A1] = dest[1];
8442: dsp_core.registers[DSP_REG_A0] = dest[2];
8443:
8444: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8445:
8446: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8447: dsp_core.registers[DSP_REG_SR] |= newsr;
8448: }
8449:
8450: static void dsp_sbc_x_b(void)
8451: {
8452: Uint32 source[3], dest[3], curcarry;
8453: Uint16 newsr;
8454:
8455: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8456:
8457: dest[2] = dsp_core.registers[DSP_REG_B0];
8458: dest[1] = dsp_core.registers[DSP_REG_B1];
8459: dest[0] = dsp_core.registers[DSP_REG_B2];
8460:
8461: source[2] = dsp_core.registers[DSP_REG_X0];
8462: source[1] = dsp_core.registers[DSP_REG_X1];
8463: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8464:
8465: newsr = dsp_sub56(source, dest);
8466:
8467: if (curcarry) {
8468: source[0]=0; source[1]=0; source[2]=1;
8469: newsr |= dsp_sub56(source, dest);
8470: }
8471:
8472: dsp_core.registers[DSP_REG_B2] = dest[0];
8473: dsp_core.registers[DSP_REG_B1] = dest[1];
8474: dsp_core.registers[DSP_REG_B0] = dest[2];
8475:
8476: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8477:
8478: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8479: dsp_core.registers[DSP_REG_SR] |= newsr;
8480: }
8481:
8482: static void dsp_sbc_y_a(void)
8483: {
8484: Uint32 source[3], dest[3], curcarry;
8485: Uint16 newsr;
8486:
8487: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8488:
8489: dest[2] = dsp_core.registers[DSP_REG_A0];
8490: dest[1] = dsp_core.registers[DSP_REG_A1];
8491: dest[0] = dsp_core.registers[DSP_REG_A2];
8492:
8493: source[2] = dsp_core.registers[DSP_REG_Y0];
8494: source[1] = dsp_core.registers[DSP_REG_Y1];
8495: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8496:
8497: newsr = dsp_sub56(source, dest);
8498:
8499: if (curcarry) {
8500: source[0]=0; source[1]=0; source[2]=1;
8501: newsr |= dsp_sub56(source, dest);
8502: }
8503:
8504: dsp_core.registers[DSP_REG_A2] = dest[0];
8505: dsp_core.registers[DSP_REG_A1] = dest[1];
8506: dsp_core.registers[DSP_REG_A0] = dest[2];
8507:
8508: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8509:
8510: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8511: dsp_core.registers[DSP_REG_SR] |= newsr;
8512: }
8513:
8514: static void dsp_sbc_y_b(void)
8515: {
8516: Uint32 source[3], dest[3], curcarry;
8517: Uint16 newsr;
8518:
8519: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8520:
8521: dest[2] = dsp_core.registers[DSP_REG_B0];
8522: dest[1] = dsp_core.registers[DSP_REG_B1];
8523: dest[0] = dsp_core.registers[DSP_REG_B2];
8524:
8525: source[2] = dsp_core.registers[DSP_REG_Y0];
8526: source[1] = dsp_core.registers[DSP_REG_Y1];
8527: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8528:
8529: newsr = dsp_sub56(source, dest);
8530:
8531: if (curcarry) {
8532: source[0]=0; source[1]=0; source[2]=1;
8533: newsr |= dsp_sub56(source, dest);
8534: }
8535:
8536: dsp_core.registers[DSP_REG_B2] = dest[0];
8537: dsp_core.registers[DSP_REG_B1] = dest[1];
8538: dsp_core.registers[DSP_REG_B0] = dest[2];
8539:
8540: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8541:
8542: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8543: dsp_core.registers[DSP_REG_SR] |= newsr;
8544: }
8545:
8546: static void dsp_sub_b_a(void)
8547: {
8548: Uint32 source[3], dest[3];
8549: Uint16 newsr;
8550:
8551: dest[2] = dsp_core.registers[DSP_REG_A0];
8552: dest[1] = dsp_core.registers[DSP_REG_A1];
8553: dest[0] = dsp_core.registers[DSP_REG_A2];
8554:
8555: source[2] = dsp_core.registers[DSP_REG_B0];
8556: source[1] = dsp_core.registers[DSP_REG_B1];
8557: source[0] = dsp_core.registers[DSP_REG_B2];
8558:
8559: newsr = dsp_sub56(source, dest);
8560:
8561: dsp_core.registers[DSP_REG_A2] = dest[0];
8562: dsp_core.registers[DSP_REG_A1] = dest[1];
8563: dsp_core.registers[DSP_REG_A0] = dest[2];
8564:
8565: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8566:
8567: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8568: dsp_core.registers[DSP_REG_SR] |= newsr;
8569: }
8570:
8571: static void dsp_sub_a_b(void)
8572: {
8573: Uint32 source[3], dest[3];
8574: Uint16 newsr;
8575:
8576: dest[2] = dsp_core.registers[DSP_REG_B0];
8577: dest[1] = dsp_core.registers[DSP_REG_B1];
8578: dest[0] = dsp_core.registers[DSP_REG_B2];
8579:
8580: source[2] = dsp_core.registers[DSP_REG_A0];
8581: source[1] = dsp_core.registers[DSP_REG_A1];
8582: source[0] = dsp_core.registers[DSP_REG_A2];
8583:
8584: newsr = dsp_sub56(source, dest);
8585:
8586: dsp_core.registers[DSP_REG_B2] = dest[0];
8587: dsp_core.registers[DSP_REG_B1] = dest[1];
8588: dsp_core.registers[DSP_REG_B0] = dest[2];
8589:
8590: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8591:
8592: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8593: dsp_core.registers[DSP_REG_SR] |= newsr;
8594: }
8595:
8596: static void dsp_sub_x_a(void)
8597: {
8598: Uint32 source[3], dest[3];
8599: Uint16 newsr;
8600:
8601: dest[2] = dsp_core.registers[DSP_REG_A0];
8602: dest[1] = dsp_core.registers[DSP_REG_A1];
8603: dest[0] = dsp_core.registers[DSP_REG_A2];
8604:
8605: source[2] = dsp_core.registers[DSP_REG_X0];
8606: source[1] = dsp_core.registers[DSP_REG_X1];
8607: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8608:
8609: newsr = dsp_sub56(source, dest);
8610:
8611: dsp_core.registers[DSP_REG_A2] = dest[0];
8612: dsp_core.registers[DSP_REG_A1] = dest[1];
8613: dsp_core.registers[DSP_REG_A0] = dest[2];
8614:
8615: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8616:
8617: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8618: dsp_core.registers[DSP_REG_SR] |= newsr;
8619: }
8620:
8621: static void dsp_sub_x_b(void)
8622: {
8623: Uint32 source[3], dest[3];
8624: Uint16 newsr;
8625:
8626: dest[2] = dsp_core.registers[DSP_REG_B0];
8627: dest[1] = dsp_core.registers[DSP_REG_B1];
8628: dest[0] = dsp_core.registers[DSP_REG_B2];
8629:
8630: source[2] = dsp_core.registers[DSP_REG_X0];
8631: source[1] = dsp_core.registers[DSP_REG_X1];
8632: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8633:
8634: newsr = dsp_sub56(source, dest);
8635:
8636: dsp_core.registers[DSP_REG_B2] = dest[0];
8637: dsp_core.registers[DSP_REG_B1] = dest[1];
8638: dsp_core.registers[DSP_REG_B0] = dest[2];
8639:
8640: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8641:
8642: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8643: dsp_core.registers[DSP_REG_SR] |= newsr;
8644: }
8645:
8646: static void dsp_sub_y_a(void)
8647: {
8648: Uint32 source[3], dest[3];
8649: Uint16 newsr;
8650:
8651: dest[2] = dsp_core.registers[DSP_REG_A0];
8652: dest[1] = dsp_core.registers[DSP_REG_A1];
8653: dest[0] = dsp_core.registers[DSP_REG_A2];
8654:
8655: source[2] = dsp_core.registers[DSP_REG_Y0];
8656: source[1] = dsp_core.registers[DSP_REG_Y1];
8657: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8658:
8659: newsr = dsp_sub56(source, dest);
8660:
8661: dsp_core.registers[DSP_REG_A2] = dest[0];
8662: dsp_core.registers[DSP_REG_A1] = dest[1];
8663: dsp_core.registers[DSP_REG_A0] = dest[2];
8664:
8665: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8666:
8667: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8668: dsp_core.registers[DSP_REG_SR] |= newsr;
8669: }
8670:
8671: static void dsp_sub_y_b(void)
8672: {
8673: Uint32 source[3], dest[3];
8674: Uint16 newsr;
8675:
8676: dest[2] = dsp_core.registers[DSP_REG_B0];
8677: dest[1] = dsp_core.registers[DSP_REG_B1];
8678: dest[0] = dsp_core.registers[DSP_REG_B2];
8679:
8680: source[2] = dsp_core.registers[DSP_REG_Y0];
8681: source[1] = dsp_core.registers[DSP_REG_Y1];
8682: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8683:
8684: newsr = dsp_sub56(source, dest);
8685:
8686: dsp_core.registers[DSP_REG_B2] = dest[0];
8687: dsp_core.registers[DSP_REG_B1] = dest[1];
8688: dsp_core.registers[DSP_REG_B0] = dest[2];
8689:
8690: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8691:
8692: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8693: dsp_core.registers[DSP_REG_SR] |= newsr;
8694: }
8695:
8696: static void dsp_sub_x0_a(void)
8697: {
8698: Uint32 source[3], dest[3];
8699: Uint16 newsr;
8700:
8701: dest[2] = dsp_core.registers[DSP_REG_A0];
8702: dest[1] = dsp_core.registers[DSP_REG_A1];
8703: dest[0] = dsp_core.registers[DSP_REG_A2];
8704:
8705: source[2] = 0;
8706: source[1] = dsp_core.registers[DSP_REG_X0];
8707: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8708:
8709: newsr = dsp_sub56(source, dest);
8710:
8711: dsp_core.registers[DSP_REG_A2] = dest[0];
8712: dsp_core.registers[DSP_REG_A1] = dest[1];
8713: dsp_core.registers[DSP_REG_A0] = dest[2];
8714:
8715: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8716:
8717: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8718: dsp_core.registers[DSP_REG_SR] |= newsr;
8719: }
8720:
8721: static void dsp_sub_x0_b(void)
8722: {
8723: Uint32 source[3], dest[3];
8724: Uint16 newsr;
8725:
8726: dest[2] = dsp_core.registers[DSP_REG_B0];
8727: dest[1] = dsp_core.registers[DSP_REG_B1];
8728: dest[0] = dsp_core.registers[DSP_REG_B2];
8729:
8730: source[2] = 0;
8731: source[1] = dsp_core.registers[DSP_REG_X0];
8732: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8733:
8734: newsr = dsp_sub56(source, dest);
8735:
8736: dsp_core.registers[DSP_REG_B2] = dest[0];
8737: dsp_core.registers[DSP_REG_B1] = dest[1];
8738: dsp_core.registers[DSP_REG_B0] = dest[2];
8739:
8740: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8741:
8742: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8743: dsp_core.registers[DSP_REG_SR] |= newsr;
8744: }
8745:
8746: static void dsp_sub_y0_a(void)
8747: {
8748: Uint32 source[3], dest[3];
8749: Uint16 newsr;
8750:
8751: dest[2] = dsp_core.registers[DSP_REG_A0];
8752: dest[1] = dsp_core.registers[DSP_REG_A1];
8753: dest[0] = dsp_core.registers[DSP_REG_A2];
8754:
8755: source[2] = 0;
8756: source[1] = dsp_core.registers[DSP_REG_Y0];
8757: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8758:
8759: newsr = dsp_sub56(source, dest);
8760:
8761: dsp_core.registers[DSP_REG_A2] = dest[0];
8762: dsp_core.registers[DSP_REG_A1] = dest[1];
8763: dsp_core.registers[DSP_REG_A0] = dest[2];
8764:
8765: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8766:
8767: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8768: dsp_core.registers[DSP_REG_SR] |= newsr;
8769: }
8770:
8771: static void dsp_sub_y0_b(void)
8772: {
8773: Uint32 source[3], dest[3];
8774: Uint16 newsr;
8775:
8776: dest[2] = dsp_core.registers[DSP_REG_B0];
8777: dest[1] = dsp_core.registers[DSP_REG_B1];
8778: dest[0] = dsp_core.registers[DSP_REG_B2];
8779:
8780: source[2] = 0;
8781: source[1] = dsp_core.registers[DSP_REG_Y0];
8782: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8783:
8784: newsr = dsp_sub56(source, dest);
8785:
8786: dsp_core.registers[DSP_REG_B2] = dest[0];
8787: dsp_core.registers[DSP_REG_B1] = dest[1];
8788: dsp_core.registers[DSP_REG_B0] = dest[2];
8789:
8790: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8791:
8792: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8793: dsp_core.registers[DSP_REG_SR] |= newsr;
8794: }
8795:
8796: static void dsp_sub_x1_a(void)
8797: {
8798: Uint32 source[3], dest[3];
8799: Uint16 newsr;
8800:
8801: dest[2] = dsp_core.registers[DSP_REG_A0];
8802: dest[1] = dsp_core.registers[DSP_REG_A1];
8803: dest[0] = dsp_core.registers[DSP_REG_A2];
8804:
8805: source[2] = 0;
8806: source[1] = dsp_core.registers[DSP_REG_X1];
8807: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8808:
8809: newsr = dsp_sub56(source, dest);
8810:
8811: dsp_core.registers[DSP_REG_A2] = dest[0];
8812: dsp_core.registers[DSP_REG_A1] = dest[1];
8813: dsp_core.registers[DSP_REG_A0] = dest[2];
8814:
8815: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8816:
8817: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8818: dsp_core.registers[DSP_REG_SR] |= newsr;
8819: }
8820:
8821: static void dsp_sub_x1_b(void)
8822: {
8823: Uint32 source[3], dest[3];
8824: Uint16 newsr;
8825:
8826: dest[2] = dsp_core.registers[DSP_REG_B0];
8827: dest[1] = dsp_core.registers[DSP_REG_B1];
8828: dest[0] = dsp_core.registers[DSP_REG_B2];
8829:
8830: source[2] = 0;
8831: source[1] = dsp_core.registers[DSP_REG_X1];
8832: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8833:
8834: newsr = dsp_sub56(source, dest);
8835:
8836: dsp_core.registers[DSP_REG_B2] = dest[0];
8837: dsp_core.registers[DSP_REG_B1] = dest[1];
8838: dsp_core.registers[DSP_REG_B0] = dest[2];
8839:
8840: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8841:
8842: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8843: dsp_core.registers[DSP_REG_SR] |= newsr;
8844: }
8845:
8846: static void dsp_sub_y1_a(void)
8847: {
8848: Uint32 source[3], dest[3];
8849: Uint16 newsr;
8850:
8851: dest[2] = dsp_core.registers[DSP_REG_A0];
8852: dest[1] = dsp_core.registers[DSP_REG_A1];
8853: dest[0] = dsp_core.registers[DSP_REG_A2];
8854:
8855: source[2] = 0;
8856: source[1] = dsp_core.registers[DSP_REG_Y1];
8857: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8858:
8859: newsr = dsp_sub56(source, dest);
8860:
8861: dsp_core.registers[DSP_REG_A2] = dest[0];
8862: dsp_core.registers[DSP_REG_A1] = dest[1];
8863: dsp_core.registers[DSP_REG_A0] = dest[2];
8864:
8865: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8866:
8867: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8868: dsp_core.registers[DSP_REG_SR] |= newsr;
8869: }
8870:
8871: static void dsp_sub_y1_b(void)
8872: {
8873: Uint32 source[3], dest[3];
8874: Uint16 newsr;
8875:
8876: dest[2] = dsp_core.registers[DSP_REG_B0];
8877: dest[1] = dsp_core.registers[DSP_REG_B1];
8878: dest[0] = dsp_core.registers[DSP_REG_B2];
8879:
8880: source[2] = 0;
8881: source[1] = dsp_core.registers[DSP_REG_Y1];
8882: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
8883:
8884: newsr = dsp_sub56(source, dest);
8885:
8886: dsp_core.registers[DSP_REG_B2] = dest[0];
8887: dsp_core.registers[DSP_REG_B1] = dest[1];
8888: dsp_core.registers[DSP_REG_B0] = dest[2];
8889:
8890: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8891:
8892: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8893: dsp_core.registers[DSP_REG_SR] |= newsr;
8894: }
8895:
8896: static void dsp_subl_a(void)
8897: {
8898: Uint32 source[3], dest[3];
8899: Uint16 newsr;
8900:
8901: dest[0] = dsp_core.registers[DSP_REG_A2];
8902: dest[1] = dsp_core.registers[DSP_REG_A1];
8903: dest[2] = dsp_core.registers[DSP_REG_A0];
8904: newsr = dsp_asl56(dest);
8905:
8906: source[0] = dsp_core.registers[DSP_REG_B2];
8907: source[1] = dsp_core.registers[DSP_REG_B1];
8908: source[2] = dsp_core.registers[DSP_REG_B0];
8909: newsr |= dsp_sub56(source, dest);
8910:
8911: dsp_core.registers[DSP_REG_A2] = dest[0];
8912: dsp_core.registers[DSP_REG_A1] = dest[1];
8913: dsp_core.registers[DSP_REG_A0] = dest[2];
8914:
8915: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8916:
8917: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8918: dsp_core.registers[DSP_REG_SR] |= newsr;
8919: }
8920:
8921: static void dsp_subl_b(void)
8922: {
8923: Uint32 source[3], dest[3];
8924: Uint16 newsr;
8925:
8926: dest[0] = dsp_core.registers[DSP_REG_B2];
8927: dest[1] = dsp_core.registers[DSP_REG_B1];
8928: dest[2] = dsp_core.registers[DSP_REG_B0];
8929: newsr = dsp_asl56(dest);
8930:
8931: source[0] = dsp_core.registers[DSP_REG_A2];
8932: source[1] = dsp_core.registers[DSP_REG_A1];
8933: source[2] = dsp_core.registers[DSP_REG_A0];
8934: newsr |= dsp_sub56(source, dest);
8935:
8936: dsp_core.registers[DSP_REG_B2] = dest[0];
8937: dsp_core.registers[DSP_REG_B1] = dest[1];
8938: dsp_core.registers[DSP_REG_B0] = dest[2];
8939:
8940: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8941:
8942: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8943: dsp_core.registers[DSP_REG_SR] |= newsr;
8944: }
8945:
8946: static void dsp_subr_a(void)
8947: {
8948: Uint32 source[3], dest[3];
8949: Uint16 newsr;
8950:
8951: dest[0] = dsp_core.registers[DSP_REG_A2];
8952: dest[1] = dsp_core.registers[DSP_REG_A1];
8953: dest[2] = dsp_core.registers[DSP_REG_A0];
8954:
8955: newsr = dsp_asr56(dest);
8956:
8957: source[0] = dsp_core.registers[DSP_REG_B2];
8958: source[1] = dsp_core.registers[DSP_REG_B1];
8959: source[2] = dsp_core.registers[DSP_REG_B0];
8960:
8961: newsr |= dsp_sub56(source, dest);
8962:
8963: dsp_core.registers[DSP_REG_A2] = dest[0];
8964: dsp_core.registers[DSP_REG_A1] = dest[1];
8965: dsp_core.registers[DSP_REG_A0] = dest[2];
8966:
8967: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8968:
8969: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8970: dsp_core.registers[DSP_REG_SR] |= newsr;
8971: }
8972:
8973: static void dsp_subr_b(void)
8974: {
8975: Uint32 source[3], dest[3];
8976: Uint16 newsr;
8977:
8978: dest[0] = dsp_core.registers[DSP_REG_B2];
8979: dest[1] = dsp_core.registers[DSP_REG_B1];
8980: dest[2] = dsp_core.registers[DSP_REG_B0];
8981:
8982: newsr = dsp_asr56(dest);
8983:
8984: source[0] = dsp_core.registers[DSP_REG_A2];
8985: source[1] = dsp_core.registers[DSP_REG_A1];
8986: source[2] = dsp_core.registers[DSP_REG_A0];
8987:
8988: newsr |= dsp_sub56(source, dest);
8989:
8990: dsp_core.registers[DSP_REG_B2] = dest[0];
8991: dsp_core.registers[DSP_REG_B1] = dest[1];
8992: dsp_core.registers[DSP_REG_B0] = dest[2];
8993:
8994: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8995:
8996: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8997: dsp_core.registers[DSP_REG_SR] |= newsr;
8998: }
8999:
9000: static void dsp_tfr_b_a(void)
9001: {
9002: dsp_core.registers[DSP_REG_A0] = dsp_core.registers[DSP_REG_B0];
9003: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_B1];
9004: dsp_core.registers[DSP_REG_A2] = dsp_core.registers[DSP_REG_B2];
9005: }
9006:
9007: static void dsp_tfr_a_b(void)
9008: {
9009: dsp_core.registers[DSP_REG_B0] = dsp_core.registers[DSP_REG_A0];
9010: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_A1];
9011: dsp_core.registers[DSP_REG_B2] = dsp_core.registers[DSP_REG_A2];
9012: }
9013:
9014: static void dsp_tfr_x0_a(void)
9015: {
9016: dsp_core.registers[DSP_REG_A0] = 0;
9017: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X0];
9018: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
9019: dsp_core.registers[DSP_REG_A2] = 0xff;
9020: else
9021: dsp_core.registers[DSP_REG_A2] = 0x0;
9022: }
9023:
9024: static void dsp_tfr_x0_b(void)
9025: {
9026: dsp_core.registers[DSP_REG_B0] = 0;
9027: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X0];
9028: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
9029: dsp_core.registers[DSP_REG_B2] = 0xff;
9030: else
9031: dsp_core.registers[DSP_REG_B2] = 0x0;
9032: }
9033:
9034: static void dsp_tfr_y0_a(void)
9035: {
9036: dsp_core.registers[DSP_REG_A0] = 0;
9037: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y0];
9038: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
9039: dsp_core.registers[DSP_REG_A2] = 0xff;
9040: else
9041: dsp_core.registers[DSP_REG_A2] = 0x0;
9042: }
9043:
9044: static void dsp_tfr_y0_b(void)
9045: {
9046: dsp_core.registers[DSP_REG_B0] = 0;
9047: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y0];
9048: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
9049: dsp_core.registers[DSP_REG_B2] = 0xff;
9050: else
9051: dsp_core.registers[DSP_REG_B2] = 0x0;
9052: }
9053:
9054: static void dsp_tfr_x1_a(void)
9055: {
9056: dsp_core.registers[DSP_REG_A0] = 0;
9057: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X1];
9058: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
9059: dsp_core.registers[DSP_REG_A2] = 0xff;
9060: else
9061: dsp_core.registers[DSP_REG_A2] = 0x0;
9062: }
9063:
9064: static void dsp_tfr_x1_b(void)
9065: {
9066: dsp_core.registers[DSP_REG_B0] = 0;
9067: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X1];
9068: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
9069: dsp_core.registers[DSP_REG_B2] = 0xff;
9070: else
9071: dsp_core.registers[DSP_REG_B2] = 0x0;
9072: }
9073:
9074: static void dsp_tfr_y1_a(void)
9075: {
9076: dsp_core.registers[DSP_REG_A0] = 0;
9077: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y1];
9078: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
9079: dsp_core.registers[DSP_REG_A2] = 0xff;
9080: else
9081: dsp_core.registers[DSP_REG_A2] = 0x0;
9082: }
9083:
9084: static void dsp_tfr_y1_b(void)
9085: {
9086: dsp_core.registers[DSP_REG_B0] = 0;
9087: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y1];
9088: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
9089: dsp_core.registers[DSP_REG_B2] = 0xff;
9090: else
9091: dsp_core.registers[DSP_REG_B2] = 0x0;
9092: }
9093:
9094: static void dsp_tst_a(void)
9095: {
9096: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_A2],
9097: dsp_core.registers[DSP_REG_A1],
9098: dsp_core.registers[DSP_REG_A0]);
9099:
9100: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
9101: }
9102:
9103: static void dsp_tst_b(void)
9104: {
9105: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_B2],
9106: dsp_core.registers[DSP_REG_B1],
9107: dsp_core.registers[DSP_REG_B0]);
9108:
9109: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
9110: }
9111:
9112: /*
9113: vim:ts=4:sw=4:
9114: */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.