Diff for /qemu/cpu-common.h between versions 1.1.1.5 and 1.1.1.6

version 1.1.1.5, 2018/04/24 18:56:49 version 1.1.1.6, 2018/04/24 19:17:57
Line 3 Line 3
   
 /* CPU interfaces that are target indpendent.  */  /* CPU interfaces that are target indpendent.  */
   
 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)  
 #define WORDS_ALIGNED  
 #endif  
   
 #ifdef TARGET_PHYS_ADDR_BITS  #ifdef TARGET_PHYS_ADDR_BITS
 #include "targphys.h"  #include "targphys.h"
 #endif  #endif
Line 27  enum device_endian { Line 23  enum device_endian {
 };  };
   
 /* address in the RAM (different from a physical address) */  /* address in the RAM (different from a physical address) */
   #if defined(CONFIG_XEN_BACKEND) && TARGET_PHYS_ADDR_BITS == 64
   typedef uint64_t ram_addr_t;
   #  define RAM_ADDR_MAX UINT64_MAX
   #  define RAM_ADDR_FMT "%" PRIx64
   #else
 typedef unsigned long ram_addr_t;  typedef unsigned long ram_addr_t;
   #  define RAM_ADDR_MAX ULONG_MAX
   #  define RAM_ADDR_FMT "%lx"
   #endif
   
 /* memory API */  /* memory API */
   
Line 168  void cpu_physical_memory_write_rom(targe Line 172  void cpu_physical_memory_write_rom(targe
 #define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */  #define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
 #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)  #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
 #define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)  #define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)
   #define IO_MEM_SUBPAGE_RAM (4 << IO_MEM_SHIFT)
   
 /* Acts like a ROM when read and like a device when written.  */  /* Acts like a ROM when read and like a device when written.  */
 #define IO_MEM_ROMD        (1)  #define IO_MEM_ROMD        (1)

Removed from v.1.1.1.5  
changed lines
  Added in v.1.1.1.6


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