![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to cpu-common.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu|
Return to cpu-common.h CVS log | Up to [Qemu by Fabrice Bellard] / qemu |
1.1 root 1: #ifndef CPU_COMMON_H
2: #define CPU_COMMON_H 1
3:
4: /* CPU interfaces that are target indpendent. */
5:
6: #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
7: #define WORDS_ALIGNED
8: #endif
9:
10: #include "bswap.h"
11:
12: /* address in the RAM (different from a physical address) */
13: typedef unsigned long ram_addr_t;
14:
15: /* memory API */
16:
17: typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
18: typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
19:
20: void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
21: ram_addr_t size,
22: ram_addr_t phys_offset,
23: ram_addr_t region_offset);
24: static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
25: ram_addr_t size,
26: ram_addr_t phys_offset)
27: {
28: cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
29: }
30:
31: ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
32: ram_addr_t qemu_ram_alloc(ram_addr_t);
33: void qemu_ram_free(ram_addr_t addr);
34: /* This should only be used for ram local to a device. */
35: void *qemu_get_ram_ptr(ram_addr_t addr);
36: /* This should not be used by devices. */
37: ram_addr_t qemu_ram_addr_from_host(void *ptr);
38:
1.1.1.2 ! root 39: int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
! 40: CPUWriteMemoryFunc * const *mem_write,
1.1 root 41: void *opaque);
42: void cpu_unregister_io_memory(int table_address);
43:
44: void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
45: int len, int is_write);
46: static inline void cpu_physical_memory_read(target_phys_addr_t addr,
47: uint8_t *buf, int len)
48: {
49: cpu_physical_memory_rw(addr, buf, len, 0);
50: }
51: static inline void cpu_physical_memory_write(target_phys_addr_t addr,
52: const uint8_t *buf, int len)
53: {
54: cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
55: }
56: void *cpu_physical_memory_map(target_phys_addr_t addr,
57: target_phys_addr_t *plen,
58: int is_write);
59: void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
60: int is_write, target_phys_addr_t access_len);
61: void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
62: void cpu_unregister_map_client(void *cookie);
63:
64: uint32_t ldub_phys(target_phys_addr_t addr);
65: uint32_t lduw_phys(target_phys_addr_t addr);
66: uint32_t ldl_phys(target_phys_addr_t addr);
67: uint64_t ldq_phys(target_phys_addr_t addr);
68: void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
69: void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
70: void stb_phys(target_phys_addr_t addr, uint32_t val);
71: void stw_phys(target_phys_addr_t addr, uint32_t val);
72: void stl_phys(target_phys_addr_t addr, uint32_t val);
73: void stq_phys(target_phys_addr_t addr, uint64_t val);
74:
75: void cpu_physical_memory_write_rom(target_phys_addr_t addr,
76: const uint8_t *buf, int len);
77:
78: #define IO_MEM_SHIFT 3
79:
80: #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
81: #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
82: #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
83: #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
84:
85: /* Acts like a ROM when read and like a device when written. */
86: #define IO_MEM_ROMD (1)
87: #define IO_MEM_SUBPAGE (2)
88: #define IO_MEM_SUBWIDTH (4)
89:
90: #endif /* !CPU_COMMON_H */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.