Diff for /qemu/cpu-defs.h between versions 1.1.1.1 and 1.1.1.2

version 1.1.1.1, 2018/04/24 16:37:52 version 1.1.1.2, 2018/04/24 16:38:40
Line 74  typedef unsigned long ram_addr_t; Line 74  typedef unsigned long ram_addr_t;
 #define EXCP_INTERRUPT  0x10000 /* async interruption */  #define EXCP_INTERRUPT  0x10000 /* async interruption */
 #define EXCP_HLT        0x10001 /* hlt instruction reached */  #define EXCP_HLT        0x10001 /* hlt instruction reached */
 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */  #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
   #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
 #define MAX_BREAKPOINTS 32  #define MAX_BREAKPOINTS 32
   
 #define CPU_TLB_SIZE 256  #define TB_JMP_CACHE_BITS 12
   #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
   
   #define CPU_TLB_BITS 8
   #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
   
 typedef struct CPUTLBEntry {  typedef struct CPUTLBEntry {
     /* bit 31 to TARGET_PAGE_BITS : virtual address       /* bit 31 to TARGET_PAGE_BITS : virtual address 
Line 86  typedef struct CPUTLBEntry { Line 90  typedef struct CPUTLBEntry {
        bit 3                      : indicates that the entry is invalid         bit 3                      : indicates that the entry is invalid
        bit 2..0                   : zero         bit 2..0                   : zero
     */      */
     target_ulong address;       target_ulong addr_read; 
       target_ulong addr_write; 
       target_ulong addr_code; 
     /* addend to virtual address to get physical address */      /* addend to virtual address to get physical address */
     target_phys_addr_t addend;       target_phys_addr_t addend; 
 } CPUTLBEntry;  } CPUTLBEntry;
   
   #define CPU_COMMON                                                      \
       struct TranslationBlock *current_tb; /* currently executing TB  */  \
       /* soft mmu support */                                              \
       /* in order to avoid passing too many arguments to the memory       \
          write helpers, we store some rarely used information in the CPU  \
          context) */                                                      \
       unsigned long mem_write_pc; /* host pc at which the memory was      \
                                      written */                           \
       target_ulong mem_write_vaddr; /* target virtual addr at which the   \
                                        memory was written */              \
       /* 0 = kernel, 1 = user */                                          \
       CPUTLBEntry tlb_table[2][CPU_TLB_SIZE];                             \
       struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
                                                                           \
       /* from this point: preserved by CPU reset */                       \
       /* ice debug support */                                             \
       target_ulong breakpoints[MAX_BREAKPOINTS];                          \
       int nb_breakpoints;                                                 \
       int singlestep_enabled;                                             \
                                                                           \
       void *next_cpu; /* next CPU sharing TB cache */                     \
       int cpu_index; /* CPU index (informative) */                        \
       /* user data */                                                     \
       void *opaque;
   
 #endif  #endif

Removed from v.1.1.1.1  
changed lines
  Added in v.1.1.1.2


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