Diff for /qemu/cpu-defs.h between versions 1.1.1.5 and 1.1.1.11

version 1.1.1.5, 2018/04/24 16:47:33 version 1.1.1.11, 2018/04/24 18:56:37
Line 14 Line 14
  * Lesser General Public License for more details.   * Lesser General Public License for more details.
  *   *
  * You should have received a copy of the GNU Lesser General Public   * You should have received a copy of the GNU Lesser General Public
  * License along with this library; if not, write to the Free Software   * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA  
  */   */
 #ifndef CPU_DEFS_H  #ifndef CPU_DEFS_H
 #define CPU_DEFS_H  #define CPU_DEFS_H
Line 27 Line 26
 #include "config.h"  #include "config.h"
 #include <setjmp.h>  #include <setjmp.h>
 #include <inttypes.h>  #include <inttypes.h>
   #include <signal.h>
 #include "osdep.h"  #include "osdep.h"
   #include "qemu-queue.h"
   #include "targphys.h"
   
 #ifndef TARGET_LONG_BITS  #ifndef TARGET_LONG_BITS
 #error TARGET_LONG_BITS must be defined before including this header  #error TARGET_LONG_BITS must be defined before including this header
 #endif  #endif
   
 #ifndef TARGET_PHYS_ADDR_BITS  
 #if TARGET_LONG_BITS >= HOST_LONG_BITS  
 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS  
 #else  
 #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS  
 #endif  
 #endif  
   
 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)  #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
   
   typedef int16_t target_short __attribute__ ((aligned(TARGET_SHORT_ALIGNMENT)));
   typedef uint16_t target_ushort __attribute__((aligned(TARGET_SHORT_ALIGNMENT)));
   typedef int32_t target_int __attribute__((aligned(TARGET_INT_ALIGNMENT)));
   typedef uint32_t target_uint __attribute__((aligned(TARGET_INT_ALIGNMENT)));
   typedef int64_t target_llong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
   typedef uint64_t target_ullong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
 /* target_ulong is the type of a virtual address */  /* target_ulong is the type of a virtual address */
 #if TARGET_LONG_SIZE == 4  #if TARGET_LONG_SIZE == 4
 typedef int32_t target_long;  typedef int32_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
 typedef uint32_t target_ulong;  typedef uint32_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
 #define TARGET_FMT_lx "%08x"  #define TARGET_FMT_lx "%08x"
 #define TARGET_FMT_ld "%d"  #define TARGET_FMT_ld "%d"
 #define TARGET_FMT_lu "%u"  #define TARGET_FMT_lu "%u"
 #elif TARGET_LONG_SIZE == 8  #elif TARGET_LONG_SIZE == 8
 typedef int64_t target_long;  typedef int64_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
 typedef uint64_t target_ulong;  typedef uint64_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
 #define TARGET_FMT_lx "%016" PRIx64  #define TARGET_FMT_lx "%016" PRIx64
 #define TARGET_FMT_ld "%" PRId64  #define TARGET_FMT_ld "%" PRId64
 #define TARGET_FMT_lu "%" PRIu64  #define TARGET_FMT_lu "%" PRIu64
Line 60  typedef uint64_t target_ulong; Line 60  typedef uint64_t target_ulong;
 #error TARGET_LONG_SIZE undefined  #error TARGET_LONG_SIZE undefined
 #endif  #endif
   
 /* target_phys_addr_t is the type of a physical address (its size can  
    be different from 'target_ulong'). We have sizeof(target_phys_addr)  
    = max(sizeof(unsigned long),  
    sizeof(size_of_target_physical_address)) because we must pass a  
    host pointer to memory operations in some cases */  
   
 #if TARGET_PHYS_ADDR_BITS == 32  
 typedef uint32_t target_phys_addr_t;  
 #define TARGET_FMT_plx "%08x"  
 #elif TARGET_PHYS_ADDR_BITS == 64  
 typedef uint64_t target_phys_addr_t;  
 #define TARGET_FMT_plx "%016" PRIx64  
 #else  
 #error TARGET_PHYS_ADDR_BITS undefined  
 #endif  
   
 /* address in the RAM (different from a physical address) */  
 typedef unsigned long ram_addr_t;  
   
 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)  #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
   
 #define EXCP_INTERRUPT  0x10000 /* async interruption */  #define EXCP_INTERRUPT  0x10000 /* async interruption */
 #define EXCP_HLT        0x10001 /* hlt instruction reached */  #define EXCP_HLT        0x10001 /* hlt instruction reached */
 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */  #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
 #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */  #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
 #define MAX_BREAKPOINTS 32  
 #define MAX_WATCHPOINTS 32  
   
 #define TB_JMP_CACHE_BITS 12  #define TB_JMP_CACHE_BITS 12
 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)  #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
Line 99  typedef unsigned long ram_addr_t; Line 78  typedef unsigned long ram_addr_t;
 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)  #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)  #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
   
   #if !defined(CONFIG_USER_ONLY)
 #define CPU_TLB_BITS 8  #define CPU_TLB_BITS 8
 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)  #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
   
   #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
   #define CPU_TLB_ENTRY_BITS 4
   #else
   #define CPU_TLB_ENTRY_BITS 5
   #endif
   
 typedef struct CPUTLBEntry {  typedef struct CPUTLBEntry {
     /* bit 31 to TARGET_PAGE_BITS : virtual address      /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
        bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io         bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
                                               zone number                                      go directly to ram.
        bit 3                      : indicates that the entry is invalid         bit 3                      : indicates that the entry is invalid
        bit 2..0                   : zero         bit 2..0                   : zero
     */      */
     target_ulong addr_read;      target_ulong addr_read;
     target_ulong addr_write;      target_ulong addr_write;
     target_ulong addr_code;      target_ulong addr_code;
     /* addend to virtual address to get physical address */      /* Addend to virtual address to get host address.  IO accesses
     target_phys_addr_t addend;         use the corresponding iotlb value.  */
       unsigned long addend;
       /* padding to get a power of two size */
       uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 
                     (sizeof(target_ulong) * 3 + 
                      ((-sizeof(target_ulong) * 3) & (sizeof(unsigned long) - 1)) + 
                      sizeof(unsigned long))];
 } CPUTLBEntry;  } CPUTLBEntry;
   
   extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1];
   
   #define CPU_COMMON_TLB \
       /* The meaning of the MMU modes is defined in the target code. */   \
       CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
       target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
       target_ulong tlb_flush_addr;                                        \
       target_ulong tlb_flush_mask;
   
   #else
   
   #define CPU_COMMON_TLB
   
   #endif
   
   
   #ifdef HOST_WORDS_BIGENDIAN
   typedef struct icount_decr_u16 {
       uint16_t high;
       uint16_t low;
   } icount_decr_u16;
   #else
   typedef struct icount_decr_u16 {
       uint16_t low;
       uint16_t high;
   } icount_decr_u16;
   #endif
   
   struct kvm_run;
   struct KVMState;
   struct qemu_work_item;
   
   typedef struct CPUBreakpoint {
       target_ulong pc;
       int flags; /* BP_* */
       QTAILQ_ENTRY(CPUBreakpoint) entry;
   } CPUBreakpoint;
   
   typedef struct CPUWatchpoint {
       target_ulong vaddr;
       target_ulong len_mask;
       int flags; /* BP_* */
       QTAILQ_ENTRY(CPUWatchpoint) entry;
   } CPUWatchpoint;
   
   #define CPU_TEMP_BUF_NLONGS 128
 #define CPU_COMMON                                                      \  #define CPU_COMMON                                                      \
     struct TranslationBlock *current_tb; /* currently executing TB  */  \      struct TranslationBlock *current_tb; /* currently executing TB  */  \
     /* soft mmu support */                                              \      /* soft mmu support */                                              \
     /* in order to avoid passing too many arguments to the memory       \      /* in order to avoid passing too many arguments to the MMIO         \
        write helpers, we store some rarely used information in the CPU  \         helpers, we store some rarely used information in the CPU        \
        context) */                                                      \         context) */                                                      \
     unsigned long mem_write_pc; /* host pc at which the memory was      \      unsigned long mem_io_pc; /* host pc at which the memory was         \
                                    written */                           \                                  accessed */                             \
     target_ulong mem_write_vaddr; /* target virtual addr at which the   \      target_ulong mem_io_vaddr; /* target virtual addr at which the      \
                                      memory was written */              \                                       memory was accessed */             \
     /* The meaning of the MMU modes is defined in the target code. */   \      uint32_t halted; /* Nonzero if the CPU is in suspend state */       \
     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \      uint32_t interrupt_request;                                         \
       volatile sig_atomic_t exit_request;                                 \
       CPU_COMMON_TLB                                                      \
     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \      struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
       /* buffer for temporaries in the code generator */                  \
       long temp_buf[CPU_TEMP_BUF_NLONGS];                                 \
                                                                           \
       int64_t icount_extra; /* Instructions until next timer event.  */   \
       /* Number of cycles left, with interrupt flag in high bit.          \
          This allows a single read-compare-cbranch-write sequence to test \
          for both decrementer underflow and exceptions.  */               \
       union {                                                             \
           uint32_t u32;                                                   \
           icount_decr_u16 u16;                                            \
       } icount_decr;                                                      \
       uint32_t can_do_io; /* nonzero if memory mapped IO is safe.  */     \
                                                                         \                                                                          \
     /* from this point: preserved by CPU reset */                       \      /* from this point: preserved by CPU reset */                       \
     /* ice debug support */                                             \      /* ice debug support */                                             \
     target_ulong breakpoints[MAX_BREAKPOINTS];                          \      QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;            \
     int nb_breakpoints;                                                 \  
     int singlestep_enabled;                                             \      int singlestep_enabled;                                             \
                                                                         \                                                                          \
     struct {                                                            \      QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;            \
         target_ulong vaddr;                                             \      CPUWatchpoint *watchpoint_hit;                                      \
         target_phys_addr_t addend;                                      \                                                                          \
     } watchpoint[MAX_WATCHPOINTS];                                      \      struct GDBRegisterState *gdb_regs;                                  \
     int nb_watchpoints;                                                 \                                                                          \
     int watchpoint_hit;                                                 \      /* Core interrupt code */                                           \
       jmp_buf jmp_env;                                                    \
       int exception_index;                                                \
                                                                         \                                                                          \
     void *next_cpu; /* next CPU sharing TB cache */                     \      CPUState *next_cpu; /* next CPU sharing TB cache */                 \
     int cpu_index; /* CPU index (informative) */                        \      int cpu_index; /* CPU index (informative) */                        \
       uint32_t host_tid; /* host thread ID */                             \
       int numa_node; /* NUMA node this cpu is belonging to  */            \
       int nr_cores;  /* number of cores within this CPU package */        \
       int nr_threads;/* number of threads within this CPU */              \
       int running; /* Nonzero if cpu is currently running(usermode).  */  \
       int thread_id;                                                      \
     /* user data */                                                     \      /* user data */                                                     \
     void *opaque;                                                       \      void *opaque;                                                       \
                                                                         \                                                                          \
     const char *cpu_model_str;      uint32_t created;                                                   \
       uint32_t stop;   /* Stop request */                                 \
       uint32_t stopped; /* Artificially stopped */                        \
       struct QemuThread *thread;                                          \
       struct QemuCond *halt_cond;                                         \
       int thread_kicked;                                                  \
       struct qemu_work_item *queued_work_first, *queued_work_last;        \
       const char *cpu_model_str;                                          \
       struct KVMState *kvm_state;                                         \
       struct kvm_run *kvm_run;                                            \
       int kvm_fd;                                                         \
       int kvm_vcpu_dirty;
   
 #endif  #endif

Removed from v.1.1.1.5  
changed lines
  Added in v.1.1.1.11


unix.superglobalmegacorp.com