Diff for /qemu/cpu-defs.h between versions 1.1.1.1 and 1.1.1.5

version 1.1.1.1, 2018/04/24 16:37:52 version 1.1.1.5, 2018/04/24 16:47:33
Line 1 Line 1
 /*  /*
  * common defines for all CPUs   * common defines for all CPUs
  *    *
  * Copyright (c) 2003 Fabrice Bellard   * Copyright (c) 2003 Fabrice Bellard
  *   *
  * This library is free software; you can redistribute it and/or   * This library is free software; you can redistribute it and/or
Line 20 Line 20
 #ifndef CPU_DEFS_H  #ifndef CPU_DEFS_H
 #define CPU_DEFS_H  #define CPU_DEFS_H
   
   #ifndef NEED_CPU_H
   #error cpu.h included from common code
   #endif
   
 #include "config.h"  #include "config.h"
 #include <setjmp.h>  #include <setjmp.h>
 #include <inttypes.h>  #include <inttypes.h>
Line 29 Line 33
 #error TARGET_LONG_BITS must be defined before including this header  #error TARGET_LONG_BITS must be defined before including this header
 #endif  #endif
   
 #ifndef TARGET_PHYS_ADDR_BITS   #ifndef TARGET_PHYS_ADDR_BITS
 #if TARGET_LONG_BITS >= HOST_LONG_BITS  #if TARGET_LONG_BITS >= HOST_LONG_BITS
 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS  #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
 #else  #else
Line 44 Line 48
 typedef int32_t target_long;  typedef int32_t target_long;
 typedef uint32_t target_ulong;  typedef uint32_t target_ulong;
 #define TARGET_FMT_lx "%08x"  #define TARGET_FMT_lx "%08x"
   #define TARGET_FMT_ld "%d"
   #define TARGET_FMT_lu "%u"
 #elif TARGET_LONG_SIZE == 8  #elif TARGET_LONG_SIZE == 8
 typedef int64_t target_long;  typedef int64_t target_long;
 typedef uint64_t target_ulong;  typedef uint64_t target_ulong;
 #define TARGET_FMT_lx "%016llx"  #define TARGET_FMT_lx "%016" PRIx64
   #define TARGET_FMT_ld "%" PRId64
   #define TARGET_FMT_lu "%" PRIu64
 #else  #else
 #error TARGET_LONG_SIZE undefined  #error TARGET_LONG_SIZE undefined
 #endif  #endif
Line 60  typedef uint64_t target_ulong; Line 68  typedef uint64_t target_ulong;
   
 #if TARGET_PHYS_ADDR_BITS == 32  #if TARGET_PHYS_ADDR_BITS == 32
 typedef uint32_t target_phys_addr_t;  typedef uint32_t target_phys_addr_t;
   #define TARGET_FMT_plx "%08x"
 #elif TARGET_PHYS_ADDR_BITS == 64  #elif TARGET_PHYS_ADDR_BITS == 64
 typedef uint64_t target_phys_addr_t;  typedef uint64_t target_phys_addr_t;
   #define TARGET_FMT_plx "%016" PRIx64
 #else  #else
 #error TARGET_PHYS_ADDR_BITS undefined  #error TARGET_PHYS_ADDR_BITS undefined
 #endif  #endif
Line 74  typedef unsigned long ram_addr_t; Line 84  typedef unsigned long ram_addr_t;
 #define EXCP_INTERRUPT  0x10000 /* async interruption */  #define EXCP_INTERRUPT  0x10000 /* async interruption */
 #define EXCP_HLT        0x10001 /* hlt instruction reached */  #define EXCP_HLT        0x10001 /* hlt instruction reached */
 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */  #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
   #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
 #define MAX_BREAKPOINTS 32  #define MAX_BREAKPOINTS 32
   #define MAX_WATCHPOINTS 32
   
 #define CPU_TLB_SIZE 256  #define TB_JMP_CACHE_BITS 12
   #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
   
   /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
      addresses on the same page.  The top bits are the same.  This allows
      TLB invalidation to quickly clear a subset of the hash table.  */
   #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
   #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
   #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
   #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
   
   #define CPU_TLB_BITS 8
   #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
   
 typedef struct CPUTLBEntry {  typedef struct CPUTLBEntry {
     /* bit 31 to TARGET_PAGE_BITS : virtual address       /* bit 31 to TARGET_PAGE_BITS : virtual address
        bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io         bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
                                               zone number                                                zone number
        bit 3                      : indicates that the entry is invalid         bit 3                      : indicates that the entry is invalid
        bit 2..0                   : zero         bit 2..0                   : zero
     */      */
     target_ulong address;       target_ulong addr_read;
       target_ulong addr_write;
       target_ulong addr_code;
     /* addend to virtual address to get physical address */      /* addend to virtual address to get physical address */
     target_phys_addr_t addend;       target_phys_addr_t addend;
 } CPUTLBEntry;  } CPUTLBEntry;
   
   #define CPU_COMMON                                                      \
       struct TranslationBlock *current_tb; /* currently executing TB  */  \
       /* soft mmu support */                                              \
       /* in order to avoid passing too many arguments to the memory       \
          write helpers, we store some rarely used information in the CPU  \
          context) */                                                      \
       unsigned long mem_write_pc; /* host pc at which the memory was      \
                                      written */                           \
       target_ulong mem_write_vaddr; /* target virtual addr at which the   \
                                        memory was written */              \
       /* The meaning of the MMU modes is defined in the target code. */   \
       CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
       struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
                                                                           \
       /* from this point: preserved by CPU reset */                       \
       /* ice debug support */                                             \
       target_ulong breakpoints[MAX_BREAKPOINTS];                          \
       int nb_breakpoints;                                                 \
       int singlestep_enabled;                                             \
                                                                           \
       struct {                                                            \
           target_ulong vaddr;                                             \
           target_phys_addr_t addend;                                      \
       } watchpoint[MAX_WATCHPOINTS];                                      \
       int nb_watchpoints;                                                 \
       int watchpoint_hit;                                                 \
                                                                           \
       void *next_cpu; /* next CPU sharing TB cache */                     \
       int cpu_index; /* CPU index (informative) */                        \
       /* user data */                                                     \
       void *opaque;                                                       \
                                                                           \
       const char *cpu_model_str;
   
 #endif  #endif

Removed from v.1.1.1.1  
changed lines
  Added in v.1.1.1.5


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