File:  [Qemu by Fabrice Bellard] / qemu / cpu-defs.h
Revision 1.1.1.2 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 16:38:40 2018 UTC (23 months, 2 weeks ago) by root
Branches: qemu, MAIN
CVS tags: qemu0081, qemu0080, HEAD
qemu 0.8.0

    1: /*
    2:  * common defines for all CPUs
    3:  * 
    4:  * Copyright (c) 2003 Fabrice Bellard
    5:  *
    6:  * This library is free software; you can redistribute it and/or
    7:  * modify it under the terms of the GNU Lesser General Public
    8:  * License as published by the Free Software Foundation; either
    9:  * version 2 of the License, or (at your option) any later version.
   10:  *
   11:  * This library is distributed in the hope that it will be useful,
   12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   14:  * Lesser General Public License for more details.
   15:  *
   16:  * You should have received a copy of the GNU Lesser General Public
   17:  * License along with this library; if not, write to the Free Software
   18:  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
   19:  */
   20: #ifndef CPU_DEFS_H
   21: #define CPU_DEFS_H
   22: 
   23: #include "config.h"
   24: #include <setjmp.h>
   25: #include <inttypes.h>
   26: #include "osdep.h"
   27: 
   28: #ifndef TARGET_LONG_BITS
   29: #error TARGET_LONG_BITS must be defined before including this header
   30: #endif
   31: 
   32: #ifndef TARGET_PHYS_ADDR_BITS 
   33: #if TARGET_LONG_BITS >= HOST_LONG_BITS
   34: #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
   35: #else
   36: #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
   37: #endif
   38: #endif
   39: 
   40: #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
   41: 
   42: /* target_ulong is the type of a virtual address */
   43: #if TARGET_LONG_SIZE == 4
   44: typedef int32_t target_long;
   45: typedef uint32_t target_ulong;
   46: #define TARGET_FMT_lx "%08x"
   47: #elif TARGET_LONG_SIZE == 8
   48: typedef int64_t target_long;
   49: typedef uint64_t target_ulong;
   50: #define TARGET_FMT_lx "%016llx"
   51: #else
   52: #error TARGET_LONG_SIZE undefined
   53: #endif
   54: 
   55: /* target_phys_addr_t is the type of a physical address (its size can
   56:    be different from 'target_ulong'). We have sizeof(target_phys_addr)
   57:    = max(sizeof(unsigned long),
   58:    sizeof(size_of_target_physical_address)) because we must pass a
   59:    host pointer to memory operations in some cases */
   60: 
   61: #if TARGET_PHYS_ADDR_BITS == 32
   62: typedef uint32_t target_phys_addr_t;
   63: #elif TARGET_PHYS_ADDR_BITS == 64
   64: typedef uint64_t target_phys_addr_t;
   65: #else
   66: #error TARGET_PHYS_ADDR_BITS undefined
   67: #endif
   68: 
   69: /* address in the RAM (different from a physical address) */
   70: typedef unsigned long ram_addr_t;
   71: 
   72: #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
   73: 
   74: #define EXCP_INTERRUPT 	0x10000 /* async interruption */
   75: #define EXCP_HLT        0x10001 /* hlt instruction reached */
   76: #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
   77: #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
   78: #define MAX_BREAKPOINTS 32
   79: 
   80: #define TB_JMP_CACHE_BITS 12
   81: #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
   82: 
   83: #define CPU_TLB_BITS 8
   84: #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
   85: 
   86: typedef struct CPUTLBEntry {
   87:     /* bit 31 to TARGET_PAGE_BITS : virtual address 
   88:        bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
   89:                                               zone number
   90:        bit 3                      : indicates that the entry is invalid
   91:        bit 2..0                   : zero
   92:     */
   93:     target_ulong addr_read; 
   94:     target_ulong addr_write; 
   95:     target_ulong addr_code; 
   96:     /* addend to virtual address to get physical address */
   97:     target_phys_addr_t addend; 
   98: } CPUTLBEntry;
   99: 
  100: #define CPU_COMMON                                                      \
  101:     struct TranslationBlock *current_tb; /* currently executing TB  */  \
  102:     /* soft mmu support */                                              \
  103:     /* in order to avoid passing too many arguments to the memory       \
  104:        write helpers, we store some rarely used information in the CPU  \
  105:        context) */                                                      \
  106:     unsigned long mem_write_pc; /* host pc at which the memory was      \
  107:                                    written */                           \
  108:     target_ulong mem_write_vaddr; /* target virtual addr at which the   \
  109:                                      memory was written */              \
  110:     /* 0 = kernel, 1 = user */                                          \
  111:     CPUTLBEntry tlb_table[2][CPU_TLB_SIZE];                             \
  112:     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
  113:                                                                         \
  114:     /* from this point: preserved by CPU reset */                       \
  115:     /* ice debug support */                                             \
  116:     target_ulong breakpoints[MAX_BREAKPOINTS];                          \
  117:     int nb_breakpoints;                                                 \
  118:     int singlestep_enabled;                                             \
  119:                                                                         \
  120:     void *next_cpu; /* next CPU sharing TB cache */                     \
  121:     int cpu_index; /* CPU index (informative) */                        \
  122:     /* user data */                                                     \
  123:     void *opaque;
  124: 
  125: #endif

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