File:  [Qemu by Fabrice Bellard] / qemu / cpu-defs.h
Revision 1.1.1.6 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 16:50:53 2018 UTC (2 years, 3 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0100, HEAD
qemu 0.10.0

    1: /*
    2:  * common defines for all CPUs
    3:  *
    4:  * Copyright (c) 2003 Fabrice Bellard
    5:  *
    6:  * This library is free software; you can redistribute it and/or
    7:  * modify it under the terms of the GNU Lesser General Public
    8:  * License as published by the Free Software Foundation; either
    9:  * version 2 of the License, or (at your option) any later version.
   10:  *
   11:  * This library is distributed in the hope that it will be useful,
   12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   14:  * Lesser General Public License for more details.
   15:  *
   16:  * You should have received a copy of the GNU Lesser General Public
   17:  * License along with this library; if not, write to the Free Software
   18:  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
   19:  */
   20: #ifndef CPU_DEFS_H
   21: #define CPU_DEFS_H
   22: 
   23: #ifndef NEED_CPU_H
   24: #error cpu.h included from common code
   25: #endif
   26: 
   27: #include "config.h"
   28: #include <setjmp.h>
   29: #include <inttypes.h>
   30: #include "osdep.h"
   31: #include "sys-queue.h"
   32: 
   33: #ifndef TARGET_LONG_BITS
   34: #error TARGET_LONG_BITS must be defined before including this header
   35: #endif
   36: 
   37: #ifndef TARGET_PHYS_ADDR_BITS
   38: #if TARGET_LONG_BITS >= HOST_LONG_BITS
   39: #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
   40: #else
   41: #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
   42: #endif
   43: #endif
   44: 
   45: #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
   46: 
   47: /* target_ulong is the type of a virtual address */
   48: #if TARGET_LONG_SIZE == 4
   49: typedef int32_t target_long;
   50: typedef uint32_t target_ulong;
   51: #define TARGET_FMT_lx "%08x"
   52: #define TARGET_FMT_ld "%d"
   53: #define TARGET_FMT_lu "%u"
   54: #elif TARGET_LONG_SIZE == 8
   55: typedef int64_t target_long;
   56: typedef uint64_t target_ulong;
   57: #define TARGET_FMT_lx "%016" PRIx64
   58: #define TARGET_FMT_ld "%" PRId64
   59: #define TARGET_FMT_lu "%" PRIu64
   60: #else
   61: #error TARGET_LONG_SIZE undefined
   62: #endif
   63: 
   64: /* target_phys_addr_t is the type of a physical address (its size can
   65:    be different from 'target_ulong'). We have sizeof(target_phys_addr)
   66:    = max(sizeof(unsigned long),
   67:    sizeof(size_of_target_physical_address)) because we must pass a
   68:    host pointer to memory operations in some cases */
   69: 
   70: #if TARGET_PHYS_ADDR_BITS == 32
   71: typedef uint32_t target_phys_addr_t;
   72: #define TARGET_FMT_plx "%08x"
   73: #elif TARGET_PHYS_ADDR_BITS == 64
   74: typedef uint64_t target_phys_addr_t;
   75: #define TARGET_FMT_plx "%016" PRIx64
   76: #else
   77: #error TARGET_PHYS_ADDR_BITS undefined
   78: #endif
   79: 
   80: #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
   81: 
   82: #define EXCP_INTERRUPT 	0x10000 /* async interruption */
   83: #define EXCP_HLT        0x10001 /* hlt instruction reached */
   84: #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
   85: #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
   86: 
   87: #define TB_JMP_CACHE_BITS 12
   88: #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
   89: 
   90: /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
   91:    addresses on the same page.  The top bits are the same.  This allows
   92:    TLB invalidation to quickly clear a subset of the hash table.  */
   93: #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
   94: #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
   95: #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
   96: #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
   97: 
   98: #define CPU_TLB_BITS 8
   99: #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
  100: 
  101: #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
  102: #define CPU_TLB_ENTRY_BITS 4
  103: #else
  104: #define CPU_TLB_ENTRY_BITS 5
  105: #endif
  106: 
  107: typedef struct CPUTLBEntry {
  108:     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
  109:        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
  110:                                     go directly to ram.
  111:        bit 3                      : indicates that the entry is invalid
  112:        bit 2..0                   : zero
  113:     */
  114:     target_ulong addr_read;
  115:     target_ulong addr_write;
  116:     target_ulong addr_code;
  117:     /* Addend to virtual address to get physical address.  IO accesses
  118:        use the corresponding iotlb value.  */
  119: #if TARGET_PHYS_ADDR_BITS == 64
  120:     /* on i386 Linux make sure it is aligned */
  121:     target_phys_addr_t addend __attribute__((aligned(8)));
  122: #else
  123:     target_phys_addr_t addend;
  124: #endif
  125:     /* padding to get a power of two size */
  126:     uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 
  127:                   (sizeof(target_ulong) * 3 + 
  128:                    ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + 
  129:                    sizeof(target_phys_addr_t))];
  130: } CPUTLBEntry;
  131: 
  132: #ifdef WORDS_BIGENDIAN
  133: typedef struct icount_decr_u16 {
  134:     uint16_t high;
  135:     uint16_t low;
  136: } icount_decr_u16;
  137: #else
  138: typedef struct icount_decr_u16 {
  139:     uint16_t low;
  140:     uint16_t high;
  141: } icount_decr_u16;
  142: #endif
  143: 
  144: struct kvm_run;
  145: struct KVMState;
  146: 
  147: typedef struct CPUBreakpoint {
  148:     target_ulong pc;
  149:     int flags; /* BP_* */
  150:     TAILQ_ENTRY(CPUBreakpoint) entry;
  151: } CPUBreakpoint;
  152: 
  153: typedef struct CPUWatchpoint {
  154:     target_ulong vaddr;
  155:     target_ulong len_mask;
  156:     int flags; /* BP_* */
  157:     TAILQ_ENTRY(CPUWatchpoint) entry;
  158: } CPUWatchpoint;
  159: 
  160: #define CPU_TEMP_BUF_NLONGS 128
  161: #define CPU_COMMON                                                      \
  162:     struct TranslationBlock *current_tb; /* currently executing TB  */  \
  163:     /* soft mmu support */                                              \
  164:     /* in order to avoid passing too many arguments to the MMIO         \
  165:        helpers, we store some rarely used information in the CPU        \
  166:        context) */                                                      \
  167:     unsigned long mem_io_pc; /* host pc at which the memory was         \
  168:                                 accessed */                             \
  169:     target_ulong mem_io_vaddr; /* target virtual addr at which the      \
  170:                                      memory was accessed */             \
  171:     uint32_t halted; /* Nonzero if the CPU is in suspend state */       \
  172:     uint32_t interrupt_request;                                         \
  173:     /* The meaning of the MMU modes is defined in the target code. */   \
  174:     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
  175:     target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
  176:     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
  177:     /* buffer for temporaries in the code generator */                  \
  178:     long temp_buf[CPU_TEMP_BUF_NLONGS];                                 \
  179:                                                                         \
  180:     int64_t icount_extra; /* Instructions until next timer event.  */   \
  181:     /* Number of cycles left, with interrupt flag in high bit.          \
  182:        This allows a single read-compare-cbranch-write sequence to test \
  183:        for both decrementer underflow and exceptions.  */               \
  184:     union {                                                             \
  185:         uint32_t u32;                                                   \
  186:         icount_decr_u16 u16;                                            \
  187:     } icount_decr;                                                      \
  188:     uint32_t can_do_io; /* nonzero if memory mapped IO is safe.  */     \
  189:                                                                         \
  190:     /* from this point: preserved by CPU reset */                       \
  191:     /* ice debug support */                                             \
  192:     TAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;            \
  193:     int singlestep_enabled;                                             \
  194:                                                                         \
  195:     TAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;            \
  196:     CPUWatchpoint *watchpoint_hit;                                      \
  197:                                                                         \
  198:     struct GDBRegisterState *gdb_regs;                                  \
  199:                                                                         \
  200:     /* Core interrupt code */                                           \
  201:     jmp_buf jmp_env;                                                    \
  202:     int exception_index;                                                \
  203:                                                                         \
  204:     void *next_cpu; /* next CPU sharing TB cache */                     \
  205:     int cpu_index; /* CPU index (informative) */                        \
  206:     int running; /* Nonzero if cpu is currently running(usermode).  */  \
  207:     /* user data */                                                     \
  208:     void *opaque;                                                       \
  209:                                                                         \
  210:     const char *cpu_model_str;                                          \
  211:     struct KVMState *kvm_state;                                         \
  212:     struct kvm_run *kvm_run;                                            \
  213:     int kvm_fd;
  214: 
  215: #endif

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