File:  [Qemu by Fabrice Bellard] / qemu / cpu-defs.h
Revision 1.1.1.7 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 16:56:50 2018 UTC (3 years, 5 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0105, qemu0104, qemu0103, qemu0102, qemu0101, HEAD
qemu 0.10.1

    1: /*
    2:  * common defines for all CPUs
    3:  *
    4:  * Copyright (c) 2003 Fabrice Bellard
    5:  *
    6:  * This library is free software; you can redistribute it and/or
    7:  * modify it under the terms of the GNU Lesser General Public
    8:  * License as published by the Free Software Foundation; either
    9:  * version 2 of the License, or (at your option) any later version.
   10:  *
   11:  * This library is distributed in the hope that it will be useful,
   12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   14:  * Lesser General Public License for more details.
   15:  *
   16:  * You should have received a copy of the GNU Lesser General Public
   17:  * License along with this library; if not, write to the Free Software
   18:  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
   19:  */
   20: #ifndef CPU_DEFS_H
   21: #define CPU_DEFS_H
   22: 
   23: #ifndef NEED_CPU_H
   24: #error cpu.h included from common code
   25: #endif
   26: 
   27: #include "config.h"
   28: #include <setjmp.h>
   29: #include <inttypes.h>
   30: #include <signal.h>
   31: #include "osdep.h"
   32: #include "sys-queue.h"
   33: 
   34: #ifndef TARGET_LONG_BITS
   35: #error TARGET_LONG_BITS must be defined before including this header
   36: #endif
   37: 
   38: #ifndef TARGET_PHYS_ADDR_BITS
   39: #if TARGET_LONG_BITS >= HOST_LONG_BITS
   40: #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
   41: #else
   42: #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
   43: #endif
   44: #endif
   45: 
   46: #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
   47: 
   48: /* target_ulong is the type of a virtual address */
   49: #if TARGET_LONG_SIZE == 4
   50: typedef int32_t target_long;
   51: typedef uint32_t target_ulong;
   52: #define TARGET_FMT_lx "%08x"
   53: #define TARGET_FMT_ld "%d"
   54: #define TARGET_FMT_lu "%u"
   55: #elif TARGET_LONG_SIZE == 8
   56: typedef int64_t target_long;
   57: typedef uint64_t target_ulong;
   58: #define TARGET_FMT_lx "%016" PRIx64
   59: #define TARGET_FMT_ld "%" PRId64
   60: #define TARGET_FMT_lu "%" PRIu64
   61: #else
   62: #error TARGET_LONG_SIZE undefined
   63: #endif
   64: 
   65: /* target_phys_addr_t is the type of a physical address (its size can
   66:    be different from 'target_ulong'). We have sizeof(target_phys_addr)
   67:    = max(sizeof(unsigned long),
   68:    sizeof(size_of_target_physical_address)) because we must pass a
   69:    host pointer to memory operations in some cases */
   70: 
   71: #if TARGET_PHYS_ADDR_BITS == 32
   72: typedef uint32_t target_phys_addr_t;
   73: #define TARGET_FMT_plx "%08x"
   74: #elif TARGET_PHYS_ADDR_BITS == 64
   75: typedef uint64_t target_phys_addr_t;
   76: #define TARGET_FMT_plx "%016" PRIx64
   77: #else
   78: #error TARGET_PHYS_ADDR_BITS undefined
   79: #endif
   80: 
   81: #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
   82: 
   83: #define EXCP_INTERRUPT 	0x10000 /* async interruption */
   84: #define EXCP_HLT        0x10001 /* hlt instruction reached */
   85: #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
   86: #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
   87: 
   88: #define TB_JMP_CACHE_BITS 12
   89: #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
   90: 
   91: /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
   92:    addresses on the same page.  The top bits are the same.  This allows
   93:    TLB invalidation to quickly clear a subset of the hash table.  */
   94: #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
   95: #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
   96: #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
   97: #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
   98: 
   99: #define CPU_TLB_BITS 8
  100: #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
  101: 
  102: #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
  103: #define CPU_TLB_ENTRY_BITS 4
  104: #else
  105: #define CPU_TLB_ENTRY_BITS 5
  106: #endif
  107: 
  108: typedef struct CPUTLBEntry {
  109:     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
  110:        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
  111:                                     go directly to ram.
  112:        bit 3                      : indicates that the entry is invalid
  113:        bit 2..0                   : zero
  114:     */
  115:     target_ulong addr_read;
  116:     target_ulong addr_write;
  117:     target_ulong addr_code;
  118:     /* Addend to virtual address to get physical address.  IO accesses
  119:        use the corresponding iotlb value.  */
  120: #if TARGET_PHYS_ADDR_BITS == 64
  121:     /* on i386 Linux make sure it is aligned */
  122:     target_phys_addr_t addend __attribute__((aligned(8)));
  123: #else
  124:     target_phys_addr_t addend;
  125: #endif
  126:     /* padding to get a power of two size */
  127:     uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 
  128:                   (sizeof(target_ulong) * 3 + 
  129:                    ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + 
  130:                    sizeof(target_phys_addr_t))];
  131: } CPUTLBEntry;
  132: 
  133: #ifdef WORDS_BIGENDIAN
  134: typedef struct icount_decr_u16 {
  135:     uint16_t high;
  136:     uint16_t low;
  137: } icount_decr_u16;
  138: #else
  139: typedef struct icount_decr_u16 {
  140:     uint16_t low;
  141:     uint16_t high;
  142: } icount_decr_u16;
  143: #endif
  144: 
  145: struct kvm_run;
  146: struct KVMState;
  147: 
  148: typedef struct CPUBreakpoint {
  149:     target_ulong pc;
  150:     int flags; /* BP_* */
  151:     TAILQ_ENTRY(CPUBreakpoint) entry;
  152: } CPUBreakpoint;
  153: 
  154: typedef struct CPUWatchpoint {
  155:     target_ulong vaddr;
  156:     target_ulong len_mask;
  157:     int flags; /* BP_* */
  158:     TAILQ_ENTRY(CPUWatchpoint) entry;
  159: } CPUWatchpoint;
  160: 
  161: #define CPU_TEMP_BUF_NLONGS 128
  162: #define CPU_COMMON                                                      \
  163:     struct TranslationBlock *current_tb; /* currently executing TB  */  \
  164:     /* soft mmu support */                                              \
  165:     /* in order to avoid passing too many arguments to the MMIO         \
  166:        helpers, we store some rarely used information in the CPU        \
  167:        context) */                                                      \
  168:     unsigned long mem_io_pc; /* host pc at which the memory was         \
  169:                                 accessed */                             \
  170:     target_ulong mem_io_vaddr; /* target virtual addr at which the      \
  171:                                      memory was accessed */             \
  172:     uint32_t halted; /* Nonzero if the CPU is in suspend state */       \
  173:     uint32_t interrupt_request;                                         \
  174:     volatile sig_atomic_t exit_request;                                 \
  175:     /* The meaning of the MMU modes is defined in the target code. */   \
  176:     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
  177:     target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
  178:     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
  179:     /* buffer for temporaries in the code generator */                  \
  180:     long temp_buf[CPU_TEMP_BUF_NLONGS];                                 \
  181:                                                                         \
  182:     int64_t icount_extra; /* Instructions until next timer event.  */   \
  183:     /* Number of cycles left, with interrupt flag in high bit.          \
  184:        This allows a single read-compare-cbranch-write sequence to test \
  185:        for both decrementer underflow and exceptions.  */               \
  186:     union {                                                             \
  187:         uint32_t u32;                                                   \
  188:         icount_decr_u16 u16;                                            \
  189:     } icount_decr;                                                      \
  190:     uint32_t can_do_io; /* nonzero if memory mapped IO is safe.  */     \
  191:                                                                         \
  192:     /* from this point: preserved by CPU reset */                       \
  193:     /* ice debug support */                                             \
  194:     TAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;            \
  195:     int singlestep_enabled;                                             \
  196:                                                                         \
  197:     TAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;            \
  198:     CPUWatchpoint *watchpoint_hit;                                      \
  199:                                                                         \
  200:     struct GDBRegisterState *gdb_regs;                                  \
  201:                                                                         \
  202:     /* Core interrupt code */                                           \
  203:     jmp_buf jmp_env;                                                    \
  204:     int exception_index;                                                \
  205:                                                                         \
  206:     void *next_cpu; /* next CPU sharing TB cache */                     \
  207:     int cpu_index; /* CPU index (informative) */                        \
  208:     int running; /* Nonzero if cpu is currently running(usermode).  */  \
  209:     /* user data */                                                     \
  210:     void *opaque;                                                       \
  211:                                                                         \
  212:     const char *cpu_model_str;                                          \
  213:     struct KVMState *kvm_state;                                         \
  214:     struct kvm_run *kvm_run;                                            \
  215:     int kvm_fd;
  216: 
  217: #endif

unix.superglobalmegacorp.com