Annotation of qemu/cpu-exec.c, revision 1.1.1.3
1.1 root 1: /*
2: * i386 emulator main execution loop
3: *
4: * Copyright (c) 2003-2005 Fabrice Bellard
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #include "config.h"
21: #include "exec.h"
22: #include "disas.h"
23:
24: #if !defined(CONFIG_SOFTMMU)
25: #undef EAX
26: #undef ECX
27: #undef EDX
28: #undef EBX
29: #undef ESP
30: #undef EBP
31: #undef ESI
32: #undef EDI
33: #undef EIP
34: #include <signal.h>
35: #include <sys/ucontext.h>
36: #endif
37:
38: int tb_invalidated_flag;
39:
40: //#define DEBUG_EXEC
41: //#define DEBUG_SIGNAL
42:
43: #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44: /* XXX: unify with i386 target */
45: void cpu_loop_exit(void)
46: {
47: longjmp(env->jmp_env, 1);
48: }
49: #endif
50: #ifndef TARGET_SPARC
51: #define reg_T2
52: #endif
53:
54: /* exit the current TB from a signal handler. The host registers are
55: restored in a state compatible with the CPU emulator
56: */
57: void cpu_resume_from_signal(CPUState *env1, void *puc)
58: {
59: #if !defined(CONFIG_SOFTMMU)
60: struct ucontext *uc = puc;
61: #endif
62:
63: env = env1;
64:
65: /* XXX: restore cpu registers saved in host registers */
66:
67: #if !defined(CONFIG_SOFTMMU)
68: if (puc) {
69: /* XXX: use siglongjmp ? */
70: sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71: }
72: #endif
73: longjmp(env->jmp_env, 1);
74: }
75:
1.1.1.2 root 76:
77: static TranslationBlock *tb_find_slow(target_ulong pc,
78: target_ulong cs_base,
79: unsigned int flags)
80: {
81: TranslationBlock *tb, **ptb1;
82: int code_gen_size;
83: unsigned int h;
84: target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85: uint8_t *tc_ptr;
86:
87: spin_lock(&tb_lock);
88:
89: tb_invalidated_flag = 0;
90:
91: regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92:
93: /* find translated block using physical mappings */
94: phys_pc = get_phys_addr_code(env, pc);
95: phys_page1 = phys_pc & TARGET_PAGE_MASK;
96: phys_page2 = -1;
97: h = tb_phys_hash_func(phys_pc);
98: ptb1 = &tb_phys_hash[h];
99: for(;;) {
100: tb = *ptb1;
101: if (!tb)
102: goto not_found;
103: if (tb->pc == pc &&
104: tb->page_addr[0] == phys_page1 &&
105: tb->cs_base == cs_base &&
106: tb->flags == flags) {
107: /* check next page if needed */
108: if (tb->page_addr[1] != -1) {
109: virt_page2 = (pc & TARGET_PAGE_MASK) +
110: TARGET_PAGE_SIZE;
111: phys_page2 = get_phys_addr_code(env, virt_page2);
112: if (tb->page_addr[1] == phys_page2)
113: goto found;
114: } else {
115: goto found;
116: }
117: }
118: ptb1 = &tb->phys_hash_next;
119: }
120: not_found:
121: /* if no translated code available, then translate it now */
122: tb = tb_alloc(pc);
123: if (!tb) {
124: /* flush must be done */
125: tb_flush(env);
126: /* cannot fail at this point */
127: tb = tb_alloc(pc);
128: /* don't forget to invalidate previous TB info */
129: tb_invalidated_flag = 1;
130: }
131: tc_ptr = code_gen_ptr;
132: tb->tc_ptr = tc_ptr;
133: tb->cs_base = cs_base;
134: tb->flags = flags;
135: cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136: code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137:
138: /* check next page if needed */
139: virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140: phys_page2 = -1;
141: if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142: phys_page2 = get_phys_addr_code(env, virt_page2);
143: }
144: tb_link_phys(tb, phys_pc, phys_page2);
145:
146: found:
147: /* we add the TB in the virtual pc hash table */
148: env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149: spin_unlock(&tb_lock);
150: return tb;
151: }
152:
153: static inline TranslationBlock *tb_find_fast(void)
154: {
155: TranslationBlock *tb;
156: target_ulong cs_base, pc;
157: unsigned int flags;
158:
159: /* we record a subset of the CPU state. It will
160: always be the same before a given translated block
161: is executed. */
162: #if defined(TARGET_I386)
163: flags = env->hflags;
164: flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165: cs_base = env->segs[R_CS].base;
166: pc = cs_base + env->eip;
167: #elif defined(TARGET_ARM)
168: flags = env->thumb | (env->vfp.vec_len << 1)
169: | (env->vfp.vec_stride << 4);
170: if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171: flags |= (1 << 6);
1.1.1.3 ! root 172: if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
! 173: flags |= (1 << 7);
1.1.1.2 root 174: cs_base = 0;
175: pc = env->regs[15];
176: #elif defined(TARGET_SPARC)
177: #ifdef TARGET_SPARC64
178: flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
179: #else
180: flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
181: #endif
182: cs_base = env->npc;
183: pc = env->pc;
184: #elif defined(TARGET_PPC)
185: flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
186: (msr_se << MSR_SE) | (msr_le << MSR_LE);
187: cs_base = 0;
188: pc = env->nip;
189: #elif defined(TARGET_MIPS)
1.1.1.3 ! root 190: flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
1.1.1.2 root 191: cs_base = 0;
192: pc = env->PC;
1.1.1.3 ! root 193: #elif defined(TARGET_SH4)
! 194: flags = env->sr & (SR_MD | SR_RB);
! 195: cs_base = 0; /* XXXXX */
! 196: pc = env->pc;
1.1.1.2 root 197: #else
198: #error unsupported CPU
199: #endif
200: tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
201: if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
202: tb->flags != flags, 0)) {
203: tb = tb_find_slow(pc, cs_base, flags);
204: /* Note: we do it here to avoid a gcc bug on Mac OS X when
205: doing it in tb_find_slow */
206: if (tb_invalidated_flag) {
207: /* as some TB could have been invalidated because
208: of memory exceptions while generating the code, we
209: must recompute the hash index here */
210: T0 = 0;
211: }
212: }
213: return tb;
214: }
215:
216:
1.1 root 217: /* main execution loop */
218:
219: int cpu_exec(CPUState *env1)
220: {
221: int saved_T0, saved_T1;
222: #if defined(reg_T2)
223: int saved_T2;
224: #endif
225: CPUState *saved_env;
226: #if defined(TARGET_I386)
227: #ifdef reg_EAX
228: int saved_EAX;
229: #endif
230: #ifdef reg_ECX
231: int saved_ECX;
232: #endif
233: #ifdef reg_EDX
234: int saved_EDX;
235: #endif
236: #ifdef reg_EBX
237: int saved_EBX;
238: #endif
239: #ifdef reg_ESP
240: int saved_ESP;
241: #endif
242: #ifdef reg_EBP
243: int saved_EBP;
244: #endif
245: #ifdef reg_ESI
246: int saved_ESI;
247: #endif
248: #ifdef reg_EDI
249: int saved_EDI;
250: #endif
251: #elif defined(TARGET_SPARC)
252: #if defined(reg_REGWPTR)
253: uint32_t *saved_regwptr;
254: #endif
255: #endif
256: #ifdef __sparc__
257: int saved_i7, tmp_T0;
258: #endif
1.1.1.2 root 259: int ret, interrupt_request;
1.1 root 260: void (*gen_func)(void);
1.1.1.2 root 261: TranslationBlock *tb;
1.1 root 262: uint8_t *tc_ptr;
1.1.1.2 root 263:
264: #if defined(TARGET_I386)
265: /* handle exit of HALTED state */
266: if (env1->hflags & HF_HALTED_MASK) {
267: /* disable halt condition */
268: if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
269: (env1->eflags & IF_MASK)) {
270: env1->hflags &= ~HF_HALTED_MASK;
271: } else {
272: return EXCP_HALTED;
273: }
274: }
275: #elif defined(TARGET_PPC)
276: if (env1->halted) {
277: if (env1->msr[MSR_EE] &&
278: (env1->interrupt_request &
279: (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
280: env1->halted = 0;
281: } else {
282: return EXCP_HALTED;
283: }
284: }
285: #elif defined(TARGET_SPARC)
286: if (env1->halted) {
287: if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
288: (env1->psret != 0)) {
289: env1->halted = 0;
290: } else {
291: return EXCP_HALTED;
292: }
293: }
294: #elif defined(TARGET_ARM)
295: if (env1->halted) {
296: /* An interrupt wakes the CPU even if the I and F CPSR bits are
297: set. */
298: if (env1->interrupt_request
299: & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
300: env1->halted = 0;
301: } else {
302: return EXCP_HALTED;
303: }
304: }
305: #elif defined(TARGET_MIPS)
306: if (env1->halted) {
307: if (env1->interrupt_request &
308: (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
309: env1->halted = 0;
310: } else {
311: return EXCP_HALTED;
312: }
313: }
314: #endif
315:
316: cpu_single_env = env1;
1.1 root 317:
318: /* first we save global registers */
319: saved_env = env;
320: env = env1;
321: saved_T0 = T0;
322: saved_T1 = T1;
323: #if defined(reg_T2)
324: saved_T2 = T2;
325: #endif
326: #ifdef __sparc__
327: /* we also save i7 because longjmp may not restore it */
328: asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
329: #endif
330:
331: #if defined(TARGET_I386)
332: #ifdef reg_EAX
333: saved_EAX = EAX;
334: #endif
335: #ifdef reg_ECX
336: saved_ECX = ECX;
337: #endif
338: #ifdef reg_EDX
339: saved_EDX = EDX;
340: #endif
341: #ifdef reg_EBX
342: saved_EBX = EBX;
343: #endif
344: #ifdef reg_ESP
345: saved_ESP = ESP;
346: #endif
347: #ifdef reg_EBP
348: saved_EBP = EBP;
349: #endif
350: #ifdef reg_ESI
351: saved_ESI = ESI;
352: #endif
353: #ifdef reg_EDI
354: saved_EDI = EDI;
355: #endif
356:
357: env_to_regs();
358: /* put eflags in CPU temporary format */
359: CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
360: DF = 1 - (2 * ((env->eflags >> 10) & 1));
361: CC_OP = CC_OP_EFLAGS;
362: env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
363: #elif defined(TARGET_ARM)
364: #elif defined(TARGET_SPARC)
365: #if defined(reg_REGWPTR)
366: saved_regwptr = REGWPTR;
367: #endif
368: #elif defined(TARGET_PPC)
369: #elif defined(TARGET_MIPS)
1.1.1.3 ! root 370: #elif defined(TARGET_SH4)
! 371: /* XXXXX */
1.1 root 372: #else
373: #error unsupported target CPU
374: #endif
375: env->exception_index = -1;
376:
377: /* prepare setjmp context for exception handling */
378: for(;;) {
379: if (setjmp(env->jmp_env) == 0) {
380: env->current_tb = NULL;
381: /* if an exception is pending, we execute it here */
382: if (env->exception_index >= 0) {
383: if (env->exception_index >= EXCP_INTERRUPT) {
384: /* exit request from the cpu execution loop */
385: ret = env->exception_index;
386: break;
387: } else if (env->user_mode_only) {
388: /* if user mode only, we simulate a fake exception
389: which will be hanlded outside the cpu execution
390: loop */
391: #if defined(TARGET_I386)
392: do_interrupt_user(env->exception_index,
393: env->exception_is_int,
394: env->error_code,
395: env->exception_next_eip);
396: #endif
397: ret = env->exception_index;
398: break;
399: } else {
400: #if defined(TARGET_I386)
401: /* simulate a real cpu exception. On i386, it can
402: trigger new exceptions, but we do not handle
403: double or triple faults yet. */
404: do_interrupt(env->exception_index,
405: env->exception_is_int,
406: env->error_code,
407: env->exception_next_eip, 0);
408: #elif defined(TARGET_PPC)
409: do_interrupt(env);
410: #elif defined(TARGET_MIPS)
411: do_interrupt(env);
412: #elif defined(TARGET_SPARC)
413: do_interrupt(env->exception_index);
1.1.1.2 root 414: #elif defined(TARGET_ARM)
415: do_interrupt(env);
1.1.1.3 ! root 416: #elif defined(TARGET_SH4)
! 417: do_interrupt(env);
1.1 root 418: #endif
419: }
420: env->exception_index = -1;
421: }
422: #ifdef USE_KQEMU
423: if (kqemu_is_ok(env) && env->interrupt_request == 0) {
424: int ret;
425: env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
426: ret = kqemu_cpu_exec(env);
427: /* put eflags in CPU temporary format */
428: CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
429: DF = 1 - (2 * ((env->eflags >> 10) & 1));
430: CC_OP = CC_OP_EFLAGS;
431: env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
432: if (ret == 1) {
433: /* exception */
434: longjmp(env->jmp_env, 1);
435: } else if (ret == 2) {
436: /* softmmu execution needed */
437: } else {
438: if (env->interrupt_request != 0) {
439: /* hardware interrupt will be executed just after */
440: } else {
441: /* otherwise, we restart */
442: longjmp(env->jmp_env, 1);
443: }
444: }
445: }
446: #endif
447:
448: T0 = 0; /* force lookup of first TB */
449: for(;;) {
450: #ifdef __sparc__
451: /* g1 can be modified by some libc? functions */
452: tmp_T0 = T0;
453: #endif
454: interrupt_request = env->interrupt_request;
455: if (__builtin_expect(interrupt_request, 0)) {
456: #if defined(TARGET_I386)
457: /* if hardware interrupt pending, we execute it */
458: if ((interrupt_request & CPU_INTERRUPT_HARD) &&
459: (env->eflags & IF_MASK) &&
460: !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
461: int intno;
462: env->interrupt_request &= ~CPU_INTERRUPT_HARD;
463: intno = cpu_get_pic_interrupt(env);
464: if (loglevel & CPU_LOG_TB_IN_ASM) {
465: fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
466: }
467: do_interrupt(intno, 0, 0, 0, 1);
468: /* ensure that no TB jump will be modified as
469: the program flow was changed */
470: #ifdef __sparc__
471: tmp_T0 = 0;
472: #else
473: T0 = 0;
474: #endif
475: }
476: #elif defined(TARGET_PPC)
477: #if 0
478: if ((interrupt_request & CPU_INTERRUPT_RESET)) {
479: cpu_ppc_reset(env);
480: }
481: #endif
482: if (msr_ee != 0) {
1.1.1.2 root 483: if ((interrupt_request & CPU_INTERRUPT_HARD)) {
1.1 root 484: /* Raise it */
485: env->exception_index = EXCP_EXTERNAL;
486: env->error_code = 0;
487: do_interrupt(env);
1.1.1.2 root 488: env->interrupt_request &= ~CPU_INTERRUPT_HARD;
489: #ifdef __sparc__
490: tmp_T0 = 0;
491: #else
492: T0 = 0;
493: #endif
494: } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
495: /* Raise it */
496: env->exception_index = EXCP_DECR;
497: env->error_code = 0;
498: do_interrupt(env);
1.1 root 499: env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
1.1.1.2 root 500: #ifdef __sparc__
501: tmp_T0 = 0;
502: #else
503: T0 = 0;
504: #endif
505: }
1.1 root 506: }
507: #elif defined(TARGET_MIPS)
508: if ((interrupt_request & CPU_INTERRUPT_HARD) &&
509: (env->CP0_Status & (1 << CP0St_IE)) &&
510: (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
511: !(env->hflags & MIPS_HFLAG_EXL) &&
512: !(env->hflags & MIPS_HFLAG_ERL) &&
513: !(env->hflags & MIPS_HFLAG_DM)) {
514: /* Raise it */
515: env->exception_index = EXCP_EXT_INTERRUPT;
516: env->error_code = 0;
517: do_interrupt(env);
518: env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1.1.1.2 root 519: #ifdef __sparc__
520: tmp_T0 = 0;
521: #else
522: T0 = 0;
523: #endif
1.1 root 524: }
525: #elif defined(TARGET_SPARC)
526: if ((interrupt_request & CPU_INTERRUPT_HARD) &&
527: (env->psret != 0)) {
528: int pil = env->interrupt_index & 15;
529: int type = env->interrupt_index & 0xf0;
530:
531: if (((type == TT_EXTINT) &&
532: (pil == 15 || pil > env->psrpil)) ||
533: type != TT_EXTINT) {
534: env->interrupt_request &= ~CPU_INTERRUPT_HARD;
535: do_interrupt(env->interrupt_index);
536: env->interrupt_index = 0;
1.1.1.2 root 537: #ifdef __sparc__
538: tmp_T0 = 0;
539: #else
540: T0 = 0;
541: #endif
1.1 root 542: }
543: } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
544: //do_interrupt(0, 0, 0, 0, 0);
545: env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
1.1.1.2 root 546: } else if (interrupt_request & CPU_INTERRUPT_HALT) {
547: env1->halted = 1;
548: return EXCP_HALTED;
549: }
550: #elif defined(TARGET_ARM)
551: if (interrupt_request & CPU_INTERRUPT_FIQ
552: && !(env->uncached_cpsr & CPSR_F)) {
553: env->exception_index = EXCP_FIQ;
554: do_interrupt(env);
555: }
556: if (interrupt_request & CPU_INTERRUPT_HARD
557: && !(env->uncached_cpsr & CPSR_I)) {
558: env->exception_index = EXCP_IRQ;
559: do_interrupt(env);
560: }
1.1.1.3 ! root 561: #elif defined(TARGET_SH4)
! 562: /* XXXXX */
1.1 root 563: #endif
1.1.1.2 root 564: if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
1.1 root 565: env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
566: /* ensure that no TB jump will be modified as
567: the program flow was changed */
568: #ifdef __sparc__
569: tmp_T0 = 0;
570: #else
571: T0 = 0;
572: #endif
573: }
574: if (interrupt_request & CPU_INTERRUPT_EXIT) {
575: env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
576: env->exception_index = EXCP_INTERRUPT;
577: cpu_loop_exit();
578: }
579: }
580: #ifdef DEBUG_EXEC
1.1.1.2 root 581: if ((loglevel & CPU_LOG_TB_CPU)) {
1.1 root 582: #if defined(TARGET_I386)
583: /* restore flags in standard format */
584: #ifdef reg_EAX
585: env->regs[R_EAX] = EAX;
586: #endif
587: #ifdef reg_EBX
588: env->regs[R_EBX] = EBX;
589: #endif
590: #ifdef reg_ECX
591: env->regs[R_ECX] = ECX;
592: #endif
593: #ifdef reg_EDX
594: env->regs[R_EDX] = EDX;
595: #endif
596: #ifdef reg_ESI
597: env->regs[R_ESI] = ESI;
598: #endif
599: #ifdef reg_EDI
600: env->regs[R_EDI] = EDI;
601: #endif
602: #ifdef reg_EBP
603: env->regs[R_EBP] = EBP;
604: #endif
605: #ifdef reg_ESP
606: env->regs[R_ESP] = ESP;
607: #endif
608: env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
609: cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
610: env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
611: #elif defined(TARGET_ARM)
612: cpu_dump_state(env, logfile, fprintf, 0);
613: #elif defined(TARGET_SPARC)
614: REGWPTR = env->regbase + (env->cwp * 16);
615: env->regwptr = REGWPTR;
616: cpu_dump_state(env, logfile, fprintf, 0);
617: #elif defined(TARGET_PPC)
618: cpu_dump_state(env, logfile, fprintf, 0);
619: #elif defined(TARGET_MIPS)
620: cpu_dump_state(env, logfile, fprintf, 0);
1.1.1.3 ! root 621: #elif defined(TARGET_SH4)
! 622: cpu_dump_state(env, logfile, fprintf, 0);
1.1 root 623: #else
624: #error unsupported target CPU
625: #endif
626: }
627: #endif
1.1.1.2 root 628: tb = tb_find_fast();
1.1 root 629: #ifdef DEBUG_EXEC
630: if ((loglevel & CPU_LOG_EXEC)) {
631: fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
632: (long)tb->tc_ptr, tb->pc,
633: lookup_symbol(tb->pc));
634: }
635: #endif
636: #ifdef __sparc__
637: T0 = tmp_T0;
638: #endif
1.1.1.2 root 639: /* see if we can patch the calling TB. When the TB
640: spans two pages, we cannot safely do a direct
641: jump. */
1.1 root 642: {
1.1.1.2 root 643: if (T0 != 0 &&
1.1.1.3 ! root 644: #if USE_KQEMU
! 645: (env->kqemu_enabled != 2) &&
! 646: #endif
1.1.1.2 root 647: tb->page_addr[1] == -1
1.1 root 648: #if defined(TARGET_I386) && defined(USE_CODE_COPY)
649: && (tb->cflags & CF_CODE_COPY) ==
650: (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
651: #endif
652: ) {
653: spin_lock(&tb_lock);
654: tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
655: #if defined(USE_CODE_COPY)
656: /* propagates the FP use info */
657: ((TranslationBlock *)(T0 & ~3))->cflags |=
658: (tb->cflags & CF_FP_USED);
659: #endif
660: spin_unlock(&tb_lock);
661: }
662: }
663: tc_ptr = tb->tc_ptr;
664: env->current_tb = tb;
665: /* execute the generated code */
666: gen_func = (void *)tc_ptr;
667: #if defined(__sparc__)
668: __asm__ __volatile__("call %0\n\t"
669: "mov %%o7,%%i0"
670: : /* no outputs */
671: : "r" (gen_func)
672: : "i0", "i1", "i2", "i3", "i4", "i5");
673: #elif defined(__arm__)
674: asm volatile ("mov pc, %0\n\t"
675: ".global exec_loop\n\t"
676: "exec_loop:\n\t"
677: : /* no outputs */
678: : "r" (gen_func)
679: : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
680: #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
681: {
682: if (!(tb->cflags & CF_CODE_COPY)) {
683: if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
684: save_native_fp_state(env);
685: }
686: gen_func();
687: } else {
688: if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
689: restore_native_fp_state(env);
690: }
691: /* we work with native eflags */
692: CC_SRC = cc_table[CC_OP].compute_all();
693: CC_OP = CC_OP_EFLAGS;
694: asm(".globl exec_loop\n"
695: "\n"
696: "debug1:\n"
697: " pushl %%ebp\n"
698: " fs movl %10, %9\n"
699: " fs movl %11, %%eax\n"
700: " andl $0x400, %%eax\n"
701: " fs orl %8, %%eax\n"
702: " pushl %%eax\n"
703: " popf\n"
704: " fs movl %%esp, %12\n"
705: " fs movl %0, %%eax\n"
706: " fs movl %1, %%ecx\n"
707: " fs movl %2, %%edx\n"
708: " fs movl %3, %%ebx\n"
709: " fs movl %4, %%esp\n"
710: " fs movl %5, %%ebp\n"
711: " fs movl %6, %%esi\n"
712: " fs movl %7, %%edi\n"
713: " fs jmp *%9\n"
714: "exec_loop:\n"
715: " fs movl %%esp, %4\n"
716: " fs movl %12, %%esp\n"
717: " fs movl %%eax, %0\n"
718: " fs movl %%ecx, %1\n"
719: " fs movl %%edx, %2\n"
720: " fs movl %%ebx, %3\n"
721: " fs movl %%ebp, %5\n"
722: " fs movl %%esi, %6\n"
723: " fs movl %%edi, %7\n"
724: " pushf\n"
725: " popl %%eax\n"
726: " movl %%eax, %%ecx\n"
727: " andl $0x400, %%ecx\n"
728: " shrl $9, %%ecx\n"
729: " andl $0x8d5, %%eax\n"
730: " fs movl %%eax, %8\n"
731: " movl $1, %%eax\n"
732: " subl %%ecx, %%eax\n"
733: " fs movl %%eax, %11\n"
734: " fs movl %9, %%ebx\n" /* get T0 value */
735: " popl %%ebp\n"
736: :
737: : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
738: "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
739: "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
740: "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
741: "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
742: "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
743: "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
744: "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
745: "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
746: "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
747: "a" (gen_func),
748: "m" (*(uint8_t *)offsetof(CPUState, df)),
749: "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
750: : "%ecx", "%edx"
751: );
752: }
753: }
754: #elif defined(__ia64)
755: struct fptr {
756: void *ip;
757: void *gp;
758: } fp;
759:
760: fp.ip = tc_ptr;
761: fp.gp = code_gen_buffer + 2 * (1 << 20);
762: (*(void (*)(void)) &fp)();
763: #else
764: gen_func();
765: #endif
766: env->current_tb = NULL;
767: /* reset soft MMU for next block (it can currently
768: only be set by a memory fault) */
769: #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
770: if (env->hflags & HF_SOFTMMU_MASK) {
771: env->hflags &= ~HF_SOFTMMU_MASK;
772: /* do not allow linking to another block */
773: T0 = 0;
774: }
775: #endif
1.1.1.3 ! root 776: #if defined(USE_KQEMU)
! 777: #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
! 778: if (kqemu_is_ok(env) &&
! 779: (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
! 780: cpu_loop_exit();
! 781: }
! 782: #endif
1.1 root 783: }
784: } else {
785: env_to_regs();
786: }
787: } /* for(;;) */
788:
789:
790: #if defined(TARGET_I386)
791: #if defined(USE_CODE_COPY)
792: if (env->native_fp_regs) {
793: save_native_fp_state(env);
794: }
795: #endif
796: /* restore flags in standard format */
797: env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
798:
799: /* restore global registers */
800: #ifdef reg_EAX
801: EAX = saved_EAX;
802: #endif
803: #ifdef reg_ECX
804: ECX = saved_ECX;
805: #endif
806: #ifdef reg_EDX
807: EDX = saved_EDX;
808: #endif
809: #ifdef reg_EBX
810: EBX = saved_EBX;
811: #endif
812: #ifdef reg_ESP
813: ESP = saved_ESP;
814: #endif
815: #ifdef reg_EBP
816: EBP = saved_EBP;
817: #endif
818: #ifdef reg_ESI
819: ESI = saved_ESI;
820: #endif
821: #ifdef reg_EDI
822: EDI = saved_EDI;
823: #endif
824: #elif defined(TARGET_ARM)
825: /* XXX: Save/restore host fpu exception state?. */
826: #elif defined(TARGET_SPARC)
827: #if defined(reg_REGWPTR)
828: REGWPTR = saved_regwptr;
829: #endif
830: #elif defined(TARGET_PPC)
831: #elif defined(TARGET_MIPS)
1.1.1.3 ! root 832: #elif defined(TARGET_SH4)
! 833: /* XXXXX */
1.1 root 834: #else
835: #error unsupported target CPU
836: #endif
837: #ifdef __sparc__
838: asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
839: #endif
840: T0 = saved_T0;
841: T1 = saved_T1;
842: #if defined(reg_T2)
843: T2 = saved_T2;
844: #endif
845: env = saved_env;
1.1.1.2 root 846: /* fail safe : never use cpu_single_env outside cpu_exec() */
847: cpu_single_env = NULL;
1.1 root 848: return ret;
849: }
850:
851: /* must only be called from the generated code as an exception can be
852: generated */
853: void tb_invalidate_page_range(target_ulong start, target_ulong end)
854: {
855: /* XXX: cannot enable it yet because it yields to MMU exception
856: where NIP != read address on PowerPC */
857: #if 0
858: target_ulong phys_addr;
859: phys_addr = get_phys_addr_code(env, start);
860: tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
861: #endif
862: }
863:
864: #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
865:
866: void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
867: {
868: CPUX86State *saved_env;
869:
870: saved_env = env;
871: env = s;
872: if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
873: selector &= 0xffff;
874: cpu_x86_load_seg_cache(env, seg_reg, selector,
875: (selector << 4), 0xffff, 0);
876: } else {
877: load_seg(seg_reg, selector);
878: }
879: env = saved_env;
880: }
881:
882: void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
883: {
884: CPUX86State *saved_env;
885:
886: saved_env = env;
887: env = s;
888:
889: helper_fsave((target_ulong)ptr, data32);
890:
891: env = saved_env;
892: }
893:
894: void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
895: {
896: CPUX86State *saved_env;
897:
898: saved_env = env;
899: env = s;
900:
901: helper_frstor((target_ulong)ptr, data32);
902:
903: env = saved_env;
904: }
905:
906: #endif /* TARGET_I386 */
907:
908: #if !defined(CONFIG_SOFTMMU)
909:
910: #if defined(TARGET_I386)
911:
912: /* 'pc' is the host PC at which the exception was raised. 'address' is
913: the effective address of the memory exception. 'is_write' is 1 if a
914: write caused the exception and otherwise 0'. 'old_set' is the
915: signal set which should be restored */
916: static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
917: int is_write, sigset_t *old_set,
918: void *puc)
919: {
920: TranslationBlock *tb;
921: int ret;
922:
923: if (cpu_single_env)
924: env = cpu_single_env; /* XXX: find a correct solution for multithread */
925: #if defined(DEBUG_SIGNAL)
926: qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
927: pc, address, is_write, *(unsigned long *)old_set);
928: #endif
929: /* XXX: locking issue */
1.1.1.3 ! root 930: if (is_write && page_unprotect(h2g(address), pc, puc)) {
1.1 root 931: return 1;
932: }
933:
934: /* see if it is an MMU fault */
935: ret = cpu_x86_handle_mmu_fault(env, address, is_write,
936: ((env->hflags & HF_CPL_MASK) == 3), 0);
937: if (ret < 0)
938: return 0; /* not an MMU fault */
939: if (ret == 0)
940: return 1; /* the MMU fault was handled without causing real CPU fault */
941: /* now we have a real cpu fault */
942: tb = tb_find_pc(pc);
943: if (tb) {
944: /* the PC is inside the translated code. It means that we have
945: a virtual CPU fault */
946: cpu_restore_state(tb, env, pc, puc);
947: }
948: if (ret == 1) {
949: #if 0
950: printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
951: env->eip, env->cr[2], env->error_code);
952: #endif
953: /* we restore the process signal mask as the sigreturn should
954: do it (XXX: use sigsetjmp) */
955: sigprocmask(SIG_SETMASK, old_set, NULL);
1.1.1.2 root 956: raise_exception_err(env->exception_index, env->error_code);
1.1 root 957: } else {
958: /* activate soft MMU for this block */
959: env->hflags |= HF_SOFTMMU_MASK;
960: cpu_resume_from_signal(env, puc);
961: }
962: /* never comes here */
963: return 1;
964: }
965:
966: #elif defined(TARGET_ARM)
967: static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
968: int is_write, sigset_t *old_set,
969: void *puc)
970: {
971: TranslationBlock *tb;
972: int ret;
973:
974: if (cpu_single_env)
975: env = cpu_single_env; /* XXX: find a correct solution for multithread */
976: #if defined(DEBUG_SIGNAL)
977: printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
978: pc, address, is_write, *(unsigned long *)old_set);
979: #endif
980: /* XXX: locking issue */
1.1.1.3 ! root 981: if (is_write && page_unprotect(h2g(address), pc, puc)) {
1.1 root 982: return 1;
983: }
984: /* see if it is an MMU fault */
985: ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
986: if (ret < 0)
987: return 0; /* not an MMU fault */
988: if (ret == 0)
989: return 1; /* the MMU fault was handled without causing real CPU fault */
990: /* now we have a real cpu fault */
991: tb = tb_find_pc(pc);
992: if (tb) {
993: /* the PC is inside the translated code. It means that we have
994: a virtual CPU fault */
995: cpu_restore_state(tb, env, pc, puc);
996: }
997: /* we restore the process signal mask as the sigreturn should
998: do it (XXX: use sigsetjmp) */
999: sigprocmask(SIG_SETMASK, old_set, NULL);
1000: cpu_loop_exit();
1001: }
1002: #elif defined(TARGET_SPARC)
1003: static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1004: int is_write, sigset_t *old_set,
1005: void *puc)
1006: {
1007: TranslationBlock *tb;
1008: int ret;
1009:
1010: if (cpu_single_env)
1011: env = cpu_single_env; /* XXX: find a correct solution for multithread */
1012: #if defined(DEBUG_SIGNAL)
1013: printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1014: pc, address, is_write, *(unsigned long *)old_set);
1015: #endif
1016: /* XXX: locking issue */
1.1.1.3 ! root 1017: if (is_write && page_unprotect(h2g(address), pc, puc)) {
1.1 root 1018: return 1;
1019: }
1020: /* see if it is an MMU fault */
1021: ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1022: if (ret < 0)
1023: return 0; /* not an MMU fault */
1024: if (ret == 0)
1025: return 1; /* the MMU fault was handled without causing real CPU fault */
1026: /* now we have a real cpu fault */
1027: tb = tb_find_pc(pc);
1028: if (tb) {
1029: /* the PC is inside the translated code. It means that we have
1030: a virtual CPU fault */
1031: cpu_restore_state(tb, env, pc, puc);
1032: }
1033: /* we restore the process signal mask as the sigreturn should
1034: do it (XXX: use sigsetjmp) */
1035: sigprocmask(SIG_SETMASK, old_set, NULL);
1036: cpu_loop_exit();
1037: }
1038: #elif defined (TARGET_PPC)
1039: static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1040: int is_write, sigset_t *old_set,
1041: void *puc)
1042: {
1043: TranslationBlock *tb;
1044: int ret;
1045:
1046: if (cpu_single_env)
1047: env = cpu_single_env; /* XXX: find a correct solution for multithread */
1048: #if defined(DEBUG_SIGNAL)
1049: printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1050: pc, address, is_write, *(unsigned long *)old_set);
1051: #endif
1052: /* XXX: locking issue */
1.1.1.3 ! root 1053: if (is_write && page_unprotect(h2g(address), pc, puc)) {
1.1 root 1054: return 1;
1055: }
1056:
1057: /* see if it is an MMU fault */
1058: ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1059: if (ret < 0)
1060: return 0; /* not an MMU fault */
1061: if (ret == 0)
1062: return 1; /* the MMU fault was handled without causing real CPU fault */
1063:
1064: /* now we have a real cpu fault */
1065: tb = tb_find_pc(pc);
1066: if (tb) {
1067: /* the PC is inside the translated code. It means that we have
1068: a virtual CPU fault */
1069: cpu_restore_state(tb, env, pc, puc);
1070: }
1071: if (ret == 1) {
1072: #if 0
1073: printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1074: env->nip, env->error_code, tb);
1075: #endif
1076: /* we restore the process signal mask as the sigreturn should
1077: do it (XXX: use sigsetjmp) */
1078: sigprocmask(SIG_SETMASK, old_set, NULL);
1079: do_raise_exception_err(env->exception_index, env->error_code);
1080: } else {
1081: /* activate soft MMU for this block */
1082: cpu_resume_from_signal(env, puc);
1083: }
1084: /* never comes here */
1085: return 1;
1086: }
1087:
1088: #elif defined (TARGET_MIPS)
1089: static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1090: int is_write, sigset_t *old_set,
1091: void *puc)
1092: {
1093: TranslationBlock *tb;
1094: int ret;
1095:
1096: if (cpu_single_env)
1097: env = cpu_single_env; /* XXX: find a correct solution for multithread */
1098: #if defined(DEBUG_SIGNAL)
1099: printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1100: pc, address, is_write, *(unsigned long *)old_set);
1101: #endif
1102: /* XXX: locking issue */
1.1.1.3 ! root 1103: if (is_write && page_unprotect(h2g(address), pc, puc)) {
1.1 root 1104: return 1;
1105: }
1106:
1107: /* see if it is an MMU fault */
1.1.1.2 root 1108: ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1.1 root 1109: if (ret < 0)
1110: return 0; /* not an MMU fault */
1111: if (ret == 0)
1112: return 1; /* the MMU fault was handled without causing real CPU fault */
1113:
1114: /* now we have a real cpu fault */
1115: tb = tb_find_pc(pc);
1116: if (tb) {
1117: /* the PC is inside the translated code. It means that we have
1118: a virtual CPU fault */
1119: cpu_restore_state(tb, env, pc, puc);
1120: }
1121: if (ret == 1) {
1122: #if 0
1123: printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1124: env->nip, env->error_code, tb);
1125: #endif
1126: /* we restore the process signal mask as the sigreturn should
1127: do it (XXX: use sigsetjmp) */
1128: sigprocmask(SIG_SETMASK, old_set, NULL);
1129: do_raise_exception_err(env->exception_index, env->error_code);
1130: } else {
1131: /* activate soft MMU for this block */
1132: cpu_resume_from_signal(env, puc);
1133: }
1134: /* never comes here */
1135: return 1;
1136: }
1137:
1.1.1.3 ! root 1138: #elif defined (TARGET_SH4)
! 1139: static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
! 1140: int is_write, sigset_t *old_set,
! 1141: void *puc)
! 1142: {
! 1143: TranslationBlock *tb;
! 1144: int ret;
! 1145:
! 1146: if (cpu_single_env)
! 1147: env = cpu_single_env; /* XXX: find a correct solution for multithread */
! 1148: #if defined(DEBUG_SIGNAL)
! 1149: printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
! 1150: pc, address, is_write, *(unsigned long *)old_set);
! 1151: #endif
! 1152: /* XXX: locking issue */
! 1153: if (is_write && page_unprotect(h2g(address), pc, puc)) {
! 1154: return 1;
! 1155: }
! 1156:
! 1157: /* see if it is an MMU fault */
! 1158: ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
! 1159: if (ret < 0)
! 1160: return 0; /* not an MMU fault */
! 1161: if (ret == 0)
! 1162: return 1; /* the MMU fault was handled without causing real CPU fault */
! 1163:
! 1164: /* now we have a real cpu fault */
! 1165: tb = tb_find_pc(pc);
! 1166: if (tb) {
! 1167: /* the PC is inside the translated code. It means that we have
! 1168: a virtual CPU fault */
! 1169: cpu_restore_state(tb, env, pc, puc);
! 1170: }
! 1171: if (ret == 1) {
! 1172: #if 0
! 1173: printf("PF exception: NIP=0x%08x error=0x%x %p\n",
! 1174: env->nip, env->error_code, tb);
! 1175: #endif
! 1176: /* we restore the process signal mask as the sigreturn should
! 1177: do it (XXX: use sigsetjmp) */
! 1178: sigprocmask(SIG_SETMASK, old_set, NULL);
! 1179: // do_raise_exception_err(env->exception_index, env->error_code);
! 1180: } else {
! 1181: /* activate soft MMU for this block */
! 1182: cpu_resume_from_signal(env, puc);
! 1183: }
! 1184: /* never comes here */
! 1185: return 1;
! 1186: }
1.1 root 1187: #else
1188: #error unsupported target CPU
1189: #endif
1190:
1191: #if defined(__i386__)
1192:
1193: #if defined(USE_CODE_COPY)
1194: static void cpu_send_trap(unsigned long pc, int trap,
1195: struct ucontext *uc)
1196: {
1197: TranslationBlock *tb;
1198:
1199: if (cpu_single_env)
1200: env = cpu_single_env; /* XXX: find a correct solution for multithread */
1201: /* now we have a real cpu fault */
1202: tb = tb_find_pc(pc);
1203: if (tb) {
1204: /* the PC is inside the translated code. It means that we have
1205: a virtual CPU fault */
1206: cpu_restore_state(tb, env, pc, uc);
1207: }
1208: sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1209: raise_exception_err(trap, env->error_code);
1210: }
1211: #endif
1212:
1213: int cpu_signal_handler(int host_signum, struct siginfo *info,
1214: void *puc)
1215: {
1216: struct ucontext *uc = puc;
1217: unsigned long pc;
1218: int trapno;
1219:
1220: #ifndef REG_EIP
1221: /* for glibc 2.1 */
1222: #define REG_EIP EIP
1223: #define REG_ERR ERR
1224: #define REG_TRAPNO TRAPNO
1225: #endif
1226: pc = uc->uc_mcontext.gregs[REG_EIP];
1227: trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1228: #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1229: if (trapno == 0x00 || trapno == 0x05) {
1230: /* send division by zero or bound exception */
1231: cpu_send_trap(pc, trapno, uc);
1232: return 1;
1233: } else
1234: #endif
1235: return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1236: trapno == 0xe ?
1237: (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1238: &uc->uc_sigmask, puc);
1239: }
1240:
1241: #elif defined(__x86_64__)
1242:
1243: int cpu_signal_handler(int host_signum, struct siginfo *info,
1244: void *puc)
1245: {
1246: struct ucontext *uc = puc;
1247: unsigned long pc;
1248:
1249: pc = uc->uc_mcontext.gregs[REG_RIP];
1250: return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1251: uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1252: (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1253: &uc->uc_sigmask, puc);
1254: }
1255:
1256: #elif defined(__powerpc__)
1257:
1258: /***********************************************************************
1259: * signal context platform-specific definitions
1260: * From Wine
1261: */
1262: #ifdef linux
1263: /* All Registers access - only for local access */
1264: # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1265: /* Gpr Registers access */
1266: # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1267: # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1268: # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1269: # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1270: # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1271: # define LR_sig(context) REG_sig(link, context) /* Link register */
1272: # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1273: /* Float Registers access */
1274: # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1275: # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1276: /* Exception Registers access */
1277: # define DAR_sig(context) REG_sig(dar, context)
1278: # define DSISR_sig(context) REG_sig(dsisr, context)
1279: # define TRAP_sig(context) REG_sig(trap, context)
1280: #endif /* linux */
1281:
1282: #ifdef __APPLE__
1283: # include <sys/ucontext.h>
1284: typedef struct ucontext SIGCONTEXT;
1285: /* All Registers access - only for local access */
1286: # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1287: # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1288: # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1289: # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1290: /* Gpr Registers access */
1291: # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1292: # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1293: # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1294: # define CTR_sig(context) REG_sig(ctr, context)
1295: # define XER_sig(context) REG_sig(xer, context) /* Link register */
1296: # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1297: # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1298: /* Float Registers access */
1299: # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1300: # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1301: /* Exception Registers access */
1302: # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1303: # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1304: # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1305: #endif /* __APPLE__ */
1306:
1307: int cpu_signal_handler(int host_signum, struct siginfo *info,
1308: void *puc)
1309: {
1310: struct ucontext *uc = puc;
1311: unsigned long pc;
1312: int is_write;
1313:
1314: pc = IAR_sig(uc);
1315: is_write = 0;
1316: #if 0
1317: /* ppc 4xx case */
1318: if (DSISR_sig(uc) & 0x00800000)
1319: is_write = 1;
1320: #else
1321: if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1322: is_write = 1;
1323: #endif
1324: return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1325: is_write, &uc->uc_sigmask, puc);
1326: }
1327:
1328: #elif defined(__alpha__)
1329:
1330: int cpu_signal_handler(int host_signum, struct siginfo *info,
1331: void *puc)
1332: {
1333: struct ucontext *uc = puc;
1334: uint32_t *pc = uc->uc_mcontext.sc_pc;
1335: uint32_t insn = *pc;
1336: int is_write = 0;
1337:
1338: /* XXX: need kernel patch to get write flag faster */
1339: switch (insn >> 26) {
1340: case 0x0d: // stw
1341: case 0x0e: // stb
1342: case 0x0f: // stq_u
1343: case 0x24: // stf
1344: case 0x25: // stg
1345: case 0x26: // sts
1346: case 0x27: // stt
1347: case 0x2c: // stl
1348: case 0x2d: // stq
1349: case 0x2e: // stl_c
1350: case 0x2f: // stq_c
1351: is_write = 1;
1352: }
1353:
1354: return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1355: is_write, &uc->uc_sigmask, puc);
1356: }
1357: #elif defined(__sparc__)
1358:
1359: int cpu_signal_handler(int host_signum, struct siginfo *info,
1360: void *puc)
1361: {
1362: uint32_t *regs = (uint32_t *)(info + 1);
1363: void *sigmask = (regs + 20);
1364: unsigned long pc;
1365: int is_write;
1366: uint32_t insn;
1367:
1368: /* XXX: is there a standard glibc define ? */
1369: pc = regs[1];
1370: /* XXX: need kernel patch to get write flag faster */
1371: is_write = 0;
1372: insn = *(uint32_t *)pc;
1373: if ((insn >> 30) == 3) {
1374: switch((insn >> 19) & 0x3f) {
1375: case 0x05: // stb
1376: case 0x06: // sth
1377: case 0x04: // st
1378: case 0x07: // std
1379: case 0x24: // stf
1380: case 0x27: // stdf
1381: case 0x25: // stfsr
1382: is_write = 1;
1383: break;
1384: }
1385: }
1386: return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1387: is_write, sigmask, NULL);
1388: }
1389:
1390: #elif defined(__arm__)
1391:
1392: int cpu_signal_handler(int host_signum, struct siginfo *info,
1393: void *puc)
1394: {
1395: struct ucontext *uc = puc;
1396: unsigned long pc;
1397: int is_write;
1398:
1399: pc = uc->uc_mcontext.gregs[R15];
1400: /* XXX: compute is_write */
1401: is_write = 0;
1402: return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1403: is_write,
1404: &uc->uc_sigmask);
1405: }
1406:
1407: #elif defined(__mc68000)
1408:
1409: int cpu_signal_handler(int host_signum, struct siginfo *info,
1410: void *puc)
1411: {
1412: struct ucontext *uc = puc;
1413: unsigned long pc;
1414: int is_write;
1415:
1416: pc = uc->uc_mcontext.gregs[16];
1417: /* XXX: compute is_write */
1418: is_write = 0;
1419: return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1420: is_write,
1421: &uc->uc_sigmask, puc);
1422: }
1423:
1424: #elif defined(__ia64)
1425:
1426: #ifndef __ISR_VALID
1427: /* This ought to be in <bits/siginfo.h>... */
1428: # define __ISR_VALID 1
1429: #endif
1430:
1431: int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1432: {
1433: struct ucontext *uc = puc;
1434: unsigned long ip;
1435: int is_write = 0;
1436:
1437: ip = uc->uc_mcontext.sc_ip;
1438: switch (host_signum) {
1439: case SIGILL:
1440: case SIGFPE:
1441: case SIGSEGV:
1442: case SIGBUS:
1443: case SIGTRAP:
1.1.1.3 ! root 1444: if (info->si_code && (info->si_segvflags & __ISR_VALID))
1.1 root 1445: /* ISR.W (write-access) is bit 33: */
1446: is_write = (info->si_isr >> 33) & 1;
1447: break;
1448:
1449: default:
1450: break;
1451: }
1452: return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1453: is_write,
1454: &uc->uc_sigmask, puc);
1455: }
1456:
1457: #elif defined(__s390__)
1458:
1459: int cpu_signal_handler(int host_signum, struct siginfo *info,
1460: void *puc)
1461: {
1462: struct ucontext *uc = puc;
1463: unsigned long pc;
1464: int is_write;
1465:
1466: pc = uc->uc_mcontext.psw.addr;
1467: /* XXX: compute is_write */
1468: is_write = 0;
1469: return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1470: is_write,
1471: &uc->uc_sigmask, puc);
1472: }
1473:
1474: #else
1475:
1476: #error host CPU specific signal handler needed
1477:
1478: #endif
1479:
1480: #endif /* !defined(CONFIG_SOFTMMU) */
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